From 2ddd74fada9b2f272923fce9c3b1926a6e9f5c80 Mon Sep 17 00:00:00 2001 From: rppicomidi Date: Fri, 12 Aug 2022 11:06:36 -0700 Subject: Add MIDI host support to tinyusb --- hw/bsp/rp2040/family.cmake | 1 + 1 file changed, 1 insertion(+) (limited to 'hw') diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index 5dba9dc39..964855c05 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -93,6 +93,7 @@ if (NOT TARGET _rp2040_family_inclusion_marker) ${TOP}/src/class/cdc/cdc_host.c ${TOP}/src/class/hid/hid_host.c ${TOP}/src/class/msc/msc_host.c + ${TOP}/src/class/midi/midi_host.c ${TOP}/src/class/vendor/vendor_host.c ) -- cgit v1.3.1 From 0f288326cc80dba192d08b74116aa0be91a81a6f Mon Sep 17 00:00:00 2001 From: Brent Kowal Date: Fri, 28 Jun 2024 16:55:27 -0400 Subject: Initial Commit for MAX32 Support Initial commit for the port of TUSB to MAX32xxx parts, staring with MAX32690 - Added dcd_max32.c (based on dcd_musb.c) for interfacing with the peripheral - Added MAX32690 part family support - Added max32690evkit board support - Updated examples for unique EP number requirement - Updated get_deps.py to fetch the MSDK Known Issues / Additional Testing Required - msc_dual_lun only shown 1 volume on Windows - USBTMC does not have a valid Windowsdriver - DFU does not have a valid Windows driver - WebUSB is "Device not Recognized" - Need to test build scripts with IAR and Clang --- examples/device/cdc_msc/src/usb_descriptors.c | 10 + .../device/cdc_msc_freertos/src/usb_descriptors.c | 10 + examples/device/cdc_uac2/src/usb_descriptors.c | 10 + .../dynamic_configuration/src/usb_descriptors.c | 13 + examples/device/midi_test/src/usb_descriptors.c | 4 + examples/device/msc_dual_lun/src/usb_descriptors.c | 6 + .../device/net_lwip_webserver/src/tusb_config.h | 2 + .../net_lwip_webserver/src/usb_descriptors.c | 7 + examples/device/uac2_headset/src/usb_descriptors.c | 7 + .../device/webusb_serial/src/usb_descriptors.c | 7 + hw/bsp/board_mcu.h | 3 + hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h | 149 ++++ hw/bsp/max32690/boards/max32690evkit/board.cmake | 1 + hw/bsp/max32690/boards/max32690evkit/board.h | 56 ++ hw/bsp/max32690/boards/max32690evkit/board.mk | 1 + hw/bsp/max32690/family.c | 159 ++++ hw/bsp/max32690/family.cmake | 152 ++++ hw/bsp/max32690/family.mk | 106 +++ hw/bsp/max32690/max32690.ld | 162 ++++ src/common/tusb_mcu.h | 8 + src/portable/analog/max32/dcd_max32.c | 841 +++++++++++++++++++++ src/tusb_option.h | 3 + tools/get_deps.py | 3 + 23 files changed, 1720 insertions(+) create mode 100644 hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/max32690/boards/max32690evkit/board.cmake create mode 100644 hw/bsp/max32690/boards/max32690evkit/board.h create mode 100644 hw/bsp/max32690/boards/max32690evkit/board.mk create mode 100644 hw/bsp/max32690/family.c create mode 100644 hw/bsp/max32690/family.cmake create mode 100644 hw/bsp/max32690/family.mk create mode 100644 hw/bsp/max32690/max32690.ld create mode 100644 src/portable/analog/max32/dcd_max32.c (limited to 'hw') diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c index 2afa24903..1ca614f4e 100644 --- a/examples/device/cdc_msc/src/usb_descriptors.c +++ b/examples/device/cdc_msc/src/usb_descriptors.c @@ -125,6 +125,16 @@ enum { #define EPNUM_MSC_OUT 0x04 #define EPNUM_MSC_IN 0x85 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // MAX32 doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_CDC_NOTIF 0x81 + #define EPNUM_CDC_OUT 0x02 + #define EPNUM_CDC_IN 0x83 + + #define EPNUM_MSC_OUT 0x04 + #define EPNUM_MSC_IN 0x85 + #else #define EPNUM_CDC_NOTIF 0x81 #define EPNUM_CDC_OUT 0x02 diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_freertos/src/usb_descriptors.c index 9c29701c7..f563e80d3 100644 --- a/examples/device/cdc_msc_freertos/src/usb_descriptors.c +++ b/examples/device/cdc_msc_freertos/src/usb_descriptors.c @@ -106,6 +106,16 @@ enum #define EPNUM_MSC_OUT 0x04 #define EPNUM_MSC_IN 0x85 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // MAX32 doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_CDC_NOTIF 0x81 + #define EPNUM_CDC_OUT 0x02 + #define EPNUM_CDC_IN 0x83 + + #define EPNUM_MSC_OUT 0x04 + #define EPNUM_MSC_IN 0x85 + #else #define EPNUM_CDC_NOTIF 0x81 #define EPNUM_CDC_OUT 0x02 diff --git a/examples/device/cdc_uac2/src/usb_descriptors.c b/examples/device/cdc_uac2/src/usb_descriptors.c index 72a695622..43e8cf3d7 100644 --- a/examples/device/cdc_uac2/src/usb_descriptors.c +++ b/examples/device/cdc_uac2/src/usb_descriptors.c @@ -117,6 +117,16 @@ uint8_t const * tud_descriptor_device_cb(void) #define EPNUM_CDC_OUT 0x04 #define EPNUM_CDC_IN 0x85 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // MAX32 doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_AUDIO_IN 0x01 + #define EPNUM_AUDIO_OUT 0x02 + + #define EPNUM_CDC_NOTIF 0x83 + #define EPNUM_CDC_OUT 0x04 + #define EPNUM_CDC_IN 0x85 + #else #define EPNUM_AUDIO_IN 0x01 #define EPNUM_AUDIO_OUT 0x01 diff --git a/examples/device/dynamic_configuration/src/usb_descriptors.c b/examples/device/dynamic_configuration/src/usb_descriptors.c index 7f35b4b22..eebdd4f69 100644 --- a/examples/device/dynamic_configuration/src/usb_descriptors.c +++ b/examples/device/dynamic_configuration/src/usb_descriptors.c @@ -158,6 +158,19 @@ enum #define EPNUM_1_MSC_OUT 0x01 #define EPNUM_1_MSC_IN 0x82 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // FT9XX doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_0_CDC_NOTIF 0x81 + #define EPNUM_0_CDC_OUT 0x02 + #define EPNUM_0_CDC_IN 0x83 + + #define EPNUM_0_MIDI_OUT 0x04 + #define EPNUM_0_MIDI_IN 0x85 + + #define EPNUM_1_MSC_OUT 0x01 + #define EPNUM_1_MSC_IN 0x82 + #else #define EPNUM_0_CDC_NOTIF 0x81 #define EPNUM_0_CDC_OUT 0x02 diff --git a/examples/device/midi_test/src/usb_descriptors.c b/examples/device/midi_test/src/usb_descriptors.c index 9781d3d6f..797b50ab2 100644 --- a/examples/device/midi_test/src/usb_descriptors.c +++ b/examples/device/midi_test/src/usb_descriptors.c @@ -90,6 +90,10 @@ enum // On Bridgetek FT9xx endpoint numbers must be unique... #define EPNUM_MIDI_OUT 0x02 #define EPNUM_MIDI_IN 0x03 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // On MAX32 endpoint numbers must be unique... + #define EPNUM_MIDI_OUT 0x02 + #define EPNUM_MIDI_IN 0x03 #else #define EPNUM_MIDI_OUT 0x01 #define EPNUM_MIDI_IN 0x01 diff --git a/examples/device/msc_dual_lun/src/usb_descriptors.c b/examples/device/msc_dual_lun/src/usb_descriptors.c index c0610945f..e32466228 100644 --- a/examples/device/msc_dual_lun/src/usb_descriptors.c +++ b/examples/device/msc_dual_lun/src/usb_descriptors.c @@ -97,6 +97,12 @@ enum #define EPNUM_MSC_OUT 0x01 #define EPNUM_MSC_IN 0x82 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // MAX32 doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_MSC_OUT 0x01 + #define EPNUM_MSC_IN 0x82 + #else #define EPNUM_MSC_OUT 0x01 #define EPNUM_MSC_IN 0x81 diff --git a/examples/device/net_lwip_webserver/src/tusb_config.h b/examples/device/net_lwip_webserver/src/tusb_config.h index d3e094517..2f641f33e 100644 --- a/examples/device/net_lwip_webserver/src/tusb_config.h +++ b/examples/device/net_lwip_webserver/src/tusb_config.h @@ -91,6 +91,8 @@ extern "C" { #define USE_ECM 1 #elif TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F1) #define USE_ECM 1 +#elif TU_CHECK_MCU(OPT_MCU_MAX32690) + #define USE_ECM 1 #else #define USE_ECM 0 #define INCLUDE_IPERF diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c index da628c8be..ba30b869e 100644 --- a/examples/device/net_lwip_webserver/src/usb_descriptors.c +++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c @@ -120,6 +120,13 @@ uint8_t const * tud_descriptor_device_cb(void) #define EPNUM_NET_OUT 0x02 #define EPNUM_NET_IN 0x83 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // MAX32 doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_NET_NOTIF 0x81 + #define EPNUM_NET_OUT 0x02 + #define EPNUM_NET_IN 0x83 + #else #define EPNUM_NET_NOTIF 0x81 #define EPNUM_NET_OUT 0x02 diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c index ff4dc2acc..bfc8a4ab5 100644 --- a/examples/device/uac2_headset/src/usb_descriptors.c +++ b/examples/device/uac2_headset/src/usb_descriptors.c @@ -104,6 +104,13 @@ uint8_t const * tud_descriptor_device_cb(void) #define EPNUM_AUDIO_OUT 0x02 #define EPNUM_AUDIO_INT 0x03 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // MAX32 doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_AUDIO_IN 0x01 + #define EPNUM_AUDIO_OUT 0x02 + #define EPNUM_AUDIO_INT 0x03 + #else #define EPNUM_AUDIO_IN 0x01 #define EPNUM_AUDIO_OUT 0x01 diff --git a/examples/device/webusb_serial/src/usb_descriptors.c b/examples/device/webusb_serial/src/usb_descriptors.c index b01fae8e3..bcfbe590e 100644 --- a/examples/device/webusb_serial/src/usb_descriptors.c +++ b/examples/device/webusb_serial/src/usb_descriptors.c @@ -105,6 +105,13 @@ enum #define EPNUM_CDC_OUT 3 #define EPNUM_VENDOR_IN 4 #define EPNUM_VENDOR_OUT 5 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // MAX32 doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_CDC_IN 2 + #define EPNUM_CDC_OUT 3 + #define EPNUM_VENDOR_IN 4 + #define EPNUM_VENDOR_OUT 5 #else #define EPNUM_CDC_IN 2 #define EPNUM_CDC_OUT 2 diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index 013eb1c83..436164c35 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -170,6 +170,9 @@ #elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837) // no header needed +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + #include "max32690.h" + #else #error "Missing MCU header" #endif diff --git a/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..e5a76af85 --- /dev/null +++ b/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,149 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "mxc_device.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS __NVIC_PRIO_BITS + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN; + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_USB); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) { + #if LED_STATE_ON + state = !state; + #endif + if(state) { + MXC_GPIO_OutClr(LED_PORT, LED_PIN); + } else { + MXC_GPIO_OutSet(LED_PORT, LED_PIN); + } +} + +uint32_t board_button_read(void) { + uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0; + return BUTTON_STATE_ACTIVE == state; +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN]; //USN Buffer + /* All other 2nd parameter is optional checkum buffer */ + MXC_SYS_GetUSN(hw_id, NULL); + + size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); + memcpy(id, hw_id, act_len); + return act_len; +} + +int board_uart_read(uint8_t *buf, int len) { + int uart_val; + int act_len = 0; + + while( act_len < len ) { + if((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { + break; + } else { + *buf++ = (uint8_t)uart_val; + act_len++; + } + } + return act_len; +} + +int board_uart_write(void const *buf, int len) { + int act_len = 0; + const uint8_t* ch_ptr = (const uint8_t*)buf; + while(act_len < len){ + MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++); + act_len++; + } + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) { + system_ticks++; +} + +uint32_t board_millis(void) { + return system_ticks; +} +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake new file mode 100644 index 000000000..e1d797f58 --- /dev/null +++ b/hw/bsp/max32690/family.cmake @@ -0,0 +1,152 @@ +include_guard() + +set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers) +set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS) +set(CMSIS_5 ${TOP}/lib/CMSIS_5) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# Get the linker file from current location (family) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32690.ld) +set(LD_FILE_Clang ${LD_FILE_GNU}) + +# toolchain set up +set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) +set(JLINK_DEVICE max32690) + +set(FAMILY_MCUS MAX32690 CACHE INTERNAL "") + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + TARGET=MAX32690 + TARGET_REV=0x4131 + MXC_ASSERT_ENABLE + MAX32690 + FLASH_ORIGIN=0x10000000 + FLASH_SIZE=0x340000 + SRAM_ORIGIN=0x20000000 + SRAM_SIZE=0x100000 + IAR_PRAGMAS=0 + CFG_TUSB_MCU=OPT_MCU_MAX32690 + BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + ) +endfunction() + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/GCC/startup_max32690.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/IAR/startup_max32690.s) + + set(PERIPH_SRC ${MAX32_PERIPH}/Source) + add_library(${BOARD_TARGET} STATIC + ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/heap.c + ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/system_max32690.c + ${PERIPH_SRC}/SYS/mxc_assert.c + ${PERIPH_SRC}/SYS/mxc_delay.c + ${PERIPH_SRC}/SYS/mxc_lock.c + ${PERIPH_SRC}/SYS/nvic_table.c + ${PERIPH_SRC}/SYS/pins_me18.c + ${PERIPH_SRC}/SYS/sys_me18.c + ${PERIPH_SRC}/CTB/ctb_me18.c + ${PERIPH_SRC}/CTB/ctb_reva.c + ${PERIPH_SRC}/CTB/ctb_common.c + ${PERIPH_SRC}/FLC/flc_common.c + ${PERIPH_SRC}/FLC/flc_me18.c + ${PERIPH_SRC}/FLC/flc_reva.c + ${PERIPH_SRC}/GPIO/gpio_common.c + ${PERIPH_SRC}/GPIO/gpio_me18.c + ${PERIPH_SRC}/GPIO/gpio_reva.c + ${PERIPH_SRC}/ICC/icc_me18.c + ${PERIPH_SRC}/ICC/icc_reva.c + ${PERIPH_SRC}/UART/uart_common.c + ${PERIPH_SRC}/UART/uart_me18.c + ${PERIPH_SRC}/UART/uart_revb.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMSIS_5}/CMSIS/Core/Include + ${MAX32_CMSIS}/Include + ${MAX32_CMSIS}/Device/Maxim/MAX32690/Include + ${MAX32_PERIPH}/Include/MAX32690 + ${PERIPH_SRC}/SYS + ${PERIPH_SRC}/GPIO + ${PERIPH_SRC}/CTB + ${PERIPH_SRC}/ICC + ${PERIPH_SRC}/FLC + ${PERIPH_SRC}/UART + ) + + target_compile_options(${TARGET} PRIVATE + -Wno-error=strict-prototypes + ) + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_MAX32690 ${RTOS}) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/analog/max32/dcd_max32.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_compile_options(${TARGET}-tinyusb PRIVATE + -Wno-error=strict-prototypes + ) + + # Link dependencies + target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + + # Flashing + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/max32690/family.mk b/hw/bsp/max32690/family.mk new file mode 100644 index 000000000..08d5e8671 --- /dev/null +++ b/hw/bsp/max32690/family.mk @@ -0,0 +1,106 @@ +DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32 + +# Important locations in the hw support for MCU +MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS +MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers + +# Add any board specific make rules +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 +PORT ?= 0 + +# GCC +SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/GCC/startup_max32690.s +LD_FILE = $(FAMILY_PATH)/max32690.ld + +# IAR +SRC_S_IAR += $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/IAR/startup_max32690.s + +# -------------- +# Compiler Flags +# -------------- +# Flags for the MAX32690 SDK +CFLAGS += -DTARGET=MAX32690 \ + -DTARGET_REV=0x4131 \ + -DMXC_ASSERT_ENABLE \ + -DMAX32690 \ + -DFLASH_ORIGIN=0x10000000 \ + -DFLASH_SIZE=0x340000 \ + -DSRAM_ORIGIN=0x20000000 \ + -DSRAM_SIZE=0x100000 \ + -DIAR_PRAGMAS=0 + +# Flags for TUSB features +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_MAX32690 \ + -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + +# mcu driver cause following warnings +CFLAGS += -Wno-error=unused-parameter \ + -Wno-error=strict-prototypes \ + -Wno-error=old-style-declaration \ + -Wno-error=sign-compare \ + -Wno-error=cast-qual \ + -Wno-lto-type-mismatch + +LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs + +# For flash-jlink target +JLINK_DEVICE = max32690 + +# flash target using Jlik +flash: flash-jlink + +# Optional flash option when running within an installed MSDK to use OpenOCD +# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. +# If the MSDK is installed, flash-msdk can be run to utilize the the modified +# openocd with the algorithms +MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) +flash-msdk: + $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ + -f interface/cmsis-dap.cfg -f target/max32690.cfg \ + -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" + +# ----------------- +# Sources & Include +# ----------------- +PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source +SRC_C += \ + src/portable/analog/max32/dcd_max32.c \ + $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/heap.c \ + $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/system_max32690.c \ + $(PERIPH_SRC)/SYS/mxc_assert.c \ + $(PERIPH_SRC)/SYS/mxc_delay.c \ + $(PERIPH_SRC)/SYS/mxc_lock.c \ + $(PERIPH_SRC)/SYS/nvic_table.c \ + $(PERIPH_SRC)/SYS/pins_me18.c \ + $(PERIPH_SRC)/SYS/sys_me18.c \ + $(PERIPH_SRC)/CTB/ctb_me18.c \ + $(PERIPH_SRC)/CTB/ctb_reva.c \ + $(PERIPH_SRC)/CTB/ctb_common.c \ + $(PERIPH_SRC)/FLC/flc_common.c \ + $(PERIPH_SRC)/FLC/flc_me18.c \ + $(PERIPH_SRC)/FLC/flc_reva.c \ + $(PERIPH_SRC)/GPIO/gpio_common.c \ + $(PERIPH_SRC)/GPIO/gpio_me18.c \ + $(PERIPH_SRC)/GPIO/gpio_reva.c \ + $(PERIPH_SRC)/ICC/icc_me18.c \ + $(PERIPH_SRC)/ICC/icc_reva.c \ + $(PERIPH_SRC)/UART/uart_common.c \ + $(PERIPH_SRC)/UART/uart_me18.c \ + $(PERIPH_SRC)/UART/uart_revb.c \ + + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(MAX32_CMSIS)/Include \ + $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32690/Include \ + $(TOP)/$(MAX32_PERIPH)/Include/MAX32690 \ + $(PERIPH_SRC)/SYS \ + $(PERIPH_SRC)/GPIO \ + $(PERIPH_SRC)/CTB \ + $(PERIPH_SRC)/ICC \ + $(PERIPH_SRC)/FLC \ + $(PERIPH_SRC)/UART diff --git a/hw/bsp/max32690/max32690.ld b/hw/bsp/max32690/max32690.ld new file mode 100644 index 000000000..35886fe3a --- /dev/null +++ b/hw/bsp/max32690/max32690.ld @@ -0,0 +1,162 @@ +MEMORY { + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00020000 /* 128kB ROM */ + FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00340000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 + + /* + * Note that CS0/CS1 address mappings may be reversed using MXC_HPC->mbr0 and ->mbr1 + * The following mappings are selected for simplicity + */ + HPB_CS0 (rwx) : ORIGIN = 0x60000000, LENGTH = 0x10000000 /* External Hyperbus/Xccelabus chip select 0 */ + HPB_CS1 (rwx) : ORIGIN = 0x70000000, LENGTH = 0x10000000 /* External Hyperbus/Xccelabus chip select 1 */ +} + +SECTIONS { + .rom : + { + KEEP(*(.rom_vector)) + *(.rom_handlers*) + } > ROM + + .text : + { + _text = .; + KEEP(*(.isr_vector)) + EXCLUDE_FILE (*riscv.o) *(.text*) /* program code, exclude RISCV code */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + /* These sections allow code to be compiled/linked for HPB addresses, but reside in + * flash until copied by code to the external HPB flash device + */ + .hpb_cs0_section : + { + __hpb_cs0_start = ABSOLUTE(.); + KEEP(*(.hpb_cs0_section*)) + } > HPB_CS0 AT>FLASH + + __load_start_hpb_cs0 = LOADADDR(.hpb_cs0_section); + __load_length_hpb_cs0 = SIZEOF(.hpb_cs0_section); + + .hpb_cs1_section : + { + __hpb_cs1_start = ABSOLUTE(.); + KEEP(*(.hpb_cs1_section*)) + } > HPB_CS1 AT>FLASH + + __load_start_hpb_cs1 = LOADADDR(.hpb_cs1_section); + __load_length_hpb_cs1 = SIZEOF(.hpb_cs1_section); + + /* Binary import */ + .bin_storage : + { + FILL(0xFF) + _bin_start_ = .; + KEEP(*(.bin_storage_img)) + _bin_end_ = .; + . = ALIGN(4); + } > FLASH + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + *(vtable) + *(.data*) /*read-write initialized data: initialized global variable*/ + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + /* Run the flash programming functions from SRAM */ + *(.flashprog) + + _edata = ALIGN(., 4); + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") +} diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index c66996c4f..a68e160bd 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -452,6 +452,14 @@ #define TUP_RHPORT_HIGHSPEED CFG_TUD_WCH_USBIP_USBHS #define TUP_DCD_ENDPOINT_MAX (CFG_TUD_WCH_USBIP_USBHS ? 16 : 8) +//--------------------------------------------------------------------+ +// Analog Devices +//--------------------------------------------------------------------+ +#elif TU_CHECK_MCU(OPT_MCU_MAX32690) + #define TUP_DCD_ENDPOINT_MAX 12 + #define TUP_RHPORT_HIGHSPEED 1 + + #endif //--------------------------------------------------------------------+ diff --git a/src/portable/analog/max32/dcd_max32.c b/src/portable/analog/max32/dcd_max32.c new file mode 100644 index 000000000..150d476fa --- /dev/null +++ b/src/portable/analog/max32/dcd_max32.c @@ -0,0 +1,841 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Koji KITAYAMA + * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUD_ENABLED && TU_CHECK_MCU(OPT_MCU_MAX32690) + +#if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) +/* GCC warns that an address may be unaligned, even though + * the target CPU has the capability for unaligned memory access. */ +_Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); +#endif + +#include "device/dcd.h" + +#include "mxc_delay.h" +#include "mxc_device.h" +#include "mxc_sys.h" +#include "nvic_table.h" +#include "usbhs_regs.h" + +#define USBHS_M31_CLOCK_RECOVERY + +/*------------------------------------------------------------------ + * MACRO TYPEDEF CONSTANT ENUM DECLARATION + *------------------------------------------------------------------*/ +#define REQUEST_TYPE_INVALID (0xFFu) + + +typedef union { + uint8_t u8; + uint16_t u16; + uint32_t u32; +} hw_fifo_t; + +typedef struct TU_ATTR_PACKED +{ + void *buf; /* the start address of a transfer data buffer */ + uint16_t length; /* the number of bytes in the buffer */ + uint16_t remaining; /* the number of bytes remaining in the buffer */ +} pipe_state_t; + +typedef struct +{ + tusb_control_request_t setup_packet; + uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */ + int8_t status_out; + pipe_state_t pipe0; + pipe_state_t pipe[2][TUP_DCD_ENDPOINT_MAX - 1]; /* pipe[direction][endpoint number - 1] */ + uint16_t pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */ +} dcd_data_t; + +/*------------------------------------------------------------------ + * INTERNAL OBJECT & FUNCTION DECLARATION + *------------------------------------------------------------------*/ +static dcd_data_t _dcd; + + +static volatile void* edpt_get_fifo_ptr(unsigned epnum) +{ + volatile uint32_t *ptr; + + ptr = &MXC_USBHS->fifo0; + ptr += epnum; /* Pointer math: multiplies ep by sizeof(uint32_t) */ + + return (volatile void *)ptr; +} + +static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) +{ + volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; + uintptr_t addr = (uintptr_t)buf; + while (len >= 4) { + reg->u32 = *(uint32_t const *)addr; + addr += 4; + len -= 4; + } + if (len >= 2) { + reg->u16 = *(uint16_t const *)addr; + addr += 2; + len -= 2; + } + if (len) { + reg->u8 = *(uint8_t const *)addr; + } +} + +static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) +{ + volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; + uintptr_t addr = (uintptr_t)buf; + while (len >= 4) { + *(uint32_t *)addr = reg->u32; + addr += 4; + len -= 4; + } + if (len >= 2) { + *(uint16_t *)addr = reg->u16; + addr += 2; + len -= 2; + } + if (len) { + *(uint8_t *)addr = reg->u8; + } +} + +static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) +{ + static const struct { + void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info); + void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n); + void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len); + } ops[] = { + /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet}, + /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, + }; + tu_fifo_buffer_info_t info; + ops[dir].tu_fifo_get_info(f, &info); + unsigned total_len = len; + len = TU_MIN(total_len, info.len_lin); + ops[dir].pipe_read_write(info.ptr_lin, fifo, len); + unsigned rem = total_len - len; + if (rem) { + len = TU_MIN(rem, info.len_wrap); + ops[dir].pipe_read_write(info.ptr_wrap, fifo, len); + rem -= len; + } + ops[dir].tu_fifo_advance(f, total_len - rem); +} + +static void process_setup_packet(uint8_t rhport) +{ + uint32_t *p = (void*)&_dcd.setup_packet; + p[0] = MXC_USBHS->fifo0; + p[1] = MXC_USBHS->fifo0; + + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; + _dcd.pipe0.remaining = 0; + dcd_event_setup_received(rhport, (const uint8_t*)(uintptr_t)&_dcd.setup_packet, true); + + const unsigned len = _dcd.setup_packet.wLength; + _dcd.remaining_ctrl = len; + const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType); + /* Clear RX FIFO and reverse the transaction direction */ + if (len && dir_in) { + MXC_USBHS->index = 0; + MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY; + } +} + +static bool handle_xfer_in(uint_fast8_t ep_addr) +{ + unsigned epnum = tu_edpt_number(ep_addr); + unsigned epnum_minus1 = epnum - 1; + pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; + const unsigned rem = pipe->remaining; + + //This function should not be for ep0 + TU_ASSERT(epnum); + + if (!rem) { + pipe->buf = NULL; + return true; + } + + MXC_USBHS->index = epnum; + const unsigned mps = MXC_USBHS->inmaxp; + const unsigned len = TU_MIN(mps, rem); + void *buf = pipe->buf; + volatile void* fifo_ptr = edpt_get_fifo_ptr(epnum); + // TU_LOG1(" %p mps %d len %d rem %d\r\n", buf, mps, len, rem); + if (len) { + if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) { + pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_IN); + } else { + pipe_write_packet(buf,fifo_ptr, len); + pipe->buf = buf + len; + } + pipe->remaining = rem - len; + } + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_INPKTRDY; //TODO: Verify a | isnt needed + + return false; +} + +static bool handle_xfer_out(uint_fast8_t ep_addr) +{ + unsigned epnum = tu_edpt_number(ep_addr); + unsigned epnum_minus1 = epnum - 1; + pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; + + //This function should not be for ep0 + TU_ASSERT(epnum); + + MXC_USBHS->index = epnum; + + TU_ASSERT(MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY); + + const unsigned mps = MXC_USBHS->outmaxp; + const unsigned rem = pipe->remaining; + const unsigned vld = MXC_USBHS->outcount; + const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); + void *buf = pipe->buf; + volatile void* fifo_ptr = edpt_get_fifo_ptr(epnum); + if (len) { + if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) { + pipe_read_write_packet_ff(buf,fifo_ptr, len, TUSB_DIR_OUT); + } else { + pipe_read_packet(buf, fifo_ptr, len); + pipe->buf = buf + len; + } + pipe->remaining = rem - len; + } + if ((len < mps) || (rem == len)) { + pipe->buf = NULL; + return NULL != buf; + } + MXC_USBHS->outcsrl = 0; /* Clear RXRDY bit */ //TODO: Verify just setting to 0 is ok + return false; +} + +static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) +{ + (void)rhport; + + unsigned epnum = tu_edpt_number(ep_addr); + unsigned epnum_minus1 = epnum - 1; + unsigned dir_in = tu_edpt_dir(ep_addr); + + pipe_state_t *pipe = &_dcd.pipe[dir_in][epnum_minus1]; + pipe->buf = buffer; + pipe->length = total_bytes; + pipe->remaining = total_bytes; + + if (dir_in) { + handle_xfer_in(ep_addr); + } else { + MXC_USBHS->index = epnum; + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY){ + MXC_USBHS->outcsrl = 0; //TODO: Verify just setting to 0 is ok + } + } + return true; +} + +static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) +{ + (void)rhport; + TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */ + + const unsigned req = _dcd.setup_packet.bmRequestType; + TU_ASSERT(req != REQUEST_TYPE_INVALID || total_bytes == 0); + + if (req == REQUEST_TYPE_INVALID || _dcd.status_out) { + /* STATUS OUT stage. + * MUSB controller automatically handles STATUS OUT packets without + * software helps. We do not have to do anything. And STATUS stage + * may have already finished and received the next setup packet + * without calling this function, so we have no choice but to + * invoke the callback function of status packet here. */ + _dcd.status_out = 0; + if (req == REQUEST_TYPE_INVALID) { + dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false); + } else { + /* The next setup packet has already been received, it aborts + * invoking callback function to avoid confusing TUSB stack. */ + TU_LOG1("Drop CONTROL_STAGE_ACK\r\n"); + } + return true; + } + const unsigned dir_in = tu_edpt_dir(ep_addr); + MXC_USBHS->index = 0; + if (tu_edpt_dir(req) == dir_in) { /* DATA stage */ + TU_ASSERT(total_bytes <= _dcd.remaining_ctrl); + const unsigned rem = _dcd.remaining_ctrl; + const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes); + volatile void* fifo_ptr = edpt_get_fifo_ptr(0); + if (dir_in) { + pipe_write_packet(buffer, fifo_ptr, len); + + _dcd.pipe0.buf = buffer + len; + _dcd.pipe0.length = len; + _dcd.pipe0.remaining = 0; + + _dcd.remaining_ctrl = rem - len; + if ((len < 64) || (rem == len)) { + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */ + _dcd.status_out = 1; + /* Flush TX FIFO and reverse the transaction direction. */ + MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_INPKTRDY | MXC_F_USBHS_CSR0_DATA_END; + } else { + MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_INPKTRDY; /* Flush TX FIFO to return ACK. */ + } + } else { + _dcd.pipe0.buf = buffer; + _dcd.pipe0.length = len; + _dcd.pipe0.remaining = len; + MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY; /* Clear RX FIFO to return ACK. */ + } + } else if (dir_in) { + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; + _dcd.pipe0.remaining = 0; + /* Clear RX FIFO and reverse the transaction direction */ + MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY | MXC_F_USBHS_CSR0_DATA_END; + } + return true; +} + +static void process_ep0(uint8_t rhport) +{ + MXC_USBHS->index = 0; + uint_fast8_t csrl = MXC_USBHS->csr0; + + if (csrl & MXC_F_USBHS_CSR0_SENT_STALL) { + /* Returned STALL packet to HOST. */ + MXC_USBHS->csr0 = 0; /* Clear STALL */ + return; + } + + unsigned req = _dcd.setup_packet.bmRequestType; + if (csrl & MXC_F_USBHS_CSR0_SETUP_END) { + TU_LOG1(" ABORT by the next packets\r\n"); + MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_SETUP_END; + if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) { + /* DATA stage was aborted by receiving STATUS or SETUP packet. */ + _dcd.pipe0.buf = NULL; + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; + dcd_event_xfer_complete(rhport, + req & TUSB_DIR_IN_MASK, + _dcd.pipe0.length - _dcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + } + req = REQUEST_TYPE_INVALID; + if (!(csrl & MXC_F_USBHS_CSR0_OUTPKTRDY)) return; /* Received SETUP packet */ + } + + if (csrl & MXC_F_USBHS_CSR0_OUTPKTRDY) { + /* Received SETUP or DATA OUT packet */ + if (req == REQUEST_TYPE_INVALID) { + /* SETUP */ + TU_ASSERT(sizeof(tusb_control_request_t) == MXC_USBHS->count0,); + process_setup_packet(rhport); + return; + } + if (_dcd.pipe0.buf) { + /* DATA OUT */ + const unsigned vld = MXC_USBHS->count0; + const unsigned rem = _dcd.pipe0.remaining; + const unsigned len = TU_MIN(TU_MIN(rem, 64), vld); + volatile void* fifo_ptr = edpt_get_fifo_ptr(0); + pipe_read_packet(_dcd.pipe0.buf, fifo_ptr, len); + + _dcd.pipe0.remaining = rem - len; + _dcd.remaining_ctrl -= len; + + _dcd.pipe0.buf = NULL; + dcd_event_xfer_complete(rhport, + tu_edpt_addr(0, TUSB_DIR_OUT), + _dcd.pipe0.length - _dcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + } + return; + } + + /* When CSRL0 is zero, it means that completion of sending a any length packet + * or receiving a zero length packet. */ + if (req != REQUEST_TYPE_INVALID && !tu_edpt_dir(req)) { + /* STATUS IN */ + if (*(const uint16_t*)(uintptr_t)&_dcd.setup_packet == 0x0500) { + /* The address must be changed on completion of the control transfer. */ + MXC_USBHS->faddr = (uint8_t)_dcd.setup_packet.wValue; + } + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; + dcd_event_xfer_complete(rhport, + tu_edpt_addr(0, TUSB_DIR_IN), + _dcd.pipe0.length - _dcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + return; + } + if (_dcd.pipe0.buf) { + /* DATA IN */ + _dcd.pipe0.buf = NULL; + dcd_event_xfer_complete(rhport, + tu_edpt_addr(0, TUSB_DIR_IN), + _dcd.pipe0.length - _dcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + } +} + +static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) +{ + bool completed; + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned epnum = tu_edpt_number(ep_addr); + + MXC_USBHS->index = epnum; + + if (dir_in) { + if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_SENTSTALL) { + MXC_USBHS->incsrl &= ~(MXC_F_USBHS_INCSRL_SENTSTALL | MXC_F_USBHS_INCSRL_UNDERRUN); + return; + } + completed = handle_xfer_in(ep_addr); + } else { + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_SENTSTALL) { + MXC_USBHS->outcsrl &= ~(MXC_F_USBHS_OUTCSRL_SENTSTALL | MXC_F_USBHS_OUTCSRL_OVERRUN); + return; + } + completed = handle_xfer_out(ep_addr); + } + + if (completed) { + pipe_state_t *pipe = &_dcd.pipe[dir_in][tu_edpt_number(ep_addr) - 1]; + dcd_event_xfer_complete(rhport, ep_addr, + pipe->length - pipe->remaining, + XFER_RESULT_SUCCESS, true); + } +} + +static void process_bus_reset(uint8_t rhport) +{ + (void)rhport; + TU_LOG0("------Bus Reset\r\n"); + /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), + * a control transfer state is SETUP or STATUS stage. */ + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; + _dcd.status_out = 0; + /* When pipe0.buf has not NULL, DATA stage works in progress. */ + _dcd.pipe0.buf = NULL; + + MXC_USBHS->intrinen = 1; /* Enable only EP0 */ + MXC_USBHS->introuten = 0; + + + /* Clear FIFO settings */ + for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { + MXC_USBHS->index = i; + if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { + /* Per musbhsfc_pg, only flush FIFO if IN packet loaded */ + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_FLUSHFIFO; + } + + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { + /* Per musbhsfc_pg, only flush FIFO if OUT packet is ready */ + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_FLUSHFIFO; + } + } + dcd_event_bus_reset(0, (MXC_USBHS->power & MXC_F_USBHS_POWER_HS_MODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); +} + +/*------------------------------------------------------------------ + * Device API + *------------------------------------------------------------------*/ + +void dcd_init(uint8_t rhport) +{ + (void)rhport; + MXC_USBHS->intrusben |= MXC_F_USBHS_INTRUSBEN_SUSPEND_INT_EN; + + //Interrupt for VBUS disconnect + MXC_USBHS->mxm_int_en |= MXC_F_USBHS_MXM_INT_EN_NOVBUS; + + NVIC_ClearPendingIRQ(USB_IRQn); + dcd_edpt_close_all(rhport); + + //Unsuspend the MAC + MXC_USBHS->mxm_suspend = 0; + + /* Configure PHY */ + MXC_USBHS->m31_phy_xcfgi_31_0 = (0x1 << 3) | (0x1 << 11); + MXC_USBHS->m31_phy_xcfgi_63_32 = 0; + MXC_USBHS->m31_phy_xcfgi_95_64 = 0x1 << (72-64); + MXC_USBHS->m31_phy_xcfgi_127_96 = 0; + + +#ifdef USBHS_M31_CLOCK_RECOVERY + MXC_USBHS->m31_phy_noncry_rstb = 1; + MXC_USBHS->m31_phy_noncry_en = 1; + MXC_USBHS->m31_phy_outclksel = 0; + MXC_USBHS->m31_phy_coreclkin = 0; + MXC_USBHS->m31_phy_xtlsel = 2; /* Select 25 MHz clock */ +#else + /* Use this option to feed the PHY a 30 MHz clock, which is them used as a PLL reference */ + /* As it depends on the system core clock, this should probably be done at the SYS level */ + MXC_USBHS->m31_phy_noncry_rstb = 0; + MXC_USBHS->m31_phy_noncry_en = 0; + MXC_USBHS->m31_phy_outclksel = 1; + MXC_USBHS->m31_phy_coreclkin = 1; + MXC_USBHS->m31_phy_xtlsel = 3; /* Select 30 MHz clock */ +#endif + MXC_USBHS->m31_phy_pll_en = 1; + MXC_USBHS->m31_phy_oscouten = 1; + + /* Reset PHY */ + MXC_USBHS->m31_phy_ponrst = 0; + MXC_USBHS->m31_phy_ponrst = 1; + + dcd_connect(rhport); +} + +void dcd_int_enable(uint8_t rhport) +{ + (void)rhport; + NVIC_EnableIRQ(USB_IRQn); +} + +void dcd_int_disable(uint8_t rhport) +{ + (void)rhport; + NVIC_DisableIRQ(USB_IRQn); +} + +// Receive Set Address request, mcu port must also include status IN response +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) +{ + (void)rhport; + (void)dev_addr; + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; + _dcd.pipe0.remaining = 0; + /* Clear RX FIFO to return ACK. */ + MXC_USBHS->index = 0; + MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY | MXC_F_USBHS_CSR0_DATA_END; +} + +// Wake up host +void dcd_remote_wakeup(uint8_t rhport) +{ + (void)rhport; + MXC_USBHS->power |= MXC_F_USBHS_POWER_RESUME; + +#if CFG_TUSB_OS != OPT_OS_NONE + osal_task_delay(10); +#else + MXC_Delay(MXC_DELAY_MSEC(10)); +#endif + + MXC_USBHS->power &= ~MXC_F_USBHS_POWER_RESUME; +} + +// Connect by enabling internal pull-up resistor on D+/D- +void dcd_connect(uint8_t rhport) +{ + (void)rhport; + MXC_USBHS->power |= TUD_OPT_HIGH_SPEED ? MXC_F_USBHS_POWER_HS_ENABLE : 0; + MXC_USBHS->power |= MXC_F_USBHS_POWER_SOFTCONN; +} + +// Disconnect by disabling internal pull-up resistor on D+/D- +void dcd_disconnect(uint8_t rhport) +{ + (void)rhport; + MXC_USBHS->power &= ~MXC_F_USBHS_POWER_SOFTCONN; +} + +void dcd_sof_enable(uint8_t rhport, bool en) +{ + (void) rhport; + (void) en; + + // TODO implement later +} + +//--------------------------------------------------------------------+ +// Endpoint API +//--------------------------------------------------------------------+ + +// Configure endpoint's registers according to descriptor +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) +{ + (void) rhport; + + const unsigned ep_addr = ep_desc->bEndpointAddress; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned xfer = ep_desc->bmAttributes.xfer; + const unsigned mps = tu_edpt_packet_size(ep_desc); + + TU_ASSERT(epn < TUP_DCD_ENDPOINT_MAX); + + pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1]; + pipe->buf = NULL; + pipe->length = 0; + pipe->remaining = 0; + + MXC_USBHS->index = epn; + + if (dir_in) { + MXC_USBHS->inmaxp = mps; + MXC_USBHS->incsru = (MXC_F_USBHS_INCSRU_DPKTBUFDIS | MXC_F_USBHS_INCSRU_MODE) | ((xfer == TUSB_XFER_ISOCHRONOUS) ? MXC_F_USBHS_INCSRU_ISO : 0); + if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO; + } else { + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; + } + MXC_USBHS->intrinen |= TU_BIT(epn); + } else { + MXC_USBHS->outmaxp = mps; + MXC_USBHS->outcsru = (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS) | ((xfer == TUSB_XFER_ISOCHRONOUS) ? MXC_F_USBHS_OUTCSRU_ISO : 0); + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO; + } else { + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG; + } + MXC_USBHS->introuten |= TU_BIT(epn); + } + + return true; +} + +void dcd_edpt_close_all(uint8_t rhport) +{ + (void) rhport; + + MXC_SYS_Crit_Enter(); + MXC_USBHS->intrinen = 1; /* Enable only EP0 */ + MXC_USBHS->introuten = 0; + + for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { + MXC_USBHS->index = i; + MXC_USBHS->inmaxp = 0; + MXC_USBHS->incsru = MXC_F_USBHS_INCSRU_DPKTBUFDIS; + + if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO; + } else { + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; + } + + MXC_USBHS->outmaxp = 0; + MXC_USBHS->outcsru = MXC_F_USBHS_OUTCSRU_DPKTBUFDIS; + + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO; + } else { + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG; + } + } + MXC_SYS_Crit_Exit(); +} + +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + unsigned const epn = tu_edpt_number(ep_addr); + unsigned const dir_in = tu_edpt_dir(ep_addr); + + MXC_SYS_Crit_Enter(); + MXC_USBHS->index = epn; + if (dir_in) { + MXC_USBHS->intrinen &= ~TU_BIT(epn); + MXC_USBHS->inmaxp = 0; + MXC_USBHS->incsru = MXC_F_USBHS_INCSRU_DPKTBUFDIS; + if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO; + } else { + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; + } + } else { + MXC_USBHS->introuten &= ~TU_BIT(epn); + MXC_USBHS->outmaxp = 0; + MXC_USBHS->outcsru = MXC_F_USBHS_OUTCSRU_DPKTBUFDIS; + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO; + } else { + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG; + } + } + MXC_SYS_Crit_Exit(); +} + +// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) +{ + (void)rhport; + bool ret; + unsigned const epnum = tu_edpt_number(ep_addr); + MXC_SYS_Crit_Enter(); + if (epnum) { + _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] &= ~TU_BIT(epnum - 1); + ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes); + } else + ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes); + MXC_SYS_Crit_Exit(); + return ret; +} + +// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c +bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) +{ + (void)rhport; + bool ret; + unsigned const epnum = tu_edpt_number(ep_addr); + TU_ASSERT(epnum); + MXC_SYS_Crit_Enter(); + _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] |= TU_BIT(epnum - 1); + ret = edpt_n_xfer(rhport, ep_addr, (uint8_t*)ff, total_bytes); + MXC_SYS_Crit_Exit(); + return ret; +} + +// Stall endpoint +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + unsigned const epn = tu_edpt_number(ep_addr); + MXC_SYS_Crit_Enter(); + MXC_USBHS->index = epn; + if (0 == epn) { + if (!ep_addr) { /* Ignore EP80 */ + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; + _dcd.pipe0.buf = NULL; + MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SEND_STALL; + } + } else { + if (tu_edpt_dir(ep_addr)) { /* IN */ + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_SENDSTALL; + } else { /* OUT */ + TU_ASSERT(!(MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY),); + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_SENDSTALL; + } + } + MXC_SYS_Crit_Exit(); +} + +// clear stall, data toggle is also reset to DATA0 +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + unsigned const epn = tu_edpt_number(ep_addr); + MXC_SYS_Crit_Enter(); + MXC_USBHS->index = epn; + if (tu_edpt_dir(ep_addr)) { /* IN */ + /* IN endpoint */ + if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { + /* Per musbhsfc_pg, only flush FIFO if IN packet loaded */ + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO; + } else { + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; + } + } else { /* OUT */ + /* Otherwise, must be OUT endpoint */ + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { + /* Per musbhsfc_pg, only flush FIFO if OUT packet is ready */ + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO; + } else { + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG; + } + } + MXC_SYS_Crit_Exit(); +} + +/*------------------------------------------------------------------- + * ISR + *-------------------------------------------------------------------*/ +void dcd_int_handler(uint8_t rhport) +{ + uint_fast8_t is, txis, rxis; + uint32_t mxm_int, mxm_int_en, mxm_is; + uint32_t saved_index; + + /* Save current index register */ + saved_index = MXC_USBHS->index; + + is = MXC_USBHS->intrusb; /* read and clear interrupt status */ + txis = MXC_USBHS->intrin; /* read and clear interrupt status */ + rxis = MXC_USBHS->introut; /* read and clear interrupt status */ + + /* These USB interrupt flags are W1C. */ + /* Order of volatile accesses must be separated for IAR */ + mxm_int = MXC_USBHS->mxm_int; + mxm_int_en = MXC_USBHS->mxm_int_en; + mxm_is = mxm_int & mxm_int_en; + MXC_USBHS->mxm_int = mxm_is; + + is &= MXC_USBHS->intrusben; /* Clear disabled interrupts */ + + if (mxm_is & MXC_F_USBHS_MXM_INT_NOVBUS) { + dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); + } + if (is & MXC_F_USBHS_INTRUSB_SOF_INT) { + dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); + } + if (is & MXC_F_USBHS_INTRUSB_RESET_INT) { + process_bus_reset(rhport); + } + if (is & MXC_F_USBHS_INTRUSB_RESUME_INT) { + dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); + } + if (is & MXC_F_USBHS_INTRUSB_SUSPEND_INT) { + dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); + } + + txis &= MXC_USBHS->intrinen; /* Clear disabled interrupts */ + if (txis & MXC_F_USBHS_INTRIN_EP0_IN_INT) { + process_ep0(rhport); + txis &= ~TU_BIT(0); + } + while (txis) { + unsigned const num = __builtin_ctz(txis); + process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN)); + txis &= ~TU_BIT(num); + } + rxis &= MXC_USBHS->introuten; /* Clear disabled interrupts */ + while (rxis) { + unsigned const num = __builtin_ctz(rxis); + process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT)); + rxis &= ~TU_BIT(num); + } + + /* Restore register index before exiting ISR */ + MXC_USBHS->index = saved_index; +} + +#endif diff --git a/src/tusb_option.h b/src/tusb_option.h index db8b94580..18f78b49c 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -188,6 +188,9 @@ #define OPT_MCU_MCXN9 2300 ///< NXP MCX N9 Series #define OPT_MCU_MCXA15 2301 ///< NXP MCX A15 Series +// Analog Devices +#define OPT_MCU_MAX32690 2400 ///< ADI MAX32690 + // Check if configured MCU is one of listed // Apply _TU_CHECK_MCU with || as separator to list of input #define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == _m) diff --git a/tools/get_deps.py b/tools/get_deps.py index 50cc5c893..e05cc4d76 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -24,6 +24,9 @@ deps_optional = { 'hw/mcu/allwinner': ['https://github.com/hathach/allwinner_driver.git', '8e5e89e8e132c0fd90e72d5422e5d3d68232b756', 'fc100s'], + 'hw/mcu/analog/max32' : ['https://github.com/analogdevicesinc/msdk.git', + 'b20b398d3e5e2007594e54a74ba3d2a2e50ddd75', + 'max32690'], 'hw/mcu/bridgetek/ft9xx/ft90x-sdk': ['https://github.com/BRTSG-FOSS/ft90x-sdk.git', '91060164afe239fcb394122e8bf9eb24d3194eb1', 'brtmm90x'], -- cgit v1.3.1 From 0b82af61f3ca7f6b708399c49519fb109ab33abb Mon Sep 17 00:00:00 2001 From: Brent Kowal Date: Mon, 1 Jul 2024 16:31:17 -0400 Subject: AD-APARD32690-SL Support and Cleanup - Added BSP for AD-APARD32690-SL board (apard32690) - Ran clang-formatting on previously committed code - Removed LOG messages from dcd_max32.c --- hw/bsp/max32690/boards/apard32690/board.cmake | 1 + hw/bsp/max32690/boards/apard32690/board.h | 56 +++++ hw/bsp/max32690/boards/apard32690/board.mk | 1 + hw/bsp/max32690/boards/max32690evkit/board.h | 22 +- hw/bsp/max32690/family.c | 32 +-- src/portable/analog/max32/dcd_max32.c | 339 ++++++++++++-------------- 6 files changed, 239 insertions(+), 212 deletions(-) create mode 100644 hw/bsp/max32690/boards/apard32690/board.cmake create mode 100644 hw/bsp/max32690/boards/apard32690/board.h create mode 100644 hw/bsp/max32690/boards/apard32690/board.mk (limited to 'hw') diff --git a/hw/bsp/max32690/boards/apard32690/board.cmake b/hw/bsp/max32690/boards/apard32690/board.cmake new file mode 100644 index 000000000..9dc6962eb --- /dev/null +++ b/hw/bsp/max32690/boards/apard32690/board.cmake @@ -0,0 +1 @@ +# Nothing to be done at the board level diff --git a/hw/bsp/max32690/boards/apard32690/board.h b/hw/bsp/max32690/boards/apard32690/board.h new file mode 100644 index 000000000..f94097ca9 --- /dev/null +++ b/hw/bsp/max32690/boards/apard32690/board.h @@ -0,0 +1,56 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "gpio.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// LED +#define LED_PORT MXC_GPIO2 +#define LED_PIN MXC_GPIO_PIN_1 +#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH +#define LED_STATE_ON 1 + +// Button +#define BUTTON_PORT MXC_GPIO1 +#define BUTTON_PIN MXC_GPIO_PIN_27 +#define BUTTON_PULL MXC_GPIO_PAD_NONE +#define BUTTON_STATE_ACTIVE 1 + +// UART Enable for UART on ARM SWD Connector +#define UART_NUM 0 + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/max32690/boards/apard32690/board.mk b/hw/bsp/max32690/boards/apard32690/board.mk new file mode 100644 index 000000000..a813a5327 --- /dev/null +++ b/hw/bsp/max32690/boards/apard32690/board.mk @@ -0,0 +1 @@ +# No specific build requirements for the board. diff --git a/hw/bsp/max32690/boards/max32690evkit/board.h b/hw/bsp/max32690/boards/max32690evkit/board.h index f5a904702..05d60f220 100644 --- a/hw/bsp/max32690/boards/max32690evkit/board.h +++ b/hw/bsp/max32690/boards/max32690evkit/board.h @@ -31,26 +31,26 @@ #include "mxc_sys.h" #ifdef __cplusplus - extern "C" { +extern "C" { #endif // LED -#define LED_PORT MXC_GPIO0 -#define LED_PIN MXC_GPIO_PIN_14 -#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH -#define LED_STATE_ON 0 +#define LED_PORT MXC_GPIO0 +#define LED_PIN MXC_GPIO_PIN_14 +#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH +#define LED_STATE_ON 0 // Button -#define BUTTON_PORT MXC_GPIO4 -#define BUTTON_PIN MXC_GPIO_PIN_0 -#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP -#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_PORT MXC_GPIO4 +#define BUTTON_PIN MXC_GPIO_PIN_0 +#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP +#define BUTTON_STATE_ACTIVE 0 // UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL -#define UART_NUM 2 +#define UART_NUM 2 #ifdef __cplusplus - } +} #endif #endif /* BOARD_H_ */ diff --git a/hw/bsp/max32690/family.c b/hw/bsp/max32690/family.c index f443bc575..acd6e2593 100644 --- a/hw/bsp/max32690/family.c +++ b/hw/bsp/max32690/family.c @@ -24,12 +24,12 @@ * This file is part of the TinyUSB stack. */ -#include "bsp/board_api.h" #include "board.h" -#include "mxc_device.h" +#include "bsp/board_api.h" +#include "gpio.h" #include "mcr_regs.h" +#include "mxc_device.h" #include "uart.h" -#include "gpio.h" //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler @@ -49,7 +49,7 @@ void board_init(void) { SysTick_Config(SystemCoreClock / 1000); #elif CFG_TUSB_OS == OPT_OS_FREERTOS // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); + NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); #endif mxc_gpio_cfg_t gpioConfig; @@ -87,10 +87,10 @@ void board_init(void) { //--------------------------------------------------------------------+ void board_led_write(bool state) { - #if LED_STATE_ON - state = !state; - #endif - if(state) { +#if LED_STATE_ON + state = !state; +#endif + if (state) { MXC_GPIO_OutClr(LED_PORT, LED_PIN); } else { MXC_GPIO_OutSet(LED_PORT, LED_PIN); @@ -103,9 +103,9 @@ uint32_t board_button_read(void) { } size_t board_get_unique_id(uint8_t id[], size_t max_len) { - uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN]; //USN Buffer - /* All other 2nd parameter is optional checkum buffer */ - MXC_SYS_GetUSN(hw_id, NULL); + uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer + /* All other 2nd parameter is optional checkum buffer */ + MXC_SYS_GetUSN(hw_id, NULL); size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); memcpy(id, hw_id, act_len); @@ -116,11 +116,11 @@ int board_uart_read(uint8_t *buf, int len) { int uart_val; int act_len = 0; - while( act_len < len ) { - if((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { + while (act_len < len) { + if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { break; } else { - *buf++ = (uint8_t)uart_val; + *buf++ = (uint8_t) uart_val; act_len++; } } @@ -129,8 +129,8 @@ int board_uart_read(uint8_t *buf, int len) { int board_uart_write(void const *buf, int len) { int act_len = 0; - const uint8_t* ch_ptr = (const uint8_t*)buf; - while(act_len < len){ + const uint8_t *ch_ptr = (const uint8_t *) buf; + while (act_len < len) { MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++); act_len++; } diff --git a/src/portable/analog/max32/dcd_max32.c b/src/portable/analog/max32/dcd_max32.c index 150d476fa..b3370ddd1 100644 --- a/src/portable/analog/max32/dcd_max32.c +++ b/src/portable/analog/max32/dcd_max32.c @@ -29,49 +29,48 @@ #if CFG_TUD_ENABLED && TU_CHECK_MCU(OPT_MCU_MAX32690) -#if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) + #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) /* GCC warns that an address may be unaligned, even though * the target CPU has the capability for unaligned memory access. */ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); -#endif + #endif -#include "device/dcd.h" + #include "device/dcd.h" -#include "mxc_delay.h" -#include "mxc_device.h" -#include "mxc_sys.h" -#include "nvic_table.h" -#include "usbhs_regs.h" + #include "mxc_delay.h" + #include "mxc_device.h" + #include "mxc_sys.h" + #include "nvic_table.h" + #include "usbhs_regs.h" -#define USBHS_M31_CLOCK_RECOVERY + #define USBHS_M31_CLOCK_RECOVERY -/*------------------------------------------------------------------ + /*------------------------------------------------------------------ * MACRO TYPEDEF CONSTANT ENUM DECLARATION *------------------------------------------------------------------*/ -#define REQUEST_TYPE_INVALID (0xFFu) + #define REQUEST_TYPE_INVALID (0xFFu) typedef union { - uint8_t u8; - uint16_t u16; - uint32_t u32; + uint8_t u8; + uint16_t u16; + uint32_t u32; } hw_fifo_t; -typedef struct TU_ATTR_PACKED -{ - void *buf; /* the start address of a transfer data buffer */ - uint16_t length; /* the number of bytes in the buffer */ - uint16_t remaining; /* the number of bytes remaining in the buffer */ +typedef struct TU_ATTR_PACKED { + void *buf; /* the start address of a transfer data buffer */ + uint16_t length; /* the number of bytes in the buffer */ + uint16_t remaining; /* the number of bytes remaining in the buffer */ } pipe_state_t; typedef struct { tusb_control_request_t setup_packet; - uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */ - int8_t status_out; + uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */ + int8_t status_out; pipe_state_t pipe0; - pipe_state_t pipe[2][TUP_DCD_ENDPOINT_MAX - 1]; /* pipe[direction][endpoint number - 1] */ - uint16_t pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */ + pipe_state_t pipe[2][TUP_DCD_ENDPOINT_MAX - 1]; /* pipe[direction][endpoint number - 1] */ + uint16_t pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */ } dcd_data_t; /*------------------------------------------------------------------ @@ -80,63 +79,59 @@ typedef struct static dcd_data_t _dcd; -static volatile void* edpt_get_fifo_ptr(unsigned epnum) -{ - volatile uint32_t *ptr; +static volatile void *edpt_get_fifo_ptr(unsigned epnum) { + volatile uint32_t *ptr; - ptr = &MXC_USBHS->fifo0; - ptr += epnum; /* Pointer math: multiplies ep by sizeof(uint32_t) */ + ptr = &MXC_USBHS->fifo0; + ptr += epnum; /* Pointer math: multiplies ep by sizeof(uint32_t) */ - return (volatile void *)ptr; + return (volatile void *) ptr; } -static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) -{ - volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; - uintptr_t addr = (uintptr_t)buf; +static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { + volatile hw_fifo_t *reg = (volatile hw_fifo_t *) fifo; + uintptr_t addr = (uintptr_t) buf; while (len >= 4) { - reg->u32 = *(uint32_t const *)addr; + reg->u32 = *(uint32_t const *) addr; addr += 4; - len -= 4; + len -= 4; } if (len >= 2) { - reg->u16 = *(uint16_t const *)addr; + reg->u16 = *(uint16_t const *) addr; addr += 2; - len -= 2; + len -= 2; } if (len) { - reg->u8 = *(uint8_t const *)addr; + reg->u8 = *(uint8_t const *) addr; } } -static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) -{ - volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; - uintptr_t addr = (uintptr_t)buf; +static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) { + volatile hw_fifo_t *reg = (volatile hw_fifo_t *) fifo; + uintptr_t addr = (uintptr_t) buf; while (len >= 4) { - *(uint32_t *)addr = reg->u32; + *(uint32_t *) addr = reg->u32; addr += 4; - len -= 4; + len -= 4; } if (len >= 2) { - *(uint16_t *)addr = reg->u16; + *(uint16_t *) addr = reg->u16; addr += 2; - len -= 2; + len -= 2; } if (len) { - *(uint8_t *)addr = reg->u8; + *(uint8_t *) addr = reg->u8; } } -static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) -{ +static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) { static const struct { void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info); void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n); void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len); } ops[] = { - /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet}, - /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, + /* OUT */ {tu_fifo_get_write_info, tu_fifo_advance_write_pointer, pipe_read_packet}, + /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, }; tu_fifo_buffer_info_t info; ops[dir].tu_fifo_get_info(f, &info); @@ -152,19 +147,18 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne ops[dir].tu_fifo_advance(f, total_len - rem); } -static void process_setup_packet(uint8_t rhport) -{ - uint32_t *p = (void*)&_dcd.setup_packet; - p[0] = MXC_USBHS->fifo0; - p[1] = MXC_USBHS->fifo0; +static void process_setup_packet(uint8_t rhport) { + uint32_t *p = (void *) &_dcd.setup_packet; + p[0] = MXC_USBHS->fifo0; + p[1] = MXC_USBHS->fifo0; - _dcd.pipe0.buf = NULL; - _dcd.pipe0.length = 0; + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; - dcd_event_setup_received(rhport, (const uint8_t*)(uintptr_t)&_dcd.setup_packet, true); + dcd_event_setup_received(rhport, (const uint8_t *) (uintptr_t) &_dcd.setup_packet, true); - const unsigned len = _dcd.setup_packet.wLength; - _dcd.remaining_ctrl = len; + const unsigned len = _dcd.setup_packet.wLength; + _dcd.remaining_ctrl = len; const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType); /* Clear RX FIFO and reverse the transaction direction */ if (len && dir_in) { @@ -173,12 +167,11 @@ static void process_setup_packet(uint8_t rhport) } } -static bool handle_xfer_in(uint_fast8_t ep_addr) -{ +static bool handle_xfer_in(uint_fast8_t ep_addr) { unsigned epnum = tu_edpt_number(ep_addr); unsigned epnum_minus1 = epnum - 1; - pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; - const unsigned rem = pipe->remaining; + pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; + const unsigned rem = pipe->remaining; //This function should not be for ep0 TU_ASSERT(epnum); @@ -191,28 +184,26 @@ static bool handle_xfer_in(uint_fast8_t ep_addr) MXC_USBHS->index = epnum; const unsigned mps = MXC_USBHS->inmaxp; const unsigned len = TU_MIN(mps, rem); - void *buf = pipe->buf; - volatile void* fifo_ptr = edpt_get_fifo_ptr(epnum); - // TU_LOG1(" %p mps %d len %d rem %d\r\n", buf, mps, len, rem); + void *buf = pipe->buf; + volatile void *fifo_ptr = edpt_get_fifo_ptr(epnum); if (len) { if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) { pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_IN); } else { - pipe_write_packet(buf,fifo_ptr, len); - pipe->buf = buf + len; + pipe_write_packet(buf, fifo_ptr, len); + pipe->buf = buf + len; } pipe->remaining = rem - len; } - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_INPKTRDY; //TODO: Verify a | isnt needed + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_INPKTRDY;//TODO: Verify a | isnt needed return false; } -static bool handle_xfer_out(uint_fast8_t ep_addr) -{ +static bool handle_xfer_out(uint_fast8_t ep_addr) { unsigned epnum = tu_edpt_number(ep_addr); unsigned epnum_minus1 = epnum - 1; - pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; + pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; //This function should not be for ep0 TU_ASSERT(epnum); @@ -225,14 +216,14 @@ static bool handle_xfer_out(uint_fast8_t ep_addr) const unsigned rem = pipe->remaining; const unsigned vld = MXC_USBHS->outcount; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); - void *buf = pipe->buf; - volatile void* fifo_ptr = edpt_get_fifo_ptr(epnum); + void *buf = pipe->buf; + volatile void *fifo_ptr = edpt_get_fifo_ptr(epnum); if (len) { if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) { - pipe_read_write_packet_ff(buf,fifo_ptr, len, TUSB_DIR_OUT); + pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_OUT); } else { pipe_read_packet(buf, fifo_ptr, len); - pipe->buf = buf + len; + pipe->buf = buf + len; } pipe->remaining = rem - len; } @@ -240,37 +231,35 @@ static bool handle_xfer_out(uint_fast8_t ep_addr) pipe->buf = NULL; return NULL != buf; } - MXC_USBHS->outcsrl = 0; /* Clear RXRDY bit */ //TODO: Verify just setting to 0 is ok + MXC_USBHS->outcsrl = 0; /* Clear RXRDY bit *///TODO: Verify just setting to 0 is ok return false; } -static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) -{ - (void)rhport; +static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { + (void) rhport; - unsigned epnum = tu_edpt_number(ep_addr); + unsigned epnum = tu_edpt_number(ep_addr); unsigned epnum_minus1 = epnum - 1; - unsigned dir_in = tu_edpt_dir(ep_addr); + unsigned dir_in = tu_edpt_dir(ep_addr); pipe_state_t *pipe = &_dcd.pipe[dir_in][epnum_minus1]; - pipe->buf = buffer; - pipe->length = total_bytes; - pipe->remaining = total_bytes; + pipe->buf = buffer; + pipe->length = total_bytes; + pipe->remaining = total_bytes; if (dir_in) { handle_xfer_in(ep_addr); } else { MXC_USBHS->index = epnum; - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY){ - MXC_USBHS->outcsrl = 0; //TODO: Verify just setting to 0 is ok + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { + MXC_USBHS->outcsrl = 0;//TODO: Verify just setting to 0 is ok } } return true; } -static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) -{ - (void)rhport; +static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { + (void) rhport; TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */ const unsigned req = _dcd.setup_packet.bmRequestType; @@ -299,15 +288,15 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ TU_ASSERT(total_bytes <= _dcd.remaining_ctrl); const unsigned rem = _dcd.remaining_ctrl; const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes); - volatile void* fifo_ptr = edpt_get_fifo_ptr(0); + volatile void *fifo_ptr = edpt_get_fifo_ptr(0); if (dir_in) { pipe_write_packet(buffer, fifo_ptr, len); - _dcd.pipe0.buf = buffer + len; - _dcd.pipe0.length = len; + _dcd.pipe0.buf = buffer + len; + _dcd.pipe0.length = len; _dcd.pipe0.remaining = 0; - _dcd.remaining_ctrl = rem - len; + _dcd.remaining_ctrl = rem - len; if ((len < 64) || (rem == len)) { _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */ _dcd.status_out = 1; @@ -317,14 +306,14 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_INPKTRDY; /* Flush TX FIFO to return ACK. */ } } else { - _dcd.pipe0.buf = buffer; - _dcd.pipe0.length = len; + _dcd.pipe0.buf = buffer; + _dcd.pipe0.length = len; _dcd.pipe0.remaining = len; MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY; /* Clear RX FIFO to return ACK. */ } } else if (dir_in) { _dcd.pipe0.buf = NULL; - _dcd.pipe0.length = 0; + _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; /* Clear RX FIFO and reverse the transaction direction */ MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY | MXC_F_USBHS_CSR0_DATA_END; @@ -332,8 +321,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ return true; } -static void process_ep0(uint8_t rhport) -{ +static void process_ep0(uint8_t rhport) { MXC_USBHS->index = 0; uint_fast8_t csrl = MXC_USBHS->csr0; @@ -364,7 +352,7 @@ static void process_ep0(uint8_t rhport) /* Received SETUP or DATA OUT packet */ if (req == REQUEST_TYPE_INVALID) { /* SETUP */ - TU_ASSERT(sizeof(tusb_control_request_t) == MXC_USBHS->count0,); + TU_ASSERT(sizeof(tusb_control_request_t) == MXC_USBHS->count0, ); process_setup_packet(rhport); return; } @@ -373,7 +361,7 @@ static void process_ep0(uint8_t rhport) const unsigned vld = MXC_USBHS->count0; const unsigned rem = _dcd.pipe0.remaining; const unsigned len = TU_MIN(TU_MIN(rem, 64), vld); - volatile void* fifo_ptr = edpt_get_fifo_ptr(0); + volatile void *fifo_ptr = edpt_get_fifo_ptr(0); pipe_read_packet(_dcd.pipe0.buf, fifo_ptr, len); _dcd.pipe0.remaining = rem - len; @@ -392,9 +380,9 @@ static void process_ep0(uint8_t rhport) * or receiving a zero length packet. */ if (req != REQUEST_TYPE_INVALID && !tu_edpt_dir(req)) { /* STATUS IN */ - if (*(const uint16_t*)(uintptr_t)&_dcd.setup_packet == 0x0500) { + if (*(const uint16_t *) (uintptr_t) &_dcd.setup_packet == 0x0500) { /* The address must be changed on completion of the control transfer. */ - MXC_USBHS->faddr = (uint8_t)_dcd.setup_packet.wValue; + MXC_USBHS->faddr = (uint8_t) _dcd.setup_packet.wValue; } _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; dcd_event_xfer_complete(rhport, @@ -413,11 +401,10 @@ static void process_ep0(uint8_t rhport) } } -static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) -{ +static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) { bool completed; - const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned epnum = tu_edpt_number(ep_addr); + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned epnum = tu_edpt_number(ep_addr); MXC_USBHS->index = epnum; @@ -443,10 +430,8 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) } } -static void process_bus_reset(uint8_t rhport) -{ - (void)rhport; - TU_LOG0("------Bus Reset\r\n"); +static void process_bus_reset(uint8_t rhport) { + (void) rhport; /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), * a control transfer state is SETUP or STATUS stage. */ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; @@ -462,14 +447,14 @@ static void process_bus_reset(uint8_t rhport) for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { MXC_USBHS->index = i; if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { - /* Per musbhsfc_pg, only flush FIFO if IN packet loaded */ - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_FLUSHFIFO; - } + /* Per musbhsfc_pg, only flush FIFO if IN packet loaded */ + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_FLUSHFIFO; + } - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { - /* Per musbhsfc_pg, only flush FIFO if OUT packet is ready */ - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_FLUSHFIFO; - } + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { + /* Per musbhsfc_pg, only flush FIFO if OUT packet is ready */ + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_FLUSHFIFO; + } } dcd_event_bus_reset(0, (MXC_USBHS->power & MXC_F_USBHS_POWER_HS_MODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); } @@ -478,9 +463,8 @@ static void process_bus_reset(uint8_t rhport) * Device API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport) -{ - (void)rhport; +void dcd_init(uint8_t rhport) { + (void) rhport; MXC_USBHS->intrusben |= MXC_F_USBHS_INTRUSBEN_SUSPEND_INT_EN; //Interrupt for VBUS disconnect @@ -495,17 +479,17 @@ void dcd_init(uint8_t rhport) /* Configure PHY */ MXC_USBHS->m31_phy_xcfgi_31_0 = (0x1 << 3) | (0x1 << 11); MXC_USBHS->m31_phy_xcfgi_63_32 = 0; - MXC_USBHS->m31_phy_xcfgi_95_64 = 0x1 << (72-64); + MXC_USBHS->m31_phy_xcfgi_95_64 = 0x1 << (72 - 64); MXC_USBHS->m31_phy_xcfgi_127_96 = 0; -#ifdef USBHS_M31_CLOCK_RECOVERY + #ifdef USBHS_M31_CLOCK_RECOVERY MXC_USBHS->m31_phy_noncry_rstb = 1; MXC_USBHS->m31_phy_noncry_en = 1; MXC_USBHS->m31_phy_outclksel = 0; MXC_USBHS->m31_phy_coreclkin = 0; MXC_USBHS->m31_phy_xtlsel = 2; /* Select 25 MHz clock */ -#else + #else /* Use this option to feed the PHY a 30 MHz clock, which is them used as a PLL reference */ /* As it depends on the system core clock, this should probably be done at the SYS level */ MXC_USBHS->m31_phy_noncry_rstb = 0; @@ -513,7 +497,7 @@ void dcd_init(uint8_t rhport) MXC_USBHS->m31_phy_outclksel = 1; MXC_USBHS->m31_phy_coreclkin = 1; MXC_USBHS->m31_phy_xtlsel = 3; /* Select 30 MHz clock */ -#endif + #endif MXC_USBHS->m31_phy_pll_en = 1; MXC_USBHS->m31_phy_oscouten = 1; @@ -524,25 +508,22 @@ void dcd_init(uint8_t rhport) dcd_connect(rhport); } -void dcd_int_enable(uint8_t rhport) -{ - (void)rhport; +void dcd_int_enable(uint8_t rhport) { + (void) rhport; NVIC_EnableIRQ(USB_IRQn); } -void dcd_int_disable(uint8_t rhport) -{ - (void)rhport; +void dcd_int_disable(uint8_t rhport) { + (void) rhport; NVIC_DisableIRQ(USB_IRQn); } // Receive Set Address request, mcu port must also include status IN response -void dcd_set_address(uint8_t rhport, uint8_t dev_addr) -{ - (void)rhport; - (void)dev_addr; - _dcd.pipe0.buf = NULL; - _dcd.pipe0.length = 0; +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { + (void) rhport; + (void) dev_addr; + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; /* Clear RX FIFO to return ACK. */ MXC_USBHS->index = 0; @@ -550,37 +531,33 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) } // Wake up host -void dcd_remote_wakeup(uint8_t rhport) -{ - (void)rhport; +void dcd_remote_wakeup(uint8_t rhport) { + (void) rhport; MXC_USBHS->power |= MXC_F_USBHS_POWER_RESUME; -#if CFG_TUSB_OS != OPT_OS_NONE + #if CFG_TUSB_OS != OPT_OS_NONE osal_task_delay(10); -#else + #else MXC_Delay(MXC_DELAY_MSEC(10)); -#endif + #endif MXC_USBHS->power &= ~MXC_F_USBHS_POWER_RESUME; } // Connect by enabling internal pull-up resistor on D+/D- -void dcd_connect(uint8_t rhport) -{ - (void)rhport; +void dcd_connect(uint8_t rhport) { + (void) rhport; MXC_USBHS->power |= TUD_OPT_HIGH_SPEED ? MXC_F_USBHS_POWER_HS_ENABLE : 0; MXC_USBHS->power |= MXC_F_USBHS_POWER_SOFTCONN; } // Disconnect by disabling internal pull-up resistor on D+/D- -void dcd_disconnect(uint8_t rhport) -{ - (void)rhport; +void dcd_disconnect(uint8_t rhport) { + (void) rhport; MXC_USBHS->power &= ~MXC_F_USBHS_POWER_SOFTCONN; } -void dcd_sof_enable(uint8_t rhport, bool en) -{ +void dcd_sof_enable(uint8_t rhport, bool en) { (void) rhport; (void) en; @@ -592,21 +569,20 @@ void dcd_sof_enable(uint8_t rhport, bool en) //--------------------------------------------------------------------+ // Configure endpoint's registers according to descriptor -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) -{ +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) { (void) rhport; const unsigned ep_addr = ep_desc->bEndpointAddress; - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned xfer = ep_desc->bmAttributes.xfer; - const unsigned mps = tu_edpt_packet_size(ep_desc); + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned xfer = ep_desc->bmAttributes.xfer; + const unsigned mps = tu_edpt_packet_size(ep_desc); TU_ASSERT(epn < TUP_DCD_ENDPOINT_MAX); pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1]; - pipe->buf = NULL; - pipe->length = 0; + pipe->buf = NULL; + pipe->length = 0; pipe->remaining = 0; MXC_USBHS->index = epn; @@ -634,8 +610,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) return true; } -void dcd_edpt_close_all(uint8_t rhport) -{ +void dcd_edpt_close_all(uint8_t rhport) { (void) rhport; MXC_SYS_Crit_Enter(); @@ -665,10 +640,9 @@ void dcd_edpt_close_all(uint8_t rhport) MXC_SYS_Crit_Exit(); } -void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) -{ - (void)rhport; - unsigned const epn = tu_edpt_number(ep_addr); +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { + (void) rhport; + unsigned const epn = tu_edpt_number(ep_addr); unsigned const dir_in = tu_edpt_dir(ep_addr); MXC_SYS_Crit_Enter(); @@ -683,7 +657,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; } } else { - MXC_USBHS->introuten &= ~TU_BIT(epn); + MXC_USBHS->introuten &= ~TU_BIT(epn); MXC_USBHS->outmaxp = 0; MXC_USBHS->outcsru = MXC_F_USBHS_OUTCSRU_DPKTBUFDIS; if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { @@ -696,9 +670,8 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) } // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) -{ - (void)rhport; +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { + (void) rhport; bool ret; unsigned const epnum = tu_edpt_number(ep_addr); MXC_SYS_Crit_Enter(); @@ -712,23 +685,21 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t } // Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c -bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) -{ - (void)rhport; +bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes) { + (void) rhport; bool ret; unsigned const epnum = tu_edpt_number(ep_addr); TU_ASSERT(epnum); MXC_SYS_Crit_Enter(); _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] |= TU_BIT(epnum - 1); - ret = edpt_n_xfer(rhport, ep_addr, (uint8_t*)ff, total_bytes); + ret = edpt_n_xfer(rhport, ep_addr, (uint8_t *) ff, total_bytes); MXC_SYS_Crit_Exit(); return ret; } // Stall endpoint -void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) -{ - (void)rhport; +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { + (void) rhport; unsigned const epn = tu_edpt_number(ep_addr); MXC_SYS_Crit_Enter(); MXC_USBHS->index = epn; @@ -742,7 +713,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) if (tu_edpt_dir(ep_addr)) { /* IN */ MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_SENDSTALL; } else { /* OUT */ - TU_ASSERT(!(MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY),); + TU_ASSERT(!(MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY), ); MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_SENDSTALL; } } @@ -750,9 +721,8 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) } // clear stall, data toggle is also reset to DATA0 -void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) -{ - (void)rhport; +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { + (void) rhport; unsigned const epn = tu_edpt_number(ep_addr); MXC_SYS_Crit_Enter(); MXC_USBHS->index = epn; @@ -779,8 +749,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) /*------------------------------------------------------------------- * ISR *-------------------------------------------------------------------*/ -void dcd_int_handler(uint8_t rhport) -{ +void dcd_int_handler(uint8_t rhport) { uint_fast8_t is, txis, rxis; uint32_t mxm_int, mxm_int_en, mxm_is; uint32_t saved_index; @@ -788,7 +757,7 @@ void dcd_int_handler(uint8_t rhport) /* Save current index register */ saved_index = MXC_USBHS->index; - is = MXC_USBHS->intrusb; /* read and clear interrupt status */ + is = MXC_USBHS->intrusb; /* read and clear interrupt status */ txis = MXC_USBHS->intrin; /* read and clear interrupt status */ rxis = MXC_USBHS->introut; /* read and clear interrupt status */ -- cgit v1.3.1 From 2353c4ffbaa50072d89008df7a06a7732c824018 Mon Sep 17 00:00:00 2001 From: Brent Kowal Date: Mon, 1 Jul 2024 17:31:38 -0400 Subject: Add MAX78002 Support -Added support for MAX78002, MAX78002EVKIT -Added provisions for remaining MAX32 USB parts --- examples/device/cdc_msc/src/usb_descriptors.c | 3 +- .../device/cdc_msc_freertos/src/usb_descriptors.c | 3 +- examples/device/cdc_uac2/src/usb_descriptors.c | 3 +- .../dynamic_configuration/src/usb_descriptors.c | 3 +- examples/device/midi_test/src/usb_descriptors.c | 3 +- examples/device/msc_dual_lun/src/usb_descriptors.c | 3 +- .../device/net_lwip_webserver/src/tusb_config.h | 2 +- .../net_lwip_webserver/src/usb_descriptors.c | 3 +- examples/device/uac2_headset/src/usb_descriptors.c | 3 +- .../device/webusb_serial/src/usb_descriptors.c | 3 +- hw/bsp/board_mcu.h | 9 ++ hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h | 149 +++++++++++++++++ hw/bsp/max78002/boards/max78002evkit/board.cmake | 1 + hw/bsp/max78002/boards/max78002evkit/board.h | 58 +++++++ hw/bsp/max78002/boards/max78002evkit/board.mk | 1 + hw/bsp/max78002/family.c | 158 ++++++++++++++++++ hw/bsp/max78002/family.cmake | 152 +++++++++++++++++ hw/bsp/max78002/family.mk | 104 ++++++++++++ hw/bsp/max78002/max78002.ld | 180 +++++++++++++++++++++ src/common/tusb_mcu.h | 3 +- src/portable/analog/max32/dcd_max32.c | 3 +- src/tusb_option.h | 3 + tools/get_deps.py | 2 +- 23 files changed, 839 insertions(+), 13 deletions(-) create mode 100644 hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/max78002/boards/max78002evkit/board.cmake create mode 100644 hw/bsp/max78002/boards/max78002evkit/board.h create mode 100644 hw/bsp/max78002/boards/max78002evkit/board.mk create mode 100644 hw/bsp/max78002/family.c create mode 100644 hw/bsp/max78002/family.cmake create mode 100644 hw/bsp/max78002/family.mk create mode 100644 hw/bsp/max78002/max78002.ld (limited to 'hw') diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c index 1ca614f4e..fac7cce8f 100644 --- a/examples/device/cdc_msc/src/usb_descriptors.c +++ b/examples/device/cdc_msc/src/usb_descriptors.c @@ -125,7 +125,8 @@ enum { #define EPNUM_MSC_OUT 0x04 #define EPNUM_MSC_IN 0x85 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // MAX32 doesn't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_CDC_NOTIF 0x81 diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_freertos/src/usb_descriptors.c index f563e80d3..917b73e10 100644 --- a/examples/device/cdc_msc_freertos/src/usb_descriptors.c +++ b/examples/device/cdc_msc_freertos/src/usb_descriptors.c @@ -106,7 +106,8 @@ enum #define EPNUM_MSC_OUT 0x04 #define EPNUM_MSC_IN 0x85 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // MAX32 doesn't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_CDC_NOTIF 0x81 diff --git a/examples/device/cdc_uac2/src/usb_descriptors.c b/examples/device/cdc_uac2/src/usb_descriptors.c index 43e8cf3d7..ab1a2ee83 100644 --- a/examples/device/cdc_uac2/src/usb_descriptors.c +++ b/examples/device/cdc_uac2/src/usb_descriptors.c @@ -117,7 +117,8 @@ uint8_t const * tud_descriptor_device_cb(void) #define EPNUM_CDC_OUT 0x04 #define EPNUM_CDC_IN 0x85 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // MAX32 doesn't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_AUDIO_IN 0x01 diff --git a/examples/device/dynamic_configuration/src/usb_descriptors.c b/examples/device/dynamic_configuration/src/usb_descriptors.c index eebdd4f69..20f237155 100644 --- a/examples/device/dynamic_configuration/src/usb_descriptors.c +++ b/examples/device/dynamic_configuration/src/usb_descriptors.c @@ -158,7 +158,8 @@ enum #define EPNUM_1_MSC_OUT 0x01 #define EPNUM_1_MSC_IN 0x82 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // FT9XX doesn't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_0_CDC_NOTIF 0x81 diff --git a/examples/device/midi_test/src/usb_descriptors.c b/examples/device/midi_test/src/usb_descriptors.c index 797b50ab2..41e6e1818 100644 --- a/examples/device/midi_test/src/usb_descriptors.c +++ b/examples/device/midi_test/src/usb_descriptors.c @@ -90,7 +90,8 @@ enum // On Bridgetek FT9xx endpoint numbers must be unique... #define EPNUM_MIDI_OUT 0x02 #define EPNUM_MIDI_IN 0x03 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // On MAX32 endpoint numbers must be unique... #define EPNUM_MIDI_OUT 0x02 #define EPNUM_MIDI_IN 0x03 diff --git a/examples/device/msc_dual_lun/src/usb_descriptors.c b/examples/device/msc_dual_lun/src/usb_descriptors.c index e32466228..c55bab0d8 100644 --- a/examples/device/msc_dual_lun/src/usb_descriptors.c +++ b/examples/device/msc_dual_lun/src/usb_descriptors.c @@ -97,7 +97,8 @@ enum #define EPNUM_MSC_OUT 0x01 #define EPNUM_MSC_IN 0x82 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // MAX32 doesn't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_MSC_OUT 0x01 diff --git a/examples/device/net_lwip_webserver/src/tusb_config.h b/examples/device/net_lwip_webserver/src/tusb_config.h index 2f641f33e..22082fc81 100644 --- a/examples/device/net_lwip_webserver/src/tusb_config.h +++ b/examples/device/net_lwip_webserver/src/tusb_config.h @@ -91,7 +91,7 @@ extern "C" { #define USE_ECM 1 #elif TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F1) #define USE_ECM 1 -#elif TU_CHECK_MCU(OPT_MCU_MAX32690) +#elif TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX78002) #define USE_ECM 1 #else #define USE_ECM 0 diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c index ba30b869e..012e1bcd8 100644 --- a/examples/device/net_lwip_webserver/src/usb_descriptors.c +++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c @@ -120,7 +120,8 @@ uint8_t const * tud_descriptor_device_cb(void) #define EPNUM_NET_OUT 0x02 #define EPNUM_NET_IN 0x83 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // MAX32 doesn't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_NET_NOTIF 0x81 diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c index bfc8a4ab5..a042ad206 100644 --- a/examples/device/uac2_headset/src/usb_descriptors.c +++ b/examples/device/uac2_headset/src/usb_descriptors.c @@ -104,7 +104,8 @@ uint8_t const * tud_descriptor_device_cb(void) #define EPNUM_AUDIO_OUT 0x02 #define EPNUM_AUDIO_INT 0x03 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // MAX32 doesn't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_AUDIO_IN 0x01 diff --git a/examples/device/webusb_serial/src/usb_descriptors.c b/examples/device/webusb_serial/src/usb_descriptors.c index bcfbe590e..ae1051af6 100644 --- a/examples/device/webusb_serial/src/usb_descriptors.c +++ b/examples/device/webusb_serial/src/usb_descriptors.c @@ -105,7 +105,8 @@ enum #define EPNUM_CDC_OUT 3 #define EPNUM_VENDOR_IN 4 #define EPNUM_VENDOR_OUT 5 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // MAX32 doesn't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_CDC_IN 2 diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index 436164c35..d3a33cf36 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -173,6 +173,15 @@ #elif CFG_TUSB_MCU == OPT_MCU_MAX32690 #include "max32690.h" +#elif CFG_TUSB_MCU == OPT_MCU_MAX32650 + #include "max32650.h" + +#elif CFG_TUSB_MCU == OPT_MCU_MAX32666 + #include "max32665.h" + +#elif CFG_TUSB_MCU == OPT_MCU_MAX78002 + #include "max78002.h" + #else #error "Missing MCU header" #endif diff --git a/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..e5a76af85 --- /dev/null +++ b/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,149 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "mxc_device.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS __NVIC_PRIO_BITS + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<vssel |= UART_VDDIO_BITS; //Set necessary bits to 3.3V + + //USB + MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN; + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) { +#if LED_STATE_ON + state = !state; +#endif + if (state) { + MXC_GPIO_OutClr(LED_PORT, LED_PIN); + } else { + MXC_GPIO_OutSet(LED_PORT, LED_PIN); + } +} + +uint32_t board_button_read(void) { + uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0; + return BUTTON_STATE_ACTIVE == state; +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer + /* All other 2nd parameter is optional checkum buffer */ + MXC_SYS_GetUSN(hw_id, NULL); + + size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); + memcpy(id, hw_id, act_len); + return act_len; +} + +int board_uart_read(uint8_t *buf, int len) { + int uart_val; + int act_len = 0; + + while (act_len < len) { + if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { + break; + } else { + *buf++ = (uint8_t) uart_val; + act_len++; + } + } + return act_len; +} + +int board_uart_write(void const *buf, int len) { + int act_len = 0; + const uint8_t *ch_ptr = (const uint8_t *) buf; + while (act_len < len) { + MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++); + act_len++; + } + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) { + system_ticks++; +} + +uint32_t board_millis(void) { + return system_ticks; +} +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake new file mode 100644 index 000000000..43b172b9f --- /dev/null +++ b/hw/bsp/max78002/family.cmake @@ -0,0 +1,152 @@ +include_guard() + +set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers) +set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS) +set(CMSIS_5 ${TOP}/lib/CMSIS_5) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# Get the linker file from current location (family) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max78002.ld) +set(LD_FILE_Clang ${LD_FILE_GNU}) + +# toolchain set up +set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) +set(JLINK_DEVICE max78000) + +set(FAMILY_MCUS MAX78002 CACHE INTERNAL "") + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + TARGET=MAX78002 + TARGET_REV=0x4131 + MXC_ASSERT_ENABLE + MAX78002 + IAR_PRAGMAS=0 + CFG_TUSB_MCU=OPT_MCU_MAX78002 + BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + ) +endfunction() + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + #set(STARTUP_FILE_IAR ?) + + set(PERIPH_SRC ${MAX32_PERIPH}/Source) + add_library(${BOARD_TARGET} STATIC + ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/heap.c + ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/system_max78002.c + ${PERIPH_SRC}/SYS/mxc_assert.c + ${PERIPH_SRC}/SYS/mxc_delay.c + ${PERIPH_SRC}/SYS/mxc_lock.c + ${PERIPH_SRC}/SYS/nvic_table.c + ${PERIPH_SRC}/SYS/pins_ai87.c + ${PERIPH_SRC}/SYS/sys_ai87.c + ${PERIPH_SRC}/AES/aes_ai87.c + ${PERIPH_SRC}/AES/aes_revb.c + ${PERIPH_SRC}/FLC/flc_common.c + ${PERIPH_SRC}/FLC/flc_ai87.c + ${PERIPH_SRC}/FLC/flc_reva.c + ${PERIPH_SRC}/GPIO/gpio_common.c + ${PERIPH_SRC}/GPIO/gpio_ai87.c + ${PERIPH_SRC}/GPIO/gpio_reva.c + ${PERIPH_SRC}/ICC/icc_ai87.c + ${PERIPH_SRC}/ICC/icc_reva.c + ${PERIPH_SRC}/TRNG/trng_ai87.c + ${PERIPH_SRC}/TRNG/trng_revb.c + ${PERIPH_SRC}/UART/uart_common.c + ${PERIPH_SRC}/UART/uart_ai87.c + ${PERIPH_SRC}/UART/uart_revb.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMSIS_5}/CMSIS/Core/Include + ${MAX32_CMSIS}/Include + ${MAX32_CMSIS}/Device/Maxim/MAX78002/Include + ${MAX32_PERIPH}/Include/MAX78002 + ${PERIPH_SRC}/SYS + ${PERIPH_SRC}/GPIO + ${PERIPH_SRC}/AES + ${PERIPH_SRC}/TRNG + ${PERIPH_SRC}/ICC + ${PERIPH_SRC}/FLC + ${PERIPH_SRC}/UART + ) + + target_compile_options(${TARGET} PRIVATE + -Wno-error=strict-prototypes + -Wno-error=redundant-decls + ) + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_MAX78002 ${RTOS}) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/analog/max32/dcd_max32.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_compile_options(${TARGET}-tinyusb PRIVATE + -Wno-error=strict-prototypes + -Wno-error=redundant-decls + ) + + # Link dependencies + target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + + # Flashing + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/max78002/family.mk b/hw/bsp/max78002/family.mk new file mode 100644 index 000000000..825920596 --- /dev/null +++ b/hw/bsp/max78002/family.mk @@ -0,0 +1,104 @@ +DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32 + +# Important locations in the hw support for MCU +MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS +MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers + +# Add any board specific make rules +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 +PORT ?= 0 + +# GCC +SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S +LD_FILE = $(FAMILY_PATH)/max78002.ld + +# IAR +#SRC_S_IAR += + +# -------------- +# Compiler Flags +# -------------- +# Flags for the MAX78002 SDK +CFLAGS += -DTARGET=MAX78002 \ + -DTARGET_REV=0x4131 \ + -DMXC_ASSERT_ENABLE \ + -DMAX78002 \ + -DIAR_PRAGMAS=0 + +# Flags for TUSB features +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_MAX78002 \ + -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + +# mcu driver cause following warnings +CFLAGS += -Wno-error=redundant-decls \ + -Wno-error=strict-prototypes \ + -Wno-error=unused-parameter \ + -Wno-error=enum-conversion \ + -Wno-error=sign-compare \ + -Wno-error=cast-qual + +LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs + +# For flash-jlink target +JLINK_DEVICE = max78000 + +# flash target using Jlik +flash: flash-jlink + +# Optional flash option when running within an installed MSDK to use OpenOCD +# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. +# If the MSDK is installed, flash-msdk can be run to utilize the the modified +# openocd with the algorithms +MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) +flash-msdk: + $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ + -f interface/cmsis-dap.cfg -f target/max78002.cfg \ + -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" + +# ----------------- +# Sources & Include +# ----------------- +PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source +SRC_C += \ + src/portable/analog/max32/dcd_max32.c \ + $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/heap.c \ + $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/system_max78002.c \ + $(PERIPH_SRC)/SYS/mxc_assert.c \ + $(PERIPH_SRC)/SYS/mxc_delay.c \ + $(PERIPH_SRC)/SYS/mxc_lock.c \ + $(PERIPH_SRC)/SYS/nvic_table.c \ + $(PERIPH_SRC)/SYS/pins_ai87.c \ + $(PERIPH_SRC)/SYS/sys_ai87.c \ + $(PERIPH_SRC)/AES/aes_ai87.c \ + $(PERIPH_SRC)/AES/aes_revb.c \ + $(PERIPH_SRC)/FLC/flc_common.c \ + $(PERIPH_SRC)/FLC/flc_ai87.c \ + $(PERIPH_SRC)/FLC/flc_reva.c \ + $(PERIPH_SRC)/GPIO/gpio_common.c \ + $(PERIPH_SRC)/GPIO/gpio_ai87.c \ + $(PERIPH_SRC)/GPIO/gpio_reva.c \ + $(PERIPH_SRC)/ICC/icc_ai87.c \ + $(PERIPH_SRC)/ICC/icc_reva.c \ + $(PERIPH_SRC)/TRNG/trng_ai87.c \ + $(PERIPH_SRC)/TRNG/trng_revb.c \ + $(PERIPH_SRC)/UART/uart_common.c \ + $(PERIPH_SRC)/UART/uart_ai87.c \ + $(PERIPH_SRC)/UART/uart_revb.c \ + + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(MAX32_CMSIS)/Include \ + $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX78002/Include \ + $(TOP)/$(MAX32_PERIPH)/Include/MAX78002 \ + $(PERIPH_SRC)/SYS \ + $(PERIPH_SRC)/GPIO \ + $(PERIPH_SRC)/AES \ + $(PERIPH_SRC)/ICC \ + $(PERIPH_SRC)/FLC \ + $(PERIPH_SRC)/TRNG \ + $(PERIPH_SRC)/UART diff --git a/hw/bsp/max78002/max78002.ld b/hw/bsp/max78002/max78002.ld new file mode 100644 index 000000000..5f9ed9356 --- /dev/null +++ b/hw/bsp/max78002/max78002.ld @@ -0,0 +1,180 @@ +MEMORY { + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64 kB ROM */ + FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00280000 /* 2.5 MB Flash */ + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00060000 /* 384 kB SRAM */ + /*CSI2 (rwx) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 4096 B CSI2 Buffer */ +} + +SECTIONS { + .rom : + { + KEEP(*(.rom_vector)) + *(.rom_handlers*) + } > ROM + + .text : + { + _text = .; + KEEP(*(.isr_vector)) + EXCLUDE_FILE (*riscv.o) *(.text*) /* Program code (exclude RISCV code) */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + /* Binary import */ + .bin_storage : + { + FILL(0xFF) + _bin_start_ = .; + KEEP(*(.bin_storage_img)) + _bin_end_ = .; + . = ALIGN(4); + } > FLASH + + .rom_code : + { + . = ALIGN(16); + _sran_code = .; + *(.rom_code_section) + _esran_code = .; + } > ROM + + .flash_code : + { + . = ALIGN(16); + _sran_code = .; + *(.flash_code_section) + _esran_code = .; + } > FLASH + + .sram_code : + { + . = ALIGN(16); + _sran_code = .; + *(.sram_code_section) + _esran_code = .; + } > SRAM + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + _csi = . + 0x20000; + *(vtable) + *(.data*) /*read-write initialized data: initialized global variable*/ + + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + .shared : + { + . = ALIGN(4); + _shared = .; + *(.mailbox*) + . = ALIGN(4); + *(.shared*) /*read-write zero initialized data: uninitialzed global variable*/ + _eshared = ALIGN(., 4); + } > SRAM + __shared_data = LOADADDR(.shared); + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") + + /* Section used by RISCV loader projects. See RISCV_LOAD documentation in the build system. */ + .riscv_flash : + { + /* Align address to mod 256 with a small offset. This is required to match the flash page size.*/ + . = ALIGN(256); /* ALIGN operatator is used here. Note that (. & 0x1FFFFF00) was used in the past, but a strange bug was seen on Windows where the & did not behave as expected.*/ + . += 0x100; + _riscv_boot = .; + KEEP(*riscv.o (.text*)) + } > FLASH +} diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index a68e160bd..07cdf3ff0 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -455,7 +455,8 @@ //--------------------------------------------------------------------+ // Analog Devices //--------------------------------------------------------------------+ -#elif TU_CHECK_MCU(OPT_MCU_MAX32690) +#elif TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32666, \ + OPT_MCU_MAX32650, OPT_MCU_MAX78002) #define TUP_DCD_ENDPOINT_MAX 12 #define TUP_RHPORT_HIGHSPEED 1 diff --git a/src/portable/analog/max32/dcd_max32.c b/src/portable/analog/max32/dcd_max32.c index b3370ddd1..7226003de 100644 --- a/src/portable/analog/max32/dcd_max32.c +++ b/src/portable/analog/max32/dcd_max32.c @@ -27,7 +27,8 @@ #include "tusb_option.h" -#if CFG_TUD_ENABLED && TU_CHECK_MCU(OPT_MCU_MAX32690) +#if CFG_TUD_ENABLED && \ + TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX78002) #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) /* GCC warns that an address may be unaligned, even though diff --git a/src/tusb_option.h b/src/tusb_option.h index 18f78b49c..1290d605c 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -190,6 +190,9 @@ // Analog Devices #define OPT_MCU_MAX32690 2400 ///< ADI MAX32690 +#define OPT_MCU_MAX32666 2401 ///< ADI MAX32666/5 +#define OPT_MCU_MAX32650 2402 ///< ADI MAX32650/1/2 +#define OPT_MCU_MAX78002 2403 ///< ADI MAX78002 // Check if configured MCU is one of listed // Apply _TU_CHECK_MCU with || as separator to list of input diff --git a/tools/get_deps.py b/tools/get_deps.py index e05cc4d76..fe548f4ab 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -26,7 +26,7 @@ deps_optional = { 'fc100s'], 'hw/mcu/analog/max32' : ['https://github.com/analogdevicesinc/msdk.git', 'b20b398d3e5e2007594e54a74ba3d2a2e50ddd75', - 'max32690'], + 'max32690 max32650 max32666 max78002'], 'hw/mcu/bridgetek/ft9xx/ft90x-sdk': ['https://github.com/BRTSG-FOSS/ft90x-sdk.git', '91060164afe239fcb394122e8bf9eb24d3194eb1', 'brtmm90x'], -- cgit v1.3.1 From 835a6ed62299ea29c04215d3a4547b74803661c6 Mon Sep 17 00:00:00 2001 From: Brent Kowal Date: Tue, 2 Jul 2024 11:54:23 -0400 Subject: Build System Updates Updated MAX32690 and MAX78002 linker and cmake scripts to work with CMake + Ninja build system. Verified all example projects build with the tools/build.py script for both board, and both make and cmake build systems. --- hw/bsp/max32690/family.cmake | 12 ++++++++---- hw/bsp/max32690/max32690.ld | 2 ++ hw/bsp/max78002/family.cmake | 8 +++++++- hw/bsp/max78002/max78002.ld | 2 ++ 4 files changed, 19 insertions(+), 5 deletions(-) (limited to 'hw') diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake index e1d797f58..8b117bae5 100644 --- a/hw/bsp/max32690/family.cmake +++ b/hw/bsp/max32690/family.cmake @@ -88,7 +88,7 @@ function(add_board_target BOARD_TARGET) ${PERIPH_SRC}/UART ) - target_compile_options(${TARGET} PRIVATE + target_compile_options(${BOARD_TARGET} PRIVATE -Wno-error=strict-prototypes ) update_board(${BOARD_TARGET}) @@ -139,10 +139,14 @@ function(family_configure_example TARGET RTOS) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/analog/max32/dcd_max32.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_compile_options(${TARGET} PRIVATE + -Wno-error=strict-prototypes + ) + + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) target_compile_options(${TARGET}-tinyusb PRIVATE - -Wno-error=strict-prototypes - ) + -Wno-error=strict-prototypes + ) # Link dependencies target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) diff --git a/hw/bsp/max32690/max32690.ld b/hw/bsp/max32690/max32690.ld index 35886fe3a..3d857b4e8 100644 --- a/hw/bsp/max32690/max32690.ld +++ b/hw/bsp/max32690/max32690.ld @@ -151,6 +151,8 @@ SECTIONS { .heap (COPY): { . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); *(.heap*) __HeapLimit = ABSOLUTE(__StackLimit); } > SRAM diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake index 43b172b9f..28eaaa7e9 100644 --- a/hw/bsp/max78002/family.cmake +++ b/hw/bsp/max78002/family.cmake @@ -86,7 +86,7 @@ function(add_board_target BOARD_TARGET) ${PERIPH_SRC}/UART ) - target_compile_options(${TARGET} PRIVATE + target_compile_options(${BOARD_TARGET} PRIVATE -Wno-error=strict-prototypes -Wno-error=redundant-decls ) @@ -133,6 +133,12 @@ function(family_configure_example TARGET RTOS) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) + target_compile_options(${TARGET} PRIVATE + -Wno-error=strict-prototypes + -Wno-error=redundant-decls + ) + + # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MAX78002 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC diff --git a/hw/bsp/max78002/max78002.ld b/hw/bsp/max78002/max78002.ld index 5f9ed9356..60f99e28f 100644 --- a/hw/bsp/max78002/max78002.ld +++ b/hw/bsp/max78002/max78002.ld @@ -159,6 +159,8 @@ SECTIONS { .heap (COPY): { . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); *(.heap*) __HeapLimit = ABSOLUTE(__StackLimit); } > SRAM -- cgit v1.3.1 From 61beb6316d5a69b13c70fabaf71231da92394cc0 Mon Sep 17 00:00:00 2001 From: Brent Kowal Date: Tue, 2 Jul 2024 14:31:38 -0400 Subject: MAX32666 Support Added support for the MAX32666, Boards MAX32666EvKit and MAX32666FTHR. --- hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h | 149 +++++++++++++++++++++ hw/bsp/max32666/boards/max32666evkit/board.cmake | 1 + hw/bsp/max32666/boards/max32666evkit/board.h | 57 ++++++++ hw/bsp/max32666/boards/max32666evkit/board.mk | 1 + hw/bsp/max32666/boards/max32666fthr/board.cmake | 1 + hw/bsp/max32666/boards/max32666fthr/board.h | 57 ++++++++ hw/bsp/max32666/boards/max32666fthr/board.mk | 1 + hw/bsp/max32666/family.c | 161 +++++++++++++++++++++++ hw/bsp/max32666/family.cmake | 151 +++++++++++++++++++++ hw/bsp/max32666/family.mk | 104 +++++++++++++++ hw/bsp/max32666/max32666.ld | 135 +++++++++++++++++++ 11 files changed, 818 insertions(+) create mode 100644 hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/max32666/boards/max32666evkit/board.cmake create mode 100644 hw/bsp/max32666/boards/max32666evkit/board.h create mode 100644 hw/bsp/max32666/boards/max32666evkit/board.mk create mode 100644 hw/bsp/max32666/boards/max32666fthr/board.cmake create mode 100644 hw/bsp/max32666/boards/max32666fthr/board.h create mode 100644 hw/bsp/max32666/boards/max32666fthr/board.mk create mode 100644 hw/bsp/max32666/family.c create mode 100644 hw/bsp/max32666/family.cmake create mode 100644 hw/bsp/max32666/family.mk create mode 100644 hw/bsp/max32666/max32666.ld (limited to 'hw') diff --git a/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..e5a76af85 --- /dev/null +++ b/hw/bsp/max32666/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,149 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "mxc_device.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS __NVIC_PRIO_BITS + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<clkcn & MXC_F_GCR_CLKCN_HIRC96M_EN)) { + MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC96M_EN; + } + + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) { +#if LED_STATE_ON + state = !state; +#endif + if (state) { + MXC_GPIO_OutClr(LED_PORT, LED_PIN); + } else { + MXC_GPIO_OutSet(LED_PORT, LED_PIN); + } +} + +uint32_t board_button_read(void) { + uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0; + return BUTTON_STATE_ACTIVE == state; +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer + /* All other 2nd parameter is optional checkum buffer */ + MXC_SYS_GetUSN(hw_id, NULL); + + size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); + memcpy(id, hw_id, act_len); + return act_len; +} + +int board_uart_read(uint8_t *buf, int len) { + int uart_val; + int act_len = 0; + + while (act_len < len) { + if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { + break; + } else { + *buf++ = (uint8_t) uart_val; + act_len++; + } + } + return act_len; +} + +int board_uart_write(void const *buf, int len) { + int act_len = 0; + const uint8_t *ch_ptr = (const uint8_t *) buf; + while (act_len < len) { + MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++); + act_len++; + } + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) { + system_ticks++; +} + +uint32_t board_millis(void) { + return system_ticks; +} +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} diff --git a/hw/bsp/max32666/family.cmake b/hw/bsp/max32666/family.cmake new file mode 100644 index 000000000..c9fa2510a --- /dev/null +++ b/hw/bsp/max32666/family.cmake @@ -0,0 +1,151 @@ +include_guard() + +set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers) +set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS) +set(CMSIS_5 ${TOP}/lib/CMSIS_5) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# Get the linker file from current location (family) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32666.ld) +set(LD_FILE_Clang ${LD_FILE_GNU}) + +# toolchain set up +set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) +set(JLINK_DEVICE max32666) + +set(FAMILY_MCUS MAX32666 CACHE INTERNAL "") + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + TARGET=MAX32665 + TARGET_REV=0x4131 + MXC_ASSERT_ENABLE + MAX32665 + IAR_PRAGMAS=0 + CFG_TUSB_MCU=OPT_MCU_MAX32666 + BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + ) +endfunction() + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/IAR/startup_max32665.S) + + set(PERIPH_SRC ${MAX32_PERIPH}/Source) + add_library(${BOARD_TARGET} STATIC + ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/heap.c + ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/system_max32665.c + ${PERIPH_SRC}/SYS/mxc_assert.c + ${PERIPH_SRC}/SYS/mxc_delay.c + ${PERIPH_SRC}/SYS/mxc_lock.c + ${PERIPH_SRC}/SYS/nvic_table.c + ${PERIPH_SRC}/SYS/pins_me14.c + ${PERIPH_SRC}/SYS/sys_me14.c + ${PERIPH_SRC}/TPU/tpu_me14.c + ${PERIPH_SRC}/TPU/tpu_reva.c + ${PERIPH_SRC}/FLC/flc_common.c + ${PERIPH_SRC}/FLC/flc_me14.c + ${PERIPH_SRC}/FLC/flc_reva.c + ${PERIPH_SRC}/GPIO/gpio_common.c + ${PERIPH_SRC}/GPIO/gpio_me14.c + ${PERIPH_SRC}/GPIO/gpio_reva.c + ${PERIPH_SRC}/ICC/icc_me14.c + ${PERIPH_SRC}/ICC/icc_reva.c + ${PERIPH_SRC}/UART/uart_common.c + ${PERIPH_SRC}/UART/uart_me14.c + ${PERIPH_SRC}/UART/uart_reva.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMSIS_5}/CMSIS/Core/Include + ${MAX32_CMSIS}/Include + ${MAX32_CMSIS}/Device/Maxim/MAX32665/Include + ${MAX32_PERIPH}/Include/MAX32665 + ${PERIPH_SRC}/SYS + ${PERIPH_SRC}/GPIO + ${PERIPH_SRC}/TPU + ${PERIPH_SRC}/ICC + ${PERIPH_SRC}/FLC + ${PERIPH_SRC}/UART + ) + + target_compile_options(${BOARD_TARGET} PRIVATE + -Wno-error=strict-prototypes + ) + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_MAX32666 ${RTOS}) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/analog/max32/dcd_max32.c + ) + target_compile_options(${TARGET} PRIVATE + -Wno-error=strict-prototypes + ) + + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_compile_options(${TARGET}-tinyusb PRIVATE + -Wno-error=strict-prototypes + ) + + # Link dependencies + target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + + # Flashing + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/max32666/family.mk b/hw/bsp/max32666/family.mk new file mode 100644 index 000000000..d35b6d508 --- /dev/null +++ b/hw/bsp/max32666/family.mk @@ -0,0 +1,104 @@ +DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32 + +# Important locations in the hw support for MCU +MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS +MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers + +# Add any board specific make rules +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 +PORT ?= 0 + +# GCC +SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S +LD_FILE = $(FAMILY_PATH)/max32666.ld + +# IAR +#SRC_S_IAR += ? + +# -------------- +# Compiler Flags +# -------------- +# Flags for the MAX32665/6 SDK +CFLAGS += -DTARGET=MAX32665 \ + -DTARGET_REV=0x4131 \ + -DMXC_ASSERT_ENABLE \ + -DMAX32665 \ + -DIAR_PRAGMAS=0 + +# Flags for TUSB features +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_MAX32666 \ + -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + +# mcu driver cause following warnings +CFLAGS += -Wno-error=strict-prototypes \ + -Wno-error=unused-parameter \ + -Wno-error=cast-align \ + -Wno-error=cast-qual \ +# +# -Wno-error=old-style-declaration \ +# -Wno-error=sign-compare \ +# -Wno-error=cast-qual \ +# -Wno-lto-type-mismatch + +LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs + +# For flash-jlink target +JLINK_DEVICE = max32666 + +# flash target using Jlik +flash: flash-jlink + +# Optional flash option when running within an installed MSDK to use OpenOCD +# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. +# If the MSDK is installed, flash-msdk can be run to utilize the the modified +# openocd with the algorithms +MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) +flash-msdk: + $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ + -f interface/cmsis-dap.cfg -f target/max32665.cfg \ + -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" + +# ----------------- +# Sources & Include +# ----------------- +PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source +SRC_C += \ + src/portable/analog/max32/dcd_max32.c \ + $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/heap.c \ + $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/system_max32665.c \ + $(PERIPH_SRC)/SYS/mxc_assert.c \ + $(PERIPH_SRC)/SYS/mxc_delay.c \ + $(PERIPH_SRC)/SYS/mxc_lock.c \ + $(PERIPH_SRC)/SYS/nvic_table.c \ + $(PERIPH_SRC)/SYS/pins_me14.c \ + $(PERIPH_SRC)/SYS/sys_me14.c \ + $(PERIPH_SRC)/FLC/flc_common.c \ + $(PERIPH_SRC)/FLC/flc_me14.c \ + $(PERIPH_SRC)/FLC/flc_reva.c \ + $(PERIPH_SRC)/GPIO/gpio_common.c \ + $(PERIPH_SRC)/GPIO/gpio_me14.c \ + $(PERIPH_SRC)/GPIO/gpio_reva.c \ + $(PERIPH_SRC)/ICC/icc_me14.c \ + $(PERIPH_SRC)/ICC/icc_reva.c \ + $(PERIPH_SRC)/TPU/tpu_me14.c \ + $(PERIPH_SRC)/TPU/tpu_reva.c \ + $(PERIPH_SRC)/UART/uart_common.c \ + $(PERIPH_SRC)/UART/uart_me14.c \ + $(PERIPH_SRC)/UART/uart_reva.c \ + + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(MAX32_CMSIS)/Include \ + $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32665/Include \ + $(TOP)/$(MAX32_PERIPH)/Include/MAX32665 \ + $(PERIPH_SRC)/SYS \ + $(PERIPH_SRC)/GPIO \ + $(PERIPH_SRC)/ICC \ + $(PERIPH_SRC)/FLC \ + $(PERIPH_SRC)/TPU \ + $(PERIPH_SRC)/UART diff --git a/hw/bsp/max32666/max32666.ld b/hw/bsp/max32666/max32666.ld new file mode 100644 index 000000000..dcf61a3d0 --- /dev/null +++ b/hw/bsp/max32666/max32666.ld @@ -0,0 +1,135 @@ +/* SPID and SPIX Sections here are maximum possible sizes */ +/* If used, they should be adjusted for the external Flash/RAM size */ +MEMORY { + + SPIX (rx) : ORIGIN = 0x08000000, LENGTH = 0x08000000 + FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00100000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x0008C000 + SPID (rw) : ORIGIN = 0x80000000, LENGTH = 512M +} + +/* Sections Definitions */ +SECTIONS { + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) /* program code */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + /* This section will keep the SPIX data until loaded into the external device */ + /* Upon initialization of SPIX (user code needs to do this) */ + .xip_section : + { + KEEP(*(.xip_section*)) + } > SPIX AT>FLASH + + __load_start_xip = LOADADDR(.xip_section); + __load_length_xip = SIZEOF(.xip_section); + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + *(vtable) + *(.data*) /*read-write initialized data: initialized global variable*/ + *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ + *(.flashprog*) /* Flash program */ + + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + /* Setup the stack for Core 1, it will only be used if the user code + * includes a definition of Stack_Size_Core1, which defines the space + * reserved above the main core's stack for core 1's stack */ + + __StackTop_Core1 = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit_Core1 = DEFINED(Stack_Size_Core1) ? __StackTop_Core1 - Stack_Size_Core1 : __StackTop_Core1; + + /* Set stack top to end of RAM, and stack limit move down by Stack_Size. + * If core 1 is used, set the stack to the bottom of Core 1's stack region */ + + __StackTop = DEFINED(Stack_Size_Core1) ? __StackLimit_Core1 : ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - Stack_Size; + + .heap (COPY): + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack(s) exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") +} -- cgit v1.3.1 From 0c37f93bc850a881327714997ec1bfeaf69173ed Mon Sep 17 00:00:00 2001 From: Brent Kowal Date: Tue, 2 Jul 2024 18:02:11 -0400 Subject: MAX32650/1/2 Support Added support for the MAX32650/1/2 series parts - MAX32650FTHR, MAX32650EvKit, MAX32651EvKit - Added special flash rule for MAX32651 due to signing required - Added depencies to flash-msdk rules for executable --- hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h | 149 +++++++++++++++++++++ hw/bsp/max32650/boards/max32650evkit/board.cmake | 1 + hw/bsp/max32650/boards/max32650evkit/board.h | 56 ++++++++ hw/bsp/max32650/boards/max32650evkit/board.mk | 17 +++ hw/bsp/max32650/boards/max32650evkit/max32650.ld | 119 +++++++++++++++++ hw/bsp/max32650/boards/max32650fthr/board.cmake | 1 + hw/bsp/max32650/boards/max32650fthr/board.h | 57 ++++++++ hw/bsp/max32650/boards/max32650fthr/board.mk | 17 +++ hw/bsp/max32650/boards/max32650fthr/max32650.ld | 119 +++++++++++++++++ hw/bsp/max32650/boards/max32651evkit/board.cmake | 1 + hw/bsp/max32650/boards/max32651evkit/board.h | 56 ++++++++ hw/bsp/max32650/boards/max32651evkit/board.mk | 42 ++++++ hw/bsp/max32650/boards/max32651evkit/max32651.ld | 132 +++++++++++++++++++ hw/bsp/max32650/family.c | 160 +++++++++++++++++++++++ hw/bsp/max32650/family.cmake | 152 +++++++++++++++++++++ hw/bsp/max32650/family.mk | 85 ++++++++++++ hw/bsp/max32666/boards/max32666fthr/board.h | 2 +- hw/bsp/max32666/family.mk | 10 +- hw/bsp/max32690/family.mk | 2 +- hw/bsp/max78002/family.mk | 2 +- 20 files changed, 1169 insertions(+), 11 deletions(-) create mode 100644 hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/max32650/boards/max32650evkit/board.cmake create mode 100644 hw/bsp/max32650/boards/max32650evkit/board.h create mode 100644 hw/bsp/max32650/boards/max32650evkit/board.mk create mode 100644 hw/bsp/max32650/boards/max32650evkit/max32650.ld create mode 100644 hw/bsp/max32650/boards/max32650fthr/board.cmake create mode 100644 hw/bsp/max32650/boards/max32650fthr/board.h create mode 100644 hw/bsp/max32650/boards/max32650fthr/board.mk create mode 100644 hw/bsp/max32650/boards/max32650fthr/max32650.ld create mode 100644 hw/bsp/max32650/boards/max32651evkit/board.cmake create mode 100644 hw/bsp/max32650/boards/max32651evkit/board.h create mode 100644 hw/bsp/max32650/boards/max32651evkit/board.mk create mode 100644 hw/bsp/max32650/boards/max32651evkit/max32651.ld create mode 100644 hw/bsp/max32650/family.c create mode 100644 hw/bsp/max32650/family.cmake create mode 100644 hw/bsp/max32650/family.mk (limited to 'hw') diff --git a/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..e5a76af85 --- /dev/null +++ b/hw/bsp/max32650/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,149 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "mxc_device.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS __NVIC_PRIO_BITS + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1< FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + *(vtable) + *(.data*) /*read-write initialized data: initialized global variable*/ + *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ + *(.flashprog*) /* Flash program */ + + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") +} diff --git a/hw/bsp/max32650/boards/max32650fthr/board.cmake b/hw/bsp/max32650/boards/max32650fthr/board.cmake new file mode 100644 index 000000000..a9ce39b4d --- /dev/null +++ b/hw/bsp/max32650/boards/max32650fthr/board.cmake @@ -0,0 +1 @@ +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32650.ld) diff --git a/hw/bsp/max32650/boards/max32650fthr/board.h b/hw/bsp/max32650/boards/max32650fthr/board.h new file mode 100644 index 000000000..d80a8fcae --- /dev/null +++ b/hw/bsp/max32650/boards/max32650fthr/board.h @@ -0,0 +1,57 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "gpio.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// LED +#define LED_PORT MXC_GPIO1 +#define LED_PIN MXC_GPIO_PIN_14 +#define LED_VDDIO MXC_GPIO_VSSEL_VDDIO +#define LED_STATE_ON 0 + +// Button +#define BUTTON_PORT MXC_GPIO1 +#define BUTTON_PIN MXC_GPIO_PIN_19 +#define BUTTON_PULL MXC_GPIO_PAD_WEAK_PULL_UP +#define BUTTON_STATE_ACTIVE 0 + +// UART Enable for SWD UART Pins. Pin Mux handled by the HAL +#define UART_NUM 0 + + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/max32650/boards/max32650fthr/board.mk b/hw/bsp/max32650/boards/max32650fthr/board.mk new file mode 100644 index 000000000..c6f018810 --- /dev/null +++ b/hw/bsp/max32650/boards/max32650fthr/board.mk @@ -0,0 +1,17 @@ +LD_FILE = $(BOARD_PATH)/max32650.ld + +# For flash-jlink target +JLINK_DEVICE = max32650 + +# flash target using Jlik +flash: flash-jlink + +# Optional flash option when running within an installed MSDK to use OpenOCD +# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. +# If the MSDK is installed, flash-msdk can be run to utilize the the modified +# openocd with the algorithms +MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) +flash-msdk: $(BUILD)/$(PROJECT).elf + $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ + -f interface/cmsis-dap.cfg -f target/max32650.cfg \ + -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" diff --git a/hw/bsp/max32650/boards/max32650fthr/max32650.ld b/hw/bsp/max32650/boards/max32650fthr/max32650.ld new file mode 100644 index 000000000..3a1e5100d --- /dev/null +++ b/hw/bsp/max32650/boards/max32650fthr/max32650.ld @@ -0,0 +1,119 @@ +MEMORY { + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64kB ROM */ + FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00300000 /* 3MB flash */ + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 /* 1MB SRAM */ +} + +SECTIONS { + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) /* program code */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + *(vtable) + *(.data*) /*read-write initialized data: initialized global variable*/ + *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ + *(.flashprog*) /* Flash program */ + + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") +} diff --git a/hw/bsp/max32650/boards/max32651evkit/board.cmake b/hw/bsp/max32650/boards/max32651evkit/board.cmake new file mode 100644 index 000000000..8bb3e6edd --- /dev/null +++ b/hw/bsp/max32650/boards/max32651evkit/board.cmake @@ -0,0 +1 @@ +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32651.ld) \ No newline at end of file diff --git a/hw/bsp/max32650/boards/max32651evkit/board.h b/hw/bsp/max32650/boards/max32651evkit/board.h new file mode 100644 index 000000000..196abdaca --- /dev/null +++ b/hw/bsp/max32650/boards/max32651evkit/board.h @@ -0,0 +1,56 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "gpio.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// LED +#define LED_PORT MXC_GPIO2 +#define LED_PIN MXC_GPIO_PIN_25 +#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH +#define LED_STATE_ON 0 + +// Button +#define BUTTON_PORT MXC_GPIO2 +#define BUTTON_PIN MXC_GPIO_PIN_28 +#define BUTTON_PULL MXC_GPIO_PAD_WEAK_PULL_UP +#define BUTTON_STATE_ACTIVE 0 + +// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL +#define UART_NUM 0 + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/max32650/boards/max32651evkit/board.mk b/hw/bsp/max32650/boards/max32651evkit/board.mk new file mode 100644 index 000000000..8d13d8edf --- /dev/null +++ b/hw/bsp/max32650/boards/max32651evkit/board.mk @@ -0,0 +1,42 @@ +LD_FILE = $(BOARD_PATH)/max32651.ld +CFLAGS += -D__SLA_FWK__ + +# For flash-jlink target +JLINK_DEVICE = max32650 + +# flash target using MSDK signing the image +flash: flash-msdk-signed + + +MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) + +# The MAX32651EVKIT is pin for pin identical to the MAX32650EVKIT, however the +# MAX32651 has a secure bootloader which requires the image to be signed before +# loading into flash. All MAX32651EVKIT's have the same key for evaluation +# purposes, so create a special flash rule to sign the binary and flash using +# the MSDK. +# For the MAX32650, the regular flash, flash-jlink and flash-msdk are sufficient +MCU_PATH = $(TOP)/hw/mcu/analog/max32/ +# Assume no extension for sign utility +SIGN_EXE = sign_app +ifeq ($(OS), Windows_NT) +# Must use .exe extension on Windows, since the binaries +# for Linux may live in the same place. +SIGN_EXE := sign_app.exe +else +UNAME = $(shell uname -s) +ifneq ($(findstring MSYS_NT,$(UNAME)),) +# Must also use .exe extension for MSYS2 +SIGN_EXE := sign_app.exe +endif +endif + +flash-msdk-signed: $(BUILD)/$(PROJECT).elf + $(OBJCOPY) $(BUILD)/$(PROJECT).elf -R .sig -O binary $(BUILD)/$(PROJECT).bin + $(MCU_PATH)/Tools/SBT/bin/$(SIGN_EXE) -c MAX32651 key_file="$(MCU_PATH)/Tools/SBT/devices/MAX32651/keys/maximtestcrk.key" \ + ca=$(BUILD)/$(PROJECT).bin sca=$(BUILD)/$(PROJECT).sbin + $(OBJCOPY) $(BUILD)/$(PROJECT).elf --update-section .sig=$(BUILD)/$(PROJECT).sig + $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ + -f interface/cmsis-dap.cfg -f target/max32650.cfg \ + -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" + diff --git a/hw/bsp/max32650/boards/max32651evkit/max32651.ld b/hw/bsp/max32650/boards/max32651evkit/max32651.ld new file mode 100644 index 000000000..a873463d4 --- /dev/null +++ b/hw/bsp/max32650/boards/max32651evkit/max32651.ld @@ -0,0 +1,132 @@ +MEMORY { + HEADER (rx): ORIGIN = 0x10000000, LENGTH = 0x200 + FLASH (rx) : ORIGIN = 0x10000200, LENGTH = 0x002FFE00 /* 3MB flash */ + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 /* 1MB SRAM */ +} + +/* Added Oct 9, 2018 to go to correct reset vector. */ +ENTRY(Reset_Handler) +PROVIDE( _start_SWAP = (((Reset_Handler) >> 24) | (((Reset_Handler) & 0x00FF0000) >> 8) | (((Reset_Handler) & 0x0000FF00) << 8) | ((Reset_Handler) << 24))); +PROVIDE_HIDDEN( _SLA_Size = _endimage - __end_header ); +PROVIDE( _SLA_Size_SWAP = (((_SLA_Size) >> 24) | (((_SLA_Size) & 0x00FF0000) >> 8) | (((_SLA_Size) & 0x0000FF00) << 8) | ((_SLA_Size) << 24))); + +/* Sections Definitions */ +SECTIONS { + .sb_sla_header : ALIGN(4) + { + FILL(0xFF) + KEEP(*(.sb_sla_header)) /* Header for ROM code */ + __end_header = . ; + . = ALIGN(512); + } > HEADER + + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) /* program code */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + *(.data*) /*read-write initialized data: initialized global variable*/ + *(.spix_config*) /* SPIX configuration functions need to be run from SRAM */ + *(.flashprog*) /* Flash program */ + + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + _enddata = LOADADDR(.data)+SIZEOF(.data); + + .sb_sla_trailer : AT(_enddata) + { + KEEP(*(.sb_sla_trailer)) + /* Align image with 16 byte boundary to conform to flash encryption block size. */ + FILL(0xDEADC0DE); + /* NOTE: The FILL and ALIGN will not work unless something is written to the section. So, we use LONG. */ + LONG(0xDEADC0DE); + . = ALIGN(16); + } > FLASH + _endimage = LOADADDR(.sb_sla_trailer)+SIZEOF(.sb_sla_trailer); + .sig : + { + KEEP(*(.sig)) + LONG(0xDEADBEEF); + + } > FLASH + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") +} diff --git a/hw/bsp/max32650/family.c b/hw/bsp/max32650/family.c new file mode 100644 index 000000000..16b5233b9 --- /dev/null +++ b/hw/bsp/max32650/family.c @@ -0,0 +1,160 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "board.h" +#include "bsp/board_api.h" +#include "gpio.h" +#include "mxc_device.h" +#include "uart.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB_IRQHandler(void) { + tud_int_handler(0); +} + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ +mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(UART_NUM); + +void board_init(void) { +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + mxc_gpio_cfg_t gpioConfig; + + // LED + gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; + gpioConfig.func = MXC_GPIO_FUNC_OUT; + gpioConfig.mask = LED_PIN; + gpioConfig.pad = MXC_GPIO_PAD_NONE; + gpioConfig.port = LED_PORT; + gpioConfig.vssel = LED_VDDIO; + MXC_GPIO_Config(&gpioConfig); + board_led_write(false); + + // Button + gpioConfig.drvstr = MXC_GPIO_DRVSTR_0; + gpioConfig.func = MXC_GPIO_FUNC_IN; + gpioConfig.mask = BUTTON_PIN; + gpioConfig.pad = BUTTON_PULL; + gpioConfig.port = BUTTON_PORT; + gpioConfig.vssel = MXC_GPIO_VSSEL_VDDIO; + MXC_GPIO_Config(&gpioConfig); + + // UART + MXC_UART_Init(ConsoleUart, CFG_BOARD_UART_BAUDRATE); + + //USB + // Startup the HIRC96M clock if it's not on already + if (!(MXC_GCR->clk_ctrl & MXC_F_GCR_CLK_CTRL_HIRC96_EN)) { + MXC_GCR->clk_ctrl |= MXC_F_GCR_CLK_CTRL_HIRC96_EN; + MXC_SYS_Clock_Timeout(MXC_F_GCR_CLK_CTRL_HIRC96_RDY); + } + + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) { +#if LED_STATE_ON + state = !state; +#endif + if (state) { + MXC_GPIO_OutClr(LED_PORT, LED_PIN); + } else { + MXC_GPIO_OutSet(LED_PORT, LED_PIN); + } +} + +uint32_t board_button_read(void) { + uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0; + return BUTTON_STATE_ACTIVE == state; +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + uint8_t hw_id[13];//USN Buffer + MXC_SYS_GetUSN(hw_id, 13); + + size_t act_len = TU_MIN(max_len, 13); + memcpy(id, hw_id, act_len); + return act_len; +} + +int board_uart_read(uint8_t *buf, int len) { + int uart_val; + int act_len = 0; + + while (act_len < len) { + if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { + break; + } else { + *buf++ = (uint8_t) uart_val; + act_len++; + } + } + return act_len; +} + +int board_uart_write(void const *buf, int len) { + int act_len = 0; + const uint8_t *ch_ptr = (const uint8_t *) buf; + while (act_len < len) { + MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++); + act_len++; + } + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) { + system_ticks++; +} + +uint32_t board_millis(void) { + return system_ticks; +} +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake new file mode 100644 index 000000000..764356495 --- /dev/null +++ b/hw/bsp/max32650/family.cmake @@ -0,0 +1,152 @@ +include_guard() + +set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers) +set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS) +set(CMSIS_5 ${TOP}/lib/CMSIS_5) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# Get the linker file from current location (family) +set(LD_FILE_Clang ${LD_FILE_GNU}) + +# toolchain set up +set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) +set(JLINK_DEVICE max32650) + +set(FAMILY_MCUS MAX32650 CACHE INTERNAL "") + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + TARGET=MAX32650 + TARGET_REV=0x4131 + MXC_ASSERT_ENABLE + MAX32650 + IAR_PRAGMAS=0 + CFG_TUSB_MCU=OPT_MCU_MAX32650 + BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + ) +endfunction() + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/GCC/startup_max32650.S) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + #set(STARTUP_FILE_IAR ?) + + set(PERIPH_SRC ${MAX32_PERIPH}/Source) + add_library(${BOARD_TARGET} STATIC + ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/heap.c + ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/system_max32650.c + ${PERIPH_SRC}/SYS/mxc_assert.c + ${PERIPH_SRC}/SYS/mxc_delay.c + ${PERIPH_SRC}/SYS/mxc_lock.c + ${PERIPH_SRC}/SYS/nvic_table.c + ${PERIPH_SRC}/SYS/pins_me10.c + ${PERIPH_SRC}/SYS/sys_me10.c + ${PERIPH_SRC}/TPU/tpu_me10.c + ${PERIPH_SRC}/TPU/tpu_reva.c + ${PERIPH_SRC}/FLC/flc_common.c + ${PERIPH_SRC}/FLC/flc_me10.c + ${PERIPH_SRC}/FLC/flc_reva.c + ${PERIPH_SRC}/GPIO/gpio_common.c + ${PERIPH_SRC}/GPIO/gpio_me10.c + ${PERIPH_SRC}/GPIO/gpio_reva.c + ${PERIPH_SRC}/ICC/icc_me10.c + ${PERIPH_SRC}/ICC/icc_reva.c + ${PERIPH_SRC}/ICC/icc_common.c + ${PERIPH_SRC}/UART/uart_common.c + ${PERIPH_SRC}/UART/uart_me10.c + ${PERIPH_SRC}/UART/uart_reva.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMSIS_5}/CMSIS/Core/Include + ${MAX32_CMSIS}/Include + ${MAX32_CMSIS}/Device/Maxim/MAX32650/Include + ${MAX32_PERIPH}/Include/MAX32650 + ${PERIPH_SRC}/SYS + ${PERIPH_SRC}/GPIO + ${PERIPH_SRC}/TPU + ${PERIPH_SRC}/ICC + ${PERIPH_SRC}/FLC + ${PERIPH_SRC}/UART + ) + + target_compile_options(${BOARD_TARGET} PRIVATE + -Wno-error=strict-prototypes + ) + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_MAX32650 ${RTOS}) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/analog/max32/dcd_max32.c + ) + target_compile_options(${TARGET} PRIVATE + -Wno-error=strict-prototypes + ) + + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_compile_options(${TARGET}-tinyusb PRIVATE + -Wno-error=strict-prototypes + ) + + # Link dependencies + target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + + # Flashing + family_flash_jlink(${TARGET}) +endfunction() + diff --git a/hw/bsp/max32650/family.mk b/hw/bsp/max32650/family.mk new file mode 100644 index 000000000..6e9b7b835 --- /dev/null +++ b/hw/bsp/max32650/family.mk @@ -0,0 +1,85 @@ +DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32 + +# Important locations in the hw support for MCU +MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS +MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers + +# Add any board specific make rules +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 +PORT ?= 0 + +# GCC +SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/GCC/startup_max32650.S + +# IAR +#SRC_S_IAR += ? + +# -------------- +# Compiler Flags +# -------------- +# Flags for the MAX32650/1/2 SDK +CFLAGS += -DTARGET=MAX32650 \ + -DTARGET_REV=0x4131 \ + -DMXC_ASSERT_ENABLE \ + -DMAX32650 \ + -DIAR_PRAGMAS=0 + +# Flags for TUSB features +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_MAX32650 \ + -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + +# mcu driver cause following warnings +CFLAGS += -Wno-error=strict-prototypes \ + -Wno-error=unused-parameter \ + -Wno-error=cast-align \ + -Wno-error=cast-qual \ + -Wno-error=sign-compare + +LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs + +# ----------------- +# Sources & Include +# ----------------- +PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source +SRC_C += \ + src/portable/analog/max32/dcd_max32.c \ + $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/heap.c \ + $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/system_max32650.c \ + $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/header_MAX32650.c \ + $(PERIPH_SRC)/SYS/mxc_assert.c \ + $(PERIPH_SRC)/SYS/mxc_delay.c \ + $(PERIPH_SRC)/SYS/mxc_lock.c \ + $(PERIPH_SRC)/SYS/nvic_table.c \ + $(PERIPH_SRC)/SYS/pins_me10.c \ + $(PERIPH_SRC)/SYS/sys_me10.c \ + $(PERIPH_SRC)/FLC/flc_common.c \ + $(PERIPH_SRC)/FLC/flc_me10.c \ + $(PERIPH_SRC)/FLC/flc_reva.c \ + $(PERIPH_SRC)/GPIO/gpio_common.c \ + $(PERIPH_SRC)/GPIO/gpio_me10.c \ + $(PERIPH_SRC)/GPIO/gpio_reva.c \ + $(PERIPH_SRC)/ICC/icc_me10.c \ + $(PERIPH_SRC)/ICC/icc_reva.c \ + $(PERIPH_SRC)/ICC/icc_common.c \ + $(PERIPH_SRC)/TPU/tpu_me10.c \ + $(PERIPH_SRC)/TPU/tpu_reva.c \ + $(PERIPH_SRC)/UART/uart_common.c \ + $(PERIPH_SRC)/UART/uart_me10.c \ + $(PERIPH_SRC)/UART/uart_reva.c \ + + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(MAX32_CMSIS)/Include \ + $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32650/Include \ + $(TOP)/$(MAX32_PERIPH)/Include/MAX32650 \ + $(PERIPH_SRC)/SYS \ + $(PERIPH_SRC)/GPIO \ + $(PERIPH_SRC)/ICC \ + $(PERIPH_SRC)/FLC \ + $(PERIPH_SRC)/TPU \ + $(PERIPH_SRC)/UART diff --git a/hw/bsp/max32666/boards/max32666fthr/board.h b/hw/bsp/max32666/boards/max32666fthr/board.h index 7e24266a1..c719b748a 100644 --- a/hw/bsp/max32666/boards/max32666fthr/board.h +++ b/hw/bsp/max32666/boards/max32666fthr/board.h @@ -46,7 +46,7 @@ extern "C" { #define BUTTON_PULL MXC_GPIO_PAD_PULL_UP #define BUTTON_STATE_ACTIVE 0 -// UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL +// UART Enable for UART on SWD. Pin Mux handled by the HAL #define UART_NUM 1 #define UART_MAP MAP_B diff --git a/hw/bsp/max32666/family.mk b/hw/bsp/max32666/family.mk index d35b6d508..31428cacd 100644 --- a/hw/bsp/max32666/family.mk +++ b/hw/bsp/max32666/family.mk @@ -36,13 +36,7 @@ CFLAGS += \ CFLAGS += -Wno-error=strict-prototypes \ -Wno-error=unused-parameter \ -Wno-error=cast-align \ - -Wno-error=cast-qual \ -# -# -Wno-error=old-style-declaration \ -# -Wno-error=sign-compare \ -# -Wno-error=cast-qual \ -# -Wno-lto-type-mismatch - + -Wno-error=cast-qual LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs # For flash-jlink target @@ -56,7 +50,7 @@ flash: flash-jlink # If the MSDK is installed, flash-msdk can be run to utilize the the modified # openocd with the algorithms MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) -flash-msdk: +flash-msdk: $(BUILD)/$(PROJECT).elf $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ -f interface/cmsis-dap.cfg -f target/max32665.cfg \ -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" diff --git a/hw/bsp/max32690/family.mk b/hw/bsp/max32690/family.mk index 08d5e8671..0405a2914 100644 --- a/hw/bsp/max32690/family.mk +++ b/hw/bsp/max32690/family.mk @@ -57,7 +57,7 @@ flash: flash-jlink # If the MSDK is installed, flash-msdk can be run to utilize the the modified # openocd with the algorithms MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) -flash-msdk: +flash-msdk: $(BUILD)/$(PROJECT).elf $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ -f interface/cmsis-dap.cfg -f target/max32690.cfg \ -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" diff --git a/hw/bsp/max78002/family.mk b/hw/bsp/max78002/family.mk index 825920596..04163417c 100644 --- a/hw/bsp/max78002/family.mk +++ b/hw/bsp/max78002/family.mk @@ -53,7 +53,7 @@ flash: flash-jlink # If the MSDK is installed, flash-msdk can be run to utilize the the modified # openocd with the algorithms MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) -flash-msdk: +flash-msdk: $(BUILD)/$(PROJECT).elf $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ -f interface/cmsis-dap.cfg -f target/max78002.cfg \ -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" -- cgit v1.3.1 From f49725d2c958dd1368b5ca191a00be72543c0752 Mon Sep 17 00:00:00 2001 From: Brent Kowal Date: Wed, 10 Jul 2024 15:18:59 -0400 Subject: BSP Cleanup - Added MSDK flash rules for CMake - Removed partial IAR support. Uniform GCC support across MAX32 parts - Updated build scripts for correctly signing the MAX32651 - Added README files for the BSPs to describe flashing and limitiations --- hw/bsp/max32650/README.md | 46 +++++++++++++++++ hw/bsp/max32650/boards/max32650evkit/board.cmake | 11 +++- hw/bsp/max32650/boards/max32650evkit/board.mk | 17 +------ hw/bsp/max32650/boards/max32650fthr/board.cmake | 9 ++++ hw/bsp/max32650/boards/max32650fthr/board.mk | 17 +------ hw/bsp/max32650/boards/max32651evkit/board.cmake | 31 +++++++++++- hw/bsp/max32650/boards/max32651evkit/board.mk | 43 ++-------------- hw/bsp/max32650/family.cmake | 32 +++++++++--- hw/bsp/max32650/family.mk | 64 ++++++++++++++++++++++-- hw/bsp/max32666/README.md | 32 ++++++++++++ hw/bsp/max32666/family.cmake | 19 +++++-- hw/bsp/max32666/family.mk | 6 +-- hw/bsp/max32690/README.md | 31 ++++++++++++ hw/bsp/max32690/family.cmake | 21 +++++--- hw/bsp/max32690/family.mk | 6 +-- hw/bsp/max78002/README.md | 28 +++++++++++ hw/bsp/max78002/family.cmake | 27 ++++++---- hw/bsp/max78002/family.mk | 6 +-- 18 files changed, 325 insertions(+), 121 deletions(-) create mode 100644 hw/bsp/max32650/README.md create mode 100644 hw/bsp/max32666/README.md create mode 100644 hw/bsp/max32690/README.md create mode 100644 hw/bsp/max78002/README.md (limited to 'hw') diff --git a/hw/bsp/max32650/README.md b/hw/bsp/max32650/README.md new file mode 100644 index 000000000..cb8069bba --- /dev/null +++ b/hw/bsp/max32650/README.md @@ -0,0 +1,46 @@ +# Analog Devices MAX32650/1/2 + +This BSP is for working with the Analog Devices +[MAX32650](https://www.analog.com/en/products/max32650.html), +[MAX32651](https://www.analog.com/en/products/max32651.html) and +[MAX32652](https://www.analog.com/en/products/max32652.html) +microcontrollers. The following boards are supported: + * [MAX32650EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html) + * [MAX32650FTHR](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html) + * [MAX32651EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32651-evkit.html) (Secure Bootloader) + +This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device +interfaces and hardware abstraction layers. This source code package is fetched +as part of the get-deps script. + +The microcontrollers utilize the standard GNU ARM toolchain. If this toolchain +is not already available on your build machine, it can be installed by using the +bundled MSDK installation. Details on downloading and installing can be found +in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/). + +## Flashing + +### MAX32650 and MAX32652 + +The default flashing behavior in this BSP for the MAX32650 and MAX32652 is to +utilize JLink. This can be done by running the `flash` or `flash-jlink` rule +for Makefiles, or the `-jlink` target for CMake. + +Both the Evaluation Kit and Feather boards are shipped with a CMSIS-DAP +compatible debug probe. However, at the time of writing, the necessary flashing +algorithms for OpenOCD have not yet been incorporated into the OpenOCD master +branch. To utilize the provided debug probes, please install the bundled MSDK +package which includes the appropriate OpenOCD modifications. To leverage this +OpenOCD instance, run the `flash-msdk` Makefile rule, or `-msdk` CMake +target. + +### MAX32651 + +The MAX32651 features an integrated secure bootloader which requires the +application image be signed prior to flashing. Both the Makefile and CMake +scripts account for this signing automatically when building for the +MAX32651EVKIT. + +To flash the signed image, the MSDK's OpenOCD variant must be used. To flash +the MAX32651EVKIT please install the bundled MSDK, and utilize the `flash-msdk` +and `-msdk` rule and target. \ No newline at end of file diff --git a/hw/bsp/max32650/boards/max32650evkit/board.cmake b/hw/bsp/max32650/boards/max32650evkit/board.cmake index e094b89e1..fffdcc9fb 100644 --- a/hw/bsp/max32650/boards/max32650evkit/board.cmake +++ b/hw/bsp/max32650/boards/max32650evkit/board.cmake @@ -1 +1,10 @@ -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32650.ld) \ No newline at end of file +# Use the standard, non-secure linker file +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32650.ld) + +function(update_board_extras TARGET) + #No extra arguments +endfunction() + +function(prepare_image TARGET_IN) + #No signing required +endfunction() diff --git a/hw/bsp/max32650/boards/max32650evkit/board.mk b/hw/bsp/max32650/boards/max32650evkit/board.mk index ad7125573..0bc210e11 100644 --- a/hw/bsp/max32650/boards/max32650evkit/board.mk +++ b/hw/bsp/max32650/boards/max32650evkit/board.mk @@ -1,17 +1,2 @@ +# Use the standard, non-secure linker file LD_FILE = $(BOARD_PATH)/max32650.ld - -# For flash-jlink target -JLINK_DEVICE = max32650 - -# flash target using Jlik -flash: flash-jlink - -# Optional flash option when running within an installed MSDK to use OpenOCD -# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. -# If the MSDK is installed, flash-msdk can be run to utilize the the modified -# openocd with the algorithms -MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) -flash-msdk: $(BUILD)/$(PROJECT).elf - $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ - -f interface/cmsis-dap.cfg -f target/max32650.cfg \ - -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" \ No newline at end of file diff --git a/hw/bsp/max32650/boards/max32650fthr/board.cmake b/hw/bsp/max32650/boards/max32650fthr/board.cmake index a9ce39b4d..fffdcc9fb 100644 --- a/hw/bsp/max32650/boards/max32650fthr/board.cmake +++ b/hw/bsp/max32650/boards/max32650fthr/board.cmake @@ -1 +1,10 @@ +# Use the standard, non-secure linker file set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32650.ld) + +function(update_board_extras TARGET) + #No extra arguments +endfunction() + +function(prepare_image TARGET_IN) + #No signing required +endfunction() diff --git a/hw/bsp/max32650/boards/max32650fthr/board.mk b/hw/bsp/max32650/boards/max32650fthr/board.mk index c6f018810..0bc210e11 100644 --- a/hw/bsp/max32650/boards/max32650fthr/board.mk +++ b/hw/bsp/max32650/boards/max32650fthr/board.mk @@ -1,17 +1,2 @@ +# Use the standard, non-secure linker file LD_FILE = $(BOARD_PATH)/max32650.ld - -# For flash-jlink target -JLINK_DEVICE = max32650 - -# flash target using Jlik -flash: flash-jlink - -# Optional flash option when running within an installed MSDK to use OpenOCD -# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. -# If the MSDK is installed, flash-msdk can be run to utilize the the modified -# openocd with the algorithms -MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) -flash-msdk: $(BUILD)/$(PROJECT).elf - $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ - -f interface/cmsis-dap.cfg -f target/max32650.cfg \ - -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" diff --git a/hw/bsp/max32650/boards/max32651evkit/board.cmake b/hw/bsp/max32650/boards/max32651evkit/board.cmake index 8bb3e6edd..bd8077a42 100644 --- a/hw/bsp/max32650/boards/max32651evkit/board.cmake +++ b/hw/bsp/max32650/boards/max32651evkit/board.cmake @@ -1 +1,30 @@ -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32651.ld) \ No newline at end of file +# Use the secure linker file +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32651.ld) + +function(update_board_extras TARGET) + # for the signed target, need to add the __SLA_FWK__ define + target_compile_definitions(${TARGET} PUBLIC + __SLA_FWK__ + ) +endfunction() + +function(prepare_image TARGET_IN) + #For the signed target, set up a POST_BUILD command to sign the elf file once + #created + if((WIN32) OR (MINGW) OR (MSYS)) + set(SIGN_EXE "sign_app.exe") + else() + set(SIGN_EXE "sign_app") + endif() + set(MCU_PATH "${TOP}/hw/mcu/analog/max32/") + + # Custom POST_BUILD command + add_custom_command( + TARGET ${TARGET_IN} POST_BUILD + COMMAND ${CMAKE_OBJCOPY} $ -R .sig -O binary $/${TARGET_IN}.bin + COMMAND ${MCU_PATH}/Tools/SBT/bin/${SIGN_EXE} -c MAX32651 key_file=${MCU_PATH}/Tools/SBT/devices/MAX32651/keys/maximtestcrk.key + ca=$/${TARGET_IN}.bin sca=$/${TARGET_IN}.sbin + COMMAND ${CMAKE_OBJCOPY} $ --update-section .sig=$/${TARGET_IN}.sig + VERBATIM + ) +endfunction() diff --git a/hw/bsp/max32650/boards/max32651evkit/board.mk b/hw/bsp/max32650/boards/max32651evkit/board.mk index 8d13d8edf..b609598c1 100644 --- a/hw/bsp/max32650/boards/max32651evkit/board.mk +++ b/hw/bsp/max32650/boards/max32651evkit/board.mk @@ -1,42 +1,5 @@ +# Use the secure linker file LD_FILE = $(BOARD_PATH)/max32651.ld -CFLAGS += -D__SLA_FWK__ - -# For flash-jlink target -JLINK_DEVICE = max32650 - -# flash target using MSDK signing the image -flash: flash-msdk-signed - - -MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) - -# The MAX32651EVKIT is pin for pin identical to the MAX32650EVKIT, however the -# MAX32651 has a secure bootloader which requires the image to be signed before -# loading into flash. All MAX32651EVKIT's have the same key for evaluation -# purposes, so create a special flash rule to sign the binary and flash using -# the MSDK. -# For the MAX32650, the regular flash, flash-jlink and flash-msdk are sufficient -MCU_PATH = $(TOP)/hw/mcu/analog/max32/ -# Assume no extension for sign utility -SIGN_EXE = sign_app -ifeq ($(OS), Windows_NT) -# Must use .exe extension on Windows, since the binaries -# for Linux may live in the same place. -SIGN_EXE := sign_app.exe -else -UNAME = $(shell uname -s) -ifneq ($(findstring MSYS_NT,$(UNAME)),) -# Must also use .exe extension for MSYS2 -SIGN_EXE := sign_app.exe -endif -endif - -flash-msdk-signed: $(BUILD)/$(PROJECT).elf - $(OBJCOPY) $(BUILD)/$(PROJECT).elf -R .sig -O binary $(BUILD)/$(PROJECT).bin - $(MCU_PATH)/Tools/SBT/bin/$(SIGN_EXE) -c MAX32651 key_file="$(MCU_PATH)/Tools/SBT/devices/MAX32651/keys/maximtestcrk.key" \ - ca=$(BUILD)/$(PROJECT).bin sca=$(BUILD)/$(PROJECT).sbin - $(OBJCOPY) $(BUILD)/$(PROJECT).elf --update-section .sig=$(BUILD)/$(PROJECT).sig - $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ - -f interface/cmsis-dap.cfg -f target/max32650.cfg \ - -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" +# Let the family script know the build needs to be signed +SIGNED_BUILD := 1 diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake index 764356495..129d99af8 100644 --- a/hw/bsp/max32650/family.cmake +++ b/hw/bsp/max32650/family.cmake @@ -4,10 +4,10 @@ set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers) set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS) set(CMSIS_5 ${TOP}/lib/CMSIS_5) -# include board specific +# include board specific information and functions include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) -# Get the linker file from current location (family) +# Get the linker file set(LD_FILE_Clang ${LD_FILE_GNU}) # toolchain set up @@ -27,6 +27,9 @@ function(update_board TARGET) CFG_TUSB_MCU=OPT_MCU_MAX32650 BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED ) + + # Run any board specific updates + update_board_extras(${TARGET}) endfunction() #------------------------------------ @@ -41,11 +44,11 @@ function(add_board_target BOARD_TARGET) # Startup & Linker script set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/GCC/startup_max32650.S) set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) - #set(STARTUP_FILE_IAR ?) set(PERIPH_SRC ${MAX32_PERIPH}/Source) add_library(${BOARD_TARGET} STATIC ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/heap.c + ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/header_MAX32650.c ${MAX32_CMSIS}/Device/Maxim/MAX32650/Source/system_max32650.c ${PERIPH_SRC}/SYS/mxc_assert.c ${PERIPH_SRC}/SYS/mxc_delay.c @@ -84,7 +87,7 @@ function(add_board_target BOARD_TARGET) ) target_compile_options(${BOARD_TARGET} PRIVATE - -Wno-error=strict-prototypes + -Wno-error=strict-prototypes ) update_board(${BOARD_TARGET}) @@ -93,15 +96,12 @@ function(add_board_target BOARD_TARGET) "LINKER:--script=${LD_FILE_GNU}" -nostartfiles --specs=nosys.specs --specs=nano.specs + -u sb_header #Needed when linking libraries to not lose the Signing header ) elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_Clang}" ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--config=${LD_FILE_IAR}" - ) endif () endfunction() @@ -148,5 +148,21 @@ function(family_configure_example TARGET RTOS) # Flashing family_flash_jlink(${TARGET}) + + # Add the optional MSDK OpenOCD flashing + family_flash_msdk(${TARGET}) endfunction() +function(family_flash_msdk TARGET) + # Prepare the image (signed) if the board requires it + prepare_image(${TARGET}) + + set(MAXIM_PATH "$ENV{MAXIM_PATH}") + add_custom_target(${TARGET}-msdk + DEPENDS ${TARGET} + COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts + -f interface/cmsis-dap.cfg -f target/max32650.cfg + -c "program $ verify; init; reset; exit" + VERBATIM + ) +endfunction() diff --git a/hw/bsp/max32650/family.mk b/hw/bsp/max32650/family.mk index 6e9b7b835..577d96717 100644 --- a/hw/bsp/max32650/family.mk +++ b/hw/bsp/max32650/family.mk @@ -13,9 +13,6 @@ PORT ?= 0 # GCC SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/GCC/startup_max32650.S -# IAR -#SRC_S_IAR += ? - # -------------- # Compiler Flags # -------------- @@ -40,6 +37,26 @@ CFLAGS += -Wno-error=strict-prototypes \ LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs +# Configure the flash rule. By default, use JLink. +SIGNED_BUILD ?= 0 +DEFAULT_FLASH = flash-jlink + +# If the applications needs to be signed (for the MAX32651), sign it first and +# then need to use MSDK's OpenOCD to flash it +# Also need to include the __SLA_FWK__ define to enable the signed header into +# memory +ifeq ($(SIGNED_BUILD), 1) +# Extra definitions to build for the secure part +CFLAGS += -D__SLA_FWK__ +DEFAULT_FLASH := sign-build flash-msdk +endif + +# For flash-jlink target +JLINK_DEVICE = max32650 + +# Configure the flash rule +flash: $(DEFAULT_FLASH) + # ----------------- # Sources & Include # ----------------- @@ -70,7 +87,6 @@ SRC_C += \ $(PERIPH_SRC)/UART/uart_me10.c \ $(PERIPH_SRC)/UART/uart_reva.c \ - INC += \ $(TOP)/$(BOARD_PATH) \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ @@ -83,3 +99,43 @@ INC += \ $(PERIPH_SRC)/FLC \ $(PERIPH_SRC)/TPU \ $(PERIPH_SRC)/UART + + +# The MAX32651EVKIT is pin for pin identical to the MAX32650EVKIT, however the +# MAX32651 has a secure bootloader which requires the image to be signed before +# loading into flash. All MAX32651EVKIT's have the same key for evaluation +# purposes, so create a special flash rule to sign the binary and flash using +# the MSDK. +MCU_PATH = $(TOP)/hw/mcu/analog/max32/ +# Assume no extension for sign utility +SIGN_EXE = sign_app +ifeq ($(OS), Windows_NT) +# Must use .exe extension on Windows, since the binaries +# for Linux may live in the same place. +SIGN_EXE := sign_app.exe +else +UNAME = $(shell uname -s) +ifneq ($(findstring MSYS_NT,$(UNAME)),) +# Must also use .exe extension for MSYS2 +SIGN_EXE := sign_app.exe +endif +endif + +# Rule to sign the build. This will in-place modifiy the existing .elf file +# an populate the .sig section with the signature value +sign-build: $(BUILD)/$(PROJECT).elf + $(OBJCOPY) $(BUILD)/$(PROJECT).elf -R .sig -O binary $(BUILD)/$(PROJECT).bin + $(MCU_PATH)/Tools/SBT/bin/$(SIGN_EXE) -c MAX32651 \ + key_file="$(MCU_PATH)/Tools/SBT/devices/MAX32651/keys/maximtestcrk.key" \ + ca=$(BUILD)/$(PROJECT).bin sca=$(BUILD)/$(PROJECT).sbin + $(OBJCOPY) $(BUILD)/$(PROJECT).elf --update-section .sig=$(BUILD)/$(PROJECT).sig + +# Optional flash option when running within an installed MSDK to use OpenOCD +# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. +# If the MSDK is installed, flash-msdk can be run to utilize the the modified +# openocd with the algorithms +MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) +flash-msdk: $(BUILD)/$(PROJECT).elf + $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ + -f interface/cmsis-dap.cfg -f target/max32650.cfg \ + -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" diff --git a/hw/bsp/max32666/README.md b/hw/bsp/max32666/README.md new file mode 100644 index 000000000..902d82e25 --- /dev/null +++ b/hw/bsp/max32666/README.md @@ -0,0 +1,32 @@ +# Analog Devices MAX32665/6 + +This BSP is for working with the Analog Devices +[MAX32665](https://www.analog.com/en/products/max32665.html) and +[MAX32666](https://www.analog.com/en/products/max32666.html) microcontrollers. +The following boards are supported: + * [MAX32666EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html) + * [MAX32666FTHR](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html) + + +This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device +interfaces and hardware abstraction layers. This source code package is fetched +as part of the get-deps script. + +The microcontrollers utilize the standard GNU ARM toolchain. If this toolchain +is not already available on your build machine, it can be installed by using the +bundled MSDK installation. Details on downloading and installing can be found +in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/). + +## Flashing + +The default flashing behavior in this BSP is to utilize JLink. This can be done +by running the `flash` or `flash-jlink` rule for Makefiles, or the +`-jlink` target for CMake. + +Both the Evaluation Kit and Feather boards are shipped with a CMSIS-DAP +compatible debug probe. However, at the time of writing, the necessary flashing +algorithms for OpenOCD have not yet been incorporated into the OpenOCD master +branch. To utilize the provided debug probes, please install the bundled MSDK +package which includes the appropriate OpenOCD modifications. To leverage this +OpenOCD instance, run the `flash-msdk` Makefile rule, or `-msdk` CMake +target. diff --git a/hw/bsp/max32666/family.cmake b/hw/bsp/max32666/family.cmake index c9fa2510a..ef2a2bb63 100644 --- a/hw/bsp/max32666/family.cmake +++ b/hw/bsp/max32666/family.cmake @@ -42,7 +42,6 @@ function(add_board_target BOARD_TARGET) # Startup & Linker script set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S) set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) - set(STARTUP_FILE_IAR ${MAX32_CMSIS}/Device/Maxim/MAX32665/Source/IAR/startup_max32665.S) set(PERIPH_SRC ${MAX32_PERIPH}/Source) add_library(${BOARD_TARGET} STATIC @@ -98,10 +97,6 @@ function(add_board_target BOARD_TARGET) target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_Clang}" ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--config=${LD_FILE_IAR}" - ) endif () endfunction() @@ -148,4 +143,18 @@ function(family_configure_example TARGET RTOS) # Flashing family_flash_jlink(${TARGET}) + family_flash_msdk(${TARGET}) +endfunction() + +# Add flash msdk target +function(family_flash_msdk TARGET) + set(MAXIM_PATH "$ENV{MAXIM_PATH}") + + add_custom_target(${TARGET}-msdk + DEPENDS ${TARGET} + COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts + -f interface/cmsis-dap.cfg -f target/max32665.cfg + -c "program $ verify; init; reset; exit" + VERBATIM + ) endfunction() diff --git a/hw/bsp/max32666/family.mk b/hw/bsp/max32666/family.mk index 31428cacd..31f81f014 100644 --- a/hw/bsp/max32666/family.mk +++ b/hw/bsp/max32666/family.mk @@ -14,9 +14,6 @@ PORT ?= 0 SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S LD_FILE = $(FAMILY_PATH)/max32666.ld -# IAR -#SRC_S_IAR += ? - # -------------- # Compiler Flags # -------------- @@ -42,7 +39,7 @@ LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs # For flash-jlink target JLINK_DEVICE = max32666 -# flash target using Jlik +# flash target using Jlink by default flash: flash-jlink # Optional flash option when running within an installed MSDK to use OpenOCD @@ -83,7 +80,6 @@ SRC_C += \ $(PERIPH_SRC)/UART/uart_me14.c \ $(PERIPH_SRC)/UART/uart_reva.c \ - INC += \ $(TOP)/$(BOARD_PATH) \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ diff --git a/hw/bsp/max32690/README.md b/hw/bsp/max32690/README.md new file mode 100644 index 000000000..081ae0ad4 --- /dev/null +++ b/hw/bsp/max32690/README.md @@ -0,0 +1,31 @@ +# Analog Devices MAX32690 + +This BSP is for working with the Analog Devices +[MAX32690](https://www.analog.com/en/products/max32690.html) microcontroller. +The following boards are supported: + * [MAX32690EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html) + * [AD-APARD32690-SL](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html) + + +This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device +interfaces and hardware abstraction layers. This source code package is fetched +as part of the get-deps script. + +The microcontroller utilizes the standard GNU ARM toolchain. If this toolchain +is not already available on your build machine, it can be installed by using the +bundled MSDK installation. Details on downloading and installing can be found +in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/). + +## Flashing + +The default flashing behavior in this BSP is to utilize JLink. This can be done +by running the `flash` or `flash-jlink` rule for Makefiles, or the +`-jlink` target for CMake. + +Both the Evaluation Kit and APARD boards are shipped with a CMSIS-DAP +compatible debug probe. However, at the time of writing, the necessary flashing +algorithms for OpenOCD have not yet been incorporated into the OpenOCD master +branch. To utilize the provided debug probes, please install the bundled MSDK +package which includes the appropriate OpenOCD modifications. To leverage this +OpenOCD instance, run the `flash-msdk` Makefile rule, or `-msdk` CMake +target. diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake index 8b117bae5..5c470f86b 100644 --- a/hw/bsp/max32690/family.cmake +++ b/hw/bsp/max32690/family.cmake @@ -46,7 +46,6 @@ function(add_board_target BOARD_TARGET) # Startup & Linker script set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/GCC/startup_max32690.s) set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) - set(STARTUP_FILE_IAR ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/IAR/startup_max32690.s) set(PERIPH_SRC ${MAX32_PERIPH}/Source) add_library(${BOARD_TARGET} STATIC @@ -89,7 +88,7 @@ function(add_board_target BOARD_TARGET) ) target_compile_options(${BOARD_TARGET} PRIVATE - -Wno-error=strict-prototypes + -Wno-error=strict-prototypes ) update_board(${BOARD_TARGET}) @@ -103,10 +102,6 @@ function(add_board_target BOARD_TARGET) target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_Clang}" ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--config=${LD_FILE_IAR}" - ) endif () endfunction() @@ -153,4 +148,18 @@ function(family_configure_example TARGET RTOS) # Flashing family_flash_jlink(${TARGET}) + family_flash_msdk(${TARGET}) +endfunction() + +# Add flash msdk target +function(family_flash_msdk TARGET) + set(MAXIM_PATH "$ENV{MAXIM_PATH}") + + add_custom_target(${TARGET}-msdk + DEPENDS ${TARGET} + COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts + -f interface/cmsis-dap.cfg -f target/max32690.cfg + -c "program $ verify; init; reset; exit" + VERBATIM + ) endfunction() diff --git a/hw/bsp/max32690/family.mk b/hw/bsp/max32690/family.mk index 0405a2914..8b9fbc175 100644 --- a/hw/bsp/max32690/family.mk +++ b/hw/bsp/max32690/family.mk @@ -14,9 +14,6 @@ PORT ?= 0 SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/GCC/startup_max32690.s LD_FILE = $(FAMILY_PATH)/max32690.ld -# IAR -SRC_S_IAR += $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/IAR/startup_max32690.s - # -------------- # Compiler Flags # -------------- @@ -49,7 +46,7 @@ LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs # For flash-jlink target JLINK_DEVICE = max32690 -# flash target using Jlik +# flash target using Jlink by default flash: flash-jlink # Optional flash option when running within an installed MSDK to use OpenOCD @@ -91,7 +88,6 @@ SRC_C += \ $(PERIPH_SRC)/UART/uart_me18.c \ $(PERIPH_SRC)/UART/uart_revb.c \ - INC += \ $(TOP)/$(BOARD_PATH) \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ diff --git a/hw/bsp/max78002/README.md b/hw/bsp/max78002/README.md new file mode 100644 index 000000000..4fb1bede4 --- /dev/null +++ b/hw/bsp/max78002/README.md @@ -0,0 +1,28 @@ +# Analog Devices MAX78002 + +This BSP is for working with the Analog Devices +[MAX78002](https://www.analog.com/en/products/max78002.html) AI microcontroller. +The following boards are supported: + * [MAX78002EVKIT](https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html) + +This part family leverages the Maxim Microcontrollers SDK (MSDK) for the device +interfaces and hardware abstraction layers. This source code package is fetched +as part of the get-deps script. + +The microcontroller utilizes the standard GNU ARM toolchain. If this toolchain +is not already available on your build machine, it can be installed by using the +bundled MSDK installation. Details on downloading and installing can be found +in the [User's Guide](https://analogdevicesinc.github.io/msdk//USERGUIDE/). + +## Flashing + +The default flashing behavior in this BSP is to utilize JLink. This can be done +by running the `flash` or `flash-jlink` rule for Makefiles, or the +`-jlink` target for CMake. + +The Evaluation Kit is shipped with a CMSIS-DAP compatible debug probe. However, +at the time of writing, the necessary flashing algorithms for OpenOCD have not +yet been incorporated into the OpenOCD master branch. To utilize the provided +debug probes, please install the bundled MSDK package which includes the +appropriate OpenOCD modifications. To leverage this OpenOCD instance, run the +`flash-msdk` Makefile rule, or `-msdk` CMake target. diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake index 28eaaa7e9..83fd3007f 100644 --- a/hw/bsp/max78002/family.cmake +++ b/hw/bsp/max78002/family.cmake @@ -42,7 +42,6 @@ function(add_board_target BOARD_TARGET) # Startup & Linker script set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S) set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) - #set(STARTUP_FILE_IAR ?) set(PERIPH_SRC ${MAX32_PERIPH}/Source) add_library(${BOARD_TARGET} STATIC @@ -87,8 +86,8 @@ function(add_board_target BOARD_TARGET) ) target_compile_options(${BOARD_TARGET} PRIVATE - -Wno-error=strict-prototypes - -Wno-error=redundant-decls + -Wno-error=strict-prototypes + -Wno-error=redundant-decls ) update_board(${BOARD_TARGET}) @@ -102,10 +101,6 @@ function(add_board_target BOARD_TARGET) target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_Clang}" ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") - target_link_options(${BOARD_TARGET} PUBLIC - "LINKER:--config=${LD_FILE_IAR}" - ) endif () endfunction() @@ -146,8 +141,8 @@ function(family_configure_example TARGET RTOS) ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) target_compile_options(${TARGET}-tinyusb PRIVATE - -Wno-error=strict-prototypes - -Wno-error=redundant-decls + -Wno-error=strict-prototypes + -Wno-error=redundant-decls ) # Link dependencies @@ -155,4 +150,18 @@ function(family_configure_example TARGET RTOS) # Flashing family_flash_jlink(${TARGET}) + family_flash_msdk(${TARGET}) +endfunction() + +# Add flash msdk target +function(family_flash_msdk TARGET) + set(MAXIM_PATH "$ENV{MAXIM_PATH}") + + add_custom_target(${TARGET}-msdk + DEPENDS ${TARGET} + COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts + -f interface/cmsis-dap.cfg -f target/max78002.cfg + -c "program $ verify; init; reset; exit" + VERBATIM + ) endfunction() diff --git a/hw/bsp/max78002/family.mk b/hw/bsp/max78002/family.mk index 04163417c..8df8517da 100644 --- a/hw/bsp/max78002/family.mk +++ b/hw/bsp/max78002/family.mk @@ -14,9 +14,6 @@ PORT ?= 0 SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S LD_FILE = $(FAMILY_PATH)/max78002.ld -# IAR -#SRC_S_IAR += - # -------------- # Compiler Flags # -------------- @@ -45,7 +42,7 @@ LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs # For flash-jlink target JLINK_DEVICE = max78000 -# flash target using Jlik +# flash target using Jlink by default flash: flash-jlink # Optional flash option when running within an installed MSDK to use OpenOCD @@ -88,7 +85,6 @@ SRC_C += \ $(PERIPH_SRC)/UART/uart_ai87.c \ $(PERIPH_SRC)/UART/uart_revb.c \ - INC += \ $(TOP)/$(BOARD_PATH) \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ -- cgit v1.3.1 From 494533f9d7b7961dd9a3acf7c2e9070f8ba172b5 Mon Sep 17 00:00:00 2001 From: Brent Kowal Date: Wed, 10 Jul 2024 15:52:43 -0400 Subject: Minor build system fix Correct a case-sensitive file extension issue in the MAX32690 build scripts. Did not present itself as an issue under MinGW or MSYS, just Linux. --- hw/bsp/max32690/family.cmake | 2 +- hw/bsp/max32690/family.mk | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'hw') diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake index 5c470f86b..d7a562956 100644 --- a/hw/bsp/max32690/family.cmake +++ b/hw/bsp/max32690/family.cmake @@ -44,7 +44,7 @@ function(add_board_target BOARD_TARGET) endif () # Startup & Linker script - set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/GCC/startup_max32690.s) + set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/GCC/startup_max32690.S) set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) set(PERIPH_SRC ${MAX32_PERIPH}/Source) diff --git a/hw/bsp/max32690/family.mk b/hw/bsp/max32690/family.mk index 8b9fbc175..9360a07c6 100644 --- a/hw/bsp/max32690/family.mk +++ b/hw/bsp/max32690/family.mk @@ -11,7 +11,7 @@ CPU_CORE ?= cortex-m4 PORT ?= 0 # GCC -SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/GCC/startup_max32690.s +SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/GCC/startup_max32690.S LD_FILE = $(FAMILY_PATH)/max32690.ld # -------------- -- cgit v1.3.1 From 13f5f20c981cc54baa8438e275524db03fb79e94 Mon Sep 17 00:00:00 2001 From: Brent Kowal Date: Thu, 11 Jul 2024 12:13:30 -0400 Subject: Pre-commit fixes. Resolve codespell and EOF errors found in the pre-commit CI task. --- hw/bsp/max32650/README.md | 2 +- hw/bsp/max32650/boards/max32650evkit/max32650.ld | 2 +- hw/bsp/max32650/boards/max32650fthr/max32650.ld | 2 +- hw/bsp/max32650/boards/max32651evkit/max32651.ld | 2 +- hw/bsp/max32650/family.mk | 2 +- hw/bsp/max32666/family.c | 2 +- hw/bsp/max32666/max32666.ld | 2 +- hw/bsp/max32690/family.c | 2 +- hw/bsp/max32690/max32690.ld | 2 +- hw/bsp/max78002/family.c | 2 +- hw/bsp/max78002/max78002.ld | 4 ++-- src/portable/analog/max32/dcd_max32.c | 2 +- 12 files changed, 13 insertions(+), 13 deletions(-) (limited to 'hw') diff --git a/hw/bsp/max32650/README.md b/hw/bsp/max32650/README.md index cb8069bba..ca66a1ac4 100644 --- a/hw/bsp/max32650/README.md +++ b/hw/bsp/max32650/README.md @@ -43,4 +43,4 @@ MAX32651EVKIT. To flash the signed image, the MSDK's OpenOCD variant must be used. To flash the MAX32651EVKIT please install the bundled MSDK, and utilize the `flash-msdk` -and `-msdk` rule and target. \ No newline at end of file +and `-msdk` rule and target. diff --git a/hw/bsp/max32650/boards/max32650evkit/max32650.ld b/hw/bsp/max32650/boards/max32650evkit/max32650.ld index 3a1e5100d..0e56a91ec 100644 --- a/hw/bsp/max32650/boards/max32650evkit/max32650.ld +++ b/hw/bsp/max32650/boards/max32650evkit/max32650.ld @@ -85,7 +85,7 @@ SECTIONS { { . = ALIGN(4); _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ *(COMMON) _ebss = ALIGN(., 4); } > SRAM diff --git a/hw/bsp/max32650/boards/max32650fthr/max32650.ld b/hw/bsp/max32650/boards/max32650fthr/max32650.ld index 3a1e5100d..0e56a91ec 100644 --- a/hw/bsp/max32650/boards/max32650fthr/max32650.ld +++ b/hw/bsp/max32650/boards/max32650fthr/max32650.ld @@ -85,7 +85,7 @@ SECTIONS { { . = ALIGN(4); _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ *(COMMON) _ebss = ALIGN(., 4); } > SRAM diff --git a/hw/bsp/max32650/boards/max32651evkit/max32651.ld b/hw/bsp/max32650/boards/max32651evkit/max32651.ld index a873463d4..3921d10f2 100644 --- a/hw/bsp/max32650/boards/max32651evkit/max32651.ld +++ b/hw/bsp/max32650/boards/max32651evkit/max32651.ld @@ -98,7 +98,7 @@ SECTIONS { { . = ALIGN(4); _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ *(COMMON) _ebss = ALIGN(., 4); } > SRAM diff --git a/hw/bsp/max32650/family.mk b/hw/bsp/max32650/family.mk index 577d96717..0718523c3 100644 --- a/hw/bsp/max32650/family.mk +++ b/hw/bsp/max32650/family.mk @@ -121,7 +121,7 @@ SIGN_EXE := sign_app.exe endif endif -# Rule to sign the build. This will in-place modifiy the existing .elf file +# Rule to sign the build. This will in-place modify the existing .elf file # an populate the .sig section with the signature value sign-build: $(BUILD)/$(PROJECT).elf $(OBJCOPY) $(BUILD)/$(PROJECT).elf -R .sig -O binary $(BUILD)/$(PROJECT).bin diff --git a/hw/bsp/max32666/family.c b/hw/bsp/max32666/family.c index 98e1248d7..1398e09ff 100644 --- a/hw/bsp/max32666/family.c +++ b/hw/bsp/max32666/family.c @@ -106,7 +106,7 @@ uint32_t board_button_read(void) { size_t board_get_unique_id(uint8_t id[], size_t max_len) { uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer - /* All other 2nd parameter is optional checkum buffer */ + /* All other 2nd parameter is optional checksum buffer */ MXC_SYS_GetUSN(hw_id, NULL); size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); diff --git a/hw/bsp/max32666/max32666.ld b/hw/bsp/max32666/max32666.ld index dcf61a3d0..06c124247 100644 --- a/hw/bsp/max32666/max32666.ld +++ b/hw/bsp/max32666/max32666.ld @@ -101,7 +101,7 @@ SECTIONS { { . = ALIGN(4); _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ *(COMMON) _ebss = ALIGN(., 4); } > SRAM diff --git a/hw/bsp/max32690/family.c b/hw/bsp/max32690/family.c index acd6e2593..f4998bdbe 100644 --- a/hw/bsp/max32690/family.c +++ b/hw/bsp/max32690/family.c @@ -104,7 +104,7 @@ uint32_t board_button_read(void) { size_t board_get_unique_id(uint8_t id[], size_t max_len) { uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer - /* All other 2nd parameter is optional checkum buffer */ + /* All other 2nd parameter is optional checksum buffer */ MXC_SYS_GetUSN(hw_id, NULL); size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); diff --git a/hw/bsp/max32690/max32690.ld b/hw/bsp/max32690/max32690.ld index 3d857b4e8..64b906a54 100644 --- a/hw/bsp/max32690/max32690.ld +++ b/hw/bsp/max32690/max32690.ld @@ -130,7 +130,7 @@ SECTIONS { { . = ALIGN(4); _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ *(COMMON) _ebss = ALIGN(., 4); } > SRAM diff --git a/hw/bsp/max78002/family.c b/hw/bsp/max78002/family.c index c105f056b..7758083a2 100644 --- a/hw/bsp/max78002/family.c +++ b/hw/bsp/max78002/family.c @@ -103,7 +103,7 @@ uint32_t board_button_read(void) { size_t board_get_unique_id(uint8_t id[], size_t max_len) { uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer - /* All other 2nd parameter is optional checkum buffer */ + /* All other 2nd parameter is optional checksum buffer */ MXC_SYS_GetUSN(hw_id, NULL); size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); diff --git a/hw/bsp/max78002/max78002.ld b/hw/bsp/max78002/max78002.ld index 60f99e28f..e5c4866ee 100644 --- a/hw/bsp/max78002/max78002.ld +++ b/hw/bsp/max78002/max78002.ld @@ -127,7 +127,7 @@ SECTIONS { { . = ALIGN(4); _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ *(COMMON) _ebss = ALIGN(., 4); } > SRAM @@ -138,7 +138,7 @@ SECTIONS { _shared = .; *(.mailbox*) . = ALIGN(4); - *(.shared*) /*read-write zero initialized data: uninitialzed global variable*/ + *(.shared*) /*read-write zero initialized data: uninitialized global variable*/ _eshared = ALIGN(., 4); } > SRAM __shared_data = LOADADDR(.shared); diff --git a/src/portable/analog/max32/dcd_max32.c b/src/portable/analog/max32/dcd_max32.c index 7226003de..df616120a 100644 --- a/src/portable/analog/max32/dcd_max32.c +++ b/src/portable/analog/max32/dcd_max32.c @@ -196,7 +196,7 @@ static bool handle_xfer_in(uint_fast8_t ep_addr) { } pipe->remaining = rem - len; } - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_INPKTRDY;//TODO: Verify a | isnt needed + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_INPKTRDY;//TODO: Verify a | isn't needed return false; } -- cgit v1.3.1 From 5122d6d109f8c4b31b6cbe29c685fad30a8961fe Mon Sep 17 00:00:00 2001 From: Brent Kowal Date: Thu, 25 Jul 2024 09:08:37 -0400 Subject: Combined DCD MUSB implementations Combined the new MAX32 MUSB implementation with the existing (TI) implementation to provide generic code base for working the MUSB DCD peripheral. - Added abstraction calls for FIFO setup, EP registers, Ctrl registers and interrupt setup. - Combined TM4C and MSP432E into a single header file. - Created musb_max32.h, and removed the MAX32 specific C implementation. - Updated MAX32 build system to use dcd_musb.c. - Added MAX32 conditions for cdc_dual_ports example descriptors missed during first testing. --- .../device/cdc_dual_ports/src/usb_descriptors.c | 12 + hw/bsp/max32650/family.cmake | 2 +- hw/bsp/max32650/family.mk | 2 +- hw/bsp/max32666/family.cmake | 2 +- hw/bsp/max32666/family.mk | 2 +- hw/bsp/max32690/family.cmake | 2 +- hw/bsp/max32690/family.mk | 2 +- hw/bsp/max78002/family.cmake | 2 +- hw/bsp/max78002/family.mk | 2 +- src/portable/analog/max32/dcd_max32.c | 811 --------------------- src/portable/mentor/musb/dcd_musb.c | 436 ++++------- src/portable/mentor/musb/hcd_musb.c | 12 +- src/portable/mentor/musb/musb_max32.h | 221 ++++++ src/portable/mentor/musb/musb_msp432e.h | 40 - src/portable/mentor/musb/musb_ti.h | 285 ++++++++ src/portable/mentor/musb/musb_tm4c.h | 45 -- src/portable/mentor/musb/musb_type.h | 33 + 17 files changed, 711 insertions(+), 1200 deletions(-) delete mode 100644 src/portable/analog/max32/dcd_max32.c create mode 100644 src/portable/mentor/musb/musb_max32.h delete mode 100644 src/portable/mentor/musb/musb_msp432e.h create mode 100644 src/portable/mentor/musb/musb_ti.h delete mode 100644 src/portable/mentor/musb/musb_tm4c.h (limited to 'hw') diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c index de2505c07..808d78411 100644 --- a/examples/device/cdc_dual_ports/src/usb_descriptors.c +++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c @@ -120,6 +120,18 @@ enum #define EPNUM_CDC_1_OUT 0x05 #define EPNUM_CDC_1_IN 0x86 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 + // MAX32 doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_CDC_0_NOTIF 0x81 + #define EPNUM_CDC_0_OUT 0x02 + #define EPNUM_CDC_0_IN 0x83 + + #define EPNUM_CDC_1_NOTIF 0x84 + #define EPNUM_CDC_1_OUT 0x05 + #define EPNUM_CDC_1_IN 0x86 + #else #define EPNUM_CDC_0_NOTIF 0x81 #define EPNUM_CDC_0_OUT 0x02 diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake index 129d99af8..92b68a1cd 100644 --- a/hw/bsp/max32650/family.cmake +++ b/hw/bsp/max32650/family.cmake @@ -132,7 +132,7 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MAX32650 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/analog/max32/dcd_max32.c + ${TOP}/src/portable/mentor/musb/dcd_musb.c ) target_compile_options(${TARGET} PRIVATE -Wno-error=strict-prototypes diff --git a/hw/bsp/max32650/family.mk b/hw/bsp/max32650/family.mk index 0718523c3..359261216 100644 --- a/hw/bsp/max32650/family.mk +++ b/hw/bsp/max32650/family.mk @@ -62,7 +62,7 @@ flash: $(DEFAULT_FLASH) # ----------------- PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source SRC_C += \ - src/portable/analog/max32/dcd_max32.c \ + src/portable/mentor/musb/dcd_musb.c \ $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/heap.c \ $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/system_max32650.c \ $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/header_MAX32650.c \ diff --git a/hw/bsp/max32666/family.cmake b/hw/bsp/max32666/family.cmake index ef2a2bb63..eb9d2175f 100644 --- a/hw/bsp/max32666/family.cmake +++ b/hw/bsp/max32666/family.cmake @@ -127,7 +127,7 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MAX32666 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/analog/max32/dcd_max32.c + ${TOP}/src/portable/mentor/musb/dcd_musb.c ) target_compile_options(${TARGET} PRIVATE -Wno-error=strict-prototypes diff --git a/hw/bsp/max32666/family.mk b/hw/bsp/max32666/family.mk index 31f81f014..720d994ef 100644 --- a/hw/bsp/max32666/family.mk +++ b/hw/bsp/max32666/family.mk @@ -57,7 +57,7 @@ flash-msdk: $(BUILD)/$(PROJECT).elf # ----------------- PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source SRC_C += \ - src/portable/analog/max32/dcd_max32.c \ + src/portable/mentor/musb/dcd_musb.c \ $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/heap.c \ $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/system_max32665.c \ $(PERIPH_SRC)/SYS/mxc_assert.c \ diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake index d7a562956..2a9422dbe 100644 --- a/hw/bsp/max32690/family.cmake +++ b/hw/bsp/max32690/family.cmake @@ -132,7 +132,7 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MAX32690 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/analog/max32/dcd_max32.c + ${TOP}/src/portable/mentor/musb/dcd_musb.c ) target_compile_options(${TARGET} PRIVATE -Wno-error=strict-prototypes diff --git a/hw/bsp/max32690/family.mk b/hw/bsp/max32690/family.mk index 9360a07c6..c533cf4a4 100644 --- a/hw/bsp/max32690/family.mk +++ b/hw/bsp/max32690/family.mk @@ -64,7 +64,7 @@ flash-msdk: $(BUILD)/$(PROJECT).elf # ----------------- PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source SRC_C += \ - src/portable/analog/max32/dcd_max32.c \ + src/portable/mentor/musb/dcd_musb.c \ $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/heap.c \ $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/system_max32690.c \ $(PERIPH_SRC)/SYS/mxc_assert.c \ diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake index 83fd3007f..090f1da43 100644 --- a/hw/bsp/max78002/family.cmake +++ b/hw/bsp/max78002/family.cmake @@ -137,7 +137,7 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MAX78002 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/analog/max32/dcd_max32.c + ${TOP}/src/portable/mentor/musb/dcd_musb.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) target_compile_options(${TARGET}-tinyusb PRIVATE diff --git a/hw/bsp/max78002/family.mk b/hw/bsp/max78002/family.mk index 8df8517da..5297815de 100644 --- a/hw/bsp/max78002/family.mk +++ b/hw/bsp/max78002/family.mk @@ -60,7 +60,7 @@ flash-msdk: $(BUILD)/$(PROJECT).elf # ----------------- PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source SRC_C += \ - src/portable/analog/max32/dcd_max32.c \ + src/portable/mentor/musb/dcd_musb.c \ $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/heap.c \ $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/system_max78002.c \ $(PERIPH_SRC)/SYS/mxc_assert.c \ diff --git a/src/portable/analog/max32/dcd_max32.c b/src/portable/analog/max32/dcd_max32.c deleted file mode 100644 index df616120a..000000000 --- a/src/portable/analog/max32/dcd_max32.c +++ /dev/null @@ -1,811 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2021 Koji KITAYAMA - * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" - -#if CFG_TUD_ENABLED && \ - TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX78002) - - #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) -/* GCC warns that an address may be unaligned, even though - * the target CPU has the capability for unaligned memory access. */ -_Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); - #endif - - #include "device/dcd.h" - - #include "mxc_delay.h" - #include "mxc_device.h" - #include "mxc_sys.h" - #include "nvic_table.h" - #include "usbhs_regs.h" - - #define USBHS_M31_CLOCK_RECOVERY - - /*------------------------------------------------------------------ - * MACRO TYPEDEF CONSTANT ENUM DECLARATION - *------------------------------------------------------------------*/ - #define REQUEST_TYPE_INVALID (0xFFu) - - -typedef union { - uint8_t u8; - uint16_t u16; - uint32_t u32; -} hw_fifo_t; - -typedef struct TU_ATTR_PACKED { - void *buf; /* the start address of a transfer data buffer */ - uint16_t length; /* the number of bytes in the buffer */ - uint16_t remaining; /* the number of bytes remaining in the buffer */ -} pipe_state_t; - -typedef struct -{ - tusb_control_request_t setup_packet; - uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */ - int8_t status_out; - pipe_state_t pipe0; - pipe_state_t pipe[2][TUP_DCD_ENDPOINT_MAX - 1]; /* pipe[direction][endpoint number - 1] */ - uint16_t pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */ -} dcd_data_t; - -/*------------------------------------------------------------------ - * INTERNAL OBJECT & FUNCTION DECLARATION - *------------------------------------------------------------------*/ -static dcd_data_t _dcd; - - -static volatile void *edpt_get_fifo_ptr(unsigned epnum) { - volatile uint32_t *ptr; - - ptr = &MXC_USBHS->fifo0; - ptr += epnum; /* Pointer math: multiplies ep by sizeof(uint32_t) */ - - return (volatile void *) ptr; -} - -static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { - volatile hw_fifo_t *reg = (volatile hw_fifo_t *) fifo; - uintptr_t addr = (uintptr_t) buf; - while (len >= 4) { - reg->u32 = *(uint32_t const *) addr; - addr += 4; - len -= 4; - } - if (len >= 2) { - reg->u16 = *(uint16_t const *) addr; - addr += 2; - len -= 2; - } - if (len) { - reg->u8 = *(uint8_t const *) addr; - } -} - -static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) { - volatile hw_fifo_t *reg = (volatile hw_fifo_t *) fifo; - uintptr_t addr = (uintptr_t) buf; - while (len >= 4) { - *(uint32_t *) addr = reg->u32; - addr += 4; - len -= 4; - } - if (len >= 2) { - *(uint16_t *) addr = reg->u16; - addr += 2; - len -= 2; - } - if (len) { - *(uint8_t *) addr = reg->u8; - } -} - -static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) { - static const struct { - void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info); - void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n); - void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len); - } ops[] = { - /* OUT */ {tu_fifo_get_write_info, tu_fifo_advance_write_pointer, pipe_read_packet}, - /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, - }; - tu_fifo_buffer_info_t info; - ops[dir].tu_fifo_get_info(f, &info); - unsigned total_len = len; - len = TU_MIN(total_len, info.len_lin); - ops[dir].pipe_read_write(info.ptr_lin, fifo, len); - unsigned rem = total_len - len; - if (rem) { - len = TU_MIN(rem, info.len_wrap); - ops[dir].pipe_read_write(info.ptr_wrap, fifo, len); - rem -= len; - } - ops[dir].tu_fifo_advance(f, total_len - rem); -} - -static void process_setup_packet(uint8_t rhport) { - uint32_t *p = (void *) &_dcd.setup_packet; - p[0] = MXC_USBHS->fifo0; - p[1] = MXC_USBHS->fifo0; - - _dcd.pipe0.buf = NULL; - _dcd.pipe0.length = 0; - _dcd.pipe0.remaining = 0; - dcd_event_setup_received(rhport, (const uint8_t *) (uintptr_t) &_dcd.setup_packet, true); - - const unsigned len = _dcd.setup_packet.wLength; - _dcd.remaining_ctrl = len; - const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType); - /* Clear RX FIFO and reverse the transaction direction */ - if (len && dir_in) { - MXC_USBHS->index = 0; - MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY; - } -} - -static bool handle_xfer_in(uint_fast8_t ep_addr) { - unsigned epnum = tu_edpt_number(ep_addr); - unsigned epnum_minus1 = epnum - 1; - pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; - const unsigned rem = pipe->remaining; - - //This function should not be for ep0 - TU_ASSERT(epnum); - - if (!rem) { - pipe->buf = NULL; - return true; - } - - MXC_USBHS->index = epnum; - const unsigned mps = MXC_USBHS->inmaxp; - const unsigned len = TU_MIN(mps, rem); - void *buf = pipe->buf; - volatile void *fifo_ptr = edpt_get_fifo_ptr(epnum); - if (len) { - if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) { - pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_IN); - } else { - pipe_write_packet(buf, fifo_ptr, len); - pipe->buf = buf + len; - } - pipe->remaining = rem - len; - } - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_INPKTRDY;//TODO: Verify a | isn't needed - - return false; -} - -static bool handle_xfer_out(uint_fast8_t ep_addr) { - unsigned epnum = tu_edpt_number(ep_addr); - unsigned epnum_minus1 = epnum - 1; - pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; - - //This function should not be for ep0 - TU_ASSERT(epnum); - - MXC_USBHS->index = epnum; - - TU_ASSERT(MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY); - - const unsigned mps = MXC_USBHS->outmaxp; - const unsigned rem = pipe->remaining; - const unsigned vld = MXC_USBHS->outcount; - const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); - void *buf = pipe->buf; - volatile void *fifo_ptr = edpt_get_fifo_ptr(epnum); - if (len) { - if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) { - pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_OUT); - } else { - pipe_read_packet(buf, fifo_ptr, len); - pipe->buf = buf + len; - } - pipe->remaining = rem - len; - } - if ((len < mps) || (rem == len)) { - pipe->buf = NULL; - return NULL != buf; - } - MXC_USBHS->outcsrl = 0; /* Clear RXRDY bit *///TODO: Verify just setting to 0 is ok - return false; -} - -static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - (void) rhport; - - unsigned epnum = tu_edpt_number(ep_addr); - unsigned epnum_minus1 = epnum - 1; - unsigned dir_in = tu_edpt_dir(ep_addr); - - pipe_state_t *pipe = &_dcd.pipe[dir_in][epnum_minus1]; - pipe->buf = buffer; - pipe->length = total_bytes; - pipe->remaining = total_bytes; - - if (dir_in) { - handle_xfer_in(ep_addr); - } else { - MXC_USBHS->index = epnum; - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { - MXC_USBHS->outcsrl = 0;//TODO: Verify just setting to 0 is ok - } - } - return true; -} - -static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - (void) rhport; - TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */ - - const unsigned req = _dcd.setup_packet.bmRequestType; - TU_ASSERT(req != REQUEST_TYPE_INVALID || total_bytes == 0); - - if (req == REQUEST_TYPE_INVALID || _dcd.status_out) { - /* STATUS OUT stage. - * MUSB controller automatically handles STATUS OUT packets without - * software helps. We do not have to do anything. And STATUS stage - * may have already finished and received the next setup packet - * without calling this function, so we have no choice but to - * invoke the callback function of status packet here. */ - _dcd.status_out = 0; - if (req == REQUEST_TYPE_INVALID) { - dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false); - } else { - /* The next setup packet has already been received, it aborts - * invoking callback function to avoid confusing TUSB stack. */ - TU_LOG1("Drop CONTROL_STAGE_ACK\r\n"); - } - return true; - } - const unsigned dir_in = tu_edpt_dir(ep_addr); - MXC_USBHS->index = 0; - if (tu_edpt_dir(req) == dir_in) { /* DATA stage */ - TU_ASSERT(total_bytes <= _dcd.remaining_ctrl); - const unsigned rem = _dcd.remaining_ctrl; - const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes); - volatile void *fifo_ptr = edpt_get_fifo_ptr(0); - if (dir_in) { - pipe_write_packet(buffer, fifo_ptr, len); - - _dcd.pipe0.buf = buffer + len; - _dcd.pipe0.length = len; - _dcd.pipe0.remaining = 0; - - _dcd.remaining_ctrl = rem - len; - if ((len < 64) || (rem == len)) { - _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */ - _dcd.status_out = 1; - /* Flush TX FIFO and reverse the transaction direction. */ - MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_INPKTRDY | MXC_F_USBHS_CSR0_DATA_END; - } else { - MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_INPKTRDY; /* Flush TX FIFO to return ACK. */ - } - } else { - _dcd.pipe0.buf = buffer; - _dcd.pipe0.length = len; - _dcd.pipe0.remaining = len; - MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY; /* Clear RX FIFO to return ACK. */ - } - } else if (dir_in) { - _dcd.pipe0.buf = NULL; - _dcd.pipe0.length = 0; - _dcd.pipe0.remaining = 0; - /* Clear RX FIFO and reverse the transaction direction */ - MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY | MXC_F_USBHS_CSR0_DATA_END; - } - return true; -} - -static void process_ep0(uint8_t rhport) { - MXC_USBHS->index = 0; - uint_fast8_t csrl = MXC_USBHS->csr0; - - if (csrl & MXC_F_USBHS_CSR0_SENT_STALL) { - /* Returned STALL packet to HOST. */ - MXC_USBHS->csr0 = 0; /* Clear STALL */ - return; - } - - unsigned req = _dcd.setup_packet.bmRequestType; - if (csrl & MXC_F_USBHS_CSR0_SETUP_END) { - TU_LOG1(" ABORT by the next packets\r\n"); - MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_SETUP_END; - if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) { - /* DATA stage was aborted by receiving STATUS or SETUP packet. */ - _dcd.pipe0.buf = NULL; - _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; - dcd_event_xfer_complete(rhport, - req & TUSB_DIR_IN_MASK, - _dcd.pipe0.length - _dcd.pipe0.remaining, - XFER_RESULT_SUCCESS, true); - } - req = REQUEST_TYPE_INVALID; - if (!(csrl & MXC_F_USBHS_CSR0_OUTPKTRDY)) return; /* Received SETUP packet */ - } - - if (csrl & MXC_F_USBHS_CSR0_OUTPKTRDY) { - /* Received SETUP or DATA OUT packet */ - if (req == REQUEST_TYPE_INVALID) { - /* SETUP */ - TU_ASSERT(sizeof(tusb_control_request_t) == MXC_USBHS->count0, ); - process_setup_packet(rhport); - return; - } - if (_dcd.pipe0.buf) { - /* DATA OUT */ - const unsigned vld = MXC_USBHS->count0; - const unsigned rem = _dcd.pipe0.remaining; - const unsigned len = TU_MIN(TU_MIN(rem, 64), vld); - volatile void *fifo_ptr = edpt_get_fifo_ptr(0); - pipe_read_packet(_dcd.pipe0.buf, fifo_ptr, len); - - _dcd.pipe0.remaining = rem - len; - _dcd.remaining_ctrl -= len; - - _dcd.pipe0.buf = NULL; - dcd_event_xfer_complete(rhport, - tu_edpt_addr(0, TUSB_DIR_OUT), - _dcd.pipe0.length - _dcd.pipe0.remaining, - XFER_RESULT_SUCCESS, true); - } - return; - } - - /* When CSRL0 is zero, it means that completion of sending a any length packet - * or receiving a zero length packet. */ - if (req != REQUEST_TYPE_INVALID && !tu_edpt_dir(req)) { - /* STATUS IN */ - if (*(const uint16_t *) (uintptr_t) &_dcd.setup_packet == 0x0500) { - /* The address must be changed on completion of the control transfer. */ - MXC_USBHS->faddr = (uint8_t) _dcd.setup_packet.wValue; - } - _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; - dcd_event_xfer_complete(rhport, - tu_edpt_addr(0, TUSB_DIR_IN), - _dcd.pipe0.length - _dcd.pipe0.remaining, - XFER_RESULT_SUCCESS, true); - return; - } - if (_dcd.pipe0.buf) { - /* DATA IN */ - _dcd.pipe0.buf = NULL; - dcd_event_xfer_complete(rhport, - tu_edpt_addr(0, TUSB_DIR_IN), - _dcd.pipe0.length - _dcd.pipe0.remaining, - XFER_RESULT_SUCCESS, true); - } -} - -static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) { - bool completed; - const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned epnum = tu_edpt_number(ep_addr); - - MXC_USBHS->index = epnum; - - if (dir_in) { - if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_SENTSTALL) { - MXC_USBHS->incsrl &= ~(MXC_F_USBHS_INCSRL_SENTSTALL | MXC_F_USBHS_INCSRL_UNDERRUN); - return; - } - completed = handle_xfer_in(ep_addr); - } else { - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_SENTSTALL) { - MXC_USBHS->outcsrl &= ~(MXC_F_USBHS_OUTCSRL_SENTSTALL | MXC_F_USBHS_OUTCSRL_OVERRUN); - return; - } - completed = handle_xfer_out(ep_addr); - } - - if (completed) { - pipe_state_t *pipe = &_dcd.pipe[dir_in][tu_edpt_number(ep_addr) - 1]; - dcd_event_xfer_complete(rhport, ep_addr, - pipe->length - pipe->remaining, - XFER_RESULT_SUCCESS, true); - } -} - -static void process_bus_reset(uint8_t rhport) { - (void) rhport; - /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), - * a control transfer state is SETUP or STATUS stage. */ - _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; - _dcd.status_out = 0; - /* When pipe0.buf has not NULL, DATA stage works in progress. */ - _dcd.pipe0.buf = NULL; - - MXC_USBHS->intrinen = 1; /* Enable only EP0 */ - MXC_USBHS->introuten = 0; - - - /* Clear FIFO settings */ - for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { - MXC_USBHS->index = i; - if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { - /* Per musbhsfc_pg, only flush FIFO if IN packet loaded */ - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_FLUSHFIFO; - } - - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { - /* Per musbhsfc_pg, only flush FIFO if OUT packet is ready */ - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_FLUSHFIFO; - } - } - dcd_event_bus_reset(0, (MXC_USBHS->power & MXC_F_USBHS_POWER_HS_MODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); -} - -/*------------------------------------------------------------------ - * Device API - *------------------------------------------------------------------*/ - -void dcd_init(uint8_t rhport) { - (void) rhport; - MXC_USBHS->intrusben |= MXC_F_USBHS_INTRUSBEN_SUSPEND_INT_EN; - - //Interrupt for VBUS disconnect - MXC_USBHS->mxm_int_en |= MXC_F_USBHS_MXM_INT_EN_NOVBUS; - - NVIC_ClearPendingIRQ(USB_IRQn); - dcd_edpt_close_all(rhport); - - //Unsuspend the MAC - MXC_USBHS->mxm_suspend = 0; - - /* Configure PHY */ - MXC_USBHS->m31_phy_xcfgi_31_0 = (0x1 << 3) | (0x1 << 11); - MXC_USBHS->m31_phy_xcfgi_63_32 = 0; - MXC_USBHS->m31_phy_xcfgi_95_64 = 0x1 << (72 - 64); - MXC_USBHS->m31_phy_xcfgi_127_96 = 0; - - - #ifdef USBHS_M31_CLOCK_RECOVERY - MXC_USBHS->m31_phy_noncry_rstb = 1; - MXC_USBHS->m31_phy_noncry_en = 1; - MXC_USBHS->m31_phy_outclksel = 0; - MXC_USBHS->m31_phy_coreclkin = 0; - MXC_USBHS->m31_phy_xtlsel = 2; /* Select 25 MHz clock */ - #else - /* Use this option to feed the PHY a 30 MHz clock, which is them used as a PLL reference */ - /* As it depends on the system core clock, this should probably be done at the SYS level */ - MXC_USBHS->m31_phy_noncry_rstb = 0; - MXC_USBHS->m31_phy_noncry_en = 0; - MXC_USBHS->m31_phy_outclksel = 1; - MXC_USBHS->m31_phy_coreclkin = 1; - MXC_USBHS->m31_phy_xtlsel = 3; /* Select 30 MHz clock */ - #endif - MXC_USBHS->m31_phy_pll_en = 1; - MXC_USBHS->m31_phy_oscouten = 1; - - /* Reset PHY */ - MXC_USBHS->m31_phy_ponrst = 0; - MXC_USBHS->m31_phy_ponrst = 1; - - dcd_connect(rhport); -} - -void dcd_int_enable(uint8_t rhport) { - (void) rhport; - NVIC_EnableIRQ(USB_IRQn); -} - -void dcd_int_disable(uint8_t rhport) { - (void) rhport; - NVIC_DisableIRQ(USB_IRQn); -} - -// Receive Set Address request, mcu port must also include status IN response -void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { - (void) rhport; - (void) dev_addr; - _dcd.pipe0.buf = NULL; - _dcd.pipe0.length = 0; - _dcd.pipe0.remaining = 0; - /* Clear RX FIFO to return ACK. */ - MXC_USBHS->index = 0; - MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY | MXC_F_USBHS_CSR0_DATA_END; -} - -// Wake up host -void dcd_remote_wakeup(uint8_t rhport) { - (void) rhport; - MXC_USBHS->power |= MXC_F_USBHS_POWER_RESUME; - - #if CFG_TUSB_OS != OPT_OS_NONE - osal_task_delay(10); - #else - MXC_Delay(MXC_DELAY_MSEC(10)); - #endif - - MXC_USBHS->power &= ~MXC_F_USBHS_POWER_RESUME; -} - -// Connect by enabling internal pull-up resistor on D+/D- -void dcd_connect(uint8_t rhport) { - (void) rhport; - MXC_USBHS->power |= TUD_OPT_HIGH_SPEED ? MXC_F_USBHS_POWER_HS_ENABLE : 0; - MXC_USBHS->power |= MXC_F_USBHS_POWER_SOFTCONN; -} - -// Disconnect by disabling internal pull-up resistor on D+/D- -void dcd_disconnect(uint8_t rhport) { - (void) rhport; - MXC_USBHS->power &= ~MXC_F_USBHS_POWER_SOFTCONN; -} - -void dcd_sof_enable(uint8_t rhport, bool en) { - (void) rhport; - (void) en; - - // TODO implement later -} - -//--------------------------------------------------------------------+ -// Endpoint API -//--------------------------------------------------------------------+ - -// Configure endpoint's registers according to descriptor -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) { - (void) rhport; - - const unsigned ep_addr = ep_desc->bEndpointAddress; - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned xfer = ep_desc->bmAttributes.xfer; - const unsigned mps = tu_edpt_packet_size(ep_desc); - - TU_ASSERT(epn < TUP_DCD_ENDPOINT_MAX); - - pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1]; - pipe->buf = NULL; - pipe->length = 0; - pipe->remaining = 0; - - MXC_USBHS->index = epn; - - if (dir_in) { - MXC_USBHS->inmaxp = mps; - MXC_USBHS->incsru = (MXC_F_USBHS_INCSRU_DPKTBUFDIS | MXC_F_USBHS_INCSRU_MODE) | ((xfer == TUSB_XFER_ISOCHRONOUS) ? MXC_F_USBHS_INCSRU_ISO : 0); - if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO; - } else { - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; - } - MXC_USBHS->intrinen |= TU_BIT(epn); - } else { - MXC_USBHS->outmaxp = mps; - MXC_USBHS->outcsru = (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS) | ((xfer == TUSB_XFER_ISOCHRONOUS) ? MXC_F_USBHS_OUTCSRU_ISO : 0); - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO; - } else { - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG; - } - MXC_USBHS->introuten |= TU_BIT(epn); - } - - return true; -} - -void dcd_edpt_close_all(uint8_t rhport) { - (void) rhport; - - MXC_SYS_Crit_Enter(); - MXC_USBHS->intrinen = 1; /* Enable only EP0 */ - MXC_USBHS->introuten = 0; - - for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { - MXC_USBHS->index = i; - MXC_USBHS->inmaxp = 0; - MXC_USBHS->incsru = MXC_F_USBHS_INCSRU_DPKTBUFDIS; - - if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO; - } else { - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; - } - - MXC_USBHS->outmaxp = 0; - MXC_USBHS->outcsru = MXC_F_USBHS_OUTCSRU_DPKTBUFDIS; - - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO; - } else { - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG; - } - } - MXC_SYS_Crit_Exit(); -} - -void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { - (void) rhport; - unsigned const epn = tu_edpt_number(ep_addr); - unsigned const dir_in = tu_edpt_dir(ep_addr); - - MXC_SYS_Crit_Enter(); - MXC_USBHS->index = epn; - if (dir_in) { - MXC_USBHS->intrinen &= ~TU_BIT(epn); - MXC_USBHS->inmaxp = 0; - MXC_USBHS->incsru = MXC_F_USBHS_INCSRU_DPKTBUFDIS; - if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO; - } else { - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; - } - } else { - MXC_USBHS->introuten &= ~TU_BIT(epn); - MXC_USBHS->outmaxp = 0; - MXC_USBHS->outcsru = MXC_F_USBHS_OUTCSRU_DPKTBUFDIS; - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO; - } else { - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG; - } - } - MXC_SYS_Crit_Exit(); -} - -// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - (void) rhport; - bool ret; - unsigned const epnum = tu_edpt_number(ep_addr); - MXC_SYS_Crit_Enter(); - if (epnum) { - _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] &= ~TU_BIT(epnum - 1); - ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes); - } else - ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes); - MXC_SYS_Crit_Exit(); - return ret; -} - -// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c -bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes) { - (void) rhport; - bool ret; - unsigned const epnum = tu_edpt_number(ep_addr); - TU_ASSERT(epnum); - MXC_SYS_Crit_Enter(); - _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] |= TU_BIT(epnum - 1); - ret = edpt_n_xfer(rhport, ep_addr, (uint8_t *) ff, total_bytes); - MXC_SYS_Crit_Exit(); - return ret; -} - -// Stall endpoint -void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - (void) rhport; - unsigned const epn = tu_edpt_number(ep_addr); - MXC_SYS_Crit_Enter(); - MXC_USBHS->index = epn; - if (0 == epn) { - if (!ep_addr) { /* Ignore EP80 */ - _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; - _dcd.pipe0.buf = NULL; - MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SEND_STALL; - } - } else { - if (tu_edpt_dir(ep_addr)) { /* IN */ - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_SENDSTALL; - } else { /* OUT */ - TU_ASSERT(!(MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY), ); - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_SENDSTALL; - } - } - MXC_SYS_Crit_Exit(); -} - -// clear stall, data toggle is also reset to DATA0 -void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - (void) rhport; - unsigned const epn = tu_edpt_number(ep_addr); - MXC_SYS_Crit_Enter(); - MXC_USBHS->index = epn; - if (tu_edpt_dir(ep_addr)) { /* IN */ - /* IN endpoint */ - if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { - /* Per musbhsfc_pg, only flush FIFO if IN packet loaded */ - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO; - } else { - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; - } - } else { /* OUT */ - /* Otherwise, must be OUT endpoint */ - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { - /* Per musbhsfc_pg, only flush FIFO if OUT packet is ready */ - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO; - } else { - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG; - } - } - MXC_SYS_Crit_Exit(); -} - -/*------------------------------------------------------------------- - * ISR - *-------------------------------------------------------------------*/ -void dcd_int_handler(uint8_t rhport) { - uint_fast8_t is, txis, rxis; - uint32_t mxm_int, mxm_int_en, mxm_is; - uint32_t saved_index; - - /* Save current index register */ - saved_index = MXC_USBHS->index; - - is = MXC_USBHS->intrusb; /* read and clear interrupt status */ - txis = MXC_USBHS->intrin; /* read and clear interrupt status */ - rxis = MXC_USBHS->introut; /* read and clear interrupt status */ - - /* These USB interrupt flags are W1C. */ - /* Order of volatile accesses must be separated for IAR */ - mxm_int = MXC_USBHS->mxm_int; - mxm_int_en = MXC_USBHS->mxm_int_en; - mxm_is = mxm_int & mxm_int_en; - MXC_USBHS->mxm_int = mxm_is; - - is &= MXC_USBHS->intrusben; /* Clear disabled interrupts */ - - if (mxm_is & MXC_F_USBHS_MXM_INT_NOVBUS) { - dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); - } - if (is & MXC_F_USBHS_INTRUSB_SOF_INT) { - dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); - } - if (is & MXC_F_USBHS_INTRUSB_RESET_INT) { - process_bus_reset(rhport); - } - if (is & MXC_F_USBHS_INTRUSB_RESUME_INT) { - dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); - } - if (is & MXC_F_USBHS_INTRUSB_SUSPEND_INT) { - dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); - } - - txis &= MXC_USBHS->intrinen; /* Clear disabled interrupts */ - if (txis & MXC_F_USBHS_INTRIN_EP0_IN_INT) { - process_ep0(rhport); - txis &= ~TU_BIT(0); - } - while (txis) { - unsigned const num = __builtin_ctz(txis); - process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN)); - txis &= ~TU_BIT(num); - } - rxis &= MXC_USBHS->introuten; /* Clear disabled interrupts */ - while (rxis) { - unsigned const num = __builtin_ctz(rxis); - process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT)); - rxis &= ~TU_BIT(num); - } - - /* Restore register index before exiting ISR */ - MXC_USBHS->index = saved_index; -} - -#endif diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index a817c5d6e..ee36656fd 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -2,6 +2,7 @@ * The MIT License (MIT) * * Copyright (c) 2021 Koji KITAYAMA + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,8 +27,7 @@ #include "tusb_option.h" -#if CFG_TUD_ENABLED && \ - TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) +#if CFG_TUD_ENABLED #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) /* GCC warns that an address may be unaligned, even though @@ -35,43 +35,30 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); #endif +#include "musb_type.h" #include "device/dcd.h" -#if TU_CHECK_MCU(OPT_MCU_MSP432E4) - #include "musb_msp432e.h" - -#elif TU_CHECK_MCU(OPT_MCU_TM4C123, OPT_MCU_TM4C129) - #include "musb_tm4c.h" - - // HACK generalize later - #include "musb_type.h" - #define FIFO0_WORD FIFO0 - #define FIFO1_WORD FIFO1 - +// Following symbols must be defined by port header +// - musb_dcd_int_enable/disable/clear/get_enable +// - musb_dcd_int_handler_enter/exit +// - musb_dcd_epn_regs: Get memory mapped struct of end point registers +// - musb_dcd_ep0_regs: Get memory mapped struct of EP0 registers +// - musb_dcd_ctl_regs: Get memory mapped struct of control registers +// - musb_dcd_ep_get_fifo_ptr: Gets the address of the provided EP's FIFO +// - musb_dcd_setup_fifo/reset_fifo: Configuration of the EP's FIFO +#if TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) + #include "musb_ti.h" +#elif TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX78002) + #include "musb_max32.h" #else - #error "Unsupported MCUs" + #error "Unsupported MCU" #endif /*------------------------------------------------------------------ * MACRO TYPEDEF CONSTANT ENUM DECLARATION *------------------------------------------------------------------*/ -#define REQUEST_TYPE_INVALID (0xFFu) -typedef struct { - uint_fast16_t beg; /* offset of including first element */ - uint_fast16_t end; /* offset of excluding the last element */ -} free_block_t; - -typedef struct TU_ATTR_PACKED { - uint16_t TXMAXP; - uint8_t TXCSRL; - uint8_t TXCSRH; - uint16_t RXMAXP; - uint8_t RXCSRL; - uint8_t RXCSRH; - uint16_t RXCOUNT; - uint16_t RESERVED[3]; -} hw_endpoint_t; +#define REQUEST_TYPE_INVALID (0xFFu) typedef union { uint8_t u8; @@ -92,7 +79,7 @@ typedef struct uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */ int8_t status_out; pipe_state_t pipe0; - pipe_state_t pipe[2][7]; /* pipe[direction][endpoint number - 1] */ + pipe_state_t pipe[2][TUP_DCD_ENDPOINT_MAX-1]; /* pipe[direction][endpoint number - 1] */ uint16_t pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */ } dcd_data_t; @@ -102,126 +89,6 @@ typedef struct static dcd_data_t _dcd; -static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr) -{ - free_block_t *cur = beg; - for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ; - return cur; -} - -static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size) -{ - free_block_t *p = find_containing_block(blks, blks + num, addr); - TU_ASSERT(p != blks + num, -2); - if (p->beg == addr) { - /* Shrink block */ - p->beg = addr + size; - if (p->beg != p->end) return 0; - /* remove block */ - free_block_t *end = blks + num; - while (p + 1 < end) { - *p = *(p + 1); - ++p; - } - return -1; - } else { - /* Split into 2 blocks */ - free_block_t tmp = { - .beg = addr + size, - .end = p->end - }; - p->end = addr; - if (p->beg == p->end) { - if (tmp.beg != tmp.end) { - *p = tmp; - return 0; - } - /* remove block */ - free_block_t *end = blks + num; - while (p + 1 < end) { - *p = *(p + 1); - ++p; - } - return -1; - } - if (tmp.beg == tmp.end) return 0; - blks[num] = tmp; - return 1; - } -} - -static inline unsigned free_block_size(free_block_t const *blk) -{ - return blk->end - blk->beg; -} - -#if 0 -static inline void print_block_list(free_block_t const *blk, unsigned num) -{ - TU_LOG1("*************\r\n"); - for (unsigned i = 0; i < num; ++i) { - TU_LOG1(" Blk%u %u %u\r\n", i, blk->beg, blk->end); - ++blk; - } -} -#else -#define print_block_list(a,b) -#endif - -static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3) -{ - free_block_t free_blocks[2 * (TUP_DCD_ENDPOINT_MAX - 1)]; - unsigned num_blocks = 1; - - /* Initialize free memory block list */ - free_blocks[0].beg = 64 / 8; - free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */ - for (int i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { - uint_fast16_t addr; - int num; - USB0->EPIDX = i; - addr = USB0->TXFIFOADD; - if (addr) { - unsigned sz = USB0->TXFIFOSZ; - unsigned sft = (sz & USB_TXFIFOSZ_SIZE_M) + ((sz & USB_TXFIFOSZ_DPB) ? 1: 0); - num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); - TU_ASSERT(-2 < num, 0); - num_blocks += num; - print_block_list(free_blocks, num_blocks); - } - addr = USB0->RXFIFOADD; - if (addr) { - unsigned sz = USB0->RXFIFOSZ; - unsigned sft = (sz & USB_RXFIFOSZ_SIZE_M) + ((sz & USB_RXFIFOSZ_DPB) ? 1: 0); - num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); - TU_ASSERT(-2 < num, 0); - num_blocks += num; - print_block_list(free_blocks, num_blocks); - } - } - print_block_list(free_blocks, num_blocks); - - /* Find the best fit memory block */ - uint_fast16_t size_in_8byte_unit = 1 << size_in_log2_minus3; - free_block_t const *min = NULL; - uint_fast16_t min_sz = 0xFFFFu; - free_block_t const *end = &free_blocks[num_blocks]; - for (free_block_t const *cur = &free_blocks[0]; cur < end; ++cur) { - uint_fast16_t sz = free_block_size(cur); - if (sz < size_in_8byte_unit) continue; - if (size_in_8byte_unit == sz) return cur->beg; - if (sz < min_sz) min = cur; - } - TU_ASSERT(min, 0); - return min->beg; -} - -static inline volatile hw_endpoint_t* edpt_regs(unsigned epnum_minus1) -{ - volatile hw_endpoint_t *regs = (volatile hw_endpoint_t*)((uintptr_t)&USB0->TXMAXP1); - return regs + epnum_minus1; -} - static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; @@ -287,8 +154,10 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne static void process_setup_packet(uint8_t rhport) { uint32_t *p = (void*)&_dcd.setup_packet; - p[0] = USB0->FIFO0_WORD; - p[1] = USB0->FIFO0_WORD; + volatile uint32_t *fifo_ptr = musb_dcd_ep_get_fifo_ptr(rhport, 0); + volatile musb_dcd_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); + p[0] = *fifo_ptr; + p[1] = *fifo_ptr; _dcd.pipe0.buf = NULL; _dcd.pipe0.length = 0; @@ -299,12 +168,13 @@ static void process_setup_packet(uint8_t rhport) _dcd.remaining_ctrl = len; const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType); /* Clear RX FIFO and reverse the transaction direction */ - if (len && dir_in) USB0->CSRL0 = USB_CSRL0_RXRDYC; + if (len && dir_in) ep0_regs->CSRL0 = USB_CSRL0_RXRDYC; } -static bool handle_xfer_in(uint_fast8_t ep_addr) +static bool handle_xfer_in(uint8_t rhport, uint_fast8_t ep_addr) { - unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1; + unsigned epnum = tu_edpt_number(ep_addr); + unsigned epnum_minus1 = epnum - 1; pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; const unsigned rem = pipe->remaining; @@ -313,30 +183,32 @@ static bool handle_xfer_in(uint_fast8_t ep_addr) return true; } - volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1); + volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epnum); const unsigned mps = regs->TXMAXP; const unsigned len = TU_MIN(mps, rem); void *buf = pipe->buf; + volatile void *fifo_ptr = musb_dcd_ep_get_fifo_ptr(rhport, epnum); // TU_LOG1(" %p mps %d len %d rem %d\r\n", buf, mps, len, rem); if (len) { if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) { - pipe_read_write_packet_ff(buf, &USB0->FIFO1_WORD + epnum_minus1, len, TUSB_DIR_IN); + pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_IN); } else { - pipe_write_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len); + pipe_write_packet(buf, fifo_ptr, len); pipe->buf = buf + len; } pipe->remaining = rem - len; } regs->TXCSRL = USB_TXCSRL1_TXRDY; - // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum_minus1 + 1, regs->TXCSRL, rem - len); + // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum, regs->TXCSRL, rem - len); return false; } -static bool handle_xfer_out(uint_fast8_t ep_addr) +static bool handle_xfer_out(uint8_t rhport, uint_fast8_t ep_addr) { - unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1; + unsigned epnum = tu_edpt_number(ep_addr); + unsigned epnum_minus1 = epnum - 1; pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; - volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1); + volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epnum); // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, regs->RXCSRL); TU_ASSERT(regs->RXCSRL & USB_RXCSRL1_RXRDY); @@ -346,11 +218,12 @@ static bool handle_xfer_out(uint_fast8_t ep_addr) const unsigned vld = regs->RXCOUNT; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; + volatile void *fifo_ptr = musb_dcd_ep_get_fifo_ptr(rhport, epnum); if (len) { if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) { - pipe_read_write_packet_ff(buf, &USB0->FIFO1_WORD + epnum_minus1, len, TUSB_DIR_OUT); + pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_OUT); } else { - pipe_read_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len); + pipe_read_packet(buf, fifo_ptr, len); pipe->buf = buf + len; } pipe->remaining = rem - len; @@ -365,9 +238,8 @@ static bool handle_xfer_out(uint_fast8_t ep_addr) static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - (void)rhport; - - unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1; + unsigned epnum = tu_edpt_number(ep_addr); + unsigned epnum_minus1 = epnum - 1; unsigned dir_in = tu_edpt_dir(ep_addr); pipe_state_t *pipe = &_dcd.pipe[dir_in][epnum_minus1]; @@ -376,9 +248,9 @@ static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16 pipe->remaining = total_bytes; if (dir_in) { - handle_xfer_in(ep_addr); + handle_xfer_in(rhport, ep_addr); } else { - volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1); + volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epnum); if (regs->RXCSRL & USB_RXCSRL1_RXRDY) regs->RXCSRL = 0; } return true; @@ -388,7 +260,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ { (void)rhport; TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */ - + volatile musb_dcd_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); const unsigned req = _dcd.setup_packet.bmRequestType; TU_ASSERT(req != REQUEST_TYPE_INVALID || total_bytes == 0); @@ -399,7 +271,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ * may have already finished and received the next setup packet * without calling this function, so we have no choice but to * invoke the callback function of status packet here. */ - // TU_LOG1(" STATUS OUT USB0->CSRL0 = %x\r\n", USB0->CSRL0); + // TU_LOG1(" STATUS OUT ep0_regs->CSRL0 = %x\r\n", ep0_regs->CSRL0); _dcd.status_out = 0; if (req == REQUEST_TYPE_INVALID) { dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false); @@ -415,8 +287,9 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ TU_ASSERT(total_bytes <= _dcd.remaining_ctrl); const unsigned rem = _dcd.remaining_ctrl; const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes); + volatile void *fifo_ptr = musb_dcd_ep_get_fifo_ptr(rhport, 0); if (dir_in) { - pipe_write_packet(buffer, &USB0->FIFO0_WORD, len); + pipe_write_packet(buffer, fifo_ptr, len); _dcd.pipe0.buf = buffer + len; _dcd.pipe0.length = len; @@ -427,45 +300,46 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */ _dcd.status_out = 1; /* Flush TX FIFO and reverse the transaction direction. */ - USB0->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND; + ep0_regs->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND; } else { - USB0->CSRL0 = USB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */ + ep0_regs->CSRL0 = USB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */ } - // TU_LOG1(" IN USB0->CSRL0 = %x\r\n", USB0->CSRL0); + // TU_LOG1(" IN ep0_regs->CSRL0 = %x\r\n", ep0_regs->CSRL0); } else { - // TU_LOG1(" OUT USB0->CSRL0 = %x\r\n", USB0->CSRL0); + // TU_LOG1(" OUT ep0_regs->CSRL0 = %x\r\n", ep0_regs->CSRL0); _dcd.pipe0.buf = buffer; _dcd.pipe0.length = len; _dcd.pipe0.remaining = len; - USB0->CSRL0 = USB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */ + ep0_regs->CSRL0 = USB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */ } } else if (dir_in) { - // TU_LOG1(" STATUS IN USB0->CSRL0 = %x\r\n", USB0->CSRL0); + // TU_LOG1(" STATUS IN ep0_regs->CSRL0 = %x\r\n", ep0_regs->CSRL0); _dcd.pipe0.buf = NULL; _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; /* Clear RX FIFO and reverse the transaction direction */ - USB0->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; + ep0_regs->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; } return true; } static void process_ep0(uint8_t rhport) { - uint_fast8_t csrl = USB0->CSRL0; + volatile musb_dcd_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); + uint_fast8_t csrl = ep0_regs->CSRL0; - // TU_LOG1(" EP0 USB0->CSRL0 = %x\r\n", csrl); + // TU_LOG1(" EP0 ep0_regs->CSRL0 = %x\r\n", csrl); if (csrl & USB_CSRL0_STALLED) { /* Returned STALL packet to HOST. */ - USB0->CSRL0 = 0; /* Clear STALL */ + ep0_regs->CSRL0 = 0; /* Clear STALL */ return; } unsigned req = _dcd.setup_packet.bmRequestType; if (csrl & USB_CSRL0_SETEND) { TU_LOG1(" ABORT by the next packets\r\n"); - USB0->CSRL0 = USB_CSRL0_SETENDC; + ep0_regs->CSRL0 = USB_CSRL0_SETENDC; if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) { /* DATA stage was aborted by receiving STATUS or SETUP packet. */ _dcd.pipe0.buf = NULL; @@ -483,16 +357,17 @@ static void process_ep0(uint8_t rhport) /* Received SETUP or DATA OUT packet */ if (req == REQUEST_TYPE_INVALID) { /* SETUP */ - TU_ASSERT(sizeof(tusb_control_request_t) == USB0->COUNT0,); + TU_ASSERT(sizeof(tusb_control_request_t) == ep0_regs->COUNT0,); process_setup_packet(rhport); return; } if (_dcd.pipe0.buf) { /* DATA OUT */ - const unsigned vld = USB0->COUNT0; + const unsigned vld = ep0_regs->COUNT0; const unsigned rem = _dcd.pipe0.remaining; const unsigned len = TU_MIN(TU_MIN(rem, 64), vld); - pipe_read_packet(_dcd.pipe0.buf, &USB0->FIFO0_WORD, len); + volatile void *fifo_ptr = musb_dcd_ep_get_fifo_ptr(rhport, 0); + pipe_read_packet(_dcd.pipe0.buf, fifo_ptr, len); _dcd.pipe0.remaining = rem - len; _dcd.remaining_ctrl -= len; @@ -506,13 +381,15 @@ static void process_ep0(uint8_t rhport) return; } + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + /* When CSRL0 is zero, it means that completion of sending a any length packet * or receiving a zero length packet. */ if (req != REQUEST_TYPE_INVALID && !tu_edpt_dir(req)) { /* STATUS IN */ if (*(const uint16_t*)(uintptr_t)&_dcd.setup_packet == 0x0500) { /* The address must be changed on completion of the control transfer. */ - USB0->FADDR = (uint8_t)_dcd.setup_packet.wValue; + ctrl_regs->FADDR = (uint8_t)_dcd.setup_packet.wValue; } _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; dcd_event_xfer_complete(rhport, @@ -535,27 +412,28 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) { bool completed; const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned epn_minus1 = tu_edpt_number(ep_addr) - 1; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned epn_minus1 = epn - 1; - volatile hw_endpoint_t *regs = edpt_regs(epn_minus1); + volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); if (dir_in) { - // TU_LOG1(" TXCSRL%d = %x\r\n", epn_minus1 + 1, regs->TXCSRL); + // TU_LOG1(" TXCSRL%d = %x\r\n", epn, regs->TXCSRL); if (regs->TXCSRL & USB_TXCSRL1_STALLED) { regs->TXCSRL &= ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_UNDRN); return; } - completed = handle_xfer_in(ep_addr); + completed = handle_xfer_in(rhport, ep_addr); } else { - // TU_LOG1(" RXCSRL%d = %x\r\n", epn_minus1 + 1, regs->RXCSRL); + // TU_LOG1(" RXCSRL%d = %x\r\n", epn, regs->RXCSRL); if (regs->RXCSRL & USB_RXCSRL1_STALLED) { regs->RXCSRL &= ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_OVER); return; } - completed = handle_xfer_out(ep_addr); + completed = handle_xfer_out(rhport, ep_addr); } if (completed) { - pipe_state_t *pipe = &_dcd.pipe[dir_in][tu_edpt_number(ep_addr) - 1]; + pipe_state_t *pipe = &_dcd.pipe[dir_in][epn_minus1]; dcd_event_xfer_complete(rhport, ep_addr, pipe->length - pipe->remaining, XFER_RESULT_SUCCESS, true); @@ -564,6 +442,7 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) static void process_bus_reset(uint8_t rhport) { + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), * a control transfer state is SETUP or STATUS stage. */ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; @@ -571,18 +450,15 @@ static void process_bus_reset(uint8_t rhport) /* When pipe0.buf has not NULL, DATA stage works in progress. */ _dcd.pipe0.buf = NULL; - USB0->TXIE = 1; /* Enable only EP0 */ - USB0->RXIE = 0; + ctrl_regs->TXIE = 1; /* Enable only EP0 */ + ctrl_regs->RXIE = 0; /* Clear FIFO settings */ for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { - USB0->EPIDX = i; - USB0->TXFIFOSZ = 0; - USB0->TXFIFOADD = 0; - USB0->RXFIFOSZ = 0; - USB0->RXFIFOADD = 0; + musb_dcd_reset_fifo(rhport, i, 0); + musb_dcd_reset_fifo(rhport, i, 1); } - dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); + dcd_event_bus_reset(rhport, (ctrl_regs->POWER & USB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); } /*------------------------------------------------------------------ @@ -591,61 +467,60 @@ static void process_bus_reset(uint8_t rhport) void dcd_init(uint8_t rhport) { - (void)rhport; - USB0->IE |= USB_IE_SUSPND; - NVIC_ClearPendingIRQ(USB0_IRQn); - + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + ctrl_regs->IE |= USB_IE_SUSPND; + musb_dcd_int_clear(rhport); + musb_dcd_phy_init(rhport); dcd_connect(rhport); } void dcd_int_enable(uint8_t rhport) { - (void)rhport; - NVIC_EnableIRQ(USB0_IRQn); + musb_dcd_int_enable(rhport); } void dcd_int_disable(uint8_t rhport) { - (void)rhport; - NVIC_DisableIRQ(USB0_IRQn); + musb_dcd_int_disable(rhport); } // Receive Set Address request, mcu port must also include status IN response void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { - (void)rhport; (void)dev_addr; + volatile musb_dcd_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); _dcd.pipe0.buf = NULL; _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; /* Clear RX FIFO to return ACK. */ - USB0->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; + ep0_regs->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; } // Wake up host void dcd_remote_wakeup(uint8_t rhport) { - (void)rhport; - USB0->POWER |= USB_POWER_RESUME; + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + ctrl_regs->POWER |= USB_POWER_RESUME; unsigned cnt = SystemCoreClock / 1000; while (cnt--) __NOP(); - USB0->POWER &= ~USB_POWER_RESUME; + ctrl_regs->POWER &= ~USB_POWER_RESUME; } // Connect by enabling internal pull-up resistor on D+/D- void dcd_connect(uint8_t rhport) { - (void)rhport; - USB0->POWER |= USB_POWER_SOFTCONN; + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + ctrl_regs->POWER |= TUD_OPT_HIGH_SPEED ? USB_POWER_HSENAB : 0; + ctrl_regs->POWER |= USB_POWER_SOFTCONN; } // Disconnect by disabling internal pull-up resistor on D+/D- void dcd_disconnect(uint8_t rhport) { - (void)rhport; - USB0->POWER &= ~USB_POWER_SOFTCONN; + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + ctrl_regs->POWER &= ~USB_POWER_SOFTCONN; } void dcd_sof_enable(uint8_t rhport, bool en) @@ -663,8 +538,6 @@ void dcd_sof_enable(uint8_t rhport, bool en) // Configure endpoint's registers according to descriptor bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { - (void) rhport; - const unsigned ep_addr = ep_desc->bEndpointAddress; const unsigned epn = tu_edpt_number(ep_addr); const unsigned dir_in = tu_edpt_dir(ep_addr); @@ -678,7 +551,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) pipe->length = 0; pipe->remaining = 0; - volatile hw_endpoint_t *regs = edpt_regs(epn - 1); + volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); if (dir_in) { regs->TXMAXP = mps; regs->TXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_TXCSRH1_ISO : 0; @@ -686,7 +560,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; else regs->TXCSRL = USB_TXCSRL1_CLRDT; - USB0->TXIE |= TU_BIT(epn); + ctrl_regs->TXIE |= TU_BIT(epn); } else { regs->RXMAXP = mps; regs->RXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0; @@ -694,36 +568,25 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; else regs->RXCSRL = USB_RXCSRL1_CLRDT; - USB0->RXIE |= TU_BIT(epn); + ctrl_regs->RXIE |= TU_BIT(epn); } /* Setup FIFO */ - int size_in_log2_minus3 = 28 - TU_MIN(28, __CLZ((uint32_t)mps)); - if ((8u << size_in_log2_minus3) < mps) ++size_in_log2_minus3; - unsigned addr = find_free_memory(size_in_log2_minus3); - TU_ASSERT(addr); - - USB0->EPIDX = epn; - if (dir_in) { - USB0->TXFIFOADD = addr; - USB0->TXFIFOSZ = size_in_log2_minus3; - } else { - USB0->RXFIFOADD = addr; - USB0->RXFIFOSZ = size_in_log2_minus3; - } + musb_dcd_setup_fifo(rhport, epn, dir_in, mps); return true; } void dcd_edpt_close_all(uint8_t rhport) { - (void) rhport; - volatile hw_endpoint_t *regs = (volatile hw_endpoint_t *)(uintptr_t)&USB0->TXMAXP1; - unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); - NVIC_DisableIRQ(USB0_IRQn); - USB0->TXIE = 1; /* Enable only EP0 */ - USB0->RXIE = 0; + volatile musb_dcd_epn_regs_t *regs; + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + unsigned const ie = musb_dcd_get_int_enable(rhport); + musb_dcd_int_disable(rhport); + ctrl_regs->TXIE = 1; /* Enable only EP0 */ + ctrl_regs->RXIE = 0; for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { + regs = musb_dcd_epn_regs(rhport, i); regs->TXMAXP = 0; regs->TXCSRH = 0; if (regs->TXCSRL & USB_TXCSRL1_TXRDY) @@ -738,50 +601,41 @@ void dcd_edpt_close_all(uint8_t rhport) else regs->RXCSRL = USB_RXCSRL1_CLRDT; - USB0->EPIDX = i; - USB0->TXFIFOSZ = 0; - USB0->TXFIFOADD = 0; - USB0->RXFIFOSZ = 0; - USB0->RXFIFOADD = 0; + musb_dcd_reset_fifo(rhport, i, 0); + musb_dcd_reset_fifo(rhport, i, 1); + } - if (ie) NVIC_EnableIRQ(USB0_IRQn); + if (ie) musb_dcd_int_enable(rhport); } void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; unsigned const epn = tu_edpt_number(ep_addr); unsigned const dir_in = tu_edpt_dir(ep_addr); - hw_endpoint_t volatile *regs = edpt_regs(epn - 1); - unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); - NVIC_DisableIRQ(USB0_IRQn); + volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + unsigned const ie = musb_dcd_get_int_enable(rhport); + musb_dcd_int_disable(rhport); if (dir_in) { - USB0->TXIE &= ~TU_BIT(epn); + ctrl_regs->TXIE &= ~TU_BIT(epn); regs->TXMAXP = 0; regs->TXCSRH = 0; if (regs->TXCSRL & USB_TXCSRL1_TXRDY) regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; else regs->TXCSRL = USB_TXCSRL1_CLRDT; - - USB0->EPIDX = epn; - USB0->TXFIFOSZ = 0; - USB0->TXFIFOADD = 0; } else { - USB0->RXIE &= ~TU_BIT(epn); + ctrl_regs->RXIE &= ~TU_BIT(epn); regs->RXMAXP = 0; regs->RXCSRH = 0; if (regs->RXCSRL & USB_RXCSRL1_RXRDY) regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; else regs->RXCSRL = USB_RXCSRL1_CLRDT; - - USB0->EPIDX = epn; - USB0->RXFIFOSZ = 0; - USB0->RXFIFOADD = 0; } - if (ie) NVIC_EnableIRQ(USB0_IRQn); + musb_dcd_reset_fifo(rhport, epn, dir_in); + if (ie) musb_dcd_int_enable(rhport); } // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack @@ -791,14 +645,14 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t bool ret; // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes); unsigned const epnum = tu_edpt_number(ep_addr); - unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); - NVIC_DisableIRQ(USB0_IRQn); + unsigned const ie = musb_dcd_get_int_enable(rhport); + musb_dcd_int_disable(rhport); if (epnum) { _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] &= ~TU_BIT(epnum - 1); ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes); } else ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes); - if (ie) NVIC_EnableIRQ(USB0_IRQn); + if (ie) musb_dcd_int_enable(rhport); return ret; } @@ -810,29 +664,29 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_ // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes); unsigned const epnum = tu_edpt_number(ep_addr); TU_ASSERT(epnum); - unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); - NVIC_DisableIRQ(USB0_IRQn); + unsigned const ie = musb_dcd_get_int_enable(rhport); + musb_dcd_int_disable(rhport); _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] |= TU_BIT(epnum - 1); ret = edpt_n_xfer(rhport, ep_addr, (uint8_t*)ff, total_bytes); - if (ie) NVIC_EnableIRQ(USB0_IRQn); + if (ie) musb_dcd_int_enable(rhport); return ret; } // Stall endpoint void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; unsigned const epn = tu_edpt_number(ep_addr); - unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); - NVIC_DisableIRQ(USB0_IRQn); + unsigned const ie = musb_dcd_get_int_enable(rhport); + musb_dcd_int_disable(rhport); if (0 == epn) { + volatile musb_dcd_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); if (!ep_addr) { /* Ignore EP80 */ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; _dcd.pipe0.buf = NULL; - USB0->CSRL0 = USB_CSRL0_STALL; + ep0_regs->CSRL0 = USB_CSRL0_STALL; } } else { - volatile hw_endpoint_t *regs = edpt_regs(epn - 1); + volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); if (tu_edpt_dir(ep_addr)) { /* IN */ regs->TXCSRL = USB_TXCSRL1_STALL; } else { /* OUT */ @@ -840,7 +694,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) regs->RXCSRL = USB_RXCSRL1_STALL; } } - if (ie) NVIC_EnableIRQ(USB0_IRQn); + if (ie) musb_dcd_int_enable(rhport); } // clear stall, data toggle is also reset to DATA0 @@ -848,15 +702,15 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { (void)rhport; unsigned const epn = tu_edpt_number(ep_addr); - hw_endpoint_t volatile *regs = edpt_regs(epn - 1); - unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); - NVIC_DisableIRQ(USB0_IRQn); + musb_dcd_epn_regs_t volatile *regs = musb_dcd_epn_regs(rhport, epn); + unsigned const ie = musb_dcd_get_int_enable(rhport); + musb_dcd_int_disable(rhport); if (tu_edpt_dir(ep_addr)) { /* IN */ regs->TXCSRL = USB_TXCSRL1_CLRDT; } else { /* OUT */ regs->RXCSRL = USB_RXCSRL1_CLRDT; } - if (ie) NVIC_EnableIRQ(USB0_IRQn); + if (ie) musb_dcd_int_enable(rhport); } /*------------------------------------------------------------------- @@ -865,13 +719,18 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) void dcd_int_handler(uint8_t rhport) { uint_fast8_t is, txis, rxis; + volatile musb_dcd_ctl_regs_t *ctrl_regs; + + //Part specific ISR setup/entry + musb_dcd_int_handler_enter(rhport); - is = USB0->IS; /* read and clear interrupt status */ - txis = USB0->TXIS; /* read and clear interrupt status */ - rxis = USB0->RXIS; /* read and clear interrupt status */ + ctrl_regs = musb_dcd_ctl_regs(rhport); + is = ctrl_regs->IS; /* read and clear interrupt status */ + txis = ctrl_regs->TXIS; /* read and clear interrupt status */ + rxis = ctrl_regs->RXIS; /* read and clear interrupt status */ // TU_LOG1("D%2x T%2x R%2x\r\n", is, txis, rxis); - is &= USB0->IE; /* Clear disabled interrupts */ + is &= ctrl_regs->IE; /* Clear disabled interrupts */ if (is & USB_IS_DISCON) { } if (is & USB_IS_SOF) { @@ -887,7 +746,7 @@ void dcd_int_handler(uint8_t rhport) dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); } - txis &= USB0->TXIE; /* Clear disabled interrupts */ + txis &= ctrl_regs->TXIE; /* Clear disabled interrupts */ if (txis & USB_TXIE_EP0) { process_ep0(rhport); txis &= ~TU_BIT(0); @@ -897,12 +756,15 @@ void dcd_int_handler(uint8_t rhport) process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN)); txis &= ~TU_BIT(num); } - rxis &= USB0->RXIE; /* Clear disabled interrupts */ + rxis &= ctrl_regs->RXIE; /* Clear disabled interrupts */ while (rxis) { unsigned const num = __builtin_ctz(rxis); process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT)); rxis &= ~TU_BIT(num); } + + //Part specific ISR exit + musb_dcd_int_handler_exit(rhport); } #endif diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c index 5312c2812..8fc225676 100644 --- a/src/portable/mentor/musb/hcd_musb.c +++ b/src/portable/mentor/musb/hcd_musb.c @@ -37,16 +37,10 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); #include "host/hcd.h" -#if TU_CHECK_MCU(OPT_MCU_MSP432E4) - #include "musb_msp432e.h" - -#elif TU_CHECK_MCU(OPT_MCU_TM4C123, OPT_MCU_TM4C129) - #include "musb_tm4c.h" - - // HACK generalize later - #include "musb_type.h" - #define FIFO0_WORD FIFO0 +#include "musb_type.h" +#if TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) + #include "musb_ti.h" #else #error "Unsupported MCUs" #endif diff --git a/src/portable/mentor/musb/musb_max32.h b/src/portable/mentor/musb/musb_max32.h new file mode 100644 index 000000000..297a695f8 --- /dev/null +++ b/src/portable/mentor/musb/musb_max32.h @@ -0,0 +1,221 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_MUSB_MAX32_H_ +#define _TUSB_MUSB_MAX32_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#if TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX78002) + #include "mxc_device.h" + #include "usbhs_regs.h" +#else + #error "Unsupported MCUs" +#endif + + +#if CFG_TUD_ENABLED +#define USBHS_M31_CLOCK_RECOVERY + +// Mapping of peripheral instances to port. Currently just 1. +static mxc_usbhs_regs_t* const musb_periph_inst[] = { + MXC_USBHS +}; + +// Mapping of IRQ numbers to port. Currently just 1. +static const IRQn_Type musb_irqs[] = { + USB_IRQn +}; + +TU_ATTR_ALWAYS_INLINE +static inline void musb_dcd_int_enable(uint8_t rhport) +{ + NVIC_EnableIRQ(musb_irqs[rhport]); +} + +TU_ATTR_ALWAYS_INLINE +static inline void musb_dcd_int_disable(uint8_t rhport) +{ + NVIC_DisableIRQ(musb_irqs[rhport]); +} + +TU_ATTR_ALWAYS_INLINE +static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) +{ + return NVIC_GetEnableIRQ(musb_irqs[rhport]); +} + +TU_ATTR_ALWAYS_INLINE +static inline void musb_dcd_int_clear(uint8_t rhport) +{ + NVIC_ClearPendingIRQ(musb_irqs[rhport]); +} + +//Used to save and restore user's register map when interrupt occurs +static volatile unsigned isr_saved_index = 0; + +static inline void musb_dcd_int_handler_enter(uint8_t rhport) +{ + uint32_t mxm_int, mxm_int_en, mxm_is; + + //save current register index + isr_saved_index = musb_periph_inst[rhport]->index; + + //Handle PHY specific events + mxm_int = musb_periph_inst[rhport]->mxm_int; + mxm_int_en = musb_periph_inst[rhport]->mxm_int_en; + mxm_is = mxm_int & mxm_int_en; + musb_periph_inst[rhport]->mxm_int = mxm_is; + + if (mxm_is & MXC_F_USBHS_MXM_INT_NOVBUS) { + dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); + } +} + +static inline void musb_dcd_int_handler_exit(uint8_t rhport) +{ + //restore register index + musb_periph_inst[rhport]->index = isr_saved_index; +} + +static inline void musb_dcd_phy_init(uint8_t rhport) +{ + //Interrupt for VBUS disconnect + musb_periph_inst[rhport]->mxm_int_en |= MXC_F_USBHS_MXM_INT_EN_NOVBUS; + + musb_dcd_int_clear(rhport); + + //Unsuspend the MAC + musb_periph_inst[rhport]->mxm_suspend = 0; + + // Configure PHY + musb_periph_inst[rhport]->m31_phy_xcfgi_31_0 = (0x1 << 3) | (0x1 << 11); + musb_periph_inst[rhport]->m31_phy_xcfgi_63_32 = 0; + musb_periph_inst[rhport]->m31_phy_xcfgi_95_64 = 0x1 << (72 - 64); + musb_periph_inst[rhport]->m31_phy_xcfgi_127_96 = 0; + + + #ifdef USBHS_M31_CLOCK_RECOVERY + musb_periph_inst[rhport]->m31_phy_noncry_rstb = 1; + musb_periph_inst[rhport]->m31_phy_noncry_en = 1; + musb_periph_inst[rhport]->m31_phy_outclksel = 0; + musb_periph_inst[rhport]->m31_phy_coreclkin = 0; + musb_periph_inst[rhport]->m31_phy_xtlsel = 2; /* Select 25 MHz clock */ + #else + musb_periph_inst[rhport]->m31_phy_noncry_rstb = 0; + musb_periph_inst[rhport]->m31_phy_noncry_en = 0; + musb_periph_inst[rhport]->m31_phy_outclksel = 1; + musb_periph_inst[rhport]->m31_phy_coreclkin = 1; + musb_periph_inst[rhport]->m31_phy_xtlsel = 3; /* Select 30 MHz clock */ + #endif + musb_periph_inst[rhport]->m31_phy_pll_en = 1; + musb_periph_inst[rhport]->m31_phy_oscouten = 1; + + /* Reset PHY */ + musb_periph_inst[rhport]->m31_phy_ponrst = 0; + musb_periph_inst[rhport]->m31_phy_ponrst = 1; +} + +static inline volatile musb_dcd_ctl_regs_t* musb_dcd_ctl_regs(uint8_t rhport) +{ + volatile musb_dcd_ctl_regs_t *regs = (volatile musb_dcd_ctl_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->faddr)); + return regs; +} + +static inline volatile musb_dcd_epn_regs_t* musb_dcd_epn_regs(uint8_t rhport, unsigned epnum) +{ + //Need to set index to map EP registers + musb_periph_inst[rhport]->index = epnum; + volatile musb_dcd_epn_regs_t *regs = (volatile musb_dcd_epn_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->inmaxp)); + return regs; +} + +static inline volatile musb_dcd_ep0_regs_t* musb_dcd_ep0_regs(uint8_t rhport) +{ + //Need to set index to map EP0 registers + musb_periph_inst[rhport]->index = 0; + volatile musb_dcd_ep0_regs_t *regs = (volatile musb_dcd_ep0_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->csr0)); + return regs; +} + +static volatile void *musb_dcd_ep_get_fifo_ptr(uint8_t rhport, unsigned epnum) +{ + volatile uint32_t *ptr; + + ptr = &(musb_periph_inst[rhport]->fifo0); + ptr += epnum; + + return (volatile void *) ptr; +} + + +static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) +{ + (void)mps; + + //Most likely the caller has already grabbed the right register block. But + //as a precaution save and restore the register bank anyways + unsigned saved_index = musb_periph_inst[rhport]->index; + + musb_periph_inst[rhport]->index = epnum; + + //Disable double buffering + if(dir_in) { + musb_periph_inst[rhport]->incsru |= (MXC_F_USBHS_INCSRU_DPKTBUFDIS | MXC_F_USBHS_INCSRU_MODE); + } else { + musb_periph_inst[rhport]->outcsru |= (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS); + } + + musb_periph_inst[rhport]->index = saved_index; +} + +static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in) +{ + //Most likely the caller has already grabbed the right register block. But + //as a precaution save and restore the register bank anyways + unsigned saved_index = musb_periph_inst[rhport]->index; + + musb_periph_inst[rhport]->index = epnum; + + //Disable double buffering + if(dir_in) { + musb_periph_inst[rhport]->incsru |= (MXC_F_USBHS_INCSRU_DPKTBUFDIS); + } else { + musb_periph_inst[rhport]->outcsru |= (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS); + } + + musb_periph_inst[rhport]->index = saved_index; +} + +#endif // CFG_TUD_ENABLED + +#ifdef __cplusplus + } +#endif + +#endif // _TUSB_MUSB_MAX32_H_ diff --git a/src/portable/mentor/musb/musb_msp432e.h b/src/portable/mentor/musb/musb_msp432e.h deleted file mode 100644 index fce21de88..000000000 --- a/src/portable/mentor/musb/musb_msp432e.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2021, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifndef _TUSB_MUSB_MSP432E_H_ -#define _TUSB_MUSB_MSP432E_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -#include "msp.h" - -#ifdef __cplusplus - } -#endif - -#endif diff --git a/src/portable/mentor/musb/musb_ti.h b/src/portable/mentor/musb/musb_ti.h new file mode 100644 index 000000000..dbf82f391 --- /dev/null +++ b/src/portable/mentor/musb/musb_ti.h @@ -0,0 +1,285 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_MUSB_TI_H_ +#define _TUSB_MUSB_TI_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#if CFG_TUSB_MCU == OPT_MCU_TM4C123 + #include "TM4C123.h" + #define FIFO0_WORD FIFO0 + #define FIFO1_WORD FIFO1 +//#elif CFG_TUSB_MCU == OPT_MCU_TM4C129 +#elif CFG_TUSB_MCU == OPT_MCU_MSP432E4 + #include "msp.h" +#else + #error "Unsupported MCUs" +#endif + + +// Header supports both device and host modes. Only include whats necessary +#if CFG_TUD_ENABLED + +// Mapping of peripheral instances to port. Currently just 1. +static USB0_Type* const musb_periph_inst[] = { + USB0 +}; + +// Mapping of IRQ numbers to port. Currently just 1. +static const IRQn_Type musb_irqs[] = { + USB0_IRQn +}; + +static inline void musb_dcd_phy_init(uint8_t rhport){ + (void)rhport; + //Nothing to do for this part +} + +TU_ATTR_ALWAYS_INLINE +static inline void musb_dcd_int_enable(uint8_t rhport) +{ + NVIC_EnableIRQ(musb_irqs[rhport]); +} + +TU_ATTR_ALWAYS_INLINE +static inline void musb_dcd_int_disable(uint8_t rhport) +{ + NVIC_DisableIRQ(musb_irqs[rhport]); +} + +TU_ATTR_ALWAYS_INLINE +static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) +{ + return NVIC_GetEnableIRQ(musb_irqs[rhport]); +} + +TU_ATTR_ALWAYS_INLINE +static inline void musb_dcd_int_clear(uint8_t rhport) +{ + NVIC_ClearPendingIRQ(musb_irqs[rhport]); +} + +static inline void musb_dcd_int_handler_enter(uint8_t rhport){ + (void)rhport; + //Nothing to do for this part +} + +static inline void musb_dcd_int_handler_exit(uint8_t rhport){ + (void)rhport; + //Nothing to do for this part +} + +static inline volatile musb_dcd_ctl_regs_t* musb_dcd_ctl_regs(uint8_t rhport) +{ + volatile musb_dcd_ctl_regs_t *regs = (volatile musb_dcd_ctl_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->FADDR)); + return regs; +} + +static inline volatile musb_dcd_epn_regs_t* musb_dcd_epn_regs(uint8_t rhport, unsigned epnum) +{ + uintptr_t baseptr = (uintptr_t)&(musb_periph_inst[rhport]->TXMAXP1); + + //On the TI parts, the epn registers are 16-bytes apart. The core regs defined + //by musb_dcd_epn_regs and 6 reserved/other use bytes + volatile musb_dcd_epn_regs_t *regs = (volatile musb_dcd_epn_regs_t*)(baseptr + ((epnum - 1)*16)); + return regs; +} + +static inline volatile musb_dcd_ep0_regs_t* musb_dcd_ep0_regs(uint8_t rhport) +{ + volatile musb_dcd_ep0_regs_t *regs = (volatile musb_dcd_ep0_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->CSRL0)); + return regs; +} + +static volatile void *musb_dcd_ep_get_fifo_ptr(uint8_t rhport, unsigned epnum) +{ + if(epnum){ + return (volatile void *)(&(musb_periph_inst[rhport]->FIFO1_WORD) + (epnum - 1)); + } else { + return (volatile void *)&(musb_periph_inst[rhport]->FIFO0_WORD); + } +} + + +typedef struct { + uint_fast16_t beg; /* offset of including first element */ + uint_fast16_t end; /* offset of excluding the last element */ +} free_block_t; + +static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr) +{ + free_block_t *cur = beg; + for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ; + return cur; +} + +static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size) +{ + free_block_t *p = find_containing_block(blks, blks + num, addr); + TU_ASSERT(p != blks + num, -2); + if (p->beg == addr) { + /* Shrink block */ + p->beg = addr + size; + if (p->beg != p->end) return 0; + /* remove block */ + free_block_t *end = blks + num; + while (p + 1 < end) { + *p = *(p + 1); + ++p; + } + return -1; + } else { + /* Split into 2 blocks */ + free_block_t tmp = { + .beg = addr + size, + .end = p->end + }; + p->end = addr; + if (p->beg == p->end) { + if (tmp.beg != tmp.end) { + *p = tmp; + return 0; + } + /* remove block */ + free_block_t *end = blks + num; + while (p + 1 < end) { + *p = *(p + 1); + ++p; + } + return -1; + } + if (tmp.beg == tmp.end) return 0; + blks[num] = tmp; + return 1; + } +} + +static inline unsigned free_block_size(free_block_t const *blk) +{ + return blk->end - blk->beg; +} + +#if 0 +static inline void print_block_list(free_block_t const *blk, unsigned num) +{ + TU_LOG1("*************\r\n"); + for (unsigned i = 0; i < num; ++i) { + TU_LOG1(" Blk%u %u %u\r\n", i, blk->beg, blk->end); + ++blk; + } +} +#else +#define print_block_list(a,b) +#endif + +static unsigned find_free_memory(uint8_t rhport, uint_fast16_t size_in_log2_minus3) +{ + free_block_t free_blocks[2 * (TUP_DCD_ENDPOINT_MAX - 1)]; + unsigned num_blocks = 1; + + /* Initialize free memory block list */ + free_blocks[0].beg = 64 / 8; + free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */ + for (int i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { + uint_fast16_t addr; + int num; + musb_periph_inst[rhport]->EPIDX = i; + addr = musb_periph_inst[rhport]->TXFIFOADD; + if (addr) { + unsigned sz = musb_periph_inst[rhport]->TXFIFOSZ; + unsigned sft = (sz & USB_TXFIFOSZ_SIZE_M) + ((sz & USB_TXFIFOSZ_DPB) ? 1: 0); + num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); + TU_ASSERT(-2 < num, 0); + num_blocks += num; + print_block_list(free_blocks, num_blocks); + } + addr = musb_periph_inst[rhport]->RXFIFOADD; + if (addr) { + unsigned sz = musb_periph_inst[rhport]->RXFIFOSZ; + unsigned sft = (sz & USB_RXFIFOSZ_SIZE_M) + ((sz & USB_RXFIFOSZ_DPB) ? 1: 0); + num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); + TU_ASSERT(-2 < num, 0); + num_blocks += num; + print_block_list(free_blocks, num_blocks); + } + } + print_block_list(free_blocks, num_blocks); + + /* Find the best fit memory block */ + uint_fast16_t size_in_8byte_unit = 1 << size_in_log2_minus3; + free_block_t const *min = NULL; + uint_fast16_t min_sz = 0xFFFFu; + free_block_t const *end = &free_blocks[num_blocks]; + for (free_block_t const *cur = &free_blocks[0]; cur < end; ++cur) { + uint_fast16_t sz = free_block_size(cur); + if (sz < size_in_8byte_unit) continue; + if (size_in_8byte_unit == sz) return cur->beg; + if (sz < min_sz) min = cur; + } + TU_ASSERT(min, 0); + return min->beg; +} + + +static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) +{ + int size_in_log2_minus3 = 28 - TU_MIN(28, __CLZ((uint32_t)mps)); + if ((8u << size_in_log2_minus3) < mps) ++size_in_log2_minus3; + unsigned addr = find_free_memory(rhport, size_in_log2_minus3); + TU_ASSERT(addr,); + + musb_periph_inst[rhport]->EPIDX = epnum; + if (dir_in) { + musb_periph_inst[rhport]->TXFIFOADD = addr; + musb_periph_inst[rhport]->TXFIFOSZ = size_in_log2_minus3; + } else { + musb_periph_inst[rhport]->RXFIFOADD = addr; + musb_periph_inst[rhport]->RXFIFOSZ = size_in_log2_minus3; + } +} + +static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in) +{ + musb_periph_inst[rhport]->EPIDX = epnum; + if (dir_in) { + musb_periph_inst[rhport]->TXFIFOADD = 0; + musb_periph_inst[rhport]->TXFIFOSZ = 0; + } else { + musb_periph_inst[rhport]->RXFIFOADD = 0; + musb_periph_inst[rhport]->RXFIFOSZ = 0; + } +} + +#endif // CFG_TUD_ENABLED + +#ifdef __cplusplus + } +#endif + +#endif // _TUSB_MUSB_TI_H_ diff --git a/src/portable/mentor/musb/musb_tm4c.h b/src/portable/mentor/musb/musb_tm4c.h deleted file mode 100644 index 65a1751b0..000000000 --- a/src/portable/mentor/musb/musb_tm4c.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2021, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifndef _TUSB_MUSB_TM4C_H_ -#define _TUSB_MUSB_TM4C_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -#if CFG_TUSB_MCU == OPT_MCU_TM4C123 - #include "TM4C123.h" -//#elif CFG_TUSB_MCU == OPT_MCU_TM4C129 -#else - #error "Unsupported MCUs" -#endif - -#ifdef __cplusplus - } -#endif - -#endif diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h index 8f83305a5..e8af8f19b 100644 --- a/src/portable/mentor/musb/musb_type.h +++ b/src/portable/mentor/musb/musb_type.h @@ -35,10 +35,43 @@ #ifndef _TUSB_MUSB_TYPE_H_ #define _TUSB_MUSB_TYPE_H_ +#include "stdint.h" + #ifdef __cplusplus extern "C" { #endif +// Endpoint register mapping. Non-zero end points. +typedef struct TU_ATTR_PACKED { + uint16_t TXMAXP; + uint8_t TXCSRL; + uint8_t TXCSRH; + uint16_t RXMAXP; + uint8_t RXCSRL; + uint8_t RXCSRH; + uint16_t RXCOUNT; +} musb_dcd_epn_regs_t; + +// Endpoint 0 register mapping. +typedef struct TU_ATTR_PACKED { + uint8_t CSRL0; + uint8_t CSRH0; + uint32_t RESERVED; + uint8_t COUNT0; +} musb_dcd_ep0_regs_t; + +// Control register mapping +typedef struct TU_ATTR_PACKED { + uint8_t FADDR; + uint8_t POWER; + uint16_t TXIS; + uint16_t RXIS; + uint16_t TXIE; + uint16_t RXIE; + uint8_t IS; + uint8_t IE; +} musb_dcd_ctl_regs_t; + //***************************************************************************** // // The following are defines for the bit fields in the USB_O_FADDR register. -- cgit v1.3.1 From 0be427bae95ef0fe94cb6f0b405eb5c3bbae160a Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 14 Aug 2024 23:59:35 +0700 Subject: use max32 cmsis, fix NVIC_GetEnableIRQ() not defined when using with CMISIS < 5 --- hw/bsp/max32650/family.c | 16 ++++++++++++++-- hw/bsp/max32650/family.cmake | 1 - hw/bsp/max32650/family.mk | 3 +-- hw/bsp/max32666/family.c | 15 +++++++++++++-- hw/bsp/max32666/family.cmake | 1 - hw/bsp/max32666/family.mk | 1 - hw/bsp/max32690/family.c | 16 ++++++++++++++-- hw/bsp/max32690/family.cmake | 1 - hw/bsp/max32690/family.mk | 1 - hw/bsp/max78002/family.c | 15 +++++++++++++-- hw/bsp/max78002/family.cmake | 1 - hw/bsp/max78002/family.mk | 1 - src/portable/mentor/musb/musb_max32.h | 33 ++++++++++++++------------------- tools/get_deps.py | 2 +- 14 files changed, 70 insertions(+), 37 deletions(-) (limited to 'hw') diff --git a/hw/bsp/max32650/family.c b/hw/bsp/max32650/family.c index 16b5233b9..89a5db160 100644 --- a/hw/bsp/max32650/family.c +++ b/hw/bsp/max32650/family.c @@ -24,12 +24,24 @@ * This file is part of the TinyUSB stack. */ -#include "board.h" -#include "bsp/board_api.h" +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() +#endif + #include "gpio.h" +#include "mxc_sys.h" #include "mxc_device.h" #include "uart.h" +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "board.h" +#include "bsp/board_api.h" + + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake index 92b68a1cd..8c4f286a2 100644 --- a/hw/bsp/max32650/family.cmake +++ b/hw/bsp/max32650/family.cmake @@ -74,7 +74,6 @@ function(add_board_target BOARD_TARGET) ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMSIS_5}/CMSIS/Core/Include ${MAX32_CMSIS}/Include ${MAX32_CMSIS}/Device/Maxim/MAX32650/Include ${MAX32_PERIPH}/Include/MAX32650 diff --git a/hw/bsp/max32650/family.mk b/hw/bsp/max32650/family.mk index 359261216..d2fc293e4 100644 --- a/hw/bsp/max32650/family.mk +++ b/hw/bsp/max32650/family.mk @@ -82,14 +82,13 @@ SRC_C += \ $(PERIPH_SRC)/ICC/icc_reva.c \ $(PERIPH_SRC)/ICC/icc_common.c \ $(PERIPH_SRC)/TPU/tpu_me10.c \ - $(PERIPH_SRC)/TPU/tpu_reva.c \ + $(PERIPH_SRC)/TPU/tpu_reva.c \ $(PERIPH_SRC)/UART/uart_common.c \ $(PERIPH_SRC)/UART/uart_me10.c \ $(PERIPH_SRC)/UART/uart_reva.c \ INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(MAX32_CMSIS)/Include \ $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32650/Include \ $(TOP)/$(MAX32_PERIPH)/Include/MAX32650 \ diff --git a/hw/bsp/max32666/family.c b/hw/bsp/max32666/family.c index 1398e09ff..8ee4b6762 100644 --- a/hw/bsp/max32666/family.c +++ b/hw/bsp/max32666/family.c @@ -24,13 +24,24 @@ * This file is part of the TinyUSB stack. */ -#include "board.h" -#include "bsp/board_api.h" +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() +#endif + #include "gpio.h" +#include "mxc_sys.h" #include "mcr_regs.h" #include "mxc_device.h" #include "uart.h" +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "board.h" +#include "bsp/board_api.h" + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ diff --git a/hw/bsp/max32666/family.cmake b/hw/bsp/max32666/family.cmake index eb9d2175f..4a3f1a428 100644 --- a/hw/bsp/max32666/family.cmake +++ b/hw/bsp/max32666/family.cmake @@ -70,7 +70,6 @@ function(add_board_target BOARD_TARGET) ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMSIS_5}/CMSIS/Core/Include ${MAX32_CMSIS}/Include ${MAX32_CMSIS}/Device/Maxim/MAX32665/Include ${MAX32_PERIPH}/Include/MAX32665 diff --git a/hw/bsp/max32666/family.mk b/hw/bsp/max32666/family.mk index 720d994ef..b4f7d1e57 100644 --- a/hw/bsp/max32666/family.mk +++ b/hw/bsp/max32666/family.mk @@ -82,7 +82,6 @@ SRC_C += \ INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(MAX32_CMSIS)/Include \ $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32665/Include \ $(TOP)/$(MAX32_PERIPH)/Include/MAX32665 \ diff --git a/hw/bsp/max32690/family.c b/hw/bsp/max32690/family.c index f4998bdbe..2418168d4 100644 --- a/hw/bsp/max32690/family.c +++ b/hw/bsp/max32690/family.c @@ -24,13 +24,25 @@ * This file is part of the TinyUSB stack. */ -#include "board.h" -#include "bsp/board_api.h" +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() +#endif + #include "gpio.h" +#include "mxc_sys.h" #include "mcr_regs.h" #include "mxc_device.h" #include "uart.h" +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "board.h" +#include "bsp/board_api.h" + + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake index 2a9422dbe..58647e432 100644 --- a/hw/bsp/max32690/family.cmake +++ b/hw/bsp/max32690/family.cmake @@ -75,7 +75,6 @@ function(add_board_target BOARD_TARGET) ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMSIS_5}/CMSIS/Core/Include ${MAX32_CMSIS}/Include ${MAX32_CMSIS}/Device/Maxim/MAX32690/Include ${MAX32_PERIPH}/Include/MAX32690 diff --git a/hw/bsp/max32690/family.mk b/hw/bsp/max32690/family.mk index c533cf4a4..d4df8ef2f 100644 --- a/hw/bsp/max32690/family.mk +++ b/hw/bsp/max32690/family.mk @@ -90,7 +90,6 @@ SRC_C += \ INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(MAX32_CMSIS)/Include \ $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32690/Include \ $(TOP)/$(MAX32_PERIPH)/Include/MAX32690 \ diff --git a/hw/bsp/max78002/family.c b/hw/bsp/max78002/family.c index 7758083a2..8d51f141c 100644 --- a/hw/bsp/max78002/family.c +++ b/hw/bsp/max78002/family.c @@ -24,13 +24,24 @@ * This file is part of the TinyUSB stack. */ -#include "board.h" -#include "bsp/board_api.h" +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() +#endif + #include "gpio.h" +#include "mxc_sys.h" #include "mcr_regs.h" #include "mxc_device.h" #include "uart.h" +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "board.h" +#include "bsp/board_api.h" + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake index 090f1da43..446930bd8 100644 --- a/hw/bsp/max78002/family.cmake +++ b/hw/bsp/max78002/family.cmake @@ -72,7 +72,6 @@ function(add_board_target BOARD_TARGET) ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMSIS_5}/CMSIS/Core/Include ${MAX32_CMSIS}/Include ${MAX32_CMSIS}/Device/Maxim/MAX78002/Include ${MAX32_PERIPH}/Include/MAX78002 diff --git a/hw/bsp/max78002/family.mk b/hw/bsp/max78002/family.mk index 5297815de..997816261 100644 --- a/hw/bsp/max78002/family.mk +++ b/hw/bsp/max78002/family.mk @@ -87,7 +87,6 @@ SRC_C += \ INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(MAX32_CMSIS)/Include \ $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX78002/Include \ $(TOP)/$(MAX32_PERIPH)/Include/MAX78002 \ diff --git a/src/portable/mentor/musb/musb_max32.h b/src/portable/mentor/musb/musb_max32.h index 297a695f8..bc6ce76dd 100644 --- a/src/portable/mentor/musb/musb_max32.h +++ b/src/portable/mentor/musb/musb_max32.h @@ -31,13 +31,8 @@ extern "C" { #endif -#if TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX78002) - #include "mxc_device.h" - #include "usbhs_regs.h" -#else - #error "Unsupported MCUs" -#endif - +#include "mxc_device.h" +#include "usbhs_regs.h" #if CFG_TUD_ENABLED #define USBHS_M31_CLOCK_RECOVERY @@ -48,39 +43,39 @@ static mxc_usbhs_regs_t* const musb_periph_inst[] = { }; // Mapping of IRQ numbers to port. Currently just 1. -static const IRQn_Type musb_irqs[] = { +static const IRQn_Type musb_irqs[] = { USB_IRQn }; TU_ATTR_ALWAYS_INLINE -static inline void musb_dcd_int_enable(uint8_t rhport) -{ +static inline void musb_dcd_int_enable(uint8_t rhport) { NVIC_EnableIRQ(musb_irqs[rhport]); } TU_ATTR_ALWAYS_INLINE -static inline void musb_dcd_int_disable(uint8_t rhport) -{ +static inline void musb_dcd_int_disable(uint8_t rhport) { NVIC_DisableIRQ(musb_irqs[rhport]); } TU_ATTR_ALWAYS_INLINE -static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) -{ +static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) { + #ifdef NVIC_GetEnableIRQ // only defined in CMSIS 5 return NVIC_GetEnableIRQ(musb_irqs[rhport]); + #else + uint32_t IRQn = (uint32_t) musb_irqs[rhport]; + return ((NVIC->ISER[IRQn >> 5UL] & (1UL << (IRQn & 0x1FUL))) != 0UL) ? 1UL : 0UL; + #endif } TU_ATTR_ALWAYS_INLINE -static inline void musb_dcd_int_clear(uint8_t rhport) -{ - NVIC_ClearPendingIRQ(musb_irqs[rhport]); +static inline void musb_dcd_int_clear(uint8_t rhport) { + NVIC_ClearPendingIRQ(musb_irqs[rhport]); } //Used to save and restore user's register map when interrupt occurs static volatile unsigned isr_saved_index = 0; -static inline void musb_dcd_int_handler_enter(uint8_t rhport) -{ +static inline void musb_dcd_int_handler_enter(uint8_t rhport) { uint32_t mxm_int, mxm_int_en, mxm_is; //save current register index diff --git a/tools/get_deps.py b/tools/get_deps.py index 51d6304ae..f141d3d41 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -26,7 +26,7 @@ deps_optional = { 'fc100s'], 'hw/mcu/analog/max32' : ['https://github.com/analogdevicesinc/msdk.git', 'b20b398d3e5e2007594e54a74ba3d2a2e50ddd75', - 'max32690 max32650 max32666 max78002'], + 'max32650 max32666 max32690 max78002'], 'hw/mcu/bridgetek/ft9xx/ft90x-sdk': ['https://github.com/BRTSG-FOSS/ft90x-sdk.git', '91060164afe239fcb394122e8bf9eb24d3194eb1', 'brtmm90x'], -- cgit v1.3.1 From 1402e6ec0d5ed60375c9deb1add9061fcb37e590 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 15 Aug 2024 14:36:31 +0700 Subject: add flash-uniflash support for ti tm4c --- README.rst | 4 +- examples/build_system/make/rules.mk | 5 ++ hw/bsp/family_support.cmake | 15 ++++ hw/bsp/tm4c/boards/ek_tm4c123gxl/board.cmake | 1 + hw/bsp/tm4c/boards/ek_tm4c123gxl/board.mk | 2 + .../tm4c/boards/ek_tm4c123gxl/ek_tm4c123gxl.ccxml | 17 +++++ hw/bsp/tm4c/family.c | 83 ++++++++++------------ hw/bsp/tm4c/family.cmake | 1 + test/hil/hil_test.py | 5 ++ 9 files changed, 85 insertions(+), 48 deletions(-) create mode 100644 hw/bsp/tm4c/boards/ek_tm4c123gxl/ek_tm4c123gxl.ccxml (limited to 'hw') diff --git a/README.rst b/README.rst index 1ae8c5375..422f23271 100644 --- a/README.rst +++ b/README.rst @@ -1,4 +1,4 @@ -|Build Status| |Documentation Status| |Fuzzing Status| |License| +|Build Status| |CircleCI Status| |Documentation Status| |Fuzzing Status| |License| Sponsors ======== @@ -197,6 +197,8 @@ Docs .. |Build Status| image:: https://github.com/hathach/tinyusb/actions/workflows/cmake_arm.yml/badge.svg :target: https://github.com/hathach/tinyusb/actions +.. |CircleCI Status| image:: https://dl.circleci.com/status-badge/img/circleci/4AYHvUhFxdnY4rA7LEsdqW/QmrpoL2AjGqetvFQNqtWyq/tree/master.svg?style=svg + :target: https://dl.circleci.com/status-badge/redirect/circleci/4AYHvUhFxdnY4rA7LEsdqW/QmrpoL2AjGqetvFQNqtWyq/tree/master .. |Documentation Status| image:: https://readthedocs.org/projects/tinyusb/badge/?version=latest :target: https://docs.tinyusb.org/en/latest/?badge=latest .. |Fuzzing Status| image:: https://oss-fuzz-build-logs.storage.googleapis.com/badges/tinyusb.svg diff --git a/examples/build_system/make/rules.mk b/examples/build_system/make/rules.mk index f322dbae6..86de17b6c 100644 --- a/examples/build_system/make/rules.mk +++ b/examples/build_system/make/rules.mk @@ -166,6 +166,11 @@ flash-bmp: $(BUILD)/$(PROJECT).elf debug-bmp: $(BUILD)/$(PROJECT).elf $(GDB) -ex 'target extended-remote $(BMP)' -ex 'monitor swdp_scan' -ex 'attach 1' $< +# --------------- TI Uniflash ----------------- +DSLITE ?= dslite.sh +flash-uniflash: $(BUILD)/$(PROJECT).hex + ${DSLITE} ${UNIFLASH_OPTION} -f $< + #-------------- Artifacts -------------- # Create binary directory diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 03a24c95b..4a31f6218 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -573,6 +573,21 @@ function(family_flash_msp430flasher TARGET) ) endfunction() + +function(family_flash_uniflash TARGET) + if (NOT DEFINED DSLITE) + set(DSLITE dslite.sh) + endif () + + separate_arguments(OPTION_LIST UNIX_COMMAND ${UNIFLASH_OPTION}) + + add_custom_target(${TARGET}-uniflash + DEPENDS ${TARGET} + COMMAND ${DSLITE} ${UNIFLASH_OPTION} -f $/${TARGET}.hex + VERBATIM + ) +endfunction() + #---------------------------------- # Family specific #---------------------------------- diff --git a/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.cmake b/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.cmake index a86b5c0e5..b8df9f189 100644 --- a/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.cmake +++ b/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.cmake @@ -4,6 +4,7 @@ set(JLINK_DEVICE TM4C123GH6PM) set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/tm4c123.ld) set(OPENOCD_OPTION "-f board/ti_ek-tm4c123gxl.cfg") +set(UNIFLASH_OPTION "-c ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ccxml -r 1") function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC diff --git a/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.mk b/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.mk index a3e8df62c..b3ded8007 100644 --- a/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.mk +++ b/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.mk @@ -10,4 +10,6 @@ JLINK_DEVICE = TM4C123GH6PM # flash using openocd OPENOCD_OPTION = -f board/ti_ek-tm4c123gxl.cfg +UNIFLASH_OPTION = -c ${TOP}/${BOARD_PATH}/${BOARD}.ccxml -r 1 + flash: flash-openocd diff --git a/hw/bsp/tm4c/boards/ek_tm4c123gxl/ek_tm4c123gxl.ccxml b/hw/bsp/tm4c/boards/ek_tm4c123gxl/ek_tm4c123gxl.ccxml new file mode 100644 index 000000000..426a6f368 --- /dev/null +++ b/hw/bsp/tm4c/boards/ek_tm4c123gxl/ek_tm4c123gxl.ccxml @@ -0,0 +1,17 @@ + + + + + + + + + + + + + + + + + diff --git a/hw/bsp/tm4c/family.c b/hw/bsp/tm4c/family.c index 738bc3fa0..5e1f6d3ff 100644 --- a/hw/bsp/tm4c/family.c +++ b/hw/bsp/tm4c/family.c @@ -5,8 +5,7 @@ //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -void USB0_Handler(void) -{ +void USB0_Handler(void) { #if CFG_TUH_ENABLED tuh_int_handler(0, true); #endif @@ -20,8 +19,7 @@ void USB0_Handler(void) // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -static void board_uart_init (void) -{ +static void board_uart_init(void) { SYSCTL->RCGCUART |= (1 << 0); // Enable the clock to UART0 SYSCTL->RCGCGPIO |= (1 << 0); // Enable the clock to GPIOA @@ -42,13 +40,12 @@ static void board_uart_init (void) UART0->CTL = (1 << 0) | (1 << 8) | (1 << 9); // UART0 Enable, Transmit Enable, Receive Enable } -static void initialize_board_led (GPIOA_Type *port, uint8_t PinMsk, uint8_t dirmsk) -{ +static void initialize_board_led(GPIOA_Type* port, uint8_t PinMsk, uint8_t dirmsk) { /* Enable PortF Clock */ SYSCTL->RCGCGPIO |= (1 << 5); /* Let the clock stabilize */ - while ( !((SYSCTL->PRGPIO) & (1 << 5)) ) {} + while (!((SYSCTL->PRGPIO) & (1 << 5))) {} /* Port Digital Enable */ port->DEN |= PinMsk; @@ -57,46 +54,33 @@ static void initialize_board_led (GPIOA_Type *port, uint8_t PinMsk, uint8_t dirm port->DIR = dirmsk; } -static void board_switch_init (void) -{ - GPIOF->DIR &= ~(1 << BOARD_BTN); - GPIOF->PUR |= (1 << BOARD_BTN); - GPIOF->DEN |= (1 << BOARD_BTN); -} - -static void WriteGPIOPin (GPIOA_Type *port, uint8_t PinMsk, bool state) -{ - if ( state ) - { +static void WriteGPIOPin(GPIOA_Type* port, uint8_t PinMsk, bool state) { + if (state) { port->DATA |= PinMsk; - } - else - { + } else { port->DATA &= ~(PinMsk); } } -static uint32_t ReadGPIOPin (GPIOA_Type *port, uint8_t pinMsk) -{ +static uint32_t ReadGPIOPin(GPIOA_Type* port, uint8_t pinMsk) { return (port->DATA & pinMsk); } -void board_init (void) -{ +void board_init(void) { SystemCoreClockUpdate(); #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); #elif CFG_TUSB_OS == OPT_OS_FREERTOS - // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB0_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); #endif /* Reset USB */ SYSCTL->SRCR2 |= (1u << 16); - for ( volatile uint8_t i = 0; i < 20; i++ ) {} + for (volatile uint8_t i = 0; i < 20; i++) {} SYSCTL->SRCR2 &= ~(1u << 16); @@ -110,7 +94,7 @@ void board_init (void) SYSCTL->RCGCGPIO |= (1u << 3); /* Let the clock stabilize */ - while ( !(SYSCTL->PRGPIO & (1u << 3)) ) {} + while (!(SYSCTL->PRGPIO & (1u << 3))) {} /* USB IOs to Analog Mode */ GPIOD->AFSEL &= ~((1u << 4) | (1u << 5)); @@ -124,7 +108,9 @@ void board_init (void) initialize_board_led(LED_PORT, leds, dirmsk); /* Configure GPIO for board switch */ - board_switch_init(); + GPIOF->DIR &= ~(1 << BOARD_BTN); + GPIOF->PUR |= (1 << BOARD_BTN); + GPIOF->DEN |= (1 << BOARD_BTN); /* Initialize board UART */ board_uart_init(); @@ -132,32 +118,35 @@ void board_init (void) TU_LOG1_INT(SystemCoreClock); } -void board_led_write (bool state) -{ +void board_led_write(bool state) { WriteGPIOPin(LED_PORT, (1 << LED_PIN_BLUE), state); } -uint32_t board_button_read (void) -{ +uint32_t board_button_read(void) { uint32_t gpio_value = ReadGPIOPin(BOARD_BTN_PORT, BOARD_BTN_Msk); return BUTTON_STATE_ACTIVE ? gpio_value : !gpio_value; } -int board_uart_write (void const *buf, int len) -{ - uint8_t const * data = buf; +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + (void) max_len; + uint8_t const len = 8; + // Note: DID0, DID1 are variant ID, they aer used since TM4C123 does not have unique ID + memcpy(id, (void*)(uintptr_t) &SYSCTL->DID0, len); + return len; +} - for ( int i = 0; i < len; i++ ) - { - while ( (UART0->FR & (1 << 5)) != 0 ) {} // Poll until previous data was shofted out - UART0->DR = data[i]; // Write UART0 DATA REGISTER +int board_uart_write(void const* buf, int len) { + uint8_t const* data = buf; + + for (int i = 0; i < len; i++) { + while ((UART0->FR & (1 << 5)) != 0) {} // Poll until previous data was shofted out + UART0->DR = data[i]; // Write UART0 DATA REGISTER } return len; } -int board_uart_read (uint8_t *buf, int len) -{ +int board_uart_read(uint8_t* buf, int len) { (void) buf; (void) len; return 0; @@ -165,13 +154,13 @@ int board_uart_read (uint8_t *buf, int len) #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; -void SysTick_Handler (void) -{ + +void SysTick_Handler(void) { system_ticks++; } -uint32_t board_millis (void) -{ +uint32_t board_millis(void) { return system_ticks; } + #endif diff --git a/hw/bsp/tm4c/family.cmake b/hw/bsp/tm4c/family.cmake index 86db985d6..9c083759b 100644 --- a/hw/bsp/tm4c/family.cmake +++ b/hw/bsp/tm4c/family.cmake @@ -92,4 +92,5 @@ function(family_configure_example TARGET RTOS) # Flashing family_add_bin_hex(${TARGET}) family_flash_openocd(${TARGET}) + family_flash_uniflash(${TARGET}) endfunction() diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py index 486f0d2eb..1d5f98e5c 100644 --- a/test/hil/hil_test.py +++ b/test/hil/hil_test.py @@ -196,6 +196,11 @@ def flash_esptool(board, firmware): return ret +def flash_uniflash(board, firmware): + ret = run_cmd(f'dslite.sh {board["flasher_args"]} -f {firmware}.hex') + return ret + + # ------------------------------------------------------------- # Tests # ------------------------------------------------------------- -- cgit v1.3.1 From e345380723051ac3342a724660e877d7b2dad2fb Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 18 Aug 2024 17:15:07 +0700 Subject: add flash_openocd_adi() for use with max32 add feather max32666 to the hil pool --- hw/bsp/family_support.cmake | 19 +++++++++++++++++++ hw/bsp/max32650/family.cmake | 2 ++ hw/bsp/max32666/family.cmake | 16 ++-------------- test/hil/hil_test.py | 12 +++++++++++- test/hil/rpi.json | 7 +++++++ 5 files changed, 41 insertions(+), 15 deletions(-) (limited to 'hw') diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 4a31f6218..1df8a6f53 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -480,6 +480,25 @@ function(family_flash_openocd_wch TARGET) endfunction() +# Add flash openocd adi (Analog Devices) target +# included with msdk or compiled from release branch of https://github.com/analogdevicesinc/openocd +function(family_flash_openocd_adi TARGET) + if (DEFINED $ENV{MAXIM_PATH}) + # use openocd from msdk + set(OPENOCD ENV{MAXIM_PATH}/Tools/OpenOCD/openocd) + set(OPENOCD_OPTION2 "-s ENV{MAXIM_PATH}/Tools/OpenOCD/scripts") + else() + # compiled from source + if (NOT DEFINED OPENOCD_ADI_PATH) + set(OPENOCD_ADI_PATH $ENV{HOME}/app/openocd_adi) + endif () + set(OPENOCD ${OPENOCD_ADI_PATH}/src/openocd) + set(OPENOCD_OPTION2 "-s ${OPENOCD_ADI_PATH}/tcl") + endif () + + family_flash_openocd(${TARGET}) +endfunction() + # Add flash with https://github.com/ch32-rs/wlink function(family_flash_wlink_rs TARGET) if (NOT DEFINED WLINK_RS) diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake index 8c4f286a2..e05bd7652 100644 --- a/hw/bsp/max32650/family.cmake +++ b/hw/bsp/max32650/family.cmake @@ -14,6 +14,7 @@ set(LD_FILE_Clang ${LD_FILE_GNU}) set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(JLINK_DEVICE max32650) +set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32650.cfg") set(FAMILY_MCUS MAX32650 CACHE INTERNAL "") @@ -150,6 +151,7 @@ function(family_configure_example TARGET RTOS) # Add the optional MSDK OpenOCD flashing family_flash_msdk(${TARGET}) + family_flash_openocd_adi(${TARGET}) endfunction() function(family_flash_msdk TARGET) diff --git a/hw/bsp/max32666/family.cmake b/hw/bsp/max32666/family.cmake index 4a3f1a428..fb8c32295 100644 --- a/hw/bsp/max32666/family.cmake +++ b/hw/bsp/max32666/family.cmake @@ -15,6 +15,7 @@ set(LD_FILE_Clang ${LD_FILE_GNU}) set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(JLINK_DEVICE max32666) +set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32665.cfg") set(FAMILY_MCUS MAX32666 CACHE INTERNAL "") @@ -142,18 +143,5 @@ function(family_configure_example TARGET RTOS) # Flashing family_flash_jlink(${TARGET}) - family_flash_msdk(${TARGET}) -endfunction() - -# Add flash msdk target -function(family_flash_msdk TARGET) - set(MAXIM_PATH "$ENV{MAXIM_PATH}") - - add_custom_target(${TARGET}-msdk - DEPENDS ${TARGET} - COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts - -f interface/cmsis-dap.cfg -f target/max32665.cfg - -c "program $ verify; init; reset; exit" - VERBATIM - ) + family_flash_openocd_adi(${TARGET}) endfunction() diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py index 1d5f98e5c..e5900c616 100644 --- a/test/hil/hil_test.py +++ b/test/hil/hil_test.py @@ -173,10 +173,20 @@ echo "Ready for Remote Connections" with open(f_wch, 'w') as file: file.write(cfg_content) - ret = run_cmd(f'openocd_wch -c "adapter serial {board["flasher_sn"]}" -f {f_wch} -c "program {firmware}.elf reset exit"') + ret = run_cmd(f'openocd_wch -c "adapter serial {board["flasher_sn"]}" -f {f_wch} ' + f'-c "program {firmware}.elf reset exit"') return ret +def flash_openocd_adi(board, firmware): + openocd_adi_script_path = f'{os.getenv("HOME")}/app/openocd_adi/tcl' + if not os.path.exists(openocd_adi_script_path): + openocd_adi_script_path = '/home/pi/openocd_adi/tcl' + + ret = run_cmd(f'openocd_adi -c "adapter serial {board["flasher_sn"]}" -s {openocd_adi_script_path} ' + f'{board["flasher_args"]} -c "program {firmware}.elf reset exit"') + return ret + def flash_wlink_rs(board, firmware): # wlink use index for probe selection and lacking usb serial support ret = run_cmd(f'wlink flash {firmware}.elf') diff --git a/test/hil/rpi.json b/test/hil/rpi.json index b7d36c543..a10fa76bd 100644 --- a/test/hil/rpi.json +++ b/test/hil/rpi.json @@ -14,6 +14,13 @@ "flasher_sn": "E6614C311B597D32", "flasher_args": "-f interface/cmsis-dap.cfg -f target/atsame5x.cfg -c \"adapter speed 5000\"" }, + { + "name": "max32666fthr", + "uid": "0C81464124010B20FF0A08CC2C", + "flasher": "openocd_adi", + "flasher_sn": "040917023bffc88100000000000000000000000097969906", + "flasher_args": "-f interface/cmsis-dap.cfg -f target/max32665.cfg" + }, { "name": "lpcxpresso11u37", "uid": "17121919", -- cgit v1.3.1 From 8fdd8d9a7b83bfb79ac9a02142592d7ee4948b83 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 19 Aug 2024 11:59:41 +0700 Subject: implement dcd_edpt_iso_alloc/dcd_edpt_iso_activate for musb. video_capture example with iso kind of work but not smoothly. audio example does not seems to work as expected --- hw/bsp/max32690/family.cmake | 1 + src/common/tusb_mcu.h | 3 +- src/device/dcd.h | 15 +-- src/device/usbd.c | 18 +++- src/portable/mentor/musb/dcd_musb.c | 198 ++++++++++++++++++++--------------- src/portable/mentor/musb/musb_ti.h | 145 +------------------------ src/portable/mentor/musb/musb_type.h | 56 +--------- 7 files changed, 147 insertions(+), 289 deletions(-) (limited to 'hw') diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake index 58647e432..736ca8eac 100644 --- a/hw/bsp/max32690/family.cmake +++ b/hw/bsp/max32690/family.cmake @@ -15,6 +15,7 @@ set(LD_FILE_Clang ${LD_FILE_GNU}) set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(JLINK_DEVICE max32690) +set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32690.cfg") set(FAMILY_MCUS MAX32690 CACHE INTERNAL "") diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index b7cbd83df..e86f55c1d 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -518,7 +518,8 @@ #define TU_ATTR_FAST_FUNC #endif -#if defined(TUP_USBIP_DWC2) || defined(TUP_USBIP_FSDEV) +// USBIP that support ISO alloc & activate API +#if defined(TUP_USBIP_DWC2) || defined(TUP_USBIP_FSDEV) || defined(TUP_USBIP_MUSB) #define TUP_DCD_EDPT_ISO_ALLOC #endif diff --git a/src/device/dcd.h b/src/device/dcd.h index 41e0fbee3..66fae0802 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -157,10 +157,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc // required for multiple configuration support. void dcd_edpt_close_all (uint8_t rhport); -// Close an endpoint. -// Since it is weak, caller must TU_ASSERT this function's existence before calling it. -void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) TU_ATTR_WEAK; - // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes); @@ -175,12 +171,19 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr); // This API never calls with control endpoints, since it is auto cleared when receiving setup packet void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr); +#ifdef TUP_DCD_EDPT_ISO_ALLOC // Allocate packet buffer used by ISO endpoints // Some MCU need manual packet buffer allocation, we allocate the largest size to avoid clustering -TU_ATTR_WEAK bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size); +bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size); // Configure and enable an ISO endpoint according to descriptor -TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep); +bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep); + +#else +// Close an endpoint. +void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr); + +#endif //--------------------------------------------------------------------+ // Event API (implemented by stack) diff --git a/src/device/usbd.c b/src/device/usbd.c index 7089e9cf1..d6f69fc24 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1418,6 +1418,10 @@ bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr) { * In progress transfers on this EP may be delivered after this call. */ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr) { +#ifdef TUP_DCD_EDPT_ISO_ALLOC + (void) rhport; (void) ep_addr; + // ISO alloc/activate Should be used instead +#else rhport = _usbd_rhport; TU_ASSERT(dcd_edpt_close, /**/); @@ -1430,6 +1434,7 @@ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr) { _usbd_dev.ep_status[epnum][dir].stalled = 0; _usbd_dev.ep_status[epnum][dir].busy = 0; _usbd_dev.ep_status[epnum][dir].claimed = 0; +#endif return; } @@ -1452,21 +1457,24 @@ void usbd_sof_enable(uint8_t rhport, sof_consumer_t consumer, bool en) { } bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { +#ifdef TUP_DCD_EDPT_ISO_ALLOC rhport = _usbd_rhport; - TU_ASSERT(dcd_edpt_iso_alloc); TU_ASSERT(tu_edpt_number(ep_addr) < CFG_TUD_ENDPPOINT_MAX); - return dcd_edpt_iso_alloc(rhport, ep_addr, largest_packet_size); +#else + (void) rhport; (void) ep_addr; (void) largest_packet_size; + return false; +#endif } bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const* desc_ep) { +#ifdef TUP_DCD_EDPT_ISO_ALLOC rhport = _usbd_rhport; uint8_t const epnum = tu_edpt_number(desc_ep->bEndpointAddress); uint8_t const dir = tu_edpt_dir(desc_ep->bEndpointAddress); - TU_ASSERT(dcd_edpt_iso_activate); TU_ASSERT(epnum < CFG_TUD_ENDPPOINT_MAX); TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed)); @@ -1474,6 +1482,10 @@ bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const* desc_ep) _usbd_dev.ep_status[epnum][dir].busy = 0; _usbd_dev.ep_status[epnum][dir].claimed = 0; return dcd_edpt_iso_activate(rhport, desc_ep); +#else + (void) rhport; (void) desc_ep; + return false; +#endif } #endif diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 585480772..dc2753ea6 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -94,64 +94,71 @@ static dcd_data_t _dcd; // First 64 bytes are reserved for EP0 static uint32_t alloced_fifo_bytes; -TU_ATTR_ALWAYS_INLINE static inline void fifo_reset(musb_regs_t* musb, unsigned epnum, unsigned dir_in) { +// ffsize is log2(mps) - 3 (round up) +TU_ATTR_ALWAYS_INLINE static inline uint8_t hwfifo_byte2size(uint16_t nbytes) { + uint8_t ffsize = 28 - tu_min8(28, __builtin_clz(nbytes)); + // round up to the next power of 2 + if ((8u << ffsize) < nbytes) { + ++ffsize; + } + + return ffsize; +} + +// index register is already set +TU_ATTR_ALWAYS_INLINE static inline void hwfifo_reset(musb_regs_t* musb, unsigned epnum, unsigned dir_in) { + (void) epnum; const uint8_t is_rx = 1 - dir_in; - musb->index = epnum; musb->fifo_size[is_rx] = 0; musb->fifo_addr[is_rx] = 0; } -TU_ATTR_ALWAYS_INLINE static inline bool fifo_configure(musb_regs_t* musb, unsigned epnum, unsigned dir_in, unsigned mps) { - // ffsize is log2(mps) - 3 (round up) - uint8_t ffsize = 28 - tu_min8(28, __builtin_clz(mps)); - // round up to the next power of 2 - if ((8u << ffsize) < mps) { - ++ffsize; - mps = 8 << ffsize; +// index register is already set +TU_ATTR_ALWAYS_INLINE static inline bool hwfifo_config(musb_regs_t* musb, unsigned epnum, unsigned dir_in, unsigned mps, bool double_packet) { + (void) epnum; + uint8_t ffsize = hwfifo_byte2size(mps); + mps = 8 << ffsize; // round up to the next power of 2 + + if (double_packet) { + ffsize |= MUSB_FIFOSZ_DOUBLE_PACKET; + mps <<= 1; } TU_ASSERT(alloced_fifo_bytes + mps <= MUSB_CFG_DYNAMIC_FIFO_SIZE); const uint8_t is_rx = 1 - dir_in; - musb->index = epnum; + musb->fifo_addr[is_rx] = alloced_fifo_bytes / 8; musb->fifo_size[is_rx] = ffsize; alloced_fifo_bytes += mps; - return true; } #else -TU_ATTR_ALWAYS_INLINE static inline void fifo_reset(musb_regs_t* musb, unsigned epnum, unsigned dir_in) { - const uint8_t is_rx = 1 - dir_in; - musb->index = epnum; - #if defined(TUP_USBIP_MUSB_ADI) - // Analog have custom double buffered in csrh register, disable it - musb->indexed_csr.maxp_csr[is_rx].csrh |= MUSB_CSRH_DISABLE_DOUBLE_PACKET(is_rx); - #else - // disable double bufeffered in extended register - #endif +// index register is already set +TU_ATTR_ALWAYS_INLINE static inline void hwfifo_reset(musb_regs_t* musb, unsigned epnum, unsigned dir_in) { + (void) musb; (void) epnum; (void) dir_in; + // nothing to do for static FIFO } -TU_ATTR_ALWAYS_INLINE static inline bool fifo_configure(musb_regs_t* musb, unsigned epnum, unsigned dir_in, unsigned mps) { - (void) mps; - const uint8_t is_rx = 1 - dir_in; - musb->index = epnum; - - uint8_t csrh = 0; - -#if defined(TUP_USBIP_MUSB_ADI) - csrh = MUSB_CSRH_DISABLE_DOUBLE_PACKET(is_rx); -#endif +// index register is already set +TU_ATTR_ALWAYS_INLINE static inline bool hwfifo_config(musb_regs_t* musb, unsigned epnum, unsigned dir_in, unsigned mps, + bool double_packet) { + (void) epnum; (void) dir_in; (void) mps; -#if MUSB_CFG_SHARED_FIFO - if (dir_in) { - csrh |= MUSB_CSRH_TX_MODE; + if (!double_packet) { + #if defined(TUP_USBIP_MUSB_ADI) + const uint8_t is_rx = 1 - dir_in; + musb->indexed_csr.maxp_csr[is_rx].csrh |= MUSB_CSRH_DISABLE_DOUBLE_PACKET(is_rx); + #else + if (is_rx) { + musb->rx_doulbe_packet_disable |= 1u << epnum; + } else { + musb->tx_double_packet_disable |= 1u << epnum; + } + #endif } -#endif - - musb->indexed_csr.maxp_csr[is_rx].csrh |= csrh; return true; } @@ -538,8 +545,9 @@ static void process_bus_reset(uint8_t rhport) { /* Clear FIFO settings */ for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { - fifo_reset(musb, i, 0); - fifo_reset(musb, i, 1); + musb->index = i; + hwfifo_reset(musb, i, 0); + hwfifo_reset(musb, i, 1); } dcd_event_bus_reset(rhport, (musb->power & MUSB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); } @@ -641,17 +649,18 @@ void dcd_sof_enable(uint8_t rhport, bool en) //--------------------------------------------------------------------+ // Endpoint API //--------------------------------------------------------------------+ +// static void edpt_setup(musb_regs_t* musb, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_size){ +// const unsigned epn = tu_edpt_number(ep_addr); +// const unsigned dir_in = tu_edpt_dir(ep_addr); +// } // Configure endpoint's registers according to descriptor bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { const unsigned ep_addr = ep_desc->bEndpointAddress; const unsigned epn = tu_edpt_number(ep_addr); const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned xfer = ep_desc->bmAttributes.xfer; const unsigned mps = tu_edpt_packet_size(ep_desc); - TU_ASSERT(epn < TUP_DCD_ENDPOINT_MAX); - pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1]; pipe->buf = NULL; pipe->length = 0; @@ -659,11 +668,16 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { musb_regs_t* musb = MUSB_REGS(rhport); musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn); - const uint8_t is_rx = 1 - dir_in; musb_ep_maxp_csr_t* maxp_csr = &ep_csr->maxp_csr[is_rx]; + maxp_csr->maxp = mps; - maxp_csr->csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? MUSB_RXCSRH1_ISO : 0; + maxp_csr->csrh = 0; +#if MUSB_CFG_SHARED_FIFO + if (dir_in) { + maxp_csr->csrh |= MUSB_CSRH_TX_MODE; + } +#endif // flush and reset data toggle uint8_t csrl = MUSB_CSRL_CLEAR_DATA_TOGGLE(is_rx); @@ -672,18 +686,65 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { } maxp_csr->csrl = csrl; + TU_ASSERT(hwfifo_config(musb, epn, dir_in, mps, false)); musb->intren_ep[is_rx] |= TU_BIT(epn); - fifo_configure(musb, epn, dir_in, mps); - return true; } -// bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { -// } -// -// bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) { -// } +bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir_in = tu_edpt_dir(ep_addr); + musb_regs_t* musb = MUSB_REGS(rhport); + musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn); + const uint8_t is_rx = 1 - dir_in; + ep_csr->maxp_csr[is_rx].csrh = 0; + return hwfifo_config(musb, epn, dir_in, largest_packet_size, true); +} + +bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc ) { + const unsigned ep_addr = ep_desc->bEndpointAddress; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned mps = tu_edpt_packet_size(ep_desc); + + unsigned const ie = musb_dcd_get_int_enable(rhport); + musb_dcd_int_disable(rhport); + + pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1]; + pipe->buf = NULL; + pipe->length = 0; + pipe->remaining = 0; + + musb_regs_t* musb = MUSB_REGS(rhport); + musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn); + const uint8_t is_rx = 1 - dir_in; + musb_ep_maxp_csr_t* maxp_csr = &ep_csr->maxp_csr[is_rx]; + + maxp_csr->maxp = mps; + maxp_csr->csrh |= MUSB_CSRH_ISO; +#if MUSB_CFG_SHARED_FIFO + if (dir_in) { + maxp_csr->csrh |= MUSB_CSRH_TX_MODE; + } +#endif + + // flush fifo + if (maxp_csr->csrl & MUSB_CSRL_PACKET_READY(is_rx)) { + maxp_csr->csrl = MUSB_CSRL_FLUSH_FIFO(is_rx); + } + +#if MUSB_CFG_DYNAMIC_FIFO + // fifo space is already allocated, keep the address and just change packet size + musb->fifo_size[is_rx] = hwfifo_byte2size(mps) | MUSB_FIFOSZ_DOUBLE_PACKET; +#endif + + musb->intren_ep[is_rx] |= TU_BIT(epn); + + if (ie) musb_dcd_int_enable(rhport); + + return true; +} void dcd_edpt_close_all(uint8_t rhport) { @@ -707,7 +768,7 @@ void dcd_edpt_close_all(uint8_t rhport) } maxp_csr->csrl = csrl; - fifo_reset(musb, i, 1-d); + hwfifo_reset(musb, i, 1-d); } } @@ -718,38 +779,6 @@ void dcd_edpt_close_all(uint8_t rhport) if (ie) musb_dcd_int_enable(rhport); } -void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) -{ - // FIXME: we should implement iso_alloc() and iso_activate() - unsigned const epn = tu_edpt_number(ep_addr); - unsigned const dir_in = tu_edpt_dir(ep_addr); - musb_regs_t* musb = MUSB_REGS(rhport); - musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn); - unsigned const ie = musb_dcd_get_int_enable(rhport); - musb_dcd_int_disable(rhport); - if (dir_in) { - musb->intr_txen &= ~TU_BIT(epn); - ep_csr->tx_maxp = 0; - ep_csr->tx_csrh = 0; - if (ep_csr->tx_csrl & MUSB_TXCSRL1_TXRDY) { - ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT | MUSB_TXCSRL1_FLUSH; - } else { - ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT; - } - } else { - musb->intr_rxen &= ~TU_BIT(epn); - ep_csr->rx_maxp = 0; - ep_csr->rx_csrh = 0; - if (ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY) { - ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT | MUSB_RXCSRL1_FLUSH; - } else { - ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT; - } - } - fifo_reset(musb, epn, dir_in); - if (ie) musb_dcd_int_enable(rhport); -} - // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) { @@ -771,7 +800,8 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t return ret; } -// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c +// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack +// - optional, however, must be listed in usbd.c bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) { (void)rhport; diff --git a/src/portable/mentor/musb/musb_ti.h b/src/portable/mentor/musb/musb_ti.h index 680bebde7..d17e836ee 100644 --- a/src/portable/mentor/musb/musb_ti.h +++ b/src/portable/mentor/musb/musb_ti.h @@ -42,8 +42,8 @@ #error "Unsupported MCUs" #endif -#define MUSB_CFG_SHARED_FIFO 0 -#define MUSB_CFG_DYNAMIC_FIFO 1 +#define MUSB_CFG_SHARED_FIFO 0 +#define MUSB_CFG_DYNAMIC_FIFO 1 #define MUSB_CFG_DYNAMIC_FIFO_SIZE 4096 const uintptr_t MUSB_BASES[] = { USB0_BASE }; @@ -51,11 +51,6 @@ const uintptr_t MUSB_BASES[] = { USB0_BASE }; // Header supports both device and host modes. Only include what's necessary #if CFG_TUD_ENABLED -// Mapping of peripheral instances to port. Currently just 1. -static USB0_Type* const musb_periph_inst[] = { - USB0 -}; - // Mapping of IRQ numbers to port. Currently just 1. static const IRQn_Type musb_irqs[] = { USB0_IRQn @@ -87,142 +82,6 @@ static inline void musb_dcd_int_handler_enter(uint8_t rhport) { //Nothing to do for this part } -#if 0 -typedef struct { - uint_fast16_t beg; /* offset of including first element */ - uint_fast16_t end; /* offset of excluding the last element */ -} free_block_t; - -static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr) { - free_block_t *cur = beg; - for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ; - return cur; -} - -static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size) { - free_block_t *p = find_containing_block(blks, blks + num, addr); - TU_ASSERT(p != blks + num, -2); - if (p->beg == addr) { - /* Shrink block */ - p->beg = addr + size; - if (p->beg != p->end) return 0; - /* remove block */ - free_block_t *end = blks + num; - while (p + 1 < end) { - *p = *(p + 1); - ++p; - } - return -1; - } else { - /* Split into 2 blocks */ - free_block_t tmp = { - .beg = addr + size, - .end = p->end - }; - p->end = addr; - if (p->beg == p->end) { - if (tmp.beg != tmp.end) { - *p = tmp; - return 0; - } - /* remove block */ - free_block_t *end = blks + num; - while (p + 1 < end) { - *p = *(p + 1); - ++p; - } - return -1; - } - if (tmp.beg == tmp.end) return 0; - blks[num] = tmp; - return 1; - } -} - -static inline unsigned free_block_size(free_block_t const *blk) { - return blk->end - blk->beg; -} - -#if 0 -static inline void print_block_list(free_block_t const *blk, unsigned num) -{ - TU_LOG1("*************\r\n"); - for (unsigned i = 0; i < num; ++i) { - TU_LOG1(" Blk%u %u %u\r\n", i, blk->beg, blk->end); - ++blk; - } -} -#else -#define print_block_list(a,b) -#endif - -static unsigned find_free_memory(uint8_t rhport, uint_fast16_t size_in_log2_minus3) -{ - free_block_t free_blocks[2 * (TUP_DCD_ENDPOINT_MAX - 1)]; - unsigned num_blocks = 1; - - /* Initialize free memory block list */ - free_blocks[0].beg = 64 / 8; - free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */ - for (int i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { - uint_fast16_t addr; - int num; - musb_periph_inst[rhport]->EPIDX = i; - addr = musb_periph_inst[rhport]->TXFIFOADD; - if (addr) { - unsigned sz = musb_periph_inst[rhport]->TXFIFOSZ; - unsigned sft = (sz & USB_TXFIFOSZ_SIZE_M) + ((sz & USB_TXFIFOSZ_DPB) ? 1: 0); - num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); - TU_ASSERT(-2 < num, 0); - num_blocks += num; - print_block_list(free_blocks, num_blocks); - } - addr = musb_periph_inst[rhport]->RXFIFOADD; - if (addr) { - unsigned sz = musb_periph_inst[rhport]->RXFIFOSZ; - unsigned sft = (sz & USB_RXFIFOSZ_SIZE_M) + ((sz & USB_RXFIFOSZ_DPB) ? 1: 0); - num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); - TU_ASSERT(-2 < num, 0); - num_blocks += num; - print_block_list(free_blocks, num_blocks); - } - } - print_block_list(free_blocks, num_blocks); - - /* Find the best fit memory block */ - uint_fast16_t size_in_8byte_unit = 1 << size_in_log2_minus3; - free_block_t const *min = NULL; - uint_fast16_t min_sz = 0xFFFFu; - free_block_t const *end = &free_blocks[num_blocks]; - for (free_block_t const *cur = &free_blocks[0]; cur < end; ++cur) { - uint_fast16_t sz = free_block_size(cur); - if (sz < size_in_8byte_unit) continue; - if (size_in_8byte_unit == sz) return cur->beg; - if (sz < min_sz) min = cur; - } - TU_ASSERT(min, 0); - return min->beg; -} - - -static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) -{ - int size_in_log2_minus3 = 28 - TU_MIN(28, __CLZ((uint32_t)mps)); - if ((8u << size_in_log2_minus3) < mps) ++size_in_log2_minus3; - unsigned addr = find_free_memory(rhport, size_in_log2_minus3); - TU_ASSERT(addr,); - - musb_periph_inst[rhport]->EPIDX = epnum; - if (dir_in) { - musb_periph_inst[rhport]->TXFIFOADD = addr; - musb_periph_inst[rhport]->TXFIFOSZ = size_in_log2_minus3; - } else { - musb_periph_inst[rhport]->RXFIFOADD = addr; - musb_periph_inst[rhport]->RXFIFOSZ = size_in_log2_minus3; - } -} -#endif - #endif // CFG_TUD_ENABLED #ifdef __cplusplus diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h index f8a66acce..4e448c0ed 100644 --- a/src/portable/mentor/musb/musb_type.h +++ b/src/portable/mentor/musb/musb_type.h @@ -338,6 +338,10 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // 0x13, 0x17: TX/RX CSRH #define MUSB_CSRH_DISABLE_DOUBLE_PACKET(_rx) (1u << 1) #define MUSB_CSRH_TX_MODE (1u << 5) // 1 = TX, 0 = RX. only relevant for SHARED FIFO +#define MUSB_CSRH_ISO (1u << 6) + +// 0x62, 0x63: TXFIFO_SZ, RXFIFO_SZ +#define MUSB_FIFOSZ_DOUBLE_PACKET (1u << 4) //***************************************************************************** @@ -417,58 +421,6 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ #define MUSB_CCONF_TXEDMA 0x0002 // TX Early DMA Enable #define MUSB_CCONF_RXEDMA 0x0001 // TX Early DMA Enable -//***************************************************************************** -// -// The following are defines for the bit fields in the MUSB_O_TXFIFOSZ register. -// -//***************************************************************************** -#define MUSB_TXFIFOSZ_DPB 0x0010 // Double Packet Buffer Support -#define MUSB_TXFIFOSZ_SIZE_M 0x000F // Max Packet Size -#define MUSB_TXFIFOSZ_SIZE_8 0x0000 // 8 -#define MUSB_TXFIFOSZ_SIZE_16 0x0001 // 16 -#define MUSB_TXFIFOSZ_SIZE_32 0x0002 // 32 -#define MUSB_TXFIFOSZ_SIZE_64 0x0003 // 64 -#define MUSB_TXFIFOSZ_SIZE_128 0x0004 // 128 -#define MUSB_TXFIFOSZ_SIZE_256 0x0005 // 256 -#define MUSB_TXFIFOSZ_SIZE_512 0x0006 // 512 -#define MUSB_TXFIFOSZ_SIZE_1024 0x0007 // 1024 -#define MUSB_TXFIFOSZ_SIZE_2048 0x0008 // 2048 - -//***************************************************************************** -// -// The following are defines for the bit fields in the MUSB_O_RXFIFOSZ register. -// -//***************************************************************************** -#define MUSB_RXFIFOSZ_DPB 0x0010 // Double Packet Buffer Support -#define MUSB_RXFIFOSZ_SIZE_M 0x000F // Max Packet Size -#define MUSB_RXFIFOSZ_SIZE_8 0x0000 // 8 -#define MUSB_RXFIFOSZ_SIZE_16 0x0001 // 16 -#define MUSB_RXFIFOSZ_SIZE_32 0x0002 // 32 -#define MUSB_RXFIFOSZ_SIZE_64 0x0003 // 64 -#define MUSB_RXFIFOSZ_SIZE_128 0x0004 // 128 -#define MUSB_RXFIFOSZ_SIZE_256 0x0005 // 256 -#define MUSB_RXFIFOSZ_SIZE_512 0x0006 // 512 -#define MUSB_RXFIFOSZ_SIZE_1024 0x0007 // 1024 -#define MUSB_RXFIFOSZ_SIZE_2048 0x0008 // 2048 - -//***************************************************************************** -// -// The following are defines for the bit fields in the MUSB_O_TXFIFOADD -// register. -// -//***************************************************************************** -#define MUSB_TXFIFOADD_ADDR_M 0x01FF // Transmit/Receive Start Address -#define MUSB_TXFIFOADD_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the MUSB_O_RXFIFOADD -// register. -// -//***************************************************************************** -#define MUSB_RXFIFOADD_ADDR_M 0x01FF // Transmit/Receive Start Address -#define MUSB_RXFIFOADD_ADDR_S 0 - //***************************************************************************** // // The following are defines for the bit fields in the MUSB_O_ULPIVBUSCTL -- cgit v1.3.1 From 61187008285d70d700e30e5f11636240ae4845d0 Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Wed, 21 Aug 2024 19:09:37 +0700 Subject: update circle ci to build make (#2769) * update build.py script to work with circleci * build make with circle ci * build vm for esp only * nrf imxrt with large resource * nrf imxrt with large resource * remove 2 of nrf boards --- .circleci/config.yml | 46 +++++- .circleci/config2.yml | 162 ++++++++++++++----- .github/workflows/build.yml | 46 +----- .github/workflows/build_util.yml | 7 +- .github/workflows/ci_set_matrix.py | 9 +- hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake | 5 - hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h | 52 ------- hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk | 15 -- .../nrf52840_mdk_dongle/nrf52840_mdk_dongle.ld | 13 -- hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake | 4 - hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h | 52 ------- hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.mk | 7 - tools/build.py | 171 +++++++++++---------- tools/build_utils.py | 35 ----- 14 files changed, 274 insertions(+), 350 deletions(-) delete mode 100644 hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake delete mode 100644 hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h delete mode 100644 hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk delete mode 100644 hw/bsp/nrf/boards/nrf52840_mdk_dongle/nrf52840_mdk_dongle.ld delete mode 100644 hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake delete mode 100644 hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h delete mode 100644 hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.mk (limited to 'hw') diff --git a/.circleci/config.yml b/.circleci/config.yml index 4d541a595..8769926b1 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -18,16 +18,52 @@ jobs: MATRIX_JSON=$(python .github/workflows/ci_set_matrix.py) echo "MATRIX_JSON=$MATRIX_JSON" - TOOLCHAIN_LIST=("arm-clang" "arm-gcc") - for toolchain in "${TOOLCHAIN_LIST[@]}"; do + BUILDSYSTEM_TOOLCHAIN=( + "cmake arm-clang" + "make aarch64-gcc" + "make arm-gcc" + "make msp430-gcc" + "make riscv-gcc" + # "make rx-gcc" llvm-gcc-renesas.com seems to be down + "cmake esp-idf" + ) + + RESOURCE_LARGE='["nrf", "imxrt"]' + + for e in "${BUILDSYSTEM_TOOLCHAIN[@]}"; do + e_arr=($e) + build_system="${e_arr[0]}" + toolchain="${e_arr[1]}" FAMILY=$(echo $MATRIX_JSON | jq -r ".\"$toolchain\".family") - echo "${toolchain}_FAMILY=$FAMILY" - echo " - build:" >> .circleci/config2.yml + echo "FAMILY_${toolchain}=$FAMILY" + + # FAMILY_LARGE = FAMILY - RESOURCE_LARGE + # Separate large from medium+ resources + FAMILY_LARGE=$(jq -n --argjson family "$FAMILY" --argjson resource "$RESOURCE_LARGE" '$family | map(select(IN($resource[])))') + FAMILY=$(jq -n --argjson family "$FAMILY" --argjson resource "$RESOURCE_LARGE" '$family | map(select(IN($resource[]) | not))') + + if [[ $toolchain == esp-idf ]]; then + echo " - build-vm:" >> .circleci/config2.yml + else + echo " - build:" >> .circleci/config2.yml + fi echo " matrix:" >> .circleci/config2.yml echo " parameters:" >> .circleci/config2.yml + echo " build-system: ['$build_system']" >> .circleci/config2.yml echo " toolchain: ['$toolchain']" >> .circleci/config2.yml - echo " build-system: ['cmake']" >> .circleci/config2.yml echo " family: $FAMILY" >> .circleci/config2.yml + #echo " resource_class: ['medium+']" >> .circleci/config2.yml + + # add large resources + if [ "$(echo $FAMILY_LARGE | jq 'length')" -gt 0 ]; then + echo " - build:" >> .circleci/config2.yml + echo " matrix:" >> .circleci/config2.yml + echo " parameters:" >> .circleci/config2.yml + echo " build-system: ['$build_system']" >> .circleci/config2.yml + echo " toolchain: ['$toolchain']" >> .circleci/config2.yml + echo " family: $FAMILY_LARGE" >> .circleci/config2.yml + echo " resource_class: ['large']" >> .circleci/config2.yml + fi done - continuation/continue: diff --git a/.circleci/config2.yml b/.circleci/config2.yml index ea7fccaff..cd844c33f 100644 --- a/.circleci/config2.yml +++ b/.circleci/config2.yml @@ -5,44 +5,124 @@ commands: parameters: toolchain: type: string + steps: - run: - name: Install Toolchain + name: Set toolchain url and key command: | TOOLCHAIN_JSON='{ + "aarch64-gcc": "https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz", "arm-clang": "https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-17.0.1/LLVMEmbeddedToolchainForArm-17.0.1-Linux-x86_64.tar.xz", - "arm-gcc": "https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v12.3.1-1.1/xpack-arm-none-eabi-gcc-12.3.1-1.1-linux-x64.tar.gz" + "arm-gcc": "https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v12.3.1-1.1/xpack-arm-none-eabi-gcc-12.3.1-1.1-linux-x64.tar.gz", + "msp430-gcc": "http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2", + "riscv-gcc": "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz", + "rx-gcc": "https://llvm-gcc-renesas.com/downloads/get.php?f=rx/8.3.0.202004-gnurx/gcc-8.3.0.202004-GNURX-ELF.run" }' toolchain_url=$(echo $TOOLCHAIN_JSON | jq -r '.["<< parameters.toolchain >>"]') - echo "toolchain_url=$toolchain_url" - # download and extract toolchain - mkdir -p ~/cache/<< parameters.toolchain >> - wget $toolchain_url -O toolchain.tar.gz - tar -C ~/cache/<< parameters.toolchain >> -xaf toolchain.tar.gz + # only cache if not a github link + if [[ $toolchain_url != "https://github.com"* ]]; then + echo "<< parameters.toolchain >>-$toolchain_url" > toolchain_key + fi + echo "export toolchain_url=$toolchain_url" >> $BASH_ENV + + - restore_cache: + name: Restore Toolchain Cache + key: deps-{{ checksum "toolchain_key" }} + paths: + - ~/cache/<< parameters.toolchain >> + + - run: + name: Install Toolchain + command: | + # download if folder does not exist (not cached) + if [ ! -d ~/cache/<< parameters.toolchain >> ]; then + mkdir -p ~/cache/<< parameters.toolchain >> + wget --progress=dot:giga $toolchain_url -O toolchain.tar.gz + if [[ << parameters.toolchain >> == rx-gcc ]]; then + mv toolchain.tar.gz toolchain.run + chmod +x toolchain.run + ./toolchain.run -p ~/cache/<< parameters.toolchain >>/gnurx -y + else + tar -C ~/cache/<< parameters.toolchain >> -xaf toolchain.tar.gz + fi + fi # Add toolchain to PATH echo "export PATH=$PATH:`echo ~/cache/<< parameters.toolchain >>/*/bin`" >> $BASH_ENV - get-deps: + - save_cache: + name: Save Toolchain Cache + key: deps-{{ checksum "toolchain_key" }} + paths: + - ~/cache/<< parameters.toolchain >> + + build: parameters: + build-system: + type: string + toolchain: + type: string family: type: string + steps: + - checkout + - when: + condition: + not: + equal: [esp-idf, << parameters.toolchain >>] + steps: + - setup-toolchain: + toolchain: << parameters.toolchain >> + - run: name: Get Dependencies command: | python tools/get_deps.py << parameters.family >> + # Install ninja if cmake build system + if [ << parameters.build-system >> == "cmake" ]; then + NINJA_URL=https://github.com/ninja-build/ninja/releases/download/v1.12.1/ninja-linux.zip + wget $NINJA_URL -O ninja-linux.zip + unzip ninja-linux.zip -d ~/bin + fi + # Install Pico SDK if [ << parameters.family >> == "rp2040" ]; then git clone --depth 1 https://github.com/raspberrypi/pico-sdk.git ~/pico-sdk echo "export PICO_SDK_PATH=~/pico-sdk" >> $BASH_ENV fi + - run: + name: Build + command: | + if [ << parameters.toolchain >> == esp-idf ]; then + docker run --rm -v $PWD:/project -w /project espressif/idf:v5.1.1 python tools/build.py << parameters.family >> + else + # Only build one board per family for non PRs i.e commit to master + ONE_PER_FAMILY="" + if [ -z "$CIRCLE_PULL_REQUEST" ]; then + ONE_PER_FAMILY="--one-per-family" + fi + + # Toolchain option default is gcc + if [ << parameters.toolchain >> == arm-clang ]; then + TOOLCHAIN_OPTION="--toolchain clang" + elif [ << parameters.toolchain >> == arm-gcc ]; then + TOOLCHAIN_OPTION="--toolchain gcc" + fi + + python tools/build.py $ONE_PER_FAMILY -s << parameters.build-system >> $TOOLCHAIN_OPTION << parameters.family >> + fi + jobs: + # Build using docker build: parameters: + resource_class: + type: string + default: medium+ build-system: type: string toolchain: @@ -52,40 +132,36 @@ jobs: docker: - image: cimg/base:current - resource_class: medium+ + resource_class: << parameters.resource_class >> + steps: - - checkout - - when: - condition: << parameters.build-system >> == 'cmake' - steps: - - run: - name: Install Ninja - command: | - # Install Ninja - NINJA_URL=https://github.com/ninja-build/ninja/releases/download/v1.12.1/ninja-linux.zip - wget $NINJA_URL -O ninja-linux.zip - unzip ninja-linux.zip -d ~/bin - - setup-toolchain: + - build: + build-system: << parameters.build-system >> toolchain: << parameters.toolchain >> - - get-deps: family: << parameters.family >> - - run: - name: Build - command: | - # Only build one board per family for non PRs i.e commit to master - ONE_PER_FAMILY="" - if [ -z "$CIRCLE_PULL_REQUEST" ]; then - ONE_PER_FAMILY="--one-per-family" - fi - # Toolchain option default is gcc - if [ "<< parameters.toolchain >>" == "arm-clang" ]; then - TOOLCHAIN_OPTION="--toolchain clang" - elif [ "<< parameters.toolchain >>" == "arm-gcc" ]; then - TOOLCHAIN_OPTION="--toolchain gcc" - fi + # Build using VM + build-vm: + parameters: + resource_class: + type: string + default: large + build-system: + type: string + toolchain: + type: string + family: + type: string - python tools/build.py $ONE_PER_FAMILY -s << parameters.build-system >> $TOOLCHAIN_OPTION << parameters.family >> + machine: + image: ubuntu-2404:current + resource_class: << parameters.resource_class >> + + steps: + - build: + build-system: << parameters.build-system >> + toolchain: << parameters.toolchain >> + family: << parameters.family >> workflows: build: @@ -93,6 +169,14 @@ workflows: # - build: # matrix: # parameters: -# toolchain: ['arm-clang'] +# toolchain: [ 'arm-gcc' ] +# build-system: [ 'cmake' ] +# family: [ 'nrf' ] +# resource_class: ['large'] +# - build-vm: +# matrix: +# parameters: +# toolchain: ['esp-idf'] # build-system: ['cmake'] -# family: ['imxrt'] +# family: ['-bespressif_kaluga_1'] +# resource_class: ['large'] diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index e4204ca3d..6ca9885f8 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -51,7 +51,6 @@ jobs: # Build CMake # --------------------------------------- cmake: - # if: false needs: set-matrix uses: ./.github/workflows/build_util.yml strategy: @@ -60,6 +59,7 @@ jobs: toolchain: # - 'arm-clang' is built by circle-ci in PR - 'aarch64-gcc' + - 'arm-gcc' - 'msp430-gcc' - 'riscv-gcc' with: @@ -69,41 +69,28 @@ jobs: one-per-family: ${{ github.event_name == 'push' }} # --------------------------------------- - # Build CMake arm-gcc - # only build with push, for PR: all board is built by circle-ci - # --------------------------------------- - cmake-arm-gcc: - if: github.event_name == 'push' - needs: set-matrix - uses: ./.github/workflows/build_util.yml - with: - build-system: 'cmake' - toolchain: 'arm-gcc' - build-args: ${{ toJSON(fromJSON(needs.set-matrix.outputs.json)['arm-gcc'].family) }} - one-per-family: true - - # --------------------------------------- - # Build Make + # Build Make (built by circle-ci in PR, only build on push here) # --------------------------------------- make: - # if: false + if: github.event_name == 'push' needs: set-matrix uses: ./.github/workflows/build_util.yml strategy: fail-fast: false matrix: toolchain: - # 'arm-clang' would be built by circle-ci - - 'aarch64-gcc' + # 'arm-clang' - 'arm-gcc' + - 'aarch64-gcc' - 'msp430-gcc' - 'riscv-gcc' - 'rx-gcc' + - 'esp-idf' # buid-system is ignored with: build-system: 'make' toolchain: ${{ matrix.toolchain }} build-args: ${{ toJSON(fromJSON(needs.set-matrix.outputs.json)[matrix.toolchain].family) }} - one-per-family: ${{ github.event_name == 'push' }} + one-per-family: true # --------------------------------------- # Build Make on Windows/MacOS @@ -122,29 +109,10 @@ jobs: build-args: '["stm32h7"]' one-per-family: true - # --------------------------------------- - # Build Espressif - # --------------------------------------- - espressif: - # if: false - uses: ./.github/workflows/build_util.yml - strategy: - fail-fast: false - matrix: - board: - - 'espressif_kaluga_1' - - 'espressif_s3_devkitm' - with: - build-system: 'cmake' - toolchain: 'esp-idf' - toolchain_version: 'v5.1.1' - build-args: '["-b${{ matrix.board }}"]' - # --------------------------------------- # Build IAR on HFP self-hosted # --------------------------------------- arm-iar: - # if: false if: github.repository_owner == 'hathach' needs: set-matrix runs-on: [self-hosted, Linux, X64, hifiphile] diff --git a/.github/workflows/build_util.yml b/.github/workflows/build_util.yml index e983f06d1..ff98aef2d 100644 --- a/.github/workflows/build_util.yml +++ b/.github/workflows/build_util.yml @@ -9,9 +9,6 @@ on: toolchain: required: true type: string - toolchain_version: - required: false - type: string build-args: required: true type: string @@ -40,7 +37,7 @@ jobs: uses: ./.github/actions/setup_toolchain with: toolchain: ${{ inputs.toolchain }} - toolchain_version: ${{ inputs.toolchain_version }} + toolchain_version: 'v5.1.1' - name: Get Dependencies uses: ./.github/actions/get_deps @@ -60,7 +57,7 @@ jobs: - name: Build run: | if [ "${{ inputs.toolchain }}" == "esp-idf" ]; then - docker run --rm -v $PWD:/project -w /project espressif/idf:${{ inputs.toolchain_version }} python3 tools/build.py ${{ matrix.arg }} + docker run --rm -v $PWD:/project -w /project espressif/idf:v5.1.1 python tools/build.py ${{ matrix.arg }} else python tools/build.py -s ${{ inputs.build-system }} ${{ steps.setup-toolchain.outputs.build_option }} ${{ steps.set-one-per-family.outputs.build_option }} ${{ matrix.arg }} fi diff --git a/.github/workflows/ci_set_matrix.py b/.github/workflows/ci_set_matrix.py index c9698c934..4da26bfea 100644 --- a/.github/workflows/ci_set_matrix.py +++ b/.github/workflows/ci_set_matrix.py @@ -6,6 +6,7 @@ toolchain_list = [ "arm-clang", "arm-iar", "arm-gcc", + "esp-idf", "msp430-gcc", "riscv-gcc", "rx-gcc" @@ -31,15 +32,19 @@ family_list = { "ra": ["arm-gcc"], "rp2040": ["arm-gcc"], "rx": ["rx-gcc"], - "samd11 samd21 saml2x": ["arm-gcc", "arm-clang"], + "samd11 saml2x": ["arm-gcc", "arm-clang"], + "samd21": ["arm-gcc", "arm-clang"], "samd5x_e5x samg": ["arm-gcc", "arm-clang"], "stm32f0 stm32f1 stm32f2 stm32f3": ["arm-gcc", "arm-clang", "arm-iar"], "stm32f4": ["arm-gcc", "arm-clang", "arm-iar"], "stm32f7": ["arm-gcc", "arm-clang", "arm-iar"], "stm32g0 stm32g4 stm32h5": ["arm-gcc", "arm-clang", "arm-iar"], "stm32h7": ["arm-gcc", "arm-clang", "arm-iar"], - "stm32l0 stm32l4 stm32u5 stm32wb": ["arm-gcc", "arm-clang", "arm-iar"], + "stm32l0 stm32l4": ["arm-gcc", "arm-clang", "arm-iar"], + "stm32u5 stm32wb": ["arm-gcc", "arm-clang", "arm-iar"], "xmc4000": ["arm-gcc"], + "-bespressif_kaluga_1": ["esp-idf"], + "-bespressif_s3_devkitm": ["esp-idf"], } diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake deleted file mode 100644 index ffa5932c1..000000000 --- a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.cmake +++ /dev/null @@ -1,5 +0,0 @@ -set(MCU_VARIANT nrf52840) -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/nrf52840_mdk_dongle.ld) - -function(update_board TARGET) -endfunction() diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h deleted file mode 100644 index 072cb2714..000000000 --- a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifndef BOARD_H_ -#define BOARD_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -#define _PINNUM(port, pin) ((port)*32 + (pin)) - -// LED -#define LED_PIN _PINNUM(0, 23) -#define LED_STATE_ON 0 - -// Button -#define BUTTON_PIN _PINNUM(0, 18) -#define BUTTON_STATE_ACTIVE 0 - -// UART -#define UART_RX_PIN 2 -#define UART_TX_PIN 3 - -#ifdef __cplusplus - } -#endif - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk deleted file mode 100644 index f25ec8f34..000000000 --- a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/board.mk +++ /dev/null @@ -1,15 +0,0 @@ -MCU_VARIANT = nrf52840 -CFLAGS += -DNRF52840_XXAA - -LD_FILE = $(BOARD_PATH)/$(BOARD).ld - -# flash using Nordic nrfutil (pip3 install nrfutil) -# make BOARD=nrf52840_mdk_dongle SERIAL=/dev/ttyACM0 all flash -NRFUTIL = nrfutil - -$(BUILD)/$(PROJECT).zip: $(BUILD)/$(PROJECT).hex - $(NRFUTIL) pkg generate --hw-version 52 --sd-req 0x0000 --debug-mode --application $^ $@ - -flash: $(BUILD)/$(PROJECT).zip - @:$(call check_defined, SERIAL, example: SERIAL=/dev/ttyACM0) - $(NRFUTIL) dfu usb-serial --package $^ -p $(SERIAL) -b 115200 diff --git a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/nrf52840_mdk_dongle.ld b/hw/bsp/nrf/boards/nrf52840_mdk_dongle/nrf52840_mdk_dongle.ld deleted file mode 100644 index a6bc6dcfe..000000000 --- a/hw/bsp/nrf/boards/nrf52840_mdk_dongle/nrf52840_mdk_dongle.ld +++ /dev/null @@ -1,13 +0,0 @@ -/* Linker script to configure memory regions. */ - -SEARCH_DIR(.) -/*GROUP(-lgcc -lc -lnosys) not compatible with clang*/ - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x1000, LENGTH = 0xE0000-0x1000 - RAM (rwx) : ORIGIN = 0x20000008, LENGTH = 0x3fff8 -} - - -INCLUDE "nrf_common.ld" diff --git a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake deleted file mode 100644 index cc370aac8..000000000 --- a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.cmake +++ /dev/null @@ -1,4 +0,0 @@ -set(MCU_VARIANT nrf52840) - -function(update_board TARGET) -endfunction() diff --git a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h deleted file mode 100644 index bc203f073..000000000 --- a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifndef BOARD_H_ -#define BOARD_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -#define _PINNUM(port, pin) ((port)*32 + (pin)) - -// LED -#define LED_PIN _PINNUM(1, 13) -#define LED_STATE_ON 0 - -// Button -#define BUTTON_PIN _PINNUM(0, 15) -#define BUTTON_STATE_ACTIVE 0 - -// UART -#define UART_RX_PIN 25 -#define UART_TX_PIN 24 - -#ifdef __cplusplus - } -#endif - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.mk b/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.mk deleted file mode 100644 index be2ed3314..000000000 --- a/hw/bsp/nrf/boards/raytac_mdbt50q_rx/board.mk +++ /dev/null @@ -1,7 +0,0 @@ -MCU_VARIANT = nrf52840 -CFLAGS += -DNRF52840_XXAA - -LD_FILE = hw/mcu/nordic/nrfx/mdk/nrf52840_xxaa.ld - -# flash using jlink -flash: flash-jlink diff --git a/tools/build.py b/tools/build.py index b937a7342..f9ae68231 100644 --- a/tools/build.py +++ b/tools/build.py @@ -9,19 +9,29 @@ from multiprocessing import Pool import build_utils -SUCCEEDED = "\033[32msucceeded\033[0m" -FAILED = "\033[31mfailed\033[0m" +STATUS_OK = "\033[32mOK\033[0m" +STATUS_FAILED = "\033[31mFailed\033[0m" +STATUS_SKIPPED = "\033[33mSkipped\033[0m" -build_separator = '-' * 106 +RET_OK = 0 +RET_FAILED = 1 +RET_SKIPPED = 2 +build_format = '| {:30} | {:40} | {:16} | {:5} |' +build_separator = '-' * 95 +build_status = [STATUS_OK, STATUS_FAILED, STATUS_SKIPPED] + +# ----------------------------- +# Helper +# ----------------------------- def run_cmd(cmd): #print(cmd) r = subprocess.run(cmd, shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) - title = 'command error' + title = f'Command Error: {cmd}' if r.returncode != 0: # print build output if failed - if os.getenv('CI'): + if os.getenv('GITHUB_ACTIONS'): print(f"::group::{title}") print(r.stdout.decode("utf-8")) print(f"::endgroup::") @@ -30,6 +40,7 @@ def run_cmd(cmd): print(r.stdout.decode("utf-8")) return r + def find_family(board): bsp_dir = Path("hw/bsp") for family_dir in bsp_dir.iterdir(): @@ -56,70 +67,91 @@ def get_examples(family): return all_examples -def build_board_cmake(board, toolchain): - start_time = time.monotonic() - ret = [0, 0, 0] +def print_build_result(board, example, status, duration): + if isinstance(duration, (int, float)): + duration = "{:.2f}s".format(duration) + print(build_format.format(board, example, build_status[status], duration)) +# ----------------------------- +# CMake +# ----------------------------- +def cmake_board(board, toolchain): + ret = [0, 0, 0] + start_time = time.monotonic() build_dir = f"cmake-build/cmake-build-{board}" family = find_family(board) if family == 'espressif': # for espressif, we have to build example individually all_examples = get_examples(family) for example in all_examples: - r = run_cmd(f'cmake examples/{example} -B {build_dir}/{example} -G "Ninja" -DBOARD={board} -DMAX3421_HOST=1') - if r.returncode == 0: - r = run_cmd(f'cmake --build {build_dir}/{example}') - if r.returncode == 0: - ret[0] += 1 - else: - ret[1] += 1 + rcmd = run_cmd(f'cmake examples/{example} -B {build_dir}/{example} -G "Ninja" -DBOARD={board} -DMAX3421_HOST=1') + if rcmd.returncode == 0: + rcmd = run_cmd(f'cmake --build {build_dir}/{example}') + ret[0 if rcmd.returncode == 0 else 1] += 1 else: - r = run_cmd(f'cmake examples -B {build_dir} -G "Ninja" -DBOARD={board} -DCMAKE_BUILD_TYPE=MinSizeRel -DTOOLCHAIN={toolchain}') - if r.returncode == 0: - r = run_cmd(f"cmake --build {build_dir}") - if r.returncode == 0: - ret[0] += 1 - else: - ret[1] += 1 + rcmd = run_cmd(f'cmake examples -B {build_dir} -G "Ninja" -DBOARD={board} -DCMAKE_BUILD_TYPE=MinSizeRel -DTOOLCHAIN={toolchain}') + if rcmd.returncode == 0: + rcmd = run_cmd(f"cmake --build {build_dir}") + ret[0 if rcmd.returncode == 0 else 1] += 1 - duration = time.monotonic() - start_time + example = 'all' + print_build_result(board, example, 0 if ret[1] == 0 else 1, time.monotonic() - start_time) + return ret - if ret[1] == 0: - status = SUCCEEDED + +# ----------------------------- +# Make +# ----------------------------- +def make_one_example(example, board, make_option): + # Check if board is skipped + if build_utils.skip_example(example, board): + print_build_result(board, example, 2, '-') + r = 2 else: - status = FAILED + start_time = time.monotonic() + # skip -j for circleci + if not os.getenv('CIRCLECI'): + make_option += ' -j' + make_cmd = f"make -C examples/{example} BOARD={board} {make_option}" + # run_cmd(f"{make_cmd} clean") + build_result = run_cmd(f"{make_cmd} all") + r = 0 if build_result.returncode == 0 else 1 + print_build_result(board, example, r, time.monotonic() - start_time) - flash_size = "-" - sram_size = "-" - example = 'all' - title = build_utils.build_format.format(example, board, status, "{:.2f}s".format(duration), flash_size, sram_size) - print(title) + ret = [0, 0, 0] + ret[r] = 1 return ret -def build_board_make_all_examples(board, toolchain, all_examples): +def make_board(board, toolchain): + print(build_separator) + all_examples = get_examples(find_family(board)) start_time = time.monotonic() ret = [0, 0, 0] - with Pool(processes=os.cpu_count()) as pool: pool_args = list((map(lambda e, b=board, o=f"TOOLCHAIN={toolchain}": [e, b, o], all_examples))) - r = pool.starmap(build_utils.build_example, pool_args) + r = pool.starmap(make_one_example, pool_args) # sum all element of same index (column sum) - rsum = list(map(sum, list(zip(*r)))) - ret[0] += rsum[0] - ret[1] += rsum[1] - ret[2] += rsum[2] - duration = time.monotonic() - start_time - if ret[1] == 0: - status = SUCCEEDED - else: - status = FAILED - - flash_size = "-" - sram_size = "-" + ret = list(map(sum, list(zip(*r)))) example = 'all' - title = build_utils.build_format.format(example, board, status, "{:.2f}s".format(duration), flash_size, sram_size) - print(title) + print_build_result(board, example, 0 if ret[1] == 0 else 1, time.monotonic() - start_time) + return ret + + +# ----------------------------- +# Build Family +# ----------------------------- +def build_boards_list(boards, toolchain, build_system): + ret = [0, 0, 0] + for b in boards: + r = [0, 0, 0] + if build_system == 'cmake': + r = cmake_board(b, toolchain) + elif build_system == 'make': + r = make_board(b, toolchain) + ret[0] += r[0] + ret[1] += r[1] + ret[2] += r[2] return ret @@ -131,7 +163,6 @@ def build_family(family, toolchain, build_system, one_per_family, boards): all_boards.sort() ret = [0, 0, 0] - # If only-one flag is set, select one random board if one_per_family: for b in boards: @@ -140,21 +171,13 @@ def build_family(family, toolchain, build_system, one_per_family, boards): return ret all_boards = [random.choice(all_boards)] - # success, failed, skipped - all_examples = get_examples(family) - for board in all_boards: - r = [0, 0, 0] - if build_system == 'cmake': - r = build_board_cmake(board, toolchain) - elif build_system == 'make': - r = build_board_make_all_examples(board, toolchain, all_examples) - ret[0] += r[0] - ret[1] += r[1] - ret[2] += r[2] - + ret = build_boards_list(all_boards, toolchain, build_system) return ret +# ----------------------------- +# Main +# ----------------------------- def main(): parser = argparse.ArgumentParser() parser.add_argument('families', nargs='*', default=[], help='Families to build') @@ -175,7 +198,7 @@ def main(): return 1 print(build_separator) - print(build_utils.build_format.format('Example', 'Board', '\033[39mResult\033[0m', 'Time', 'Flash', 'SRAM')) + print(build_format.format('Board', 'Example', '\033[39mResult\033[0m', 'Time')) total_time = time.monotonic() result = [0, 0, 0] @@ -189,28 +212,22 @@ def main(): all_families = list(families) all_families.sort() - # succeeded, failed + # succeeded, failed, skipped for f in all_families: - fret = build_family(f, toolchain, build_system, one_per_family, boards) - result[0] += fret[0] - result[1] += fret[1] - result[2] += fret[2] - - # build boards - for b in boards: - r = [0, 0, 0] - if build_system == 'cmake': - r = build_board_cmake(b, toolchain) - elif build_system == 'make': - all_examples = get_examples(find_family(b)) - r = build_board_make_all_examples(b, toolchain, all_examples) + r = build_family(f, toolchain, build_system, one_per_family, boards) result[0] += r[0] result[1] += r[1] result[2] += r[2] + # build boards + r = build_boards_list(boards, toolchain, build_system) + result[0] += r[0] + result[1] += r[1] + result[2] += r[2] + total_time = time.monotonic() - total_time print(build_separator) - print(f"Build Summary: {result[0]} {SUCCEEDED}, {result[1]} {FAILED} and took {total_time:.2f}s") + print(f"Build Summary: {result[0]} {STATUS_OK}, {result[1]} {STATUS_FAILED} and took {total_time:.2f}s") print(build_separator) return result[1] diff --git a/tools/build_utils.py b/tools/build_utils.py index 32aca95dd..5f88db8a2 100644 --- a/tools/build_utils.py +++ b/tools/build_utils.py @@ -92,38 +92,3 @@ def build_size(make_cmd): return (flash_size, sram_size) return (0, 0) - - -def build_example(example, board, make_option): - start_time = time.monotonic() - flash_size = "-" - sram_size = "-" - - # succeeded, failed, skipped - ret = [0, 0, 0] - - make_cmd = f"make -j -C examples/{example} BOARD={board} {make_option}" - - # Check if board is skipped - if skip_example(example, board): - status = SKIPPED - ret[2] = 1 - print(build_format.format(example, board, status, '-', flash_size, sram_size)) - else: - build_result = subprocess.run(f"{make_cmd} all", shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) - - if build_result.returncode == 0: - status = SUCCEEDED - ret[0] = 1 - (flash_size, sram_size) = build_size(make_cmd) - else: - status = FAILED - ret[1] = 1 - - build_duration = time.monotonic() - start_time - print(build_format.format(example, board, status, "{:.2f}s".format(build_duration), flash_size, sram_size)) - - if build_result.returncode != 0: - print(build_result.stdout.decode("utf-8")) - - return ret -- cgit v1.3.1 From 858ad66c9316250876dad533e47513b7def915d1 Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Thu, 22 Aug 2024 12:37:11 +0700 Subject: circleci tweaks (#2770) * skip circleci build on master push * change max32666 probe to jlink, max32625pico is not reliable enough --- .circleci/config.yml | 4 ++++ .circleci/config2.yml | 8 +------- hw/bsp/max32690/family.cmake | 15 +-------------- test/hil/rpi.json | 13 ++++++++++--- 4 files changed, 16 insertions(+), 24 deletions(-) (limited to 'hw') diff --git a/.circleci/config.yml b/.circleci/config.yml index 8769926b1..5136d6331 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -71,5 +71,9 @@ jobs: workflows: set-matrix: + # Only build PR here, Push will be built by github action. + when: + and: + - not: << pipeline.git.branch.is_default >> jobs: - set-matrix diff --git a/.circleci/config2.yml b/.circleci/config2.yml index cd844c33f..70b5c60ac 100644 --- a/.circleci/config2.yml +++ b/.circleci/config2.yml @@ -100,12 +100,6 @@ commands: if [ << parameters.toolchain >> == esp-idf ]; then docker run --rm -v $PWD:/project -w /project espressif/idf:v5.1.1 python tools/build.py << parameters.family >> else - # Only build one board per family for non PRs i.e commit to master - ONE_PER_FAMILY="" - if [ -z "$CIRCLE_PULL_REQUEST" ]; then - ONE_PER_FAMILY="--one-per-family" - fi - # Toolchain option default is gcc if [ << parameters.toolchain >> == arm-clang ]; then TOOLCHAIN_OPTION="--toolchain clang" @@ -113,7 +107,7 @@ commands: TOOLCHAIN_OPTION="--toolchain gcc" fi - python tools/build.py $ONE_PER_FAMILY -s << parameters.build-system >> $TOOLCHAIN_OPTION << parameters.family >> + python tools/build.py -s << parameters.build-system >> $TOOLCHAIN_OPTION << parameters.family >> fi jobs: diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake index 736ca8eac..96dcfedff 100644 --- a/hw/bsp/max32690/family.cmake +++ b/hw/bsp/max32690/family.cmake @@ -148,18 +148,5 @@ function(family_configure_example TARGET RTOS) # Flashing family_flash_jlink(${TARGET}) - family_flash_msdk(${TARGET}) -endfunction() - -# Add flash msdk target -function(family_flash_msdk TARGET) - set(MAXIM_PATH "$ENV{MAXIM_PATH}") - - add_custom_target(${TARGET}-msdk - DEPENDS ${TARGET} - COMMAND ${MAXIM_PATH}/Tools/OpenOCD/openocd -s ${MAXIM_PATH}/Tools/OpenOCD/scripts - -f interface/cmsis-dap.cfg -f target/max32690.cfg - -c "program $ verify; init; reset; exit" - VERBATIM - ) + family_flash_openocd_adi(${TARGET}) endfunction() diff --git a/test/hil/rpi.json b/test/hil/rpi.json index 49d2d8286..8eaca2621 100644 --- a/test/hil/rpi.json +++ b/test/hil/rpi.json @@ -17,9 +17,9 @@ { "name": "max32666fthr", "uid": "0C81464124010B20FF0A08CC2C", - "flasher": "openocd_adi", - "flasher_sn": "042217023bffc88100000000000000000000000097969906", - "flasher_args": "-f interface/cmsis-dap.cfg -f target/max32665.cfg" + "flasher": "jlink", + "flasher_sn": "000801011822", + "flasher_args": "-device max32666" }, { "name": "lpcxpresso11u37", @@ -83,6 +83,13 @@ "flasher": "esptool", "flasher_sn": "3ea619acd1cdeb11a0a0b806e93fd3f1", "flasher_args": "-b 921600" + }, + { + "name": "max32666fthr", + "uid": "0C81464124010B20FF0A08CC2C", + "flasher": "openocd_adi", + "flasher_sn": "042217023bffc88100000000000000000000000097969906", + "flasher_args": "-f interface/cmsis-dap.cfg -f target/max32665.cfg" } ] } -- cgit v1.3.1 From 0db42aac71a6fb2a821a034ee29d2587638d309a Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 22 Aug 2024 18:06:48 +0700 Subject: add hil support for dual host_info_to_cdc replace itsybitsy m4 by metro m4 + max3421e --- examples/dual/host_info_to_device_cdc/src/main.c | 26 ++++--- .../samd5x_e5x/boards/metro_m4_express/board.cmake | 3 + test/hil/hil_test.py | 89 ++++++++++++++-------- test/hil/rpi.json | 25 ++++-- 4 files changed, 95 insertions(+), 48 deletions(-) (limited to 'hw') diff --git a/examples/dual/host_info_to_device_cdc/src/main.c b/examples/dual/host_info_to_device_cdc/src/main.c index 5be531098..443cc4674 100644 --- a/examples/dual/host_info_to_device_cdc/src/main.c +++ b/examples/dual/host_info_to_device_cdc/src/main.c @@ -24,7 +24,7 @@ */ /* Host example will get device descriptors of attached devices and print it out via device cdc as follows: - * Device 1: ID 046d:c52f + * Device 1: ID 046d:c52f SN 11223344 Device Descriptor: bLength 18 bDescriptorType 1 @@ -147,7 +147,21 @@ void print_device_info(uint8_t daddr) { return; } - cdc_printf("Device %u: ID %04x:%04x\r\n", daddr, desc_device.idVendor, desc_device.idProduct); + // Get String descriptor using Sync API + uint16_t serial[64]; + uint16_t buf[128]; + + cdc_printf("Device %u: ID %04x:%04x SN ", daddr, desc_device.idVendor, desc_device.idProduct); + xfer_result = tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, serial, sizeof(serial)); + if (XFER_RESULT_SUCCESS != xfer_result) { + serial[0] = 'n'; + serial[1] = '/'; + serial[2] = 'a'; + serial[3] = 0; + } + print_utf16(serial, TU_ARRAY_SIZE(serial)); + tud_cdc_write_str("\r\n"); + cdc_printf("Device Descriptor:\r\n"); cdc_printf(" bLength %u\r\n" , desc_device.bLength); cdc_printf(" bDescriptorType %u\r\n" , desc_device.bDescriptorType); @@ -160,9 +174,6 @@ void print_device_info(uint8_t daddr) { cdc_printf(" idProduct 0x%04x\r\n" , desc_device.idProduct); cdc_printf(" bcdDevice %04x\r\n" , desc_device.bcdDevice); - // Get String descriptor using Sync API - uint16_t buf[128]; - cdc_printf(" iManufacturer %u " , desc_device.iManufacturer); xfer_result = tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, buf, sizeof(buf)); if (XFER_RESULT_SUCCESS == xfer_result ) { @@ -178,10 +189,7 @@ void print_device_info(uint8_t daddr) { tud_cdc_write_str("\r\n"); cdc_printf(" iSerialNumber %u " , desc_device.iSerialNumber); - xfer_result = tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, buf, sizeof(buf)); - if (XFER_RESULT_SUCCESS == xfer_result) { - print_utf16(buf, TU_ARRAY_SIZE(buf)); - } + tud_cdc_write_str((char*)serial); // serial is already to UTF-8 tud_cdc_write_str("\r\n"); cdc_printf(" bNumConfigurations %u\r\n" , desc_device.bNumConfigurations); diff --git a/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.cmake b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.cmake index 86d12ca24..ebc32b1f7 100644 --- a/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.cmake +++ b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.cmake @@ -3,6 +3,9 @@ set(SAM_FAMILY samd51) set(JLINK_DEVICE ATSAMD51J19) set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld) +# force max3421e for testing with hardware-in-the-loop +set(MAX3421_HOST 1) + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC __SAMD51J19A__ diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py index 09c30bf52..5a4799cfb 100644 --- a/test/hil/hil_test.py +++ b/test/hil/hil_test.py @@ -27,6 +27,7 @@ import argparse import os +import re import sys import time import serial @@ -212,14 +213,39 @@ def flash_uniflash(board, firmware): # ------------------------------------------------------------- -# Tests +# Tests: dual # ------------------------------------------------------------- -def test_board_test(board): + +def test_dual_host_info_to_device_cdc(board): + uid = board['uid'] + declared_devs = [f'{d["vid_pid"]}_{d["serial"]}' for d in board['tests']['dual_attached']] + + port = get_serial_dev(uid, 'TinyUSB', "TinyUSB_Device", 0) + ser = open_serial_dev(port) + # read from cdc, first line should contain vid/pid and serial + data = ser.read(1000) + lines = data.decode('utf-8').splitlines() + enum_dev_sn = [] + for l in lines: + vid_pid_sn = re.search(r'ID ([0-9a-fA-F]+):([0-9a-fA-F]+) SN (\w+)', l) + if vid_pid_sn: + print(f'\r\n {l} ', end='') + enum_dev_sn.append(f'{vid_pid_sn.group(1)}_{vid_pid_sn.group(2)}_{vid_pid_sn.group(3)}') + + assert(set(declared_devs) == set(enum_dev_sn)), \ + f'Enumerated devices {enum_dev_sn} not match with declared {declared_devs}' + return 0 + + +# ------------------------------------------------------------- +# Tests: device +# ------------------------------------------------------------- +def test_device_board_test(board): # Dummy test pass -def test_cdc_dual_ports(board): +def test_device_cdc_dual_ports(board): uid = board['uid'] port1 = get_serial_dev(uid, 'TinyUSB', "TinyUSB_Device", 0) port2 = get_serial_dev(uid, 'TinyUSB', "TinyUSB_Device", 2) @@ -241,7 +267,7 @@ def test_cdc_dual_ports(board): assert ser2.read(100) == str2.upper(), 'Port2 wrong data' -def test_cdc_msc(board): +def test_device_cdc_msc(board): uid = board['uid'] # Echo test port = get_serial_dev(uid, 'TinyUSB', "TinyUSB_Device", 0) @@ -262,11 +288,11 @@ issue at github.com/hathach/tinyusb" assert data == readme, 'MSC wrong data' -def test_cdc_msc_freertos(board): - test_cdc_msc(board) +def test_device_cdc_msc_freertos(board): + test_device_cdc_msc(board) -def test_dfu(board): +def test_device_dfu(board): uid = board['uid'] # Wait device enum @@ -308,7 +334,7 @@ def test_dfu(board): os.remove(f_dfu1) -def test_dfu_runtime(board): +def test_device_dfu_runtime(board): uid = board['uid'] # Wait device enum @@ -325,7 +351,7 @@ def test_dfu_runtime(board): assert timeout, 'Device not available' -def test_hid_boot_interface(board): +def test_device_hid_boot_interface(board): uid = board['uid'] kbd = get_hid_dev(uid, 'TinyUSB', 'TinyUSB_Device', 'event-kbd') mouse1 = get_hid_dev(uid, 'TinyUSB', 'TinyUSB_Device', 'if01-event-mouse') @@ -341,7 +367,7 @@ def test_hid_boot_interface(board): assert timeout, 'HID device not available' -def test_hid_composite_freertos(id): +def test_device_hid_composite_freertos(id): # TODO implement later pass @@ -351,13 +377,15 @@ def test_hid_composite_freertos(id): # ------------------------------------------------------------- # all possible tests: board_test is added last to disable board's usb all_tests = [ - 'cdc_dual_ports', - 'cdc_msc', - 'dfu', - 'cdc_msc_freertos', # dont test 2 cdc_msc next to each other, since they have same vid/pid. Can be confused by host - 'dfu_runtime', - 'hid_boot_interface', - 'board_test' + 'device/cdc_dual_ports', + 'device/cdc_msc', + 'device/dfu', + 'device/cdc_msc_freertos', # don't test 2 cdc_msc next to each other + 'device/dfu_runtime', + 'device/hid_boot_interface', + + 'dual/host_info_to_device_cdc', + 'device/board_test' ] @@ -366,23 +394,23 @@ def test_board(board): flasher = board['flasher'].lower() # default to all tests - if 'tests' in board: - test_list = board['tests'] + ['board_test'] - else: - test_list = list(all_tests) + test_list = list(all_tests) - # remove skip_tests - if 'tests_skip' in board: - for skip in board['tests_skip']: - if skip in test_list: - test_list.remove(skip) + if 'tests' in board: + board_tests = board['tests'] + if 'only' in board_tests: + test_list = board_tests['only'] + ['device/board_test'] + if 'skip' in board_tests: + for skip in board_tests['skip']: + if skip in test_list: + test_list.remove(skip) err_count = 0 for test in test_list: - fw_dir = f'cmake-build/cmake-build-{name}/device/{test}' + fw_dir = f'cmake-build/cmake-build-{name}/{test}' if not os.path.exists(fw_dir): - fw_dir = f'examples/cmake-build-{name}/device/{test}' - fw_name = f'{fw_dir}/{test}' + fw_dir = f'examples/cmake-build-{name}/{test}' + fw_name = f'{fw_dir}/{os.path.basename(test)}' print(f'{name:30} {test:20} ... ', end='') if not os.path.exists(fw_dir): @@ -400,7 +428,7 @@ def test_board(board): if ret.returncode == 0: try: - ret = globals()[f'test_{test}'](board) + ret = globals()[f'test_{test.replace("/", "_")}'](board) print('OK') except Exception as e: err_count += 1 @@ -409,7 +437,6 @@ def test_board(board): else: err_count += 1 print('Flash failed') - return err_count diff --git a/test/hil/rpi.json b/test/hil/rpi.json index 8eaca2621..3f07a8f42 100644 --- a/test/hil/rpi.json +++ b/test/hil/rpi.json @@ -8,11 +8,18 @@ "flasher_args": "-device nrf52840_xxaa" }, { - "name": "itsybitsy_m4", - "uid": "D784B28C5338533335202020FF044726", + "name": "metro_m4_express", + "uid": "9995AD485337433231202020FF100A34", "flasher": "openocd", - "flasher_sn": "E6614C311B597D32", - "flasher_args": "-f interface/cmsis-dap.cfg -f target/atsame5x.cfg -c \"adapter speed 5000\"" + "flasher_sn": "E6633861A3978538", + "flasher_args": "-f interface/cmsis-dap.cfg -f target/atsame5x.cfg", + "tests": { + "dual_attached": [ + { + "vid_pid": "1a86_55d4", "serial": "52D2002130" + } + ] + } }, { "name": "max32666fthr", @@ -31,7 +38,9 @@ { "name": "ra4m1_ek", "uid": "152E163038303131393346E46F26574B", - "tests_skip": ["cdc_msc", "cdc_msc_freertos"], + "tests": { + "skip": ["device/cdc_msc", "device/cdc_msc_freertos"] + }, "comment": "MSC is slow to enumerated #2602", "flasher": "jlink", "flasher_sn": "000831174392", @@ -77,9 +86,9 @@ { "name": "espressif_s3_devkitm", "uid": "84F703C084E4", - "tests": [ - "cdc_msc_freertos", "hid_composite_freertos" - ], + "tests": { + "only": ["device/cdc_msc_freertos", "device/hid_composite_freertos"] + }, "flasher": "esptool", "flasher_sn": "3ea619acd1cdeb11a0a0b806e93fd3f1", "flasher_args": "-b 921600" -- cgit v1.3.1 From ccf886ca80ed74d985483fdb90e67703ebeb7dad Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 22 Aug 2024 18:51:32 +0700 Subject: add pio-usb host test to hil. fix build as well --- hw/bsp/rp2040/family.c | 4 ++-- test/hil/rpi.json | 11 +++++------ 2 files changed, 7 insertions(+), 8 deletions(-) (limited to 'hw') diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c index 250989ce9..64a3a0af6 100644 --- a/hw/bsp/rp2040/family.c +++ b/hw/bsp/rp2040/family.c @@ -42,7 +42,7 @@ static uart_inst_t *uart_inst; #endif -#if CFG_TUH_RPI_PIO_USB || CFG_TUD_RPI_PIO_USB +#if (CFG_TUH_ENABLED && CFG_TUH_RPI_PIO_USB) || (CFG_TUD_ENABLED && CFG_TUD_RPI_PIO_USB) #include "pio_usb.h" #endif @@ -126,7 +126,7 @@ void stdio_rtt_init(void) { void board_init(void) { -#if CFG_TUH_RPI_PIO_USB || CFG_TUD_RPI_PIO_USB +#if (CFG_TUH_ENABLED && CFG_TUH_RPI_PIO_USB) || (CFG_TUD_ENABLED && CFG_TUD_RPI_PIO_USB) // Set the system clock to a multiple of 120mhz for bitbanging USB with pico-usb set_sys_clock_khz(120000, true); diff --git a/test/hil/rpi.json b/test/hil/rpi.json index 3f07a8f42..b75c1339b 100644 --- a/test/hil/rpi.json +++ b/test/hil/rpi.json @@ -14,11 +14,7 @@ "flasher_sn": "E6633861A3978538", "flasher_args": "-f interface/cmsis-dap.cfg -f target/atsame5x.cfg", "tests": { - "dual_attached": [ - { - "vid_pid": "1a86_55d4", "serial": "52D2002130" - } - ] + "dual_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002130"}] } }, { @@ -51,7 +47,10 @@ "uid": "E6614C311B764A37", "flasher": "openocd", "flasher_sn": "E6614103E72C1D2F", - "flasher_args": "-f interface/cmsis-dap.cfg -f target/rp2040.cfg -c \"adapter speed 5000\"" + "flasher_args": "-f interface/cmsis-dap.cfg -f target/rp2040.cfg -c \"adapter speed 5000\"", + "tests": { + "dual_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002470"}] + } }, { "name": "stm32f072disco", -- cgit v1.3.1 From 45d06cd4ab2adea07513243447b6ec729d7d8c2c Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 22 Aug 2024 22:25:14 +0700 Subject: skip dual/host_info_to_device_cdc for pico due to a bug in pio-usb --- hw/bsp/family_support.cmake | 2 +- hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake | 2 +- test/hil/rpi.json | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) (limited to 'hw') diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 1df8a6f53..b457fcfac 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -463,7 +463,7 @@ function(family_flash_openocd TARGET) # note skip verify since it has issue with rp2040 add_custom_target(${TARGET}-openocd DEPENDS ${TARGET} - COMMAND ${OPENOCD} ${OPTION_LIST} -c init -c halt -c "program $ reset" ${OPTION_LIST2} -c exit + COMMAND ${OPENOCD} -c "tcl_port disabled" -c "gdb_port disabled" ${OPTION_LIST} -c init -c halt -c "program $" -c reset ${OPTION_LIST2} -c exit VERBATIM ) endfunction() diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake index 6ff1a7b59..a0282aa23 100644 --- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake +++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.cmake @@ -2,7 +2,7 @@ set(MCU_VARIANT nrf52840) set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/nrf52840_s140_v6.ld) # enable max3421 host driver for this board -set(MAX3421_HOST 1) +# set(MAX3421_HOST 1) function(update_board TARGET) endfunction() diff --git a/test/hil/rpi.json b/test/hil/rpi.json index b75c1339b..7821f1660 100644 --- a/test/hil/rpi.json +++ b/test/hil/rpi.json @@ -49,6 +49,7 @@ "flasher_sn": "E6614103E72C1D2F", "flasher_args": "-f interface/cmsis-dap.cfg -f target/rp2040.cfg -c \"adapter speed 5000\"", "tests": { + "skip": ["dual/host_info_to_device_cdc"], "dual_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002470"}] } }, -- cgit v1.3.1 From 27ddf19631d135df15f3388686f59e379e146dbb Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 26 Aug 2024 12:24:29 +0700 Subject: add sndfifo owner info to skip rewriting data for retrying NAKed --- README.rst | 2 +- hw/bsp/family_support.cmake | 6 + src/host/usbh.h | 2 +- src/portable/analog/max3421/hcd_max3421.c | 191 +++++++++++++++++++----------- 4 files changed, 127 insertions(+), 74 deletions(-) (limited to 'hw') diff --git a/README.rst b/README.rst index 6dd0e2714..2ffe3823a 100644 --- a/README.rst +++ b/README.rst @@ -197,7 +197,7 @@ Docs - `Structure`_ - `Porting`_ -.. |Build Status| image:: https://github.com/hathach/tinyusb/actions/workflows/cmake_arm.yml/badge.svg +.. |Build Status| image:: https://github.com/hathach/tinyusb/actions/workflows/build.yml/badge.svg :target: https://github.com/hathach/tinyusb/actions .. |CircleCI Status| image:: https://dl.circleci.com/status-badge/img/circleci/4AYHvUhFxdnY4rA7LEsdqW/QmrpoL2AjGqetvFQNqtWyq/tree/master.svg?style=svg :target: https://dl.circleci.com/status-badge/redirect/circleci/4AYHvUhFxdnY4rA7LEsdqW/QmrpoL2AjGqetvFQNqtWyq/tree/master diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index b457fcfac..aa5e037d1 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -418,6 +418,12 @@ exit" COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} ${OPTION_LIST} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $/${TARGET}.jlink VERBATIM ) + + # optional flash post build +# add_custom_command(TARGET ${TARGET} POST_BUILD +# COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} ${OPTION_LIST} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $/${TARGET}.jlink +# VERBATIM +# ) endfunction() diff --git a/src/host/usbh.h b/src/host/usbh.h index 359684169..d0a5732e5 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -81,7 +81,7 @@ enum { }; typedef struct { - uint8_t max_nak; // max NAK per endpoint per frame + uint8_t max_nak; // max NAK per endpoint per frame to save CPU/SPI bus usage uint8_t cpuctl; // R16: CPU Control Register uint8_t pinctl; // R17: Pin Control Register. FDUPSPI bit is ignored } tuh_configure_max3421_t; diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 3d054b66e..215feb481 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -168,14 +168,14 @@ enum { }; enum { - MAX_NAK_DEFAULT = 1 // Number of NAK per endpoint per usb frame + MAX_NAK_DEFAULT = 1 // Number of NAK per endpoint per usb frame to save CPU/SPI bus usage }; enum { EP_STATE_IDLE = 0, EP_STATE_COMPLETE = 1, EP_STATE_ABORTING = 2, - EP_STATE_ATTEMPT_1 = 3, // pending 1st attempt + EP_STATE_ATTEMPT_1 = 3, // Number of attempts to transfer in a frame. Incremented after each NAK EP_STATE_ATTEMPT_MAX = 15 }; @@ -183,17 +183,20 @@ enum { // //--------------------------------------------------------------------+ +typedef struct TU_ATTR_PACKED { + uint8_t ep_num : 4; + uint8_t is_setup : 1; + uint8_t is_out : 1; + uint8_t is_iso : 1; +} hxfr_bm_t; + +TU_VERIFY_STATIC(sizeof(hxfr_bm_t) == 1, "size is not correct"); + typedef struct { uint8_t daddr; - union { ; - struct TU_ATTR_PACKED { - uint8_t ep_num : 4; - uint8_t is_setup : 1; - uint8_t is_out : 1; - uint8_t is_iso : 1; - }hxfr_bm; - + union { + hxfr_bm_t hxfr_bm; uint8_t hxfr; }; @@ -203,13 +206,12 @@ typedef struct { uint16_t packet_size : 11; }; - bool received_nak; uint16_t total_len; uint16_t xferred_len; uint8_t* buf; } max3421_ep_t; -TU_VERIFY_STATIC(sizeof(max3421_ep_t) == 16, "size is not correct"); +TU_VERIFY_STATIC(sizeof(max3421_ep_t) == 12, "size is not correct"); typedef struct { volatile uint16_t frame_count; @@ -220,7 +222,16 @@ typedef struct { uint8_t hien; uint8_t mode; uint8_t peraddr; - uint8_t hxfr; + union { + hxfr_bm_t hxfr_bm; + uint8_t hxfr; + }; + + // owner of data in SNDFIFO, for retrying NAKed without re-writing to FIFO + struct { + uint8_t daddr; + uint8_t hxfr; + }sndfifo_owner; atomic_flag busy; // busy transferring @@ -318,33 +329,9 @@ bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_is return ret; } -static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint16_t len, bool in_isr) { - uint8_t hirq; - reg |= CMDBYTE_WRITE; - - max3421_spi_lock(rhport, in_isr); - - tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); - _hcd_data.hirq = hirq; - tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len); - - max3421_spi_unlock(rhport, in_isr); -} - -static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) { - uint8_t hirq; - uint8_t const reg = RCVVFIFO_ADDR; - - max3421_spi_lock(rhport, in_isr); - - tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); - _hcd_data.hirq = hirq; - tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len); - - max3421_spi_unlock(rhport, in_isr); -} - -//------------- register write helper -------------// +//-------------------------------------------------------------------- +// Register helper +//-------------------------------------------------------------------- TU_ATTR_ALWAYS_INLINE static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) { reg_write(rhport, HIRQ_ADDR, data, in_isr); // HIRQ write 1 is clear @@ -378,6 +365,47 @@ TU_ATTR_ALWAYS_INLINE static inline void sndbc_write(uint8_t rhport, uint8_t dat reg_write(rhport, SNDBC_ADDR, data, in_isr); } +//-------------------------------------------------------------------- +// FIFO access (receive, send, setup) +//-------------------------------------------------------------------- +static void hwfifo_write(uint8_t rhport, uint8_t reg, const uint8_t* buffer, uint8_t len, bool in_isr) { + uint8_t hirq; + reg |= CMDBYTE_WRITE; + + max3421_spi_lock(rhport, in_isr); + + tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); + _hcd_data.hirq = hirq; + tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len); + + max3421_spi_unlock(rhport, in_isr); +} + +// Write to SNDFIFO if len > 0 and update SNDBC +TU_ATTR_ALWAYS_INLINE static inline void hwfifo_send(uint8_t rhport, const uint8_t* buffer, uint8_t len, bool in_isr) { + if (len) { + hwfifo_write(rhport, SNDFIFO_ADDR, buffer, len, in_isr); + } + sndbc_write(rhport, len, in_isr); +} + +TU_ATTR_ALWAYS_INLINE static inline void hwfifo_setup(uint8_t rhport, const uint8_t* buffer, bool in_isr) { + hwfifo_write(rhport, SUDFIFO_ADDR, buffer, 8, in_isr); +} + +static void hwfifo_receive(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) { + uint8_t hirq; + uint8_t const reg = RCVVFIFO_ADDR; + + max3421_spi_lock(rhport, in_isr); + + tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); + _hcd_data.hirq = hirq; + tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len); + + max3421_spi_unlock(rhport, in_isr); +} + //--------------------------------------------------------------------+ // Endpoint helper //--------------------------------------------------------------------+ @@ -418,7 +446,7 @@ static void free_ep(uint8_t daddr) { } } -// Check if endpoint has an queued transfer and not reach max NAK +// Check if endpoint has a queued transfer and not reach max NAK in this frame TU_ATTR_ALWAYS_INLINE static inline bool is_ep_pending(max3421_ep_t const * ep) { uint8_t const state = ep->state; return ep->packet_size && (state >= EP_STATE_ATTEMPT_1) && @@ -488,6 +516,7 @@ bool hcd_init(uint8_t rhport) { reg_write(rhport, PINCTL_ADDR, _tuh_cfg.pinctl | PINCTL_FDUPSPI, false); // v1 is 0x01, v2 is 0x12, v3 is 0x13 + // Note: v1 and v2 has host OUT errata whose workaround is not implemented in this driver uint8_t const revision = reg_read(rhport, REVISION_ADDR, false); TU_LOG2_HEX(revision); TU_ASSERT(revision == 0x01 || revision == 0x12 || revision == 0x13, false); @@ -616,27 +645,44 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e return true; } +/* The microcontroller repeatedly writes the SNDFIFO register R2 to load the FIFO with up to 64 data bytes. + * Then the microcontroller writes the SNDBC register, which this does three things: + * 1. Tells the MAX3421E SIE (Serial Interface Engine) how many bytes in the FIFO to send. + * 2. Connects the SNDFIFO and SNDBC register to the USB logic for USB transmission. + * 3. Clears the SNDBAVIRQ interrupt flag. If the second FIFO is available for µC loading, the SNDBAVIRQ immediately re-asserts. + + +-----------+ + --->| SNDBC-A | + / | SNDFIFO-A | + / +-----------+ + +------+ +-------------+ / +----------+ + | MCU |------>| R2: SNDFIFO |---- << Write R7 Flip >> ---| MAX3241E | + |(hcd) | | R7: SNDBC | / | SIE | + +------+ +-------------+ / +----------+ + +-----------+ / + | SNDBC-B | / + | SNDFIFO-B |<--- + +-----------+ + Note: xact_out() is called when starting a new transfer, continue a transfer (isr) or retry a transfer (NAK) + For NAK retry, we do not need to write to FIFO or SNDBC register again. +*/ static void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { // Page 12: Programming BULK-OUT Transfers - // TODO double buffered + // TODO: double buffering for ISO transfer if (switch_ep) { peraddr_write(rhport, ep->daddr, in_isr); - - uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0); + const uint8_t hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0); reg_write(rhport, HCTL_ADDR, hctl, in_isr); } - if (!ep->received_nak){ - // do not write to fifo or sdnbc register again if previous attempt got NAK - uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size); - if (xact_len) { - // only check SNDBAV IRQ if there is data to send - TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,); - fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr); - } - - sndbc_write(rhport, xact_len, in_isr); + // Only write to sndfifo and sdnbc register if it is not a NAKed retry + if (!(ep->daddr == _hcd_data.sndfifo_owner.daddr && ep->hxfr == _hcd_data.sndfifo_owner.hxfr)) { + // skip SNDBAV IRQ check, overwrite sndfifo if needed + const uint8_t xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size); + hwfifo_send(rhport, ep->buf, xact_len, in_isr); } + _hcd_data.sndfifo_owner.daddr = ep->daddr; + _hcd_data.sndfifo_owner.hxfr = ep->hxfr; hxfr_write(rhport, ep->hxfr, in_isr); } @@ -655,7 +701,7 @@ static void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_is static void xact_setup(uint8_t rhport, max3421_ep_t *ep, bool in_isr) { peraddr_write(rhport, ep->daddr, in_isr); - fifo_write(rhport, SUDFIFO_ADDR, ep->buf, 8, in_isr); + hwfifo_setup(rhport, ep->buf, in_isr); hxfr_write(rhport, HXFR_SETUP, in_isr); } @@ -669,7 +715,7 @@ static void xact_generic(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool // status if (ep->buf == NULL || ep->total_len == 0) { - uint8_t const hxfr = (uint8_t) (HXFR_HS | (ep->hxfr & HXFR_OUT_NIN)); + const uint8_t hxfr = (uint8_t) (HXFR_HS | (ep->hxfr & HXFR_OUT_NIN)); peraddr_write(rhport, ep->daddr, in_isr); hxfr_write(rhport, hxfr, in_isr); return; @@ -830,11 +876,11 @@ static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t re } static void handle_xfer_done(uint8_t rhport, bool in_isr) { - uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, in_isr); - uint8_t const hresult = hrsl & HRSL_RESULT_MASK; - uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; - uint8_t const hxfr_type = _hcd_data.hxfr & 0xf0; - uint8_t const ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1; + const uint8_t hrsl = reg_read(rhport, HRSL_ADDR, in_isr); + const uint8_t hresult = hrsl & HRSL_RESULT_MASK; + const uint8_t ep_num = _hcd_data.hxfr_bm.ep_num; + const uint8_t hxfr_type = _hcd_data.hxfr & 0xf0; + const uint8_t ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1; max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, ep_dir); TU_VERIFY(ep, ); @@ -849,9 +895,9 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) { // control endpoint -> retry immediately and return hxfr_write(rhport, _hcd_data.hxfr, in_isr); return; - } else if (EP_STATE_ATTEMPT_1 <= ep->state && ep->state < EP_STATE_ATTEMPT_MAX) { + } + if (EP_STATE_ATTEMPT_1 <= ep->state && ep->state < EP_STATE_ATTEMPT_MAX) { ep->state++; - ep->received_nak = true; } } @@ -861,7 +907,6 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) { hxfr_write(rhport, _hcd_data.hxfr, in_isr); } else if (next_ep) { // switch to next pending endpoint - // TODO could have issue with double buffered if not clear previously out data xact_generic(rhport, next_ep, true, in_isr); } else { // no more pending in this frame -> clear busy @@ -875,7 +920,6 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) { case HRSL_SUCCESS: xfer_result = XFER_RESULT_SUCCESS; - ep->received_nak = false; break; case HRSL_STALL: @@ -905,11 +949,15 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) { if (ep->state == EP_STATE_COMPLETE) { xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr); }else { - // more to transfer - hxfr_write(rhport, _hcd_data.hxfr, in_isr); + hxfr_write(rhport, _hcd_data.hxfr, in_isr); // more to transfer } } else { // SETUP or OUT transfer + + // clear sndfifo owner since data is sent + _hcd_data.sndfifo_owner.daddr = 0xff; + _hcd_data.sndfifo_owner.hxfr = 0xff; + uint8_t xact_len; if (hxfr_type & HXFR_SETUP) { @@ -926,8 +974,7 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) { if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) { xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr); } else { - // more to transfer - xact_out(rhport, ep, false, in_isr); + xact_out(rhport, ep, false, in_isr); // more to transfer } } } @@ -987,16 +1034,16 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { // not call this handler again. So we need to loop until all IRQ are cleared while (hirq & (HIRQ_RCVDAV_IRQ | HIRQ_HXFRDN_IRQ)) { if (hirq & HIRQ_RCVDAV_IRQ) { - uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; + const uint8_t ep_num = _hcd_data.hxfr_bm.ep_num; max3421_ep_t* ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1); uint8_t xact_len = 0; // RCVDAV_IRQ can trigger 2 times (dual buffered) while (hirq & HIRQ_RCVDAV_IRQ) { - uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, in_isr); + const uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, in_isr); xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len); if (xact_len) { - fifo_read(rhport, ep->buf, xact_len, in_isr); + hwfifo_receive(rhport, ep->buf, xact_len, in_isr); ep->buf += xact_len; ep->xferred_len += xact_len; } -- cgit v1.3.1 From 29d4c82efb9654aa8739cd806a9e81d37830e23e Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 27 Aug 2024 16:38:26 +0700 Subject: reset usb when init for max32650/66. change hil max32 to use pico (cmsis dap2), change metro m4 flasher --- hw/bsp/max32650/family.c | 1 + hw/bsp/max32650/family.cmake | 2 +- hw/bsp/max32666/family.c | 1 + test/hil/rpi.json | 19 ++++++------------- 4 files changed, 9 insertions(+), 14 deletions(-) (limited to 'hw') diff --git a/hw/bsp/max32650/family.c b/hw/bsp/max32650/family.c index 89a5db160..bb382cdd4 100644 --- a/hw/bsp/max32650/family.c +++ b/hw/bsp/max32650/family.c @@ -94,6 +94,7 @@ void board_init(void) { } MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); + MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB); } //--------------------------------------------------------------------+ diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake index e05bd7652..48853b92c 100644 --- a/hw/bsp/max32650/family.cmake +++ b/hw/bsp/max32650/family.cmake @@ -148,10 +148,10 @@ function(family_configure_example TARGET RTOS) # Flashing family_flash_jlink(${TARGET}) + family_flash_openocd_adi(${TARGET}) # Add the optional MSDK OpenOCD flashing family_flash_msdk(${TARGET}) - family_flash_openocd_adi(${TARGET}) endfunction() function(family_flash_msdk TARGET) diff --git a/hw/bsp/max32666/family.c b/hw/bsp/max32666/family.c index 8ee4b6762..f96393fe1 100644 --- a/hw/bsp/max32666/family.c +++ b/hw/bsp/max32666/family.c @@ -93,6 +93,7 @@ void board_init(void) { } MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); + MXC_SYS_Reset_Periph(MXC_SYS_RESET_USB); } //--------------------------------------------------------------------+ diff --git a/test/hil/rpi.json b/test/hil/rpi.json index 7821f1660..259f8ca83 100644 --- a/test/hil/rpi.json +++ b/test/hil/rpi.json @@ -10,9 +10,9 @@ { "name": "metro_m4_express", "uid": "9995AD485337433231202020FF100A34", - "flasher": "openocd", - "flasher_sn": "E6633861A3978538", - "flasher_args": "-f interface/cmsis-dap.cfg -f target/atsame5x.cfg", + "flasher": "jlink", + "flasher_sn": "123456", + "flasher_args": "-device ATSAMD51J19", "tests": { "dual_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002130"}] } @@ -20,9 +20,9 @@ { "name": "max32666fthr", "uid": "0C81464124010B20FF0A08CC2C", - "flasher": "jlink", - "flasher_sn": "000801011822", - "flasher_args": "-device max32666" + "flasher": "openocd_adi", + "flasher_sn": "E6614C311B597D32", + "flasher_args": "-f interface/cmsis-dap.cfg -f target/max32665.cfg" }, { "name": "lpcxpresso11u37", @@ -92,13 +92,6 @@ "flasher": "esptool", "flasher_sn": "3ea619acd1cdeb11a0a0b806e93fd3f1", "flasher_args": "-b 921600" - }, - { - "name": "max32666fthr", - "uid": "0C81464124010B20FF0A08CC2C", - "flasher": "openocd_adi", - "flasher_sn": "042217023bffc88100000000000000000000000097969906", - "flasher_args": "-f interface/cmsis-dap.cfg -f target/max32665.cfg" } ] } -- cgit v1.3.1 From c419b1e7c57ab701c904adfe6ebf14f780862557 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 13 Sep 2024 19:12:26 +0700 Subject: add pico2 rp2350 (arm) board add pico2 to hil ci --- .idea/cmake.xml | 4 +++- .../boards/feather_rp2040_max3421/board.cmake | 1 + hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake | 1 + .../rp2040/boards/raspberry_pi_pico2/board.cmake | 2 ++ hw/bsp/rp2040/family.cmake | 27 +++++++++++++++------- test/hil/hil_test.py | 20 +++++++++++----- test/hil/rpi.json | 10 ++++++++ 7 files changed, 50 insertions(+), 15 deletions(-) create mode 100644 hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake (limited to 'hw') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index fec01a08e..96ff19c89 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -2,7 +2,9 @@ - + + + diff --git a/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.cmake b/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.cmake index b8e5890f3..2afe0f264 100644 --- a/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.cmake +++ b/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.cmake @@ -1,3 +1,4 @@ +set(PICO_PLATFORM rp2040) set(PICO_BOARD adafruit_feather_rp2040) # Enable MAX3421E USB Host diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake index f9887c09c..804cdb50a 100644 --- a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake +++ b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake @@ -1 +1,2 @@ +set(PICO_PLATFORM rp2040) set(PICO_BOARD pico) diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake new file mode 100644 index 000000000..3482e2674 --- /dev/null +++ b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake @@ -0,0 +1,2 @@ +set(PICO_PLATFORM rp2350-arm-s) +set(PICO_BOARD pico2) diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index d91821ffa..8f01eac74 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -6,21 +6,32 @@ if (NOT BOARD) set(BOARD pico_sdk) endif() -if (TOOLCHAIN STREQUAL "clang") - set(PICO_COMPILER "pico_arm_clang") -else() - set(PICO_COMPILER "pico_arm_gcc") -endif() +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +#if (TOOLCHAIN STREQUAL "clang") +# set(PICO_COMPILER "pico_arm_clang") +#else() +# set(PICO_COMPILER "pico_arm_gcc") +#endif() # add the SDK in case we are standalone tinyusb example (noop if already present) include(${CMAKE_CURRENT_LIST_DIR}/pico_sdk_import.cmake) # include basic family CMake functionality set(FAMILY_MCUS RP2040) -set(JLINK_DEVICE rp2040_m0_0) -set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/rp2040.cfg -c \"adapter speed 5000\"") -include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) +if (PICO_PLATFORM STREQUAL "rp2040") + set(JLINK_DEVICE rp2040_m0_0) + set(OPENOCD_TARGET rp2040) +elseif (PICO_PLATFORM STREQUAL "rp2350-arm-s" OR PICO_PLATFORM STREQUAL "rp2350") + set(JLINK_DEVICE rp2350_m33_0) + set(OPENOCD_TARGET rp2350) +elseif (PICO_PLATFORM STREQUAL "rp2350-riscv") + set(JLINK_DEVICE rp2350_riscv_0) + set(OPENOCD_TARGET rp2350-riscv) +endif() + +set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/${OPENOCD_TARGET}.cfg -c \"adapter speed 5000\"") if (NOT PICO_TINYUSB_PATH) set(PICO_TINYUSB_PATH ${TOP}) diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py index 52ec5ae1d..a569e7666 100644 --- a/test/hil/hil_test.py +++ b/test/hil/hil_test.py @@ -43,6 +43,8 @@ STATUS_OK = "\033[32mOK\033[0m" STATUS_FAILED = "\033[31mFailed\033[0m" STATUS_SKIPPED = "\033[33mSkipped\033[0m" +verbose = False + # get usb serial by id def get_serial_dev(id, vendor_str, product_str, ifnum): if vendor_str and product_str: @@ -111,7 +113,6 @@ def read_disk_file(uid, lun, fname): # Flashing firmware # ------------------------------------------------------------- def run_cmd(cmd): - #print(cmd) r = subprocess.run(cmd, shell=True, stdout=subprocess.PIPE, stderr=subprocess.STDOUT) if r.returncode != 0: title = f'COMMAND FAILED: {cmd}' @@ -123,6 +124,9 @@ def run_cmd(cmd): else: print(title) print(r.stdout.decode("utf-8")) + elif verbose: + print(cmd) + print(r.stdout.decode("utf-8")) return r @@ -260,14 +264,14 @@ def test_device_cdc_dual_ports(board): str1 = b"test_no1" ser1.write(str1) ser1.flush() - assert ser1.read(100) == str1.lower(), 'Port1 wrong data' - assert ser2.read(100) == str1.upper(), 'Port2 wrong data' + assert ser1.read(len(str1)) == str1.lower(), 'Port1 wrong data' + assert ser2.read(len(str1)) == str1.upper(), 'Port2 wrong data' str2 = b"test_no2" ser2.write(str2) ser2.flush() - assert ser1.read(100) == str2.lower(), 'Port1 wrong data' - assert ser2.read(100) == str2.upper(), 'Port2 wrong data' + assert ser1.read(len(str2)) == str2.lower(), 'Port1 wrong data' + assert ser2.read(len(str2)) == str2.upper(), 'Port2 wrong data' def test_device_cdc_msc(board): @@ -279,7 +283,7 @@ def test_device_cdc_msc(board): str = b"test_str" ser.write(str) ser.flush() - assert ser.read(100) == str, 'CDC wrong data' + assert ser.read(len(str)) == str, 'CDC wrong data' # Block test data = read_disk_file(uid,0,'README.TXT') @@ -447,13 +451,17 @@ def main(): """ Hardware test on specified boards """ + global verbose + parser = argparse.ArgumentParser() parser.add_argument('config_file', help='Configuration JSON file') parser.add_argument('-b', '--board', action='append', default=[], help='Boards to test, all if not specified') + parser.add_argument('-v', '--verbose', action='store_true', help='Verbose output') args = parser.parse_args() config_file = args.config_file boards = args.board + verbose = args.verbose # if config file is not found, try to find it in the same directory as this script if not os.path.exists(config_file): diff --git a/test/hil/rpi.json b/test/hil/rpi.json index 36376a873..77919f346 100644 --- a/test/hil/rpi.json +++ b/test/hil/rpi.json @@ -52,6 +52,16 @@ "dual_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002470"}] } }, + { + "name": "raspberry_pi_pico2", + "uid": "560AE75E1C7152C9", + "flasher": "openocd", + "flasher_sn": "E6633861A3978538", + "flasher_args": "-f interface/cmsis-dap.cfg -f target/rp2350.cfg -c \"adapter speed 5000\"", + "tests": { + "dual_attached": [{"vid_pid": "1a86_55d4", "serial": "533D004242"}] + } + }, { "name": "stm32f072disco", "uid": "3A001A001357364230353532", -- cgit v1.3.1 From 2c27f29f713d80da53f26a8b06173ac4e1f8de05 Mon Sep 17 00:00:00 2001 From: Uwe Bonnes Date: Sat, 14 Sep 2024 20:23:31 +0200 Subject: Add STM32 B_5585I-IOT2A board --- hw/bsp/stm32u5/boards/b_u585i_iot2a/board.cmake | 8 ++ hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h | 112 ++++++++++++++++++++++++ hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk | 11 +++ 3 files changed, 131 insertions(+) create mode 100644 hw/bsp/stm32u5/boards/b_u585i_iot2a/board.cmake create mode 100644 hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h create mode 100644 hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk (limited to 'hw') diff --git a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.cmake b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.cmake new file mode 100644 index 000000000..1cb92d710 --- /dev/null +++ b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.cmake @@ -0,0 +1,8 @@ +set(MCU_VARIANT stm32u585xx) +set(JLINK_DEVICE stm32u585zi) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + STM32U585xx + ) +endfunction() diff --git a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h new file mode 100644 index 000000000..2f1c451db --- /dev/null +++ b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h @@ -0,0 +1,112 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +// LED GREEN +#define LED_PORT GPIOH +#define LED_PIN GPIO_PIN_7 +#define LED_STATE_ON 0 + +// BUTTON +#define BUTTON_PORT GPIOC +#define BUTTON_PIN GPIO_PIN_13 +#define BUTTON_STATE_ACTIVE 1 + +// UART Enable for STLink VCOM +#define UART_DEV USART1 +#define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE +#define UART_GPIO_PORT GPIOA +#define UART_GPIO_AF GPIO_AF7_USART1 +#define UART_TX_PIN GPIO_PIN_9 +#define UART_RX_PIN GPIO_PIN_10 + +//--------------------------------------------------------------------+ +// RCC Clock +//--------------------------------------------------------------------+ + +static void SystemClock_Config(void) { + RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; + RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; + RCC_PeriphCLKInitTypeDef PeriphClkInit = { 0 }; + + /* Enable Power Clock */ + __HAL_RCC_PWR_CLK_ENABLE(); + + /** Configure the main internal regulator output voltage + */ + HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1; + RCC_OscInitStruct.PLL.PLLM = 1; + RCC_OscInitStruct.PLL.PLLN = 10; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 1; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48; + + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = + RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; + + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4); +} + +static void SystemPower_Config(void) { +} + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk new file mode 100644 index 000000000..ae63afef3 --- /dev/null +++ b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.mk @@ -0,0 +1,11 @@ +CFLAGS += \ + -DSTM32U585xx \ + +# All source paths should be relative to the top level. +LD_FILE = ${FAMILY_PATH}/linker/STM32U575xx_FLASH.ld + +SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32u575xx.s + +MCU_VARIANT = stm32u585xx +# For flash-jlink target +JLINK_DEVICE = stm32u585zi -- cgit v1.3.1 From 616532892d913b7224806ed1e881b72ed66bb3e1 Mon Sep 17 00:00:00 2001 From: Shawn Hoffman Date: Tue, 17 Sep 2024 12:17:12 -0700 Subject: make all python files executable and standardize interpreter --- .github/workflows/ci_set_matrix.py | 1 + docs/conf.py | 1 + examples/device/audio_4_channel_mic/src/plot_audio_samples.py | 1 + examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py | 1 + examples/device/audio_test/src/plot_audio_samples.py | 1 + examples/device/audio_test_freertos/src/plot_audio_samples.py | 1 + examples/device/audio_test_multi_rate/src/plot_audio_samples.py | 1 + examples/device/hid_generic_inout/hid_test.py | 1 + examples/device/uac2_speaker_fb/src/audio_debug.py | 1 + examples/device/usbtmc/visaQuery.py | 0 hw/bsp/fomu/dfu.py | 2 +- hw/mcu/sony/cxd56/tools/flash_writer.py | 2 +- hw/mcu/sony/cxd56/tools/xmodem.py | 1 + src/portable/synopsys/dwc2/dwc2_info.py | 1 + test/hil/hil_test.py | 1 + test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py | 2 +- test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py | 1 + tools/build.py | 1 + tools/build_utils.py | 1 + tools/gen_doc.py | 1 + tools/get_deps.py | 1 + tools/iar_gen.py | 2 +- tools/make_release.py | 1 + tools/mksunxi.py | 0 tools/pcapng_to_corpus.py | 2 +- 25 files changed, 23 insertions(+), 5 deletions(-) mode change 100644 => 100755 .github/workflows/ci_set_matrix.py mode change 100644 => 100755 docs/conf.py mode change 100644 => 100755 examples/device/audio_4_channel_mic/src/plot_audio_samples.py mode change 100644 => 100755 examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py mode change 100644 => 100755 examples/device/audio_test/src/plot_audio_samples.py mode change 100644 => 100755 examples/device/audio_test_freertos/src/plot_audio_samples.py mode change 100644 => 100755 examples/device/audio_test_multi_rate/src/plot_audio_samples.py mode change 100644 => 100755 examples/device/hid_generic_inout/hid_test.py mode change 100644 => 100755 examples/device/uac2_speaker_fb/src/audio_debug.py mode change 100644 => 100755 examples/device/usbtmc/visaQuery.py mode change 100644 => 100755 hw/bsp/fomu/dfu.py mode change 100644 => 100755 hw/mcu/sony/cxd56/tools/xmodem.py mode change 100644 => 100755 src/portable/synopsys/dwc2/dwc2_info.py mode change 100644 => 100755 test/hil/hil_test.py mode change 100644 => 100755 test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py mode change 100644 => 100755 test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py mode change 100644 => 100755 tools/build.py mode change 100644 => 100755 tools/build_utils.py mode change 100644 => 100755 tools/gen_doc.py mode change 100644 => 100755 tools/get_deps.py mode change 100644 => 100755 tools/iar_gen.py mode change 100644 => 100755 tools/make_release.py mode change 100644 => 100755 tools/mksunxi.py (limited to 'hw') diff --git a/.github/workflows/ci_set_matrix.py b/.github/workflows/ci_set_matrix.py old mode 100644 new mode 100755 index 4da26bfea..fde6e81d6 --- a/.github/workflows/ci_set_matrix.py +++ b/.github/workflows/ci_set_matrix.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import json # toolchain, url diff --git a/docs/conf.py b/docs/conf.py old mode 100644 new mode 100755 index 878b29645..af44b7339 --- a/docs/conf.py +++ b/docs/conf.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 # Configuration file for the Sphinx documentation builder. # # This file only contains a selection of the most common options. For a full diff --git a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py old mode 100644 new mode 100755 index d17a908b6..4d61e7f5e --- a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py +++ b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import sounddevice as sd import matplotlib.pyplot as plt import numpy as np diff --git a/examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py b/examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py old mode 100644 new mode 100755 index 8312b4e28..4d5ca28d6 --- a/examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py +++ b/examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import sounddevice as sd import matplotlib.pyplot as plt import numpy as np diff --git a/examples/device/audio_test/src/plot_audio_samples.py b/examples/device/audio_test/src/plot_audio_samples.py old mode 100644 new mode 100755 index 1504684a6..ea6aa661e --- a/examples/device/audio_test/src/plot_audio_samples.py +++ b/examples/device/audio_test/src/plot_audio_samples.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import sounddevice as sd import matplotlib.pyplot as plt import numpy as np diff --git a/examples/device/audio_test_freertos/src/plot_audio_samples.py b/examples/device/audio_test_freertos/src/plot_audio_samples.py old mode 100644 new mode 100755 index 304b2d5de..46738eb3f --- a/examples/device/audio_test_freertos/src/plot_audio_samples.py +++ b/examples/device/audio_test_freertos/src/plot_audio_samples.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import sounddevice as sd import matplotlib.pyplot as plt import numpy as np diff --git a/examples/device/audio_test_multi_rate/src/plot_audio_samples.py b/examples/device/audio_test_multi_rate/src/plot_audio_samples.py old mode 100644 new mode 100755 index c92e49957..1f33a003e --- a/examples/device/audio_test_multi_rate/src/plot_audio_samples.py +++ b/examples/device/audio_test_multi_rate/src/plot_audio_samples.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import sounddevice as sd import matplotlib.pyplot as plt import numpy as np diff --git a/examples/device/hid_generic_inout/hid_test.py b/examples/device/hid_generic_inout/hid_test.py old mode 100644 new mode 100755 index 5bdba9db0..3aaca9d2c --- a/examples/device/hid_generic_inout/hid_test.py +++ b/examples/device/hid_generic_inout/hid_test.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 # Install python3 HID package https://pypi.org/project/hid/ import hid diff --git a/examples/device/uac2_speaker_fb/src/audio_debug.py b/examples/device/uac2_speaker_fb/src/audio_debug.py old mode 100644 new mode 100755 index 336c46c01..05b49baf6 --- a/examples/device/uac2_speaker_fb/src/audio_debug.py +++ b/examples/device/uac2_speaker_fb/src/audio_debug.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 # Install python3 HID package https://pypi.org/project/hid/ # Install python3 matplotlib package https://pypi.org/project/matplotlib/ diff --git a/examples/device/usbtmc/visaQuery.py b/examples/device/usbtmc/visaQuery.py old mode 100644 new mode 100755 diff --git a/hw/bsp/fomu/dfu.py b/hw/bsp/fomu/dfu.py old mode 100644 new mode 100755 index 32479350c..8383852e3 --- a/hw/bsp/fomu/dfu.py +++ b/hw/bsp/fomu/dfu.py @@ -1,4 +1,4 @@ -#!/usr/bin/python +#!/usr/bin/env python3 # Written by Antonio Galea - 2010/11/18 # Updated for DFU 1.1 by Sean Cross - 2020/03/31 diff --git a/hw/mcu/sony/cxd56/tools/flash_writer.py b/hw/mcu/sony/cxd56/tools/flash_writer.py index bf630547a..387e679da 100755 --- a/hw/mcu/sony/cxd56/tools/flash_writer.py +++ b/hw/mcu/sony/cxd56/tools/flash_writer.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python3 +#!/usr/bin/env python3 # Copyright (C) 2018 Sony Semiconductor Solutions Corp. # diff --git a/hw/mcu/sony/cxd56/tools/xmodem.py b/hw/mcu/sony/cxd56/tools/xmodem.py old mode 100644 new mode 100755 index 60fcc952c..3ee2698f7 --- a/hw/mcu/sony/cxd56/tools/xmodem.py +++ b/hw/mcu/sony/cxd56/tools/xmodem.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 ''' =============================== XMODEM file transfer protocol diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py old mode 100644 new mode 100755 index 55bec3d23..9bbc18850 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import click import ctypes import pandas as pd diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py old mode 100644 new mode 100755 index a569e7666..b2e17c8e3 --- a/test/hil/hil_test.py +++ b/test/hil/hil_test.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 # # The MIT License (MIT) # diff --git a/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py b/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py old mode 100644 new mode 100755 index 00c0da8cc..a8e5b2726 --- a/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py +++ b/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py @@ -1,4 +1,4 @@ -#! python3 +#!/usr/bin/env python3 # ========================================== # Unity Project - A Test Framework for C # Copyright (c) 2015 Alexander Mueller / XelaRellum@web.de diff --git a/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py b/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py old mode 100644 new mode 100755 index 71dd56888..2379ad49a --- a/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py +++ b/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import sys import os from glob import glob diff --git a/tools/build.py b/tools/build.py old mode 100644 new mode 100755 index f9ae68231..1f3a7e0af --- a/tools/build.py +++ b/tools/build.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import argparse import random import os diff --git a/tools/build_utils.py b/tools/build_utils.py old mode 100644 new mode 100755 index 5f88db8a2..357a95c93 --- a/tools/build_utils.py +++ b/tools/build_utils.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import subprocess import pathlib import time diff --git a/tools/gen_doc.py b/tools/gen_doc.py old mode 100644 new mode 100755 index 668c77ef6..c69f3ff29 --- a/tools/gen_doc.py +++ b/tools/gen_doc.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import pandas as pd from tabulate import tabulate from pathlib import Path diff --git a/tools/get_deps.py b/tools/get_deps.py old mode 100644 new mode 100755 index 06da54b41..84c6a9e61 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import argparse import sys import subprocess diff --git a/tools/iar_gen.py b/tools/iar_gen.py old mode 100644 new mode 100755 index ebcfa1423..8d45659db --- a/tools/iar_gen.py +++ b/tools/iar_gen.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 import os import sys diff --git a/tools/make_release.py b/tools/make_release.py old mode 100644 new mode 100755 index 3e653c12d..92c75baf9 --- a/tools/make_release.py +++ b/tools/make_release.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import re import gen_doc diff --git a/tools/mksunxi.py b/tools/mksunxi.py old mode 100644 new mode 100755 diff --git a/tools/pcapng_to_corpus.py b/tools/pcapng_to_corpus.py index 9c31365eb..3089f0bb6 100755 --- a/tools/pcapng_to_corpus.py +++ b/tools/pcapng_to_corpus.py @@ -1,4 +1,4 @@ -#!/bin/python3 +#!/usr/bin/env python3 import argparse import pcapng import zipfile -- cgit v1.3.1 From 86b4608365e66ba250cf4fb52226b0ed02488cc1 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 24 Sep 2024 17:38:31 +0700 Subject: update dfifo allocation scheme to use top pointer, update document and explanation for EPInfo address and GDFIFO. some function rename update h743 linker to use SRAM1 since USB DMA cannot access DTCM ram update xmc4500 to use uuid for testing --- hw/bsp/stm32h7/linker/stm32h743xx_flash.ld | 35 +-- hw/bsp/xmc4000/family.c | 6 + src/portable/synopsys/dwc2/dcd_dwc2.c | 361 ++++++++++++++--------------- src/portable/synopsys/dwc2/dwc2_type.h | 14 +- 4 files changed, 206 insertions(+), 210 deletions(-) (limited to 'hw') diff --git a/hw/bsp/stm32h7/linker/stm32h743xx_flash.ld b/hw/bsp/stm32h7/linker/stm32h743xx_flash.ld index 336afc01f..ba18c8cd1 100644 --- a/hw/bsp/stm32h7/linker/stm32h743xx_flash.ld +++ b/hw/bsp/stm32h7/linker/stm32h743xx_flash.ld @@ -32,23 +32,24 @@ /* Entry Point */ ENTRY(Reset_Handler) -/* Highest address of the user mode stack */ -_estack = 0x20020000; /* end of RAM */ -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - /* Specify the memory areas */ MEMORY { -DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K -RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K -RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K -RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K -ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K -FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K + DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K + RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K + RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K + ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + } +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1); /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + /* Define output sections */ SECTIONS { @@ -127,7 +128,7 @@ SECTIONS . = ALIGN(4); _edata = .; /* define a global symbol at data end */ - } >DTCMRAM AT> FLASH + } >RAM_D1 AT> FLASH /* Uninitialized data section */ @@ -144,7 +145,9 @@ SECTIONS . = ALIGN(4); _ebss = .; /* define a global symbol at bss end */ __bss_end__ = _ebss; - } >DTCMRAM + } >RAM_D1 + + /* User_heap_stack section, used to check that there is enough RAM left */ ._user_heap_stack : @@ -155,9 +158,7 @@ SECTIONS . = . + _Min_Heap_Size; . = . + _Min_Stack_Size; . = ALIGN(8); - } >DTCMRAM - - + } >RAM_D1 /* Remove information from the standard libraries */ /DISCARD/ : diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c index 88810de7a..c776cb58a 100644 --- a/hw/bsp/xmc4000/family.c +++ b/hw/bsp/xmc4000/family.c @@ -103,6 +103,12 @@ uint32_t board_button_read(void) { return BUTTON_STATE_ACTIVE == XMC_GPIO_GetInput(BUTTON_PIN); } +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + uint8_t const len = tu_min8(16, max_len); + memcpy(id, g_chipid, len); + return len; +} + int board_uart_read(uint8_t* buf, int len) { #ifdef UART_DEV for(int i=0;igrxfsiz -static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs) +static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type +static uint16_t _dfifo_top; // top free location in FIFO RAM // Number of IN endpoints active static uint8_t _allocated_ep_in_count; @@ -92,68 +90,125 @@ static uint8_t _allocated_ep_in_count; // SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by static bool _sof_en; -// Calculate the RX FIFO size according to minimum recommendations from reference manual -// RxFIFO = (5 * number of control endpoints + 8) + -// ((largest USB packet used / 4) + 1 for status information) + -// (2 * number of OUT endpoints) + 1 for Global NAK -// with number of control endpoints = 1 we have -// RxFIFO = 15 + (largest USB packet used / 4) + 2 * number of OUT endpoints -// we double the largest USB packet size to be able to hold up to 2 packets -static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count) { - return 15 + 2 * (max_ep_size / 4) + 2 * ep_count; +//-------------------------------------------------------------------- +// DMA +//-------------------------------------------------------------------- + +TU_ATTR_ALWAYS_INLINE static inline bool dma_enabled(const dwc2_regs_t* dwc2) { + (void) dwc2; + // DMA doesn't support fifo transfer +#ifdef TUD_AUDIO_PREFER_RING_BUFFER +#if TUD_AUDIO_PREFER_RING_BUFFER + return false; +#endif +#endif + // Internal DMA only + return (dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA); + // return false; +} + +TU_ATTR_ALWAYS_INLINE static inline uint16_t dma_cal_epfifo_base(uint8_t rhport) { + // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per endpoint direction + const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport]; + return dwc2_controller->ep_fifo_size/4 - 2*dwc2_controller->ep_count; } -TU_ATTR_ALWAYS_INLINE static inline void fifo_flush_tx(dwc2_regs_t* dwc2, uint8_t epnum) { +static void dma_setup_prepare(uint8_t rhport) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + + if (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a) { + if(dwc2->epout[0].doepctl & DOEPCTL_EPENA) { + return; + } + } + + // Receive only 1 packet + dwc2->epout[0].doeptsiz = (1 << DOEPTSIZ_STUPCNT_Pos) | (1 << DOEPTSIZ_PKTCNT_Pos) | (8 << DOEPTSIZ_XFRSIZ_Pos); + dwc2->epout[0].doepdma = (uintptr_t)_setup_packet; + dwc2->epout[0].doepctl |= DOEPCTL_EPENA | DOEPCTL_USBAEP; +} + +//--------------------------------------------------------------------+ +// Data FIFO +//--------------------------------------------------------------------+ + +TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_tx(dwc2_regs_t* dwc2, uint8_t epnum) { // flush TX fifo and wait for it cleared dwc2->grstctl = GRSTCTL_TXFFLSH | (epnum << GRSTCTL_TXFNUM_Pos); while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {} } -TU_ATTR_ALWAYS_INLINE static inline void fifo_flush_rx(dwc2_regs_t* dwc2) { +TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_rx(dwc2_regs_t* dwc2) { // flush RX fifo and wait for it cleared dwc2->grstctl = GRSTCTL_RXFFLSH; while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {} } -static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { +/* USB Data FIFO Layout + + The FIFO is split up into + - EPInfo: for storing DMA metadata, only required when use DMA. Maximum size is called + EP_LOC_CNT = ep_fifo_size - ghwcfg3.dfifo_depth. For value less than EP_LOC_CNT, gdfifocfg must be configured before + gahbcfg.dmaen is set + - Buffer mode: 1 word per endpoint direction + - Scatter/Gather DMA: 4 words per endpoint direction + - TX FIFO: one fifo for each IN endpoint. Size is dynamic depending on packet size, starting from top with EP0 IN. + - Shared RX FIFO: a shared fifo for all OUT endpoints. Typically, can hold up to 2 packets of the largest EP size. + + We allocated TX FIFO from top to bottom (using top pointer), this to allow the RX FIFO to grow dynamically which is + possible since the free space is located between the RX and TX FIFOs. + + ---------------- ep_fifo_size + | EPInfo | + | for DMA | + |-------------|-- gdfifocfg.EPINFOBASE (max is ghwcfg3.dfifo_depth) + | IN FIFO 0 | + | control | + |-------------| + | IN FIFO 1 | + |-------------| + | . . . . | + |-------------| + | IN FIFO n | + |-------------| + | FREE | + |-------------|-- GRXFSIZ (expandable) + | OUT FIFO | + | ( Shared ) | + --------------- 0 + + According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits): + - Each EP IN needs at least max packet size + - All EP OUT shared a unique OUT FIFO which uses (for Slave or Buffer DMA, Scatt/Gather DMA use different formula): + - 13 for setup packets + control words (up to 3 setup packets). + - 1 for global NAK (not required/used here). + - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4) + 1" + - 2 for each used OUT endpoint + + Therefore GRXFSIZ = 13 + 1 + 2 x (Largest-EPsize/4 + 1) + 2 x EPOUTnum +*/ + +TU_ATTR_ALWAYS_INLINE static inline uint16_t calc_grxfsiz(uint16_t largest_ep_size, uint8_t ep_count) { + return 13 + 1 + 2 * ((largest_ep_size / 4) + 1) + 2 * ep_count; +} + +static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint8_t const ep_count = _dwc2_controller[rhport].ep_count; + const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport]; + uint8_t const ep_count = dwc2_controller->ep_count; uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); TU_ASSERT(epnum < ep_count); uint16_t fifo_size = tu_div_ceil(packet_size, 4); - - // "USB Data FIFOs" section in reference manual - // Peripheral FIFO architecture - // - // --------------- 320 or 1024 ( 1280 or 4096 bytes ) - // | IN FIFO 0 | - // --------------- (320 or 1024) - 16 - // | IN FIFO 1 | - // --------------- (320 or 1024) - 16 - x - // | . . . . | - // --------------- (320 or 1024) - 16 - x - y - ... - z - // | IN FIFO MAX | - // --------------- - // | FREE | - // --------------- GRXFSIZ - // | OUT FIFO | - // | ( Shared ) | - // --------------- 0 - // - // In FIFO is allocated by following rules: - // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". if (dir == TUSB_DIR_OUT) { // Calculate required size of RX FIFO - uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count); + uint16_t const new_sz = calc_grxfsiz(4 * fifo_size, ep_count); - // If size_rx needs to be extended check if possible and if so enlarge it - if (dwc2->grxfsiz < sz) { - TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size / 4); - - // Enlarge RX FIFO - dwc2->grxfsiz = sz; + // If size_rx needs to be extended check if there is enough free space + if (dwc2->grxfsiz < new_sz) { + TU_ASSERT(new_sz <= _dfifo_top); + dwc2->grxfsiz = new_sz; // Enlarge RX FIFO } } else { // Check IN endpoints concurrently active limit @@ -162,59 +217,48 @@ static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { _allocated_ep_in_count++; } - // Note if The TXFELVL is configured as half empty. In order - // to be able to write a packet at that point, the fifo must be twice the max_size. + // If The TXFELVL is configured as half empty, the fifo must be twice the max_size. if ((dwc2->gahbcfg & GAHBCFG_TXFELVL) == 0) { fifo_size *= 2; } // Check if free space is available - TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4); - _allocated_fifo_words_tx += fifo_size; - TU_LOG(DWC2_DEBUG, " Allocated %u bytes at offset %" PRIu32, fifo_size * 4, - _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4); + TU_ASSERT(_dfifo_top >= fifo_size + dwc2->grxfsiz); + _dfifo_top -= fifo_size; + TU_LOG(DWC2_DEBUG, " TX FIFO %u: allocated %u words at offset %u\r\n", epnum, fifo_size, _dfifo_top); - // DIEPTXF starts at FIFO #1. // Both TXFD and TXSA are in unit of 32-bit words. - dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | - (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx); + if (epnum == 0) { + dwc2->dieptxf0 = (fifo_size << DIEPTXF0_TX0FD_Pos) | _dfifo_top; + } else { + // DIEPTXF starts at FIFO #1. + dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | _dfifo_top; + } } return true; } -static inline bool dma_enabled(uint8_t rhport) -{ - // DMA doesn't support fifo transfer -#ifdef TUD_AUDIO_PREFER_RING_BUFFER -#if TUD_AUDIO_PREFER_RING_BUFFER - return false; -#endif -#endif - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - // Internal DMA only - return (dwc2->ghwcfg2_bm.arch == 2); -} - -static void dma_stpkt_rx(uint8_t rhport) -{ +static void dfifo_init(uint8_t rhport) { + const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport]; dwc2_regs_t* dwc2 = DWC2_REG(rhport); + dwc2->grxfsiz = calc_grxfsiz(CFG_TUD_ENDPOINT0_SIZE, dwc2_controller->ep_count); - if (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a) { - if(dwc2->epout[0].doepctl & DOEPCTL_EPENA) - return; + if(dma_enabled(dwc2)) { + // DMA use last DFIFO to store metadata + _dfifo_top = dma_cal_epfifo_base(rhport); + }else { + _dfifo_top = dwc2_controller->ep_fifo_size / 4; } - // Receive only 1 packet - dwc2->epout[0].doeptsiz = 0; - dwc2->epout[0].doeptsiz |= (1 << DOEPTSIZ_STUPCNT_Pos); - dwc2->epout[0].doeptsiz |= 8; - dwc2->epout[0].doeptsiz |= (1 << DOEPTSIZ_PKTCNT_Pos); - dwc2->epout[0].doepdma = (uintptr_t)_setup_packet; - - dwc2->epout[0].doepctl |= DOEPCTL_EPENA | DOEPCTL_USBAEP; + // Allocate FIFO for EP0 IN + dfifo_alloc(rhport, 0x80, CFG_TUD_ENDPOINT0_SIZE); } +//-------------------------------------------------------------------- +// Endpoint +//-------------------------------------------------------------------- + static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); @@ -235,7 +279,7 @@ static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoin dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum); } else { dwc2->epin[epnum].diepctl = dxepctl | (epnum << DIEPCTL_TXFNUM_Pos); - dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum)); + dwc2->daintmsk |= TU_BIT(DAINTMSK_IEPM_Pos + epnum); } } @@ -265,7 +309,7 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { } // Flush the FIFO, and wait until we have confirmed it cleared. - fifo_flush_tx(dwc2, epnum); + dfifo_flush_tx(dwc2, epnum); } else { dwc2_epout_t* epout = dwc2->epout; @@ -318,88 +362,27 @@ static void bus_reset(uint8_t rhport) { } } - fifo_flush_tx(dwc2, 0x10); // all tx fifo - fifo_flush_rx(dwc2); + dfifo_flush_tx(dwc2, 0x10); // all tx fifo + dfifo_flush_rx(dwc2); // 3. Set up interrupt mask dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos); dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM; dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM; - // "USB Data FIFOs" section in reference manual - // Peripheral FIFO architecture - // - // The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start. - // We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located - // between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard - // configuration done below. - // - // Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed. - // All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a - // configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually - // opened when the host sends an additional command: setInterface. At this point in time - // the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size - // an additional memory - // - // --------------- 320 or 1024 ( 1280 or 4096 bytes ) - // | IN FIFO 0 | - // --------------- (320 or 1024) - 16 - // | IN FIFO 1 | - // --------------- (320 or 1024) - 16 - x - // | . . . . | - // --------------- (320 or 1024) - 16 - x - y - ... - z - // | IN FIFO MAX | - // --------------- - // | FREE | - // --------------- GRXFSIZ - // | OUT FIFO | - // | ( Shared ) | - // --------------- 0 - // - // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits): - // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN - // - // - All EP OUT shared a unique OUT FIFO which uses - // - 13 for setup packets + control words (up to 3 setup packets). - // - 1 for global NAK (not required/used here). - // - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4) + 1" - // - 2 for each used OUT endpoint - // - // Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum - // - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x 16 + 2 x ep_count = 47 + 2 x ep_count - // - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x ep_count = 271 + 2 x ep_count - // - // NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge - // of the overall picture yet. We will use the worst scenario: largest possible + ep_count - // - // For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO - // are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to - // overwrite this. - - // EP0 out max is 64 - dwc2->grxfsiz = calc_grxfsiz(64, ep_count); - - // Setup the control endpoint 0 - _allocated_fifo_words_tx = 16; - - // DMA needs extra space for processing - if(dma_enabled(rhport)) { - uint16_t reserved = _dwc2_controller[rhport].ep_fifo_size / 4- dwc2->ghwcfg3_bm.total_fifo_size; - _allocated_fifo_words_tx += reserved; - } - - // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) - dwc2->dieptxf0 = (16 << DIEPTXF0_TX0FD_Pos) | (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx); + dfifo_init(rhport); // Fixed control EP0 size to 64 bytes dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos); + dwc2->epout[0].doepctl &= ~(0x03 << DOEPCTL_MPSIZ_Pos); + xfer_status[0][TUSB_DIR_OUT].max_size = 64; xfer_status[0][TUSB_DIR_IN].max_size = 64; - dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); - - if(dma_enabled(rhport)) { - dma_stpkt_rx(rhport); + if(dma_enabled(dwc2)) { + dma_setup_prepare(rhport); + } else { + dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); } dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT; @@ -427,7 +410,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); - if(dma_enabled(rhport)) { + if(dma_enabled(dwc2)) { epin[epnum].diepdma = (uintptr_t)xfer->buffer; // For ISO endpoint set correct odd/even bit for next frame. @@ -468,7 +451,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); } - if(dma_enabled(rhport)) { + if(dma_enabled(dwc2)) { epout[epnum].doepdma = (uintptr_t)xfer->buffer; } @@ -599,7 +582,9 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347) - if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) dcfg |= DCFG_XCVRDLY; + if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) { + dcfg |= DCFG_XCVRDLY; + } dwc2->dcfg = dcfg; } @@ -625,12 +610,9 @@ void dcd_init(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Check Synopsys ID register, failed if controller clock/power is not enabled - if (!check_dwc2(dwc2)) return; + TU_ASSERT(check_dwc2(dwc2), ); dcd_disconnect(rhport); - // max number of endpoints & total_fifo_size are: - // hw_cfg2->num_dev_ep, hw_cfg2->total_fifo_size - if (phy_hs_supported(dwc2)) { phy_hs_init(dwc2); // Highspeed } else { @@ -660,8 +642,8 @@ void dcd_init(uint8_t rhport) { // (non zero-length packet), send STALL back and discard. dwc2->dcfg |= DCFG_NZLSOHSK; - fifo_flush_tx(dwc2, 0x10); // all tx fifo - fifo_flush_rx(dwc2); + dfifo_flush_tx(dwc2, 0x10); // all tx fifo + dfifo_flush_rx(dwc2); // Clear all interrupts uint32_t int_mask = dwc2->gintsts; @@ -670,20 +652,24 @@ void dcd_init(uint8_t rhport) { dwc2->gotgint |= int_mask; // Required as part of core initialization. - dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_RXFLVLM | - GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM; + dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM; // Configure TX FIFO empty level for interrupt. Default is complete empty dwc2->gahbcfg |= GAHBCFG_TXFELVL; - // Enable global interrupt - dwc2->gahbcfg |= GAHBCFG_GINT; + if (dma_enabled(dwc2)) { + const uint16_t epinfo_base = dma_cal_epfifo_base(rhport); + dwc2->gdfifocfg = (epinfo_base << GDFIFOCFG_EPINFOBASE_SHIFT) | epinfo_base; - if (dma_enabled(rhport)) { + // DMA seems to be only settable after a core reset dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2; - dwc2->gintmsk &=~GINTMSK_RXFLVLM; + }else { + dwc2->gintmsk |= GINTMSK_RXFLVLM; } + // Enable global interrupt + dwc2->gahbcfg |= GAHBCFG_GINT; + // make sure we are in device mode // TU_ASSERT(!(dwc2->gintsts & GINTSTS_CMOD), ); @@ -783,7 +769,7 @@ void dcd_sof_enable(uint8_t rhport, bool en) { *------------------------------------------------------------------*/ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) { - TU_ASSERT(fifo_alloc(rhport, desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt))); + TU_ASSERT(dfifo_alloc(rhport, desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt))); edpt_activate(rhport, desc_edpt); return true; } @@ -812,32 +798,21 @@ void dcd_edpt_close_all(uint8_t rhport) { xfer_status[n][TUSB_DIR_IN].max_size = 0; } - // reset allocated fifo OUT - dwc2->grxfsiz = calc_grxfsiz(64, ep_count); - // reset allocated fifo IN - _allocated_fifo_words_tx = 16; - - fifo_flush_tx(dwc2, 0x10); // all tx fifo - fifo_flush_rx(dwc2); + dfifo_flush_tx(dwc2, 0x10); // all tx fifo + dfifo_flush_rx(dwc2); - // DMA needs extra space for processing - if(dma_enabled(rhport)) { - uint16_t reserved = _dwc2_controller[rhport].ep_fifo_size / 4- dwc2->ghwcfg3_bm.total_fifo_size; - _allocated_fifo_words_tx += reserved; - } + dfifo_init(rhport); // re-init dfifo } bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { - TU_ASSERT(fifo_alloc(rhport, ep_addr, largest_packet_size)); + TU_ASSERT(dfifo_alloc(rhport, ep_addr, largest_packet_size)); return true; } bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { // Disable EP to clear potential incomplete transfers edpt_disable(rhport, p_endpoint_desc->bEndpointAddress, false); - edpt_activate(rhport, p_endpoint_desc); - return true; } @@ -904,8 +879,8 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { edpt_disable(rhport, ep_addr, true); - if((tu_edpt_number(ep_addr) == 0) && dma_enabled(rhport)) { - dma_stpkt_rx(rhport); + if((tu_edpt_number(ep_addr) == 0) && dma_enabled(DWC2_REG(rhport))) { + dma_setup_prepare(rhport); } } @@ -1075,13 +1050,15 @@ static void handle_epout_irq(uint8_t rhport) { uint32_t const doepint = epout->doepint; + TU_ASSERT((epout->doepint & DOEPINT_AHBERR) == 0, ); + // OUT XFER complete if (epout->doepint & DOEPINT_XFRC) { epout->doepint = DOEPINT_XFRC; xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); - if(dma_enabled(rhport)) { + if(dma_enabled(dwc2)) { if (doepint & DOEPINT_STUP) { // STPKTRX is only available for version from 3_00a if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { @@ -1103,7 +1080,7 @@ static void handle_epout_irq(uint8_t rhport) { xfer->total_len -= remain; // this is ZLP, so prepare EP0 for next setup if(n == 0 && xfer->total_len == 0) { - dma_stpkt_rx(rhport); + dma_setup_prepare(rhport); } dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); @@ -1135,8 +1112,8 @@ static void handle_epout_irq(uint8_t rhport) { if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { epout->doepint = DOEPINT_STPKTRX; } - if(dma_enabled(rhport) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { - dma_stpkt_rx(rhport); + if(dma_enabled(dwc2) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { + dma_setup_prepare(rhport); } dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); @@ -1165,8 +1142,8 @@ static void handle_epin_irq(uint8_t rhport) { // Schedule another packet to be transmitted. edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); } else { - if((n == 0) && dma_enabled(rhport)) { - dma_stpkt_rx(rhport); + if((n == 0) && dma_enabled(dwc2)) { + dma_setup_prepare(rhport); } dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); } diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 244323b51..c21bf9e94 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -100,6 +100,12 @@ enum { FS_PHY_TYPE_ULPI, }; +enum { + GHWCFG2_ARCH_SLAVE_ONLY = 0, + GHWCFG2_ARCH_EXTERNAL_DMA, // 1 + GHWCFG2_ARCH_INTERNAL_DMA, // 2 +}; + typedef struct TU_ATTR_PACKED { uint32_t op_mode : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP @@ -134,7 +140,7 @@ typedef struct TU_ATTR_PACKED uint32_t otg_enable_hsic : 1; // 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC uint32_t battery_charger_support : 1; // support battery charger uint32_t lpm_mode : 1; // LPC mode - uint32_t total_fifo_size : 16; // DFIFO depth value in terms of 32-bit words + uint32_t dfifo_depth : 16; // DFIFO depth - EP_LOC_CNT in terms of 32-bit words }dwc2_ghwcfg3_t; TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size"); @@ -1240,6 +1246,12 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GLPMCFG_ENBESL_Msk (0x1UL << GLPMCFG_ENBESL_Pos) // 0x10000000 #define GLPMCFG_ENBESL GLPMCFG_ENBESL_Msk // Enable best effort service latency +// GDFIFOCFG +#define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16) +#define GDFIFOCFG_EPINFOBASE_SHIFT 16 +#define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0) +#define GDFIFOCFG_GDFIFOCFG_SHIFT 0 + /******************** Bit definition for DIEPEACHMSK1 register ********************/ #define DIEPEACHMSK1_XFRCM_Pos (0U) #define DIEPEACHMSK1_XFRCM_Msk (0x1UL << DIEPEACHMSK1_XFRCM_Pos) // 0x00000001 -- cgit v1.3.1 From 7e472fa3cacdd97e0329faa4dbc53a6d457a77f2 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 25 Sep 2024 17:18:41 +0700 Subject: try to add esp32 p4 and esp-idf v5.3 support --- hw/bsp/espressif/boards/CMakeLists.txt | 2 +- hw/bsp/espressif/boards/family.c | 135 +++++++++++++++++++++------------ src/common/tusb_mcu.h | 6 ++ src/tusb_option.h | 1 + 4 files changed, 93 insertions(+), 51 deletions(-) (limited to 'hw') diff --git a/hw/bsp/espressif/boards/CMakeLists.txt b/hw/bsp/espressif/boards/CMakeLists.txt index 8209e8747..fe1273d4c 100644 --- a/hw/bsp/espressif/boards/CMakeLists.txt +++ b/hw/bsp/espressif/boards/CMakeLists.txt @@ -2,7 +2,7 @@ set(hw_dir "${CMAKE_CURRENT_LIST_DIR}/../../../") idf_component_register(SRCS family.c INCLUDE_DIRS "." ${BOARD} ${hw_dir} - PRIV_REQUIRES "driver" + PRIV_REQUIRES driver usb REQUIRES led_strip src tinyusb_src) target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format) diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index 02e478a0c..a1b4334b2 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -31,20 +31,9 @@ #include "esp_mac.h" #include "hal/gpio_ll.h" -#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) -#include "hal/usb_hal.h" -#include "soc/usb_periph.h" -static void configure_pins(usb_hal_context_t* usb); -#endif - #include "driver/gpio.h" #include "driver/uart.h" - -#if ESP_IDF_VERSION_MAJOR > 4 - #include "esp_private/periph_ctrl.h" -#else - #include "driver/periph_ctrl.h" -#endif +#include "esp_private/periph_ctrl.h" // Note; current code use UART0 can cause device to reset while monitoring #define USE_UART 0 @@ -60,6 +49,7 @@ static led_strip_handle_t led_strip; static void max3421_init(void); #endif +static bool usb_init(void); //--------------------------------------------------------------------+ // Implementation @@ -111,16 +101,8 @@ void board_init(void) { gpio_set_direction(BUTTON_PIN, GPIO_MODE_INPUT); gpio_set_pull_mode(BUTTON_PIN, BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN_ONLY : GPIO_PULLUP_ONLY); -#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) - // USB Controller Hal init - periph_module_reset(PERIPH_USB_MODULE); - periph_module_enable(PERIPH_USB_MODULE); - - usb_hal_context_t hal = { - .use_external_phy = false // use built-in PHY - }; - usb_hal_init(&hal); - configure_pins(&hal); +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32P4) + usb_init(); #endif #if CFG_TUH_ENABLED && CFG_TUH_MAX3421 @@ -129,35 +111,7 @@ void board_init(void) { } #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) -static void configure_pins(usb_hal_context_t* usb) { - /* usb_periph_iopins currently configures USB_OTG as USB Device. - * Introduce additional parameters in usb_hal_context_t when adding support - * for USB Host. */ - for (const usb_iopin_dsc_t* iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) { - if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) { - esp_rom_gpio_pad_select_gpio(iopin->pin); - if (iopin->is_output) { - esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false); - } else { - esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false); -#if ESP_IDF_VERSION_MAJOR > 4 - if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT)) -#else - if ((iopin->pin != GPIO_FUNC_IN_LOW) && (iopin->pin != GPIO_FUNC_IN_HIGH)) -#endif - { - gpio_ll_input_enable(&GPIO, iopin->pin); - } - } - esp_rom_gpio_pad_unhold(iopin->pin); - } - } - if (!usb->use_external_phy) { - gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3); - gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3); - } -} #endif //--------------------------------------------------------------------+ @@ -204,6 +158,87 @@ int board_getchar(void) { return board_uart_read(&c, 1) > 0 ? (int) c : (-1); } +//-------------------------------------------------------------------- +// PHY Init +//-------------------------------------------------------------------- + +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3, OPT_MCU_ESP32P4) +#if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 3, 0) + +#include "esp_private/usb_phy.h" +#include "soc/usb_pins.h" + +static usb_phy_handle_t phy_hdl; + +bool usb_init(void) { + // Configure USB PHY + usb_phy_config_t phy_conf = { + .controller = USB_PHY_CTRL_OTG, + .target = USB_PHY_TARGET_INT, + .otg_mode = USB_OTG_MODE_DEVICE, + }; + + // OTG IOs config + // const usb_phy_otg_io_conf_t otg_io_conf = USB_PHY_SELF_POWERED_DEVICE(config->vbus_monitor_io); + // if (config->self_powered) { + // phy_conf.otg_io_conf = &otg_io_conf; + // } + // ESP_RETURN_ON_ERROR(usb_new_phy(&phy_conf, &phy_hdl), TAG, "Install USB PHY failed"); + + usb_new_phy(&phy_conf, &phy_hdl); + + return true; +} + +#else + +#include "esp_private/usb_phy.h" +#include "hal/usb_hal.h" +#include "soc/usb_periph.h" + +static void configure_pins(usb_hal_context_t* usb) { + /* usb_periph_iopins currently configures USB_OTG as USB Device. + * Introduce additional parameters in usb_hal_context_t when adding support + * for USB Host. */ + for (const usb_iopin_dsc_t* iopin = usb_periph_iopins; iopin->pin != -1; ++iopin) { + if ((usb->use_external_phy) || (iopin->ext_phy_only == 0)) { + esp_rom_gpio_pad_select_gpio(iopin->pin); + if (iopin->is_output) { + esp_rom_gpio_connect_out_signal(iopin->pin, iopin->func, false, false); + } else { + esp_rom_gpio_connect_in_signal(iopin->pin, iopin->func, false); + if ((iopin->pin != GPIO_MATRIX_CONST_ZERO_INPUT) && (iopin->pin != GPIO_MATRIX_CONST_ONE_INPUT)) { + gpio_ll_input_enable(&GPIO, iopin->pin); + } + } + esp_rom_gpio_pad_unhold(iopin->pin); + } + } + + if (!usb->use_external_phy) { + gpio_set_drive_capability(USBPHY_DM_NUM, GPIO_DRIVE_CAP_3); + gpio_set_drive_capability(USBPHY_DP_NUM, GPIO_DRIVE_CAP_3); + } +} + +bool usb_init(void) { + // USB Controller Hal init + periph_module_reset(PERIPH_USB_MODULE); + periph_module_enable(PERIPH_USB_MODULE); + + usb_hal_context_t hal = { + .use_external_phy = false // use built-in PHY + }; + + usb_hal_init(&hal); + configure_pins(&hal); + + return true; +} + +#endif +#endif + //--------------------------------------------------------------------+ // API: SPI transfer with MAX3421E, must be implemented by application //--------------------------------------------------------------------+ diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 6ead1ea0b..26a8ee26b 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -339,6 +339,12 @@ #define TUP_USBIP_DWC2_ESP32 #define TUP_DCD_ENDPOINT_MAX 6 +#elif TU_CHECK_MCU(OPT_MCU_ESP32P4) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_ESP32 + #define TUP_RHPORT_HIGHSPEED 1 // 1 port FS, 1 port HS + #define TUP_DCD_ENDPOINT_MAX 8 // FS 6 ep, HS 8 ep + #elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2) #if (CFG_TUD_ENABLED || !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)) #error "MCUs are only supported with CFG_TUH_MAX3421 enabled" diff --git a/src/tusb_option.h b/src/tusb_option.h index 17de9cd72..79f49636f 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -123,6 +123,7 @@ #define OPT_MCU_ESP32C6 904 ///< Espressif ESP32-C6 #define OPT_MCU_ESP32C2 905 ///< Espressif ESP32-C2 #define OPT_MCU_ESP32H2 906 ///< Espressif ESP32-H2 +#define OPT_MCU_ESP32P4 907 ///< Espressif ESP32-P4 #define TUP_MCU_ESPRESSIF (CFG_TUSB_MCU >= 900 && CFG_TUSB_MCU < 1000) // check if Espressif MCU // Dialog -- cgit v1.3.1 From 67e5577b428e70878d99c4f83039cef020a272cb Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 25 Sep 2024 20:36:16 +0700 Subject: added p4, seems to work well and enumerated --- .idea/cmake.xml | 9 +- .../boards/espressif_p4_function_ev/board.cmake | 2 + .../boards/espressif_p4_function_ev/board.h | 43 ++++++++ hw/bsp/espressif/family.cmake | 3 + src/common/tusb_mcu.h | 6 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 23 ++-- src/portable/synopsys/dwc2/dwc2_esp32.h | 48 +++++++-- src/portable/synopsys/dwc2/dwc2_info.md | 116 ++++++++++----------- src/portable/synopsys/dwc2/dwc2_info.py | 1 + 9 files changed, 164 insertions(+), 87 deletions(-) create mode 100644 hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake create mode 100644 hw/bsp/espressif/boards/espressif_p4_function_ev/board.h (limited to 'hw') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 96ff19c89..b6a237a1d 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -37,7 +37,7 @@ - + @@ -145,6 +145,13 @@ + + + + + + + \ No newline at end of file diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake new file mode 100644 index 000000000..fe4db4fc1 --- /dev/null +++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake @@ -0,0 +1,2 @@ +# Apply board specific content here +set(IDF_TARGET "esp32p4") diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h new file mode 100644 index 000000000..9c8aa409f --- /dev/null +++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h @@ -0,0 +1,43 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// #define NEOPIXEL_PIN 48 + +#define BUTTON_PIN 0 +#define BUTTON_STATE_ACTIVE 0 + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake index eb97401c3..b0786f1cc 100644 --- a/hw/bsp/espressif/family.cmake +++ b/hw/bsp/espressif/family.cmake @@ -8,4 +8,7 @@ string(TOUPPER ${IDF_TARGET} FAMILY_MCUS) # Add example src and bsp directories set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components") +# set SDKCONFIG for each IDF Target +set(SDKCONFIG ${CMAKE_SOURCE_DIR}/sdkconfig.${IDF_TARGET}) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 26a8ee26b..6b19ac9fe 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -337,13 +337,13 @@ #elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) #define TUP_USBIP_DWC2 #define TUP_USBIP_DWC2_ESP32 - #define TUP_DCD_ENDPOINT_MAX 6 + #define TUP_DCD_ENDPOINT_MAX 7 // only 5 TX FIFO for endpoint IN #elif TU_CHECK_MCU(OPT_MCU_ESP32P4) #define TUP_USBIP_DWC2 #define TUP_USBIP_DWC2_ESP32 - #define TUP_RHPORT_HIGHSPEED 1 // 1 port FS, 1 port HS - #define TUP_DCD_ENDPOINT_MAX 8 // FS 6 ep, HS 8 ep + #define TUP_RHPORT_HIGHSPEED 1 // port0 FS, port1 HS + #define TUP_DCD_ENDPOINT_MAX 16 // FS 7 ep, HS 16 ep #elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2) #if (CFG_TUD_ENABLED || !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 13143073d..d1eb22ed7 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -508,18 +508,6 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ -#if CFG_TUSB_DEBUG >= DWC2_DEBUG -void print_dwc2_info(dwc2_regs_t* dwc2) { - // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4 - // use dwc2_info.py/md for bit-field value and comparison with other ports - volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid; - TU_LOG(DWC2_DEBUG, "guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n"); - for (size_t i = 0; i < 5; i++) { - TU_LOG(DWC2_DEBUG, "0x%08" PRIX32 ", ", p[i]); - } - TU_LOG(DWC2_DEBUG, "0x%08" PRIX32 "\r\n", p[5]); -} -#endif static void reset_core(dwc2_regs_t* dwc2) { // reset core @@ -633,8 +621,15 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { } static bool check_dwc2(dwc2_regs_t* dwc2) { -#if CFG_TUSB_DEBUG >= DWC2_DEBUG - print_dwc2_info(dwc2); +#if CFG_TUSB_DEBUG >= DWC2_DEBUG || 1 + // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4 + // Run 'dwc2_info.py render-md' and check dwc2_info.md for bit-field value and comparison with other ports + volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid; + TU_LOG1("guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n"); + for (size_t i = 0; i < 5; i++) { + TU_LOG1("0x%08" PRIX32 ", ", p[i]); + } + TU_LOG1("0x%08" PRIX32 "\r\n", p[5]); #endif // For some reason: GD32VF103 snpsid and all hwcfg register are always zero (skip it) diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index 921cee29e..af04347d1 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -38,29 +38,55 @@ #include "soc/periph_defs.h" #include "soc/usb_wrap_struct.h" -#define DWC2_REG_BASE 0x60080000UL -#define DWC2_EP_MAX 7 -#define DWC2_EP_IN_MAX 5 +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) +#define DWC2_PERIPH_COUNT 1 +#define DWC2_FS_REG_BASE 0x60080000UL +#define DWC2_EP_MAX 7 static const dwc2_controller_t _dwc2_controller[] = { - { .reg_base = DWC2_REG_BASE, .irqnum = 0, .ep_count = DWC2_EP_MAX, .ep_in_count = DWC2_EP_IN_MAX, .ep_fifo_size = 1024 } + { .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 } }; -static intr_handle_t usb_ih; +#elif TU_CHECK_MCU(OPT_MCU_ESP32P4) + +#define DWC2_PERIPH_COUNT 2 +#define DWC2_FS_REG_BASE 0x50040000UL +#define DWC2_HS_REG_BASE 0x50000000UL +#define DWC2_EP_MAX 16 + +// On ESP32 for consistency we associate +// - Port0 to OTG_FS, and Port1 to OTG_HS +static const dwc2_controller_t _dwc2_controller[] = { + { + .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, + .ep_fifo_size = 4096 + }, +{ + .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, + .ep_fifo_size = 1024 +} + +}; +#endif + +enum { + DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller) +}; + +static intr_handle_t usb_ih[DWC2_CONTROLLER_COUNT]; static void dcd_int_handler_wrap(void* arg) { - (void)arg; - dcd_int_handler(0); + const uint8_t rhport = (uint8_t) arg; + dcd_int_handler(rhport); } TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { - (void)rhport; - esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, dcd_int_handler_wrap, NULL, &usb_ih); + esp_intr_alloc(_dwc2_controller[rhport].irqnum, ESP_INTR_FLAG_LOWMED, + dcd_int_handler_wrap, (void*) rhport, &usb_ih[rhport]); } TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) { - (void)rhport; - esp_intr_free(usb_ih); + esp_intr_free(usb_ih[rhport]); } TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index 9798fb0de..462b5856a 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -1,58 +1,58 @@ -| | BCM2711 (Pi4) | EFM32GG FS | ESP32-S2/S3 | STM32F 407/411/429 FS | STM32F 407/429 HS | STM32F 412/767 FS | STM32F723 FS | STM32F723 HS | STM32H743 HS | STM32L476 FS | STM32U5A5 HS | GD32VF103 FS | XMC4500 | -|:---------------------------|:----------------|:-------------|:--------------|:------------------------|:--------------------|:--------------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:-----------| -| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | -| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | -| - specs version | 2.80a | 3.30a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | -| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | -| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | -| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | -| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 2 | 2 | 0 | 2 | 0 | 2 | -| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | -| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 3 | 2 | 0 | 1 | 0 | 0 | -| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 5 | 5 | 8 | 8 | 5 | 8 | 0 | 6 | -| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 11 | 11 | 15 | 15 | 11 | 15 | 0 | 13 | -| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nptx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - ptx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | -| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | -| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | -| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | -| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | -| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | -| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | -| - dfifo_depth | 4080 | 498 | 200 | 512 | 1012 | 512 | 512 | 1006 | 952 | 512 | 952 | 0 | 634 | -| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | -| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - enhanced_lpm_support | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 2 | -| - ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - num_dev_in_eps | 7 | 6 | 4 | 3 | 5 | 5 | 5 | 8 | 8 | 5 | 8 | 0 | 6 | -| - dma_desc_enable | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | -| - dma_desc_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | +| | BCM2711 (Pi4) | EFM32GG FS | ESP32-S2/S3 | ESP32-P4 | STM32F 407/411/429 FS | STM32F 407/429 HS | STM32F 412/767 FS | STM32F723 FS | STM32F723 HS | STM32H743 HS | STM32L476 FS | STM32U5A5 HS | GD32VF103 FS | XMC4500 | +|:---------------------------|:----------------|:-------------|:--------------|:-----------|:------------------------|:--------------------|:--------------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:-----------| +| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | +| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | +| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | +| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | +| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| - arch | 2 | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 2 | 2 | 0 | 2 | 0 | 2 | +| - point2point | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | +| - hs_phy_type | 1 | 0 | 0 | 3 | 0 | 2 | 0 | 0 | 3 | 2 | 0 | 1 | 0 | 0 | +| - fs_phy_type | 1 | 1 | 1 | 3 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 5 | 8 | 0 | 6 | +| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 11 | 15 | 0 | 13 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nptx_q_depth | 2 | 2 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - ptx_q_depth | 2 | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | +| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | +| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | +| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | +| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 952 | 512 | 952 | 0 | 634 | +| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | +| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - phy_data_width | 0 | 2 | 2 | 2 | 2 | 0 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 2 | +| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 5 | 8 | 0 | 6 | +| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | +| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 871ac112d..e382ba011 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -9,6 +9,7 @@ dwc2_reg_value = { 'BCM2711 (Pi4)': [0x2708A000, 0x4F54280A, 0, 0x228DDD50, 0xFF000E8, 0x1FF00020], 'EFM32GG FS': [0, 0x4F54330A, 0, 0x228F5910, 0x1F204E8, 0x1BF08030], 'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0xC804B5, 0xD3F0A030], + 'ESP32-P4': [0, 0x4F54400A, 0, 0x215FFFD0, 0x03805EB5, 0xDFF1A030], 'STM32F 407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030], 'STM32F 407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030], 'STM32F 412/767 FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], -- cgit v1.3.1 From 87f199330405f0a51f8ad4b3b8b2d69c9a21ac3e Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Sep 2024 15:32:47 +0700 Subject: esp32p4 use port0 as fs, port1 as highspeed --- .idea/cmake.xml | 16 +++++----- hw/bsp/espressif/boards/CMakeLists.txt | 2 -- .../components/tinyusb_src/CMakeLists.txt | 3 ++ hw/bsp/espressif/family.cmake | 10 +++++- src/portable/synopsys/dwc2/dcd_dwc2.c | 30 +++++++++++++----- src/portable/synopsys/dwc2/dwc2_esp32.h | 36 ++++++---------------- 6 files changed, 52 insertions(+), 45 deletions(-) (limited to 'hw') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index b6a237a1d..37cd73c65 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -37,7 +37,7 @@ - + @@ -65,6 +65,13 @@ + + + + + + + @@ -145,13 +152,6 @@ - - - - - - - \ No newline at end of file diff --git a/hw/bsp/espressif/boards/CMakeLists.txt b/hw/bsp/espressif/boards/CMakeLists.txt index fe1273d4c..434f77704 100644 --- a/hw/bsp/espressif/boards/CMakeLists.txt +++ b/hw/bsp/espressif/boards/CMakeLists.txt @@ -4,5 +4,3 @@ idf_component_register(SRCS family.c INCLUDE_DIRS "." ${BOARD} ${hw_dir} PRIV_REQUIRES driver usb REQUIRES led_strip src tinyusb_src) - -target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format) diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt index 8bdb3802e..26c7e4030 100644 --- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt +++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt @@ -9,6 +9,9 @@ string(TOUPPER OPT_MCU_${target} tusb_mcu) list(APPEND compile_definitions CFG_TUSB_MCU=${tusb_mcu} CFG_TUSB_OS=OPT_OS_FREERTOS + # EXAMPLE port selection: port0 is fullspeed, port1 is highspeed + BOARD_TUD_RHPORT=${TUD_PORT} + BOARD_TUD_MAX_SPEED=$ ) list(APPEND srcs diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake index b0786f1cc..ada082c76 100644 --- a/hw/bsp/espressif/family.cmake +++ b/hw/bsp/espressif/family.cmake @@ -2,9 +2,17 @@ cmake_minimum_required(VERSION 3.5) # Apply board specific content i.e IDF_TARGET must be set before project.cmake is included include("${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake") - string(TOUPPER ${IDF_TARGET} FAMILY_MCUS) +# Device port default to Port1 for P4 (highspeed), Port0 for others (fullspeed) +if (NOT DEFINED TUD_PORT) + if (IDF_TARGET STREQUAL "esp32p4") + set(TUD_PORT 1) + else () + set(TUD_PORT 0) + endif () +endif() + # Add example src and bsp directories set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components") diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index d1eb22ed7..4fa869241 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -31,6 +31,9 @@ #if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2) +// Debug level for DWC2 +#define DWC2_DEBUG 2 + #include "device/dcd.h" #include "dwc2_type.h" @@ -57,15 +60,24 @@ #error "Unsupported MCUs" #endif -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM -//--------------------------------------------------------------------+ +enum { + DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller) +}; // DWC2 registers -#define DWC2_REG(_port) ((dwc2_regs_t*) _dwc2_controller[_port].reg_base) +//#define DWC2_REG(_port) ((dwc2_regs_t*) _dwc2_controller[_port].reg_base) -// Debug level for DWC2 -#define DWC2_DEBUG 2 +TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { + if (rhport >= DWC2_CONTROLLER_COUNT) { + // user mis-configured, ignore and use first controller + rhport = 0; + } + return (dwc2_regs_t*) _dwc2_controller[rhport].reg_base; +} + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2]; @@ -584,7 +596,9 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); // Set 16-bit interface if supported - if (dwc2->ghwcfg4_bm.phy_data_width) gusbcfg |= GUSBCFG_PHYIF16; + if (dwc2->ghwcfg4_bm.phy_data_width) { + gusbcfg |= GUSBCFG_PHYIF16; + } } // Apply config @@ -621,7 +635,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { } static bool check_dwc2(dwc2_regs_t* dwc2) { -#if CFG_TUSB_DEBUG >= DWC2_DEBUG || 1 +#if CFG_TUSB_DEBUG >= DWC2_DEBUG // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4 // Run 'dwc2_info.py render-md' and check dwc2_info.md for bit-field value and comparison with other ports volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid; diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index af04347d1..4cdbcdb7a 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -39,50 +39,36 @@ #include "soc/usb_wrap_struct.h" #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) -#define DWC2_PERIPH_COUNT 1 -#define DWC2_FS_REG_BASE 0x60080000UL -#define DWC2_EP_MAX 7 +#define DWC2_FS_REG_BASE 0x60080000UL +#define DWC2_EP_MAX 7 static const dwc2_controller_t _dwc2_controller[] = { { .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 } }; #elif TU_CHECK_MCU(OPT_MCU_ESP32P4) - -#define DWC2_PERIPH_COUNT 2 -#define DWC2_FS_REG_BASE 0x50040000UL -#define DWC2_HS_REG_BASE 0x50000000UL -#define DWC2_EP_MAX 16 +#define DWC2_FS_REG_BASE 0x50040000UL +#define DWC2_HS_REG_BASE 0x50000000UL +#define DWC2_EP_MAX 16 // On ESP32 for consistency we associate // - Port0 to OTG_FS, and Port1 to OTG_HS static const dwc2_controller_t _dwc2_controller[] = { - { - .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, - .ep_fifo_size = 4096 - }, -{ - .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, - .ep_fifo_size = 1024 -} - +{ .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 }, +{ .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 } }; #endif -enum { - DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller) -}; - -static intr_handle_t usb_ih[DWC2_CONTROLLER_COUNT]; +static intr_handle_t usb_ih[TU_ARRAY_SIZE(_dwc2_controller)]; static void dcd_int_handler_wrap(void* arg) { - const uint8_t rhport = (uint8_t) arg; + const uint8_t rhport = (uint8_t)(uintptr_t) arg; dcd_int_handler(rhport); } TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { esp_intr_alloc(_dwc2_controller[rhport].irqnum, ESP_INTR_FLAG_LOWMED, - dcd_int_handler_wrap, (void*) rhport, &usb_ih[rhport]); + dcd_int_handler_wrap, (void*)(uintptr_t) rhport, &usb_ih[rhport]); } TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) { @@ -97,7 +83,6 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { (void)dwc2; (void)hs_phy_type; - // nothing to do } @@ -105,7 +90,6 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { (void)dwc2; (void)hs_phy_type; - // nothing to do } -- cgit v1.3.1 From 4617fb52296d2361bf848f7629d2d8be1aba5130 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 30 Sep 2024 21:53:57 +0700 Subject: update build script to correctly skip non max3421 enabled for espressif boards --- .../boards/adafruit_feather_esp32_v2/board.cmake | 1 + .../boards/adafruit_feather_esp32s2/board.cmake | 1 + .../boards/adafruit_feather_esp32s3/board.cmake | 3 ++ .../boards/adafruit_feather_esp32s3/board.h | 53 ++++++++++++++++++++++ .../boards/adafruit_metro_esp32s2/board.cmake | 1 + .../boards/espressif_c3_devkitc/board.cmake | 1 + .../boards/espressif_c6_devkitc/board.cmake | 1 + tools/build.py | 11 +++-- tools/build_utils.py | 44 +++++++++--------- 9 files changed, 89 insertions(+), 27 deletions(-) create mode 100644 hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.cmake create mode 100644 hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h (limited to 'hw') diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.cmake b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.cmake index 18c956714..84ea4940b 100644 --- a/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.cmake +++ b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.cmake @@ -1,2 +1,3 @@ # Apply board specific content here set(IDF_TARGET "esp32") +set(MAX3421_HOST 1) diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake index abbdf7abc..0bbf5a013 100644 --- a/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake +++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.cmake @@ -1,2 +1,3 @@ # Apply board specific content here set(IDF_TARGET "esp32s2") +set(MAX3421_HOST 1) diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.cmake b/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.cmake new file mode 100644 index 000000000..dd204f0a4 --- /dev/null +++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.cmake @@ -0,0 +1,3 @@ +# Apply board specific content here +set(IDF_TARGET "esp32s3") +set(MAX3421_HOST 1) diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h new file mode 100644 index 000000000..9aa2e7535 --- /dev/null +++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h @@ -0,0 +1,53 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define NEOPIXEL_PIN 33 +#define NEOPIXEL_POWER_PIN 21 +#define NEOPIXEL_POWER_STATE 1 + +#define BUTTON_PIN 0 +#define BUTTON_STATE_ACTIVE 0 + +// SPI for USB host shield +#define MAX3421_SPI_HOST SPI2_HOST +#define MAX3421_SCK_PIN 36 +#define MAX3421_MOSI_PIN 35 +#define MAX3421_MISO_PIN 37 +#define MAX3421_CS_PIN 10 +#define MAX3421_INTR_PIN 9 + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake index abbdf7abc..0bbf5a013 100644 --- a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake +++ b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.cmake @@ -1,2 +1,3 @@ # Apply board specific content here set(IDF_TARGET "esp32s2") +set(MAX3421_HOST 1) diff --git a/hw/bsp/espressif/boards/espressif_c3_devkitc/board.cmake b/hw/bsp/espressif/boards/espressif_c3_devkitc/board.cmake index ab4bc1a06..6a0060f9e 100644 --- a/hw/bsp/espressif/boards/espressif_c3_devkitc/board.cmake +++ b/hw/bsp/espressif/boards/espressif_c3_devkitc/board.cmake @@ -1,2 +1,3 @@ # Apply board specific content here set(IDF_TARGET "esp32c3") +set(MAX3421_HOST 1) diff --git a/hw/bsp/espressif/boards/espressif_c6_devkitc/board.cmake b/hw/bsp/espressif/boards/espressif_c6_devkitc/board.cmake index 50c7cb35d..9adaefb17 100644 --- a/hw/bsp/espressif/boards/espressif_c6_devkitc/board.cmake +++ b/hw/bsp/espressif/boards/espressif_c6_devkitc/board.cmake @@ -1,2 +1,3 @@ # Apply board specific content here set(IDF_TARGET "esp32c6") +set(MAX3421_HOST 1) diff --git a/tools/build.py b/tools/build.py index f9ae68231..44ac251de 100644 --- a/tools/build.py +++ b/tools/build.py @@ -84,10 +84,13 @@ def cmake_board(board, toolchain): # for espressif, we have to build example individually all_examples = get_examples(family) for example in all_examples: - rcmd = run_cmd(f'cmake examples/{example} -B {build_dir}/{example} -G "Ninja" -DBOARD={board} -DMAX3421_HOST=1') - if rcmd.returncode == 0: - rcmd = run_cmd(f'cmake --build {build_dir}/{example}') - ret[0 if rcmd.returncode == 0 else 1] += 1 + if build_utils.skip_example(example, board): + ret[2] += 1 + else: + rcmd = run_cmd(f'cmake examples/{example} -B {build_dir}/{example} -G "Ninja" -DBOARD={board}') + if rcmd.returncode == 0: + rcmd = run_cmd(f'cmake --build {build_dir}/{example}') + ret[0 if rcmd.returncode == 0 else 1] += 1 else: rcmd = run_cmd(f'cmake examples -B {build_dir} -G "Ninja" -DBOARD={board} -DCMAKE_BUILD_TYPE=MinSizeRel -DTOOLCHAIN={toolchain}') if rcmd.returncode == 0: diff --git a/tools/build_utils.py b/tools/build_utils.py index 5f88db8a2..265ab5c52 100644 --- a/tools/build_utils.py +++ b/tools/build_utils.py @@ -13,33 +13,25 @@ def skip_example(example, board): ex_dir = pathlib.Path('examples/') / example bsp = pathlib.Path("hw/bsp") - if (bsp / board / "board.mk").exists(): - # board without family - board_dir = bsp / board - family = "" - mk_contents = "" - else: - # board within family - board_dir = list(bsp.glob("*/boards/" + board)) - if not board_dir: - # Skip unknown boards - return True - - board_dir = list(board_dir)[0] + # board within family + board_dir = list(bsp.glob("*/boards/" + board)) + if not board_dir: + # Skip unknown boards + return True - family_dir = board_dir.parent.parent - family = family_dir.name + board_dir = list(board_dir)[0] + family_dir = board_dir.parent.parent + family = family_dir.name - # family.mk - family_mk = family_dir / "family.mk" - mk_contents = family_mk.read_text() + # family.mk + family_mk = family_dir / "family.mk" + mk_contents = family_mk.read_text() # Find the mcu, first in family mk then board mk if "CFG_TUSB_MCU=OPT_MCU_" not in mk_contents: - board_mk = board_dir / "board.cmake" + board_mk = board_dir / "board.mk" if not board_mk.exists(): - board_mk = board_dir / "board.mk" - + board_mk = board_dir / "board.cmake" mk_contents = board_mk.read_text() mcu = "NONE" @@ -49,18 +41,23 @@ def skip_example(example, board): token = token.strip("\"") _, opt_mcu = token.split("=") mcu = opt_mcu[len("OPT_MCU_"):] - break if "esp32s2" in token: mcu = "ESP32S2" - break if "esp32s3" in token: mcu = "ESP32S3" + if mcu != "NONE": break # Skip all OPT_MCU_NONE these are WIP port if mcu == "NONE": return True + max3421_enabled = False + for line in mk_contents.splitlines(): + if "MAX3421_HOST=1" in line or 'MAX3421_HOST 1' in line: + max3421_enabled = True + break + skip_file = ex_dir / "skip.txt" only_file = ex_dir / "only.txt" @@ -74,6 +71,7 @@ def skip_example(example, board): if only_file.exists(): onlys = only_file.read_text().split() if not ("mcu:" + mcu in onlys or + ("mcu:MAX3421" in onlys and max3421_enabled) or "board:" + board in onlys or "family:" + family in onlys): return True -- cgit v1.3.1 From 599bb0c8227f659b15302dac6a04706c7d3b2a4e Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 4 Oct 2024 22:26:40 +0700 Subject: improving dwc2, merging diep and doep if possible --- .idea/cmake.xml | 62 +++--- hw/bsp/stm32h7/boards/stm32h743eval/board.cmake | 1 + hw/bsp/stm32l4/boards/stm32l476disco/board.cmake | 2 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 230 ++++++++++++----------- src/portable/synopsys/dwc2/dwc2_info.md | 6 +- src/portable/synopsys/dwc2/dwc2_info.py | 6 +- src/portable/synopsys/dwc2/dwc2_type.h | 108 +++++++++-- 7 files changed, 246 insertions(+), 169 deletions(-) (limited to 'hw') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 37cd73c65..d4ad3a748 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -9,49 +9,49 @@ - + - + - + - + - + - + - + @@ -65,19 +65,15 @@ - - - - - - - + + + @@ -86,33 +82,22 @@ - - - - - - - - - - - - - - + + + - + - + @@ -124,22 +109,31 @@ - + + + + + - - + + + + + + + + - diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake index a28aa87bd..6d7a97741 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake @@ -1,5 +1,6 @@ set(MCU_VARIANT stm32h743xx) set(JLINK_DEVICE stm32h743xi) +# set(JLINK_OPTION "-USB jtrace") set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld) diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake b/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake index 4ade0a5c9..fd1c931c2 100644 --- a/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake +++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake @@ -1,6 +1,6 @@ set(MCU_VARIANT stm32l476xx) set(JLINK_DEVICE stm32l476vg) - +# set(JLINK_OPTION "-USB 000777632258") set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32L476VGTx_FLASH.ld) function(update_board TARGET) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 210ce1bba..99cf3fdaa 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -327,53 +327,49 @@ static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoin xfer->interval = p_endpoint_desc->bInterval; // USBAEP, EPTYP, SD0PID_SEVNFRM, MPSIZ are the same for IN and OUT endpoints. - uint32_t const dxepctl = (1 << DOEPCTL_USBAEP_Pos) | - (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) | - (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << DOEPCTL_MPSIZ_Pos); - - if (dir == TUSB_DIR_OUT) { - dwc2->epout[epnum].doepctl = dxepctl; - dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum); - } else { - dwc2->epin[epnum].diepctl = dxepctl | (epnum << DIEPCTL_TXFNUM_Pos); - dwc2->daintmsk |= TU_BIT(DAINTMSK_IEPM_Pos + epnum); + uint32_t epctl = (1 << DOEPCTL_USBAEP_Pos) | + (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) | + (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | + (xfer->max_size << DOEPCTL_MPSIZ_Pos); + if (dir == TUSB_DIR_IN) { + epctl |= (epnum << DIEPCTL_TXFNUM_Pos); } + + dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum]; + dep->ctl = epctl; + dwc2->daintmsk |= TU_BIT(epnum + DAINT_SHIFT(dir)); } static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { (void) rhport; dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + const uint8_t epnum = tu_edpt_number(ep_addr); + const uint8_t dir = tu_edpt_dir(ep_addr); + dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum]; if (dir == TUSB_DIR_IN) { - dwc2_epin_t* epin = dwc2->epin; - // Only disable currently enabled non-control endpoint - if ((epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA)) { - epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0); + if ((epnum == 0) || !(dep->diepctl & DIEPCTL_EPENA)) { + dep->diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0); } else { // Stop transmitting packets and NAK IN xfers. - epin[epnum].diepctl |= DIEPCTL_SNAK; - while ((epin[epnum].diepint & DIEPINT_INEPNE) == 0) {} + dep->diepctl |= DIEPCTL_SNAK; + while ((dep->diepint & DIEPINT_INEPNE) == 0) {} // Disable the endpoint. - epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0); - while ((epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0) {} + dep->diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0); + while ((dep->diepint & DIEPINT_EPDISD_Msk) == 0) {} - epin[epnum].diepint = DIEPINT_EPDISD; + dep->diepint = DIEPINT_EPDISD; } // Flush the FIFO, and wait until we have confirmed it cleared. dfifo_flush_tx(dwc2, epnum); } else { - dwc2_epout_t* epout = dwc2->epout; - // Only disable currently enabled non-control endpoint - if ((epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA)) { - epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0; + if ((epnum == 0) || !(dep->doepctl & DOEPCTL_EPENA)) { + dep->doepctl |= stall ? DOEPCTL_STALL : 0; } else { // Asserting GONAK is required to STALL an OUT endpoint. // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt @@ -382,11 +378,11 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { dwc2->dctl |= DCTL_SGONAK; while ((dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0) {} - // Ditto here- disable the endpoint. - epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); - while ((epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0) {} + // Ditto here disable the endpoint. + dep->doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); + while ((dep->doepint & DOEPINT_EPDISD_Msk) == 0) {} - epout[epnum].doepint = DOEPINT_EPDISD; + dep->doepint = DOEPINT_EPDISD; // Allow other OUT endpoints to keep receiving. dwc2->dctl |= DCTL_CGONAK; @@ -430,7 +426,7 @@ static void bus_reset(uint8_t rhport) { dfifo_init(rhport); - // Fixed control EP0 size to 64 bytes + // Fixed both control EP0 size to 64 bytes dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos); dwc2->epout[0].doepctl &= ~(0x03 << DOEPCTL_MPSIZ_Pos); @@ -461,33 +457,33 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c } // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here. - if (dir == TUSB_DIR_IN) { - dwc2_epin_t* epin = dwc2->epin; + const uint8_t is_epout = 1 - dir; + dwc2_dep_t* dep = &dwc2->ep[is_epout][epnum]; + if (dir == TUSB_DIR_IN) { // A full IN transfer (multiple packets, possibly) triggers XFRC. - epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | + dep->dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); if(dma_enabled(dwc2)) { - epin[epnum].diepdma = (uintptr_t)xfer->buffer; + dep->diepdma = (uintptr_t)xfer->buffer; // For ISO endpoint set correct odd/even bit for next frame. - if ((epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { + if ((dep->diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { // Take odd/even bit from frame counter. uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); - epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); + dep->diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); } - epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; + dep->diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; } else { - - epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; + dep->diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; // For ISO endpoint set correct odd/even bit for next frame. - if ((epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { + if ((dep->diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { // Take odd/even bit from frame counter. uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); - epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); + dep->diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); } // Enable fifo empty interrupt only if there are something to put in the fifo. if (total_bytes != 0) { @@ -495,25 +491,23 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c } } } else { - dwc2_epout_t* epout = dwc2->epout; - // A full OUT transfer (multiple packets, possibly) triggers XFRC. - epout[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ); - epout[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) | + dep->doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ); + dep->doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) | ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk); - if ((epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && + if ((dep->doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && XFER_CTL_BASE(epnum, dir)->interval == 1) { // Take odd/even bit from frame counter. uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); - epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); + dep->doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); } if(dma_enabled(dwc2)) { - epout[epnum].doepdma = (uintptr_t)xfer->buffer; + dep->doepdma = (uintptr_t)xfer->buffer; } - epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK; + dep->doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK; } } @@ -837,17 +831,13 @@ void dcd_edpt_close_all(uint8_t rhport) { dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); for (uint8_t n = 1; n < ep_count; n++) { - // disable OUT endpoint - if (dwc2->epout[n].doepctl & DOEPCTL_EPENA) { - dwc2->epout[n].doepctl |= DOEPCTL_SNAK | DOEPCTL_EPDIS; - } - xfer_status[n][TUSB_DIR_OUT].max_size = 0; - - // disable IN endpoint - if (dwc2->epin[n].diepctl & DIEPCTL_EPENA) { - dwc2->epin[n].diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS; + for (uint8_t d = 0; d < 2; d++) { + dwc2_dep_t* dep = &dwc2->ep[d][n]; + if (dep->ctl & EPCTL_EPENA) { + dep->ctl |= EPCTL_SNAK | EPCTL_EPDIS; + } + xfer_status[n][1-d].max_size = 0; } - xfer_status[n][TUSB_DIR_IN].max_size = 0; } dfifo_flush_tx(dwc2, 0x10); // all tx fifo @@ -937,21 +927,14 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { } void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - (void) rhport; - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); + dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum]; // Clear stall and reset data toggle - if (dir == TUSB_DIR_IN) { - dwc2->epin[epnum].diepctl &= ~DIEPCTL_STALL; - dwc2->epin[epnum].diepctl |= DIEPCTL_SD0PID_SEVNFRM; - } else { - dwc2->epout[epnum].doepctl &= ~DOEPCTL_STALL; - dwc2->epout[epnum].doepctl |= DOEPCTL_SD0PID_SEVNFRM; - } + dep->ctl &= ~EPCTL_STALL;; + dep->ctl |= EPCTL_SD0PID_SEVNFRM; } //-------------------------------------------------------------------- @@ -963,10 +946,10 @@ static void handle_rxflvl_irq(uint8_t rhport) { volatile uint32_t const* rx_fifo = dwc2->fifo[0]; // Pop control word off FIFO - uint32_t const ctl_word = dwc2->grxstsp; - uint8_t const pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; - uint8_t const epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; - uint16_t const bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; + uint32_t const grxstsp = dwc2->grxstsp; + uint8_t const pktsts = (grxstsp & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; + uint8_t const epnum = (grxstsp & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; + uint16_t const bcnt = (grxstsp & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; dwc2_epout_t* epout = &dwc2->epout[epnum]; @@ -1024,20 +1007,16 @@ static void handle_rxflvl_irq(uint8_t rhport) { ep0_pending[TUSB_DIR_OUT] = 0; } } - } break; + } - // Out packet done (Interrupt) case GRXSTS_PKTSTS_OUTDONE: - // Occurred on STM32L47 with dwc2 version 3.10a but not found on other version like 2.80a or 3.30a - // May (or not) be 3.10a specific feature/bug or depending on MCU configuration - // XFRC complete is additionally generated when - // - setup packet is received - // - complete the data stage of control write is complete - // It will be handled in handle_epout_irq() + /* Out packet done (Interrupt) + After this entry is popped from the receive FIFO, the controller asserts a Transfer Completed interrupt on + the specified OUT endpoint which will be handled by handle_epout_irq() */ break; - default: // Invalid + default: TU_BREAKPOINT(); break; } @@ -1049,73 +1028,73 @@ static void handle_epout_irq(uint8_t rhport) { // DAINT for a given EP clears when DOEPINTx is cleared. // OEPINT will be cleared when DAINT's out bits are cleared. - for (uint8_t n = 0; n < ep_count; n++) { - if (dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + n)) { - dwc2_epout_t* epout = &dwc2->epout[n]; - - uint32_t const doepint = epout->doepint; - + for (uint8_t epnum = 0; epnum < ep_count; epnum++) { + if (dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + epnum)) { + dwc2_epout_t* epout = &dwc2->epout[epnum]; + const uint32_t doepint = epout->doepint; TU_ASSERT((epout->doepint & DOEPINT_AHBERR) == 0, ); // OUT XFER complete - if (epout->doepint & DOEPINT_XFRC) { + if (doepint & DOEPINT_XFRC) { epout->doepint = DOEPINT_XFRC; - xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); + xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); if(dma_enabled(dwc2)) { - if (doepint & DOEPINT_STUP) { + if (doepint & DOEPINT_SETUP) { // STPKTRX is only available for version from 3_00a - if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { - epout->doepint = DOEPINT_STPKTRX; + if ((doepint & DOEPINT_DMA_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { + epout->doepint = DOEPINT_DMA_STPKTRX; } - } else if (doepint & DOEPINT_OTEPSPR) { - epout->doepint = DOEPINT_OTEPSPR; + } else if (doepint & DOEPINT_STSPHSRX) { + epout->doepint = DOEPINT_STSPHSRX; } else { - if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { - epout->doepint = DOEPINT_STPKTRX; + if ((doepint & DOEPINT_DMA_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { + epout->doepint = DOEPINT_DMA_STPKTRX; } else { // EP0 can only handle one packet - if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) { + if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { // Schedule another packet to be received. - edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); } else { // Fix packet length uint16_t remain = (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; xfer->total_len -= remain; // this is ZLP, so prepare EP0 for next setup - if(n == 0 && xfer->total_len == 0) { + if(epnum == 0 && xfer->total_len == 0) { dma_setup_prepare(rhport); } - dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); + dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); } } } } else { - if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid == DWC2_CORE_REV_3_10a)) { - epout->doepint = DOEPINT_STPKTRX; + // DMA_STPKTRX should only be set in Buffer DMA Mode. However, STM32L476 (slave-only) with v3.10a + // incorrectly set this along with SETUP bit. This may (or not) be STM32L476 or 3.10a specific bug + if ((doepint & DOEPINT_DMA_STPKTRX) && (dwc2->gsnpsid == DWC2_CORE_REV_3_10a)) { + epout->doepint = DOEPINT_DMA_STPKTRX; } else { - if ((doepint & DOEPINT_OTEPSPR) && (dwc2->gsnpsid == DWC2_CORE_REV_3_10a)) { - epout->doepint = DOEPINT_OTEPSPR; + if ((doepint & DOEPINT_STSPHSRX) && (dwc2->gsnpsid == DWC2_CORE_REV_3_10a)) { + epout->doepint = DOEPINT_STSPHSRX; } // EP0 can only handle one packet - if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) { + if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { // Schedule another packet to be received. - edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); } else { - dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); + dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); } } } } // SETUP packet Setup Phase done. - if (doepint & DOEPINT_STUP) { - epout->doepint = DOEPINT_STUP; - if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { - epout->doepint = DOEPINT_STPKTRX; + if (doepint & DOEPINT_SETUP) { + epout->doepint = DOEPINT_SETUP; + if ((doepint & DOEPINT_DMA_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { + epout->doepint = DOEPINT_DMA_STPKTRX; } if(dma_enabled(dwc2) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { dma_setup_prepare(rhport); @@ -1195,6 +1174,29 @@ static void handle_epin_irq(uint8_t rhport) { } } +/* Interrupt Hierarchy + + DxEPMSK.XferComplMsk DxEPINTn.XferCompl + | | + +---------- AND --------+ + | + DAINT.xEPnInt DAINTMSK.xEPnMsk + | | + +---------- AND --------+ + | + GINTSTS.xEPInt GINTMSK.xEPIntMsk + | | + +---------- AND --------+ + | + GAHBCFG.GblIntrMsk + | + IRQn + + Note: when OTG_MULTI_PROC_INTRPT = 1, Device Each endpoint interrupt deachint/deachmsk/diepeachmsk/doepeachmsk + are combined to generate dedicated interrupt line for each endpoint. + */ + + void dcd_int_handler(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); @@ -1276,8 +1278,8 @@ void dcd_int_handler(uint8_t rhport) { // Mask out RXFLVL while reading data from FIFO dwc2->gintmsk &= ~GINTMSK_RXFLVLM; - // Loop until all available packets were handled do { + // Loop until all available packets were handled handle_rxflvl_irq(rhport); } while(dwc2->gintsts & GINTSTS_RXFLVL); diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index cd8a57ec3..5c7e5e688 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -8,13 +8,13 @@ | - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | | - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | DMA internal | | - p2p (hub support) | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | -| - hs_phy_type | UTMI+ | N/A | N/A | UTMI+/ULPI | N/A | ULPI | N/A | N/A | UTMI+/ULPI | ULPI | ULPI | N/A | UTMI+ | N/A | N/A | -| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | N/A | N/A | Dedicated | +| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | +| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | n/a | Dedicated | | - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | | - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 0 | 13 | | - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | | - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | | - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | - nptx_q_depth | 2 | 2 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | | - ptx_q_depth | 2 | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 62437cfde..ac32eb585 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -50,7 +50,7 @@ class GHWCFG2(ctypes.LittleEndianStructure): ("num_host_ch", ctypes.c_uint32, 4), ("period_channel_support", ctypes.c_uint32, 1), ("enable_dynamic_fifo", ctypes.c_uint32, 1), - ("mul_cpu_int", ctypes.c_uint32, 1), + ("mul_proc_intrpt", ctypes.c_uint32, 1), ("reserved21", ctypes.c_uint32, 1), ("nptx_q_depth", ctypes.c_uint32, 2), ("ptx_q_depth", ctypes.c_uint32, 2), @@ -119,13 +119,13 @@ GHWCFG2_field = { 2: "DMA internal" }, 'hs_phy_type': { - 0: "N/A", + 0: "n/a", 1: "UTMI+", 2: "ULPI", 3: "UTMI+/ULPI" }, 'fs_phy_type': { - 0: "N/A", + 0: "n/a", 1: "Dedicated", 2: "Shared UTMI+", 3: "Shared ULPI" diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index ac88dd24d..d5a51fb09 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -250,7 +250,7 @@ typedef struct TU_ATTR_PACKED { uint32_t num_host_ch : 4; // 14..17 Number of host channel (excluding control) uint32_t period_channel_support : 1; // 18 Support Periodic OUT Host Channel uint32_t enable_dynamic_fifo : 1; // 19 Dynamic FIFO Sizing Enabled - uint32_t mul_cpu_int : 1; // 20 Multi-Processor Interrupt Enabled + uint32_t mul_proc_intrpt : 1; // 20 Multi-Processor Interrupt enabled (OTG_MULTI_PROC_INTRPT) uint32_t reserved21 : 1; // 21 reserved uint32_t nptx_q_depth : 2; // 22..23 Non-periodic request queue depth: 0 = 2. 1 = 4, 2 = 8 uint32_t ptx_q_depth : 2; // 24..25 Host periodic request queue depth: 0 = 2. 1 = 4, 2 = 8 @@ -336,6 +336,32 @@ typedef struct { uint32_t reserved18[2]; // B18..B1C } dwc2_epout_t; +typedef struct { + union { + volatile uint32_t diepctl; + volatile uint32_t doepctl; + volatile uint32_t ctl; + }; + uint32_t rsv04; + union { + volatile uint32_t diepint; + volatile uint32_t doepint; + }; + uint32_t rsv0c; + union { + volatile uint32_t dieptsiz; + volatile uint32_t doeptsiz; + }; + union { + volatile uint32_t diepdma; + volatile uint32_t doepdma; + }; + volatile uint32_t dtxfsts; + uint32_t rsv1c; +}dwc2_dep_t; + +TU_VERIFY_STATIC(sizeof(dwc2_dep_t) == 0x20, "incorrect size"); + //-------------------------------------------------------------------- // CSR Register Map //-------------------------------------------------------------------- @@ -418,16 +444,24 @@ typedef struct { volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time volatile uint32_t dthrctl; // 830 Device threshold Control volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask + + // Device Each Endpoint (IN/OUT) Interrupt/Mask for generating dedicated EP interrupt line + // require OTG_MULTI_PROC_INTRPT=1 volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt - volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt msk + volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt mask volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask volatile uint32_t doepeachmsk[16]; // 880..8BF Device Each OUT Endpoint mask uint32_t reserved8c0[16]; // 8C0..8FF //------------- Device Endpoint -------------// - dwc2_epin_t epin[16]; // 900..AFF IN Endpoints - dwc2_epout_t epout[16]; // B00..CFF OUT Endpoints - uint32_t reservedd00[64]; // D00..DFF + union { + dwc2_dep_t ep[2][16]; // 0: IN, 1 OUT + struct { + dwc2_epin_t epin[16]; // 900..AFF IN Endpoints + dwc2_epout_t epout[16]; // B00..CFF OUT Endpoints + }; + }; + uint32_t reservedd00[64]; // D00..DFF //------------- Power Clock -------------// volatile uint32_t pcgctl; // E00 Power and Clock Gating Control @@ -1094,6 +1128,8 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DAINTMSK_OEPM_Msk (0xFFFFUL << DAINTMSK_OEPM_Pos) // 0xFFFF0000 #define DAINTMSK_OEPM DAINTMSK_OEPM_Msk // OUT EP interrupt mask bits +#define DAINT_SHIFT(_dir) ((_dir == TUSB_DIR_IN) ? 0 : 16) + #if 0 /******************** Bit definition for OTG register ********************/ #define CHNUM_Pos (0U) @@ -1803,6 +1839,45 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DIEPTXF_INEPTXFD_Msk (0xFFFFUL << DIEPTXF_INEPTXFD_Pos) // 0xFFFF0000 #define DIEPTXF_INEPTXFD DIEPTXF_INEPTXFD_Msk // IN endpoint TxFIFO depth + +/******************** Bit definition for Common EPCTL register ********************/ +#define EPCTL_MPSIZ_Pos (0U) +#define EPCTL_MPSIZ_Msk (0x7FFUL << EPCTL_MPSIZ_Pos) // 0x000007FF +#define EPCTL_MPSIZ EPCTL_MPSIZ_Msk // Maximum packet size //Bit 1 +#define EPCTL_USBAEP_Pos (15U) +#define EPCTL_USBAEP_Msk (0x1UL << EPCTL_USBAEP_Pos) // 0x00008000 +#define EPCTL_USBAEP EPCTL_USBAEP_Msk // USB active endpoint +#define EPCTL_NAKSTS_Pos (17U) +#define EPCTL_NAKSTS_Msk (0x1UL << EPCTL_NAKSTS_Pos) // 0x00020000 +#define EPCTL_NAKSTS EPCTL_NAKSTS_Msk // NAK status +#define EPCTL_EPTYP_Pos (18U) +#define EPCTL_EPTYP_Msk (0x3UL << EPCTL_EPTYP_Pos) // 0x000C0000 +#define EPCTL_EPTYP EPCTL_EPTYP_Msk // Endpoint type +#define EPCTL_EPTYP_0 (0x1UL << EPCTL_EPTYP_Pos) // 0x00040000 +#define EPCTL_EPTYP_1 (0x2UL << EPCTL_EPTYP_Pos) // 0x00080000 +#define EPCTL_SNPM EPCTL_SNPM_Msk // Snoop mode +#define EPCTL_STALL_Pos (21U) +#define EPCTL_STALL_Msk (0x1UL << EPCTL_STALL_Pos) // 0x00200000 +#define EPCTL_STALL EPCTL_STALL_Msk // STALL handshake +#define EPCTL_CNAK_Pos (26U) +#define EPCTL_CNAK_Msk (0x1UL << EPCTL_CNAK_Pos) // 0x04000000 +#define EPCTL_CNAK EPCTL_CNAK_Msk // Clear NAK +#define EPCTL_SNAK_Pos (27U) +#define EPCTL_SNAK_Msk (0x1UL << EPCTL_SNAK_Pos) // 0x08000000 +#define EPCTL_SNAK EPCTL_SNAK_Msk // Set NAK +#define EPCTL_SD0PID_SEVNFRM_Pos (28U) +#define EPCTL_SD0PID_SEVNFRM_Msk (0x1UL << EPCTL_SD0PID_SEVNFRM_Pos) // 0x10000000 +#define EPCTL_SD0PID_SEVNFRM EPCTL_SD0PID_SEVNFRM_Msk // Set DATA0 PID +#define EPCTL_SODDFRM_Pos (29U) +#define EPCTL_SODDFRM_Msk (0x1UL << EPCTL_SODDFRM_Pos) // 0x20000000 +#define EPCTL_SODDFRM EPCTL_SODDFRM_Msk // Set odd frame +#define EPCTL_EPDIS_Pos (30U) +#define EPCTL_EPDIS_Msk (0x1UL << EPCTL_EPDIS_Pos) // 0x40000000 +#define EPCTL_EPDIS EPCTL_EPDIS_Msk // Endpoint disable +#define EPCTL_EPENA_Pos (31U) +#define EPCTL_EPENA_Msk (0x1UL << EPCTL_EPENA_Pos) // 0x80000000 +#define EPCTL_EPENA EPCTL_EPENA_Msk // Endpoint enable + /******************** Bit definition for DOEPCTL register ********************/ #define DOEPCTL_MPSIZ_Pos (0U) #define DOEPCTL_MPSIZ_Msk (0x7FFUL << DOEPCTL_MPSIZ_Pos) // 0x000007FF @@ -1853,15 +1928,19 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DOEPINT_AHBERR_Pos (2U) #define DOEPINT_AHBERR_Msk (0x1UL << DOEPINT_AHBERR_Pos) // 0x00000004 #define DOEPINT_AHBERR DOEPINT_AHBERR_Msk // AHB Error (AHBErr) during an OUT transaction -#define DOEPINT_STUP_Pos (3U) -#define DOEPINT_STUP_Msk (0x1UL << DOEPINT_STUP_Pos) // 0x00000008 -#define DOEPINT_STUP DOEPINT_STUP_Msk // SETUP phase done + +#define DOEPINT_SETUP_Pos (3U) +#define DOEPINT_SETUP_Msk (0x1UL << DOEPINT_SETUP_Pos) // 0x00000008 +#define DOEPINT_SETUP DOEPINT_SETUP_Msk // SETUP phase done + #define DOEPINT_OTEPDIS_Pos (4U) #define DOEPINT_OTEPDIS_Msk (0x1UL << DOEPINT_OTEPDIS_Pos) // 0x00000010 #define DOEPINT_OTEPDIS DOEPINT_OTEPDIS_Msk // OUT token received when endpoint disabled -#define DOEPINT_OTEPSPR_Pos (5U) -#define DOEPINT_OTEPSPR_Msk (0x1UL << DOEPINT_OTEPSPR_Pos) // 0x00000020 -#define DOEPINT_OTEPSPR DOEPINT_OTEPSPR_Msk // Status Phase Received For Control Write + +#define DOEPINT_STSPHSRX_Pos (5U) +#define DOEPINT_STSPHSRX_Msk (0x1UL << DOEPINT_STSPHSRX_Pos) // 0x00000020 +#define DOEPINT_STSPHSRX DOEPINT_STSPHSRX_Msk // Status Phase Received For Control Write + #define DOEPINT_B2BSTUP_Pos (6U) #define DOEPINT_B2BSTUP_Msk (0x1UL << DOEPINT_B2BSTUP_Pos) // 0x00000040 #define DOEPINT_B2BSTUP DOEPINT_B2BSTUP_Msk // Back-to-back SETUP packets received @@ -1874,9 +1953,10 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DOEPINT_NYET_Pos (14U) #define DOEPINT_NYET_Msk (0x1UL << DOEPINT_NYET_Pos) // 0x00004000 #define DOEPINT_NYET DOEPINT_NYET_Msk // NYET interrupt -#define DOEPINT_STPKTRX_Pos (15U) -#define DOEPINT_STPKTRX_Msk (0x1UL << DOEPINT_STPKTRX_Pos) // 0x00008000 -#define DOEPINT_STPKTRX DOEPINT_STPKTRX_Msk // Setup Packet Received + +#define DOEPINT_DMA_STPKTRX_Pos (15U) +#define DOEPINT_DMA_STPKTRX_Msk (0x1UL << DOEPINT_DMA_STPKTRX_Pos) // 0x00008000 +#define DOEPINT_DMA_STPKTRX DOEPINT_DMA_STPKTRX_Msk // Setup Packet Received in Buffer DMA Mode /******************** Bit definition for DOEPTSIZ register ********************/ #define DOEPTSIZ_XFRSIZ_Pos (0U) -- cgit v1.3.1 From 07c14f30a6d6cfb1758e3496c3ea73275ae4a062 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 8 Oct 2024 12:36:45 +0700 Subject: add f407disco to hil pool --- hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake | 16 ++ hw/bsp/stm32h7/boards/stm32h750_weact/board.h | 132 ++++++++++++++++ hw/bsp/stm32h7/boards/stm32h750_weact/board.mk | 21 +++ .../stm32h750_weact/stm32h750xx_flash_CM7.ld | 170 +++++++++++++++++++++ hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake | 2 +- hw/bsp/stm32h7/boards/stm32h750bdk/board.mk | 2 +- hw/bsp/stm32h7/family.c | 12 +- src/portable/synopsys/dwc2/dwc2_info.md | 116 +++++++------- src/portable/synopsys/dwc2/dwc2_info.py | 23 +-- test/hil/hil_test.py | 2 +- test/hil/tinyusb.json | 24 ++- 11 files changed, 438 insertions(+), 82 deletions(-) create mode 100644 hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake create mode 100644 hw/bsp/stm32h7/boards/stm32h750_weact/board.h create mode 100644 hw/bsp/stm32h7/boards/stm32h750_weact/board.mk create mode 100644 hw/bsp/stm32h7/boards/stm32h750_weact/stm32h750xx_flash_CM7.ld (limited to 'hw') diff --git a/hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake b/hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake new file mode 100644 index 000000000..6303ca462 --- /dev/null +++ b/hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake @@ -0,0 +1,16 @@ +set(MCU_VARIANT stm32h750xx) +set(JLINK_DEVICE stm32h750vb) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${MCU_VARIANT}_flash_CM7.ld) +set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + STM32H750xx + HSE_VALUE=25000000 + CORE_CM7 + # default to PORT 0 + BOARD_TUD_RHPORT=0 + BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED + ) +endfunction() diff --git a/hw/bsp/stm32h7/boards/stm32h750_weact/board.h b/hw/bsp/stm32h7/boards/stm32h750_weact/board.h new file mode 100644 index 000000000..d117637a5 --- /dev/null +++ b/hw/bsp/stm32h7/boards/stm32h750_weact/board.h @@ -0,0 +1,132 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define LED_PORT GPIOE +#define LED_PIN GPIO_PIN_3 +#define LED_STATE_ON 1 + +// Blue push-button +#define BUTTON_PORT GPIOC +#define BUTTON_PIN GPIO_PIN_13 +#define BUTTON_STATE_ACTIVE 1 + +// UART +//#define UART_DEV USART3 +//#define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE +//#define UART_GPIO_PORT GPIOB +//#define UART_GPIO_AF GPIO_AF7_USART3 +//#define UART_TX_PIN GPIO_PIN_10 +//#define UART_RX_PIN GPIO_PIN_11 + +// VBUS Sense detection +#define OTG_FS_VBUS_SENSE 1 +#define OTG_HS_VBUS_SENSE 0 + +//--------------------------------------------------------------------+ +// RCC Clock +//--------------------------------------------------------------------+ +static inline void SystemClock_Config(void) { + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + // Supply configuration update enable + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + + // Configure the main internal regulator output voltage + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + // Configure the PLL clock source + __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE); + + // Initializes the CPU, AHB and APB busses clocks + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 5; + RCC_OscInitStruct.PLL.PLLN = 96; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + // Initializes the CPU, AHB and APB busses clocks + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1); + + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_SPI4 + |RCC_PERIPHCLK_SPI1|RCC_PERIPHCLK_USB + |RCC_PERIPHCLK_QSPI; + PeriphClkInitStruct.PLL3.PLL3M = 10; + PeriphClkInitStruct.PLL3.PLL3N = 96; + PeriphClkInitStruct.PLL3.PLL3P = 5; + PeriphClkInitStruct.PLL3.PLL3Q = 5; + PeriphClkInitStruct.PLL3.PLL3R = 2; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_1; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK; + PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL; + PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_D2PCLK1; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + // Enable USB Voltage detector + HAL_PWREx_EnableUSBVoltageDetector(); +} + +static inline void board_stm32h7_post_init(void) { + // For this board does nothing +} + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/stm32h7/boards/stm32h750_weact/board.mk b/hw/bsp/stm32h7/boards/stm32h750_weact/board.mk new file mode 100644 index 000000000..a50172cb0 --- /dev/null +++ b/hw/bsp/stm32h7/boards/stm32h750_weact/board.mk @@ -0,0 +1,21 @@ +# STM32H745I-DISCO uses OTG_FS +# FIXME: Reset enumerates, un/replug USB plug does not enumerate + +CFLAGS += -DSTM32H750xx -DCORE_CM7 -DHSE_VALUE=25000000 + +# Default is FulSpeed port +PORT ?= 0 + +# GCC +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h750xx.s +LD_FILE_GCC = $(BOARD_PATH)/stm32h750xx_flash_CM7.ld + +# IAR +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h750xx.s +LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h750xx_flash.icf + +# For flash-jlink target +JLINK_DEVICE = stm32h750vb + +# flash target using on-board stlink +flash: flash-jlink diff --git a/hw/bsp/stm32h7/boards/stm32h750_weact/stm32h750xx_flash_CM7.ld b/hw/bsp/stm32h7/boards/stm32h750_weact/stm32h750xx_flash_CM7.ld new file mode 100644 index 000000000..30f220a42 --- /dev/null +++ b/hw/bsp/stm32h7/boards/stm32h750_weact/stm32h750xx_flash_CM7.ld @@ -0,0 +1,170 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** +** Abstract : Linker script for STM32H7 series +** 128Kbytes FLASH and 1Mbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed ďż˝as is,ďż˝ without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2019 STMicroelectronics. +** All rights reserved. +** +** This software component is licensed by ST under BSD 3-Clause license, +** the "License"; You may not use this file except in compliance with the +** License. You may obtain a copy of the License at: +** opensource.org/licenses/BSD-3-Clause +** +**************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20020000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 1M +ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake b/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake index 6eff708a8..e87be8255 100644 --- a/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake +++ b/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake @@ -1,5 +1,5 @@ set(MCU_VARIANT stm32h750xx) -set(JLINK_DEVICE stm32h750xb_m7) +set(JLINK_DEVICE stm32h750xb) set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${MCU_VARIANT}_flash_CM7.ld) set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) diff --git a/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk b/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk index d37a425fb..923c90753 100644 --- a/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk +++ b/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk @@ -15,7 +15,7 @@ SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h750xx.s LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h750xx_flash.icf # For flash-jlink target -JLINK_DEVICE = stm32h750xb_m7 +JLINK_DEVICE = stm32h750xb # flash target using on-board stlink flash: flash-stlink diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c index adeb38e74..c81437958 100644 --- a/hw/bsp/stm32h7/family.c +++ b/hw/bsp/stm32h7/family.c @@ -102,9 +102,6 @@ void board_init(void) { trace_etm_init(); - // Enable UART Clock - UART_CLK_EN(); - #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); @@ -136,7 +133,10 @@ void board_init(void) { GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); +#ifdef UART_DEV // Uart + UART_CLK_EN(); + GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_PULLUP; @@ -153,6 +153,7 @@ void board_init(void) { UartHandle.Init.Mode = UART_MODE_TX_RX; UartHandle.Init.OverSampling = UART_OVERSAMPLING_16; HAL_UART_Init(&UartHandle); +#endif #if BOARD_TUD_RHPORT == 0 // Despite being call USB2_OTG @@ -280,8 +281,13 @@ int board_uart_read(uint8_t *buf, int len) { } int board_uart_write(void const *buf, int len) { +#ifdef UART_DEV HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t) buf, len, 0xffff); +#else + (void) buf; +#endif + return len; } diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index 5c7e5e688..cfd0c81a8 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -1,58 +1,58 @@ -| | BCM2711 (Pi4) | EFM32GG FS | ESP32-S2/S3 | ESP32-P4 | ST F407/411/429 FS | ST F407/429 HS | ST F412/767 FS | ST F723 FS | ST F723 HS | ST F769 | ST H743 HS | ST L476 FS | ST U5A5 HS | GD32VF103 FS | XMC4500 | -|:---------------------------|:----------------|:-------------|:--------------|:-------------|:---------------------|:-----------------|:-----------------|:-------------|:-------------|:-------------|:-------------|:-------------|:-------------|:---------------|:-------------| -| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | -| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | -| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | -| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | -| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | -| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | -| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | DMA internal | -| - p2p (hub support) | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | -| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | -| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | n/a | Dedicated | -| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | -| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 0 | 13 | -| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nptx_q_depth | 2 | 2 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - ptx_q_depth | 2 | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | -| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | -| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | -| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | -| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | -| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | -| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | -| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 0 | 634 | -| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | -| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | -| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | -| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | -| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | +| | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/767 FS | ST F723/L4P5 FS | ST F723 HS | ST F769 | ST H743/H750 | ST L476 FS | ST U5A5 HS | GD32VF103 | XMC4500 | +|:---------------------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:-------------|:------------|:-------------| +| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | +| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | +| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | +| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | +| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | +| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | DMA internal | +| - p2p (hub support) | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | +| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | +| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | n/a | Dedicated | +| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | +| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 0 | 13 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nptx_q_depth | 2 | 2 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - ptx_q_depth | 2 | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | +| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | +| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | +| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | +| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 0 | 634 | +| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | +| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | +| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | +| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | +| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index ac32eb585..d1793a005 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -10,20 +10,21 @@ import pandas as pd dwc2_reg_list = ['GUID', 'GSNPSID', 'GHWCFG1', 'GHWCFG2', 'GHWCFG3', 'GHWCFG4'] dwc2_reg_value = { 'BCM2711 (Pi4)': [0x2708A000, 0x4F54280A, 0, 0x228DDD50, 0xFF000E8, 0x1FF00020], - 'EFM32GG FS': [0, 0x4F54330A, 0, 0x228F5910, 0x1F204E8, 0x1BF08030], - 'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0xC804B5, 0xD3F0A030], + 'EFM32GG': [0, 0x4F54330A, 0, 0x228F5910, 0x01F204E8, 0x1BF08030], + 'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0x0C804B5, 0xD3F0A030], 'ESP32-P4': [0, 0x4F54400A, 0, 0x215FFFD0, 0x03805EB5, 0xDFF1A030], - 'ST F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030], - 'ST F407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030], - 'ST F412/767 FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], - 'ST F723 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], - 'ST F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x3EED2E8, 0x23F00030], + 'ST F207/F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x020001E8, 0x0FF08030], + 'ST F407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x03F403E8, 0x17F00030], + 'ST F412/767 FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], + 'ST F723/L4P5 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], + 'ST F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x03EED2E8, 0x23F00030], 'ST F769': [0x2100, 0x4F54320A, 0, 0x229FE190, 0x03EED2E8, 0x23F00030], - 'ST H743 HS': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x3B8D2E8, 0xE3F00030], # both HS cores - 'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], + 'ST H743/H750': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x03B8D2E8, 0xE3F00030], + 'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], 'ST U5A5 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30], - 'GD32VF103 FS': [0x1000, 0, 0, 0, 0, 0], - 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x27A01E5, 0xDBF08030] + 'GD32VF103': [0x1000, 0, 0, 0, 0, 0], + 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030] + } # Combine dwc2_info with dwc2_reg_list diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py index 60bba9bd2..0d7cae77e 100755 --- a/test/hil/hil_test.py +++ b/test/hil/hil_test.py @@ -245,7 +245,7 @@ def test_dual_host_info_to_device_cdc(board): # for pico/pico2 make this test optional failed_msg = f'Enumerated devices {enum_dev_sn} not match with declared {declared_devs}' if 'raspberry_pi_pico' in board['name']: - print(f'\r\n {failed_msg} ', end='') + print(f'\r\n {failed_msg} {STATUS_FAILED} ', end='') else: assert False, failed_msg return 0 diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json index 2358c3c4f..44d4a617c 100644 --- a/test/hil/tinyusb.json +++ b/test/hil/tinyusb.json @@ -20,6 +20,13 @@ "flasher_sn": "000682804350", "flasher_args": "-device nrf52840_xxaa" }, + { + "name": "max32666fthr", + "uid": "0C81464124010B20FF0A08CC2C", + "flasher": "openocd_adi", + "flasher_sn": "E6614C311B597D32", + "flasher_args": "-f interface/cmsis-dap.cfg -f target/max32665.cfg" + }, { "name": "metro_m4_express", "uid": "9995AD485337433231202020FF100A34", @@ -30,13 +37,6 @@ "dual_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002130"}] } }, - { - "name": "max32666fthr", - "uid": "0C81464124010B20FF0A08CC2C", - "flasher": "openocd_adi", - "flasher_sn": "E6614C311B597D32", - "flasher_args": "-f interface/cmsis-dap.cfg -f target/max32665.cfg" - }, { "name": "lpcxpresso11u37", "uid": "17121919", @@ -82,6 +82,16 @@ "flasher_sn": "779541626", "flasher_args": "-device stm32f072rb" }, + { + "name": "stm32f407disco", + "uid": "30001A000647313332353735", + "build" : { + "flags_on": ["", "CFG_TUD_DWC2_DMA"] + }, + "flasher": "jlink", + "flasher_sn": "000773661813", + "flasher_args": "-device stm32f407vg" + }, { "name": "stm32f769disco", "uid": "21002F000F51363531383437", -- cgit v1.3.1 From 98e94a5d6d5dfd2bb468f3c2f4c9e82925fedd91 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 9 Oct 2024 21:47:23 +0700 Subject: enhance dwc2 --- hw/bsp/xmc4000/boards/xmc4500_relax/board.cmake | 1 + src/portable/synopsys/dwc2/dcd_dwc2.c | 135 ++++++++++-------------- src/portable/synopsys/dwc2/dwc2_type.h | 6 +- 3 files changed, 61 insertions(+), 81 deletions(-) (limited to 'hw') diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.cmake b/hw/bsp/xmc4000/boards/xmc4500_relax/board.cmake index ec36bcc4d..e18741a9b 100644 --- a/hw/bsp/xmc4000/boards/xmc4500_relax/board.cmake +++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.cmake @@ -1,6 +1,7 @@ set(MCU_VARIANT XMC4500) set(JLINK_DEVICE XMC4500-1024) +#set(JLINK_OPTION "-USB 000551005307") set(LD_FILE_GNU ${SDK_DIR}/CMSIS/Infineon/COMPONENT_${MCU_VARIANT}/Source/TOOLCHAIN_GCC_ARM/XMC4500x1024.ld) function(update_board TARGET) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 99cf3fdaa..c0700633d 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -398,12 +398,8 @@ static void bus_reset(uint8_t rhport) { tu_memclr(xfer_status, sizeof(xfer_status)); _sof_en = false; - _allocated_ep_in_count = 1; - // clear device address - dwc2->dcfg &= ~DCFG_DAD_Msk; - // 1. NAK for all OUT endpoints for (uint8_t n = 0; n < ep_count; n++) { dwc2->epout[n].doepctl |= DOEPCTL_SNAK; @@ -419,13 +415,17 @@ static void bus_reset(uint8_t rhport) { dfifo_flush_tx(dwc2, 0x10); // all tx fifo dfifo_flush_rx(dwc2); - // 3. Set up interrupt mask + // 3. Set up interrupt mask for EP0 dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos); dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM; dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM; + // 4. Set up DFIFO dfifo_init(rhport); + // 5. Reset device address + dwc2->dcfg &= ~DCFG_DAD_Msk; + // Fixed both control EP0 size to 64 bytes dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos); dwc2->epout[0].doepctl &= ~(0x03 << DOEPCTL_MPSIZ_Pos); @@ -907,7 +907,9 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t uint16_t const short_packet_size = total_bytes % xfer->max_size; // Zero-size packet is special case. - if (short_packet_size > 0 || (total_bytes == 0)) num_packets++; + if (short_packet_size > 0 || (total_bytes == 0)) { + num_packets++; + } // Schedule packets to be sent within interrupt edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); @@ -941,6 +943,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { // Interrupt Handler //-------------------------------------------------------------------- +// Process shared receive FIFO, this interrupt is only used in Slave mode static void handle_rxflvl_irq(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); volatile uint32_t const* rx_fifo = dwc2->fifo[0]; @@ -950,20 +953,8 @@ static void handle_rxflvl_irq(uint8_t rhport) { uint8_t const pktsts = (grxstsp & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; uint8_t const epnum = (grxstsp & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; uint16_t const bcnt = (grxstsp & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; - dwc2_epout_t* epout = &dwc2->epout[epnum]; -//#if CFG_TUSB_DEBUG >= DWC2_DEBUG -// const char * pktsts_str[] = -// { -// "ASSERT", "Global NAK (ISR)", "Out Data Received", "Out Transfer Complete (ISR)", -// "Setup Complete (ISR)", "ASSERT", "Setup Data Received" -// }; -// TU_LOG_LOCATION(); -// TU_LOG(DWC2_DEBUG, " EP %02X, Byte Count %u, %s\r\n", epnum, bcnt, pktsts_str[pktsts]); -// TU_LOG(DWC2_DEBUG, " daint = %08lX, doepint = %04X\r\n", (unsigned long) dwc2->daint, (unsigned int) epout->doepint); -//#endif - switch (pktsts) { // Global OUT NAK: do nothing case GRXSTS_PKTSTS_GLOBALOUTNAK: @@ -971,15 +962,14 @@ static void handle_rxflvl_irq(uint8_t rhport) { case GRXSTS_PKTSTS_SETUPRX: // Setup packet received - - // We can receive up to three setup packets in succession, but - // only the last one is valid. + // We can receive up to three setup packets in succession, but only the last one is valid. _setup_packet[0] = (*rx_fifo); _setup_packet[1] = (*rx_fifo); break; case GRXSTS_PKTSTS_SETUPDONE: - // Setup packet done (Interrupt) + // Setup packet done: + // After popping this out, dwc2 asserts a DOEPINT_SETUP interrupt which is handled by handle_epout_irq() epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); break; @@ -1011,8 +1001,8 @@ static void handle_rxflvl_irq(uint8_t rhport) { } case GRXSTS_PKTSTS_OUTDONE: - /* Out packet done (Interrupt) - After this entry is popped from the receive FIFO, the controller asserts a Transfer Completed interrupt on + /* Out packet done + After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed interrupt on the specified OUT endpoint which will be handled by handle_epout_irq() */ break; @@ -1034,51 +1024,56 @@ static void handle_epout_irq(uint8_t rhport) { const uint32_t doepint = epout->doepint; TU_ASSERT((epout->doepint & DOEPINT_AHBERR) == 0, ); + TU_LOG1_HEX(doepint); + + // Setup and/or STPKTRX/STSPHSRX (from 3.00a) can be set along with XFRC, and also set independently. + if (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a) { + if (doepint & DOEPINT_STSPHSRX) { + // Status phase received for control write: In token received from Host + epout->doepint = DOEPINT_STSPHSRX; + } + + if (doepint & DOEPINT_STPKTRX) { + // New setup packet received, but wait for Setup done, since we can receive up to 3 setup consecutively + epout->doepint = DOEPINT_STPKTRX; + } + } + + if (doepint & DOEPINT_SETUP) { + epout->doepint = DOEPINT_SETUP; + + if(dma_enabled(dwc2)) { + dma_setup_prepare(rhport); + } + + dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); + } + // OUT XFER complete if (doepint & DOEPINT_XFRC) { epout->doepint = DOEPINT_XFRC; - xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); + // only handle data skip if it is setup or status related + // Normal OUT transfer complete + if (!(doepint & (DOEPINT_SETUP | DOEPINT_STPKTRX | DOEPINT_STSPHSRX))) { + xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - if(dma_enabled(dwc2)) { - if (doepint & DOEPINT_SETUP) { - // STPKTRX is only available for version from 3_00a - if ((doepint & DOEPINT_DMA_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { - epout->doepint = DOEPINT_DMA_STPKTRX; - } - } else if (doepint & DOEPINT_STSPHSRX) { - epout->doepint = DOEPINT_STSPHSRX; - } else { - if ((doepint & DOEPINT_DMA_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { - epout->doepint = DOEPINT_DMA_STPKTRX; + if(dma_enabled(dwc2)) { + if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { + // EP0 can only handle one packet Schedule another packet to be received. + edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); } else { - // EP0 can only handle one packet - if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { - // Schedule another packet to be received. - edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); - } else { - // Fix packet length - uint16_t remain = (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; - xfer->total_len -= remain; - // this is ZLP, so prepare EP0 for next setup - if(epnum == 0 && xfer->total_len == 0) { - dma_setup_prepare(rhport); - } - - dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); + // Fix packet length + uint16_t remain = (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; + xfer->total_len -= remain; + // this is ZLP, so prepare EP0 for next setup + if(epnum == 0 && xfer->total_len == 0) { + dma_setup_prepare(rhport); } + + dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); } - } - } else { - // DMA_STPKTRX should only be set in Buffer DMA Mode. However, STM32L476 (slave-only) with v3.10a - // incorrectly set this along with SETUP bit. This may (or not) be STM32L476 or 3.10a specific bug - if ((doepint & DOEPINT_DMA_STPKTRX) && (dwc2->gsnpsid == DWC2_CORE_REV_3_10a)) { - epout->doepint = DOEPINT_DMA_STPKTRX; } else { - if ((doepint & DOEPINT_STSPHSRX) && (dwc2->gsnpsid == DWC2_CORE_REV_3_10a)) { - epout->doepint = DOEPINT_STSPHSRX; - } - // EP0 can only handle one packet if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { // Schedule another packet to be received. @@ -1089,19 +1084,6 @@ static void handle_epout_irq(uint8_t rhport) { } } } - - // SETUP packet Setup Phase done. - if (doepint & DOEPINT_SETUP) { - epout->doepint = DOEPINT_SETUP; - if ((doepint & DOEPINT_DMA_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { - epout->doepint = DOEPINT_DMA_STPKTRX; - } - if(dma_enabled(dwc2) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { - dma_setup_prepare(rhport); - } - - dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); - } } } } @@ -1274,13 +1256,10 @@ void dcd_int_handler(uint8_t rhport) { // RxFIFO non-empty interrupt handling. if (int_status & GINTSTS_RXFLVL) { // RXFLVL bit is read-only - - // Mask out RXFLVL while reading data from FIFO - dwc2->gintmsk &= ~GINTMSK_RXFLVLM; + dwc2->gintmsk &= ~GINTMSK_RXFLVLM; // disable RXFLVL interrupt while reading do { - // Loop until all available packets were handled - handle_rxflvl_irq(rhport); + handle_rxflvl_irq(rhport); // read all packets } while(dwc2->gintsts & GINTSTS_RXFLVL); dwc2->gintmsk |= GINTMSK_RXFLVLM; diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index d5a51fb09..cf05bbfec 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -1954,9 +1954,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DOEPINT_NYET_Msk (0x1UL << DOEPINT_NYET_Pos) // 0x00004000 #define DOEPINT_NYET DOEPINT_NYET_Msk // NYET interrupt -#define DOEPINT_DMA_STPKTRX_Pos (15U) -#define DOEPINT_DMA_STPKTRX_Msk (0x1UL << DOEPINT_DMA_STPKTRX_Pos) // 0x00008000 -#define DOEPINT_DMA_STPKTRX DOEPINT_DMA_STPKTRX_Msk // Setup Packet Received in Buffer DMA Mode +#define DOEPINT_STPKTRX_Pos (15U) +#define DOEPINT_STPKTRX_Msk (0x1UL << DOEPINT_STPKTRX_Pos) // 0x00008000 +#define DOEPINT_STPKTRX DOEPINT_STPKTRX_Msk // Setup Packet Received /******************** Bit definition for DOEPTSIZ register ********************/ #define DOEPTSIZ_XFRSIZ_Pos (0U) -- cgit v1.3.1 From 57aac432b52df6d284c98daf591e661d1c55aa05 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 10 Oct 2024 16:22:12 +0700 Subject: add new tusb_int_handler(rhport, in_isr) as common irq handler update tusb_init() to take rhport and role, defined as macro with optional argument for backward compatible --- docs/reference/getting_started.rst | 13 ++--- examples/device/audio_4_channel_mic/src/main.c | 2 +- .../device/audio_4_channel_mic_freertos/src/main.c | 2 +- examples/device/audio_test/src/main.c | 2 +- examples/device/audio_test_freertos/src/main.c | 2 +- examples/device/audio_test_multi_rate/src/main.c | 2 +- examples/device/board_test/src/tusb_config.h | 5 -- examples/device/cdc_dual_ports/src/main.c | 2 +- examples/device/cdc_msc/src/main.c | 2 +- examples/device/cdc_msc_freertos/src/main.c | 2 +- examples/device/cdc_uac2/src/main.c | 2 +- examples/device/dfu/src/main.c | 2 +- examples/device/dfu_runtime/src/main.c | 2 +- examples/device/dynamic_configuration/src/main.c | 2 +- examples/device/hid_boot_interface/src/main.c | 2 +- examples/device/hid_composite/src/main.c | 2 +- examples/device/hid_composite_freertos/src/main.c | 2 +- examples/device/hid_generic_inout/src/main.c | 2 +- examples/device/hid_multiple_interface/src/main.c | 2 +- examples/device/midi_test/src/main.c | 2 +- examples/device/msc_dual_lun/src/main.c | 2 +- examples/device/net_lwip_webserver/src/main.c | 2 +- examples/device/uac2_headset/src/main.c | 2 +- examples/device/uac2_speaker_fb/src/main.c | 2 +- examples/device/usbtmc/src/main.c | 2 +- examples/device/video_capture/src/main.c | 4 +- examples/device/video_capture_2ch/src/main.c | 4 +- examples/device/webusb_serial/src/main.c | 2 +- examples/dual/host_hid_to_device_cdc/src/main.c | 4 +- examples/dual/host_info_to_device_cdc/src/main.c | 4 +- examples/host/bare_api/src/main.c | 2 +- examples/host/cdc_msc_hid/src/main.c | 2 +- examples/host/cdc_msc_hid_freertos/src/main.c | 2 +- examples/host/device_info/CMakeLists.txt | 8 +-- examples/host/device_info/only.txt | 4 +- examples/host/device_info/src/main.c | 2 +- examples/host/hid_controller/src/main.c | 2 +- examples/host/msc_file_explorer/src/main.c | 2 +- hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake | 1 + hw/bsp/imxrt/family.c | 28 +--------- hw/bsp/lpc18/family.c | 33 +----------- hw/bsp/lpc43/family.c | 46 +++-------------- hw/bsp/lpc54/family.c | 20 ++------ hw/bsp/lpc55/family.c | 20 ++------ hw/bsp/mcx/family.c | 26 ++-------- hw/bsp/ra/family.c | 36 ++----------- hw/bsp/rp2040/family.c | 4 +- hw/bsp/stm32f4/boards/stm32f412disco/board.cmake | 1 + hw/bsp/stm32f4/family.c | 4 +- hw/bsp/stm32h7/family.c | 32 +++++------- src/common/tusb_types.h | 6 +++ src/common/tusb_verify.h | 6 +-- src/device/usbd.c | 2 +- src/host/usbh.c | 2 +- src/host/usbh.h | 5 +- src/tusb.c | 60 +++++++++++++++++++--- src/tusb.h | 26 ++++++++-- test/unit-test/test/device/msc/test_msc_device.c | 2 +- test/unit-test/test/device/usbd/test_usbd.c | 2 +- 59 files changed, 187 insertions(+), 281 deletions(-) (limited to 'hw') diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst index 3db3fa206..ac4ab6392 100644 --- a/docs/reference/getting_started.rst +++ b/docs/reference/getting_started.rst @@ -12,22 +12,19 @@ It is relatively simple to incorporate tinyusb to your project * Add *your_project/tinyusb/src* to your include path. Also make sure your current include path also contains the configuration file tusb_config.h. * Make sure all required macros are all defined properly in tusb_config.h (configure file in demo application is sufficient, but you need to add a few more such as CFG_TUSB_MCU, CFG_TUSB_OS since they are passed by IDE/compiler to maintain a unique configure for all boards). * If you use the device stack, make sure you have created/modified usb descriptors for your own need. Ultimately you need to implement all **tud descriptor** callbacks for the stack to work. -* Add tusb_init() call to your reset initialization code. -* Call ``tud_int_handler()`` (device) and/or ``tuh_int_handler()`` (host) in your USB IRQ Handler +* Add tusb_init(rhport, role) call to your reset initialization code. +* Call ``tusb_int_handler(rhport, in_isr)`` in your USB IRQ Handler * Implement all enabled classes's callbacks. * If you don't use any RTOSes at all, you need to continuously and/or periodically call tud_task()/tuh_task() function. All of the callbacks and functionality are handled and invoked within the call of that task runner. .. code-block:: - int main(void) - { + int main(void) { your_init_code(); - tusb_init(); // initialize tinyusb stack + tusb_init(0, TUSB_ROLE_DEVICE); // initialize device stack on roothub port 0 - while(1) // the mainloop - { + while(1) { // the mainloop your_application_code(); - tud_task(); // device task tuh_task(); // host task } diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c index 10e6fe88a..6c75d95bf 100644 --- a/examples/device/audio_4_channel_mic/src/main.c +++ b/examples/device/audio_4_channel_mic/src/main.c @@ -86,7 +86,7 @@ int main(void) board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/audio_4_channel_mic_freertos/src/main.c b/examples/device/audio_4_channel_mic_freertos/src/main.c index 08f49326c..d24113df6 100644 --- a/examples/device/audio_4_channel_mic_freertos/src/main.c +++ b/examples/device/audio_4_channel_mic_freertos/src/main.c @@ -209,7 +209,7 @@ void usb_device_task(void* param) // init device stack on configured roothub port // This should be called after scheduler/kernel is started. // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c index f79bb4468..9702060e0 100644 --- a/examples/device/audio_test/src/main.c +++ b/examples/device/audio_test/src/main.c @@ -79,7 +79,7 @@ int main(void) board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/audio_test_freertos/src/main.c b/examples/device/audio_test_freertos/src/main.c index a3751da40..3d9166263 100644 --- a/examples/device/audio_test_freertos/src/main.c +++ b/examples/device/audio_test_freertos/src/main.c @@ -156,7 +156,7 @@ void usb_device_task(void* param) // init device stack on configured roothub port // This should be called after scheduler/kernel is started. // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c index 2ff7f10bd..99b81f74d 100644 --- a/examples/device/audio_test_multi_rate/src/main.c +++ b/examples/device/audio_test_multi_rate/src/main.c @@ -97,7 +97,7 @@ int main(void) board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/board_test/src/tusb_config.h b/examples/device/board_test/src/tusb_config.h index 36eafe807..89c27d1c0 100644 --- a/examples/device/board_test/src/tusb_config.h +++ b/examples/device/board_test/src/tusb_config.h @@ -30,11 +30,6 @@ extern "C" { #endif -// board_test example is special example that doesn't enable device or host stack -// This can cause some TinyUSB API missing, this define hack to allow us to fill those API -// to pass the compilation process -#define tud_int_handler(x) - //-------------------------------------------------------------------- // COMMON CONFIGURATION //-------------------------------------------------------------------- diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c index ef12186f2..07f41371a 100644 --- a/examples/device/cdc_dual_ports/src/main.c +++ b/examples/device/cdc_dual_ports/src/main.c @@ -52,7 +52,7 @@ int main(void) { board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c index 4581a3bab..a1f178e2a 100644 --- a/examples/device/cdc_msc/src/main.c +++ b/examples/device/cdc_msc/src/main.c @@ -51,7 +51,7 @@ int main(void) { board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index 607d40270..b84b33a8c 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -132,7 +132,7 @@ static void usb_device_task(void *param) { // init device stack on configured roothub port // This should be called after scheduler/kernel is started. // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/cdc_uac2/src/main.c b/examples/device/cdc_uac2/src/main.c index 25b2cd9a5..a75ec1427 100644 --- a/examples/device/cdc_uac2/src/main.c +++ b/examples/device/cdc_uac2/src/main.c @@ -46,7 +46,7 @@ int main(void) board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); #if (CFG_TUSB_MCU == OPT_MCU_RP2040) stdio_init_all(); diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c index 81fc0a62c..5efec9d32 100644 --- a/examples/device/dfu/src/main.c +++ b/examples/device/dfu/src/main.c @@ -75,7 +75,7 @@ int main(void) board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c index 170dde932..c21034fc1 100644 --- a/examples/device/dfu_runtime/src/main.c +++ b/examples/device/dfu_runtime/src/main.c @@ -70,7 +70,7 @@ int main(void) board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c index b6409c8e1..bc9ab0b2b 100644 --- a/examples/device/dynamic_configuration/src/main.c +++ b/examples/device/dynamic_configuration/src/main.c @@ -57,7 +57,7 @@ int main(void) board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c index c2aef502d..351a60854 100644 --- a/examples/device/hid_boot_interface/src/main.c +++ b/examples/device/hid_boot_interface/src/main.c @@ -57,7 +57,7 @@ int main(void) board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c index dcf13079f..8f7873ee3 100644 --- a/examples/device/hid_composite/src/main.c +++ b/examples/device/hid_composite/src/main.c @@ -58,7 +58,7 @@ int main(void) board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c index 2bd545bc2..d1842368b 100644 --- a/examples/device/hid_composite_freertos/src/main.c +++ b/examples/device/hid_composite_freertos/src/main.c @@ -136,7 +136,7 @@ void usb_device_task(void* param) // init device stack on configured roothub port // This should be called after scheduler/kernel is started. // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c index cfa9f6283..03de8bfee 100644 --- a/examples/device/hid_generic_inout/src/main.c +++ b/examples/device/hid_generic_inout/src/main.c @@ -81,7 +81,7 @@ int main(void) board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/hid_multiple_interface/src/main.c b/examples/device/hid_multiple_interface/src/main.c index 30b4ae055..0b7544fe0 100644 --- a/examples/device/hid_multiple_interface/src/main.c +++ b/examples/device/hid_multiple_interface/src/main.c @@ -62,7 +62,7 @@ int main(void) board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c index b1d51598f..84ca1d944 100644 --- a/examples/device/midi_test/src/main.c +++ b/examples/device/midi_test/src/main.c @@ -63,7 +63,7 @@ int main(void) board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c index aabd0bf8a..9b0930ce0 100644 --- a/examples/device/msc_dual_lun/src/main.c +++ b/examples/device/msc_dual_lun/src/main.c @@ -54,7 +54,7 @@ int main(void) { board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c index 791e09b4f..dbd7746b0 100644 --- a/examples/device/net_lwip_webserver/src/main.c +++ b/examples/device/net_lwip_webserver/src/main.c @@ -216,7 +216,7 @@ int main(void) { board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c index c285211b8..73616109f 100644 --- a/examples/device/uac2_headset/src/main.c +++ b/examples/device/uac2_headset/src/main.c @@ -100,7 +100,7 @@ int main(void) board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/uac2_speaker_fb/src/main.c b/examples/device/uac2_speaker_fb/src/main.c index 0a8529a61..21c2ac24a 100644 --- a/examples/device/uac2_speaker_fb/src/main.c +++ b/examples/device/uac2_speaker_fb/src/main.c @@ -106,7 +106,7 @@ int main(void) board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c index 9d8f0783d..8dbded632 100644 --- a/examples/device/usbtmc/src/main.c +++ b/examples/device/usbtmc/src/main.c @@ -55,7 +55,7 @@ int main(void) board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index ddb51e03a..4b8877a2f 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -68,7 +68,7 @@ int main(void) { freertos_init_task(); #else // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); @@ -319,7 +319,7 @@ void usb_device_task(void *param) { // init device stack on configured roothub port // This should be called after scheduler/kernel is started. // Otherwise, it could cause kernel issue since USB IRQ handler does use RTOS queue API. - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/video_capture_2ch/src/main.c b/examples/device/video_capture_2ch/src/main.c index e8c2ec6b0..118ee669d 100644 --- a/examples/device/video_capture_2ch/src/main.c +++ b/examples/device/video_capture_2ch/src/main.c @@ -68,7 +68,7 @@ int main(void) { freertos_init_task(); #else // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); @@ -327,7 +327,7 @@ void usb_device_task(void *param) { // init device stack on configured roothub port // This should be called after scheduler/kernel is started. // Otherwise, it could cause kernel issue since USB IRQ handler does use RTOS queue API. - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c index bcc33f657..e809c6319 100644 --- a/examples/device/webusb_serial/src/main.c +++ b/examples/device/webusb_serial/src/main.c @@ -91,7 +91,7 @@ int main(void) { board_init(); // init device stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c index 0b4165e38..ce586201c 100644 --- a/examples/dual/host_hid_to_device_cdc/src/main.c +++ b/examples/dual/host_hid_to_device_cdc/src/main.c @@ -79,8 +79,8 @@ int main(void) { printf("TinyUSB Host HID <-> Device CDC Example\r\n"); // init device and host stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); - tuh_init(BOARD_TUH_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); + tusb_init(BOARD_TUH_RHPORT, TUSB_ROLE_HOST); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/dual/host_info_to_device_cdc/src/main.c b/examples/dual/host_info_to_device_cdc/src/main.c index 443cc4674..7a862f5ad 100644 --- a/examples/dual/host_info_to_device_cdc/src/main.c +++ b/examples/dual/host_info_to_device_cdc/src/main.c @@ -82,8 +82,8 @@ int main(void) { printf("TinyUSB Host Information -> Device CDC Example\r\n"); // init device and host stack on configured roothub port - tud_init(BOARD_TUD_RHPORT); - tuh_init(BOARD_TUH_RHPORT); + tusb_init(BOARD_TUD_RHPORT, TUSB_ROLE_DEVICE); + tusb_init(BOARD_TUH_RHPORT, TUSB_ROLE_HOST); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c index ae574c078..f248dd28d 100644 --- a/examples/host/bare_api/src/main.c +++ b/examples/host/bare_api/src/main.c @@ -62,7 +62,7 @@ int main(void) printf("TinyUSB Bare API Example\r\n"); // init host stack on configured roothub port - tuh_init(BOARD_TUH_RHPORT); + tusb_init(BOARD_TUH_RHPORT, TUSB_ROLE_HOST); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c index a3b80e030..65f7b5201 100644 --- a/examples/host/cdc_msc_hid/src/main.c +++ b/examples/host/cdc_msc_hid/src/main.c @@ -50,7 +50,7 @@ int main(void) { printf("TinyUSB Host CDC MSC HID Example\r\n"); // init host stack on configured roothub port - tuh_init(BOARD_TUH_RHPORT); + tusb_init(BOARD_TUH_RHPORT, TUSB_ROLE_HOST); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c index fa799aede..2116e6dcf 100644 --- a/examples/host/cdc_msc_hid_freertos/src/main.c +++ b/examples/host/cdc_msc_hid_freertos/src/main.c @@ -126,7 +126,7 @@ static void usb_host_task(void *param) { (void) param; // init host stack on configured roothub port - if (!tuh_init(BOARD_TUH_RHPORT)) { + if (!tusb_init(BOARD_TUH_RHPORT, TUSB_ROLE_HOST)) { printf("Failed to init USB Host Stack\r\n"); vTaskSuspend(NULL); } diff --git a/examples/host/device_info/CMakeLists.txt b/examples/host/device_info/CMakeLists.txt index 76182d6fa..6a16155ec 100644 --- a/examples/host/device_info/CMakeLists.txt +++ b/examples/host/device_info/CMakeLists.txt @@ -19,13 +19,13 @@ add_executable(${PROJECT}) # Example source target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ) # Example include target_include_directories(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) # Configure compilation flags and libraries for the example without RTOS. # See the corresponding function in hw/bsp/FAMILY/family.cmake for details. diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt index fee10f9e2..b3f4468bb 100644 --- a/examples/host/device_info/only.txt +++ b/examples/host/device_info/only.txt @@ -4,11 +4,11 @@ mcu:LPC177X_8X mcu:LPC18XX mcu:LPC40XX mcu:LPC43XX +mcu:MAX3421 mcu:MIMXRT1XXX mcu:MIMXRT10XX mcu:MIMXRT11XX -mcu:RP2040 mcu:MSP432E4 +mcu:RP2040 mcu:RX65X mcu:RAXXX -mcu:MAX3421 diff --git a/examples/host/device_info/src/main.c b/examples/host/device_info/src/main.c index 18beea663..55d685a5d 100644 --- a/examples/host/device_info/src/main.c +++ b/examples/host/device_info/src/main.c @@ -66,7 +66,7 @@ int main(void) { printf("TinyUSB Device Info Example\r\n"); // init host stack on configured roothub port - tuh_init(BOARD_TUH_RHPORT); + tusb_init(BOARD_TUH_RHPORT, TUSB_ROLE_HOST); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c index 05a5ae176..76b686683 100644 --- a/examples/host/hid_controller/src/main.c +++ b/examples/host/hid_controller/src/main.c @@ -52,7 +52,7 @@ int main(void) printf("Note: Events only displayed for explicit supported controllers\r\n"); // init host stack on configured roothub port - tuh_init(BOARD_TUH_RHPORT); + tusb_init(BOARD_TUH_RHPORT, TUSB_ROLE_HOST); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c index f6b6810f5..3af079b0e 100644 --- a/examples/host/msc_file_explorer/src/main.c +++ b/examples/host/msc_file_explorer/src/main.c @@ -78,7 +78,7 @@ int main(void) { printf("TinyUSB Host MassStorage Explorer Example\r\n"); // init host stack on configured roothub port - tuh_init(BOARD_TUH_RHPORT); + tusb_init(BOARD_TUH_RHPORT, TUSB_ROLE_HOST); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake index fd335cdf5..f70a5f923 100644 --- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.cmake @@ -1,6 +1,7 @@ set(MCU_VARIANT MIMXRT1062) set(JLINK_DEVICE MIMXRT1062xxx6A) +#set(JLINK_OPTION "-USB 000726129165") set(PYOCD_TARGET mimxrt1060) set(NXPLINK_DEVICE MIMXRT1062xxxxA:EVK-MIMXRT1060) diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index 2f305aa4d..6087ee37d 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -46,18 +46,6 @@ #pragma GCC diagnostic pop #endif -#if defined(BOARD_TUD_RHPORT) && CFG_TUD_ENABLED - #define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n) -#else - #define PORT_SUPPORT_DEVICE(_n) 0 -#endif - -#if defined(BOARD_TUH_RHPORT) && CFG_TUH_ENABLED - #define PORT_SUPPORT_HOST(_n) (BOARD_TUH_RHPORT == _n) -#else - #define PORT_SUPPORT_HOST(_n) 0 -#endif - // needed by fsl_flexspi_nor_boot TU_ATTR_USED const uint8_t dcd_data[] = { 0x00 }; @@ -156,23 +144,11 @@ void board_init(void) // USB Interrupt Handler //--------------------------------------------------------------------+ void USB_OTG1_IRQHandler(void) { - #if PORT_SUPPORT_DEVICE(0) - tud_int_handler(0); - #endif - - #if PORT_SUPPORT_HOST(0) - tuh_int_handler(0, true); - #endif + tusb_int_handler(0, true); } void USB_OTG2_IRQHandler(void) { - #if PORT_SUPPORT_DEVICE(1) - tud_int_handler(1); - #endif - - #if PORT_SUPPORT_HOST(1) - tuh_int_handler(1, true); - #endif + tusb_int_handler(1, true); } //--------------------------------------------------------------------+ diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c index e6abecb4b..55ef31ee4 100644 --- a/hw/bsp/lpc18/family.c +++ b/hw/bsp/lpc18/family.c @@ -28,39 +28,15 @@ #include "bsp/board_api.h" #include "board.h" -#ifdef BOARD_TUD_RHPORT - #define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n) -#else - #define PORT_SUPPORT_DEVICE(_n) 0 -#endif - -#ifdef BOARD_TUH_RHPORT - #define PORT_SUPPORT_HOST(_n) (BOARD_TUH_RHPORT == _n) -#else - #define PORT_SUPPORT_HOST(_n) 0 -#endif - //--------------------------------------------------------------------+ // USB Interrupt Handler //--------------------------------------------------------------------+ void USB0_IRQHandler(void) { - #if PORT_SUPPORT_DEVICE(0) - tud_int_handler(0); - #endif - - #if PORT_SUPPORT_HOST(0) - tuh_int_handler(0, true); - #endif + tusb_int_handler(0, true); } void USB1_IRQHandler(void) { - #if PORT_SUPPORT_DEVICE(1) - tud_int_handler(1); - #endif - - #if PORT_SUPPORT_HOST(1) - tuh_int_handler(1, true); - #endif + tusb_int_handler(1, true); } //--------------------------------------------------------------------+ @@ -118,13 +94,8 @@ void board_init(void) { Chip_UART_TXEnable(UART_DEV); //------------- USB -------------// -#if PORT_SUPPORT_DEVICE(0) || PORT_SUPPORT_HOST(0) Chip_USB0_Init(); -#endif - -#if PORT_SUPPORT_DEVICE(1) || PORT_SUPPORT_HOST(1) Chip_USB1_Init(); -#endif } //--------------------------------------------------------------------+ diff --git a/hw/bsp/lpc43/family.c b/hw/bsp/lpc43/family.c index 8be729f7d..dfee9f5ea 100644 --- a/hw/bsp/lpc43/family.c +++ b/hw/bsp/lpc43/family.c @@ -39,18 +39,6 @@ #include "bsp/board_api.h" #include "board.h" -#ifdef BOARD_TUD_RHPORT - #define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n) -#else - #define PORT_SUPPORT_DEVICE(_n) 0 -#endif - -#ifdef BOARD_TUH_RHPORT - #define PORT_SUPPORT_HOST(_n) (BOARD_TUH_RHPORT == _n) -#else - #define PORT_SUPPORT_HOST(_n) 0 -#endif - /* System configuration variables used by chip driver */ const uint32_t OscRateIn = 12000000; const uint32_t ExtRateIn = 0; @@ -161,9 +149,7 @@ void board_init(void) * - Insert jumpers in position 2-3 in JP17/JP18/JP19 * - Insert jumpers in JP31 (OTG) */ -#if PORT_SUPPORT_DEVICE(0) || PORT_SUPPORT_HOST(0) Chip_USB0_Init(); -#endif /* From EA4357 user manual * @@ -186,17 +172,15 @@ void board_init(void) * - LED34 lights green when +5V is available on J20. * - JP15 shall not be inserted. JP16 has no effect */ -#if PORT_SUPPORT_DEVICE(1) || PORT_SUPPORT_HOST(1) Chip_USB1_Init(); -#endif // USB0 Vbus Power: P2_3 on EA4357 channel B U20 GPIO26 active low (base board) Chip_SCU_PinMuxSet(2, 3, SCU_MODE_PULLUP | SCU_MODE_INBUFF_EN | SCU_MODE_FUNC7); - #if PORT_SUPPORT_DEVICE(0) - // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low. - Chip_SCU_PinMuxSet(9, 5, SCU_MODE_PULLDOWN | SCU_MODE_FUNC4); - Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 18); + #if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0 + // P9_5 (GPIO5[18]) (GPIO28 on oem base) as USB connect, active low. + Chip_SCU_PinMuxSet(9, 5, SCU_MODE_PULLDOWN | SCU_MODE_FUNC4); + Chip_GPIO_SetPinDIROutput(LPC_GPIO_PORT, 5, 18); #endif // USB1 Power: EA4357 channel A U20 is enabled by SJ5 connected to pad 1-2, no more action required @@ -206,26 +190,12 @@ void board_init(void) //--------------------------------------------------------------------+ // USB Interrupt Handler //--------------------------------------------------------------------+ -void USB0_IRQHandler(void) -{ - #if PORT_SUPPORT_DEVICE(0) - tud_int_handler(0); - #endif - - #if PORT_SUPPORT_HOST(0) - tuh_int_handler(0, true); - #endif +void USB0_IRQHandler(void) { + tusb_int_handler(0, true); } -void USB1_IRQHandler(void) -{ - #if PORT_SUPPORT_DEVICE(1) - tud_int_handler(1); - #endif - - #if PORT_SUPPORT_HOST(1) - tuh_int_handler(1, true); - #endif +void USB1_IRQHandler(void) { + tusb_int_handler(1, true); } //--------------------------------------------------------------------+ diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c index 5e5732d74..5e6ff2231 100644 --- a/hw/bsp/lpc54/family.c +++ b/hw/bsp/lpc54/family.c @@ -33,18 +33,6 @@ #include "bsp/board_api.h" #include "board.h" -#ifdef BOARD_TUD_RHPORT - #define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n) -#else - #define PORT_SUPPORT_DEVICE(_n) 0 -#endif - -#ifdef BOARD_TUH_RHPORT - #define PORT_SUPPORT_HOST(_n) (BOARD_TUH_RHPORT == _n) -#else - #define PORT_SUPPORT_HOST(_n) 0 -#endif - //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ @@ -71,11 +59,11 @@ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ void USB0_IRQHandler(void) { - tud_int_handler(0); + tusb_int_handler(0, true); } void USB1_IRQHandler(void) { - tud_int_handler(1); + tusb_int_handler(1, true); } /**************************************************************** @@ -160,7 +148,7 @@ void board_init(void) { #if defined(FSL_FEATURE_SOC_USBHSD_COUNT) && FSL_FEATURE_SOC_USBHSD_COUNT // LPC546xx and LPC540xx has OTG 1 FS + 1 HS rhports - #if PORT_SUPPORT_DEVICE(0) + #if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0 // Port0 is Full Speed POWER_DisablePD(kPDRUNCFG_PD_USB0_PHY); /*< Turn on USB Phy */ CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1, false); @@ -174,7 +162,7 @@ void board_init(void) { CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbSrcFro, CLOCK_GetFroHfFreq()); #endif - #if PORT_SUPPORT_DEVICE(1) + #if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 1 // Port1 is High Speed POWER_DisablePD(kPDRUNCFG_PD_USB1_PHY); diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c index 075832ea7..68ccf52d5 100644 --- a/hw/bsp/lpc55/family.c +++ b/hw/bsp/lpc55/family.c @@ -37,18 +37,6 @@ #include "sct_neopixel.h" #endif -#ifdef BOARD_TUD_RHPORT - #define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n) -#else - #define PORT_SUPPORT_DEVICE(_n) 0 -#endif - -#ifdef BOARD_TUH_RHPORT - #define PORT_SUPPORT_HOST(_n) (BOARD_TUH_RHPORT == _n) -#else - #define PORT_SUPPORT_HOST(_n) 0 -#endif - //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ @@ -73,11 +61,11 @@ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ void USB0_IRQHandler(void) { - tud_int_handler(0); + tusb_int_handler(0, true); } void USB1_IRQHandler(void) { - tud_int_handler(1); + tusb_int_handler(1, true); } /**************************************************************** @@ -209,7 +197,7 @@ void board_init(void) { /* PORT0 PIN22 configured as USB0_VBUS */ IOCON_PinMuxSet(IOCON, 0U, 22U, IOCON_PIO_DIG_FUNC7_EN); -#if PORT_SUPPORT_DEVICE(0) +#if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0 // Port0 is Full Speed /* Turn on USB0 Phy */ @@ -234,7 +222,7 @@ void board_init(void) { CLOCK_EnableUsbfs0DeviceClock(kCLOCK_UsbfsSrcFro, CLOCK_GetFreq(kCLOCK_FroHf)); #endif -#if PORT_SUPPORT_DEVICE(1) +#if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 1 // Port1 is High Speed /* Turn on USB1 Phy */ diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c index cc675a49d..ce54097fe 100644 --- a/hw/bsp/mcx/family.c +++ b/hw/bsp/mcx/family.c @@ -33,39 +33,23 @@ #include "pin_mux.h" #include "clock_config.h" -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM -//--------------------------------------------------------------------+ - -#ifdef BOARD_TUD_RHPORT - #define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n) -#else - #define PORT_SUPPORT_DEVICE(_n) 0 -#endif - -#ifdef BOARD_TUH_RHPORT - #define PORT_SUPPORT_HOST(_n) (BOARD_TUH_RHPORT == _n) -#else - #define PORT_SUPPORT_HOST(_n) 0 -#endif - //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ #if CFG_TUSB_MCU == OPT_MCU_MCXN9 void USB0_FS_IRQHandler(void) { - tud_int_handler(0); + tusb_int_handler(0, true); } void USB1_HS_IRQHandler(void) { - tud_int_handler(1); + tusb_int_handler(1, true); } #elif CFG_TUSB_MCU == OPT_MCU_MCXA15 void USB0_IRQHandler(void) { - tud_int_handler(0); + tusb_int_handler(0, true); } #endif @@ -133,7 +117,7 @@ void board_init(void) { // USB VBUS /* PORT0 PIN22 configured as USB0_VBUS */ -#if PORT_SUPPORT_DEVICE(0) +#if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 0 // Port0 is Full Speed #if CFG_TUSB_MCU == OPT_MCU_MCXA15 @@ -147,7 +131,7 @@ void board_init(void) { CLOCK_EnableUsbfsClock(); #endif -#if PORT_SUPPORT_DEVICE(1) && (CFG_TUSB_MCU == OPT_MCU_MCXN9) +#if defined(BOARD_TUD_RHPORT) && BOARD_TUD_RHPORT == 1 && (CFG_TUSB_MCU == OPT_MCU_MCXN9) // Port1 is High Speed // Power diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index a8b4ebcc7..87f7b4a22 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -182,43 +182,19 @@ uint32_t board_millis(void) { // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ -#if CFG_TUD_ENABLED && defined(BOARD_TUD_RHPORT) - #define PORT_SUPPORT_DEVICE(_n) (BOARD_TUD_RHPORT == _n) -#else - #define PORT_SUPPORT_DEVICE(_n) 0 -#endif - -#if CFG_TUH_ENABLED && defined(BOARD_TUH_RHPORT) - #define PORT_SUPPORT_HOST(_n) (BOARD_TUH_RHPORT == _n) -#else - #define PORT_SUPPORT_HOST(_n) 0 -#endif - //------------- USB0 FullSpeed -------------// void usbfs_interrupt_handler(void) { IRQn_Type irq = R_FSP_CurrentIrqGet(); R_BSP_IrqStatusClear(irq); - #if PORT_SUPPORT_HOST(0) - tuh_int_handler(0, true); - #endif - - #if PORT_SUPPORT_DEVICE(0) - tud_int_handler(0); - #endif + tusb_int_handler(0, true); } void usbfs_resume_handler(void) { IRQn_Type irq = R_FSP_CurrentIrqGet(); R_BSP_IrqStatusClear(irq); - #if PORT_SUPPORT_HOST(0) - tuh_int_handler(0, true); - #endif - - #if PORT_SUPPORT_DEVICE(0) - tud_int_handler(0); - #endif + tusb_int_handler(0, true); } void usbfs_d0fifo_handler(void) { @@ -240,13 +216,7 @@ void usbhs_interrupt_handler(void) { IRQn_Type irq = R_FSP_CurrentIrqGet(); R_BSP_IrqStatusClear(irq); - #if PORT_SUPPORT_HOST(1) - tuh_int_handler(1, true); - #endif - - #if PORT_SUPPORT_DEVICE(1) - tud_int_handler(1); - #endif + tusb_int_handler(1, true); } void usbhs_d0fifo_handler(void) { diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c index 64a3a0af6..ccc1e1f70 100644 --- a/hw/bsp/rp2040/family.c +++ b/hw/bsp/rp2040/family.c @@ -205,7 +205,9 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) { pico_get_unique_board_id(&pico_id); size_t len = PICO_UNIQUE_BOARD_ID_SIZE_BYTES; - if (len > max_len) len = max_len; + if (len > max_len) { + len = max_len; + } memcpy(id, pico_id.id, len); return len; diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/board.cmake b/hw/bsp/stm32f4/boards/stm32f412disco/board.cmake index f9e834409..c282af98e 100644 --- a/hw/bsp/stm32f4/boards/stm32f412disco/board.cmake +++ b/hw/bsp/stm32f4/boards/stm32f412disco/board.cmake @@ -1,5 +1,6 @@ set(MCU_VARIANT stm32f412zx) set(JLINK_DEVICE stm32f412zg) +# set(JLINK_OPTION "-USB 000771775987") set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F412ZGTx_FLASH.ld) diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c index fb0347aba..b4a661421 100644 --- a/hw/bsp/stm32f4/family.c +++ b/hw/bsp/stm32f4/family.c @@ -32,11 +32,11 @@ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ void OTG_FS_IRQHandler(void) { - tud_int_handler(0); + tusb_int_handler(0, true); } void OTG_HS_IRQHandler(void) { - tud_int_handler(1); + tusb_int_handler(1, true); } //--------------------------------------------------------------------+ diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c index c81437958..6e4b388d6 100644 --- a/hw/bsp/stm32h7/family.c +++ b/hw/bsp/stm32h7/family.c @@ -35,6 +35,12 @@ TU_ATTR_UNUSED static void Error_Handler(void) { #include "board.h" +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ + +UART_HandleTypeDef UartHandle; + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ @@ -42,26 +48,15 @@ TU_ATTR_UNUSED static void Error_Handler(void) { // Despite being call USB2_OTG_FS on some MCUs // OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port void OTG_FS_IRQHandler(void) { - tud_int_handler(0); + tusb_int_handler(0, true); } // Despite being call USB1_OTG_HS on some MCUs // OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port void OTG_HS_IRQHandler(void) { - tud_int_handler(1); + tusb_int_handler(1, true); } - -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM -//--------------------------------------------------------------------+ - -UART_HandleTypeDef UartHandle; - -//--------------------------------------------------------------------+ -// -//--------------------------------------------------------------------+ - #ifdef TRACE_ETM void trace_etm_init(void) { // H7 trace pin is PE2 to PE6 @@ -111,9 +106,10 @@ void board_init(void) { SysTick->CTRL &= ~1U; // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) -#ifdef USB_OTG_FS_PERIPH_BASE + #ifdef USB_OTG_FS_PERIPH_BASE NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); -#endif + #endif + NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); #endif @@ -206,13 +202,11 @@ void board_init(void) { struct { GPIO_TypeDef* port; uint32_t pin; - } const ulpi_pins[] = - { + } const ulpi_pins[] = { ULPI_PINS }; - for (uint8_t i=0; i < sizeof(ulpi_pins)/sizeof(ulpi_pins[0]); i++) - { + for (uint8_t i=0; i < sizeof(ulpi_pins)/sizeof(ulpi_pins[0]); i++) { GPIO_InitStruct.Pin = ulpi_pins[i].pin; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 1501a5af6..adf4b5720 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -39,6 +39,12 @@ /* CONSTANTS *------------------------------------------------------------------*/ +typedef enum { + TUSB_ROLE_INVALID = 0, + TUSB_ROLE_DEVICE, + TUSB_ROLE_HOST, +} tusb_role_t; + /// defined base on EHCI specs value for Endpoint Speed typedef enum { TUSB_SPEED_FULL = 0, diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h index 4344575b7..8ad218b03 100644 --- a/src/common/tusb_verify.h +++ b/src/common/tusb_verify.h @@ -94,7 +94,7 @@ #endif // Helper to implement optional parameter for TU_VERIFY Macro family -#define _GET_3RD_ARG(arg1, arg2, arg3, ...) arg3 +#define TU_GET_3RD_ARG(arg1, arg2, arg3, ...) arg3 /*------------------------------------------------------------------*/ /* TU_VERIFY @@ -109,7 +109,7 @@ #define TU_VERIFY_1ARGS(_cond) TU_VERIFY_DEFINE(_cond, false) #define TU_VERIFY_2ARGS(_cond, _ret) TU_VERIFY_DEFINE(_cond, _ret) -#define TU_VERIFY(...) _GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_2ARGS, TU_VERIFY_1ARGS, _dummy)(__VA_ARGS__) +#define TU_VERIFY(...) TU_GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_2ARGS, TU_VERIFY_1ARGS, _dummy)(__VA_ARGS__) /*------------------------------------------------------------------*/ /* ASSERT @@ -126,7 +126,7 @@ #define TU_ASSERT_2ARGS(_cond, _ret) TU_ASSERT_DEFINE(_cond, _ret) #ifndef TU_ASSERT -#define TU_ASSERT(...) _GET_3RD_ARG(__VA_ARGS__, TU_ASSERT_2ARGS, TU_ASSERT_1ARGS, _dummy)(__VA_ARGS__) +#define TU_ASSERT(...) TU_GET_3RD_ARG(__VA_ARGS__, TU_ASSERT_2ARGS, TU_ASSERT_1ARGS, _dummy)(__VA_ARGS__) #endif #ifdef __cplusplus diff --git a/src/device/usbd.c b/src/device/usbd.c index 67faf0da7..6fe7e416e 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -557,7 +557,7 @@ bool tud_task_event_ready(void) { * int main(void) { application_init(); - tusb_init(); + tusb_init(0, TUSB_ROLE_DEVICE); while(1) { // the mainloop application_code(); diff --git a/src/host/usbh.c b/src/host/usbh.c index 8c488aaa2..ed253ffcc 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -459,7 +459,7 @@ bool tuh_task_event_ready(void) { int main(void) { application_init(); - tusb_init(); + tusb_init(0, TUSB_ROLE_HOST); while(1) // the mainloop { diff --git a/src/host/usbh.h b/src/host/usbh.h index d0a5732e5..217cb1a9c 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -149,12 +149,9 @@ extern void hcd_int_handler(uint8_t rhport, bool in_isr); #endif // Interrupt handler alias to HCD with in_isr as optional parameter -// - tuh_int_handler(rhport) --> hcd_int_handler(rhport, true) -// - tuh_int_handler(rhport, in_isr) --> hcd_int_handler(rhport, in_isr) -// Note: this is similar to TU_VERIFY(), _GET_3RD_ARG() is defined in tusb_verify.h #define _tuh_int_handler_1arg(_rhport) hcd_int_handler(_rhport, true) #define _tuh_int_hanlder_2arg(_rhport, _in_isr) hcd_int_handler(_rhport, _in_isr) -#define tuh_int_handler(...) _GET_3RD_ARG(__VA_ARGS__, _tuh_int_hanlder_2arg, _tuh_int_handler_1arg, _dummy)(__VA_ARGS__) +#define tuh_int_handler(...) TU_GET_3RD_ARG(__VA_ARGS__, _tuh_int_hanlder_2arg, _tuh_int_handler_1arg, _dummy)(__VA_ARGS__) // Check if roothub port is initialized and active as a host bool tuh_rhport_is_active(uint8_t rhport); diff --git a/src/tusb.c b/src/tusb.c index 11690b203..9f0e45fef 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -39,21 +39,50 @@ #include "host/usbh_pvt.h" #endif +#define TUP_USBIP_CONTROLLER_NUM 2 + +static tusb_role_t _rhport_role[TUP_USBIP_CONTROLLER_NUM] = { 0 }; + //--------------------------------------------------------------------+ // Public API //--------------------------------------------------------------------+ -bool tusb_init(void) { - #if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT) - // init device stack CFG_TUSB_RHPORTx_MODE must be defined - TU_ASSERT ( tud_init(TUD_OPT_RHPORT) ); +bool _tusb_rhport_init(uint8_t rhport, tusb_role_t role) { + // backward compatible called with tusb_init(void) + #if defined(TUD_OPT_RHPORT) || defined(TUH_OPT_RHPORT) + if (rhport == 0xff || role == TUSB_ROLE_INVALID) { + #if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT) + // init device stack CFG_TUSB_RHPORTx_MODE must be defined + TU_ASSERT ( tud_init(TUD_OPT_RHPORT) ); + _rhport_role[TUD_OPT_RHPORT] = TUSB_ROLE_DEVICE; + #endif + + #if CFG_TUH_ENABLED && defined(TUH_OPT_RHPORT) + // init host stack CFG_TUSB_RHPORTx_MODE must be defined + TU_ASSERT( tuh_init(TUH_OPT_RHPORT) ); + _rhport_role[TUH_OPT_RHPORT] = TUSB_ROLE_HOST; + #endif + + return true; + } + #endif + + // new API with explicit rhport and role + TU_ASSERT(rhport < TUP_USBIP_CONTROLLER_NUM && role != TUSB_ROLE_INVALID); + + #if CFG_TUD_ENABLED + if (role == TUSB_ROLE_DEVICE) { + TU_ASSERT( tud_init(rhport) ); + } #endif - #if CFG_TUH_ENABLED && defined(TUH_OPT_RHPORT) - // init host stack CFG_TUSB_RHPORTx_MODE must be defined - TU_ASSERT( tuh_init(TUH_OPT_RHPORT) ); + #if CFG_TUH_ENABLED + if (role == TUSB_ROLE_HOST) { + TU_ASSERT( tuh_init(rhport) ); + } #endif + _rhport_role[rhport] = role; return true; } @@ -71,6 +100,23 @@ bool tusb_inited(void) { return ret; } +void tusb_int_handler(uint8_t rhport, bool in_isr) { + TU_VERIFY(rhport < TUP_USBIP_CONTROLLER_NUM,); + + #if CFG_TUD_ENABLED + if (_rhport_role[rhport] == TUSB_ROLE_DEVICE) { + (void) in_isr; + tud_int_handler(rhport); + } + #endif + + #if CFG_TUH_ENABLED + if (_rhport_role[rhport] == TUSB_ROLE_HOST) { + tuh_int_handler(rhport, in_isr); + } + #endif +} + //--------------------------------------------------------------------+ // Descriptor helper //--------------------------------------------------------------------+ diff --git a/src/tusb.h b/src/tusb.h index 4f69a1414..911d1bae0 100644 --- a/src/tusb.h +++ b/src/tusb.h @@ -129,18 +129,38 @@ //--------------------------------------------------------------------+ // APPLICATION API //--------------------------------------------------------------------+ +#if CFG_TUH_ENABLED || CFG_TUD_ENABLED -// Initialize device/host stack +// Internal helper for backward compatible with tusb_init(void) +bool _tusb_rhport_init(uint8_t rhport, tusb_role_t role); + +// Initialize roothub port with device/host role // Note: when using with RTOS, this should be called after scheduler/kernel is started. -// Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. -bool tusb_init(void); +// Otherwise, it could cause kernel issue since USB IRQ handler does use RTOS queue API. +// Note2: defined as macro for backward compatible with tusb_init(void), can be changed to function in the future. +#define _tusb_init_0arg() _tusb_rhport_init(0xff, TUSB_ROLE_INVALID) +#define _tusb_init_1arg(_rhport) _tusb_rhport_init(_rhport, TUSB_ROLE_INVALID) +#define _tusb_init_2arg(_rhport, _role) _tusb_rhport_init(_rhport, _role) +#define tusb_init(...) TU_GET_3RD_ARG(__VA_ARGS__, _tusb_init_2arg, _tusb_init_1arg, _tusb_init_0arg)(__VA_ARGS__) // Check if stack is initialized bool tusb_inited(void); +// Called to handle usb interrupt/event. tusb_init(rhport, role) must be called before +void tusb_int_handler(uint8_t rhport, bool in_isr); + // TODO // bool tusb_teardown(void); +#else + +#define tusb_init(...) (false) +#define tusb_int_handler(...) do {}while(0) +#define tusb_inited() (false) + +#endif + + #ifdef __cplusplus } #endif diff --git a/test/unit-test/test/device/msc/test_msc_device.c b/test/unit-test/test/device/msc/test_msc_device.c index a62418524..28216af10 100644 --- a/test/unit-test/test/device/msc/test_msc_device.c +++ b/test/unit-test/test/device/msc/test_msc_device.c @@ -200,7 +200,7 @@ void setUp(void) if ( !tud_inited() ) { dcd_init_Expect(rhport); - tusb_init(); + tusb_init(0, TUSB_ROLE_DEVICE); } dcd_event_bus_reset(rhport, TUSB_SPEED_HIGH, false); diff --git a/test/unit-test/test/device/usbd/test_usbd.c b/test/unit-test/test/device/usbd/test_usbd.c index 00950c5a9..43722d175 100644 --- a/test/unit-test/test/device/usbd/test_usbd.c +++ b/test/unit-test/test/device/usbd/test_usbd.c @@ -128,7 +128,7 @@ void setUp(void) { mscd_init_Expect(); dcd_init_Expect(rhport); - tusb_init(); + tusb_init(0, TUSB_ROLE_DEVICE); } } -- cgit v1.3.1 From 10a3aa3cc8f58a783d2109f5a6c9a4012992f982 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 15 Oct 2024 13:03:12 +0700 Subject: adding hcd dwc2 --- examples/dual/host_hid_to_device_cdc/only.txt | 1 + examples/dual/host_info_to_device_cdc/only.txt | 1 + examples/host/device_info/only.txt | 1 + hw/bsp/stm32h7/family.c | 7 +- hw/bsp/stm32h7/family.cmake | 2 + src/portable/synopsys/dwc2/dcd_dwc2.c | 194 +----------------------- src/portable/synopsys/dwc2/dwc2_common.c | 196 +++++++++++++++++++++++++ src/portable/synopsys/dwc2/dwc2_common.h | 70 +++++++++ src/portable/synopsys/dwc2/dwc2_type.h | 4 +- src/portable/synopsys/dwc2/hcd_dwc2.c | 167 +++++++++++++++++++++ 10 files changed, 447 insertions(+), 196 deletions(-) create mode 100644 src/portable/synopsys/dwc2/dwc2_common.c create mode 100644 src/portable/synopsys/dwc2/dwc2_common.h create mode 100644 src/portable/synopsys/dwc2/hcd_dwc2.c (limited to 'hw') diff --git a/examples/dual/host_hid_to_device_cdc/only.txt b/examples/dual/host_hid_to_device_cdc/only.txt index cfc87eb4e..149ece856 100644 --- a/examples/dual/host_hid_to_device_cdc/only.txt +++ b/examples/dual/host_hid_to_device_cdc/only.txt @@ -4,3 +4,4 @@ board:mcb1800 mcu:RP2040 mcu:ra6m5 mcu:MAX3421 +mcu:STM32H7 diff --git a/examples/dual/host_info_to_device_cdc/only.txt b/examples/dual/host_info_to_device_cdc/only.txt index cfc87eb4e..149ece856 100644 --- a/examples/dual/host_info_to_device_cdc/only.txt +++ b/examples/dual/host_info_to_device_cdc/only.txt @@ -4,3 +4,4 @@ board:mcb1800 mcu:RP2040 mcu:ra6m5 mcu:MAX3421 +mcu:STM32H7 diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt index b3f4468bb..a38fc251b 100644 --- a/examples/host/device_info/only.txt +++ b/examples/host/device_info/only.txt @@ -12,3 +12,4 @@ mcu:MSP432E4 mcu:RP2040 mcu:RX65X mcu:RAXXX +mcu:STM32H7 diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c index 6e4b388d6..3bed1f5ec 100644 --- a/hw/bsp/stm32h7/family.c +++ b/hw/bsp/stm32h7/family.c @@ -151,7 +151,7 @@ void board_init(void) { HAL_UART_Init(&UartHandle); #endif -#if BOARD_TUD_RHPORT == 0 + //------------- USB FS -------------// // Despite being call USB2_OTG // OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port // PA9 VUSB, PA10 ID, PA11 DM, PA12 DP @@ -195,10 +195,9 @@ void board_init(void) { USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; #endif // vbus sense -#elif BOARD_TUD_RHPORT == 1 + //------------- USB HS -------------// // Despite being call USB2_OTG // OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port - struct { GPIO_TypeDef* port; uint32_t pin; @@ -238,8 +237,6 @@ void board_init(void) { // For waveshare openh743 ULPI PHY reset walkaround board_stm32h7_post_init(); -#endif // rhport = 1 - } //--------------------------------------------------------------------+ diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake index 026c7c3df..e4161ffe5 100644 --- a/hw/bsp/stm32h7/family.cmake +++ b/hw/bsp/stm32h7/family.cmake @@ -106,6 +106,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_STM32H7 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index f30ec5ee3..a9b3770ee 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -35,45 +35,7 @@ #define DWC2_DEBUG 2 #include "device/dcd.h" -#include "dwc2_type.h" - -// Following symbols must be defined by port header -// - _dwc2_controller[]: array of controllers -// - DWC2_EP_MAX: largest EP counts of all controllers -// - dwc2_phy_init/dwc2_phy_update: phy init called before and after core reset -// - dwc2_dcd_int_enable/dwc2_dcd_int_disable -// - dwc2_remote_wakeup_delay - -#if defined(TUP_USBIP_DWC2_STM32) - #include "dwc2_stm32.h" -#elif defined(TUP_USBIP_DWC2_ESP32) - #include "dwc2_esp32.h" -#elif TU_CHECK_MCU(OPT_MCU_GD32VF103) - #include "dwc2_gd32.h" -#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837) - #include "dwc2_bcm.h" -#elif TU_CHECK_MCU(OPT_MCU_EFM32GG) - #include "dwc2_efm32.h" -#elif TU_CHECK_MCU(OPT_MCU_XMC4000) - #include "dwc2_xmc.h" -#else - #error "Unsupported MCUs" -#endif - -enum { - DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller) -}; - -// DWC2 registers -//#define DWC2_REG(_port) ((dwc2_regs_t*) _dwc2_controller[_port].reg_base) - -TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { - if (rhport >= DWC2_CONTROLLER_COUNT) { - // user mis-configured, ignore and use first controller - rhport = 0; - } - return (dwc2_regs_t*) _dwc2_controller[rhport].reg_base; -} +#include "dwc2_common.h" //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM @@ -511,162 +473,16 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c } } -/*------------------------------------------------------------------*/ -/* Controller API - *------------------------------------------------------------------*/ - -static void reset_core(dwc2_regs_t* dwc2) { - // reset core - dwc2->grstctl |= GRSTCTL_CSRST; - - // wait for reset bit is cleared - // TODO version 4.20a should wait for RESET DONE mask - while (dwc2->grstctl & GRSTCTL_CSRST) {} - - // wait for AHB master IDLE - while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {} - - // wait for device mode ? -} - -static bool phy_hs_supported(dwc2_regs_t* dwc2) { - (void) dwc2; - -#if !TUD_OPT_HIGH_SPEED - return false; -#else - return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED; -#endif -} - -static void phy_fs_init(dwc2_regs_t* dwc2) { - TU_LOG(DWC2_DEBUG, "Fullspeed PHY init\r\n"); - - // Select FS PHY - dwc2->gusbcfg |= GUSBCFG_PHYSEL; - - // MCU specific PHY init before reset - dwc2_phy_init(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED); - - // Reset core after selecting PHY - reset_core(dwc2); - - // USB turnaround time is critical for certification where long cables and 5-Hubs are used. - // So if you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical, - // these bits can be programmed to a larger value. Default is 5 - dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos); - - // MCU specific PHY update post reset - dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED); - - // set max speed - dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos); -} - -static void phy_hs_init(dwc2_regs_t* dwc2) { - uint32_t gusbcfg = dwc2->gusbcfg; - - // De-select FS PHY - gusbcfg &= ~GUSBCFG_PHYSEL; - - if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { - TU_LOG(DWC2_DEBUG, "Highspeed ULPI PHY init\r\n"); - - // Select ULPI - gusbcfg |= GUSBCFG_ULPI_UTMI_SEL; - - // ULPI 8-bit interface, single data rate - gusbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); - - // default internal VBUS Indicator and Drive - gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); - - // Disable FS/LS ULPI - gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM); - } else { - TU_LOG(DWC2_DEBUG, "Highspeed UTMI+ PHY init\r\n"); - - // Select UTMI+ with 8-bit interface - gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); - - // Set 16-bit interface if supported - if (dwc2->ghwcfg4_bm.phy_data_width) { - gusbcfg |= GUSBCFG_PHYIF16; - } - } - - // Apply config - dwc2->gusbcfg = gusbcfg; - - // mcu specific phy init - dwc2_phy_init(dwc2, dwc2->ghwcfg2_bm.hs_phy_type); - - // Reset core after selecting PHY - reset_core(dwc2); - - // Set turn-around, must after core reset otherwise it will be clear - // - 9 if using 8-bit PHY interface - // - 5 if using 16-bit PHY interface - gusbcfg &= ~GUSBCFG_TRDT_Msk; - gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; - dwc2->gusbcfg = gusbcfg; - - // MCU specific PHY update post reset - dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type); - - // Set max speed - uint32_t dcfg = dwc2->dcfg; - dcfg &= ~DCFG_DSPD_Msk; - dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos; - - // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required - // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347) - if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { - dcfg |= DCFG_XCVRDLY; - } - - dwc2->dcfg = dcfg; -} - -static bool check_dwc2(dwc2_regs_t* dwc2) { -#if CFG_TUSB_DEBUG >= DWC2_DEBUG - // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4 - // Run 'python dwc2_info.py' and check dwc2_info.md for bit-field value and comparison with other ports - volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid; - TU_LOG1("guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n"); - for (size_t i = 0; i < 5; i++) { - TU_LOG1("0x%08" PRIX32 ", ", p[i]); - } - TU_LOG1("0x%08" PRIX32 "\r\n", p[5]); -#endif - - // For some reason: GD32VF103 snpsid and all hwcfg register are always zero (skip it) - (void) dwc2; -#if !TU_CHECK_MCU(OPT_MCU_GD32VF103) - uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK; - TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID); -#endif - - return true; -} - +//-------------------------------------------------------------------- +// Controller API +//-------------------------------------------------------------------- bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { - (void) rhport; (void) rh_init; - // Programming model begins in the last section of the chapter on the USB - // peripheral in each Reference Manual. dwc2_regs_t* dwc2 = DWC2_REG(rhport); - // Check Synopsys ID register, failed if controller clock/power is not enabled - TU_ASSERT(check_dwc2(dwc2)); + TU_ASSERT(dwc2_controller_init(rhport, rh_init)); dcd_disconnect(rhport); - if (phy_hs_supported(dwc2)) { - phy_hs_init(dwc2); // Highspeed - } else { - phy_fs_init(dwc2); // core does not support highspeed or hs phy is not present - } - // Restart PHY clock dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE); diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c new file mode 100644 index 000000000..7fd2311db --- /dev/null +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -0,0 +1,196 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#define DWC2_COMMON_DEBUG 2 + +#if defined(TUP_USBIP_DWC2) && (CFG_TUH_ENABLED || CFG_TUD_ENABLED) + +#include "common/tusb_common.h" +#include "dwc2_common.h" + +static void reset_core(dwc2_regs_t* dwc2) { + // reset core + dwc2->grstctl |= GRSTCTL_CSRST; + + // wait for reset bit is cleared + // TODO version 4.20a should wait for RESET DONE mask + while (dwc2->grstctl & GRSTCTL_CSRST) {} + + // wait for AHB master IDLE + while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {} + + // wait for device mode ? +} + +static bool phy_hs_supported(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { + (void) dwc2; + + +#if !TUD_OPT_HIGH_SPEED + return false; +#else + return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED; +#endif +} + +static void phy_fs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { + TU_LOG(DWC2_COMMON_DEBUG, "Fullspeed PHY init\r\n"); + + // Select FS PHY + dwc2->gusbcfg |= GUSBCFG_PHYSEL; + + // MCU specific PHY init before reset + dwc2_phy_init(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED); + + // Reset core after selecting PHY + reset_core(dwc2); + + // USB turnaround time is critical for certification where long cables and 5-Hubs are used. + // So if you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical, + // these bits can be programmed to a larger value. Default is 5 + dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos); + + // MCU specific PHY update post reset + dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED); + + // set max speed + dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos); +} + +static void phy_hs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { + uint32_t gusbcfg = dwc2->gusbcfg; + + // De-select FS PHY + gusbcfg &= ~GUSBCFG_PHYSEL; + + if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { + TU_LOG(DWC2_COMMON_DEBUG, "Highspeed ULPI PHY init\r\n"); + + // Select ULPI PHY (external) + gusbcfg |= GUSBCFG_ULPI_UTMI_SEL; + + // ULPI is always 8-bit interface + gusbcfg &= ~GUSBCFG_PHYIF16; + + // ULPI select single data rate + gusbcfg &= ~GUSBCFG_DDRSEL; + + // default internal VBUS Indicator and Drive + gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); + + // Disable FS/LS ULPI + gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM); + } else { + TU_LOG(DWC2_COMMON_DEBUG, "Highspeed UTMI+ PHY init\r\n"); + + // Select UTMI+ PHY (internal) + gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL; + + // Set 16-bit interface if supported + if (dwc2->ghwcfg4_bm.phy_data_width) { + gusbcfg |= GUSBCFG_PHYIF16; // 16 bit + }else { + gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit + } + } + + // Apply config + dwc2->gusbcfg = gusbcfg; + + // mcu specific phy init + dwc2_phy_init(dwc2, dwc2->ghwcfg2_bm.hs_phy_type); + + // Reset core after selecting PHY + reset_core(dwc2); + + // Set turn-around, must after core reset otherwise it will be clear + // - 9 if using 8-bit PHY interface + // - 5 if using 16-bit PHY interface + gusbcfg &= ~GUSBCFG_TRDT_Msk; + gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; + dwc2->gusbcfg = gusbcfg; + + // MCU specific PHY update post reset + dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type); + + // Set max speed + uint32_t dcfg = dwc2->dcfg; + dcfg &= ~DCFG_DSPD_Msk; + dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos; + + // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required + // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347) + if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { + dcfg |= DCFG_XCVRDLY; + } + + dwc2->dcfg = dcfg; +} + +static bool check_dwc2(dwc2_regs_t* dwc2) { +#if CFG_TUSB_DEBUG >= DWC2_COMMON_DEBUG + // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4 + // Run 'python dwc2_info.py' and check dwc2_info.md for bit-field value and comparison with other ports + volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid; + TU_LOG1("guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n"); + for (size_t i = 0; i < 5; i++) { + TU_LOG1("0x%08" PRIX32 ", ", p[i]); + } + TU_LOG1("0x%08" PRIX32 "\r\n", p[5]); +#endif + + // For some reason: GD32VF103 gsnpsid and all hwcfg register are always zero (skip it) + (void) dwc2; +#if !TU_CHECK_MCU(OPT_MCU_GD32VF103) + uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK; + TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID); +#endif + + return true; +} + +//-------------------------------------------------------------------- +// +//-------------------------------------------------------------------- +bool dwc2_controller_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + + // Check Synopsys ID register, failed if controller clock/power is not enabled + TU_ASSERT(check_dwc2(dwc2)); + + if (phy_hs_supported(dwc2, rh_init)) { + phy_hs_init(dwc2, rh_init); // Highspeed + } else { + phy_fs_init(dwc2, rh_init); // core does not support highspeed or hs phy is not present + } + + return true; +} + +#endif diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h new file mode 100644 index 000000000..2a48654c0 --- /dev/null +++ b/src/portable/synopsys/dwc2/dwc2_common.h @@ -0,0 +1,70 @@ +/* +* The MIT License (MIT) + * + * Copyright (c) 2024 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef TUSB_DWC2_COMMON_H +#define TUSB_DWC2_COMMON_H + +#include "dwc2_type.h" + +// Following symbols must be defined by port header +// - _dwc2_controller[]: array of controllers +// - DWC2_EP_MAX: largest EP counts of all controllers +// - dwc2_phy_init/dwc2_phy_update: phy init called before and after core reset +// - dwc2_dcd_int_enable/dwc2_dcd_int_disable +// - dwc2_remote_wakeup_delay + +#if defined(TUP_USBIP_DWC2_STM32) + #include "dwc2_stm32.h" +#elif defined(TUP_USBIP_DWC2_ESP32) + #include "dwc2_esp32.h" +#elif TU_CHECK_MCU(OPT_MCU_GD32VF103) + #include "dwc2_gd32.h" +#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837) + #include "dwc2_bcm.h" +#elif TU_CHECK_MCU(OPT_MCU_EFM32GG) + #include "dwc2_efm32.h" +#elif TU_CHECK_MCU(OPT_MCU_XMC4000) + #include "dwc2_xmc.h" +#else + #error "Unsupported MCUs" +#endif + +enum { + DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller) +}; + +TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { + if (rhport >= DWC2_CONTROLLER_COUNT) { + // user mis-configured, ignore and use first controller + rhport = 0; + } + return (dwc2_regs_t*)_dwc2_controller[rhport].reg_base; +} + + +bool dwc2_controller_init(uint8_t rhport, const tusb_rhport_init_t* rh_init); + +#endif diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index cf05bbfec..b9dc413b1 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -31,8 +31,8 @@ * opensource.org/licenses/BSD-3-Clause */ -#ifndef _TUSB_DWC2_TYPES_H_ -#define _TUSB_DWC2_TYPES_H_ +#ifndef TUSB_DWC2_TYPES_H_ +#define TUSB_DWC2_TYPES_H_ #include "stdint.h" diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c new file mode 100644 index 000000000..8798f982c --- /dev/null +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -0,0 +1,167 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUH_ENABLED && defined(TUP_USBIP_DWC2) + +// Debug level for DWC2 +#define DWC2_DEBUG 2 + +#include "host/hcd.h" +#include "dwc2_common.h" + +//--------------------------------------------------------------------+ +// Controller API +//--------------------------------------------------------------------+ + +// optional hcd configuration, called by tuh_configure() +bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { + (void) rhport; + (void) cfg_id; + (void) cfg_param; + + return false; +} + +// Initialize controller to host mode +bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rhport; + (void) rh_init; + return false; +} + +// Interrupt Handler +void hcd_int_handler(uint8_t rhport, bool in_isr) { + (void) rhport; + (void) in_isr; +} + +// Enable USB interrupt +void hcd_int_enable (uint8_t rhport) { + (void) rhport; +} + +// Disable USB interrupt +void hcd_int_disable(uint8_t rhport) { + (void) rhport; +} + +// Get frame number (1ms) +uint32_t hcd_frame_number(uint8_t rhport) { + (void) rhport; + + return 0; +} + +//--------------------------------------------------------------------+ +// Port API +//--------------------------------------------------------------------+ + +// Get the current connect status of roothub port +bool hcd_port_connect_status(uint8_t rhport) { + (void) rhport; + + return false; +} + +// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete. +// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence. +void hcd_port_reset(uint8_t rhport) { + (void) rhport; +} + +// Complete bus reset sequence, may be required by some controllers +void hcd_port_reset_end(uint8_t rhport) { + (void) rhport; +} + +// Get port link speed +tusb_speed_t hcd_port_speed_get(uint8_t rhport) { + (void) rhport; + + return TUSB_SPEED_FULL; +} + +// HCD closes all opened endpoints belong to this device +void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { + (void) rhport; + (void) dev_addr; +} + +//--------------------------------------------------------------------+ +// Endpoints API +//--------------------------------------------------------------------+ + +// Open an endpoint +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { + (void) rhport; + (void) dev_addr; + (void) ep_desc; + + return false; +} + +// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked +bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + (void) buffer; + (void) buflen; + + return false; +} + +// Abort a queued transfer. Note: it can only abort transfer that has not been started +// Return true if a queued transfer is aborted, false if there is no transfer to abort +bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + + return false; +} + +// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked +bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { + (void) rhport; + (void) dev_addr; + (void) setup_packet; + + return false; +} + +// clear stall, data toggle is also reset to DATA0 +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + + return false; +} + +#endif -- cgit v1.3.1 From 4012e150757b517620465d93a22b0787c6400c5d Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 15 Oct 2024 17:55:24 +0700 Subject: move core init code to dwc2 common. update/correct build for esppressif --- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- .../device/audio_4_channel_mic_freertos/src/main.c | 6 +-- .../audio_4_channel_mic_freertos/src/tusb_config.h | 2 +- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- examples/device/audio_test_freertos/src/main.c | 9 ++-- .../device/audio_test_freertos/src/tusb_config.h | 2 +- examples/device/board_test/src/main.c | 2 +- examples/device/board_test/src/tusb_config.h | 2 +- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- examples/device/cdc_msc_freertos/src/main.c | 6 +-- examples/device/cdc_msc_freertos/src/tusb_config.h | 2 +- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- examples/device/hid_composite_freertos/src/main.c | 6 +-- .../hid_composite_freertos/src/tusb_config.h | 2 +- examples/device/video_capture/src/main.c | 4 +- examples/device/video_capture/src/tusb_config.h | 2 +- examples/device/video_capture_2ch/src/main.c | 4 +- .../device/video_capture_2ch/src/tusb_config.h | 2 +- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- examples/host/cdc_msc_hid_freertos/src/cdc_app.c | 2 +- examples/host/cdc_msc_hid_freertos/src/main.c | 6 +-- .../host/cdc_msc_hid_freertos/src/tusb_config.h | 2 +- examples/typec/power_delivery/src/main.c | 2 +- hw/bsp/board_api.h | 2 +- hw/bsp/broadcom_32bit/family.cmake | 2 + hw/bsp/broadcom_64bit/family.cmake | 2 + .../components/tinyusb_src/CMakeLists.txt | 2 + hw/bsp/gd32vf103/family.cmake | 2 + hw/bsp/stm32f2/family.cmake | 2 + hw/bsp/stm32f4/family.cmake | 2 + hw/bsp/stm32f7/family.cmake | 2 + hw/bsp/stm32h7/boards/stm32h743eval/board.cmake | 2 +- hw/bsp/stm32u5/family.cmake | 17 +++--- hw/bsp/xmc4000/family.cmake | 2 + src/common/tusb_verify.h | 2 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 34 +++++++----- src/portable/synopsys/dwc2/dwc2_common.c | 63 ++++++++++++---------- src/portable/synopsys/dwc2/dwc2_common.h | 5 +- src/portable/synopsys/dwc2/dwc2_esp32.h | 5 +- src/portable/synopsys/dwc2/dwc2_type.h | 60 ++++++++++----------- src/tusb_option.h | 3 +- tools/build_utils.py | 29 +++++----- 42 files changed, 171 insertions(+), 140 deletions(-) (limited to 'hw') diff --git a/examples/device/audio_4_channel_mic_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/audio_4_channel_mic_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h index 869500ad2..902a54f08 100644 --- a/examples/device/audio_4_channel_mic_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h +++ b/examples/device/audio_4_channel_mic_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -48,7 +48,7 @@ // Include MCU header #include "bsp/board_mcu.h" -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 +#if TUSB_MCU_VENDOR_ESPRESSIF #error "ESP32-Sx should use IDF's FreeRTOSConfig.h" #endif diff --git a/examples/device/audio_4_channel_mic_freertos/src/main.c b/examples/device/audio_4_channel_mic_freertos/src/main.c index 2ac7516cd..c9de4029a 100644 --- a/examples/device/audio_4_channel_mic_freertos/src/main.c +++ b/examples/device/audio_4_channel_mic_freertos/src/main.c @@ -39,7 +39,7 @@ #include "bsp/board_api.h" #include "tusb.h" -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" @@ -186,14 +186,14 @@ int main(void) #endif // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 - #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) + #if !TUSB_MCU_VENDOR_ESPRESSIF vTaskStartScheduler(); #endif return 0; } -#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) +#if TUSB_MCU_VENDOR_ESPRESSIF void app_main(void) { main(); diff --git a/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h b/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h index 88f20278b..5cd93b0d6 100644 --- a/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h +++ b/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h @@ -59,7 +59,7 @@ extern "C" { #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/audio_test_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/audio_test_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h index 869500ad2..902a54f08 100644 --- a/examples/device/audio_test_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h +++ b/examples/device/audio_test_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -48,7 +48,7 @@ // Include MCU header #include "bsp/board_mcu.h" -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 +#if TUSB_MCU_VENDOR_ESPRESSIF #error "ESP32-Sx should use IDF's FreeRTOSConfig.h" #endif diff --git a/examples/device/audio_test_freertos/src/main.c b/examples/device/audio_test_freertos/src/main.c index 4e2264b5d..c5143c3fc 100644 --- a/examples/device/audio_test_freertos/src/main.c +++ b/examples/device/audio_test_freertos/src/main.c @@ -38,7 +38,7 @@ #include "bsp/board_api.h" #include "tusb.h" -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" @@ -133,16 +133,15 @@ int main(void) #endif // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 - #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) + #if !TUSB_MCU_VENDOR_ESPRESSIF vTaskStartScheduler(); #endif return 0; } -#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) -void app_main(void) -{ +#if TUSB_MCU_VENDOR_ESPRESSIF +void app_main(void) { main(); } #endif diff --git a/examples/device/audio_test_freertos/src/tusb_config.h b/examples/device/audio_test_freertos/src/tusb_config.h index 8b376a4c3..61c5cbb96 100644 --- a/examples/device/audio_test_freertos/src/tusb_config.h +++ b/examples/device/audio_test_freertos/src/tusb_config.h @@ -59,7 +59,7 @@ extern "C" { #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c index 91799eb89..2269d45f1 100644 --- a/examples/device/board_test/src/main.c +++ b/examples/device/board_test/src/main.c @@ -67,7 +67,7 @@ int main(void) { } } -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 +#if TUSB_MCU_VENDOR_ESPRESSIF void app_main(void) { main(); } diff --git a/examples/device/board_test/src/tusb_config.h b/examples/device/board_test/src/tusb_config.h index 89c27d1c0..8ac3bc8de 100644 --- a/examples/device/board_test/src/tusb_config.h +++ b/examples/device/board_test/src/tusb_config.h @@ -44,7 +44,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h index 869500ad2..902a54f08 100644 --- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h +++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -48,7 +48,7 @@ // Include MCU header #include "bsp/board_mcu.h" -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 +#if TUSB_MCU_VENDOR_ESPRESSIF #error "ESP32-Sx should use IDF's FreeRTOSConfig.h" #endif diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index f70267e33..a05ceff58 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -30,7 +30,7 @@ #include "bsp/board_api.h" #include "tusb.h" -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" @@ -111,14 +111,14 @@ int main(void) { #endif // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 -#if !TUP_MCU_ESPRESSIF +#if !TUSB_MCU_VENDOR_ESPRESSIF vTaskStartScheduler(); #endif return 0; } -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF void app_main(void) { main(); } diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h index e743c9148..c3f2f7fb5 100644 --- a/examples/device/cdc_msc_freertos/src/tusb_config.h +++ b/examples/device/cdc_msc_freertos/src/tusb_config.h @@ -59,7 +59,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h index 869500ad2..902a54f08 100644 --- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h +++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -48,7 +48,7 @@ // Include MCU header #include "bsp/board_mcu.h" -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 +#if TUSB_MCU_VENDOR_ESPRESSIF #error "ESP32-Sx should use IDF's FreeRTOSConfig.h" #endif diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c index ae091571e..30c0331ef 100644 --- a/examples/device/hid_composite_freertos/src/main.c +++ b/examples/device/hid_composite_freertos/src/main.c @@ -31,7 +31,7 @@ #include "tusb.h" #include "usb_descriptors.h" -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" @@ -113,14 +113,14 @@ int main(void) xTimerStart(blinky_tm, 0); // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 -#if !TUP_MCU_ESPRESSIF +#if !TUSB_MCU_VENDOR_ESPRESSIF vTaskStartScheduler(); #endif return 0; } -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF void app_main(void) { main(); diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h index 0689e0f23..6ec38b95c 100644 --- a/examples/device/hid_composite_freertos/src/tusb_config.h +++ b/examples/device/hid_composite_freertos/src/tusb_config.h @@ -59,7 +59,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index aeeeb8930..8bb924c61 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -292,7 +292,7 @@ void led_blinking_task(void* param) { #define BLINKY_STACK_SIZE configMINIMAL_STACK_SIZE #define VIDEO_STACK_SIZE (configMINIMAL_STACK_SIZE*4) -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define USBD_STACK_SIZE 4096 int main(void); void app_main(void) { @@ -352,7 +352,7 @@ void freertos_init_task(void) { #endif // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 - #if !TUP_MCU_ESPRESSIF + #if !TUSB_MCU_VENDOR_ESPRESSIF vTaskStartScheduler(); #endif } diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h index 3a6daa3d3..6dbd6f2a5 100644 --- a/examples/device/video_capture/src/tusb_config.h +++ b/examples/device/video_capture/src/tusb_config.h @@ -58,7 +58,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/video_capture_2ch/src/main.c b/examples/device/video_capture_2ch/src/main.c index dd6983766..245e7abb8 100644 --- a/examples/device/video_capture_2ch/src/main.c +++ b/examples/device/video_capture_2ch/src/main.c @@ -300,7 +300,7 @@ void led_blinking_task(void* param) { #define BLINKY_STACK_SIZE configMINIMAL_STACK_SIZE #define VIDEO_STACK_SIZE (configMINIMAL_STACK_SIZE*4) -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define USBD_STACK_SIZE 4096 int main(void); void app_main(void) { @@ -360,7 +360,7 @@ void freertos_init_task(void) { #endif // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 - #if !TUP_MCU_ESPRESSIF + #if !TUSB_MCU_VENDOR_ESPRESSIF vTaskStartScheduler(); #endif } diff --git a/examples/device/video_capture_2ch/src/tusb_config.h b/examples/device/video_capture_2ch/src/tusb_config.h index 43c7dfc90..91775a327 100644 --- a/examples/device/video_capture_2ch/src/tusb_config.h +++ b/examples/device/video_capture_2ch/src/tusb_config.h @@ -58,7 +58,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h index bd754518d..6a886adec 100644 --- a/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h +++ b/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -48,7 +48,7 @@ // Include MCU header #include "bsp/board_mcu.h" -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 +#if TUSB_MCU_VENDOR_ESPRESSIF #error "ESP32-Sx should use IDF's FreeRTOSConfig.h" #endif diff --git a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c index f3495ab28..dfe1418f6 100644 --- a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c +++ b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c @@ -27,7 +27,7 @@ #include "tusb.h" #include "bsp/board_api.h" -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c index 7fb84a40f..fe050d334 100644 --- a/examples/host/cdc_msc_hid_freertos/src/main.c +++ b/examples/host/cdc_msc_hid_freertos/src/main.c @@ -30,7 +30,7 @@ #include "bsp/board_api.h" #include "tusb.h" -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" @@ -107,14 +107,14 @@ int main(void) { xTimerStart(blinky_tm, 0); // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 -#if !TUP_MCU_ESPRESSIF +#if !TUSB_MCU_VENDOR_ESPRESSIF vTaskStartScheduler(); #endif return 0; } -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF void app_main(void) { main(); } diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h index 0aab2cd2f..02de4197b 100644 --- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h +++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h @@ -44,7 +44,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c index a8214f34e..068dbbeb1 100644 --- a/examples/typec/power_delivery/src/main.c +++ b/examples/typec/power_delivery/src/main.c @@ -71,7 +71,7 @@ int main(void) } } -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 +#if TUSB_MCU_VENDOR_ESPRESSIF void app_main(void) { main(); diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h index a458a3fdc..eaee1ee97 100644 --- a/hw/bsp/board_api.h +++ b/hw/bsp/board_api.h @@ -39,7 +39,7 @@ extern "C" { #include "tusb.h" #if CFG_TUSB_OS == OPT_OS_FREERTOS -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" diff --git a/hw/bsp/broadcom_32bit/family.cmake b/hw/bsp/broadcom_32bit/family.cmake index 6205d4e1b..93e7d3545 100644 --- a/hw/bsp/broadcom_32bit/family.cmake +++ b/hw/bsp/broadcom_32bit/family.cmake @@ -97,6 +97,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_BCM2835 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/broadcom_64bit/family.cmake b/hw/bsp/broadcom_64bit/family.cmake index f373dc633..d790944bc 100644 --- a/hw/bsp/broadcom_64bit/family.cmake +++ b/hw/bsp/broadcom_64bit/family.cmake @@ -104,6 +104,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_BCM${BCM_VERSION} ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt index 26c7e4030..ae94a0ea4 100644 --- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt +++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt @@ -34,6 +34,8 @@ list(APPEND srcs ${tusb_src}/class/vendor/vendor_device.c ${tusb_src}/class/video/video_device.c ${tusb_src}/portable/synopsys/dwc2/dcd_dwc2.c + ${tusb_src}/portable/synopsys/dwc2/hcd_dwc2.c + ${tusb_src}/portable/synopsys/dwc2/dwc2_common.c # host ${tusb_src}/host/usbh.c ${tusb_src}/host/hub.c diff --git a/hw/bsp/gd32vf103/family.cmake b/hw/bsp/gd32vf103/family.cmake index 5f4a3da8d..1441e41de 100644 --- a/hw/bsp/gd32vf103/family.cmake +++ b/hw/bsp/gd32vf103/family.cmake @@ -108,6 +108,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_GD32VF103 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/stm32f2/family.cmake b/hw/bsp/stm32f2/family.cmake index a01ebef5c..538a6cd66 100644 --- a/hw/bsp/stm32f2/family.cmake +++ b/hw/bsp/stm32f2/family.cmake @@ -102,6 +102,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_STM32F2 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/stm32f4/family.cmake b/hw/bsp/stm32f4/family.cmake index f24ef366e..a2832763a 100644 --- a/hw/bsp/stm32f4/family.cmake +++ b/hw/bsp/stm32f4/family.cmake @@ -102,6 +102,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_STM32F4 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/stm32f7/family.cmake b/hw/bsp/stm32f7/family.cmake index 938c2697a..798dc4dbb 100644 --- a/hw/bsp/stm32f7/family.cmake +++ b/hw/bsp/stm32f7/family.cmake @@ -104,6 +104,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_STM32F7 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake index 6d7a97741..2ff874690 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake @@ -1,6 +1,6 @@ set(MCU_VARIANT stm32h743xx) set(JLINK_DEVICE stm32h743xi) -# set(JLINK_OPTION "-USB jtrace") +set(JLINK_OPTION "-USB jtrace") set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld) diff --git a/hw/bsp/stm32u5/family.cmake b/hw/bsp/stm32u5/family.cmake index f7a7aeb33..3ab7cdf8b 100644 --- a/hw/bsp/stm32u5/family.cmake +++ b/hw/bsp/stm32u5/family.cmake @@ -102,16 +102,13 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_STM32U5 ${RTOS}) - if ((${MCU_VARIANT} STREQUAL "stm32u535xx") OR (${MCU_VARIANT} STREQUAL "stm32u545xx")) - target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - ) - else () - target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c - #${TOP}/src/portable/st/typec/typec_stm32.c - ) - endif () + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c + #${TOP}/src/portable/st/typec/typec_stm32.c + ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) # Link dependencies diff --git a/hw/bsp/xmc4000/family.cmake b/hw/bsp/xmc4000/family.cmake index d91e6f0b6..85444db28 100644 --- a/hw/bsp/xmc4000/family.cmake +++ b/hw/bsp/xmc4000/family.cmake @@ -86,6 +86,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_XMC4000 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h index 3e0f1f106..6d02d3572 100644 --- a/src/common/tusb_verify.h +++ b/src/common/tusb_verify.h @@ -83,7 +83,7 @@ if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */ \ } while(0) -#elif defined(__riscv) && !TUP_MCU_ESPRESSIF +#elif defined(__riscv) && !TUSB_MCU_VENDOR_ESPRESSIF #define TU_BREAKPOINT() do { __asm("ebreak\n"); } while(0) #elif defined(_mips) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index a9b3770ee..c67c34404 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -480,21 +480,28 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; dwc2_regs_t* dwc2 = DWC2_REG(rhport); - TU_ASSERT(dwc2_controller_init(rhport, rh_init)); + TU_ASSERT(dwc2_core_init(rhport, rh_init)); + + // Device Initialization dcd_disconnect(rhport); - // Restart PHY clock - dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE); + // Set device max speed + uint32_t dcfg = dwc2->dcfg & ~DCFG_DSPD_Msk; + if (dwc2_core_is_highspeed(dwc2, rh_init)) { + dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos; + + // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required + // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347) + if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { + dcfg |= DCFG_XCVRDLY; + } + }else { + dcfg |= DCFG_DSPD_FS << DCFG_DSPD_Pos; + } + dwc2->dcfg = dcfg; - /* Set HS/FS Timeout Calibration to 7 (max available value). - * The number of PHY clocks that the application programs in - * this field is added to the high/full speed interpacket timeout - * duration in the core to account for any additional delays - * introduced by the PHY. This can be required, because the delay - * introduced by the PHY in generating the linestate condition - * can vary from one PHY to another. - */ - dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos); + // Enable PHY clock TODO stop/gate clock when suspended mode + dwc2->pcgcctl &= ~(PCGCCTL_STOPPCLK | PCGCCTL_GATEHCLK | PCGCCTL_PWRCLMP | PCGCCTL_RSTPDWNMODULE); // Force device mode dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD; @@ -502,8 +509,7 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Clear A override, force B Valid dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL; - // If USB host misbehaves during status portion of control xfer - // (non zero-length packet), send STALL back and discard. + // If USB host misbehaves during status portion of control xfer (non zero-length packet), send STALL back and discard dwc2->dcfg |= DCFG_NZLSOHSK; dfifo_flush_tx(dwc2, 0x10); // all tx fifo diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index 7fd2311db..190dc0734 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -30,7 +30,14 @@ #if defined(TUP_USBIP_DWC2) && (CFG_TUH_ENABLED || CFG_TUD_ENABLED) -#include "common/tusb_common.h" +#if CFG_TUD_ENABLED +#include "device/dcd.h" +#endif + +#if CFG_TUH_ENABLED +#include "host/hcd.h" +#endif + #include "dwc2_common.h" static void reset_core(dwc2_regs_t* dwc2) { @@ -47,18 +54,24 @@ static void reset_core(dwc2_regs_t* dwc2) { // wait for device mode ? } -static bool phy_hs_supported(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { +bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { (void) dwc2; +#if CFG_TUD_ENABLED + if (rh_init->role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) { + return false; + } +#endif +#if CFG_TUH_ENABLED + if (rh_init->role == TUSB_ROLE_DEVICE && !TUH_OPT_HIGH_SPEED) { + return false; + } +#endif -#if !TUD_OPT_HIGH_SPEED - return false; -#else return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED; -#endif } -static void phy_fs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { +static void phy_fs_init(dwc2_regs_t* dwc2) { TU_LOG(DWC2_COMMON_DEBUG, "Fullspeed PHY init\r\n"); // Select FS PHY @@ -77,12 +90,9 @@ static void phy_fs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { // MCU specific PHY update post reset dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED); - - // set max speed - dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos); } -static void phy_hs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { +static void phy_hs_init(dwc2_regs_t* dwc2) { uint32_t gusbcfg = dwc2->gusbcfg; // De-select FS PHY @@ -137,19 +147,6 @@ static void phy_hs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { // MCU specific PHY update post reset dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type); - - // Set max speed - uint32_t dcfg = dwc2->dcfg; - dcfg &= ~DCFG_DSPD_Msk; - dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos; - - // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required - // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347) - if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { - dcfg |= DCFG_XCVRDLY; - } - - dwc2->dcfg = dcfg; } static bool check_dwc2(dwc2_regs_t* dwc2) { @@ -177,19 +174,29 @@ static bool check_dwc2(dwc2_regs_t* dwc2) { //-------------------------------------------------------------------- // //-------------------------------------------------------------------- -bool dwc2_controller_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Check Synopsys ID register, failed if controller clock/power is not enabled TU_ASSERT(check_dwc2(dwc2)); - if (phy_hs_supported(dwc2, rh_init)) { - phy_hs_init(dwc2, rh_init); // Highspeed + if (dwc2_core_is_highspeed(dwc2, rh_init)) { + phy_hs_init(dwc2); // Highspeed } else { - phy_fs_init(dwc2, rh_init); // core does not support highspeed or hs phy is not present + phy_fs_init(dwc2); // core does not support highspeed or hs phy is not present } + /* Set HS/FS Timeout Calibration to 7 (max available value). + * The number of PHY clocks that the application programs in + * this field is added to the high/full speed interpacket timeout + * duration in the core to account for any additional delays + * introduced by the PHY. This can be required, because the delay + * introduced by the PHY in generating the linestate condition + * can vary from one PHY to another. + */ + dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos); + return true; } diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h index 2a48654c0..4039ebaa3 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.h +++ b/src/portable/synopsys/dwc2/dwc2_common.h @@ -27,6 +27,7 @@ #ifndef TUSB_DWC2_COMMON_H #define TUSB_DWC2_COMMON_H +#include "common/tusb_common.h" #include "dwc2_type.h" // Following symbols must be defined by port header @@ -64,7 +65,7 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { return (dwc2_regs_t*)_dwc2_controller[rhport].reg_base; } - -bool dwc2_controller_init(uint8_t rhport, const tusb_rhport_init_t* rh_init); +bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init); +bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init); #endif diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index 4cdbcdb7a..c8c5bffd0 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -25,13 +25,14 @@ */ -#ifndef _DWC2_ESP32_H_ -#define _DWC2_ESP32_H_ +#ifndef TUSB_DWC2_ESP32_H_ +#define TUSB_DWC2_ESP32_H_ #ifdef __cplusplus extern "C" { #endif +#include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "esp_intr_alloc.h" diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index b9dc413b1..81e3ab6b8 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -464,8 +464,8 @@ typedef struct { uint32_t reservedd00[64]; // D00..DFF //------------- Power Clock -------------// - volatile uint32_t pcgctl; // E00 Power and Clock Gating Control - volatile uint32_t pcgctl1; // E04 + volatile uint32_t pcgcctl; // E00 Power and Clock Gating Characteristic Control + volatile uint32_t pcgcctl1; // E04 Power and Clock Gating Characteristic Control 1 uint32_t reservede08[126]; // E08..FFF //------------- FIFOs -------------// @@ -478,7 +478,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x0500, "incorrect size"); TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg ) == 0x0800, "incorrect size"); TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epin ) == 0x0900, "incorrect size"); TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout ) == 0x0B00, "incorrect size"); -TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgctl ) == 0x0E00, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgcctl) == 0x0E00, "incorrect size"); TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); //--------------------------------------------------------------------+ @@ -720,7 +720,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); /******************** Bit definition for GUSBCFG register ********************/ #define GUSBCFG_TOCAL_Pos (0U) #define GUSBCFG_TOCAL_Msk (0x7UL << GUSBCFG_TOCAL_Pos) // 0x00000007 -#define GUSBCFG_TOCAL GUSBCFG_TOCAL_Msk // FS timeout calibration +#define GUSBCFG_TOCAL GUSBCFG_TOCAL_Msk // HS/FS timeout calibration #define GUSBCFG_PHYIF16_Pos (3U) #define GUSBCFG_PHYIF16_Msk (0x1UL << GUSBCFG_PHYIF16_Pos) // 0x00000008 #define GUSBCFG_PHYIF16 GUSBCFG_PHYIF16_Msk // PHY Interface (PHYIf) @@ -1973,32 +1973,32 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DOEPTSIZ_STUPCNT_1 (0x2UL << DOEPTSIZ_STUPCNT_Pos) // 0x40000000 /******************** Bit definition for PCGCTL register ********************/ -#define PCGCTL_IF_DEV_MODE TU_BIT(31) -#define PCGCTL_P2HD_PRT_SPD_MASK (0x3ul << 29) -#define PCGCTL_P2HD_PRT_SPD_SHIFT 29 -#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3ul << 27) -#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27 -#define PCGCTL_MAC_DEV_ADDR_MASK (0x7ful << 20) -#define PCGCTL_MAC_DEV_ADDR_SHIFT 20 -#define PCGCTL_MAX_TERMSEL TU_BIT(19) -#define PCGCTL_MAX_XCVRSELECT_MASK (0x3ul << 17) -#define PCGCTL_MAX_XCVRSELECT_SHIFT 17 -#define PCGCTL_PORT_POWER TU_BIT(16) -#define PCGCTL_PRT_CLK_SEL_MASK (0x3ul << 14) -#define PCGCTL_PRT_CLK_SEL_SHIFT 14 -#define PCGCTL_ESS_REG_RESTORED TU_BIT(13) -#define PCGCTL_EXTND_HIBER_SWITCH TU_BIT(12) -#define PCGCTL_EXTND_HIBER_PWRCLMP TU_BIT(11) -#define PCGCTL_ENBL_EXTND_HIBER TU_BIT(10) -#define PCGCTL_RESTOREMODE TU_BIT(9) -#define PCGCTL_RESETAFTSUSP TU_BIT(8) -#define PCGCTL_DEEP_SLEEP TU_BIT(7) -#define PCGCTL_PHY_IN_SLEEP TU_BIT(6) -#define PCGCTL_ENBL_SLEEP_GATING TU_BIT(5) -#define PCGCTL_RSTPDWNMODULE TU_BIT(3) -#define PCGCTL_PWRCLMP TU_BIT(2) -#define PCGCTL_GATEHCLK TU_BIT(1) -#define PCGCTL_STOPPCLK TU_BIT(0) +#define PCGCCTL_IF_DEV_MODE TU_BIT(31) +#define PCGCCTL_P2HD_PRT_SPD_MASK (0x3ul << 29) +#define PCGCCTL_P2HD_PRT_SPD_SHIFT 29 +#define PCGCCTL_P2HD_DEV_ENUM_SPD_MASK (0x3ul << 27) +#define PCGCCTL_P2HD_DEV_ENUM_SPD_SHIFT 27 +#define PCGCCTL_MAC_DEV_ADDR_MASK (0x7ful << 20) +#define PCGCCTL_MAC_DEV_ADDR_SHIFT 20 +#define PCGCCTL_MAX_TERMSEL TU_BIT(19) +#define PCGCCTL_MAX_XCVRSELECT_MASK (0x3ul << 17) +#define PCGCCTL_MAX_XCVRSELECT_SHIFT 17 +#define PCGCCTL_PORT_POWER TU_BIT(16) +#define PCGCCTL_PRT_CLK_SEL_MASK (0x3ul << 14) +#define PCGCCTL_PRT_CLK_SEL_SHIFT 14 +#define PCGCCTL_ESS_REG_RESTORED TU_BIT(13) +#define PCGCCTL_EXTND_HIBER_SWITCH TU_BIT(12) +#define PCGCCTL_EXTND_HIBER_PWRCLMP TU_BIT(11) +#define PCGCCTL_ENBL_EXTND_HIBER TU_BIT(10) +#define PCGCCTL_RESTOREMODE TU_BIT(9) +#define PCGCCTL_RESETAFTSUSP TU_BIT(8) +#define PCGCCTL_DEEP_SLEEP TU_BIT(7) +#define PCGCCTL_PHY_IN_SLEEP TU_BIT(6) +#define PCGCCTL_ENBL_SLEEP_GATING TU_BIT(5) +#define PCGCCTL_RSTPDWNMODULE TU_BIT(3) +#define PCGCCTL_PWRCLMP TU_BIT(2) +#define PCGCCTL_GATEHCLK TU_BIT(1) +#define PCGCCTL_STOPPCLK TU_BIT(0) #define PCGCTL1_TIMER (0x3ul << 1) #define PCGCTL1_GATEEN TU_BIT(0) diff --git a/src/tusb_option.h b/src/tusb_option.h index fdc949747..d36d0bcad 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -125,7 +125,8 @@ #define OPT_MCU_ESP32C2 905 ///< Espressif ESP32-C2 #define OPT_MCU_ESP32H2 906 ///< Espressif ESP32-H2 #define OPT_MCU_ESP32P4 907 ///< Espressif ESP32-P4 -#define TUP_MCU_ESPRESSIF (CFG_TUSB_MCU >= 900 && CFG_TUSB_MCU < 1000) // check if Espressif MCU +#define TUSB_MCU_VENDOR_ESPRESSIF (CFG_TUSB_MCU >= 900 && CFG_TUSB_MCU < 1000) // check if Espressif MCU +#define TUP_MCU_ESPRESSIF TUSB_MCU_VENDOR_ESPRESSIF // for backward compatibility // Dialog #define OPT_MCU_DA1469X 1000 ///< Dialog Semiconductor DA1469x diff --git a/tools/build_utils.py b/tools/build_utils.py index 5462829e2..b4a1dc096 100755 --- a/tools/build_utils.py +++ b/tools/build_utils.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 import subprocess import pathlib -import time +import re build_format = '| {:29} | {:30} | {:18} | {:7} | {:6} | {:6} |' @@ -36,18 +36,21 @@ def skip_example(example, board): mk_contents = board_mk.read_text() mcu = "NONE" - for token in mk_contents.split(): - if "CFG_TUSB_MCU=OPT_MCU_" in token: - # Strip " because cmake files has them. - token = token.strip("\"") - _, opt_mcu = token.split("=") - mcu = opt_mcu[len("OPT_MCU_"):] - if "esp32s2" in token: - mcu = "ESP32S2" - if "esp32s3" in token: - mcu = "ESP32S3" - if mcu != "NONE": - break + if family == "espressif": + for line in mk_contents.splitlines(): + match = re.search(r'set\(IDF_TARGET\s+"([^"]+)"\)', line) + if match: + mcu = match.group(1) + break + else: + for token in mk_contents.split(): + if "CFG_TUSB_MCU=OPT_MCU_" in token: + # Strip " because cmake files has them. + token = token.strip("\"") + _, opt_mcu = token.split("=") + mcu = opt_mcu[len("OPT_MCU_"):] + if mcu != "NONE": + break # Skip all OPT_MCU_NONE these are WIP port if mcu == "NONE": -- cgit v1.3.1 From 42b6f30edaf91196ecdaaebb36385bcc3f312d17 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 18 Oct 2024 18:33:50 +0700 Subject: add VBUS drive via MFX for h743 eval, but does not seems to work yet --- hw/bsp/stm32h7/boards/daisyseed/board.h | 2 +- hw/bsp/stm32h7/boards/stm32h723nucleo/board.h | 2 +- hw/bsp/stm32h7/boards/stm32h743eval/board.h | 153 ++++++++++++++++++++- .../boards/stm32h743eval/cubemx/stm32h743eval.ioc | 27 ++-- hw/bsp/stm32h7/boards/stm32h743nucleo/board.h | 2 +- hw/bsp/stm32h7/boards/stm32h745disco/board.h | 2 +- hw/bsp/stm32h7/boards/stm32h750_weact/board.h | 2 +- hw/bsp/stm32h7/boards/stm32h750bdk/board.h | 2 +- hw/bsp/stm32h7/boards/waveshare_openh743i/board.h | 2 +- hw/bsp/stm32h7/family.c | 7 +- hw/bsp/stm32h7/family.cmake | 7 + hw/bsp/stm32h7/stm32h7xx_hal_conf.h | 2 +- tools/get_deps.py | 3 + 13 files changed, 191 insertions(+), 22 deletions(-) (limited to 'hw') diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.h b/hw/bsp/stm32h7/boards/daisyseed/board.h index abc07488b..532e3bfd5 100644 --- a/hw/bsp/stm32h7/boards/daisyseed/board.h +++ b/hw/bsp/stm32h7/boards/daisyseed/board.h @@ -128,7 +128,7 @@ static inline void SystemClock_Config(void) HAL_EnableCompensationCell(); } -static inline void board_stm32h7_post_init(void) +static inline void board_init2(void) { // For this board does nothing } diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h index 3d9344a87..b3da1348f 100644 --- a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h +++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h @@ -118,7 +118,7 @@ static inline void SystemClock_Config(void) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct); } -static inline void board_stm32h7_post_init(void) +static inline void board_init2(void) { // For this board does nothing } diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h index 22d66d735..9e2649d14 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h @@ -31,6 +31,8 @@ extern "C" { #endif +#include "mfxstm32l152.h" + #define LED_PORT GPIOA #define LED_PIN GPIO_PIN_4 #define LED_STATE_ON 1 @@ -58,6 +60,22 @@ {GPIOB, GPIO_PIN_5 }, {GPIOB, GPIO_PIN_10}, {GPIOB, GPIO_PIN_11}, {GPIOB, GPIO_PIN_12}, \ {GPIOB, GPIO_PIN_13}, {GPIOC, GPIO_PIN_0 }, {GPIOH, GPIO_PIN_4 }, {GPIOI, GPIO_PIN_11} +// vbus drive +#define BOARD_VBUS_DRIVE(_rhport, _on) do { \ + if ( mfx_io_drv ) { \ + uint32_t io_pin = (_rhport) ? MFXSTM32L152_GPIO_PIN_9 : MFXSTM32L152_GPIO_PIN_7; \ + mfx_io_drv->IO_WritePin(&Io_CompObj, io_pin, _on); \ + }\ + } while(0) + +/* Definition for I2C1 Pins */ +#define BUS_I2C1_SCL_PIN GPIO_PIN_6 +#define BUS_I2C1_SDA_PIN GPIO_PIN_7 +#define BUS_I2C1_SCL_GPIO_PORT GPIOB +#define BUS_I2C1_SDA_GPIO_PORT GPIOB +#define BUS_I2C1_SCL_AF GPIO_AF4_I2C1 +#define BUS_I2C1_SDA_AF GPIO_AF4_I2C1 + //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ @@ -132,11 +150,140 @@ static inline void SystemClock_Config(void) { HAL_EnableCompensationCell(); } -static inline void board_stm32h7_post_init(void) -{ - // For this board does nothing +//--------------------------------------------------------------------+ +// MFX +//--------------------------------------------------------------------+ +I2C_HandleTypeDef hbus_i2c1 = { .Instance = I2C1}; +static MFXSTM32L152_Object_t mfx_obj = { 0 }; +static MFXSTM32L152_IO_Mode_t* mfx_io_drv = NULL; + +HAL_StatusTypeDef MX_I2C1_Init(I2C_HandleTypeDef* hI2c, uint32_t timing) { + hI2c->Init.Timing = timing; + hI2c->Init.OwnAddress1 = 0; + hI2c->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; + hI2c->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + hI2c->Init.OwnAddress2 = 0; + hI2c->Init.OwnAddress2Masks = I2C_OA2_NOMASK; + hI2c->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; + hI2c->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; + + if (HAL_I2C_Init(hI2c) != HAL_OK) { + return HAL_ERROR; + } + if (HAL_I2CEx_ConfigAnalogFilter(hI2c, I2C_ANALOGFILTER_ENABLE) != HAL_OK) { + return HAL_ERROR; + } + if (HAL_I2CEx_ConfigDigitalFilter(hI2c, 0) != HAL_OK) { + return HAL_ERROR; + } + + return HAL_OK; +} + +int32_t BSP_I2C1_Init(void) { + // Init I2C + GPIO_InitTypeDef gpio_init_structure; + gpio_init_structure.Pin = BUS_I2C1_SCL_PIN; + gpio_init_structure.Mode = GPIO_MODE_AF_OD; + gpio_init_structure.Pull = GPIO_NOPULL; + gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH; + gpio_init_structure.Alternate = BUS_I2C1_SCL_AF; + HAL_GPIO_Init(BUS_I2C1_SCL_GPIO_PORT, &gpio_init_structure); + + gpio_init_structure.Pin = BUS_I2C1_SDA_PIN; + gpio_init_structure.Mode = GPIO_MODE_AF_OD; + gpio_init_structure.Pull = GPIO_NOPULL; + gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH; + gpio_init_structure.Alternate = BUS_I2C1_SDA_AF; + HAL_GPIO_Init(BUS_I2C1_SDA_GPIO_PORT, &gpio_init_structure); + + __HAL_RCC_I2C1_CLK_ENABLE(); + __HAL_RCC_I2C1_FORCE_RESET(); + __HAL_RCC_I2C1_RELEASE_RESET(); + + if (MX_I2C1_Init(&hbus_i2c1, /*0x10C0ECFF*/ 1890596921) != HAL_OK) { + return -1; + } + + return 0; +} + +int32_t BSP_I2C1_DeInit(void) { + return 0; +} + +int32_t BSP_I2C1_ReadReg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { + if (HAL_OK != HAL_I2C_Mem_Read(&hbus_i2c1, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)) { + return -1; + } + return 0; } +int32_t BSP_I2C1_WriteReg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { + if(HAL_OK != HAL_I2C_Mem_Write(&hbus_i2c1, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)) { + return -1; + } + return 0; +} + + +static inline void board_init2(void) { + // Init MFX IO expanding for vbus drive + BSP_I2C1_Init(); + + /* Configure the audio driver */ + MFXSTM32L152_IO_t IOCtx; + IOCtx.Init = BSP_I2C1_DeInit; + IOCtx.DeInit = BSP_I2C1_DeInit; + IOCtx.ReadReg = BSP_I2C1_ReadReg; + IOCtx.WriteReg = BSP_I2C1_WriteReg; + IOCtx.GetTick = (MFXSTM32L152_GetTick_Func) HAL_GetTick; + + uint8_t i2c_address[] = {0x84, 0x86}; + for(uint8_t i = 0U; i < 2U; i++) { + uint32_t mfx_id; + IOCtx.Address = (uint16_t)i2c_address[i]; + if (MFXSTM32L152_RegisterBusIO(&mfx_obj, &IOCtx) != MFXSTM32L152_OK) { + return; + } + if (MFXSTM32L152_ReadID(&mfx_obj, &mfx_id) != MFXSTM32L152_OK) { + return; + } + + if ((mfx_id == MFXSTM32L152_ID) || (mfx_id == MFXSTM32L152_ID_2)) { + if (MFXSTM32L152_Init(&mfx_obj) != MFXSTM32L152_OK) { + return; + } + break; + } + } + + mfx_io_drv = &MFXSTM32L152_IO_Driver; + + static MFXSTM32L152_IO_Init_t io_init = { 0 }; + mfx_io_drv->Init(&mfx_obj, &io_init); + + io_init.Pin = MFXSTM32L152_GPIO_PIN_7; + io_init.Mode = MFXSTM32L152_GPIO_MODE_OUTPUT_PP; + io_init.Pull = MFXSTM32L152_GPIO_PULLUP; + mfx_io_drv->Init(&mfx_obj, &io_init); // VBUS[0] + + io_init.Pin = MFXSTM32L152_GPIO_PIN_9; + mfx_io_drv->Init(&mfx_obj, &io_init); // VBUS[1] + +#if 1 // write then read IO7 but it does not seems to change value + int32_t pin_value; + pin_value = mfx_io_drv->IO_ReadPin(&mfx_obj, MFXSTM32L152_GPIO_PIN_7); + TU_LOG1_INT(pin_value); + + mfx_io_drv->IO_WritePin(&mfx_obj, MFXSTM32L152_GPIO_PIN_7, 1); + + pin_value = mfx_io_drv->IO_ReadPin(&mfx_obj, MFXSTM32L152_GPIO_PIN_7); + TU_LOG1_INT(pin_value); +#endif +} + + #ifdef __cplusplus } #endif diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc index 01458a0a9..0e5a4cc00 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc +++ b/hw/bsp/stm32h7/boards/stm32h743eval/cubemx/stm32h743eval.ioc @@ -4,17 +4,20 @@ CAD.pinconfig=Project naming CAD.provider= File.Version=6 GPIO.groupedBy=Group By Peripherals +I2C1.IPParameters=Timing +I2C1.Timing=0x10C0ECFF KeepUserPlacement=false Mcu.CPN=STM32H743XIH6 Mcu.Family=STM32H7 Mcu.IP0=CORTEX_M7 Mcu.IP1=DEBUG -Mcu.IP2=NVIC -Mcu.IP3=RCC -Mcu.IP4=SYS -Mcu.IP5=USB_OTG_FS -Mcu.IP6=USB_OTG_HS -Mcu.IPNb=7 +Mcu.IP2=I2C1 +Mcu.IP3=NVIC +Mcu.IP4=RCC +Mcu.IP5=SYS +Mcu.IP6=USB_OTG_FS +Mcu.IP7=USB_OTG_HS +Mcu.IPNb=8 Mcu.Name=STM32H743XIHx Mcu.Package=TFBGA240 Mcu.Pin0=PI6 @@ -190,8 +193,8 @@ Mcu.PinsNb=169 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32H743XIHx -MxCube.Version=6.8.1 -MxDb.Version=DB.6.0.81 +MxCube.Version=6.10.0 +MxDb.Version=DB.6.0.100 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:true\:false\:false NVIC.ForceEnableDMAVector=true @@ -325,10 +328,12 @@ PB5.Signal=USB_OTG_HS_ULPI_D7 PB6.GPIOParameters=GPIO_Label PB6.GPIO_Label=I2C1_SCL [STM32L152CCT6_I2C_SCL] PB6.Locked=true +PB6.Mode=I2C PB6.Signal=I2C1_SCL PB7.GPIOParameters=GPIO_Label PB7.GPIO_Label=I2C1_SDA [STM32L152CCT6_I2C_SDA] PB7.Locked=true +PB7.Mode=I2C PB7.Signal=I2C1_SDA PB8.GPIOParameters=GPIO_Label PB8.GPIO_Label=SDIO1_CKIN @@ -880,7 +885,7 @@ ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 ProjectManager.KeepUserCode=true -ProjectManager.LastFirmware=true +ProjectManager.LastFirmware=false ProjectManager.LibraryCopy=2 ProjectManager.MainLocation=Src ProjectManager.NoMain=false @@ -893,8 +898,10 @@ ProjectManager.RegisterCallBack= ProjectManager.StackSize=0x400 ProjectManager.TargetToolchain=Makefile ProjectManager.ToolChainLocation=Src/ +ProjectManager.UAScriptAfterPath= +ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,4-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-false-HAL-true,4-MX_I2C1_Init-I2C1-false-HAL-true,5-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true RCC.ADCFreq_Value=50390625 RCC.AHB12Freq_Value=200000000 RCC.AHB4Freq_Value=200000000 diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h index 614e6e38b..513ce2bb7 100644 --- a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h +++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h @@ -122,7 +122,7 @@ static inline void SystemClock_Config(void) { } } -static inline void board_stm32h7_post_init(void) +static inline void board_init2(void) { // For this board does nothing } diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.h b/hw/bsp/stm32h7/boards/stm32h745disco/board.h index 6d1506ca1..c0f85ddbe 100644 --- a/hw/bsp/stm32h7/boards/stm32h745disco/board.h +++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.h @@ -127,7 +127,7 @@ static inline void SystemClock_Config(void) HAL_EnableCompensationCell(); } -static inline void board_stm32h7_post_init(void) +static inline void board_init2(void) { // For this board does nothing } diff --git a/hw/bsp/stm32h7/boards/stm32h750_weact/board.h b/hw/bsp/stm32h7/boards/stm32h750_weact/board.h index d117637a5..5beab20ce 100644 --- a/hw/bsp/stm32h7/boards/stm32h750_weact/board.h +++ b/hw/bsp/stm32h7/boards/stm32h750_weact/board.h @@ -121,7 +121,7 @@ static inline void SystemClock_Config(void) { HAL_PWREx_EnableUSBVoltageDetector(); } -static inline void board_stm32h7_post_init(void) { +static inline void board_init2(void) { // For this board does nothing } diff --git a/hw/bsp/stm32h7/boards/stm32h750bdk/board.h b/hw/bsp/stm32h7/boards/stm32h750bdk/board.h index c5922efc4..b0b063cda 100644 --- a/hw/bsp/stm32h7/boards/stm32h750bdk/board.h +++ b/hw/bsp/stm32h7/boards/stm32h750bdk/board.h @@ -132,7 +132,7 @@ static inline void SystemClock_Config(void) HAL_EnableCompensationCell(); } -static inline void board_stm32h7_post_init(void) +static inline void board_init2(void) { // For this board does nothing } diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h index 8f4af6f48..46efca6fb 100644 --- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h +++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h @@ -184,7 +184,7 @@ static inline void timer_board_delay(TIM_HandleTypeDef* tim_hdl, uint32_t ms) } } -static inline void board_stm32h7_post_init(void) +static inline void board_init2(void) { // walkaround for resetting the ULPI PHY using Timer since systick is not // available when RTOS is used. diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c index 3bed1f5ec..c8b7c6fe3 100644 --- a/hw/bsp/stm32h7/family.c +++ b/hw/bsp/stm32h7/family.c @@ -236,7 +236,12 @@ void board_init(void) { HAL_PWREx_EnableUSBVoltageDetector(); // For waveshare openh743 ULPI PHY reset walkaround - board_stm32h7_post_init(); + board_init2(); + +#if CFG_TUH_ENABLED && defined(BOARD_VBUS_DRIVE) + BOARD_VBUS_DRIVE(BOARD_TUH_RHPORT, 1); +#endif + } //--------------------------------------------------------------------+ diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake index e4161ffe5..d0fb963a9 100644 --- a/hw/bsp/stm32h7/family.cmake +++ b/hw/bsp/stm32h7/family.cmake @@ -5,6 +5,7 @@ set(ST_PREFIX stm32${ST_FAMILY}xx) set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver) set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY}) +set(MFXSTM32L152 ${TOP}/hw/mcu/st/stm32-mfxstm32l152) set(CMSIS_5 ${TOP}/lib/CMSIS_5) # include board specific @@ -42,6 +43,8 @@ function(add_board_target BOARD_TARGET) ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_i2c.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_i2c_ex.c ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c @@ -49,12 +52,16 @@ function(add_board_target BOARD_TARGET) ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + # MFXSTM32L152 + ${MFXSTM32L152}/mfxstm32l152.c + ${MFXSTM32L152}/mfxstm32l152_reg.c ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} ${CMSIS_5}/CMSIS/Core/Include ${ST_CMSIS}/Include ${ST_HAL_DRIVER}/Inc + ${MFXSTM32L152} ) #target_compile_options(${BOARD_TARGET} PUBLIC) #target_compile_definitions(${BOARD_TARGET} PUBLIC) diff --git a/hw/bsp/stm32h7/stm32h7xx_hal_conf.h b/hw/bsp/stm32h7/stm32h7xx_hal_conf.h index 216fc82f2..303dcc137 100644 --- a/hw/bsp/stm32h7/stm32h7xx_hal_conf.h +++ b/hw/bsp/stm32h7/stm32h7xx_hal_conf.h @@ -70,7 +70,7 @@ /* #define HAL_HCD_MODULE_ENABLED */ /* #define HAL_HRTIM_MODULE_ENABLED */ /* #define HAL_HSEM_MODULE_ENABLED */ -/* #define HAL_I2C_MODULE_ENABLED */ +#define HAL_I2C_MODULE_ENABLED /* #define HAL_I2S_MODULE_ENABLED */ /* #define HAL_IRDA_MODULE_ENABLED */ /* #define HAL_IWDG_MODULE_ENABLED */ diff --git a/tools/get_deps.py b/tools/get_deps.py index 519cb1d53..6d0ef9d0c 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -121,6 +121,9 @@ deps_optional = { 'hw/mcu/st/cmsis_device_wb': ['https://github.com/STMicroelectronics/cmsis_device_wb.git', '9c5d1920dd9fabbe2548e10561d63db829bb744f', 'stm32wb'], + 'hw/mcu/st/stm32-mfxstm32l152': ['https://github.com/STMicroelectronics/stm32-mfxstm32l152.git', + '7f4389efee9c6a655b55e5df3fceef5586b35f9b', + 'stm32h7'], 'hw/mcu/st/stm32f0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git', '0e95cd88657030f640a11e690a8a5186c7712ea5', 'stm32f0'], -- cgit v1.3.1 From 61b33ca926065cd25a2045077ab96dd990ce2560 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 18 Oct 2024 22:16:21 +0700 Subject: testing hcd with f723 due to h743eval issue with mfx vbus drive. --- hw/bsp/stm32f7/boards/stm32f723disco/board.cmake | 2 +- hw/bsp/stm32f7/boards/stm32f723disco/board.h | 41 ++++++++++++++++++++++-- hw/bsp/stm32f7/family.c | 24 ++++++-------- src/common/tusb_types.h | 4 +-- 4 files changed, 50 insertions(+), 21 deletions(-) (limited to 'hw') diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake b/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake index dd3c35b00..8a7b4cb27 100644 --- a/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake +++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake @@ -1,6 +1,6 @@ set(MCU_VARIANT stm32f723xx) set(JLINK_DEVICE stm32f723ie) - +#set(JLINK_OPTION "-USB 000776606156") set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F723xE_FLASH.ld) function(update_board TARGET) diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.h b/hw/bsp/stm32f7/boards/stm32f723disco/board.h index 258786b7f..178fd6e5e 100644 --- a/hw/bsp/stm32f7/boards/stm32f723disco/board.h +++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.h @@ -56,8 +56,7 @@ //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ -static inline void board_clock_init(void) -{ +static inline void board_clock_init(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; @@ -74,7 +73,7 @@ static inline void board_clock_init(void) RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; - RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; + RCC_OscInitStruct.PLL.PLLM = HSE_VALUE / 1000000; RCC_OscInitStruct.PLL.PLLN = 432; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 9; @@ -98,6 +97,42 @@ static inline void board_clock_init(void) // //} +typedef struct { + GPIO_TypeDef* port; + GPIO_InitTypeDef pin_init; + bool active_state; +} board_pindef_t; + +static board_pindef_t vbus_pindef[] = { +{ + .port = GPIOG, + .pin_init = { + .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_OUTPUT_OD, .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_HIGH, .Alternate = 0 + }, + .active_state = false + }, +{ + .port = GPIOH, + .pin_init = { + .Pin = GPIO_PIN_12, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_NOPULL, + .Speed = GPIO_SPEED_HIGH, .Alternate = 0 + }, + .active_state = true + }, +}; + +static inline void board_vbus_set(uint8_t rhport, bool state) { + static bool pin_inited[2] = { false, false }; + board_pindef_t* pindef = &vbus_pindef[rhport]; + if (!pin_inited[rhport]) { + HAL_GPIO_Init(pindef->port, &pindef->pin_init); + pin_inited[rhport] = true; + } + + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET); +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c index 61f1d2a7f..1f49d7693 100644 --- a/hw/bsp/stm32f7/family.c +++ b/hw/bsp/stm32f7/family.c @@ -34,13 +34,13 @@ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ void OTG_FS_IRQHandler(void) { - tud_int_handler(0); + tusb_int_handler(0, true); } // Despite being call USB2_OTG // OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port void OTG_HS_IRQHandler(void) { - tud_int_handler(1); + tusb_int_handler(1, true); } //--------------------------------------------------------------------+ @@ -65,7 +65,7 @@ void board_init(void) { __HAL_RCC_GPIOJ_CLK_ENABLE(); #endif - UART_CLK_EN(); + UART_CLK_EN(); #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer @@ -122,9 +122,7 @@ void board_init(void) { UartHandle.Init.OverSampling = UART_OVERSAMPLING_16; HAL_UART_Init(&UartHandle); -#if BOARD_TUD_RHPORT == 0 - // OTG_FS - + //------------- rhport0: OTG_FS -------------// /* Configure DM DP Pins */ GPIO_InitStruct.Pin = (GPIO_PIN_11 | GPIO_PIN_12); GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -171,9 +169,7 @@ void board_init(void) { USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; #endif // vbus sense -#else - // OTG_HS - + //------------- rhport1: OTG_HS -------------// #ifdef USB_HS_PHYC // MCU with built-in HS PHY such as F723, F733, F730 @@ -261,12 +257,10 @@ void board_init(void) { USB_OTG_HS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; #endif - // Force device mode - USB_OTG_HS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD; - USB_OTG_HS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; - -#endif // BOARD_TUD_RHPORT - + // Turn on host vbus +#if CFG_TUH_ENABLED + board_vbus_set(BOARD_TUH_RHPORT, true); +#endif } //--------------------------------------------------------------------+ diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 53bb367cb..0faa6eee9 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -41,8 +41,8 @@ typedef enum { TUSB_ROLE_INVALID = 0, - TUSB_ROLE_DEVICE, - TUSB_ROLE_HOST, + TUSB_ROLE_DEVICE = 0x1, + TUSB_ROLE_HOST = 0x2, } tusb_role_t; /// defined base on EHCI specs value for Endpoint Speed -- cgit v1.3.1 From 8461525d48cb4a97a7b18816f65b548a875ffe50 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 21 Oct 2024 17:45:40 +0700 Subject: add tusb_time_millis(), able to reset and enable dwc2 port and get SOF active --- hw/bsp/board.c | 5 ++ src/host/usbh.c | 21 ++++++--- src/portable/synopsys/dwc2/dwc2_common.c | 8 ++++ src/portable/synopsys/dwc2/dwc2_info.md | 2 +- src/portable/synopsys/dwc2/dwc2_info.py | 6 ++- src/portable/synopsys/dwc2/dwc2_type.h | 20 +++++--- src/portable/synopsys/dwc2/hcd_dwc2.c | 81 +++++++++++++++++++++++++++----- src/tusb.h | 10 ++-- 8 files changed, 123 insertions(+), 30 deletions(-) (limited to 'hw') diff --git a/hw/bsp/board.c b/hw/bsp/board.c index bb339f613..d4fdb7586 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -134,3 +134,8 @@ int board_getchar(void) { char c; return (sys_read(0, &c, 1) > 0) ? (int) c : (-1); } + + +uint32_t tusb_time_millis(void) { + return board_millis(); +} diff --git a/src/host/usbh.c b/src/host/usbh.c index b5df29f50..8bf40a607 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -447,9 +447,9 @@ bool tuh_deinit(uint8_t rhport) { } bool tuh_task_event_ready(void) { - // Skip if stack is not initialized - if ( !tuh_inited() ) return false; - + if (!tuh_inited()) { + return false; // Skip if stack is not initialized + } return !osal_queue_empty(_usbh_q); } @@ -1520,10 +1520,17 @@ static bool enum_new_device(hcd_event_t* event) { _dev0.hub_port = event->connection.hub_port; if (_dev0.hub_addr == 0) { - // connected/disconnected directly with roothub + // connected directly to roothub hcd_port_reset(_dev0.rhport); - osal_task_delay(ENUM_RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since - // sof of controller may not running while resetting +#if CFG_TUSB_OS == OPT_OS_NONE + // Since we are in middle of rhport reset, frame number is not available for time delay + // need to depend on tusb_time_millis() instead + const uint32_t start_reset = tusb_time_millis(); + while ((tusb_time_millis() - start_reset) < ENUM_RESET_DELAY) {} +#else + osal_task_delay(ENUM_RESET_DELAY); +#endif + hcd_port_reset_end(_dev0.rhport); // wait until device connection is stable TODO non blocking @@ -1548,7 +1555,7 @@ static bool enum_new_device(hcd_event_t* event) { } #if CFG_TUH_HUB else { - // connected/disconnected via external hub + // connected via external hub // wait until device connection is stable TODO non blocking osal_task_delay(ENUM_CONTACT_DEBOUNCING_DELAY); diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index a5f1c2b08..d0ad764a5 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -185,6 +185,14 @@ bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED; } +/* dwc2 has several PHYs option + * - UTMI+ is internal highspeed PHY, clock can be 30 Mhz (8-bit) or 60 Mhz (16-bit) + * - ULPI is external highspeed PHY, clock is 60Mhz with only 8-bit interface + * - Dedicated FS PHY is internal with clock 48Mhz. + * + * In addition, UTMI+/ULPI can be shared to run at fullspeed mode with 48Mhz + * +*/ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index cfd0c81a8..92293a072 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -7,7 +7,7 @@ | GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | | - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | | - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | DMA internal | -| - p2p (hub support) | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | +| - single_point | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | hub | n/a | | - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | | - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | n/a | Dedicated | | - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index d1793a005..d97a1192e 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -44,7 +44,7 @@ class GHWCFG2(ctypes.LittleEndianStructure): _fields_ = [ ("op_mode", ctypes.c_uint32, 3), ("arch", ctypes.c_uint32, 2), - ("p2p (hub support)", ctypes.c_uint32, 1), + ("single_point", ctypes.c_uint32, 1), ("hs_phy_type", ctypes.c_uint32, 2), ("fs_phy_type", ctypes.c_uint32, 2), ("num_dev_ep", ctypes.c_uint32, 4), @@ -119,6 +119,10 @@ GHWCFG2_field = { 1: "DMA external", 2: "DMA internal" }, + 'single_point': { + 0: "hub", + 1: "n/a" + }, 'hs_phy_type': { 0: "n/a", 1: "UTMI+", diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 8fb926a21..d2993bdd9 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -208,7 +208,7 @@ typedef struct TU_ATTR_PACKED { based on the speed of enumeration. The number of bit times added per PHY clock are as follows: - High-speed: PHY clock One 30-MHz = 16 bit times, One 60-MHz = 8 bit times - Full-speed: PHY clock One 30-MHz = 0.4 bit times, One 60-MHz = 0.2 bit times, One 48-MHz = 0.25 bit times */ - uint32_t phy_if : 1; // 3 PHY interface. 0: 8 bits, 1: 16 bits + uint32_t phy_if16 : 1; // 3 PHY interface. 0: 8 bits, 1: 16 bits uint32_t ulpi_utmi_sel : 1; // 4 ULPI/UTMI select. 0: UTMI+, 1: ULPI uint32_t fs_intf_sel : 1; // 5 Fullspeed serial interface select. 0: 6-pin, 1: 3-pin uint32_t phy_sel : 1; // 6 HS/FS PHY selection. 0: HS UTMI+ or ULPI, 1: FS serial transceiver @@ -259,7 +259,7 @@ TU_VERIFY_STATIC(sizeof(dwc2_grstctl_t) == 4, "incorrect size"); typedef struct TU_ATTR_PACKED { uint32_t op_mode : 3; // 0..2 HNP/SRP Host/Device/OTG mode uint32_t arch : 2; // 3..4 Slave/External/Internal DMA - uint32_t point2point : 1; // 5 0: support hub and split | 1: no hub, no split + uint32_t single_point : 1; // 5 0: support hub and split | 1: no hub, no split uint32_t hs_phy_type : 2; // 6..7 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI uint32_t fs_phy_type : 2; // 8..9 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI uint32_t num_dev_ep : 4; // 10..13 Number of device endpoints (excluding EP0) @@ -407,7 +407,10 @@ typedef struct { }; volatile uint32_t gotgint; // 004 OTG Interrupt volatile uint32_t gahbcfg; // 008 AHB Configuration + union { volatile uint32_t gusbcfg; // 00c USB Configuration + volatile dwc2_gusbcfg_t gusbcfg_bm; + }; volatile uint32_t grstctl; // 010 Reset volatile uint32_t gintsts; // 014 Interrupt volatile uint32_t gintmsk; // 018 Interrupt Mask @@ -459,7 +462,10 @@ typedef struct { volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask volatile uint32_t hflbaddr; // 41C Host Frame List Base Address uint32_t reserved420[8]; // 420..43F + union { volatile uint32_t hprt; // 440 Host Port Control and Status + volatile dwc2_hprt_t hprt_bm; + }; uint32_t reserved444[47]; // 444..4FF //------------- Host Channel -------------// @@ -1490,14 +1496,14 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define HPRT_CONN_STATUS_Msk (0x1UL << HPRT_CONN_STATUS_Pos) // 0x00000001 #define HPRT_CONN_STATUS HPRT_CONN_STATUS_Msk // Port connect status #define HPRT_CONN_DETECT_Pos (1U) -#define HPRT_CONN_DETECT_Msk (0x1UL << HPRT_CONN_DETECT_Pos) // 0x00000002 -#define HPRT_CONN_DETECT HPRT_CONN_DETECT_Msk // Port connect detected +#define HPRT_CONN_DETECT_Msk (0x1UL << HPRT_CONN_DETECT_Pos) // 0x00000002 +#define HPRT_CONN_DETECT HPRT_CONN_DETECT_Msk // Port connect detected #define HPRT_ENABLE_Pos (2U) #define HPRT_ENABLE_Msk (0x1UL << HPRT_ENABLE_Pos) // 0x00000004 #define HPRT_ENABLE HPRT_ENABLE_Msk // Port enable -#define HPRT_EN_CHANGE_Pos (3U) -#define HPRT_EN_CHANGE_Msk (0x1UL << HPRT_EN_CHANGE_Pos) // 0x00000008 -#define HPRT_EN_CHANGE HPRT_EN_CHANGE_Msk // Port enable/disable change +#define HPRT_ENABLE_CHANGE_Pos (3U) +#define HPRT_ENABLE_CHANGE_Msk (0x1UL << HPRT_ENABLE_CHANGE_Pos) // 0x00000008 +#define HPRT_ENABLE_CHANGE HPRT_ENABLE_CHANGE_Msk // Port enable/disable change #define HPRT_OVER_CURRENT_ACTIVE_Pos (4U) #define HPRT_OVER_CURRENT_ACTIVE_Msk (0x1UL << HPRT_OVER_CURRENT_ACTIVE_Pos) // 0x00000010 #define HPRT_OVER_CURRENT_ACTIVE HPRT_OVER_CURRENT_ACTIVE_Msk // Port overcurrent active diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 2d4368e94..bb5086631 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -35,9 +35,20 @@ #include "dwc2_common.h" enum { - HPRT_W1C_MASK = HPRT_CONN_DETECT | HPRT_ENABLE | HPRT_EN_CHANGE | HPRT_OVER_CURRENT_CHANGE + HPRT_W1C_MASK = HPRT_CONN_DETECT | HPRT_ENABLE | HPRT_ENABLE_CHANGE | HPRT_OVER_CURRENT_CHANGE }; +TU_ATTR_ALWAYS_INLINE static inline tusb_speed_t convert_hprt_speed(uint32_t hprt_speed) { + tusb_speed_t speed; + switch(hprt_speed) { + case HPRT_SPEED_HIGH: speed = TUSB_SPEED_HIGH; break; + case HPRT_SPEED_FULL: speed = TUSB_SPEED_FULL; break; + case HPRT_SPEED_LOW : speed = TUSB_SPEED_LOW ; break; + default: TU_BREAKPOINT(); break; + } + return speed; +} + //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ @@ -81,6 +92,8 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { } dwc2->hcfg = hcfg; + // Enable HFIR reload + // force host mode and wait for mode switch dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD; while( (dwc2->gintsts & GINTSTS_CMOD) != GINTSTS_CMODE_HOST) {} @@ -107,8 +120,8 @@ void hcd_int_disable(uint8_t rhport) { // Get frame number (1ms) uint32_t hcd_frame_number(uint8_t rhport) { - (void) rhport; - return 0; + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + return dwc2->hfnum & HFNUM_FRNUM_Msk; } //--------------------------------------------------------------------+ @@ -125,7 +138,9 @@ bool hcd_port_connect_status(uint8_t rhport) { // Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence. void hcd_port_reset(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - dwc2->hprt = HPRT_RESET; + uint32_t hprt = dwc2->hprt & ~HPRT_W1C_MASK; + hprt |= HPRT_RESET; + dwc2->hprt = hprt; } // Complete bus reset sequence, may be required by some controllers @@ -138,9 +153,9 @@ void hcd_port_reset_end(uint8_t rhport) { // Get port link speed tusb_speed_t hcd_port_speed_get(uint8_t rhport) { - (void) rhport; - - return TUSB_SPEED_FULL; + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + const tusb_speed_t speed = convert_hprt_speed(dwc2->hprt_bm.speed); + return speed; } // HCD closes all opened endpoints belong to this device @@ -227,18 +242,62 @@ static void handle_rxflvl_irq(uint8_t rhport) { */ TU_ATTR_ALWAYS_INLINE static inline void handle_hprt_irq(uint8_t rhport, bool in_isr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint32_t hprt = dwc2->hprt; + uint32_t hprt = dwc2->hprt & ~HPRT_W1C_MASK; + const dwc2_hprt_t hprt_bm = dwc2->hprt_bm; - if (hprt & HPRT_CONN_DETECT) { + if (dwc2->hprt & HPRT_CONN_DETECT) { // Port Connect Detect - dwc2->hprt = HPRT_CONN_DETECT; // clear + hprt |= HPRT_CONN_DETECT; - if (hprt & HPRT_CONN_STATUS) { + if (hprt_bm.conn_status) { hcd_event_device_attach(rhport, in_isr); } else { hcd_event_device_remove(rhport, in_isr); } } + + if (dwc2->hprt & HPRT_ENABLE_CHANGE) { + // Port enable change + hprt |= HPRT_ENABLE_CHANGE; + + if (hprt_bm.enable) { + // Port enable + // Config HCFG FS/LS clock and HFIR for SOF interval according to link speed (value is in PHY clock unit) + const tusb_speed_t speed = convert_hprt_speed(hprt_bm.speed); + uint32_t hcfg = dwc2->hcfg & ~HCFG_FSLS_PHYCLK_SEL; + + const dwc2_gusbcfg_t gusbcfg_bm = dwc2->gusbcfg_bm; + uint32_t clock = 60; + if (gusbcfg_bm.phy_sel) { + // dedicated FS is 48Mhz + clock = 48; + hcfg |= HCFG_FSLS_PHYCLK_SEL_48MHZ; + } else { + // UTMI+ or ULPI + if (gusbcfg_bm.ulpi_utmi_sel) { + clock = 60; // ULPI 8-bit is 60Mhz + } else if (gusbcfg_bm.phy_if16) { + clock = 30; // UTMI+ 16-bit is 30Mhz + } else { + clock = 60; // UTMI+ 8-bit is 60Mhz + } + hcfg |= HCFG_FSLS_PHYCLK_SEL_30_60MHZ; + } + + dwc2->hcfg = hcfg; + + uint32_t hfir = dwc2->hfir & ~HFIR_FRIVL_Msk; + if (speed == TUSB_SPEED_HIGH) { + hfir |= 125*clock; + } else { + hfir |= 1000*clock; + } + + dwc2->hfir = hfir; + } + } + + dwc2->hprt = hprt; // clear interrupt } /* Interrupt Hierarchy diff --git a/src/tusb.h b/src/tusb.h index 2f30a5739..3ffaafded 100644 --- a/src/tusb.h +++ b/src/tusb.h @@ -127,10 +127,8 @@ //--------------------------------------------------------------------+ -// APPLICATION API +// User API //--------------------------------------------------------------------+ - - #if CFG_TUH_ENABLED || CFG_TUD_ENABLED // Internal helper for backward compatible with tusb_init(void) @@ -167,6 +165,12 @@ void tusb_int_handler(uint8_t rhport, bool in_isr); #endif +//--------------------------------------------------------------------+ +// API Implemented by user +//--------------------------------------------------------------------+ + +// Get current milliseconds, maybe required by some port with no RTOS +uint32_t tusb_time_millis(void); #ifdef __cplusplus } -- cgit v1.3.1 From 77fa2f67019647b063eab139afa01a5036ad4d40 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 25 Oct 2024 19:08:23 +0700 Subject: fix make build --- hw/bsp/broadcom_32bit/family.mk | 2 ++ hw/bsp/broadcom_64bit/family.mk | 2 ++ hw/bsp/gd32vf103/family.mk | 2 ++ hw/bsp/sltb009a/board.mk | 4 +++- hw/bsp/stm32f2/family.mk | 2 ++ hw/bsp/stm32f4/family.mk | 2 ++ hw/bsp/stm32f7/family.mk | 2 ++ hw/bsp/stm32h7/family.mk | 2 ++ hw/bsp/stm32l4/family.mk | 2 ++ hw/bsp/stm32u5/family.mk | 4 +++- hw/bsp/xmc4000/family.mk | 2 ++ 11 files changed, 24 insertions(+), 2 deletions(-) (limited to 'hw') diff --git a/hw/bsp/broadcom_32bit/family.mk b/hw/bsp/broadcom_32bit/family.mk index e15bd93f7..a282e9961 100644 --- a/hw/bsp/broadcom_32bit/family.mk +++ b/hw/bsp/broadcom_32bit/family.mk @@ -19,6 +19,8 @@ CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ $(MCU_DIR)/broadcom/gen/interrupt_handlers.c \ $(MCU_DIR)/broadcom/gpio.c \ $(MCU_DIR)/broadcom/interrupts.c \ diff --git a/hw/bsp/broadcom_64bit/family.mk b/hw/bsp/broadcom_64bit/family.mk index 89f798f19..37d381f9f 100644 --- a/hw/bsp/broadcom_64bit/family.mk +++ b/hw/bsp/broadcom_64bit/family.mk @@ -18,6 +18,8 @@ CFLAGS += -Wno-error=cast-qual -Wno-error=redundant-decls SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ $(MCU_DIR)/broadcom/gen/interrupt_handlers.c \ $(MCU_DIR)/broadcom/gpio.c \ $(MCU_DIR)/broadcom/interrupts.c \ diff --git a/hw/bsp/gd32vf103/family.mk b/hw/bsp/gd32vf103/family.mk index 48588886c..75b3efb33 100644 --- a/hw/bsp/gd32vf103/family.mk +++ b/hw/bsp/gd32vf103/family.mk @@ -31,6 +31,8 @@ CFLAGS += -Wno-error=unused-parameter SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ $(GD32VF103_SDK_DRIVER)/gd32vf103_gpio.c \ $(GD32VF103_SDK_DRIVER)/gd32vf103_rcu.c \ $(GD32VF103_SDK_DRIVER)/gd32vf103_usart.c \ diff --git a/hw/bsp/sltb009a/board.mk b/hw/bsp/sltb009a/board.mk index a04bc19d8..687761364 100644 --- a/hw/bsp/sltb009a/board.mk +++ b/hw/bsp/sltb009a/board.mk @@ -26,7 +26,9 @@ LD_FILE = $(SILABS_CMSIS)/Source/GCC/$(SILABS_FAMILY).ld SRC_C += \ $(SILABS_CMSIS)/Source/system_$(SILABS_FAMILY).c \ - src/portable/synopsys/dwc2/dcd_dwc2.c + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ SRC_S += \ $(SILABS_CMSIS)/Source/GCC/startup_$(SILABS_FAMILY).S diff --git a/hw/bsp/stm32f2/family.mk b/hw/bsp/stm32f2/family.mk index 7e71f6eed..7af9a76a0 100644 --- a/hw/bsp/stm32f2/family.mk +++ b/hw/bsp/stm32f2/family.mk @@ -26,6 +26,8 @@ LDFLAGS_GCC += \ SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk index 523a1cb04..70c9cdf42 100644 --- a/hw/bsp/stm32f4/family.mk +++ b/hw/bsp/stm32f4/family.mk @@ -34,6 +34,8 @@ LDFLAGS_GCC += \ SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk index bae7d6d5b..4e9cc152d 100644 --- a/hw/bsp/stm32f7/family.mk +++ b/hw/bsp/stm32f7/family.mk @@ -45,6 +45,8 @@ LDFLAGS_GCC += \ SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk index 40df190db..d46324a2d 100644 --- a/hw/bsp/stm32h7/family.mk +++ b/hw/bsp/stm32h7/family.mk @@ -46,6 +46,8 @@ LDFLAGS_GCC += \ SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ diff --git a/hw/bsp/stm32l4/family.mk b/hw/bsp/stm32l4/family.mk index 411436cf6..950b6f9cb 100644 --- a/hw/bsp/stm32l4/family.mk +++ b/hw/bsp/stm32l4/family.mk @@ -32,6 +32,8 @@ LDFLAGS_GCC += \ SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk index 89193b99f..0e3c54c4b 100644 --- a/hw/bsp/stm32u5/family.mk +++ b/hw/bsp/stm32u5/family.mk @@ -46,7 +46,9 @@ SRC_C += \ src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c else SRC_C += \ - src/portable/synopsys/dwc2/dcd_dwc2.c + src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ endif INC += \ diff --git a/hw/bsp/xmc4000/family.mk b/hw/bsp/xmc4000/family.mk index 80b38acef..a1679a2f0 100644 --- a/hw/bsp/xmc4000/family.mk +++ b/hw/bsp/xmc4000/family.mk @@ -16,6 +16,8 @@ CFLAGS += \ SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ + src/portable/synopsys/dwc2/hcd_dwc2.c \ + src/portable/synopsys/dwc2/dwc2_common.c \ ${SDK_DIR}/CMSIS/Infineon/COMPONENT_${MCU_VARIANT}/Source/system_${MCU_VARIANT}.c \ ${SDK_DIR}/Newlib/syscalls.c \ ${SDK_DIR}/XMCLib/src/xmc_gpio.c \ -- cgit v1.3.1 From 79c0a249e878c425f3a5f926f444bb5178a748ef Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 25 Oct 2024 22:56:11 +0700 Subject: got In transfer working, able to get 1st device descriptor and set address --- hw/bsp/stm32u5/family.mk | 2 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 30 +++---- src/portable/synopsys/dwc2/dwc2_common.c | 3 - src/portable/synopsys/dwc2/dwc2_type.h | 40 +++++++--- src/portable/synopsys/dwc2/hcd_dwc2.c | 130 +++++++++++++++++++++---------- 5 files changed, 135 insertions(+), 70 deletions(-) (limited to 'hw') diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk index 0e3c54c4b..05fe4608a 100644 --- a/hw/bsp/stm32u5/family.mk +++ b/hw/bsp/stm32u5/family.mk @@ -48,7 +48,7 @@ else SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ src/portable/synopsys/dwc2/hcd_dwc2.c \ - src/portable/synopsys/dwc2/dwc2_common.c \ + src/portable/synopsys/dwc2/dwc2_common.c endif INC += \ diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index b389b0f74..a04f03b50 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -445,8 +445,11 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Enable required interrupts dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM; - // Enable global interrupt - dwc2->gahbcfg |= GAHBCFG_GINT; + // TX FIFO empty level for interrupt is complete empty + uint32_t gahbcfg = dwc2->gahbcfg; + gahbcfg |= GAHBCFG_TX_FIFO_EPMTY_LVL; + gahbcfg |= GAHBCFG_GINT; // Enable global interrupt + dwc2->gahbcfg = gahbcfg; dcd_connect(rhport); return true; @@ -671,16 +674,15 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { // Process shared receive FIFO, this interrupt is only used in Slave mode static void handle_rxflvl_irq(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - volatile uint32_t const* rx_fifo = dwc2->fifo[0]; + const volatile uint32_t* rx_fifo = dwc2->fifo[0]; // Pop control word off FIFO - uint32_t const grxstsp = dwc2->grxstsp; - uint8_t const pktsts = (grxstsp & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; - uint8_t const epnum = (grxstsp & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; - uint16_t const bcnt = (grxstsp & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; + const dwc2_grxstsp_t grxstsp_bm = dwc2->grxstsp_bm; + const uint8_t epnum = grxstsp_bm.ep_ch_num; + const uint16_t byte_count = grxstsp_bm.byte_count; dwc2_epout_t* epout = &dwc2->epout[epnum]; - switch (pktsts) { + switch (grxstsp_bm.packet_status) { // Global OUT NAK: do nothing case GRXSTS_PKTSTS_GLOBALOUTNAK: break; @@ -705,18 +707,18 @@ static void handle_rxflvl_irq(uint8_t rhport) { // Read packet off RxFIFO if (xfer->ff) { // Ring buffer - tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt); + tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, byte_count); } else { // Linear buffer - dfifo_read_packet(dwc2, xfer->buffer, bcnt); + dfifo_read_packet(dwc2, xfer->buffer, byte_count); // Increment pointer to xfer data - xfer->buffer += bcnt; + xfer->buffer += byte_count; } - // Truncate transfer length in case of short packet - if (bcnt < xfer->max_size) { - xfer->total_len -= (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; + // short packet, minus remaining bytes (xfer_size) + if (byte_count < xfer->max_size) { + xfer->total_len -= epout->doeptsiz_bm.xfer_size; if (epnum == 0) { xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; ep0_pending[TUSB_DIR_OUT] = 0; diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index 1527932a5..66dc59b11 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -242,9 +242,6 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) { dwc2->gintmsk |= GINTMSK_RXFLVLM; } - // (non-periodic) TX FIFO empty level for interrupt is complete empty - dwc2->gahbcfg |= GAHBCFG_TX_FIFO_EPMTY_LVL; - return true; } diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 36e917d43..9aaa8f0bd 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -145,6 +145,21 @@ enum { HCTSIZ_PID_SETUP = 3, }; +enum { + GRXSTS_PKTSTS_GLOBALOUTNAK = 1, + GRXSTS_PKTSTS_OUTRX = 2, + GRXSTS_PKTSTS_OUTDONE = 3, + GRXSTS_PKTSTS_SETUPDONE = 4, + GRXSTS_PKTSTS_SETUPRX = 6 +}; + +enum { + GRXSTS_PKTSTS_HOST_IN_RECEIVED = 2, + GRXSTS_PKTSTS_HOST_IN_XFER_COMPL = 3, + GRXSTS_PKTSTS_HOST_DATATOGGLE_ERR = 5, + GRXSTS_PKTSTS_HOST_CHANNEL_HALTED = 7 +}; + //-------------------------------------------------------------------- // Common Register Bitfield //-------------------------------------------------------------------- @@ -263,6 +278,17 @@ typedef struct TU_ATTR_PACKED { } dwc2_grstctl_t; TU_VERIFY_STATIC(sizeof(dwc2_grstctl_t) == 4, "incorrect size"); +typedef struct TU_ATTR_PACKED { + uint32_t ep_ch_num : 4; // 0..3 Endpoint/Channel Number + uint32_t byte_count :11; // 4..14 Byte Count + uint32_t dpid : 2; // 15..16 Data PID + uint32_t packet_status : 4; // 17..20 Packet Status + uint32_t frame_number : 4; // 21..24 Frame Number + uint32_t rsv25_31 : 7; // 25..31 Reserved +} dwc2_grxstsp_t; +TU_VERIFY_STATIC(sizeof(dwc2_grxstsp_t) == 4, "incorrect size"); + +// Hardware Configuration typedef struct TU_ATTR_PACKED { uint32_t op_mode : 3; // 0..2 HNP/SRP Host/Device/OTG mode uint32_t arch : 2; // 3..4 Slave/External/Internal DMA @@ -496,7 +522,10 @@ typedef struct { volatile uint32_t gintsts; // 014 Interrupt volatile uint32_t gintmsk; // 018 Interrupt Mask volatile uint32_t grxstsr; // 01c Receive Status Debug Read + union { volatile uint32_t grxstsp; // 020 Receive Status Read/Pop + volatile dwc2_grxstsp_t grxstsp_bm; + }; volatile uint32_t grxfsiz; // 024 Receive FIFO Size union { volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size @@ -1236,17 +1265,6 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GRXSTSP_PKTSTS_Msk (0xFUL << GRXSTSP_PKTSTS_Pos) // 0x001E0000 #define GRXSTSP_PKTSTS GRXSTSP_PKTSTS_Msk // OUT EP interrupt mask bits -#define GRXSTS_PKTSTS_GLOBALOUTNAK 1 -#define GRXSTS_PKTSTS_OUTRX 2 -#define GRXSTS_PKTSTS_HCHIN 2 -#define GRXSTS_PKTSTS_OUTDONE 3 -#define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3 -#define GRXSTS_PKTSTS_SETUPDONE 4 -#define GRXSTS_PKTSTS_DATATOGGLEERR 5 -#define GRXSTS_PKTSTS_SETUPRX 6 -#define GRXSTS_PKTSTS_HCHHALTED 7 - - /******************** Bit definition for DAINTMSK register ********************/ #define DAINTMSK_IEPM_Pos (0U) #define DAINTMSK_IEPM_Msk (0xFFFFUL << DAINTMSK_IEPM_Pos) // 0x0000FFFF diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index f388776c5..7d74d7a33 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -54,7 +54,7 @@ typedef struct { dwc2_channel_split_t hcsplt_bm; }; - uint8_t* buf; + uint8_t* buffer; uint16_t total_len; uint8_t next_data_toggle; bool pending_tx; @@ -218,7 +218,7 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dwc2->hprt = HPRT_POWER; // turn on VBUS // Enable required interrupts - dwc2->gintmsk |= GINTMSK_OTGINT | GINTSTS_CONIDSTSCHNG | GINTMSK_PRTIM ; // | GINTMSK_WUIM; + dwc2->gintmsk |= GINTSTS_OTGINT | GINTSTS_CONIDSTSCHNG | GINTSTS_HPRTINT | GINTSTS_HCINT; // NPTX can hold at least 2 packet, change interrupt level to half-empty uint32_t gahbcfg = dwc2->gahbcfg & ~GAHBCFG_TX_FIFO_EPMTY_LVL; @@ -354,6 +354,11 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t find_opened_pipe(uint8_t dev_addr, u return TUSB_INDEX_INVALID_8; } +TU_ATTR_ALWAYS_INLINE static inline uint8_t find_opened_pipe_by_channel(const dwc2_channel_t* channel) { + const dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; + return find_opened_pipe(hcchar_bm.dev_addr, hcchar_bm.ep_num, hcchar_bm.ep_dir); +} + void schedule_out_packet(dwc2_regs_t* dwc2, uint8_t pipe_id, uint8_t ch_id) { // To prevent conflict with other channel, we will enable periodic/non-periodic FIFO empty interrupt accordingly. // And write packet in the interrupt handler @@ -382,8 +387,12 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * dwc2->haintmsk |= TU_BIT(ch_id); dwc2_channel_t* channel = &dwc2->channel[ch_id]; - channel->hcintmsk = HCINT_XFER_COMPLETE | HCINT_CHANNEL_HALTED | HCINT_STALL | - HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR; + uint32_t hcintmsk = HCINT_XFER_COMPLETE | HCINT_CHANNEL_HALTED | HCINT_STALL | + HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR; + if (ep_dir == TUSB_DIR_IN) { + hcintmsk |= HCINT_NAK; + } + channel->hcintmsk = hcintmsk; uint16_t packet_count = tu_div_ceil(buflen, hcchar_bm->ep_size); if (packet_count == 0) { @@ -405,21 +414,24 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * hcchar_bm->ep_dir = ep_dir; // control endpoint can switch direction channel->hcchar = pipe->hcchar & ~HCCHAR_CHENA; // restore hcchar but don't enable yet + pipe->buffer = buffer; + pipe->total_len = buflen; + if (dma_host_enabled(dwc2)) { channel->hcdma = (uint32_t) buffer; } else { - if (ep_dir == TUSB_DIR_IN) { - TU_ASSERT(false); // not yet support - } else { - pipe->buf = buffer; - pipe->total_len = buflen; + // enable channel for: + // - OUT endpoint: it will enable corresponding FIFO channel + // - IN endpoint: it will write an IN request to the Non-periodic Request Queue, this will have dwc2 trying to send + // IN Token. If we got NAK, we have to re-enable the channel again in the interrupt. Due to the way usbh stack only + // call hcd_edpt_xfer() once, we will need to manage de-allocate/re-allocate IN channel dynamically. + channel->hcchar |= HCCHAR_CHENA; - channel->hcchar |= HCCHAR_CHENA; // enable channel before writing to FIFO + if (ep_dir == TUSB_DIR_IN) { - if (ep_dir == TUSB_DIR_OUT && buflen > 0) { + } else { + if (buflen > 0) { schedule_out_packet(dwc2, pipe_id, ch_id); - } else { - TU_ASSERT(false); // not yet support } } } @@ -460,20 +472,50 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { // HCD Event Handler //-------------------------------------------------------------------- -#if 1 static void handle_rxflvl_irq(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - // volatile uint32_t const* rx_fifo = dwc2->fifo[0]; // Pop control word off FIFO - uint32_t const grxstsp = dwc2->grxstsp; - (void) grxstsp; - // uint8_t const pktsts = (grxstsp & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; - // uint8_t const epnum = (grxstsp & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; - // uint16_t const bcnt = (grxstsp & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; - // dwc2_epout_t* epout = &dwc2->epout[epnum]; + const dwc2_grxstsp_t grxstsp_bm = dwc2->grxstsp_bm; + const uint8_t ch_id = grxstsp_bm.ep_ch_num; + dwc2_channel_t* channel = &dwc2->channel[ch_id]; + + switch (grxstsp_bm.packet_status) { + case GRXSTS_PKTSTS_HOST_IN_RECEIVED: { + // In packet received + const uint16_t byte_count = grxstsp_bm.byte_count; + const uint8_t pipe_id = find_opened_pipe_by_channel(channel); + TU_VERIFY(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX, ); + hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; + + dfifo_read_packet(dwc2, pipe->buffer, byte_count); + pipe->buffer += byte_count; + + // short packet, minus remaining bytes (xfer_size) + if (byte_count < channel->hctsiz_bm.xfer_size) { + pipe->total_len -= channel->hctsiz_bm.xfer_size; + } + + break; + } + + case GRXSTS_PKTSTS_HOST_IN_XFER_COMPL: + // In transfer complete: After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed + // interrupt --> handle_channel_irq() + break; + + case GRXSTS_PKTSTS_HOST_DATATOGGLE_ERR: + TU_ASSERT(0, ); // maybe try to change DToggle + break; + + case GRXSTS_PKTSTS_HOST_CHANNEL_HALTED: + // triggered when channel.hcchar_bm.disable is set + // TODO handle later + break; + + default: break; // ignore other status + } } -#endif /* Handle Host Port interrupt, possible source are: - Connection Detection @@ -548,25 +590,31 @@ void handle_channel_irq(uint8_t rhport, bool in_isr) { uint32_t hcint = channel->hcint; hcint &= channel->hcintmsk; - xfer_result_t result = XFER_RESULT_FAILED; - if (hcint & HCINT_XFER_COMPLETE) { - result = XFER_RESULT_SUCCESS; - } - if (hcint & HCINT_STALL) { - result = XFER_RESULT_STALLED; - } - if (hcint & (HCINT_CHANNEL_HALTED | HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR | - HCINT_BUFFER_NAK | HCINT_XCS_XACT_ERR | HCINT_DESC_ROLLOVER)) { - result = XFER_RESULT_FAILED; - } + if (hcint & HCINT_NAK) { + // NAK received, re-enable channel. Check if request queue is available + channel->hcchar |= HCCHAR_CHENA; + } else { + // transfer result interrupt + xfer_result_t result = XFER_RESULT_FAILED; + if (hcint & HCINT_XFER_COMPLETE) { + result = XFER_RESULT_SUCCESS; + } + if (hcint & HCINT_STALL) { + result = XFER_RESULT_STALLED; + } + if (hcint & (HCINT_CHANNEL_HALTED | HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR | + HCINT_BUFFER_NAK | HCINT_XCS_XACT_ERR | HCINT_DESC_ROLLOVER)) { + result = XFER_RESULT_FAILED; + } - const uint8_t ep_addr = tu_edpt_addr(channel->hcchar_bm.ep_num, channel->hcchar_bm.ep_dir); - hcd_event_xfer_complete(channel->hcchar_bm.dev_addr, ep_addr, 0, result, in_isr); + const uint8_t ep_addr = tu_edpt_addr(channel->hcchar_bm.ep_num, channel->hcchar_bm.ep_dir); + hcd_event_xfer_complete(channel->hcchar_bm.dev_addr, ep_addr, 0, result, in_isr); - channel->hcint = hcint; // clear all interrupt flags + // de-allocate channel by clearing haintmsk + dwc2->haintmsk &= ~TU_BIT(ch_id); + } - // de-allocate channel by clearing haintmsk - dwc2->haintmsk &= ~TU_BIT(ch_id); + channel->hcint = hcint; // clear all interrupt flags } } } @@ -581,7 +629,7 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; const dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { - uint8_t pipe_id = find_opened_pipe(hcchar_bm.dev_addr, hcchar_bm.ep_num, TUSB_DIR_OUT); + uint8_t pipe_id = find_opened_pipe_by_channel(channel); if (pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX) { hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; if (pipe->pending_tx) { @@ -595,8 +643,8 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { break; } - dfifo_write_packet(dwc2, ch_id, pipe->buf, packet_bytes); - pipe->buf += packet_bytes; + dfifo_write_packet(dwc2, ch_id, pipe->buffer, packet_bytes); + pipe->buffer += packet_bytes; if (channel->hctsiz_bm.xfer_size == 0) { pipe->pending_tx = false; // all data has been written -- cgit v1.3.1 From f953b6bf9253814ea45a76739101d478ac3f9ad1 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 28 Oct 2024 18:40:21 +0700 Subject: minor rename --- examples/host/msc_file_explorer/only.txt | 1 + hw/bsp/stm32l4/family.cmake | 2 ++ src/portable/synopsys/dwc2/dwc2_type.h | 4 +-- src/portable/synopsys/dwc2/hcd_dwc2.c | 42 ++++++++++++++++---------------- 4 files changed, 26 insertions(+), 23 deletions(-) (limited to 'hw') diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt index fee10f9e2..9b3d6994e 100644 --- a/examples/host/msc_file_explorer/only.txt +++ b/examples/host/msc_file_explorer/only.txt @@ -12,3 +12,4 @@ mcu:MSP432E4 mcu:RX65X mcu:RAXXX mcu:MAX3421 +mcu:STM32F7 diff --git a/hw/bsp/stm32l4/family.cmake b/hw/bsp/stm32l4/family.cmake index b6eae7c7f..77876cb8b 100644 --- a/hw/bsp/stm32l4/family.cmake +++ b/hw/bsp/stm32l4/family.cmake @@ -104,6 +104,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS} ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 0d62c404c..7296475cf 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -154,8 +154,8 @@ enum { }; enum { - GRXSTS_PKTSTS_HOST_IN_RECEIVED = 2, - GRXSTS_PKTSTS_HOST_IN_XFER_COMPL = 3, + GRXSTS_PKTSTS_RX_DATA = 2, + GRXSTS_PKTSTS_RX_COMPLETE = 3, GRXSTS_PKTSTS_HOST_DATATOGGLE_ERR = 5, GRXSTS_PKTSTS_HOST_CHANNEL_HALTED = 7 }; diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 464ade9bf..027a839bb 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -59,9 +59,9 @@ typedef struct { }; uint8_t* buffer; - uint16_t total_len; + uint16_t total_bytes; uint8_t next_data_toggle; - bool pending_data; + volatile bool pending_data; } hcd_pipe_t; typedef struct { @@ -70,6 +70,8 @@ typedef struct { hcd_data_t _hcd_data; +#define DWC2_CHANNEL_MAX(_dwc2) tu_min8((_dwc2)->ghwcfg2_bm.num_host_ch + 1, 16) + //-------------------------------------------------------------------- // //-------------------------------------------------------------------- @@ -108,8 +110,8 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t request_queue_avail(const dwc2_regs_ // Find a free channel for new transfer TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_free(dwc2_regs_t* dwc2) { - const uint8_t max_channel = tu_min8(dwc2->ghwcfg2_bm.num_host_ch, 16); - for (uint8_t ch_id=0; ch_idhaintmsk, ch_id)) { return ch_id; @@ -120,7 +122,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_free(dwc2_regs_t* dwc2) // Find currently enabled/active channel associated with a pipe TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_enabled_by_pipe(dwc2_regs_t* dwc2, const hcd_pipe_t* pipe) { - const uint8_t max_channel = tu_min8(dwc2->ghwcfg2_bm.num_host_ch, 16); + const uint8_t max_channel = DWC2_CHANNEL_MAX(dwc2); for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { if (tu_bit_test(dwc2->haintmsk, ch_id)) { const dwc2_channel_char_t hcchar_bm = dwc2->channel[ch_id].hcchar_bm; @@ -366,7 +368,6 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { //--------------------------------------------------------------------+ // Open an endpoint -// channel0 is reserved for dev0 control endpoint bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep) { (void) rhport; //dwc2_regs_t* dwc2 = DWC2_REG(rhport); @@ -452,7 +453,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * channel->hcchar = pipe->hcchar & ~HCCHAR_CHENA; // restore hcchar but don't enable yet pipe->buffer = buffer; - pipe->total_len = buflen; + pipe->total_bytes = buflen; if (dma_host_enabled(dwc2)) { channel->hcdma = (uint32_t) buffer; @@ -542,7 +543,7 @@ static void handle_rxflvl_irq(uint8_t rhport) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; switch (grxstsp_bm.packet_status) { - case GRXSTS_PKTSTS_HOST_IN_RECEIVED: { + case GRXSTS_PKTSTS_RX_DATA: { // In packet received const uint16_t byte_count = grxstsp_bm.byte_count; const uint8_t pipe_id = pipe_find_opened_by_channel(channel); @@ -554,13 +555,13 @@ static void handle_rxflvl_irq(uint8_t rhport) { // short packet, minus remaining bytes (xfer_size) if (byte_count < channel->hctsiz_bm.xfer_size) { - pipe->total_len -= channel->hctsiz_bm.xfer_size; + pipe->total_bytes -= channel->hctsiz_bm.xfer_size; } break; } - case GRXSTS_PKTSTS_HOST_IN_XFER_COMPL: + case GRXSTS_PKTSTS_RX_COMPLETE: // In transfer complete: After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed // interrupt --> handle_channel_irq() break; @@ -645,14 +646,13 @@ TU_ATTR_ALWAYS_INLINE static inline void handle_hprt_irq(uint8_t rhport, bool in void handle_channel_irq(uint8_t rhport, bool in_isr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - for(uint8_t ch_id=0; ch_id<32; ch_id++) { + for (uint8_t ch_id = 0; ch_id < 32; ch_id++) { if (tu_bit_test(dwc2->haint, ch_id)) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; uint32_t hcint = channel->hcint; hcint &= channel->hcintmsk; dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; - xfer_result_t result = XFER_RESULT_INVALID; // invalid means transfer is not complete if (hcint & HCINT_XFER_COMPLETE) { @@ -686,12 +686,11 @@ void handle_channel_irq(uint8_t rhport, bool in_isr) { // Transfer is complete (success, stalled, failed) or channel is disabled if (result != XFER_RESULT_INVALID || (hcint & HCINT_CHANNEL_HALTED)) { uint8_t pipe_id = pipe_find_opened_by_channel(channel); - if (pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX) { - hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; - pipe->pending_data = false; - } + TU_ASSERT(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX, ); + hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; const uint8_t ep_addr = tu_edpt_addr(hcchar_bm.ep_num, hcchar_bm.ep_dir); + pipe->pending_data = false; dwc2->haintmsk &= ~TU_BIT(ch_id); // de-allocate channel // notify usbh if transfer is complete (skip if channel is disabled) @@ -709,8 +708,9 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { // Use period txsts for both p/np to get request queue space available (1-bit difference, it is small enough) volatile dwc2_hptxsts_t* txsts_bm = (volatile dwc2_hptxsts_t*) (is_periodic ? &dwc2->hptxsts : &dwc2->hnptxsts); - // find which channel have pending packet + // find OUT channel with pending data bool ff_written = false; + //const uint8_t max_channel = DWC2_CHANNEL_MAX(dwc2); for (uint8_t ch_id = 0; ch_id < 32; ch_id++) { if (tu_bit_test(dwc2->haintmsk, ch_id)) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; @@ -723,16 +723,16 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { const uint16_t remain_packets = channel->hctsiz_bm.packet_count; for (uint16_t i = 0; i < remain_packets; i++) { const uint16_t remain_bytes = channel->hctsiz_bm.xfer_size; - const uint16_t packet_bytes = tu_min16(remain_bytes, hcchar_bm.ep_size); + const uint16_t xact_bytes = tu_min16(remain_bytes, hcchar_bm.ep_size); // check if there is enough space in FIFO and request queue. // the last dword written to FIFO will trigger dwc2 controller to write to RequestQueue - if ((packet_bytes > txsts_bm->fifo_available) && (txsts_bm->req_queue_available > 0)) { + if ((xact_bytes > txsts_bm->fifo_available) && (txsts_bm->req_queue_available > 0)) { break; } - dfifo_write_packet(dwc2, ch_id, pipe->buffer, packet_bytes); - pipe->buffer += packet_bytes; + dfifo_write_packet(dwc2, ch_id, pipe->buffer, xact_bytes); + pipe->buffer += xact_bytes; if (channel->hctsiz_bm.xfer_size == 0) { pipe->pending_data = false; // all data has been written -- cgit v1.3.1 From 9897a36ac4cf0dcc469f46d381c4b13d72298acb Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 31 Oct 2024 12:11:47 +0700 Subject: fix f7 ci build --- hw/bsp/stm32f7/boards/stm32f723disco/board.h | 2 +- hw/bsp/stm32f7/family.c | 3 +++ hw/bsp/stm32h7/boards/stm32h743eval/board.h | 15 +++++++-------- hw/bsp/stm32h7/family.c | 10 ++++++---- 4 files changed, 17 insertions(+), 13 deletions(-) (limited to 'hw') diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.h b/hw/bsp/stm32f7/boards/stm32f723disco/board.h index 178fd6e5e..37f18fedf 100644 --- a/hw/bsp/stm32f7/boards/stm32f723disco/board.h +++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.h @@ -122,7 +122,7 @@ static board_pindef_t vbus_pindef[] = { }, }; -static inline void board_vbus_set(uint8_t rhport, bool state) { +void board_vbus_set(uint8_t rhport, bool state) { static bool pin_inited[2] = { false, false }; board_pindef_t* pindef = &vbus_pindef[rhport]; if (!pin_inited[rhport]) { diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c index 1f49d7693..f1671b362 100644 --- a/hw/bsp/stm32f7/family.c +++ b/hw/bsp/stm32f7/family.c @@ -28,6 +28,9 @@ #include "stm32f7xx_hal.h" #include "bsp/board_api.h" + +void board_vbus_set(uint8_t rhport, bool state) TU_ATTR_WEAK; + #include "board.h" //--------------------------------------------------------------------+ diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h index 9e2649d14..2e2d4aebd 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h @@ -60,14 +60,6 @@ {GPIOB, GPIO_PIN_5 }, {GPIOB, GPIO_PIN_10}, {GPIOB, GPIO_PIN_11}, {GPIOB, GPIO_PIN_12}, \ {GPIOB, GPIO_PIN_13}, {GPIOC, GPIO_PIN_0 }, {GPIOH, GPIO_PIN_4 }, {GPIOI, GPIO_PIN_11} -// vbus drive -#define BOARD_VBUS_DRIVE(_rhport, _on) do { \ - if ( mfx_io_drv ) { \ - uint32_t io_pin = (_rhport) ? MFXSTM32L152_GPIO_PIN_9 : MFXSTM32L152_GPIO_PIN_7; \ - mfx_io_drv->IO_WritePin(&Io_CompObj, io_pin, _on); \ - }\ - } while(0) - /* Definition for I2C1 Pins */ #define BUS_I2C1_SCL_PIN GPIO_PIN_6 #define BUS_I2C1_SDA_PIN GPIO_PIN_7 @@ -283,6 +275,13 @@ static inline void board_init2(void) { #endif } +// vbus drive +void board_vbus_set(uint8_t rhport, bool state) { + if ( mfx_io_drv ) { + uint32_t io_pin = (_rhport) ? MFXSTM32L152_GPIO_PIN_9 : MFXSTM32L152_GPIO_PIN_7; + mfx_io_drv->IO_WritePin(&Io_CompObj, io_pin, _on); + } +} #ifdef __cplusplus } diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c index c8b7c6fe3..27e7d0a49 100644 --- a/hw/bsp/stm32h7/family.c +++ b/hw/bsp/stm32h7/family.c @@ -30,8 +30,8 @@ #include "stm32h7xx_hal.h" #include "bsp/board_api.h" -TU_ATTR_UNUSED static void Error_Handler(void) { -} +TU_ATTR_UNUSED static void Error_Handler(void) { } +void board_vbus_set(uint8_t rhport, bool state) TU_ATTR_WEAK; #include "board.h" @@ -196,6 +196,7 @@ void board_init(void) { #endif // vbus sense //------------- USB HS -------------// +#if (CFG_TUD_ENABLED && BOARD_TUD_RHPORT == 1) || (CFG_TUH_ENABLED && BOARD_TUH_RHPORT == 1) // Despite being call USB2_OTG // OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port struct { @@ -232,14 +233,15 @@ void board_init(void) { // Force device mode USB_OTG_HS->GUSBCFG &= ~USB_OTG_GUSBCFG_FHMOD; USB_OTG_HS->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; +#endif HAL_PWREx_EnableUSBVoltageDetector(); // For waveshare openh743 ULPI PHY reset walkaround board_init2(); -#if CFG_TUH_ENABLED && defined(BOARD_VBUS_DRIVE) - BOARD_VBUS_DRIVE(BOARD_TUH_RHPORT, 1); +#if CFG_TUH_ENABLED + board_vbus_set(BOARD_TUH_RHPORT, 1); #endif } -- cgit v1.3.1 From 56f53a61329f3a3a492530e364f543f3a419297f Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 2 Nov 2024 12:45:32 +0100 Subject: Replace cache clean/invalidate by MPU config. --- hw/bsp/imxrt/family.c | 450 +++++++++++++++++++++++++++--- hw/bsp/imxrt/family.cmake | 1 + hw/bsp/imxrt/family.mk | 3 +- src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 43 +-- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 43 --- 5 files changed, 425 insertions(+), 115 deletions(-) (limited to 'hw') diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index 6087ee37d..d3a228f0f 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -24,30 +24,43 @@ * This file is part of the TinyUSB stack. */ -#include "bsp/board_api.h" +#include "board.h" #include "board/clock_config.h" #include "board/pin_mux.h" -#include "board.h" +#include "bsp/board_api.h" // Suppress warning caused by mcu driver #ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wunused-parameter" + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wunused-parameter" #endif +#include "fsl_clock.h" #include "fsl_device_registers.h" #include "fsl_gpio.h" #include "fsl_iomuxc.h" -#include "fsl_clock.h" #include "fsl_lpuart.h" #include "fsl_ocotp.h" #ifdef __GNUC__ -#pragma GCC diagnostic pop + #pragma GCC diagnostic pop #endif +/* --- Note about USB buffer RAM --- +For M7 core it's recommanded to put USB buffer in DTCM for better performance (flexspi_nor linker default) +Otherwise you have to put the buffer in a non-cacheable section by configurate MPU manually or using BOARD_ConfigMPU(): +- Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) +- (IAR only) Change __NCACHE_REGION_SIZE in linker script to cover the size of non-cacheable section, multiple of 2^N + +For secondary M4 core, the USB controller doesn't support transfer from DTCM so OCRAM must be used: +- __NCACHE_REGION_SIZE is defined by the linker script by default +- Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) +*/ + +static void BOARD_ConfigMPU(void); + // needed by fsl_flexspi_nor_boot -TU_ATTR_USED const uint8_t dcd_data[] = { 0x00 }; +TU_ATTR_USED const uint8_t dcd_data[] = {0x00}; //--------------------------------------------------------------------+ // @@ -59,20 +72,20 @@ TU_ATTR_USED const uint8_t dcd_data[] = { 0x00 }; #endif static void init_usb_phy(uint8_t usb_id) { - USBPHY_Type* usb_phy; + USBPHY_Type *usb_phy; if (usb_id == 0) { usb_phy = USBPHY1; CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, BOARD_XTAL0_CLK_HZ); } - #ifdef USBPHY2 +#ifdef USBPHY2 else if (usb_id == 1) { usb_phy = USBPHY2; CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, BOARD_XTAL0_CLK_HZ); } - #endif +#endif else { return; } @@ -91,13 +104,8 @@ static void init_usb_phy(uint8_t usb_id) { usb_phy->TX = phytx; } -void board_init(void) -{ - // make sure the dcache is on. -#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT - if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) SCB_EnableDCache(); -#endif - +void board_init(void) { + BOARD_ConfigMPU(); BOARD_InitPins(); BOARD_BootClockRUN(); SystemCoreClockUpdate(); @@ -113,9 +121,9 @@ void board_init(void) #elif CFG_TUSB_OS == OPT_OS_FREERTOS // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) NVIC_SetPriority(USB_OTG1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); -#ifdef USBPHY2 + #ifdef USBPHY2 NVIC_SetPriority(USB_OTG2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); -#endif + #endif #endif board_led_write(true); @@ -127,19 +135,397 @@ void board_init(void) uart_config.enableTx = true; uart_config.enableRx = true; - if ( kStatus_Success != LPUART_Init(UART_PORT, &uart_config, UART_CLK_ROOT) ) { + if (kStatus_Success != LPUART_Init(UART_PORT, &uart_config, UART_CLK_ROOT)) { // failed to init uart, probably baudrate is not supported // TU_BREAKPOINT(); } //------------- USB -------------// // Note: RT105x RT106x and later have dual USB controllers. - init_usb_phy(0); // USB0 + init_usb_phy(0);// USB0 #ifdef USBPHY2 - init_usb_phy(1); // USB1 + init_usb_phy(1);// USB1 #endif } +/* MPU configuration. */ +#if __CORTEX_M == 7 +static void BOARD_ConfigMPU(void) { + #if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RW_m_ncache$$Base[]; + /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */ + extern uint32_t Image$$RW_m_ncache_unused$$Base[]; + extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[]; + uint32_t nonCacheStart = (uint32_t) Image$$RW_m_ncache$$Base; + uint32_t size = ((uint32_t) Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? 0 : ((uint32_t) Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart); + #elif defined(__MCUXPRESSO) + #if defined(__USE_SHMEM) + extern uint32_t __base_rpmsg_sh_mem; + extern uint32_t __top_rpmsg_sh_mem; + uint32_t nonCacheStart = (uint32_t) (&__base_rpmsg_sh_mem); + uint32_t size = (uint32_t) (&__top_rpmsg_sh_mem) - nonCacheStart; + #else + extern uint32_t __base_NCACHE_REGION; + extern uint32_t __top_NCACHE_REGION; + uint32_t nonCacheStart = (uint32_t) (&__base_NCACHE_REGION); + uint32_t size = (uint32_t) (&__top_NCACHE_REGION) - nonCacheStart; + #endif + #elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = (uint32_t) __NCACHE_REGION_START; + uint32_t size = (uint32_t) __NCACHE_REGION_SIZE; + #endif + volatile uint32_t i = 0; + + #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT + /* Disable I cache and D cache */ + if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) { + SCB_DisableICache(); + } + #endif + #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT + if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) { + SCB_DisableDCache(); + } + #endif + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* MPU configure: + * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, + * SubRegionDisable, Size) + * API in mpu_armv7.h. + * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches + * disabled. + * param AccessPermission Data access permissions, allows you to configure read/write access for User and + * Privileged mode. + * Use MACROS defined in mpu_armv7.h: + * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO + * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. + * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache + * 0 x 0 0 Strongly Ordered shareable + * 0 x 0 1 Device shareable + * 0 0 1 0 Normal not shareable Outer and inner write + * through no write allocate + * 0 0 1 1 Normal not shareable Outer and inner write + * back no write allocate + * 0 1 1 0 Normal shareable Outer and inner write + * through no write allocate + * 0 1 1 1 Normal shareable Outer and inner write + * back no write allocate + * 1 0 0 0 Normal not shareable outer and inner + * noncache + * 1 1 0 0 Normal shareable outer and inner + * noncache + * 1 0 1 1 Normal not shareable outer and inner write + * back write/read acllocate + * 1 1 1 1 Normal shareable outer and inner write + * back write/read acllocate + * 2 x 0 0 Device not shareable + * Above are normal use settings, if your want to see more details or want to config different inner/outer cache + * policy. + * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide + * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. + * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in + * mpu_armv7.h. + */ + + /* + * Add default region to deny access to whole address space to workaround speculative prefetch. + * Refer to Arm errata 1013783-B for more details. + * + */ + /* Region 0 setting: Instruction access disabled, No data access permission. */ + MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB); + + /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + #if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH + /* Region 6 setting: Memory with Normal type, not shareable, write through */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Region 7 setting: Memory with Normal type, not shareable, write trough */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB); + #else + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB); + #endif + + #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) + /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */ + MPU->RBAR = ARM_MPU_RBAR(8, 0x30000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB); + #endif + + #ifdef USE_SDRAM + #if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH + /* Region 9 setting: Memory with Normal type, not shareable, write trough */ + MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB); + #else + /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB); + #endif + #endif + + while ((size >> i) > 0x1U) { + i++; + } + + if (i != 0) { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(nonCacheStart % size)); + assert(size == (uint32_t) (1 << i)); + assert(i >= 5); + + /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1); + } + + /* Region 11 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_16MB); + + /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(12, 0x41000000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); + + /* Region 13 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(13, 0x41400000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Region 14 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(14, 0x41800000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); + + /* Region 15 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(15, 0x42000000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); + + /* Enable I cache and D cache */ + #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT + SCB_EnableDCache(); + #endif + #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT + SCB_EnableICache(); + #endif +} +#elif __CORTEX_M == 4 +void BOARD_ConfigMPU(void) { + #if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RW_m_ncache$$Base[]; + /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */ + extern uint32_t Image$$RW_m_ncache_unused$$Base[]; + extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[]; + uint32_t nonCacheStart = (uint32_t) Image$$RW_m_ncache$$Base; + uint32_t nonCacheSize = ((uint32_t) Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? 0 : ((uint32_t) Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart); + #elif defined(__MCUXPRESSO) + extern uint32_t __base_NCACHE_REGION; + extern uint32_t __top_NCACHE_REGION; + uint32_t nonCacheStart = (uint32_t) (&__base_NCACHE_REGION); + uint32_t nonCacheSize = (uint32_t) (&__top_NCACHE_REGION) - nonCacheStart; + #elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = (uint32_t) __NCACHE_REGION_START; + uint32_t nonCacheSize = (uint32_t) __NCACHE_REGION_SIZE; + #endif + #if defined(__USE_SHMEM) + #if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RPMSG_SH_MEM$$Base[]; + /* RPMSG_SH_MEM_unused is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */ + extern uint32_t Image$$RPMSG_SH_MEM_unused$$Base[]; + extern uint32_t Image$$RPMSG_SH_MEM_unused$$ZI$$Limit[]; + uint32_t rpmsgShmemStart = (uint32_t) Image$$RPMSG_SH_MEM$$Base; + uint32_t rpmsgShmemSize = (uint32_t) Image$$RPMSG_SH_MEM_unused$$ZI$$Limit - rpmsgShmemStart; + #elif defined(__MCUXPRESSO) + extern uint32_t __base_rpmsg_sh_mem; + extern uint32_t __top_rpmsg_sh_mem; + uint32_t rpmsgShmemStart = (uint32_t) (&__base_rpmsg_sh_mem); + uint32_t rpmsgShmemSize = (uint32_t) (&__top_rpmsg_sh_mem) - rpmsgShmemStart; + #elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __RPMSG_SH_MEM_START[]; + extern uint32_t __RPMSG_SH_MEM_SIZE[]; + uint32_t rpmsgShmemStart = (uint32_t) __RPMSG_SH_MEM_START; + uint32_t rpmsgShmemSize = (uint32_t) __RPMSG_SH_MEM_SIZE; + #endif + #endif + uint32_t i = 0; + + /* Only config non-cacheable region on system bus */ + assert(nonCacheStart >= 0x20000000); + + /* Disable code bus cache */ + if (LMEM_PCCCR_ENCACHE_MASK == (LMEM_PCCCR_ENCACHE_MASK & LMEM->PCCCR)) { + /* Enable the processor code bus to push all modified lines. */ + LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK; + /* Wait until the cache command completes. */ + while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK); + /* Now disable the cache. */ + LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK; + } + + /* Disable system bus cache */ + if (LMEM_PSCCR_ENCACHE_MASK == (LMEM_PSCCR_ENCACHE_MASK & LMEM->PSCCR)) { + /* Enable the processor system bus to push all modified lines. */ + LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK; + /* Wait until the cache command completes. */ + while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK); + /* Now disable the cache. */ + LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK; + } + + /* Disable MPU */ + ARM_MPU_Disable(); + + #if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH + /* Region 0 setting: Memory with Normal type, not shareable, write trough */ + MPU->RBAR = ARM_MPU_RBAR(0, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Region 1 setting: Memory with Normal type, not shareable, write through */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x20300000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB); + + /* Region 2 setting: Memory with Normal type, not shareable, write through */ + MPU->RBAR = ARM_MPU_RBAR(2, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB); + + while ((nonCacheSize >> i) > 0x1U) { + i++; + } + + if (i != 0) { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(nonCacheStart % nonCacheSize)); + assert(nonCacheSize == (uint32_t) (1 << i)); + assert(i >= 5); + + /* Region 3 setting: Memory with device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(3, nonCacheStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1); + } + + #if defined(__USE_SHMEM) + i = 0; + + while ((rpmsgShmemSize >> i) > 0x1U) { + i++; + } + + if (i != 0) { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(rpmsgShmemStart % rpmsgShmemSize)); + assert(rpmsgShmemSize == (uint32_t) (1 << i)); + assert(i >= 5); + + /* Region 4 setting: Memory with device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(4, rpmsgShmemStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1); + } + #endif + #else + while ((nonCacheSize >> i) > 0x1U) { + i++; + } + + if (i != 0) { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(nonCacheStart % nonCacheSize)); + assert(nonCacheSize == (uint32_t) (1 << i)); + assert(i >= 5); + + /* Region 0 setting: Memory with device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(0, nonCacheStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1); + } + + #if defined(__USE_SHMEM) + i = 0; + + while ((rpmsgShmemSize >> i) > 0x1U) { + i++; + } + + if (i != 0) { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(rpmsgShmemStart % rpmsgShmemSize)); + assert(rpmsgShmemSize == (uint32_t) (1 << i)); + assert(i >= 5); + + /* Region 1 setting: Memory with device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(1, rpmsgShmemStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1); + } + #endif + #endif + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); + + /* Enables the processor system bus to invalidate all lines in both ways. + and Initiate the processor system bus cache command. */ + LMEM->PSCCR |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_GO_MASK; + /* Wait until the cache command completes */ + while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PSCCR &= ~(LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK); + /* Now enable the system bus cache. */ + LMEM->PSCCR |= LMEM_PSCCR_ENCACHE_MASK; + + /* Enables the processor code bus to invalidate all lines in both ways. + and Initiate the processor code bus code cache command. */ + LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK; + /* Wait until the cache command completes. */ + while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK); + /* Now enable the code bus cache. */ + LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK; +} +#endif + //--------------------------------------------------------------------+ // USB Interrupt Handler //--------------------------------------------------------------------+ @@ -166,18 +552,18 @@ uint32_t board_button_read(void) { size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; - #if FSL_FEATURE_OCOTP_HAS_TIMING_CTRL +#if FSL_FEATURE_OCOTP_HAS_TIMING_CTRL OCOTP_Init(OCOTP, CLOCK_GetFreq(kCLOCK_IpgClk)); - #else +#else OCOTP_Init(OCOTP, 0u); - #endif +#endif // Reads shadow registers 0x01 - 0x04 (Configuration and Manufacturing Info) // into 8 bit wide destination, avoiding punning. for (int i = 0; i < 4; ++i) { uint32_t wr = OCOTP_ReadFuseShadowRegister(OCOTP, i + 1); for (int j = 0; j < 4; j++) { - id[i*4+j] = wr & 0xff; + id[i * 4 + j] = wr & 0xff; wr >>= 8; } } @@ -186,7 +572,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) { return 16; } -int board_uart_read(uint8_t* buf, int len) { +int board_uart_read(uint8_t *buf, int len) { int count = 0; while (count < len) { @@ -209,8 +595,8 @@ int board_uart_read(uint8_t* buf, int len) { return count; } -int board_uart_write(void const * buf, int len) { - LPUART_WriteBlocking(UART_PORT, (uint8_t const*)buf, len); +int board_uart_write(void const *buf, int len) { + LPUART_WriteBlocking(UART_PORT, (uint8_t const *) buf, len); return len; } @@ -236,10 +622,10 @@ TU_ATTR_UNUSED void _start(void) { while (1) {} } -#ifdef __clang__ -void _exit (int __status) { + #ifdef __clang__ +void _exit(int __status) { while (1) {} } -#endif + #endif #endif diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index d917e9777..436d6e6a3 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -64,6 +64,7 @@ function(add_board_target BOARD_TARGET) XIP_EXTERNAL_FLASH=1 XIP_BOOT_HEADER_ENABLE=1 __STARTUP_CLEAR_BSS + CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk index f00afb6a4..45c3ad31d 100644 --- a/hw/bsp/imxrt/family.mk +++ b/hw/bsp/imxrt/family.mk @@ -14,7 +14,8 @@ CFLAGS += \ -D__STARTUP_CLEAR_BSS \ -DXIP_EXTERNAL_FLASH=1 \ -DXIP_BOOT_HEADER_ENABLE=1 \ - -DCFG_TUSB_MCU=OPT_MCU_MIMXRT1XXX + -DCFG_TUSB_MCU=OPT_MCU_MIMXRT1XXX \ + -DCFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) \ ifdef BOARD_TUD_RHPORT CFLAGS += -DBOARD_TUD_RHPORT=$(BOARD_TUD_RHPORT) diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h index c59c107ff..201936e53 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h +++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h @@ -56,46 +56,11 @@ static const ci_hs_controller_t _ci_controller[] = #define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base) //------------- DCD -------------// -#define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum) -#define CI_DCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum) +#define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ ((IRQn_Type)_ci_controller[_p].irqnum) +#define CI_DCD_INT_DISABLE(_p) NVIC_DisableIRQ((IRQn_Type)_ci_controller[_p].irqnum) //------------- HCD -------------// -#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum) -#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum) - -//------------- DCache -------------// -TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uintptr_t addr) { - return !(0x20000000 <= addr && addr < 0x20100000); -} - -TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean(void const* addr, uint32_t data_size) { - const uintptr_t addr32 = (uintptr_t) addr; - if (imxrt_is_cache_mem(addr32)) { - TU_ASSERT(tu_is_aligned32(addr32)); - SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size); - } - return true; -} - -TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_invalidate(void const* addr, uint32_t data_size) { - const uintptr_t addr32 = (uintptr_t) addr; - if (imxrt_is_cache_mem(addr32)) { - // Invalidating does not push cached changes back to RAM so we need to be - // *very* careful when we do it. If we're not aligned, then we risk resetting - // values back to their RAM state. - TU_ASSERT(tu_is_aligned32(addr32)); - SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size); - } - return true; -} - -TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean_invalidate(void const* addr, uint32_t data_size) { - const uintptr_t addr32 = (uintptr_t) addr; - if (imxrt_is_cache_mem(addr32)) { - TU_ASSERT(tu_is_aligned32(addr32)); - SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size); - } - return true; -} +#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ ((IRQn_Type)_ci_controller[_p].irqnum) +#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ((IRQn_Type)_ci_controller[_p].irqnum) #endif diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index 430a0aad1..76b78cb57 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -33,19 +33,6 @@ #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX #include "ci_hs_imxrt.h" - - void dcd_dcache_clean(void const* addr, uint32_t data_size) { - imxrt_dcache_clean(addr, data_size); - } - - void dcd_dcache_invalidate(void const* addr, uint32_t data_size) { - imxrt_dcache_invalidate(addr, data_size); - } - - void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { - imxrt_dcache_clean_invalidate(addr, data_size); - } - #else #if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) @@ -57,18 +44,6 @@ #else #error "Unsupported MCUs" #endif - - TU_ATTR_WEAK void dcd_dcache_clean(void const* addr, uint32_t data_size) { - (void) addr; (void) data_size; - } - - TU_ATTR_WEAK void dcd_dcache_invalidate(void const* addr, uint32_t data_size) { - (void) addr; (void) data_size; - } - - TU_ATTR_WEAK void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { - (void) addr; (void) data_size; - } #endif //--------------------------------------------------------------------+ @@ -230,8 +205,6 @@ static void bus_reset(uint8_t rhport) _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID; _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only - - dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); } bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { @@ -257,8 +230,6 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED; #endif - dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); - dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment dcd_reg->USBSTS = dcd_reg->USBSTS; dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_SUSPEND; @@ -325,10 +296,6 @@ void dcd_sof_enable(uint8_t rhport, bool en) static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes) { - // Force the CPU to flush the buffer. We increase the size by 31 because the call aligns the - // address to 32-byte boundaries. Buffer must be word aligned - dcd_dcache_clean_invalidate((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31); - tu_memclr(p_qtd, sizeof(dcd_qtd_t)); p_qtd->next = QTD_NEXT_INVALID; @@ -402,8 +369,6 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) p_qhd->qtd_overlay.next = QTD_NEXT_INVALID; - dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); - // Enable EP Control uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET; @@ -461,9 +426,6 @@ static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir) p_qhd->qtd_overlay.halted = false; // clear any previous error p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd - // flush cache - dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); - if ( epnum == 0 ) { // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism @@ -539,8 +501,6 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 page++; } } - - dcd_dcache_clean_invalidate((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31); } else { @@ -652,9 +612,6 @@ void dcd_int_handler(uint8_t rhport) if (int_status & INTR_USB) { - // Make sure we read the latest version of _dcd_data. - dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); - uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE; dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge -- cgit v1.3.1 From 54df3b2e9463771896195e9b84db55f99b0729e6 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 2 Nov 2024 15:13:08 +0100 Subject: mimxrt1170_evkb: add M4 build support. --- hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake | 17 +++++++++++++---- hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk | 18 ++++++++++++++---- hw/bsp/imxrt/family.cmake | 23 +++++++++++++++++------ hw/bsp/imxrt/family.mk | 12 ++++++++---- 4 files changed, 52 insertions(+), 18 deletions(-) (limited to 'hw') diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake index 692d9e498..46a97344f 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake @@ -1,8 +1,17 @@ set(MCU_VARIANT MIMXRT1176) -set(MCU_CORE _cm7) -set(JLINK_DEVICE MIMXRT1176xxxA_M7) -set(PYOCD_TARGET mimxrt1170_cm7) +if (M4 STREQUAL "1") + set(MCU_CORE _cm4) + set(JLINK_CORE _M4) + set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_ram.ld) + set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +else () + set(MCU_CORE _cm7) + set(JLINK_CORE _M7) +endif() + +set(JLINK_DEVICE MIMXRT1176xxxA${JLINK_CORE}) +set(PYOCD_TARGET mimxrt1170${MCU_CORE}) set(NXPLINK_DEVICE MIMXRT1176xxxxx:MIMXRT1170-EVK) function(update_board TARGET) @@ -10,7 +19,7 @@ function(update_board TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/evkbmimxrt1170_flexspi_nor_config.c ) target_compile_definitions(${TARGET} PUBLIC - CPU_MIMXRT1176DVMAA_cm7 + CPU_MIMXRT1176DVMAA${MCU_CORE} BOARD_TUD_RHPORT=0 BOARD_TUH_RHPORT=1 ) diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk index e8500a4c9..8270ae587 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.mk @@ -1,12 +1,22 @@ -CFLAGS += -DCPU_MIMXRT1176DVMAA_cm7 MCU_VARIANT = MIMXRT1176 -MCU_CORE = _cm7 + +ifeq ($(M4), 1) + MCU_CORE = _cm4 + JLINK_CORE = _M4 + CPU_CORE = cortex-m4 + LD_FILE ?= $(MCU_DIR)/gcc/$(MCU_VARIANT)xxxxx${MCU_CORE}_ram.ld +else + MCU_CORE = _cm7 + JLINK_CORE = _M7 +endif + +CFLAGS += -DCPU_MIMXRT1176DVMAA$(MCU_CORE) # For flash-jlink target -JLINK_DEVICE = MIMXRT1176xxxA_M7 +JLINK_DEVICE = MIMXRT1176xxxA$(JLINK_CORE) # For flash-pyocd target -PYOCD_TARGET = mimxrt1170_cm7 +PYOCD_TARGET = mimxrt1170$(MCU_CORE) BOARD_TUD_RHPORT = 0 BOARD_TUH_RHPORT = 1 diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 436d6e6a3..85440746c 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -8,7 +8,9 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) set(MCU_VARIANT_WITH_CORE ${MCU_VARIANT}${MCU_CORE}) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor") +if (NOT DEFINED CMAKE_SYSTEM_PROCESSOR) + set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor") +endif () set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS MIMXRT1XXX CACHE INTERNAL "") @@ -58,14 +60,21 @@ function(add_board_target BOARD_TARGET) endif() endforeach() + target_compile_definitions(${BOARD_TARGET} PUBLIC - __ARMVFP__=0 - __ARMFPV5__=0 - XIP_EXTERNAL_FLASH=1 - XIP_BOOT_HEADER_ENABLE=1 __STARTUP_CLEAR_BSS - CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) + CFG_TUSB_MEM_SECTION=__attribute__\(\(section\(\"NonCacheable\"\)\)\) ) + + if (NOT M4 STREQUAL "1") + target_compile_definitions(${BOARD_TARGET} PUBLIC + __ARMVFP__=0 + __ARMFPV5__=0 + XIP_EXTERNAL_FLASH=1 + XIP_BOOT_HEADER_ENABLE=1 + ) + endif () + target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/board @@ -140,6 +149,8 @@ function(family_configure_example TARGET RTOS) # Link dependencies target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + family_add_bin_hex(${TARGET}) + # Flashing family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk index 45c3ad31d..0cf84a4ae 100644 --- a/hw/bsp/imxrt/family.mk +++ b/hw/bsp/imxrt/family.mk @@ -8,14 +8,18 @@ CPU_CORE ?= cortex-m7 MCU_VARIANT_WITH_CORE = ${MCU_VARIANT}${MCU_CORE} MCU_DIR = $(SDK_DIR)/devices/$(MCU_VARIANT) +CFLAGS += \ + -D__STARTUP_CLEAR_BSS \ + -DCFG_TUSB_MCU=OPT_MCU_MIMXRT1XXX \ + -DCFG_TUSB_MEM_SECTION='__attribute__((section("NonCacheable")))' \ + +ifneq ($(M4), 1) CFLAGS += \ -D__ARMVFP__=0 \ -D__ARMFPV5__=0 \ - -D__STARTUP_CLEAR_BSS \ -DXIP_EXTERNAL_FLASH=1 \ - -DXIP_BOOT_HEADER_ENABLE=1 \ - -DCFG_TUSB_MCU=OPT_MCU_MIMXRT1XXX \ - -DCFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) \ + -DXIP_BOOT_HEADER_ENABLE=1 +endif ifdef BOARD_TUD_RHPORT CFLAGS += -DBOARD_TUD_RHPORT=$(BOARD_TUD_RHPORT) -- cgit v1.3.1 From 5f891e020c9fb41134babeab3ce4e8574ac47d25 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 4 Nov 2024 17:24:49 +0700 Subject: usbh use the new tusb_time_delay_ms_api() fix duplicated device attach for some devices which cause "USBH Defer Attach until current enumeration complete" include dev0 for tuh_edpt_abort_xfer() --- hw/bsp/board.c | 2 +- hw/bsp/stm32f7/family.c | 6 +-- src/host/usbh.c | 104 ++++++++++++++++++++++++------------------------ 3 files changed, 56 insertions(+), 56 deletions(-) (limited to 'hw') diff --git a/hw/bsp/board.c b/hw/bsp/board.c index d4fdb7586..6d9488431 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -136,6 +136,6 @@ int board_getchar(void) { } -uint32_t tusb_time_millis(void) { +uint32_t tusb_time_millis_api(void) { return board_millis(); } diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c index f1671b362..630837d8c 100644 --- a/hw/bsp/stm32f7/family.c +++ b/hw/bsp/stm32f7/family.c @@ -173,7 +173,7 @@ void board_init(void) { #endif // vbus sense //------------- rhport1: OTG_HS -------------// - #ifdef USB_HS_PHYC +#ifdef USB_HS_PHYC // MCU with built-in HS PHY such as F723, F733, F730 /* Configure DM DP Pins */ @@ -197,7 +197,7 @@ void board_init(void) { /* Enable PHYC Clocks */ __HAL_RCC_OTGPHYC_CLK_ENABLE(); - #else +#else // MCU with external ULPI PHY /* ULPI CLK */ @@ -243,7 +243,7 @@ void board_init(void) { GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Alternate = GPIO_AF10_OTG_HS; HAL_GPIO_Init(GPIOI, &GPIO_InitStruct); - #endif // USB_HS_PHYC +#endif // USB_HS_PHYC // Enable USB HS & ULPI Clocks __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); diff --git a/src/host/usbh.c b/src/host/usbh.c index 8bf40a607..b0a2b2160 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -278,15 +278,6 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size); static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); -#if CFG_TUSB_OS == OPT_OS_NONE -// TODO rework time-related function later -// weak and overridable -TU_ATTR_WEAK void osal_task_delay(uint32_t msec) { - const uint32_t start = hcd_frame_number(_usbh_controller); - while ( ( hcd_frame_number(_usbh_controller) - start ) < msec ) {} -} -#endif - TU_ATTR_ALWAYS_INLINE static inline bool queue_event(hcd_event_t const * event, bool in_isr) { TU_ASSERT(osal_queue_send(_usbh_q, event, in_isr)); tuh_event_hook_cb(event->rhport, event->event_id, in_isr); @@ -487,17 +478,27 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { // due to the shared _usbh_ctrl_buf, we must complete enumerating one device before enumerating another one. // TODO better to have an separated queue for newly attached devices if (_dev0.enumerating) { - TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport); + // Some device can cause multiple duplicated attach events + // drop current enumerating and start over for a proper port reset + if (event.rhport == _dev0.rhport && event.connection.hub_addr == _dev0.hub_addr && + event.connection.hub_port == _dev0.hub_port) { + // abort/cancel current enumeration and start new one + TU_LOG1("[%u:] USBH Device Attach (duplicated)\r\n", event.rhport); + tuh_edpt_abort_xfer(0, 0); + enum_new_device(&event); + } else { + TU_LOG_USBH("[%u:] USBH Defer Attach until current enumeration complete\r\n", event.rhport); - bool is_empty = osal_queue_empty(_usbh_q); - queue_event(&event, in_isr); + bool is_empty = osal_queue_empty(_usbh_q); + queue_event(&event, in_isr); - if (is_empty) { - // Exit if this is the only event in the queue, otherwise we may loop forever - return; + if (is_empty) { + // Exit if this is the only event in the queue, otherwise we may loop forever + return; + } } } else { - TU_LOG_USBH("[%u:] USBH DEVICE ATTACH\r\n", event.rhport); + TU_LOG1("[%u:] USBH Device Attach\r\n", event.rhport); _dev0.enumerating = 1; enum_new_device(&event); } @@ -603,12 +604,12 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { TU_VERIFY(xfer->ep_addr == 0 && xfer->setup); // Check if device is still connected (enumerating for dev0) - uint8_t const daddr = xfer->daddr; - if ( daddr == 0 ) { - if (!_dev0.enumerating) return false; + const uint8_t daddr = xfer->daddr; + if (daddr == 0) { + TU_VERIFY(_dev0.enumerating); } else { - usbh_device_t const* dev = get_device(daddr); - if (dev && dev->connected == 0) return false; + const usbh_device_t* dev = get_device(daddr); + TU_VERIFY(dev && dev->connected); } // pre-check to help reducing mutex lock @@ -778,24 +779,26 @@ bool tuh_edpt_xfer(tuh_xfer_t* xfer) { } bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr) { - usbh_device_t* dev = get_device(daddr); - TU_VERIFY(dev); - TU_LOG_USBH("[%u] Aborted transfer on EP %02X\r\n", daddr, ep_addr); - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + const uint8_t epnum = tu_edpt_number(ep_addr); + const uint8_t dir = tu_edpt_dir(ep_addr); + + if (epnum == 0) { + // Also include dev0 for aborting enumerating + const uint8_t rhport = usbh_get_rhport(daddr); - if ( epnum == 0 ) { // control transfer: only 1 control at a time, check if we are aborting the current one TU_VERIFY(daddr == _ctrl_xfer.daddr && _ctrl_xfer.stage != CONTROL_STAGE_IDLE); - TU_VERIFY(hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr)); - // reset control transfer state to idle - _set_control_xfer_stage(CONTROL_STAGE_IDLE); + hcd_edpt_abort_xfer(rhport, daddr, ep_addr); + _set_control_xfer_stage(CONTROL_STAGE_IDLE); // reset control transfer state to idle } else { - // non-control skip if not busy - TU_VERIFY(dev->ep_status[epnum][dir].busy); - TU_VERIFY(hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr)); + usbh_device_t* dev = get_device(daddr); + TU_VERIFY(dev); + + TU_VERIFY(dev->ep_status[epnum][dir].busy); // non-control skip if not busy + hcd_edpt_abort_xfer(dev->rhport, daddr, ep_addr); + // mark as ready and release endpoint if transfer is aborted dev->ep_status[epnum][dir].busy = false; tu_edpt_release(&dev->ep_status[epnum][dir], _usbh_mutex); @@ -1281,9 +1284,9 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu //--------------------------------------------------------------------+ enum { - ENUM_RESET_DELAY = 50, // USB specs: 10 to 50ms - ENUM_CONTACT_DEBOUNCING_DELAY = 450, // when plug/unplug a device, physical connection can be bouncing and may - // generate a series of attach/detach event. This delay wait for stable connection + ENUM_RESET_DELAY_MS = 50, // USB specs: 10 to 50ms + ENUM_DEBOUNCING_DELAY_MS = 450, // when plug/unplug a device, physical connection can be bouncing and may + // generate a series of attach/detach event. This delay wait for stable connection }; enum { @@ -1322,7 +1325,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { bool retry = _dev0.enumerating && (failed_count < ATTEMPT_COUNT_MAX); if ( retry ) { failed_count++; - osal_task_delay(ATTEMPT_DELAY_MS); // delay a bit + tusb_time_delay_ms_api(ATTEMPT_DELAY_MS); // delay a bit TU_LOG1("Enumeration attempt %u\r\n", failed_count); retry = tuh_control_xfer(xfer); } @@ -1364,7 +1367,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { } case ENUM_HUB_GET_STATUS_2: - osal_task_delay(ENUM_RESET_DELAY); + tusb_time_delay_ms_api(ENUM_RESET_DELAY_MS); TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, process_enumeration, ENUM_HUB_CLEAR_RESET_2),); break; @@ -1402,7 +1405,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { if (_dev0.hub_addr == 0) { // connected directly to roothub hcd_port_reset( _dev0.rhport ); - osal_task_delay(RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since + tusb_time_delay_ms_api(RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since // sof of controller may not running while resetting hcd_port_reset_end(_dev0.rhport); // TODO: fall through to SET ADDRESS, refactor later @@ -1424,9 +1427,9 @@ static void process_enumeration(tuh_xfer_t* xfer) { case ENUM_GET_DEVICE_DESC: { // Allow 2ms for address recovery time, Ref USB Spec 9.2.6.3 - osal_task_delay(2); + tusb_time_delay_ms_api(2); - uint8_t const new_addr = (uint8_t) tu_le16toh(xfer->setup->wValue); + const uint8_t new_addr = (uint8_t) tu_le16toh(xfer->setup->wValue); usbh_device_t* new_dev = get_device(new_addr); TU_ASSERT(new_dev,); @@ -1514,6 +1517,8 @@ static void process_enumeration(tuh_xfer_t* xfer) { } } + + static bool enum_new_device(hcd_event_t* event) { _dev0.rhport = event->rhport; _dev0.hub_addr = event->connection.hub_addr; @@ -1522,19 +1527,15 @@ static bool enum_new_device(hcd_event_t* event) { if (_dev0.hub_addr == 0) { // connected directly to roothub hcd_port_reset(_dev0.rhport); -#if CFG_TUSB_OS == OPT_OS_NONE - // Since we are in middle of rhport reset, frame number is not available for time delay - // need to depend on tusb_time_millis() instead - const uint32_t start_reset = tusb_time_millis(); - while ((tusb_time_millis() - start_reset) < ENUM_RESET_DELAY) {} -#else - osal_task_delay(ENUM_RESET_DELAY); -#endif + + // Since we are in middle of rhport reset, frame number is not available yet. + // need to depend on tusb_time_millis_api() + tusb_time_delay_ms_api(ENUM_RESET_DELAY_MS); hcd_port_reset_end(_dev0.rhport); // wait until device connection is stable TODO non blocking - osal_task_delay(ENUM_CONTACT_DEBOUNCING_DELAY); + tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); // device unplugged while delaying if (!hcd_port_connect_status(_dev0.rhport)) { @@ -1557,10 +1558,9 @@ static bool enum_new_device(hcd_event_t* event) { else { // connected via external hub // wait until device connection is stable TODO non blocking - osal_task_delay(ENUM_CONTACT_DEBOUNCING_DELAY); + tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); // ENUM_HUB_GET_STATUS - //TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status0_complete, 0) ); TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, process_enumeration, ENUM_HUB_CLEAR_RESET_1)); } -- cgit v1.3.1 From e5c26924ed7061ff002961a03cd04a789cad5d8b Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 6 Nov 2024 21:46:18 +0700 Subject: update bsp for f7 --- hw/bsp/stm32f7/boards/stlinkv3mini/board.cmake | 12 ++- hw/bsp/stm32f7/boards/stlinkv3mini/board.h | 47 +++++++---- hw/bsp/stm32f7/boards/stlinkv3mini/board.mk | 4 + hw/bsp/stm32f7/boards/stm32f723disco/board.cmake | 13 ++- hw/bsp/stm32f7/boards/stm32f723disco/board.h | 97 ++++++++++------------- hw/bsp/stm32f7/boards/stm32f723disco/board.mk | 4 + hw/bsp/stm32f7/boards/stm32f746disco/board.cmake | 13 ++- hw/bsp/stm32f7/boards/stm32f746disco/board.h | 52 ++++++++---- hw/bsp/stm32f7/boards/stm32f746disco/board.mk | 4 + hw/bsp/stm32f7/boards/stm32f746nucleo/board.cmake | 9 ++- hw/bsp/stm32f7/boards/stm32f746nucleo/board.h | 50 ++++++++---- hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk | 3 + hw/bsp/stm32f7/boards/stm32f767nucleo/board.cmake | 9 ++- hw/bsp/stm32f7/boards/stm32f767nucleo/board.h | 50 ++++++++---- hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk | 3 + hw/bsp/stm32f7/boards/stm32f769disco/board.cmake | 12 ++- hw/bsp/stm32f7/boards/stm32f769disco/board.h | 51 ++++++++---- hw/bsp/stm32f7/boards/stm32f769disco/board.mk | 4 + hw/bsp/stm32f7/family.c | 68 +++++++--------- hw/bsp/stm32f7/family.cmake | 20 ++++- hw/bsp/stm32f7/family.mk | 21 +++++ 21 files changed, 362 insertions(+), 184 deletions(-) (limited to 'hw') diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/board.cmake b/hw/bsp/stm32f7/boards/stlinkv3mini/board.cmake index 378e736d4..6a1132ef8 100644 --- a/hw/bsp/stm32f7/boards/stlinkv3mini/board.cmake +++ b/hw/bsp/stm32f7/boards/stlinkv3mini/board.cmake @@ -3,12 +3,18 @@ set(JLINK_DEVICE stm32f723xx) set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F723xE_FLASH.ld) +set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) + +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 1) +endif() + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32F723xx HSE_VALUE=25000000 - # default to PORT 1 High Speed - BOARD_TUD_RHPORT=1 - BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED ) endfunction() diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/board.h b/hw/bsp/stm32f7/boards/stlinkv3mini/board.h index ed02df061..632fd99ed 100644 --- a/hw/bsp/stm32f7/boards/stlinkv3mini/board.h +++ b/hw/bsp/stm32f7/boards/stlinkv3mini/board.h @@ -31,29 +31,37 @@ extern "C" { #endif -#define LED_PORT GPIOA -#define LED_PIN GPIO_PIN_10 -#define LED_STATE_ON 1 - -// No physical button is populated -#define BUTTON_PORT GPIOA -#define BUTTON_PIN GPIO_PIN_0 -#define BUTTON_STATE_ACTIVE 1 - #define UART_DEV USART6 #define UART_CLK_EN __HAL_RCC_USART6_CLK_ENABLE -#define UART_GPIO_AF GPIO_AF8_USART6 - -#define UART_TX_PORT GPIOG -#define UART_TX_PIN GPIO_PIN_9 - -#define UART_RX_PORT GPIOG -#define UART_RX_PIN GPIO_PIN_14 // VBUS Sense detection #define OTG_FS_VBUS_SENSE 1 #define OTG_HS_VBUS_SENSE 0 +#define PINID_LED 0 +#define PINID_UART_TX 1 +#define PINID_UART_RX 2 +//#define PINID_VBUS0_EN 4 +//#define PINID_VBUS1_EN 5 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOG, + .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF8_USART6 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOG, + .pin_init = { .Pin = GPIO_PIN_14, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF8_USART6 }, + .active_state = 0 + } +}; + //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ @@ -92,8 +100,15 @@ static inline void board_clock_init(void) RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7); + + UART_CLK_EN(); +} + +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; } + #ifdef __cplusplus } #endif diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk b/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk index 94dce5e84..a19e455c7 100644 --- a/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk +++ b/hw/bsp/stm32f7/boards/stlinkv3mini/board.mk @@ -1,6 +1,10 @@ MCU_VARIANT = stm32f723xx # Only OTG-HS has a connector on this board +RHPORT_SPEED = OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 1 + PORT ?= 1 SPEED ?= high diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake b/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake index 8a7b4cb27..5655c217e 100644 --- a/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake +++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake @@ -3,12 +3,19 @@ set(JLINK_DEVICE stm32f723ie) #set(JLINK_OPTION "-USB 000776606156") set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F723xE_FLASH.ld) +set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) + +# device default to PORT 1 High Speed +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) +endif() + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32F723xx HSE_VALUE=25000000 - # default to PORT 1 High Speed - BOARD_TUD_RHPORT=1 - BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED ) endfunction() diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.h b/hw/bsp/stm32f7/boards/stm32f723disco/board.h index 37f18fedf..d45ceec5c 100644 --- a/hw/bsp/stm32f7/boards/stm32f723disco/board.h +++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.h @@ -31,28 +31,53 @@ extern "C" { #endif -#define LED_PORT GPIOB -#define LED_PIN GPIO_PIN_1 -#define LED_STATE_ON 1 - -#define BUTTON_PORT GPIOA -#define BUTTON_PIN GPIO_PIN_0 -#define BUTTON_STATE_ACTIVE 1 - #define UART_DEV USART6 #define UART_CLK_EN __HAL_RCC_USART6_CLK_ENABLE -#define UART_GPIO_AF GPIO_AF8_USART6 - -#define UART_TX_PORT GPIOC -#define UART_TX_PIN GPIO_PIN_6 - -#define UART_RX_PORT GPIOC -#define UART_RX_PIN GPIO_PIN_7 // VBUS Sense detection #define OTG_FS_VBUS_SENSE 1 #define OTG_HS_VBUS_SENSE 0 +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +#define PINID_VBUS0_EN 4 +#define PINID_VBUS1_EN 5 + +static board_pindef_t board_pindef[] = { +{ // LED + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_1, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, +{ // Button + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, +{ // UART TX + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_6, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF8_USART6 }, + .active_state = 0 + }, +{ // UART RX + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_7, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF8_USART6 }, + .active_state = 0 + }, +{ // VBUS0 EN + .port = GPIOG, + .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_OUTPUT_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 0 + }, +{ // VBUS1 EN + .port = GPIOH, + .pin_init = { .Pin = GPIO_PIN_12, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, +}; + //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ @@ -90,46 +115,12 @@ static inline void board_clock_init(void) { RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7); -} - -//static inline void board_vbus_sense_init(void) -//{ -// -//} - -typedef struct { - GPIO_TypeDef* port; - GPIO_InitTypeDef pin_init; - bool active_state; -} board_pindef_t; - -static board_pindef_t vbus_pindef[] = { -{ - .port = GPIOG, - .pin_init = { - .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_OUTPUT_OD, .Pull = GPIO_NOPULL, - .Speed = GPIO_SPEED_HIGH, .Alternate = 0 - }, - .active_state = false - }, -{ - .port = GPIOH, - .pin_init = { - .Pin = GPIO_PIN_12, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_NOPULL, - .Speed = GPIO_SPEED_HIGH, .Alternate = 0 - }, - .active_state = true - }, -}; -void board_vbus_set(uint8_t rhport, bool state) { - static bool pin_inited[2] = { false, false }; - board_pindef_t* pindef = &vbus_pindef[rhport]; - if (!pin_inited[rhport]) { - HAL_GPIO_Init(pindef->port, &pindef->pin_init); - pin_inited[rhport] = true; - } + UART_CLK_EN(); +} +static inline void board_vbus_set(uint8_t rhport, bool state) { + board_pindef_t* pindef = &board_pindef[rhport ? PINID_VBUS1_EN : PINID_VBUS0_EN]; HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET); } diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk index 43e8eafe1..c731323ca 100644 --- a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk +++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk @@ -1,5 +1,9 @@ MCU_VARIANT = stm32f723xx +RHPORT_SPEED = OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 0 + PORT ?= 1 SPEED ?= high diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/board.cmake b/hw/bsp/stm32f7/boards/stm32f746disco/board.cmake index e44c164b8..bc26c6ef4 100644 --- a/hw/bsp/stm32f7/boards/stm32f746disco/board.cmake +++ b/hw/bsp/stm32f7/boards/stm32f746disco/board.cmake @@ -3,12 +3,19 @@ set(JLINK_DEVICE stm32f746xx) set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F746ZGTx_FLASH.ld) +set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) + +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) +endif() + + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32F746xx HSE_VALUE=25000000 - # default to PORT 1 High Speed - BOARD_TUD_RHPORT=1 - BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED ) endfunction() diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/board.h b/hw/bsp/stm32f7/boards/stm32f746disco/board.h index 1c7e6dd2b..d8e92931e 100644 --- a/hw/bsp/stm32f7/boards/stm32f746disco/board.h +++ b/hw/bsp/stm32f7/boards/stm32f746disco/board.h @@ -31,28 +31,43 @@ extern "C" { #endif -#define LED_PORT GPIOI -#define LED_PIN GPIO_PIN_1 -#define LED_STATE_ON 1 - -#define BUTTON_PORT GPIOI -#define BUTTON_PIN GPIO_PIN_11 -#define BUTTON_STATE_ACTIVE 1 - #define UART_DEV USART1 #define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE -#define UART_GPIO_AF GPIO_AF7_USART1 - -#define UART_TX_PORT GPIOA -#define UART_TX_PIN GPIO_PIN_9 - -#define UART_RX_PORT GPIOB -#define UART_RX_PIN GPIO_PIN_7 // VBUS Sense detection #define OTG_FS_VBUS_SENSE 0 #define OTG_HS_VBUS_SENSE 0 +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +//#define PINID_VBUS0_EN 4 +//#define PINID_VBUS1_EN 5 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOI, + .pin_init = { .Pin = GPIO_PIN_1, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // Button + .port = GPIOI, + .pin_init = { .Pin = GPIO_PIN_11, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART1 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_7, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART1 }, + .active_state = 0 + }, +}; + //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ @@ -91,8 +106,15 @@ static inline void board_clock_init(void) RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7); + + UART_CLK_EN(); +} + +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; } + #ifdef __cplusplus } #endif diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/board.mk b/hw/bsp/stm32f7/boards/stm32f746disco/board.mk index 61c0aaa7d..c2b54406e 100644 --- a/hw/bsp/stm32f7/boards/stm32f746disco/board.mk +++ b/hw/bsp/stm32f7/boards/stm32f746disco/board.mk @@ -1,5 +1,9 @@ MCU_VARIANT = stm32f746xx +RHPORT_SPEED = OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 0 + PORT ?= 1 SPEED ?= high diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.cmake b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.cmake index dd4d4a753..fd5c1ef11 100644 --- a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.cmake +++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.cmake @@ -3,11 +3,16 @@ set(JLINK_DEVICE stm32f746xx) set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F746ZGTx_FLASH.ld) +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 0) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) +endif() + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32F746xx HSE_VALUE=8000000 - BOARD_TUD_RHPORT=0 - BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED ) endfunction() diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h index cf895af87..55e77fe5f 100644 --- a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h +++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h @@ -31,27 +31,43 @@ extern "C" { #endif -#define LED_PORT GPIOB -#define LED_PIN GPIO_PIN_14 -#define LED_STATE_ON 1 - -#define BUTTON_PORT GPIOC -#define BUTTON_PIN GPIO_PIN_13 -#define BUTTON_STATE_ACTIVE 1 - #define UART_DEV USART3 #define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE -#define UART_GPIO_AF GPIO_AF7_USART3 - -#define UART_TX_PORT GPIOD -#define UART_TX_PIN GPIO_PIN_8 -#define UART_RX_PORT GPIOD -#define UART_RX_PIN GPIO_PIN_9 // VBUS Sense detection #define OTG_FS_VBUS_SENSE 1 #define OTG_HS_VBUS_SENSE 0 +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +//#define PINID_VBUS0_EN 4 +//#define PINID_VBUS1_EN 5 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_14, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // Button + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, +}; + static inline void board_clock_init(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct; @@ -89,6 +105,12 @@ static inline void board_clock_init(void) RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7); + + UART_CLK_EN(); +} + +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; } #ifdef __cplusplus diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk index 3683c79a5..fe7104eca 100644 --- a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk +++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.mk @@ -1,5 +1,8 @@ MCU_VARIANT = stm32f746xx +RHPORT_DEVICE ?= 0 +RHPORT_HOST ?= 0 + PORT ?= 0 SPEED ?= full diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.cmake b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.cmake index 679a6ce87..e4cf4c5f5 100644 --- a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.cmake +++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.cmake @@ -3,11 +3,16 @@ set(JLINK_DEVICE stm32f767zi) set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F767ZITx_FLASH.ld) +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 0) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) +endif() + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32F767xx HSE_VALUE=8000000 - BOARD_TUD_RHPORT=0 - BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED ) endfunction() diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h index e053572a7..81cb60aeb 100644 --- a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h +++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h @@ -31,28 +31,43 @@ extern "C" { #endif -#define LED_PORT GPIOB -#define LED_PIN GPIO_PIN_14 -#define LED_STATE_ON 1 - -#define BUTTON_PORT GPIOC -#define BUTTON_PIN GPIO_PIN_13 -#define BUTTON_STATE_ACTIVE 1 - #define UART_DEV USART3 #define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE -#define UART_GPIO_AF GPIO_AF7_USART3 - -#define UART_TX_PORT GPIOD -#define UART_TX_PIN GPIO_PIN_8 - -#define UART_RX_PORT GPIOD -#define UART_RX_PIN GPIO_PIN_9 // VBUS Sense detection #define OTG_FS_VBUS_SENSE 1 #define OTG_HS_VBUS_SENSE 0 +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +//#define PINID_VBUS0_EN 4 +//#define PINID_VBUS1_EN 5 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_14, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // Button + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, +}; + //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ @@ -92,8 +107,13 @@ static inline void board_clock_init(void) RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7); + + UART_CLK_EN(); } +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} #ifdef __cplusplus } diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk index 059ad166a..d61e0a00d 100644 --- a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk +++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.mk @@ -1,5 +1,8 @@ MCU_VARIANT = stm32f767xx +RHPORT_DEVICE ?= 0 +RHPORT_HOST ?= 0 + PORT ?= 0 SPEED ?= full diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/board.cmake b/hw/bsp/stm32f7/boards/stm32f769disco/board.cmake index 329ada093..2335b869e 100644 --- a/hw/bsp/stm32f7/boards/stm32f769disco/board.cmake +++ b/hw/bsp/stm32f7/boards/stm32f769disco/board.cmake @@ -3,12 +3,18 @@ set(JLINK_DEVICE stm32f769ni) set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F769ZITx_FLASH.ld) +set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) + +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 1) +endif() + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32F769xx HSE_VALUE=25000000 - # default to PORT 1 High Speed - BOARD_TUD_RHPORT=1 - BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED ) endfunction() diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/board.h b/hw/bsp/stm32f7/boards/stm32f769disco/board.h index 472af0b98..268919b61 100644 --- a/hw/bsp/stm32f7/boards/stm32f769disco/board.h +++ b/hw/bsp/stm32f7/boards/stm32f769disco/board.h @@ -31,28 +31,43 @@ extern "C" { #endif -#define LED_PORT GPIOJ -#define LED_PIN GPIO_PIN_12 -#define LED_STATE_ON 5 - -#define BUTTON_PORT GPIOA -#define BUTTON_PIN GPIO_PIN_0 -#define BUTTON_STATE_ACTIVE 1 - #define UART_DEV USART1 #define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE -#define UART_GPIO_AF GPIO_AF7_USART1 - -#define UART_TX_PORT GPIOA -#define UART_TX_PIN GPIO_PIN_9 - -#define UART_RX_PORT GPIOA -#define UART_RX_PIN GPIO_PIN_10 // VBUS Sense detection #define OTG_FS_VBUS_SENSE 1 #define OTG_HS_VBUS_SENSE 0 +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +//#define PINID_VBUS0_EN 4 +//#define PINID_VBUS1_EN 5 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOJ, + .pin_init = { .Pin = GPIO_PIN_12, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // Button + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART1 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART1 }, + .active_state = 0 + }, +}; + //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ @@ -92,6 +107,12 @@ static inline void board_clock_init(void) RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7); + + UART_CLK_EN(); +} + +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; } #ifdef __cplusplus diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/board.mk b/hw/bsp/stm32f7/boards/stm32f769disco/board.mk index 705f1a633..e756c9727 100644 --- a/hw/bsp/stm32f7/boards/stm32f769disco/board.mk +++ b/hw/bsp/stm32f7/boards/stm32f769disco/board.mk @@ -1,6 +1,10 @@ MCU_VARIANT = stm32f769xx # Only OTG-HS has a connector on this board +RHPORT_SPEED = OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 1 + PORT ?= 1 SPEED ?= high diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c index 630837d8c..61beac47e 100644 --- a/hw/bsp/stm32f7/family.c +++ b/hw/bsp/stm32f7/family.c @@ -29,7 +29,11 @@ #include "stm32f7xx_hal.h" #include "bsp/board_api.h" -void board_vbus_set(uint8_t rhport, bool state) TU_ATTR_WEAK; +typedef struct { + GPIO_TypeDef* port; + GPIO_InitTypeDef pin_init; + uint8_t active_state; +} board_pindef_t; #include "board.h" @@ -63,12 +67,13 @@ void board_init(void) { __HAL_RCC_GPIOG_CLK_ENABLE(); __HAL_RCC_GPIOH_CLK_ENABLE(); // ULPI NXT __HAL_RCC_GPIOI_CLK_ENABLE(); // ULPI NXT - #ifdef __HAL_RCC_GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE(); #endif - UART_CLK_EN(); + for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) { + HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init); + } #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer @@ -83,38 +88,7 @@ void board_init(void) { NVIC_SetPriority(OTG_HS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); #endif - GPIO_InitTypeDef GPIO_InitStruct; - - // LED - GPIO_InitStruct.Pin = LED_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct); - - // Button - GPIO_InitStruct.Pin = BUTTON_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); - - // Uart TX - GPIO_InitStruct.Pin = UART_TX_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - GPIO_InitStruct.Alternate = UART_GPIO_AF; - HAL_GPIO_Init(UART_TX_PORT, &GPIO_InitStruct); - - // Uart RX - GPIO_InitStruct.Pin = UART_RX_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - GPIO_InitStruct.Alternate = UART_GPIO_AF; - HAL_GPIO_Init(UART_RX_PORT, &GPIO_InitStruct); - +#ifdef UART_DEV UartHandle.Instance = UART_DEV; UartHandle.Init.BaudRate = CFG_BOARD_UART_BAUDRATE; UartHandle.Init.WordLength = UART_WORDLENGTH_8B; @@ -124,6 +98,9 @@ void board_init(void) { UartHandle.Init.Mode = UART_MODE_TX_RX; UartHandle.Init.OverSampling = UART_OVERSAMPLING_16; HAL_UART_Init(&UartHandle); +#endif + + GPIO_InitTypeDef GPIO_InitStruct; //------------- rhport0: OTG_FS -------------// /* Configure DM DP Pins */ @@ -271,12 +248,22 @@ void board_init(void) { //--------------------------------------------------------------------+ void board_led_write(bool state) { - GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1 - LED_STATE_ON)); - HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state); +#ifdef PINID_LED + board_pindef_t* pindef = &board_pindef[PINID_LED]; + GPIO_PinState pin_state = state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, pin_state); +#else + (void) state; +#endif } uint32_t board_button_read(void) { - return HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN); +#ifdef PINID_BUTTON + board_pindef_t* pindef = &board_pindef[PINID_BUTTON]; + return pindef->active_state == HAL_GPIO_ReadPin(pindef->port, pindef->pin_init.Pin); +#else + return 0; +#endif } size_t board_get_unique_id(uint8_t id[], size_t max_len) { @@ -299,8 +286,13 @@ int board_uart_read(uint8_t *buf, int len) { } int board_uart_write(void const *buf, int len) { +#ifdef UART_DEV HAL_UART_Transmit(&UartHandle, (uint8_t *) (uintptr_t) buf, len, 0xffff); return len; +#else + (void) buf; (void) len; + return -1; +#endif } #if CFG_TUSB_OS == OPT_OS_NONE diff --git a/hw/bsp/stm32f7/family.cmake b/hw/bsp/stm32f7/family.cmake index 798dc4dbb..2186a526d 100644 --- a/hw/bsp/stm32f7/family.cmake +++ b/hw/bsp/stm32f7/family.cmake @@ -16,6 +16,18 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL set(FAMILY_MCUS STM32F7 CACHE INTERNAL "") +if (NOT DEFINED RHPORT_SPEED) + # Most F7 does not has built-in HS PHY + set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_FULL_SPEED) +endif () +if (NOT DEFINED RHPORT_DEVICE_SPEED) + list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED) +endif () +if (NOT DEFINED RHPORT_HOST_SPEED) + list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED) +endif () + +cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED) #------------------------------------ # BOARD_TARGET @@ -54,8 +66,12 @@ function(add_board_target BOARD_TARGET) ${ST_CMSIS}/Include ${ST_HAL_DRIVER}/Inc ) - #target_compile_options(${BOARD_TARGET} PUBLIC) - #target_compile_definitions(${BOARD_TARGET} PUBLIC) + target_compile_definitions(${BOARD_TARGET} PUBLIC + BOARD_TUD_RHPORT=${RHPORT_DEVICE} + BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} + BOARD_TUH_RHPORT=${RHPORT_HOST} + BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} + ) update_board(${BOARD_TARGET}) diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk index 4e9cc152d..429170f86 100644 --- a/hw/bsp/stm32f7/family.mk +++ b/hw/bsp/stm32f7/family.mk @@ -8,6 +8,27 @@ ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m7-fpsp +# Default RHPORT_SPEED if not defined +RHPORT_SPEED ?= OPT_MODE_FULL_SPEED OPT_MODE_FULL_SPEED + +# Determine RHPORT_DEVICE_SPEED if not defined +ifndef RHPORT_DEVICE_SPEED +ifeq ($(RHPORT_DEVICE), 0) + RHPORT_DEVICE_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_DEVICE_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif + +# Determine RHPORT_HOST_SPEED if not defined +ifndef RHPORT_HOST_SPEED +ifeq ($(RHPORT_HOST), 0) + RHPORT_HOST_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_HOST_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif + # -------------- # Compiler Flags # -------------- -- cgit v1.3.1 From 772edf879be75b121ac4e9ff21081495a623a64e Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 6 Nov 2024 22:13:05 +0700 Subject: fix iar build --- .../dual/host_hid_to_device_cdc/CMakeLists.txt | 22 ++++++++++++---------- examples/dual/host_hid_to_device_cdc/Makefile | 2 +- .../dual/host_info_to_device_cdc/CMakeLists.txt | 22 ++++++++++++---------- examples/dual/host_info_to_device_cdc/Makefile | 2 +- hw/bsp/stm32f7/family.cmake | 2 -- 5 files changed, 26 insertions(+), 24 deletions(-) (limited to 'hw') diff --git a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt index a6557c2d0..54e36e3d3 100644 --- a/examples/dual/host_hid_to_device_cdc/CMakeLists.txt +++ b/examples/dual/host_hid_to_device_cdc/CMakeLists.txt @@ -28,13 +28,15 @@ target_include_directories(${PROJECT} PUBLIC family_configure_dual_usb_example(${PROJECT} noos) # due to warnings from Pico-PIO-USB -target_compile_options(${PROJECT} PUBLIC - -Wno-error=shadow - -Wno-error=cast-align - -Wno-error=cast-qual - -Wno-error=redundant-decls - -Wno-error=sign-conversion - -Wno-error=conversion - -Wno-error=sign-compare - -Wno-error=unused-function - ) +if (FAMILY STREQUAL rp2040) + target_compile_options(${PROJECT} PUBLIC + -Wno-error=shadow + -Wno-error=cast-align + -Wno-error=cast-qual + -Wno-error=redundant-decls + -Wno-error=sign-conversion + -Wno-error=conversion + -Wno-error=sign-compare + -Wno-error=unused-function + ) +endif () diff --git a/examples/dual/host_hid_to_device_cdc/Makefile b/examples/dual/host_hid_to_device_cdc/Makefile index 2c2168f5d..474ae9814 100644 --- a/examples/dual/host_hid_to_device_cdc/Makefile +++ b/examples/dual/host_hid_to_device_cdc/Makefile @@ -8,7 +8,7 @@ INC += \ EXAMPLE_SOURCE += $(wildcard src/*.c) SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) -CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference +CFLAGS_GCC += -Wno-error=cast-align -Wno-error=null-dereference SRC_C += \ src/class/hid/hid_host.c \ diff --git a/examples/dual/host_info_to_device_cdc/CMakeLists.txt b/examples/dual/host_info_to_device_cdc/CMakeLists.txt index a6557c2d0..54e36e3d3 100644 --- a/examples/dual/host_info_to_device_cdc/CMakeLists.txt +++ b/examples/dual/host_info_to_device_cdc/CMakeLists.txt @@ -28,13 +28,15 @@ target_include_directories(${PROJECT} PUBLIC family_configure_dual_usb_example(${PROJECT} noos) # due to warnings from Pico-PIO-USB -target_compile_options(${PROJECT} PUBLIC - -Wno-error=shadow - -Wno-error=cast-align - -Wno-error=cast-qual - -Wno-error=redundant-decls - -Wno-error=sign-conversion - -Wno-error=conversion - -Wno-error=sign-compare - -Wno-error=unused-function - ) +if (FAMILY STREQUAL rp2040) + target_compile_options(${PROJECT} PUBLIC + -Wno-error=shadow + -Wno-error=cast-align + -Wno-error=cast-qual + -Wno-error=redundant-decls + -Wno-error=sign-conversion + -Wno-error=conversion + -Wno-error=sign-compare + -Wno-error=unused-function + ) +endif () diff --git a/examples/dual/host_info_to_device_cdc/Makefile b/examples/dual/host_info_to_device_cdc/Makefile index 0ede79c17..083c9169a 100644 --- a/examples/dual/host_info_to_device_cdc/Makefile +++ b/examples/dual/host_info_to_device_cdc/Makefile @@ -8,7 +8,7 @@ INC += \ EXAMPLE_SOURCE += $(wildcard src/*.c) SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) -CFLAGS += -Wno-error=cast-align -Wno-error=null-dereference +CFLAGS_GCC += -Wno-error=cast-align -Wno-error=null-dereference SRC_C += \ src/host/hub.c \ diff --git a/hw/bsp/stm32f7/family.cmake b/hw/bsp/stm32f7/family.cmake index 2186a526d..0bf90a8bd 100644 --- a/hw/bsp/stm32f7/family.cmake +++ b/hw/bsp/stm32f7/family.cmake @@ -27,8 +27,6 @@ if (NOT DEFINED RHPORT_HOST_SPEED) list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED) endif () -cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED) - #------------------------------------ # BOARD_TARGET #------------------------------------ -- cgit v1.3.1 From 4baeeeb564ca4c06a2c7b65fabf764fe0d96e93c Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 7 Nov 2024 09:49:04 +0700 Subject: enable stm32f4 host --- examples/host/cdc_msc_hid/only.txt | 1 + examples/host/msc_file_explorer/only.txt | 1 + .../stm32f4/boards/feather_stm32f405/board.cmake | 1 - hw/bsp/stm32f4/boards/feather_stm32f405/board.h | 60 +++++++---- hw/bsp/stm32f4/boards/pyboardv11/board.cmake | 1 - hw/bsp/stm32f4/boards/pyboardv11/board.h | 60 +++++++---- .../stm32f4/boards/stm32f401blackpill/board.cmake | 1 - hw/bsp/stm32f4/boards/stm32f401blackpill/board.h | 64 +++++++----- .../stm32f4/boards/stm32f407blackvet/board.cmake | 2 - hw/bsp/stm32f4/boards/stm32f407blackvet/board.h | 54 ++++++---- hw/bsp/stm32f4/boards/stm32f407disco/board.cmake | 1 - hw/bsp/stm32f4/boards/stm32f407disco/board.h | 70 +++++++++---- .../stm32f4/boards/stm32f411blackpill/board.cmake | 1 - hw/bsp/stm32f4/boards/stm32f411blackpill/board.h | 63 ++++++----- hw/bsp/stm32f4/boards/stm32f411disco/board.cmake | 1 - hw/bsp/stm32f4/boards/stm32f411disco/board.h | 70 ++++++++----- hw/bsp/stm32f4/boards/stm32f412disco/board.cmake | 1 - hw/bsp/stm32f4/boards/stm32f412disco/board.h | 62 ++++++++--- hw/bsp/stm32f4/boards/stm32f412nucleo/board.h | 69 +++++++++---- hw/bsp/stm32f4/boards/stm32f439nucleo/board.h | 70 +++++++++---- hw/bsp/stm32f4/family.c | 115 ++++++++++++--------- hw/bsp/stm32f4/family.cmake | 30 +++++- hw/bsp/stm32f4/family.mk | 30 +++++- hw/bsp/stm32f7/family.cmake | 10 ++ hw/bsp/stm32f7/family.mk | 35 ++++--- 25 files changed, 587 insertions(+), 286 deletions(-) (limited to 'hw') diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt index 9b3d6994e..2c88734d3 100644 --- a/examples/host/cdc_msc_hid/only.txt +++ b/examples/host/cdc_msc_hid/only.txt @@ -12,4 +12,5 @@ mcu:MSP432E4 mcu:RX65X mcu:RAXXX mcu:MAX3421 +mcu:STM32F4 mcu:STM32F7 diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt index 9b3d6994e..2c88734d3 100644 --- a/examples/host/msc_file_explorer/only.txt +++ b/examples/host/msc_file_explorer/only.txt @@ -12,4 +12,5 @@ mcu:MSP432E4 mcu:RX65X mcu:RAXXX mcu:MAX3421 +mcu:STM32F4 mcu:STM32F7 diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/board.cmake b/hw/bsp/stm32f4/boards/feather_stm32f405/board.cmake index fff6c502d..4910d3a88 100644 --- a/hw/bsp/stm32f4/boards/feather_stm32f405/board.cmake +++ b/hw/bsp/stm32f4/boards/feather_stm32f405/board.cmake @@ -6,6 +6,5 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F405RGTx_FLASH.ld) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32F405xx - BOARD_TUD_RHPORT=0 ) endfunction() diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h index d1ad2a6ce..b4ca8d275 100644 --- a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h +++ b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h @@ -31,22 +31,35 @@ extern "C" { #endif -// LED -#define LED_PORT GPIOC -#define LED_PIN GPIO_PIN_1 -#define LED_STATE_ON 1 +#define UART_DEV USART3 -// Button: Pin D5 -#define BUTTON_PORT GPIOC -#define BUTTON_PIN GPIO_PIN_7 -#define BUTTON_STATE_ACTIVE 0 +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 -// UART -#define UART_DEV USART3 -#define UART_GPIO_PORT GPIOB -#define UART_GPIO_AF GPIO_AF7_USART3 -#define UART_TX_PIN GPIO_PIN_10 -#define UART_RX_PIN GPIO_PIN_11 +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_4, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // BUTTON + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_7, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 0 + }, + { // UART TX + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, +}; //--------------------------------------------------------------------+ // RCC Clock @@ -84,17 +97,20 @@ static inline void board_clock_init(void) RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); - // Enable clocks for LED, Button, Uart - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); + // Enable clocks for Uart __HAL_RCC_USART3_CLK_ENABLE(); } -static inline void board_vbus_sense_init(void) -{ - // Enable VBUS sense (B device) via pin PA9 - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; +static inline void board_vbus_sense_init(uint8_t rhport) { + if (rhport == 0) { + // Enable VBUS sense (B device) via pin PA9 + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; + } +} + +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; } #ifdef __cplusplus diff --git a/hw/bsp/stm32f4/boards/pyboardv11/board.cmake b/hw/bsp/stm32f4/boards/pyboardv11/board.cmake index fff6c502d..4910d3a88 100644 --- a/hw/bsp/stm32f4/boards/pyboardv11/board.cmake +++ b/hw/bsp/stm32f4/boards/pyboardv11/board.cmake @@ -6,6 +6,5 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F405RGTx_FLASH.ld) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32F405xx - BOARD_TUD_RHPORT=0 ) endfunction() diff --git a/hw/bsp/stm32f4/boards/pyboardv11/board.h b/hw/bsp/stm32f4/boards/pyboardv11/board.h index c126f0666..077313518 100644 --- a/hw/bsp/stm32f4/boards/pyboardv11/board.h +++ b/hw/bsp/stm32f4/boards/pyboardv11/board.h @@ -31,22 +31,35 @@ extern "C" { #endif -// Blue LED is chosen because the other LEDs are connected to ST-LINK lines. -#define LED_PORT GPIOB -#define LED_PIN GPIO_PIN_4 -#define LED_STATE_ON 1 +#define UART_DEV USART2 -#define BUTTON_PORT GPIOB -#define BUTTON_PIN GPIO_PIN_3 -#define BUTTON_STATE_ACTIVE 1 +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 -// Enable PA2 as the debug log UART -// It is not routed to the ST/Link on the Discovery board. -//#define UART_DEV USART2 -//#define UART_GPIO_PORT GPIOA -//#define UART_GPIO_AF GPIO_AF7_USART2 -//#define UART_TX_PIN GPIO_PIN_2 -//#define UART_RX_PIN GPIO_PIN_3 +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_4, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // BUTTON + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 }, + .active_state = 0 + }, +}; //--------------------------------------------------------------------+ // RCC Clock @@ -84,15 +97,20 @@ static inline void board_clock_init(void) RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); - // Enable clocks for LED, Button, Uart - __HAL_RCC_GPIOB_CLK_ENABLE(); + // Enable clocks for Uart + __HAL_RCC_USART2_CLK_ENABLE(); } -static inline void board_vbus_sense_init(void) -{ - // Enable VBUS sense (B device) via pin PA9 - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; +static inline void board_vbus_sense_init(uint8_t rhport) { + if (rhport == 0) { + // Enable VBUS sense (B device) via pin PA9 + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; + } +} + +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; } #ifdef __cplusplus diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.cmake b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.cmake index bf2bef38b..fab6a42d2 100644 --- a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.cmake +++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.cmake @@ -6,6 +6,5 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F401VCTx_FLASH.ld) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32F405xx - BOARD_TUD_RHPORT=0 ) endfunction() diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h index e6c99a462..ef40089c9 100644 --- a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h +++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h @@ -31,23 +31,36 @@ extern "C" { #endif -// LED -#define LED_PORT GPIOC -#define LED_PIN GPIO_PIN_13 -#define LED_STATE_ON 0 - -// Button -#define BUTTON_PORT GPIOA -#define BUTTON_PIN GPIO_PIN_0 -#define BUTTON_STATE_ACTIVE 0 - // Enable PA2 as the debug log UART -//#define UART_DEV USART2 -//#define UART_GPIO_PORT GPIOA -//#define UART_GPIO_AF GPIO_AF7_USART2 -//#define UART_TX_PIN GPIO_PIN_2 -//#define UART_RX_PIN GPIO_PIN_3 +#define UART_DEV USART2 + +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 0 + }, + { // BUTTON + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 0 + }, + { // UART TX + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 }, + .active_state = 0 + }, +}; //--------------------------------------------------------------------+ // RCC Clock @@ -85,18 +98,21 @@ static inline void board_clock_init(void) RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2); - // Enable clocks for LED, Button, Uart - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - //__HAL_RCC_USART2_CLK_ENABLE(); + // Enable clocks for Uart + __HAL_RCC_USART2_CLK_ENABLE(); } -static inline void board_vbus_sense_init(void) -{ +static inline void board_vbus_sense_init(uint8_t rhport) { // Blackpill doesn't use VBUS sense (B device) explicitly disable it - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; + if (rhport == 0) { + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; + } +} + +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; } #ifdef __cplusplus diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.cmake b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.cmake index 64626d7bd..50e6b1592 100644 --- a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.cmake +++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.cmake @@ -7,7 +7,5 @@ function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32F407xx HSE_VALUE=8000000 - BOARD_TUD_RHPORT=0 - BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED ) endfunction() diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h index b7a6d96c2..ea4c462c3 100644 --- a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h +++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h @@ -31,24 +31,36 @@ extern "C" { #endif -// LED -#define LED_PORT GPIOA -#define LED_PIN GPIO_PIN_6 -#define LED_STATE_ON 1 - -// Button -#define BUTTON_PORT GPIOE -#define BUTTON_PIN GPIO_PIN_4 -#define BUTTON_STATE_ACTIVE 0 - // Enable PA2 as the debug log UART -// It is not routed to the ST/Link on the Discovery board. #define UART_DEV USART2 -#define UART_GPIO_PORT GPIOA -#define UART_GPIO_AF GPIO_AF7_USART2 -#define UART_TX_PIN GPIO_PIN_2 -#define UART_RX_PIN GPIO_PIN_3 +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_6, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // BUTTON + .port = GPIOE, + .pin_init = { .Pin = GPIO_PIN_4, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 }, + .active_state = 0 + }, +}; //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ @@ -86,18 +98,20 @@ static inline void board_clock_init(void) HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); // Enable clocks for LED, Button, Uart - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOE_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); __HAL_RCC_USART2_CLK_ENABLE(); } -static inline void board_vbus_sense_init(void) -{ +static inline void board_vbus_sense_init(uint8_t rhport) { + if (rhport == 0) { // Black F407VET6 doesn't use VBUS sense (B device) explicitly disable it USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; + } +} + +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; } #ifdef __cplusplus diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/board.cmake b/hw/bsp/stm32f4/boards/stm32f407disco/board.cmake index b2514dc5e..c8f0330ed 100644 --- a/hw/bsp/stm32f4/boards/stm32f407disco/board.cmake +++ b/hw/bsp/stm32f4/boards/stm32f407disco/board.cmake @@ -6,6 +6,5 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F407VGTx_FLASH.ld) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32F407xx - BOARD_TUD_RHPORT=0 ) endfunction() diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/board.h b/hw/bsp/stm32f4/boards/stm32f407disco/board.h index c38f354ce..380f8e391 100644 --- a/hw/bsp/stm32f4/boards/stm32f407disco/board.h +++ b/hw/bsp/stm32f4/boards/stm32f407disco/board.h @@ -31,23 +31,43 @@ extern "C" { #endif -// LED -#define LED_PORT GPIOD -#define LED_PIN GPIO_PIN_14 -#define LED_STATE_ON 1 - -// Button -#define BUTTON_PORT GPIOA -#define BUTTON_PIN GPIO_PIN_0 -#define BUTTON_STATE_ACTIVE 1 - // Enable PA2 as the debug log UART // It is not routed to the ST/Link on the Discovery board. #define UART_DEV USART2 -#define UART_GPIO_PORT GPIOA -#define UART_GPIO_AF GPIO_AF7_USART2 -#define UART_TX_PIN GPIO_PIN_2 -#define UART_RX_PIN GPIO_PIN_3 + +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +#define PINID_VBUS0_EN 4 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_14, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // BUTTON + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 }, + .active_state = 0 + }, + { // VBUS0 EN + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 0 + } +}; //--------------------------------------------------------------------+ // RCC Clock @@ -85,17 +105,23 @@ static inline void board_clock_init(void) RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); - // Enable clocks for LED, Button, Uart - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); + // Enable clocks Uart __HAL_RCC_USART2_CLK_ENABLE(); } -static inline void board_vbus_sense_init(void) -{ - // Enable VBUS sense (B device) via pin PA9 - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; +static inline void board_vbus_sense_init(uint8_t rhport) { + if (rhport == 0) { + // Enable VBUS sense (B device) via pin PA9 + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; + } +} + +static inline void board_vbus_set(uint8_t rhport, bool state) { + if (rhport == 0) { + board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN]; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET); + } } #ifdef __cplusplus diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake index 185507d7f..d16db508f 100644 --- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake +++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.cmake @@ -6,6 +6,5 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F411CEUx_FLASH.ld) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32F411xE - BOARD_TUD_RHPORT=0 ) endfunction() diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h index e6c99a462..efa618b72 100644 --- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h +++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h @@ -31,23 +31,35 @@ extern "C" { #endif -// LED -#define LED_PORT GPIOC -#define LED_PIN GPIO_PIN_13 -#define LED_STATE_ON 0 +#define UART_DEV USART2 -// Button -#define BUTTON_PORT GPIOA -#define BUTTON_PIN GPIO_PIN_0 -#define BUTTON_STATE_ACTIVE 0 - -// Enable PA2 as the debug log UART -//#define UART_DEV USART2 -//#define UART_GPIO_PORT GPIOA -//#define UART_GPIO_AF GPIO_AF7_USART2 -//#define UART_TX_PIN GPIO_PIN_2 -//#define UART_RX_PIN GPIO_PIN_3 +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 0 + }, + { // BUTTON + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 0 + }, + { // UART TX + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 }, + .active_state = 0 + }, +}; //--------------------------------------------------------------------+ // RCC Clock @@ -85,18 +97,21 @@ static inline void board_clock_init(void) RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2); - // Enable clocks for LED, Button, Uart - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - //__HAL_RCC_USART2_CLK_ENABLE(); + // Enable clocks for Uart + __HAL_RCC_USART2_CLK_ENABLE(); } -static inline void board_vbus_sense_init(void) -{ +static inline void board_vbus_sense_init(uint8_t rhport) { // Blackpill doesn't use VBUS sense (B device) explicitly disable it - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; + if (rhport == 0) { + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; + } +} + +static inline void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; } #ifdef __cplusplus diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/board.cmake b/hw/bsp/stm32f4/boards/stm32f411disco/board.cmake index 80cf94160..d7c32c27d 100644 --- a/hw/bsp/stm32f4/boards/stm32f411disco/board.cmake +++ b/hw/bsp/stm32f4/boards/stm32f411disco/board.cmake @@ -6,6 +6,5 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F411VETx_FLASH.ld) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32F411xE - BOARD_TUD_RHPORT=0 ) endfunction() diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/board.h b/hw/bsp/stm32f4/boards/stm32f411disco/board.h index 57d1e061e..d4bad8e40 100644 --- a/hw/bsp/stm32f4/boards/stm32f411disco/board.h +++ b/hw/bsp/stm32f4/boards/stm32f411disco/board.h @@ -31,28 +31,46 @@ extern "C" { #endif -// Orange LED -#define LED_PORT GPIOD -#define LED_PIN GPIO_PIN_13 -#define LED_STATE_ON 1 - -#define BUTTON_PORT GPIOA -#define BUTTON_PIN GPIO_PIN_0 -#define BUTTON_STATE_ACTIVE 1 - -// Enable PA2 as the debug log UART #define UART_DEV USART2 -#define UART_GPIO_PORT GPIOA -#define UART_GPIO_AF GPIO_AF7_USART2 -#define UART_TX_PIN GPIO_PIN_2 -#define UART_RX_PIN GPIO_PIN_3 +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +#define PINID_VBUS0_EN 4 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // BUTTON + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 }, + .active_state = 0 + }, + { // VBUS0 EN + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 0 + } +}; //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ -static inline void board_clock_init(void) -{ +static inline void board_clock_init(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; @@ -84,17 +102,23 @@ static inline void board_clock_init(void) RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2); - // Enable clocks for LED, Button, Uart - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); + // Enable clocks for UART __HAL_RCC_USART2_CLK_ENABLE(); } -static inline void board_vbus_sense_init(void) -{ +static inline void board_vbus_sense_init(uint8_t rhport) { // Enable VBUS sense (B device) via pin PA9 - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; + if (rhport == 0) { + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; + } +} + +static inline void board_vbus_set(uint8_t rhport, bool state) { + if (rhport == 0) { + board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN]; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET); + } } #ifdef __cplusplus diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/board.cmake b/hw/bsp/stm32f4/boards/stm32f412disco/board.cmake index c282af98e..59c1c3a7b 100644 --- a/hw/bsp/stm32f4/boards/stm32f412disco/board.cmake +++ b/hw/bsp/stm32f4/boards/stm32f412disco/board.cmake @@ -7,6 +7,5 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F412ZGTx_FLASH.ld) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32F412Zx - BOARD_TUD_RHPORT=0 ) endfunction() diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/board.h b/hw/bsp/stm32f4/boards/stm32f412disco/board.h index d61b70eb9..d89ff7d3d 100644 --- a/hw/bsp/stm32f4/boards/stm32f412disco/board.h +++ b/hw/bsp/stm32f4/boards/stm32f412disco/board.h @@ -43,16 +43,45 @@ // UART Enable PA2 as the debug log UART #define UART_DEV USART2 -#define UART_GPIO_PORT GPIOA -#define UART_GPIO_AF GPIO_AF7_USART2 -#define UART_TX_PIN GPIO_PIN_2 -#define UART_RX_PIN GPIO_PIN_3 + +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +#define PINID_VBUS0_EN 4 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOE, + .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 0 + }, + { // BUTTON + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART2 }, + .active_state = 0 + }, + { // VBUS0 EN + .port = GPIOG, + .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 0 + } +}; //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ -static inline void board_clock_init(void) -{ +static inline void board_clock_init(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_OscInitTypeDef RCC_OscInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct; @@ -99,18 +128,25 @@ static inline void board_clock_init(void) RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); - // Enable clocks for LED, Button, Uart - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOE_CLK_ENABLE(); + // Enable clocks for Uart __HAL_RCC_USART2_CLK_ENABLE(); } -static inline void board_vbus_sense_init(void) -{ - // Enable VBUS sense (B device) via pin PA9 - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; +static inline void board_vbus_sense_init(uint8_t rhport) { + if (rhport == 0) { + // Enable VBUS sense (B device) via pin PA9 + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; + } +} + +static inline void board_vbus_set(uint8_t rhport, bool state) { + if (rhport == 0) { + board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN]; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET); + } } + #ifdef __cplusplus } #endif diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h index 73c5f83b9..8900a1e6b 100644 --- a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h +++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h @@ -31,22 +31,42 @@ extern "C" { #endif -// LED -#define LED_PORT GPIOB -#define LED_PIN GPIO_PIN_14 -#define LED_STATE_ON 0 - -// Button -#define BUTTON_PORT GPIOC -#define BUTTON_PIN GPIO_PIN_13 -#define BUTTON_STATE_ACTIVE 1 - // UART Enable for STLink VCOM #define UART_DEV USART3 -#define UART_GPIO_PORT GPIOD -#define UART_GPIO_AF GPIO_AF7_USART3 -#define UART_TX_PIN GPIO_PIN_8 -#define UART_RX_PIN GPIO_PIN_9 + +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +#define PINID_VBUS0_EN 4 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_14, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 0 + }, + { // BUTTON + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // VBUS0 EN + .port = GPIOG, + .pin_init = { .Pin = GPIO_PIN_6, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + } +}; //--------------------------------------------------------------------+ // RCC Clock @@ -99,17 +119,22 @@ static inline void board_clock_init(void) RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3); - // Enable clocks for LED, Button, Uart - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); + // Enable clocks for Uart __HAL_RCC_USART3_CLK_ENABLE(); } -static inline void board_vbus_sense_init(void) -{ - // Enable VBUS sense (B device) via pin PA9 - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; +static inline void board_vbus_sense_init(uint8_t rhport) { + if (rhport == 0) { + // Enable VBUS sense (B device) via pin PA9 + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBDEN; + } +} + +static inline void board_vbus_set(uint8_t rhport, bool state) { + if (rhport == 0) { + board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN]; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET); + } } #ifdef __cplusplus diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h index e5a822426..aa9de4073 100644 --- a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h +++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h @@ -31,22 +31,43 @@ extern "C" { #endif -// LED -#define LED_PORT GPIOB -#define LED_PIN GPIO_PIN_14 -#define LED_STATE_ON 0 - -// Button -#define BUTTON_PORT GPIOC -#define BUTTON_PIN GPIO_PIN_13 -#define BUTTON_STATE_ACTIVE 1 // UART Enable for STLink VCOM #define UART_DEV USART3 -#define UART_GPIO_PORT GPIOD -#define UART_GPIO_AF GPIO_AF7_USART3 -#define UART_TX_PIN GPIO_PIN_8 -#define UART_RX_PIN GPIO_PIN_9 + +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +#define PINID_VBUS0_EN 4 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_14, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 0 + }, + { // BUTTON + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // VBUS0 EN + .port = GPIOG, + .pin_init = { .Pin = GPIO_PIN_6, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + } +}; //--------------------------------------------------------------------+ // RCC Clock @@ -87,18 +108,23 @@ static inline void board_clock_init(void) RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5); - // Enable clocks for LED, Button, Uart - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); + // Enable clocks Uart __HAL_RCC_USART3_CLK_ENABLE(); } -static inline void board_vbus_sense_init(void) -{ - // Enable VBUS sense (B device) via pin PA9 - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; +static inline void board_vbus_sense_init(uint8_t rhport) { + if (rhport == 0) { + // Enable VBUS sense (B device) via pin PA9 + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; + } +} + +static inline void board_vbus_set(uint8_t rhport, bool state) { + if (rhport == 0) { + board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN]; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET); + } } #ifdef __cplusplus diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c index b4a661421..866a09d6f 100644 --- a/hw/bsp/stm32f4/family.c +++ b/hw/bsp/stm32f4/family.c @@ -26,6 +26,13 @@ #include "stm32f4xx_hal.h" #include "bsp/board_api.h" + +typedef struct { + GPIO_TypeDef* port; + GPIO_InitTypeDef pin_init; + uint8_t active_state; +} board_pindef_t; + #include "board.h" //--------------------------------------------------------------------+ @@ -42,12 +49,49 @@ void OTG_HS_IRQHandler(void) { //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -UART_HandleTypeDef UartHandle; +UART_HandleTypeDef UartHandle = { + .Instance = UART_DEV, + .Init = { + .BaudRate = CFG_BOARD_UART_BAUDRATE, + .WordLength = UART_WORDLENGTH_8B, + .StopBits = UART_STOPBITS_1, + .Parity = UART_PARITY_NONE, + .HwFlowCtl = UART_HWCONTROL_NONE, + .Mode = UART_MODE_TX_RX, + .OverSampling = UART_OVERSAMPLING_16 + } +}; void board_init(void) { board_clock_init(); //SystemCoreClockUpdate(); + // Enable All GPIOs clocks + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_GPIOD_CLK_ENABLE(); +#ifdef __HAL_RCC_GPIOE_CLK_ENABLE + __HAL_RCC_GPIOE_CLK_ENABLE(); +#endif +#ifdef __HAL_RCC_GPIOF_CLK_ENABLE + __HAL_RCC_GPIOF_CLK_ENABLE(); +#endif +#ifdef __HAL_RCC_GPIOG_CLK_ENABLE + __HAL_RCC_GPIOG_CLK_ENABLE(); +#endif + __HAL_RCC_GPIOH_CLK_ENABLE(); +#ifdef __HAL_RCC_GPIOI_CLK_ENABLE + __HAL_RCC_GPIOI_CLK_ENABLE(); +#endif +#ifdef __HAL_RCC_GPIOJ_CLK_ENABLE + __HAL_RCC_GPIOJ_CLK_ENABLE(); +#endif + + for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) { + HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init); + } + #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); @@ -59,49 +103,14 @@ void board_init(void) { NVIC_SetPriority(OTG_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); #endif - GPIO_InitTypeDef GPIO_InitStruct; - - // LED - GPIO_InitStruct.Pin = LED_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct); - board_led_write(false); - // Button - GPIO_InitStruct.Pin = BUTTON_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); - #ifdef UART_DEV - // UART - GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - GPIO_InitStruct.Alternate = UART_GPIO_AF; - HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct); - - UartHandle = (UART_HandleTypeDef) { - .Instance = UART_DEV, - .Init.BaudRate = CFG_BOARD_UART_BAUDRATE, - .Init.WordLength = UART_WORDLENGTH_8B, - .Init.StopBits = UART_STOPBITS_1, - .Init.Parity = UART_PARITY_NONE, - .Init.HwFlowCtl = UART_HWCONTROL_NONE, - .Init.Mode = UART_MODE_TX_RX, - .Init.OverSampling = UART_OVERSAMPLING_16 - }; HAL_UART_Init(&UartHandle); #endif -#if BOARD_TUD_RHPORT == 0 - /* Configure USB FS GPIOs */ - __HAL_RCC_GPIOA_CLK_ENABLE(); + //------------- USB FS -------------// + GPIO_InitTypeDef GPIO_InitStruct; /* Configure USB D+ D- Pins */ GPIO_InitStruct.Pin = GPIO_PIN_11 | GPIO_PIN_12; @@ -127,11 +136,9 @@ void board_init(void) { // Enable USB OTG clock __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); -#else - /* Configure USB HS GPIOs */ - __HAL_RCC_GPIOB_CLK_ENABLE(); - /* Configure USB D+ D- Pins */ + //------------- USB HS -------------// +#ifdef __HAL_RCC_USB_OTG_HS_CLK_ENABLE GPIO_InitStruct.Pin = GPIO_PIN_14 | GPIO_PIN_15; GPIO_InitStruct.Speed = GPIO_SPEED_HIGH; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -166,7 +173,13 @@ void board_init(void) { HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); #endif - board_vbus_sense_init(); +#if CFG_TUD_ENABLED + board_vbus_sense_init(BOARD_TUD_RHPORT); +#endif + +#if CFG_TUH_ENABLED + board_vbus_set(BOARD_TUD_RHPORT, true); +#endif } //--------------------------------------------------------------------+ @@ -174,12 +187,22 @@ void board_init(void) { //--------------------------------------------------------------------+ void board_led_write(bool state) { - GPIO_PinState pin_state = (GPIO_PinState) (state ? LED_STATE_ON : (1 - LED_STATE_ON)); - HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state); +#ifdef PINID_LED + board_pindef_t* pindef = &board_pindef[PINID_LED]; + GPIO_PinState pin_state = state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, pin_state); +#else + (void) state; +#endif } uint32_t board_button_read(void) { - return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN); +#ifdef PINID_BUTTON + board_pindef_t* pindef = &board_pindef[PINID_BUTTON]; + return pindef->active_state == HAL_GPIO_ReadPin(pindef->port, pindef->pin_init.Pin); +#else + return 0; +#endif } size_t board_get_unique_id(uint8_t id[], size_t max_len) { diff --git a/hw/bsp/stm32f4/family.cmake b/hw/bsp/stm32f4/family.cmake index a2832763a..c0c9fe902 100644 --- a/hw/bsp/stm32f4/family.cmake +++ b/hw/bsp/stm32f4/family.cmake @@ -16,6 +16,28 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL set(FAMILY_MCUS STM32F4 CACHE INTERNAL "") +# ---------------------- +# Port & Speed Selection +# ---------------------- +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 0) +endif () +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) +endif () + +if (NOT DEFINED RHPORT_SPEED) + # Most F7 does not has built-in HS PHY + set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_FULL_SPEED) +endif () +if (NOT DEFINED RHPORT_DEVICE_SPEED) + list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED) +endif () +if (NOT DEFINED RHPORT_HOST_SPEED) + list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED) +endif () + +cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED) #------------------------------------ # BOARD_TARGET @@ -52,8 +74,12 @@ function(add_board_target BOARD_TARGET) ${ST_CMSIS}/Include ${ST_HAL_DRIVER}/Inc ) - # target_compile_options(${BOARD_TARGET} PUBLIC) - # target_compile_definitions(${BOARD_TARGET} PUBLIC) + target_compile_definitions(${BOARD_TARGET} PUBLIC + BOARD_TUD_RHPORT=${RHPORT_DEVICE} + BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} + BOARD_TUH_RHPORT=${RHPORT_HOST} + BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} + ) update_board(${BOARD_TARGET}) diff --git a/hw/bsp/stm32f4/family.mk b/hw/bsp/stm32f4/family.mk index 70c9cdf42..51ff43a60 100644 --- a/hw/bsp/stm32f4/family.mk +++ b/hw/bsp/stm32f4/family.mk @@ -8,14 +8,40 @@ ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m4 -PORT ?= 0 +# ---------------------- +# Port & Speed Selection +# ---------------------- +RHPORT_SPEED ?= OPT_MODE_FULL_SPEED OPT_MODE_FULL_SPEED +RHPORT_DEVICE ?= 0 +RHPORT_HOST ?= 0 + +# Determine RHPORT_DEVICE_SPEED if not defined +ifndef RHPORT_DEVICE_SPEED +ifeq ($(RHPORT_DEVICE), 0) + RHPORT_DEVICE_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_DEVICE_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif + +# Determine RHPORT_HOST_SPEED if not defined +ifndef RHPORT_HOST_SPEED +ifeq ($(RHPORT_HOST), 0) + RHPORT_HOST_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_HOST_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif # -------------- # Compiler Flags # -------------- CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_STM32F4 \ - -DBOARD_TUD_RHPORT=$(PORT) + -DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \ + -DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \ + -DBOARD_TUH_RHPORT=${RHPORT_HOST} \ + -DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \ # GCC Flags CFLAGS_GCC += \ diff --git a/hw/bsp/stm32f7/family.cmake b/hw/bsp/stm32f7/family.cmake index 0bf90a8bd..8ba744fed 100644 --- a/hw/bsp/stm32f7/family.cmake +++ b/hw/bsp/stm32f7/family.cmake @@ -16,6 +16,16 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL set(FAMILY_MCUS STM32F7 CACHE INTERNAL "") +# ---------------------- +# Port & Speed Selection +# ---------------------- +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 0) +endif () +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) +endif () + if (NOT DEFINED RHPORT_SPEED) # Most F7 does not has built-in HS PHY set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_FULL_SPEED) diff --git a/hw/bsp/stm32f7/family.mk b/hw/bsp/stm32f7/family.mk index 429170f86..abeea784c 100644 --- a/hw/bsp/stm32f7/family.mk +++ b/hw/bsp/stm32f7/family.mk @@ -8,8 +8,12 @@ ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m7-fpsp -# Default RHPORT_SPEED if not defined +# ---------------------- +# Port & Speed Selection +# ---------------------- RHPORT_SPEED ?= OPT_MODE_FULL_SPEED OPT_MODE_FULL_SPEED +RHPORT_DEVICE ?= 0 +RHPORT_HOST ?= 0 # Determine RHPORT_DEVICE_SPEED if not defined ifndef RHPORT_DEVICE_SPEED @@ -34,20 +38,23 @@ endif # -------------- CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_STM32F7 \ - -DBOARD_TUD_RHPORT=$(PORT) + -DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \ + -DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \ + -DBOARD_TUH_RHPORT=${RHPORT_HOST} \ + -DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \ -ifeq ($(PORT), 1) - ifeq ($(SPEED), high) - CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - $(info "Using OTG_HS in HighSpeed mode") - else - CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED - $(info "Using OTG_HS in FullSpeed mode") - endif -else - CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED - $(info "Using OTG_FS") -endif +#ifeq ($(PORT), 1) +# ifeq ($(SPEED), high) +# CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED +# $(info "Using OTG_HS in HighSpeed mode") +# else +# CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED +# $(info "Using OTG_HS in FullSpeed mode") +# endif +#else +# CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED +# $(info "Using OTG_FS") +#endif # GCC Flags CFLAGS_GCC += \ -- cgit v1.3.1 From 9920ebff4ac5c5d60ca228897713a1c154ab6b57 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 7 Nov 2024 15:04:19 +0700 Subject: update bsp for h7 to support host mode --- examples/dual/host_hid_to_device_cdc/only.txt | 2 + examples/dual/host_info_to_device_cdc/only.txt | 3 +- examples/host/bare_api/only.txt | 3 + examples/host/cdc_msc_hid/only.txt | 1 + examples/host/cdc_msc_hid/src/hid_app.c | 11 +- examples/host/cdc_msc_hid_freertos/only.txt | 3 + examples/host/device_info/only.txt | 3 + examples/host/hid_controller/only.txt | 3 + examples/host/msc_file_explorer/only.txt | 1 + hw/bsp/stm32f7/boards/stm32f723disco/board.mk | 3 - hw/bsp/stm32h7/boards/daisyseed/board.cmake | 3 - hw/bsp/stm32h7/boards/daisyseed/board.h | 51 +++-- hw/bsp/stm32h7/boards/daisyseed/board.mk | 10 +- hw/bsp/stm32h7/boards/stm32h723nucleo/board.cmake | 3 - hw/bsp/stm32h7/boards/stm32h723nucleo/board.h | 55 ++++-- hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk | 12 +- hw/bsp/stm32h7/boards/stm32h743eval/board.cmake | 20 +- hw/bsp/stm32h7/boards/stm32h743eval/board.h | 215 +++++++++------------ hw/bsp/stm32h7/boards/stm32h743eval/board.mk | 19 +- hw/bsp/stm32h7/boards/stm32h743nucleo/board.cmake | 3 - hw/bsp/stm32h7/boards/stm32h743nucleo/board.h | 61 ++++-- hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk | 12 +- hw/bsp/stm32h7/boards/stm32h745disco/board.cmake | 3 - hw/bsp/stm32h7/boards/stm32h745disco/board.h | 57 ++++-- hw/bsp/stm32h7/boards/stm32h745disco/board.mk | 7 +- hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake | 3 - hw/bsp/stm32h7/boards/stm32h750_weact/board.h | 49 +++-- hw/bsp/stm32h7/boards/stm32h750_weact/board.mk | 11 +- hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake | 3 - hw/bsp/stm32h7/boards/stm32h750bdk/board.h | 62 ++++-- hw/bsp/stm32h7/boards/stm32h750bdk/board.mk | 11 +- .../stm32h7/boards/waveshare_openh743i/board.cmake | 13 +- hw/bsp/stm32h7/boards/waveshare_openh743i/board.h | 60 ++++-- hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk | 16 +- hw/bsp/stm32h7/family.c | 93 +++++---- hw/bsp/stm32h7/family.cmake | 34 +++- hw/bsp/stm32h7/family.mk | 82 +++++--- 37 files changed, 571 insertions(+), 430 deletions(-) (limited to 'hw') diff --git a/examples/dual/host_hid_to_device_cdc/only.txt b/examples/dual/host_hid_to_device_cdc/only.txt index 149ece856..3f40b4e7c 100644 --- a/examples/dual/host_hid_to_device_cdc/only.txt +++ b/examples/dual/host_hid_to_device_cdc/only.txt @@ -4,4 +4,6 @@ board:mcb1800 mcu:RP2040 mcu:ra6m5 mcu:MAX3421 +mcu:STM32F4 +mcu:STM32F7 mcu:STM32H7 diff --git a/examples/dual/host_info_to_device_cdc/only.txt b/examples/dual/host_info_to_device_cdc/only.txt index f9db1db85..3f40b4e7c 100644 --- a/examples/dual/host_info_to_device_cdc/only.txt +++ b/examples/dual/host_info_to_device_cdc/only.txt @@ -4,5 +4,6 @@ board:mcb1800 mcu:RP2040 mcu:ra6m5 mcu:MAX3421 -mcu:STM32H7 +mcu:STM32F4 mcu:STM32F7 +mcu:STM32H7 diff --git a/examples/host/bare_api/only.txt b/examples/host/bare_api/only.txt index fee10f9e2..95f9f1d82 100644 --- a/examples/host/bare_api/only.txt +++ b/examples/host/bare_api/only.txt @@ -12,3 +12,6 @@ mcu:MSP432E4 mcu:RX65X mcu:RAXXX mcu:MAX3421 +mcu:STM32F4 +mcu:STM32F7 +mcu:STM32H7 diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt index 2c88734d3..95f9f1d82 100644 --- a/examples/host/cdc_msc_hid/only.txt +++ b/examples/host/cdc_msc_hid/only.txt @@ -14,3 +14,4 @@ mcu:RAXXX mcu:MAX3421 mcu:STM32F4 mcu:STM32F7 +mcu:STM32H7 diff --git a/examples/host/cdc_msc_hid/src/hid_app.c b/examples/host/cdc_msc_hid/src/hid_app.c index 6bb3a2072..3f98ec89f 100644 --- a/examples/host/cdc_msc_hid/src/hid_app.c +++ b/examples/host/cdc_msc_hid/src/hid_app.c @@ -130,13 +130,12 @@ void tuh_hid_report_received_cb(uint8_t dev_addr, uint8_t instance, uint8_t cons //--------------------------------------------------------------------+ // look up new key in previous keys -static inline bool find_key_in_report(hid_keyboard_report_t const *report, uint8_t keycode) -{ - for(uint8_t i=0; i<6; i++) - { - if (report->keycode[i] == keycode) return true; +static inline bool find_key_in_report(hid_keyboard_report_t const* report, uint8_t keycode) { + for (uint8_t i = 0; i < 6; i++) { + if (report->keycode[i] == keycode) { + return true; + } } - return false; } diff --git a/examples/host/cdc_msc_hid_freertos/only.txt b/examples/host/cdc_msc_hid_freertos/only.txt index 1e0e60075..472745301 100644 --- a/examples/host/cdc_msc_hid_freertos/only.txt +++ b/examples/host/cdc_msc_hid_freertos/only.txt @@ -9,3 +9,6 @@ mcu:MIMXRT11XX mcu:MSP432E4 mcu:RX65X mcu:MAX3421 +mcu:STM32F4 +mcu:STM32F7 +mcu:STM32H7 diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt index aed9583b4..de21a54bd 100644 --- a/examples/host/device_info/only.txt +++ b/examples/host/device_info/only.txt @@ -14,3 +14,6 @@ mcu:RX65X mcu:RAXXX mcu:STM32H7 mcu:STM32F7 +mcu:STM32F4 +mcu:STM32F7 +mcu:STM32H7 diff --git a/examples/host/hid_controller/only.txt b/examples/host/hid_controller/only.txt index fee10f9e2..95f9f1d82 100644 --- a/examples/host/hid_controller/only.txt +++ b/examples/host/hid_controller/only.txt @@ -12,3 +12,6 @@ mcu:MSP432E4 mcu:RX65X mcu:RAXXX mcu:MAX3421 +mcu:STM32F4 +mcu:STM32F7 +mcu:STM32H7 diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt index 2c88734d3..95f9f1d82 100644 --- a/examples/host/msc_file_explorer/only.txt +++ b/examples/host/msc_file_explorer/only.txt @@ -14,3 +14,4 @@ mcu:RAXXX mcu:MAX3421 mcu:STM32F4 mcu:STM32F7 +mcu:STM32H7 diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk index c731323ca..eb6799eb0 100644 --- a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk +++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk @@ -4,9 +4,6 @@ RHPORT_SPEED = OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED RHPORT_DEVICE ?= 1 RHPORT_HOST ?= 0 -PORT ?= 1 -SPEED ?= high - CFLAGS += \ -DSTM32F723xx \ -DHSE_VALUE=25000000 \ diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.cmake b/hw/bsp/stm32h7/boards/daisyseed/board.cmake index 4811c97e8..ff22b3e22 100644 --- a/hw/bsp/stm32h7/boards/daisyseed/board.cmake +++ b/hw/bsp/stm32h7/boards/daisyseed/board.cmake @@ -8,8 +8,5 @@ function(update_board TARGET) STM32H750xx HSE_VALUE=16000000 CORE_CM7 - # default to PORT 0 - BOARD_TUD_RHPORT=0 - BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED ) endfunction() diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.h b/hw/bsp/stm32h7/boards/daisyseed/board.h index 532e3bfd5..2d681d640 100644 --- a/hw/bsp/stm32h7/boards/daisyseed/board.h +++ b/hw/bsp/stm32h7/boards/daisyseed/board.h @@ -31,32 +31,46 @@ extern "C" { #endif -#define LED_PORT GPIOC -#define LED_PIN GPIO_PIN_7 -#define LED_STATE_ON 1 - -// Blue push-button -#define BUTTON_PORT GPIOC -#define BUTTON_PIN GPIO_PIN_13 -#define BUTTON_STATE_ACTIVE 1 - // UART #define UART_DEV USART3 #define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE -#define UART_GPIO_PORT GPIOB -#define UART_GPIO_AF GPIO_AF7_USART3 -#define UART_TX_PIN GPIO_PIN_10 -#define UART_RX_PIN GPIO_PIN_11 // VBUS Sense detection #define OTG_FS_VBUS_SENSE 1 #define OTG_HS_VBUS_SENSE 0 +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_7, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // Button + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + } +}; + //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ -static inline void SystemClock_Config(void) -{ +static inline void SystemClock_Config(void) { RCC_ClkInitTypeDef RCC_ClkInitStruct = { 0 }; RCC_OscInitTypeDef RCC_OscInitStruct = { 0 }; RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = { 0 }; @@ -128,11 +142,14 @@ static inline void SystemClock_Config(void) HAL_EnableCompensationCell(); } -static inline void board_init2(void) -{ +static inline void board_init2(void) { // For this board does nothing } +void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.mk b/hw/bsp/stm32h7/boards/daisyseed/board.mk index da2eb4433..bb254cfc2 100644 --- a/hw/bsp/stm32h7/boards/daisyseed/board.mk +++ b/hw/bsp/stm32h7/boards/daisyseed/board.mk @@ -1,16 +1,8 @@ +MCU_VARIANT = stm32h750xx CFLAGS += -DSTM32H750xx -DCORE_CM7 -DHSE_VALUE=16000000 -# Default is FulSpeed port -PORT ?= 0 - -# GCC -SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h750xx.s LD_FILE_GCC = $(BOARD_PATH)/stm32h750ibkx_flash.ld -# IAR -SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h750xx.s -LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h750xx_flash.icf - # For flash-jlink target JLINK_DEVICE = stm32h750ibk6_m7 diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.cmake b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.cmake index b7d133dfa..a6f0a5c45 100644 --- a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.cmake +++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.cmake @@ -7,8 +7,5 @@ function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32H723xx HSE_VALUE=8000000 - # default to PORT 0 - BOARD_TUD_RHPORT=0 - BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED ) endfunction() diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h index b3da1348f..c5257901d 100644 --- a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h +++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h @@ -31,20 +31,8 @@ extern "C" { #endif -#define LED_PORT GPIOB -#define LED_PIN GPIO_PIN_0 -#define LED_STATE_ON 1 - -#define BUTTON_PORT GPIOC -#define BUTTON_PIN GPIO_PIN_13 -#define BUTTON_STATE_ACTIVE 1 - #define UART_DEV USART3 #define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE -#define UART_GPIO_PORT GPIOD -#define UART_GPIO_AF GPIO_AF7_USART3 -#define UART_TX_PIN GPIO_PIN_8 -#define UART_RX_PIN GPIO_PIN_9 // VBUS Sense detection #define OTG_FS_VBUS_SENSE 1 @@ -59,6 +47,40 @@ #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG1_HS #define USB_OTG_FS USB_OTG_HS +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +#define PINID_VBUS0_EN 4 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // Button + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // VBUS0 EN + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 0 + } +}; + //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ @@ -118,11 +140,16 @@ static inline void SystemClock_Config(void) HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct); } -static inline void board_init2(void) -{ +static inline void board_init2(void) { // For this board does nothing } +void board_vbus_set(uint8_t rhport, bool state) { + if (rhport == 0) { + board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN]; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET); + } +} #ifdef __cplusplus } diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk index 57a316f41..c1a98a025 100644 --- a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk +++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.mk @@ -1,15 +1,7 @@ +MCU_VARIANT = stm32h723xx CFLAGS += -DSTM32H723xx -DHSE_VALUE=8000000 -# Default is FulSpeed port -PORT ?= 0 - -# GCC -SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h723xx.s -LD_FILE_GCC = $(FAMILY_PATH)/linker/stm32h723xx_flash.ld - -# IAR -SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h723xx.s -LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h723xx_flash.icf +LD_FILE_GCC = $(FAMILY_PATH)/linker/${MCU_VARIANT}_flash.ld # For flash-jlink target JLINK_DEVICE = stm32h723zg diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake index 2ff874690..6926b905a 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake @@ -4,12 +4,26 @@ set(JLINK_OPTION "-USB jtrace") set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld) +set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) + +# device default to PORT 1 High Speed +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) +endif() + function(update_board TARGET) + target_sources(${TARGET} PUBLIC + ${ST_MFXSTM32L152}/mfxstm32l152.c + ${ST_MFXSTM32L152}/mfxstm32l152_reg.c + ) + target_include_directories(${TARGET} PUBLIC + ${ST_MFXSTM32L152} + ) target_compile_definitions(${TARGET} PUBLIC STM32H743xx HSE_VALUE=25000000 - # default to PORT 1 High Speed - BOARD_TUD_RHPORT=1 - BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED ) endfunction() diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h index 2e2d4aebd..fa9721be3 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h @@ -33,22 +33,9 @@ #include "mfxstm32l152.h" -#define LED_PORT GPIOA -#define LED_PIN GPIO_PIN_4 -#define LED_STATE_ON 1 - -// Tamper push-button -#define BUTTON_PORT GPIOC -#define BUTTON_PIN GPIO_PIN_13 -#define BUTTON_STATE_ACTIVE 0 - // Need to change jumper setting J7 and J8 from RS-232 to STLink #define UART_DEV USART1 #define UART_CLK_EN __HAL_RCC_USART1_CLK_ENABLE -#define UART_GPIO_PORT GPIOB -#define UART_GPIO_AF GPIO_AF4_USART1 -#define UART_TX_PIN GPIO_PIN_14 -#define UART_RX_PIN GPIO_PIN_15 // VBUS Sense detection #define OTG_FS_VBUS_SENSE 1 @@ -60,13 +47,43 @@ {GPIOB, GPIO_PIN_5 }, {GPIOB, GPIO_PIN_10}, {GPIOB, GPIO_PIN_11}, {GPIOB, GPIO_PIN_12}, \ {GPIOB, GPIO_PIN_13}, {GPIOC, GPIO_PIN_0 }, {GPIOH, GPIO_PIN_4 }, {GPIOI, GPIO_PIN_11} -/* Definition for I2C1 Pins */ -#define BUS_I2C1_SCL_PIN GPIO_PIN_6 -#define BUS_I2C1_SDA_PIN GPIO_PIN_7 -#define BUS_I2C1_SCL_GPIO_PORT GPIOB -#define BUS_I2C1_SDA_GPIO_PORT GPIOB -#define BUS_I2C1_SCL_AF GPIO_AF4_I2C1 -#define BUS_I2C1_SDA_AF GPIO_AF4_I2C1 +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_4, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // Button + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 0 + }, + { // UART TX + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_14, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF4_USART1 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_15, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF4_USART1 }, + .active_state = 0 + }, + { // I2C SCL for MFX VBUS + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_6, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF4_I2C1 }, + .active_state = 0 + }, + { // I2C SDA for MFX VBUS + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_7, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF4_I2C1 }, + .active_state = 1 + }, +}; //--------------------------------------------------------------------+ // RCC Clock @@ -145,141 +162,91 @@ static inline void SystemClock_Config(void) { //--------------------------------------------------------------------+ // MFX //--------------------------------------------------------------------+ -I2C_HandleTypeDef hbus_i2c1 = { .Instance = I2C1}; +static I2C_HandleTypeDef i2c_handle = { + .Instance = I2C1, + .Init = { + .Timing = 0x10C0ECFF, + .OwnAddress1 = 0, + .AddressingMode = I2C_ADDRESSINGMODE_7BIT, + .DualAddressMode = I2C_DUALADDRESS_DISABLE, + .OwnAddress2 = 0, + .OwnAddress2Masks = I2C_OA2_NOMASK, + .GeneralCallMode = I2C_GENERALCALL_DISABLE, + .NoStretchMode = I2C_NOSTRETCH_DISABLE, + } +}; static MFXSTM32L152_Object_t mfx_obj = { 0 }; -static MFXSTM32L152_IO_Mode_t* mfx_io_drv = NULL; - -HAL_StatusTypeDef MX_I2C1_Init(I2C_HandleTypeDef* hI2c, uint32_t timing) { - hI2c->Init.Timing = timing; - hI2c->Init.OwnAddress1 = 0; - hI2c->Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - hI2c->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; - hI2c->Init.OwnAddress2 = 0; - hI2c->Init.OwnAddress2Masks = I2C_OA2_NOMASK; - hI2c->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; - hI2c->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; - - if (HAL_I2C_Init(hI2c) != HAL_OK) { +static MFXSTM32L152_IO_Mode_t* mfx_io = NULL; +static uint32_t mfx_vbus_pin[2] = { MFXSTM32L152_GPIO_PIN_7, MFXSTM32L152_GPIO_PIN_9 }; + +int32_t board_i2c_init(void) { + __HAL_RCC_I2C1_CLK_ENABLE(); + __HAL_RCC_I2C1_FORCE_RESET(); + __HAL_RCC_I2C1_RELEASE_RESET(); + if (HAL_I2C_Init(&i2c_handle) != HAL_OK) { return HAL_ERROR; } - if (HAL_I2CEx_ConfigAnalogFilter(hI2c, I2C_ANALOGFILTER_ENABLE) != HAL_OK) { + if (HAL_I2CEx_ConfigAnalogFilter(&i2c_handle, I2C_ANALOGFILTER_ENABLE) != HAL_OK) { return HAL_ERROR; } - if (HAL_I2CEx_ConfigDigitalFilter(hI2c, 0) != HAL_OK) { + if (HAL_I2CEx_ConfigDigitalFilter(&i2c_handle, 0) != HAL_OK) { return HAL_ERROR; } - - return HAL_OK; -} - -int32_t BSP_I2C1_Init(void) { - // Init I2C - GPIO_InitTypeDef gpio_init_structure; - gpio_init_structure.Pin = BUS_I2C1_SCL_PIN; - gpio_init_structure.Mode = GPIO_MODE_AF_OD; - gpio_init_structure.Pull = GPIO_NOPULL; - gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH; - gpio_init_structure.Alternate = BUS_I2C1_SCL_AF; - HAL_GPIO_Init(BUS_I2C1_SCL_GPIO_PORT, &gpio_init_structure); - - gpio_init_structure.Pin = BUS_I2C1_SDA_PIN; - gpio_init_structure.Mode = GPIO_MODE_AF_OD; - gpio_init_structure.Pull = GPIO_NOPULL; - gpio_init_structure.Speed = GPIO_SPEED_FREQ_HIGH; - gpio_init_structure.Alternate = BUS_I2C1_SDA_AF; - HAL_GPIO_Init(BUS_I2C1_SDA_GPIO_PORT, &gpio_init_structure); - - __HAL_RCC_I2C1_CLK_ENABLE(); - __HAL_RCC_I2C1_FORCE_RESET(); - __HAL_RCC_I2C1_RELEASE_RESET(); - - if (MX_I2C1_Init(&hbus_i2c1, /*0x10C0ECFF*/ 1890596921) != HAL_OK) { - return -1; - } - return 0; } -int32_t BSP_I2C1_DeInit(void) { +int32_t board_i2c_deinit(void) { return 0; } -int32_t BSP_I2C1_ReadReg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { - if (HAL_OK != HAL_I2C_Mem_Read(&hbus_i2c1, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)) { - return -1; - } +int32_t i2c_readreg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { + TU_ASSERT (HAL_OK == HAL_I2C_Mem_Read(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)); return 0; } -int32_t BSP_I2C1_WriteReg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { - if(HAL_OK != HAL_I2C_Mem_Write(&hbus_i2c1, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)) { - return -1; - } +int32_t i2c_writereg(uint16_t DevAddr, uint16_t Reg, uint8_t *pData, uint16_t Length) { + TU_ASSERT(HAL_OK == HAL_I2C_Mem_Write(&i2c_handle, DevAddr, Reg, I2C_MEMADD_SIZE_8BIT, pData, Length, 10000)); return 0; } - static inline void board_init2(void) { - // Init MFX IO expanding for vbus drive - BSP_I2C1_Init(); - - /* Configure the audio driver */ - MFXSTM32L152_IO_t IOCtx; - IOCtx.Init = BSP_I2C1_DeInit; - IOCtx.DeInit = BSP_I2C1_DeInit; - IOCtx.ReadReg = BSP_I2C1_ReadReg; - IOCtx.WriteReg = BSP_I2C1_WriteReg; - IOCtx.GetTick = (MFXSTM32L152_GetTick_Func) HAL_GetTick; - - uint8_t i2c_address[] = {0x84, 0x86}; + // IO control via MFX + MFXSTM32L152_IO_t io_ctx; + io_ctx.Init = board_i2c_init; + io_ctx.DeInit = board_i2c_deinit; + io_ctx.ReadReg = i2c_readreg; + io_ctx.WriteReg = i2c_writereg; + io_ctx.GetTick = (MFXSTM32L152_GetTick_Func) HAL_GetTick; + + uint16_t i2c_addr[] = { 0x84, 0x86 }; for(uint8_t i = 0U; i < 2U; i++) { uint32_t mfx_id; - IOCtx.Address = (uint16_t)i2c_address[i]; - if (MFXSTM32L152_RegisterBusIO(&mfx_obj, &IOCtx) != MFXSTM32L152_OK) { - return; - } - if (MFXSTM32L152_ReadID(&mfx_obj, &mfx_id) != MFXSTM32L152_OK) { - return; - } - + io_ctx.Address = i2c_addr[i]; + TU_ASSERT(MFXSTM32L152_RegisterBusIO(&mfx_obj, &io_ctx) == MFXSTM32L152_OK, ); + TU_ASSERT(MFXSTM32L152_ReadID(&mfx_obj, &mfx_id) == MFXSTM32L152_OK, ); if ((mfx_id == MFXSTM32L152_ID) || (mfx_id == MFXSTM32L152_ID_2)) { - if (MFXSTM32L152_Init(&mfx_obj) != MFXSTM32L152_OK) { - return; - } + TU_ASSERT(MFXSTM32L152_Init(&mfx_obj) == MFXSTM32L152_OK, ); break; } } - mfx_io_drv = &MFXSTM32L152_IO_Driver; + mfx_io = &MFXSTM32L152_IO_Driver; + mfx_io->IO_Start(&mfx_obj, MFXSTM32L152_GPIO_PINS_ALL); - static MFXSTM32L152_IO_Init_t io_init = { 0 }; - mfx_io_drv->Init(&mfx_obj, &io_init); - - io_init.Pin = MFXSTM32L152_GPIO_PIN_7; - io_init.Mode = MFXSTM32L152_GPIO_MODE_OUTPUT_PP; - io_init.Pull = MFXSTM32L152_GPIO_PULLUP; - mfx_io_drv->Init(&mfx_obj, &io_init); // VBUS[0] - - io_init.Pin = MFXSTM32L152_GPIO_PIN_9; - mfx_io_drv->Init(&mfx_obj, &io_init); // VBUS[1] - -#if 1 // write then read IO7 but it does not seems to change value - int32_t pin_value; - pin_value = mfx_io_drv->IO_ReadPin(&mfx_obj, MFXSTM32L152_GPIO_PIN_7); - TU_LOG1_INT(pin_value); - - mfx_io_drv->IO_WritePin(&mfx_obj, MFXSTM32L152_GPIO_PIN_7, 1); - - pin_value = mfx_io_drv->IO_ReadPin(&mfx_obj, MFXSTM32L152_GPIO_PIN_7); - TU_LOG1_INT(pin_value); -#endif + for(uint32_t i=0; i<2; i++) { + MFXSTM32L152_IO_Init_t io_init = { + .Pin = mfx_vbus_pin[i], + .Mode = MFXSTM32L152_GPIO_MODE_OUTPUT_PP, + .Pull = MFXSTM32L152_GPIO_PULLUP, + }; + mfx_io->Init(&mfx_obj, &io_init); + } } -// vbus drive +// VBUS1 is actually controlled by USB3320C PHY (using dwc2 drivebus signal) void board_vbus_set(uint8_t rhport, bool state) { - if ( mfx_io_drv ) { - uint32_t io_pin = (_rhport) ? MFXSTM32L152_GPIO_PIN_9 : MFXSTM32L152_GPIO_PIN_7; - mfx_io_drv->IO_WritePin(&Io_CompObj, io_pin, _on); + if (mfx_io) { + mfx_io->IO_WritePin(&mfx_obj, mfx_vbus_pin[rhport], state); } } diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.mk b/hw/bsp/stm32h7/boards/stm32h743eval/board.mk index 36882a0e5..67b403932 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.mk +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.mk @@ -1,16 +1,17 @@ +MCU_VARIANT = stm32h743xx CFLAGS += -DSTM32H743xx -DHSE_VALUE=25000000 -# Default is Highspeed port -PORT ?= 1 -SPEED ?= high +RHPORT_SPEED = OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 0 -# GCC -SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s -LD_FILE_GCC = $(FAMILY_PATH)/linker/stm32h743xx_flash.ld +LD_FILE_GCC = $(FAMILY_PATH)/linker/${MCU_VARIANT}_flash.ld -# IAR -SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h743xx.s -LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h743xx_flash.icf +SRC_C += \ + ${ST_MFXSTM32L152}/mfxstm32l152.c \ + ${ST_MFXSTM32L152}/mfxstm32l152_reg.c \ + +INC += $(TOP)/${ST_MFXSTM32L152} # For flash-jlink target JLINK_DEVICE = stm32h743xi diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.cmake b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.cmake index f1532a95f..021799775 100644 --- a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.cmake +++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.cmake @@ -7,8 +7,5 @@ function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32H743xx HSE_VALUE=8000000 - # default to PORT 0 - BOARD_TUD_RHPORT=0 - BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED ) endfunction() diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h index 513ce2bb7..0606f395a 100644 --- a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h +++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h @@ -31,25 +31,47 @@ extern "C" { #endif -#define LED_PORT GPIOB -#define LED_PIN GPIO_PIN_0 -#define LED_STATE_ON 1 - -#define BUTTON_PORT GPIOC -#define BUTTON_PIN GPIO_PIN_13 -#define BUTTON_STATE_ACTIVE 1 - #define UART_DEV USART3 #define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE -#define UART_GPIO_PORT GPIOD -#define UART_GPIO_AF GPIO_AF7_USART3 -#define UART_TX_PIN GPIO_PIN_8 -#define UART_RX_PIN GPIO_PIN_9 // VBUS Sense detection #define OTG_FS_VBUS_SENSE 1 #define OTG_HS_VBUS_SENSE 0 +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +#define PINID_VBUS0_EN 4 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // Button + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // VBUS0 EN + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_OUTPUT_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 0 + } +}; + //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ @@ -100,8 +122,7 @@ static inline void SystemClock_Config(void) { RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) - { + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) { Error_Handler(); } @@ -116,17 +137,21 @@ static inline void SystemClock_Config(void) { PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_3; PeriphClkInitStruct.PLL3.PLL3FRACN = 0; PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) - { + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { Error_Handler(); } } -static inline void board_init2(void) -{ +static inline void board_init2(void) { // For this board does nothing } +void board_vbus_set(uint8_t rhport, bool state) { + if (rhport == 0) { + board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN]; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET); + } +} #ifdef __cplusplus } diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk index f641b77aa..d904de6d2 100644 --- a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk +++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.mk @@ -1,15 +1,7 @@ +MCU_VARIANT = stm32h743xx CFLAGS += -DSTM32H743xx -DHSE_VALUE=8000000 -# Default is FulSpeed port -PORT ?= 0 - -# GCC -SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s -LD_FILE_GCC = $(FAMILY_PATH)/linker/stm32h743xx_flash.ld - -# IAR -SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h743xx.s -LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h743xx_flash.icf +LD_FILE_GCC = $(FAMILY_PATH)/linker/${MCU_VARIANT}_flash.ld # For flash-jlink target JLINK_DEVICE = stm32h743zi diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake b/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake index f1313d54e..39a9d5798 100644 --- a/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake +++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.cmake @@ -9,8 +9,5 @@ function(update_board TARGET) STM32H745xx HSE_VALUE=25000000 CORE_CM7 - # default to PORT 0 - BOARD_TUD_RHPORT=0 - BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED ) endfunction() diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.h b/hw/bsp/stm32h7/boards/stm32h745disco/board.h index c0f85ddbe..b9d9cdea4 100644 --- a/hw/bsp/stm32h7/boards/stm32h745disco/board.h +++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.h @@ -31,27 +31,48 @@ extern "C" { #endif -#define LED_PORT GPIOJ -#define LED_PIN GPIO_PIN_2 -#define LED_STATE_ON 1 - -// Blue push-button -#define BUTTON_PORT GPIOC -#define BUTTON_PIN GPIO_PIN_13 -#define BUTTON_STATE_ACTIVE 1 - // UART #define UART_DEV USART3 #define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE -#define UART_GPIO_PORT GPIOB -#define UART_GPIO_AF GPIO_AF7_USART3 -#define UART_TX_PIN GPIO_PIN_10 -#define UART_RX_PIN GPIO_PIN_11 // VBUS Sense detection #define OTG_FS_VBUS_SENSE 1 #define OTG_HS_VBUS_SENSE 0 +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +#define PINID_VBUS0_EN 4 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOJ, + .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // Button + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // VBUS0 EN + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_5, .Mode = GPIO_MODE_OUTPUT_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + } +}; + //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ @@ -127,11 +148,17 @@ static inline void SystemClock_Config(void) HAL_EnableCompensationCell(); } -static inline void board_init2(void) -{ +static inline void board_init2(void) { // For this board does nothing } +void board_vbus_set(uint8_t rhport, bool state) { + if (rhport == 0) { + board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN]; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET); + } +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.mk b/hw/bsp/stm32h7/boards/stm32h745disco/board.mk index 9c3615f05..588620ce2 100644 --- a/hw/bsp/stm32h7/boards/stm32h745disco/board.mk +++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.mk @@ -1,17 +1,12 @@ # STM32H745I-DISCO uses OTG_FS # FIXME: Reset enumerates, un/replug USB plug does not enumerate - +MCU_VARIANT = stm32h745xx CFLAGS += -DSTM32H745xx -DCORE_CM7 -DHSE_VALUE=25000000 # Default is FulSpeed port PORT ?= 0 -# GCC -SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h745xx.s LD_FILE_GCC = $(ST_CMSIS)/Source/Templates/gcc/linker/stm32h745xx_flash_CM7.ld - -# IAR -SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h745xx.s LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h745xx_flash_CM7.icf # For flash-jlink target diff --git a/hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake b/hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake index 6303ca462..6eab26c07 100644 --- a/hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake +++ b/hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake @@ -9,8 +9,5 @@ function(update_board TARGET) STM32H750xx HSE_VALUE=25000000 CORE_CM7 - # default to PORT 0 - BOARD_TUD_RHPORT=0 - BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED ) endfunction() diff --git a/hw/bsp/stm32h7/boards/stm32h750_weact/board.h b/hw/bsp/stm32h7/boards/stm32h750_weact/board.h index 5beab20ce..f1c363082 100644 --- a/hw/bsp/stm32h7/boards/stm32h750_weact/board.h +++ b/hw/bsp/stm32h7/boards/stm32h750_weact/board.h @@ -31,27 +31,42 @@ extern "C" { #endif -#define LED_PORT GPIOE -#define LED_PIN GPIO_PIN_3 -#define LED_STATE_ON 1 - -// Blue push-button -#define BUTTON_PORT GPIOC -#define BUTTON_PIN GPIO_PIN_13 -#define BUTTON_STATE_ACTIVE 1 - // UART -//#define UART_DEV USART3 -//#define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE -//#define UART_GPIO_PORT GPIOB -//#define UART_GPIO_AF GPIO_AF7_USART3 -//#define UART_TX_PIN GPIO_PIN_10 -//#define UART_RX_PIN GPIO_PIN_11 +#define UART_DEV USART3 +#define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE // VBUS Sense detection #define OTG_FS_VBUS_SENSE 1 #define OTG_HS_VBUS_SENSE 0 +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOE, + .pin_init = { .Pin = GPIO_PIN_3, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // Button + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + } +}; + //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ @@ -125,6 +140,10 @@ static inline void board_init2(void) { // For this board does nothing } +void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/stm32h7/boards/stm32h750_weact/board.mk b/hw/bsp/stm32h7/boards/stm32h750_weact/board.mk index a50172cb0..988fed804 100644 --- a/hw/bsp/stm32h7/boards/stm32h750_weact/board.mk +++ b/hw/bsp/stm32h7/boards/stm32h750_weact/board.mk @@ -1,19 +1,10 @@ # STM32H745I-DISCO uses OTG_FS # FIXME: Reset enumerates, un/replug USB plug does not enumerate - +MCU_VARIANT = stm32h750xx CFLAGS += -DSTM32H750xx -DCORE_CM7 -DHSE_VALUE=25000000 -# Default is FulSpeed port -PORT ?= 0 - -# GCC -SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h750xx.s LD_FILE_GCC = $(BOARD_PATH)/stm32h750xx_flash_CM7.ld -# IAR -SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h750xx.s -LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h750xx_flash.icf - # For flash-jlink target JLINK_DEVICE = stm32h750vb diff --git a/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake b/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake index e87be8255..72a139ab6 100644 --- a/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake +++ b/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake @@ -9,8 +9,5 @@ function(update_board TARGET) STM32H750xx HSE_VALUE=25000000 CORE_CM7 - # default to PORT 0 - BOARD_TUD_RHPORT=0 - BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED ) endfunction() diff --git a/hw/bsp/stm32h7/boards/stm32h750bdk/board.h b/hw/bsp/stm32h7/boards/stm32h750bdk/board.h index b0b063cda..2895f0973 100644 --- a/hw/bsp/stm32h7/boards/stm32h750bdk/board.h +++ b/hw/bsp/stm32h7/boards/stm32h750bdk/board.h @@ -31,33 +31,47 @@ extern "C" { #endif -#define LED_PORT GPIOJ -#define LED_PIN GPIO_PIN_2 -#define LED_STATE_ON 1 - -// Blue push-button -#define BUTTON_PORT GPIOC -#define BUTTON_PIN GPIO_PIN_13 -#define BUTTON_STATE_ACTIVE 1 - // UART #define UART_DEV USART3 #define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE -#define UART_GPIO_PORT GPIOB -#define UART_GPIO_AF GPIO_AF7_USART3 -#define UART_TX_PIN GPIO_PIN_10 -#define UART_RX_PIN GPIO_PIN_11 // VBUS Sense detection #define OTG_FS_VBUS_SENSE 1 #define OTG_HS_VBUS_SENSE 0 -// USB HS External PHY Pin: CLK, STP, DIR, NXT, D0-D7 -#define ULPI_PINS \ - {GPIOA, GPIO_PIN_3 }, {GPIOA, GPIO_PIN_5 }, {GPIOB, GPIO_PIN_0 }, {GPIOB, GPIO_PIN_1 }, \ - {GPIOB, GPIO_PIN_5 }, {GPIOB, GPIO_PIN_10}, {GPIOB, GPIO_PIN_11}, {GPIOB, GPIO_PIN_12}, \ - {GPIOB, GPIO_PIN_13}, {GPIOC, GPIO_PIN_0 }, {GPIOH, GPIO_PIN_4 }, {GPIOI, GPIO_PIN_11} - +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 +#define PINID_VBUS0_EN 4 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOJ, + .pin_init = { .Pin = GPIO_PIN_2, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // Button + .port = GPIOC, + .pin_init = { .Pin = GPIO_PIN_13, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_10, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_11, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // VBUS0 EN + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_5, .Mode = GPIO_MODE_OUTPUT_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + } +}; //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ @@ -132,11 +146,17 @@ static inline void SystemClock_Config(void) HAL_EnableCompensationCell(); } -static inline void board_init2(void) -{ +static inline void board_init2(void) { // For this board does nothing } +void board_vbus_set(uint8_t rhport, bool state) { + if (rhport == 0) { + board_pindef_t* pindef = &board_pindef[PINID_VBUS0_EN]; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET); + } +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk b/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk index 923c90753..6eb3eb498 100644 --- a/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk +++ b/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk @@ -1,19 +1,10 @@ # STM32H745I-DISCO uses OTG_FS # FIXME: Reset enumerates, un/replug USB plug does not enumerate - +MCU_VARIANT = stm32h750xx CFLAGS += -DSTM32H750xx -DCORE_CM7 -DHSE_VALUE=25000000 -# Default is FulSpeed port -PORT ?= 0 - -# GCC -SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h750xx.s LD_FILE_GCC = $(BOARD_PATH)/stm32h750xx_flash_CM7.ld -# IAR -SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h750xx.s -LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h750xx_flash.icf - # For flash-jlink target JLINK_DEVICE = stm32h750xb diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.cmake b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.cmake index 83c8d4833..3aaa81612 100644 --- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.cmake +++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.cmake @@ -3,14 +3,21 @@ set(JLINK_DEVICE stm32h743xi) set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld) +set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) + +# device default to PORT 1 High Speed +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) +endif() + function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32H743xx HSE_VALUE=8000000 HAL_TIM_MODULE_ENABLED - # default to PORT 1 High Speed - BOARD_TUD_RHPORT=1 - BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED ) target_sources(${TARGET} PUBLIC ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_tim.c diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h index 46efca6fb..625c6a137 100644 --- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h +++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h @@ -70,22 +70,9 @@ extern "C" { #endif -#define LED_PORT GPIOB -#define LED_PIN GPIO_PIN_6 -#define LED_STATE_ON 1 - -// Tamper push-button -#define BUTTON_PORT GPIOA -#define BUTTON_PIN GPIO_PIN_0 -#define BUTTON_STATE_ACTIVE 1 - // Need to change jumper setting J7 and J8 from RS-232 to STLink #define UART_DEV USART3 #define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE -#define UART_GPIO_PORT GPIOD -#define UART_GPIO_AF GPIO_AF7_USART3 -#define UART_TX_PIN GPIO_PIN_8 -#define UART_RX_PIN GPIO_PIN_9 // VBUS Sense detection #define OTG_FS_VBUS_SENSE 1 @@ -101,6 +88,45 @@ #define ULPI_RST_PORT GPIOD #define ULPI_RST_PIN GPIO_PIN_14 +#define PINID_LED 0 +#define PINID_BUTTON 1 +#define PINID_UART_TX 2 +#define PINID_UART_RX 3 + +static board_pindef_t board_pindef[] = { + { // LED + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_6, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // Button + .port = GPIOA, + .pin_init = { .Pin = GPIO_PIN_0, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 1 + }, + { // UART TX + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_8, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + { // UART RX + .port = GPIOD, + .pin_init = { .Pin = GPIO_PIN_9, .Mode = GPIO_MODE_AF_PP, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF7_USART3 }, + .active_state = 0 + }, + + { // I2C SCL for MFX VBUS + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_6, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF4_I2C1 }, + .active_state = 0 + }, + { // I2C SDA for MFX VBUS + .port = GPIOB, + .pin_init = { .Pin = GPIO_PIN_7, .Mode = GPIO_MODE_AF_OD, .Pull = GPIO_NOPULL, .Speed = GPIO_SPEED_HIGH, .Alternate = GPIO_AF4_I2C1 }, + .active_state = 1 + }, +}; + //--------------------------------------------------------------------+ // RCC Clock //--------------------------------------------------------------------+ @@ -178,8 +204,7 @@ static inline void SystemClock_Config(void) static inline void timer_board_delay(TIM_HandleTypeDef* tim_hdl, uint32_t ms) { uint32_t startMs = __HAL_TIM_GET_COUNTER(tim_hdl); - while ((__HAL_TIM_GET_COUNTER(tim_hdl) - startMs) < ms) - { + while ((__HAL_TIM_GET_COUNTER(tim_hdl) - startMs) < ms) { asm("nop"); //do nothing } } @@ -230,6 +255,11 @@ static inline void board_init2(void) __HAL_RCC_TIM2_CLK_DISABLE(); } +// need to short a jumper +void board_vbus_set(uint8_t rhport, bool state) { + (void) rhport; (void) state; +} + #ifdef __cplusplus } #endif diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk index cea4bfacb..5ff2f4165 100644 --- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk +++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.mk @@ -1,7 +1,11 @@ +MCU_VARIANT = stm32h743xx CFLAGS += -DSTM32H743xx -DHSE_VALUE=8000000 -# Default is HS port -PORT ?= 1 +RHPORT_SPEED = OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 0 + +LD_FILE_GCC = $(FAMILY_PATH)/linker/stm32h743xx_flash.ld # Use Timer module for ULPI PHY reset CFLAGS += -DHAL_TIM_MODULE_ENABLED @@ -9,14 +13,6 @@ SRC_C += \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_tim.c \ $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_tim_ex.c -# GCC -SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h743xx.s -LD_FILE_GCC = $(FAMILY_PATH)/linker/stm32h743xx_flash.ld - -# IAR -SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h743xx.s -LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h743xx_flash.icf - # For flash-jlink target JLINK_DEVICE = stm32h743ii diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c index 27e7d0a49..0be18350c 100644 --- a/hw/bsp/stm32h7/family.c +++ b/hw/bsp/stm32h7/family.c @@ -31,7 +31,12 @@ #include "bsp/board_api.h" TU_ATTR_UNUSED static void Error_Handler(void) { } -void board_vbus_set(uint8_t rhport, bool state) TU_ATTR_WEAK; + +typedef struct { + GPIO_TypeDef* port; + GPIO_InitTypeDef pin_init; + uint8_t active_state; +} board_pindef_t; #include "board.h" @@ -39,7 +44,20 @@ void board_vbus_set(uint8_t rhport, bool state) TU_ATTR_WEAK; // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -UART_HandleTypeDef UartHandle; +#ifdef UART_DEV +UART_HandleTypeDef UartHandle = { + .Instance = UART_DEV, + .Init = { + .BaudRate = CFG_BOARD_UART_BAUDRATE, + .WordLength = UART_WORDLENGTH_8B, + .StopBits = UART_STOPBITS_1, + .Parity = UART_PARITY_NONE, + .HwFlowCtl = UART_HWCONTROL_NONE, + .Mode = UART_MODE_TX_RX, + .OverSampling = UART_OVERSAMPLING_16, + } +}; +#endif //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler @@ -60,8 +78,6 @@ void OTG_HS_IRQHandler(void) { #ifdef TRACE_ETM void trace_etm_init(void) { // H7 trace pin is PE2 to PE6 - // __HAL_RCC_GPIOE_CLK_ENABLE(); - GPIO_InitTypeDef gpio_init; gpio_init.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6; gpio_init.Mode = GPIO_MODE_AF_PP; @@ -83,20 +99,24 @@ void board_init(void) { // Enable All GPIOs clocks __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); // USB ULPI NXT - __HAL_RCC_GPIOC_CLK_ENABLE(); // USB ULPI NXT + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOF_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); // USB ULPI NXT + __HAL_RCC_GPIOH_CLK_ENABLE(); #ifdef __HAL_RCC_GPIOI_CLK_ENABLE - __HAL_RCC_GPIOI_CLK_ENABLE(); // USB ULPI NXT + __HAL_RCC_GPIOI_CLK_ENABLE(); #endif __HAL_RCC_GPIOJ_CLK_ENABLE(); trace_etm_init(); + for (uint8_t i = 0; i < TU_ARRAY_SIZE(board_pindef); i++) { + HAL_GPIO_Init(board_pindef[i].port, &board_pindef[i].pin_init); + } + #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); @@ -115,39 +135,8 @@ void board_init(void) { GPIO_InitTypeDef GPIO_InitStruct; - // LED - GPIO_InitStruct.Pin = LED_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - HAL_GPIO_Init(LED_PORT, &GPIO_InitStruct); - - // Button - GPIO_InitStruct.Pin = BUTTON_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; - HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); - #ifdef UART_DEV - // Uart UART_CLK_EN(); - - GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_PULLUP; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = UART_GPIO_AF; - HAL_GPIO_Init(UART_GPIO_PORT, &GPIO_InitStruct); - - UartHandle.Instance = UART_DEV; - UartHandle.Init.BaudRate = CFG_BOARD_UART_BAUDRATE; - UartHandle.Init.WordLength = UART_WORDLENGTH_8B; - UartHandle.Init.StopBits = UART_STOPBITS_1; - UartHandle.Init.Parity = UART_PARITY_NONE; - UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - UartHandle.Init.Mode = UART_MODE_TX_RX; - UartHandle.Init.OverSampling = UART_OVERSAMPLING_16; HAL_UART_Init(&UartHandle); #endif @@ -237,8 +226,7 @@ void board_init(void) { HAL_PWREx_EnableUSBVoltageDetector(); - // For waveshare openh743 ULPI PHY reset walkaround - board_init2(); + board_init2(); // optional init #if CFG_TUH_ENABLED board_vbus_set(BOARD_TUH_RHPORT, 1); @@ -251,12 +239,22 @@ void board_init(void) { //--------------------------------------------------------------------+ void board_led_write(bool state) { - GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON)); - HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state); +#ifdef PINID_LED + board_pindef_t* pindef = &board_pindef[PINID_LED]; + GPIO_PinState pin_state = state == pindef->active_state ? GPIO_PIN_SET : GPIO_PIN_RESET; + HAL_GPIO_WritePin(pindef->port, pindef->pin_init.Pin, pin_state); +#else + (void) state; +#endif } uint32_t board_button_read(void) { - return (BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN)) ? 1 : 0; +#ifdef PINID_BUTTON + board_pindef_t* pindef = &board_pindef[PINID_BUTTON]; + return pindef->active_state == HAL_GPIO_ReadPin(pindef->port, pindef->pin_init.Pin); +#else + return 0; +#endif } size_t board_get_unique_id(uint8_t id[], size_t max_len) { @@ -282,14 +280,13 @@ int board_uart_write(void const *buf, int len) { #ifdef UART_DEV HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t) buf, len, 0xffff); + return len; #else - (void) buf; + (void) buf; (void) len; + return -1; #endif - - return len; } - #if CFG_TUSB_OS == OPT_OS_NONE volatile uint32_t system_ticks = 0; diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake index d0fb963a9..69e29a20d 100644 --- a/hw/bsp/stm32h7/family.cmake +++ b/hw/bsp/stm32h7/family.cmake @@ -5,7 +5,7 @@ set(ST_PREFIX stm32${ST_FAMILY}xx) set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver) set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY}) -set(MFXSTM32L152 ${TOP}/hw/mcu/st/stm32-mfxstm32l152) +set(ST_MFXSTM32L152 ${TOP}/hw/mcu/st/stm32-mfxstm32l152) set(CMSIS_5 ${TOP}/lib/CMSIS_5) # include board specific @@ -17,6 +17,26 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL set(FAMILY_MCUS STM32H7 CACHE INTERNAL "") +# ---------------------- +# Port & Speed Selection +# ---------------------- +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 0) +endif () +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) +endif () + +if (NOT DEFINED RHPORT_SPEED) + # Most F7 does not has built-in HS PHY + set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_FULL_SPEED) +endif () +if (NOT DEFINED RHPORT_DEVICE_SPEED) + list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED) +endif () +if (NOT DEFINED RHPORT_HOST_SPEED) + list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED) +endif () #------------------------------------ # BOARD_TARGET @@ -52,19 +72,19 @@ function(add_board_target BOARD_TARGET) ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} - # MFXSTM32L152 - ${MFXSTM32L152}/mfxstm32l152.c - ${MFXSTM32L152}/mfxstm32l152_reg.c ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} ${CMSIS_5}/CMSIS/Core/Include ${ST_CMSIS}/Include ${ST_HAL_DRIVER}/Inc - ${MFXSTM32L152} ) - #target_compile_options(${BOARD_TARGET} PUBLIC) - #target_compile_definitions(${BOARD_TARGET} PUBLIC) + target_compile_definitions(${BOARD_TARGET} PUBLIC + BOARD_TUD_RHPORT=${RHPORT_DEVICE} + BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} + BOARD_TUH_RHPORT=${RHPORT_HOST} + BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} + ) update_board(${BOARD_TARGET}) diff --git a/hw/bsp/stm32h7/family.mk b/hw/bsp/stm32h7/family.mk index d46324a2d..29b83cf7d 100644 --- a/hw/bsp/stm32h7/family.mk +++ b/hw/bsp/stm32h7/family.mk @@ -1,31 +1,48 @@ -UF2_FAMILY_ID = 0x6db66082 ST_FAMILY = h7 -DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver - +ST_PREFIX = stm32${ST_FAMILY}xx ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) -ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver +ST_HAL_DRIVER = hw/mcu/st/${ST_PREFIX}_hal_driver +ST_MFXSTM32L152 = hw/mcu/st/stm32-mfxstm32l152 + +UF2_FAMILY_ID = 0x6db66082 include $(TOP)/$(BOARD_PATH)/board.mk CPU_CORE ?= cortex-m7 +# ---------------------- +# Port & Speed Selection +# ---------------------- +RHPORT_SPEED ?= OPT_MODE_FULL_SPEED OPT_MODE_FULL_SPEED +RHPORT_DEVICE ?= 0 +RHPORT_HOST ?= 0 + +# Determine RHPORT_DEVICE_SPEED if not defined +ifndef RHPORT_DEVICE_SPEED +ifeq ($(RHPORT_DEVICE), 0) + RHPORT_DEVICE_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_DEVICE_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif + +# Determine RHPORT_HOST_SPEED if not defined +ifndef RHPORT_HOST_SPEED +ifeq ($(RHPORT_HOST), 0) + RHPORT_HOST_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_HOST_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif + # -------------- # Compiler Flags # -------------- CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_STM32H7 \ - -DBOARD_TUD_RHPORT=$(PORT) - -ifeq ($(PORT), 1) - ifeq ($(SPEED), high) - CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - $(info "Using OTG_HS in HighSpeed mode") - else - CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED - $(info "Using OTG_HS in FullSpeed mode") - endif -else - $(info "Using OTG_FS") -endif + -DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \ + -DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \ + -DBOARD_TUH_RHPORT=${RHPORT_HOST} \ + -DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} \ # GCC Flags CFLAGS_GCC += \ @@ -48,20 +65,29 @@ SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ src/portable/synopsys/dwc2/hcd_dwc2.c \ src/portable/synopsys/dwc2/dwc2_common.c \ - $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \ - $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c \ + $(ST_CMSIS)/Source/Templates/system_${ST_PREFIX}.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_cortex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_dma.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_gpio.c \ + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_i2c.c \ + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_i2c_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_pwr_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_rcc_ex.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart.c \ + $(ST_HAL_DRIVER)/Src/${ST_PREFIX}_hal_uart_ex.c \ INC += \ $(TOP)/$(BOARD_PATH) \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(ST_CMSIS)/Include \ $(TOP)/$(ST_HAL_DRIVER)/Inc + +# Startup +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_$(MCU_VARIANT).s +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_$(MCU_VARIANT).s + +# Linker +LD_FILE_IAR ?= $(ST_CMSIS)/Source/Templates/iar/linker/$(MCU_VARIANT)_flash.icf -- cgit v1.3.1 From ab8160a29bcfdc451b68c68598cdb5f9d212f395 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 7 Nov 2024 16:37:33 +0700 Subject: hcd work with esp32p4 in slave mode but have issue with DMA mode. In slave it enumerate device but has issue with msc bulk in --- docs/reference/supported.rst | 24 ++++++++------- examples/host/cdc_msc_hid_freertos/only.txt | 1 + hw/bsp/espressif/boards/family.c | 6 ++++ .../components/tinyusb_src/CMakeLists.txt | 7 +++-- hw/bsp/espressif/family.cmake | 17 +++++++++-- src/portable/synopsys/dwc2/dwc2_esp32.h | 34 ++++++++++++++++------ 6 files changed, 63 insertions(+), 26 deletions(-) (limited to 'hw') diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index b871490dc..da2431415 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -21,11 +21,13 @@ Supported MCUs +--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ | Dialog | DA1469x | âś” | âś– | âś– | da146xx | | +--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ -| Espressif | ESP32 S2, S3 | âś” | | âś– | dwc2 or esp32sx | | -+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ +| Espressif | S2, S3 | âś” | âś” | âś– | dwc2 or esp32sx | | +| ESP32 +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| | P4 | âś” | âś” | âś” | dwc2 | | ++--------------+----+------------------------+--------+------+-----------+------------------------+-------------------+ | GigaDevice | GD32VF103 | âś” | | âś– | dwc2 | | +--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ -| Infineon | XMC4500 | âś” | | âś– | dwc2 | | +| Infineon | XMC4500 | âś” | âś” | âś– | dwc2 | | +--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+ | MicroChip | SAM | D11, D21, L21, L22 | âś” | | âś– | samd | | | | +-----------------------+--------+------+-----------+------------------------+-------------------+ @@ -89,31 +91,31 @@ Supported MCUs | +----+------------------------+--------+------+-----------+------------------------+-------------------+ | | F1 | 102, 103 | âś” | âś– | âś– | stm32_fsdev | | | | +------------------------+--------+------+-----------+------------------------+-------------------+ -| | | 105, 107 | âś” | | âś– | dwc2 | | +| | | 105, 107 | âś” | âś” | âś– | dwc2 | | | +----+------------------------+--------+------+-----------+------------------------+-------------------+ -| | F2, F4, F7, H7 | âś” | | âś” | dwc2 | | +| | F2, F4, F7, H7 | âś” | âś” | âś” | dwc2 | | | +-----------------------------+--------+------+-----------+------------------------+-------------------+ | | F3 | âś” | âś– | âś– | stm32_fsdev | | | +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | G0, H5 | âś” | | âś– | stm32_fsdev | | +| | G0, H5 | âś” | âś– | âś– | stm32_fsdev | | | +-----------------------------+--------+------+-----------+------------------------+-------------------+ | | G4 | âś” | âś– | âś– | stm32_fsdev | | | +-----------------------------+--------+------+-----------+------------------------+-------------------+ | | L0, L1 | âś” | âś– | âś– | stm32_fsdev | | -| +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| +----+------------------------+--------+------+-----------+------------------------+-------------------+ | | L4 | 4x2, 4x3 | âś” | âś– | âś– | stm32_fsdev | | | | +------------------------+--------+------+-----------+------------------------+-------------------+ -| | | 4x5, 4x6 | âś” | | âś– | dwc2 | | +| | | 4x5, 4x6 | âś” | âś” | âś– | dwc2 | | | +----+------------------------+--------+------+-----------+------------------------+-------------------+ -| | L4+ | âś” | | âś– | dwc2 | | +| | L4+ | âś” | âś” | âś– | dwc2 | | | +-----------------------------+--------+------+-----------+------------------------+-------------------+ | | L5 | âś” | âś– | âś– | stm32_fsdev | | | +----+------------------------+--------+------+-----------+------------------------+-------------------+ | | U5 | 535, 545 | âś” | | âś– | stm32_fsdev | | | | +------------------------+--------+------+-----------+------------------------+-------------------+ -| | | 575, 585 | âś” | | âś– | dwc2 | | +| | | 575, 585 | âś” | âś” | âś– | dwc2 | | | | +------------------------+--------+------+-----------+------------------------+-------------------+ -| | | 59x,5Ax,5Fx,5Gx | âś” | | âś” | dwc2 | | +| | | 59x,5Ax,5Fx,5Gx | âś” | âś” | âś” | dwc2 | | | +----+------------------------+--------+------+-----------+------------------------+-------------------+ | | WBx5 | âś” | âś– | âś– | stm32_fsdev | | +--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ diff --git a/examples/host/cdc_msc_hid_freertos/only.txt b/examples/host/cdc_msc_hid_freertos/only.txt index 472745301..e3ae25260 100644 --- a/examples/host/cdc_msc_hid_freertos/only.txt +++ b/examples/host/cdc_msc_hid_freertos/only.txt @@ -1,3 +1,4 @@ +mcu:ESP32P4 mcu:LPC175X_6X mcu:LPC177X_8X mcu:LPC18XX diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index a1b4334b2..7f4535d49 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -175,7 +175,13 @@ bool usb_init(void) { usb_phy_config_t phy_conf = { .controller = USB_PHY_CTRL_OTG, .target = USB_PHY_TARGET_INT, + + // maybe we can use USB_OTG_MODE_DEFAULT and switch using dwc2 driver +#if CFG_TUD_ENABLED .otg_mode = USB_OTG_MODE_DEVICE, +#elif CFG_TUH_ENABLED + .otg_mode = USB_OTG_MODE_HOST, +#endif }; // OTG IOs config diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt index ae94a0ea4..e2250c4ca 100644 --- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt +++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt @@ -9,9 +9,10 @@ string(TOUPPER OPT_MCU_${target} tusb_mcu) list(APPEND compile_definitions CFG_TUSB_MCU=${tusb_mcu} CFG_TUSB_OS=OPT_OS_FREERTOS - # EXAMPLE port selection: port0 is fullspeed, port1 is highspeed - BOARD_TUD_RHPORT=${TUD_PORT} - BOARD_TUD_MAX_SPEED=$ + BOARD_TUD_RHPORT=${RHPORT_DEVICE} + BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} + BOARD_TUH_RHPORT=${RHPORT_HOST} + BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} ) list(APPEND srcs diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake index ada082c76..aaa611fac 100644 --- a/hw/bsp/espressif/family.cmake +++ b/hw/bsp/espressif/family.cmake @@ -5,14 +5,25 @@ include("${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake") string(TOUPPER ${IDF_TARGET} FAMILY_MCUS) # Device port default to Port1 for P4 (highspeed), Port0 for others (fullspeed) -if (NOT DEFINED TUD_PORT) +set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) + +if (NOT DEFINED RHPORT_DEVICE) if (IDF_TARGET STREQUAL "esp32p4") - set(TUD_PORT 1) + set(RHPORT_DEVICE 1) + set(RHPORT_HOST 1) else () - set(TUD_PORT 0) + set(RHPORT_DEVICE 0) + set(RHPORT_HOST 0) endif () endif() +if (NOT DEFINED RHPORT_DEVICE_SPEED) + list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED) +endif () +if (NOT DEFINED RHPORT_HOST_SPEED) + list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED) +endif () + # Add example src and bsp directories set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components") diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index c8c5bffd0..a86587786 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -60,21 +60,37 @@ static const dwc2_controller_t _dwc2_controller[] = { }; #endif +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ static intr_handle_t usb_ih[TU_ARRAY_SIZE(_dwc2_controller)]; -static void dcd_int_handler_wrap(void* arg) { - const uint8_t rhport = (uint8_t)(uintptr_t) arg; - dcd_int_handler(rhport); +static void dwc2_int_handler_wrap(void* arg) { + const uint8_t rhport = tu_u16_low((uint16_t)(uintptr_t)arg); + const tusb_role_t role = (tusb_role_t) tu_u16_high((uint16_t)(uintptr_t)arg); +#if CFG_TUD_ENABLED + if (role == TUSB_ROLE_DEVICE) { + dcd_int_handler(rhport); + } +#endif +#if CFG_TUH_ENABLED + if (role == TUSB_ROLE_HOST) { + hcd_int_handler(rhport, true); + } +#endif } -TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { - esp_intr_alloc(_dwc2_controller[rhport].irqnum, ESP_INTR_FLAG_LOWMED, - dcd_int_handler_wrap, (void*)(uintptr_t) rhport, &usb_ih[rhport]); +TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) { + if (enabled) { + esp_intr_alloc(_dwc2_controller[rhport].irqnum, ESP_INTR_FLAG_LOWMED, + dwc2_int_handler_wrap, (void*)(uintptr_t)tu_u16(role, rhport), &usb_ih[rhport]); + } else { + esp_intr_free(usb_ih[rhport]); + } } -TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) { - esp_intr_free(usb_ih[rhport]); -} +#define dwc2_dcd_int_enable(_rhport) dwc2_int_set(_rhport, TUSB_ROLE_DEVICE, true) +#define dwc2_dcd_int_disable(_rhport) dwc2_int_set(_rhport, TUSB_ROLE_DEVICE, false) TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { vTaskDelay(pdMS_TO_TICKS(1)); -- cgit v1.3.1 From 8174ab064002edadaaffa50607e7bcbb6802cf82 Mon Sep 17 00:00:00 2001 From: subsonicpulse Date: Thu, 7 Nov 2024 12:16:42 +0100 Subject: Fix Usage of Bootsel Button for Pico 2 see code from https://github.com/raspberrypi/pico-examples/blob/master/picoboard/button/button.c --- hw/bsp/rp2040/family.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c index ccc1e1f70..47d729ea3 100644 --- a/hw/bsp/rp2040/family.c +++ b/hw/bsp/rp2040/family.c @@ -79,7 +79,13 @@ bool __no_inline_not_in_flash_func(get_bootsel_button)(void) { // The HI GPIO registers in SIO can observe and control the 6 QSPI pins. // Note the button pulls the pin *low* when pressed. - bool button_state = (sio_hw->gpio_hi_in & (1u << CS_PIN_INDEX)); + + #if PICO_RP2040 + #define CS_BIT (1u << 1) + #else + #define CS_BIT SIO_GPIO_HI_IN_QSPI_CSN_BITS + #endif + bool button_state = (sio_hw->gpio_hi_in & CS_BIT); // Need to restore the state of chip select, else we are going to have a // bad time when we return to code in flash! -- cgit v1.3.1 From 5d00488907e5591f35772769a917cf6c3ff97181 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 8 Nov 2024 17:23:43 +0700 Subject: get hcd work esp32p4 but only in slave mode. In DMA channel's HCDMA is increased but data transfer over USB is not correct. --- hw/bsp/espressif/boards/family.c | 2 ++ hw/bsp/espressif/family.cmake | 8 +++++++- src/common/tusb_mcu.h | 3 +++ src/portable/synopsys/dwc2/dwc2_esp32.h | 5 +++-- src/portable/synopsys/dwc2/dwc2_type.h | 9 +++++++++ src/tusb_option.h | 13 ++++++++++--- 6 files changed, 34 insertions(+), 6 deletions(-) (limited to 'hw') diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index 7f4535d49..0b1e8badb 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -179,8 +179,10 @@ bool usb_init(void) { // maybe we can use USB_OTG_MODE_DEFAULT and switch using dwc2 driver #if CFG_TUD_ENABLED .otg_mode = USB_OTG_MODE_DEVICE, + .otg_speed = BOARD_TUD_RHPORT ? USB_PHY_SPEED_HIGH : USB_PHY_SPEED_FULL, #elif CFG_TUH_ENABLED .otg_mode = USB_OTG_MODE_HOST, + .otg_speed= BOARD_TUH_RHPORT ? USB_PHY_SPEED_HIGH : USB_PHY_SPEED_FULL, #endif }; diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake index aaa611fac..daa12cdb4 100644 --- a/hw/bsp/espressif/family.cmake +++ b/hw/bsp/espressif/family.cmake @@ -10,9 +10,15 @@ set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) if (NOT DEFINED RHPORT_DEVICE) if (IDF_TARGET STREQUAL "esp32p4") set(RHPORT_DEVICE 1) - set(RHPORT_HOST 1) else () set(RHPORT_DEVICE 0) + endif () +endif() + +if (NOT DEFINED RHPORT_HOST) + if (IDF_TARGET STREQUAL "esp32p4") + set(RHPORT_HOST 1) + else () set(RHPORT_HOST 0) endif () endif() diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index c77afecad..41f552d33 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -169,6 +169,7 @@ defined (STM32F107xB) || defined (STM32F107xC) #define TUP_USBIP_DWC2 #define TUP_USBIP_DWC2_STM32 + #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0 #define TUP_DCD_ENDPOINT_MAX 4 #elif defined(STM32F102x6) || defined(STM32F102xB) || \ @@ -343,12 +344,14 @@ #define TUP_USBIP_DWC2 #define TUP_USBIP_DWC2_ESP32 #define TUP_DCD_ENDPOINT_MAX 7 // only 5 TX FIFO for endpoint IN + #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0 // TODO currently have issue with buffer DMA with espressif #elif TU_CHECK_MCU(OPT_MCU_ESP32P4) #define TUP_USBIP_DWC2 #define TUP_USBIP_DWC2_ESP32 #define TUP_RHPORT_HIGHSPEED 1 // port0 FS, port1 HS #define TUP_DCD_ENDPOINT_MAX 16 // FS 7 ep, HS 16 ep + #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0 // TODO currently have issue with buffer DMA with espressif #elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2) #if (CFG_TUD_ENABLED || !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)) diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index a86587786..42ab4b80f 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -100,14 +100,15 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { (void)dwc2; (void)hs_phy_type; - // nothing to do + // maybe usb_utmi_hal_init() + } // MCU specific PHY update, it is called AFTER init() and core reset TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { (void)dwc2; (void)hs_phy_type; - // nothing to do + // maybe usb_utmi_hal_disable() } #ifdef __cplusplus diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index dfd61bc32..1247f19a3 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -541,13 +541,22 @@ typedef struct { volatile uint32_t gotgctl; // 000 OTG Control and Status volatile dwc2_gotgctl_t gotgctl_bm; }; + union { volatile uint32_t gotgint; // 004 OTG Interrupt + volatile dwc2_gotgint_t gotgint_bm; + }; + union { volatile uint32_t gahbcfg; // 008 AHB Configuration + volatile dwc2_gahbcfg_t gahbcfg_bm; + }; union { volatile uint32_t gusbcfg; // 00c USB Configuration volatile dwc2_gusbcfg_t gusbcfg_bm; }; + union { volatile uint32_t grstctl; // 010 Reset + volatile dwc2_grstctl_t grstctl_bm; + }; volatile uint32_t gintsts; // 014 Interrupt volatile uint32_t gintmsk; // 018 Interrupt Mask volatile uint32_t grxstsr; // 01c Receive Status Debug Read diff --git a/src/tusb_option.h b/src/tusb_option.h index b193d9c09..e9b6a5806 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -241,6 +241,8 @@ #include "tusb_config.h" #endif +#include "common/tusb_mcu.h" + //--------------------------------------------------------------------+ // USBIP //--------------------------------------------------------------------+ @@ -256,12 +258,18 @@ // Enable DWC2 Slave mode for host #ifndef CFG_TUH_DWC2_SLAVE_ENABLE - #define CFG_TUH_DWC2_SLAVE_ENABLE 1 + #ifndef CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT + #define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT 1 + #endif + #define CFG_TUH_DWC2_SLAVE_ENABLE CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT #endif // Enable DWC2 DMA for host #ifndef CFG_TUH_DWC2_DMA_ENABLE - #define CFG_TUH_DWC2_DMA_ENABLE 1 + #ifndef CFG_TUH_DWC2_DMA_ENABLE_DEFAULT + #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 1 + #endif + #define CFG_TUH_DWC2_DMA_ENABLE CFG_TUH_DWC2_DMA_ENABLE_DEFAULT #endif // Enable PIO-USB software host controller @@ -278,7 +286,6 @@ #define CFG_TUH_MAX3421 0 #endif -#include "common/tusb_mcu.h" //-------------------------------------------------------------------- // RootHub Mode detection -- cgit v1.3.1 From 3831786ede034c9cf52a1dbae5b84f7d4449ace6 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 8 Nov 2024 22:53:28 +0700 Subject: minor clean up --- examples/host/device_info/only.txt | 2 -- hw/bsp/stm32f4/boards/feather_stm32f405/board.h | 2 +- hw/bsp/stm32f4/boards/stm32f407blackvet/board.h | 4 ++-- hw/bsp/stm32f4/boards/stm32f412disco/board.h | 10 ---------- hw/bsp/stm32f7/family.cmake | 2 ++ hw/bsp/stm32h7/boards/stm32h743eval/board.cmake | 2 +- hw/bsp/stm32h7/family.cmake | 2 ++ 7 files changed, 8 insertions(+), 16 deletions(-) (limited to 'hw') diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt index de21a54bd..f06d4df00 100644 --- a/examples/host/device_info/only.txt +++ b/examples/host/device_info/only.txt @@ -12,8 +12,6 @@ mcu:MSP432E4 mcu:RP2040 mcu:RX65X mcu:RAXXX -mcu:STM32H7 -mcu:STM32F7 mcu:STM32F4 mcu:STM32F7 mcu:STM32H7 diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h index b4ca8d275..670ce8012 100644 --- a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h +++ b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h @@ -41,7 +41,7 @@ static board_pindef_t board_pindef[] = { { // LED .port = GPIOC, - .pin_init = { .Pin = GPIO_PIN_4, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .pin_init = { .Pin = GPIO_PIN_1, .Mode = GPIO_MODE_OUTPUT_PP, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, .active_state = 1 }, { // BUTTON diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h index ea4c462c3..6879d066b 100644 --- a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h +++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h @@ -47,8 +47,8 @@ static board_pindef_t board_pindef[] = { }, { // BUTTON .port = GPIOE, - .pin_init = { .Pin = GPIO_PIN_4, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLDOWN, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, - .active_state = 1 + .pin_init = { .Pin = GPIO_PIN_4, .Mode = GPIO_MODE_INPUT, .Pull = GPIO_PULLUP, .Speed = GPIO_SPEED_HIGH, .Alternate = 0 }, + .active_state = 0 }, { // UART TX .port = GPIOA, diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/board.h b/hw/bsp/stm32f4/boards/stm32f412disco/board.h index d89ff7d3d..74e664418 100644 --- a/hw/bsp/stm32f4/boards/stm32f412disco/board.h +++ b/hw/bsp/stm32f4/boards/stm32f412disco/board.h @@ -31,16 +31,6 @@ extern "C" { #endif -// LED -#define LED_PORT GPIOE -#define LED_PIN GPIO_PIN_2 -#define LED_STATE_ON 0 - -// Button -#define BUTTON_PORT GPIOA -#define BUTTON_PIN GPIO_PIN_0 -#define BUTTON_STATE_ACTIVE 1 - // UART Enable PA2 as the debug log UART #define UART_DEV USART2 diff --git a/hw/bsp/stm32f7/family.cmake b/hw/bsp/stm32f7/family.cmake index 8ba744fed..dc134e9c0 100644 --- a/hw/bsp/stm32f7/family.cmake +++ b/hw/bsp/stm32f7/family.cmake @@ -37,6 +37,8 @@ if (NOT DEFINED RHPORT_HOST_SPEED) list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED) endif () +cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED) + #------------------------------------ # BOARD_TARGET #------------------------------------ diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake index 6926b905a..02c6bf5fa 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake @@ -1,6 +1,6 @@ set(MCU_VARIANT stm32h743xx) set(JLINK_DEVICE stm32h743xi) -set(JLINK_OPTION "-USB jtrace") +#set(JLINK_OPTION "-USB jtrace") set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld) diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake index 69e29a20d..3e246faed 100644 --- a/hw/bsp/stm32h7/family.cmake +++ b/hw/bsp/stm32h7/family.cmake @@ -38,6 +38,8 @@ if (NOT DEFINED RHPORT_HOST_SPEED) list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED) endif () +cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED) + #------------------------------------ # BOARD_TARGET #------------------------------------ -- cgit v1.3.1 From 13f78e2e7716fda1c0ee1ef09a8bc76fde4f4c57 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 11 Nov 2024 16:07:33 +0700 Subject: add esp32p4 to hil --- hw/bsp/espressif/boards/espressif_p4_function_ev/board.h | 4 ++++ hw/bsp/espressif/boards/family.c | 6 ++++++ test/hil/tinyusb.json | 13 +++++++++++++ 3 files changed, 23 insertions(+) (limited to 'hw') diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h index 9c8aa409f..0022f0d2d 100644 --- a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h +++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h @@ -36,6 +36,10 @@ #define BUTTON_PIN 0 #define BUTTON_STATE_ACTIVE 0 +// For CI hardware test, to test both device and host on the same HS port with help of +#define HIL_DEVICE_HOST_MUX_PIN 47 +#define HIL_DEVICE_STATE 1 + #ifdef __cplusplus } #endif diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index 0b1e8badb..729b3539d 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -105,6 +105,12 @@ void board_init(void) { usb_init(); #endif +#ifdef HIL_DEVICE_HOST_MUX_PIN + gpio_reset_pin(HIL_DEVICE_HOST_MUX_PIN); + gpio_set_direction(HIL_DEVICE_HOST_MUX_PIN, GPIO_MODE_OUTPUT); + gpio_set_level(HIL_DEVICE_HOST_MUX_PIN, CFG_TUD_ENABLED ? HIL_DEVICE_STATE : (1-HIL_DEVICE_STATE)); +#endif + #if CFG_TUH_ENABLED && CFG_TUH_MAX3421 max3421_init(); #endif diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json index 2313f5d13..c92224e26 100644 --- a/test/hil/tinyusb.json +++ b/test/hil/tinyusb.json @@ -1,5 +1,18 @@ { "boards": [ + { + "name": "espressif_p4_function_ev", + "uid": "6055F9F98715", + "build" : { + "flags_on": ["", "CFG_TUD_DWC2_DMA"] + }, + "tests": { + "only": ["device/cdc_msc_freertos", "device/hid_composite_freertos"] + }, + "flasher": "esptool", + "flasher_sn": "4ea4f48f6bc3ee11bbb9d00f9e1b1c54", + "flasher_args": "-b 1500000" + }, { "name": "espressif_s3_devkitm", "uid": "84F703C084E4", -- cgit v1.3.1 From 57c8c223e5f873e8075eb807844140004c74472d Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 11 Nov 2024 16:42:08 +0700 Subject: correctly test dwc2 dma device for s3, disable for p4 (cache issue) and f407 fs (slave only) --- .../components/tinyusb_src/CMakeLists.txt | 5 + src/portable/synopsys/dwc2/dwc2_info.md | 116 ++++++++++----------- src/portable/synopsys/dwc2/dwc2_info.py | 6 +- test/hil/tinyusb.json | 6 -- 4 files changed, 66 insertions(+), 67 deletions(-) (limited to 'hw') diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt index e2250c4ca..900f620fd 100644 --- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt +++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt @@ -60,6 +60,11 @@ if (DEFINED LOG) endif () endif() +if(DEFINED CFLAGS_CLI) + list(APPEND compile_definitions ${CFLAGS_CLI}) +endif() + + idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${tusb_src} REQUIRES src diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index 78c2c50f8..dec021f59 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -1,58 +1,58 @@ -| | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/767 FS | ST F723/L4P5 FS | ST F723 HS | ST F769 | ST H743/H750 | ST L476 FS | ST U5A5 HS | GD32VF103 | XMC4500 | -|:---------------------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:-------------|:------------|:-------------| -| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | -| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | -| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | -| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | -| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | -| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | -| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | DMA internal | -| - single_point | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | hub | n/a | -| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | -| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | n/a | Dedicated | -| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | -| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 0 | 13 | -| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nptx_q_depth | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | 8 | -| - ptx_q_depth | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | 8 | -| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | -| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | -| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | -| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | -| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | -| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | -| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | -| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 0 | 634 | -| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | -| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | -| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | -| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | -| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | +| | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5 HS | XMC4500 | GD32VF103 | +|:---------------------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:-------------|:-------------|:------------| +| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00AEC000 | 0x00001000 | +| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54292A | 0x00000000 | +| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 2.92a | 0.00W | +| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228F5930 | 0x00000000 | +| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | +| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | Slave only | +| - single_point | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | n/a | hub | +| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | +| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | Dedicated | n/a | +| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | +| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 13 | 0 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nptx_q_depth | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | +| - ptx_q_depth | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | +| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 | +| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 | +| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | +| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | +| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 634 | 0 | +| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xDBF08030 | 0x00000000 | +| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit | +| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | +| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | +| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 5884cd455..25edcf22d 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -15,15 +15,15 @@ dwc2_reg_value = { 'ESP32-P4': [0, 0x4F54400A, 0, 0x215FFFD0, 0x03805EB5, 0xDFF1A030], 'ST F207/F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x020001E8, 0x0FF08030], 'ST F407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x03F403E8, 0x17F00030], - 'ST F412/767 FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], + 'ST F412/76x FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], 'ST F723/L4P5 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], 'ST F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x03EED2E8, 0x23F00030], - 'ST F769': [0x2100, 0x4F54320A, 0, 0x229FE190, 0x03EED2E8, 0x23F00030], + 'ST F76x HS': [0x2100, 0x4F54320A, 0, 0x229FE190, 0x03EED2E8, 0x23F00030], 'ST H743/H750': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x03B8D2E8, 0xE3F00030], 'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], 'ST U5A5 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30], + 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030], 'GD32VF103': [0x1000, 0, 0, 0, 0, 0], - 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030] } # Combine dwc2_info with dwc2_reg_list diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json index c92224e26..f5a3f109e 100644 --- a/test/hil/tinyusb.json +++ b/test/hil/tinyusb.json @@ -3,9 +3,6 @@ { "name": "espressif_p4_function_ev", "uid": "6055F9F98715", - "build" : { - "flags_on": ["", "CFG_TUD_DWC2_DMA"] - }, "tests": { "only": ["device/cdc_msc_freertos", "device/hid_composite_freertos"] }, @@ -98,9 +95,6 @@ { "name": "stm32f407disco", "uid": "30001A000647313332353735", - "build" : { - "flags_on": ["", "CFG_TUD_DWC2_DMA"] - }, "flasher": "jlink", "flasher_sn": "000773661813", "flasher_args": "-device stm32f407vg" -- cgit v1.3.1 From 3a89442dbaf7f56b0be06c324d4bc9db02fbaf06 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 11 Nov 2024 21:55:30 +0700 Subject: use arm arch to detect rp2040 --- hw/bsp/rp2040/family.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'hw') diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c index 47d729ea3..452a5568f 100644 --- a/hw/bsp/rp2040/family.c +++ b/hw/bsp/rp2040/family.c @@ -80,9 +80,9 @@ bool __no_inline_not_in_flash_func(get_bootsel_button)(void) { // The HI GPIO registers in SIO can observe and control the 6 QSPI pins. // Note the button pulls the pin *low* when pressed. - #if PICO_RP2040 + #ifdef __ARM_ARCH_6M__ // CM0 for rp2040 #define CS_BIT (1u << 1) - #else + #else // rp2350 (cm33/risv) #define CS_BIT SIO_GPIO_HI_IN_QSPI_CSN_BITS #endif bool button_state = (sio_hw->gpio_hi_in & CS_BIT); -- cgit v1.3.1 From aeae2966a2afa669068e54eef7c4dd2dceffaa0d Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 13 Nov 2024 13:08:30 +0700 Subject: hil add stm32f723disco, add test flags for device/host/dual --- examples/device/cdc_msc/CMakeLists.txt | 2 +- examples/host/device_info/src/main.c | 20 +-- hw/bsp/stm32f7/boards/stm32f723disco/board.cmake | 6 +- hw/bsp/stm32f7/boards/stm32f723disco/board.mk | 5 +- hw/bsp/stm32f7/family.c | 29 +++-- src/portable/synopsys/dwc2/hcd_dwc2.c | 6 +- test/hil/hil_test.py | 147 ++++++++++++++++------- test/hil/tinyusb.json | 69 +++++++++-- 8 files changed, 200 insertions(+), 84 deletions(-) (limited to 'hw') diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt index 9415f8c68..c2f9cb095 100644 --- a/examples/device/cdc_msc/CMakeLists.txt +++ b/examples/device/cdc_msc/CMakeLists.txt @@ -1,5 +1,5 @@ cmake_minimum_required(VERSION 3.17) -set_property(GLOBAL PROPERTY USE_FOLDERS ON) +#set_property(GLOBAL PROPERTY USE_FOLDERS ON) include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) diff --git a/examples/host/device_info/src/main.c b/examples/host/device_info/src/main.c index 8e0185878..70304e449 100644 --- a/examples/host/device_info/src/main.c +++ b/examples/host/device_info/src/main.c @@ -56,8 +56,12 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTYPES //--------------------------------------------------------------------+ - -static uint32_t blink_interval_ms = 1000; +enum { + BLINK_NOT_MOUNTED = 250, + BLINK_MOUNTED = 1000, + BLINK_SUSPENDED = 2500, +}; +static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED; void led_blinking_task(void* param); static void print_utf16(uint16_t* temp_buf, size_t buf_len); @@ -102,6 +106,8 @@ int main(void) { // Invoked when device is mounted (configured) void tuh_mount_cb(uint8_t daddr) { + blink_interval_ms = BLINK_MOUNTED; + // Get Device Descriptor tusb_desc_device_t desc_device; uint8_t xfer_result = tuh_descriptor_get_device_sync(daddr, &desc_device, 18); @@ -161,6 +167,7 @@ void tuh_mount_cb(uint8_t daddr) { // Invoked when device is unmounted (bus reset/unplugged) void tuh_umount_cb(uint8_t daddr) { + blink_interval_ms = BLINK_NOT_MOUNTED; printf("Device removed, address = %d\r\n", daddr); } @@ -227,15 +234,8 @@ void led_blinking_task(void* param) { while (1) { #if CFG_TUSB_OS == OPT_OS_FREERTOS - if (blink_interval_ms == 0) { - vTaskSuspend(NULL); - } else { - vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS); - } + vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS); #else - if (blink_interval_ms == 0) { - return; - } if (board_millis() - start_ms < blink_interval_ms) { return; // not enough time } diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake b/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake index 5655c217e..eb3ed407b 100644 --- a/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake +++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake @@ -5,12 +5,12 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F723xE_FLASH.ld) set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) -# device default to PORT 1 High Speed +# For Hardware test: device default to PORT 0, Host to port 1 if (NOT DEFINED RHPORT_DEVICE) - set(RHPORT_DEVICE 1) + set(RHPORT_DEVICE 0) endif() if (NOT DEFINED RHPORT_HOST) - set(RHPORT_HOST 0) + set(RHPORT_HOST 1) endif() function(update_board TARGET) diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk index eb6799eb0..9b8e7a969 100644 --- a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk +++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk @@ -1,8 +1,9 @@ MCU_VARIANT = stm32f723xx +# For Hardware test: device default to PORT 0, Host to port 1 RHPORT_SPEED = OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED -RHPORT_DEVICE ?= 1 -RHPORT_HOST ?= 0 +RHPORT_DEVICE ?= 0 +RHPORT_HOST ?= 1 CFLAGS += \ -DSTM32F723xx \ diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c index 61beac47e..527fbfe5c 100644 --- a/hw/bsp/stm32f7/family.c +++ b/hw/bsp/stm32f7/family.c @@ -37,6 +37,25 @@ typedef struct { #include "board.h" +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ + +#ifdef UART_DEV +UART_HandleTypeDef UartHandle = { + .Instance = UART_DEV, + .Init = { + .BaudRate = CFG_BOARD_UART_BAUDRATE, + .WordLength = UART_WORDLENGTH_8B, + .StopBits = UART_STOPBITS_1, + .Parity = UART_PARITY_NONE, + .HwFlowCtl = UART_HWCONTROL_NONE, + .Mode = UART_MODE_TX_RX, + .OverSampling = UART_OVERSAMPLING_16, + } +}; +#endif + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ @@ -54,8 +73,6 @@ void OTG_HS_IRQHandler(void) { // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -UART_HandleTypeDef UartHandle; - void board_init(void) { board_clock_init(); @@ -89,14 +106,6 @@ void board_init(void) { #endif #ifdef UART_DEV - UartHandle.Instance = UART_DEV; - UartHandle.Init.BaudRate = CFG_BOARD_UART_BAUDRATE; - UartHandle.Init.WordLength = UART_WORDLENGTH_8B; - UartHandle.Init.StopBits = UART_STOPBITS_1; - UartHandle.Init.Parity = UART_PARITY_NONE; - UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - UartHandle.Init.Mode = UART_MODE_TX_RX; - UartHandle.Init.OverSampling = UART_OVERSAMPLING_16; HAL_UART_Init(&UartHandle); #endif diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index f9fc5ca8e..53583426f 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -1181,8 +1181,7 @@ static bool handle_sof_irq(uint8_t rhport, bool in_isr) { } // Config HCFG FS/LS clock and HFIR for SOF interval according to link speed (value is in PHY clock unit) -static void port0_enable(dwc2_regs_t* dwc2) { - const tusb_speed_t speed = hprt_speed_get(dwc2); +static void port0_enable(dwc2_regs_t* dwc2, tusb_speed_t speed) { uint32_t hcfg = dwc2->hcfg & ~HCFG_FSLS_PHYCLK_SEL; const dwc2_gusbcfg_t gusbcfg_bm = dwc2->gusbcfg_bm; @@ -1252,7 +1251,8 @@ static void handle_hprt_irq(uint8_t rhport, bool in_isr) { if (hprt_bm.enable) { // Port enable - port0_enable(dwc2); + const tusb_speed_t speed = hprt_speed_get(dwc2); + port0_enable(dwc2, speed); } else { // TU_ASSERT(false, ); } diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py index 91fe6b67c..b395c28a4 100755 --- a/test/hil/hil_test.py +++ b/test/hil/hil_test.py @@ -46,6 +46,26 @@ STATUS_SKIPPED = "\033[33mSkipped\033[0m" verbose = False +WCH_RISCV_CONTENT = """ +adapter driver wlinke +adapter speed 6000 +transport select sdi + +wlink_set_address 0x00000000 +set _CHIPNAME wch_riscv +sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1 +set _FLASHNAME $_CHIPNAME.flash + +flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0 + +echo "Ready for Remote Connections" +""" + # ------------------------------------------------------------- # Path # ------------------------------------------------------------- @@ -147,49 +167,60 @@ def flash_jlink(board, firmware): return ret -def flash_stlink(board, firmware): - ret = run_cmd(f'STM32_Programmer_CLI --connect port=swd sn={board["flasher_sn"]} --write {firmware}.elf --go') +def reset_jlink(board): + script = ['halt', 'r', 'go', 'exit'] + f_jlink = f'{board["name"]}_reset.jlink' + if not os.path.exists(f_jlink): + with open(f_jlink, 'w') as f: + f.writelines(f'{s}\n' for s in script) + ret = run_cmd(f'JLinkExe -USB {board["flasher_sn"]} {board["flasher_args"]} -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile {f_jlink}') return ret +def flash_stlink(board, firmware): + return run_cmd(f'STM32_Programmer_CLI --connect port=swd sn={board["flasher_sn"]} --write {firmware}.elf --go') + + +def reset_stlink(board): + return run_cmd(f'STM32_Programmer_CLI --connect port=swd sn={board["flasher_sn"]} --rst --go') + def flash_stflash(board, firmware): ret = run_cmd(f'st-flash --serial {board["flasher_sn"]} write {firmware}.bin 0x8000000') return ret +def reset_stflash(board): + return subprocess.CompletedProcess(args=['dummy'], returncode=0) + + def flash_openocd(board, firmware): ret = run_cmd(f'openocd -c "adapter serial {board["flasher_sn"]}" {board["flasher_args"]} -c "program {firmware}.elf reset exit"') return ret -def flash_openocd_wch(board, firmware): - # Content of the wch-riscv.cfg file - cfg_content = """ -adapter driver wlinke -adapter speed 6000 -transport select sdi +def reset_openocd(board): + ret = run_cmd(f'openocd -c "adapter serial {board["flasher_sn"]}" {board["flasher_args"]} -c "reset exit"') + return ret -wlink_set_address 0x00000000 -set _CHIPNAME wch_riscv -sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001 -set _TARGETNAME $_CHIPNAME.cpu +def flash_openocd_wch(board, firmware): + f_wch = f"wch-riscv_{board['uid']}.cfg" + if not os.path.exists(f_wch): + with open(f_wch, 'w') as file: + file.write(WCH_RISCV_CONTENT) -target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1 -set _FLASHNAME $_CHIPNAME.flash + ret = run_cmd(f'openocd_wch -c "adapter serial {board["flasher_sn"]}" -f {f_wch} ' + f'-c "program {firmware}.elf reset exit"') + return ret -flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0 -echo "Ready for Remote Connections" -""" +def reset_openocd_wch(board): f_wch = f"wch-riscv_{board['uid']}.cfg" if not os.path.exists(f_wch): with open(f_wch, 'w') as file: - file.write(cfg_content) + file.write(WCH_RISCV_CONTENT) - ret = run_cmd(f'openocd_wch -c "adapter serial {board["flasher_sn"]}" -f {f_wch} ' - f'-c "program {firmware}.elf reset exit"') + ret = run_cmd(f'openocd_wch -c "adapter serial {board["flasher_sn"]}" -f {f_wch} -c "program reset exit"') return ret @@ -198,12 +229,25 @@ def flash_openocd_adi(board, firmware): f'{board["flasher_args"]} -c "program {firmware}.elf reset exit"') return ret + +def reset_openocd_adi(board): + ret = run_cmd(f'{OPENCOD_ADI_PATH}/src/openocd -c "adapter serial {board["flasher_sn"]}" -s {OPENCOD_ADI_PATH}/tcl ' + f'{board["flasher_args"]} -c "program reset exit"') + return ret + + def flash_wlink_rs(board, firmware): # wlink use index for probe selection and lacking usb serial support ret = run_cmd(f'wlink flash {firmware}.elf') return ret +def reset_wlink_rs(board): + # wlink use index for probe selection and lacking usb serial support + ret = run_cmd(f'wlink reset') + return ret + + def flash_esptool(board, firmware): port = get_serial_dev(board["flasher_sn"], None, None, 0) fw_dir = os.path.dirname(f'{firmware}.bin') @@ -213,28 +257,39 @@ def flash_esptool(board, firmware): flash_args = f.read().strip().replace('\n', ' ') command = (f'esptool.py --chip {idf_target} -p {port} {board["flasher_args"]} ' f'--before=default_reset --after=hard_reset write_flash {flash_args}') - # command = f'echo abc' ret = run_cmd(command, cwd=fw_dir) return ret +def reset_esptool(board): + return subprocess.CompletedProcess(args=['dummy'], returncode=0) + + def flash_uniflash(board, firmware): ret = run_cmd(f'dslite.sh {board["flasher_args"]} -f {firmware}.hex') return ret +def reset_uniflash(board): + return subprocess.CompletedProcess(args=['dummy'], returncode=0) + + # ------------------------------------------------------------- # Tests: dual # ------------------------------------------------------------- def test_dual_host_info_to_device_cdc(board): uid = board['uid'] declared_devs = [f'{d["vid_pid"]}_{d["serial"]}' for d in board['tests']['dev_attached']] - port = get_serial_dev(uid, 'TinyUSB', "TinyUSB_Device", 0) ser = open_serial_dev(port) - # read from serial, first line should contain vid/pid and serial + + # read from cdc, first line should contain vid/pid and serial data = ser.read(1000) + ser.close() + if len(data) == 0: + assert False, 'No data from device' lines = data.decode('utf-8').splitlines() + enum_dev_sn = [] for l in lines: vid_pid_sn = re.search(r'ID ([0-9a-fA-F]+):([0-9a-fA-F]+) SN (\w+)', l) @@ -243,12 +298,8 @@ def test_dual_host_info_to_device_cdc(board): enum_dev_sn.append(f'{vid_pid_sn.group(1)}_{vid_pid_sn.group(2)}_{vid_pid_sn.group(3)}') if set(declared_devs) != set(enum_dev_sn): - # for pico/pico2 make this test optional - failed_msg = f'Enumerated devices {enum_dev_sn} not match with declared {declared_devs}' - if 'raspberry_pi_pico' in board['name']: - print(f'\r\n {failed_msg} {STATUS_FAILED} ', end='') - else: - assert False, failed_msg + failed_msg = f'Expected {declared_devs}, Enumerated {enum_dev_sn}' + assert False, failed_msg return 0 @@ -256,12 +307,17 @@ def test_dual_host_info_to_device_cdc(board): # Tests: host # ------------------------------------------------------------- def test_host_device_info(board): - uid = board['uid'] declared_devs = [f'{d["vid_pid"]}_{d["serial"]}' for d in board['tests']['dev_attached']] port = get_serial_dev(board["flasher_sn"], None, None, 0) ser = open_serial_dev(port) + + # reset device since we can miss the first line + ret = globals()[f'reset_{board["flasher"].lower()}'](board) + assert ret.returncode == 0, 'Failed to reset device' + data = ser.read(1000) + ser.close() if len(data) == 0: assert False, 'No data from device' @@ -274,12 +330,8 @@ def test_host_device_info(board): enum_dev_sn.append(f'{vid_pid_sn.group(1)}_{vid_pid_sn.group(2)}_{vid_pid_sn.group(3)}') if set(declared_devs) != set(enum_dev_sn): - # for pico/pico2 make this test optional - failed_msg = f'Enumerated devices {enum_dev_sn} not match with declared {declared_devs}' - if 'raspberry_pi_pico' in board['name']: - print(f'\r\n {failed_msg} {STATUS_FAILED} ', end='') - else: - assert False, failed_msg + failed_msg = f'Expected {declared_devs}, Enumerated {enum_dev_sn}' + assert False, failed_msg return 0 @@ -323,7 +375,8 @@ def test_device_cdc_msc(board): str = b"test_str" ser.write(str) ser.flush() - assert ser.read(len(str)) == str, 'CDC wrong data' + rd_str = ser.read(len(str)) + assert rd_str == str, f'CDC wrong data: expected: {str} was {rd_str}' # Block test data = read_disk_file(uid,0,'README.TXT') @@ -430,10 +483,14 @@ device_tests = [ 'device/hid_boot_interface', ] -host_tests = [ +dual_tests = [ 'dual/host_info_to_device_cdc', ] +host_test = [ + 'host/device_info', +] + def test_board(board): name = board['name'] @@ -444,8 +501,12 @@ def test_board(board): if 'tests' in board: board_tests = board['tests'] - if 'dev_attached' in board_tests: - test_list += host_tests + if 'device' in board_tests and board_tests['device'] == True: + test_list += list(device_tests) + if 'dual' in board_tests and board_tests['dual'] == True: + test_list += dual_tests + if 'host' in board_tests and board_tests['host'] == True: + test_list += host_test if 'only' in board_tests: test_list = board_tests['only'] if 'skip' in board_tests: @@ -455,7 +516,7 @@ def test_board(board): print(f'{name:25} {skip:30} ... Skip') # board_test is added last to disable board's usb - #test_list.append('device/board_test') + test_list.append('device/board_test') err_count = 0 flags_on_list = [""] @@ -473,7 +534,7 @@ def test_board(board): fw_name = f'{fw_dir}/{os.path.basename(test)}' print(f'{name+f1_str:40} {test:30} ... ', end='') - if not os.path.exists(fw_dir): + if not os.path.exists(fw_dir) or not (os.path.exists(f'{fw_name}.elf') or os.path.exists(f'{fw_name}.bin')): print('Skip (no binary)') continue diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json index 2d61981f2..f3ef9dcf7 100644 --- a/test/hil/tinyusb.json +++ b/test/hil/tinyusb.json @@ -27,6 +27,9 @@ { "name": "feather_nrf52840_express", "uid": "1F0479CD0F764471", + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "jlink", "flasher_sn": "000682804350", "flasher_args": "-device nrf52840_xxaa" @@ -34,6 +37,9 @@ { "name": "max32666fthr", "uid": "0C81464124010B20FF0A08CC2C", + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "openocd_adi", "flasher_sn": "E6614C311B597D32", "flasher_args": "-f interface/cmsis-dap.cfg -f target/max32665.cfg" @@ -41,16 +47,20 @@ { "name": "metro_m4_express", "uid": "9995AD485337433231202020FF100A34", - "flasher": "jlink", - "flasher_sn": "123456", - "flasher_args": "-device ATSAMD51J19", "tests": { + "device": true, "host": false, "dual": true, "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002130"}] - } + }, + "flasher": "jlink", + "flasher_sn": "123456", + "flasher_args": "-device ATSAMD51J19" }, { "name": "lpcxpresso11u37", "uid": "17121919", + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "jlink", "flasher_sn": "000724441579", "flasher_args": "-device LPC11U37/401" @@ -59,6 +69,7 @@ "name": "ra4m1_ek", "uid": "152E163038303131393346E46F26574B", "tests": { + "device": true, "host": false, "dual": false, "skip": ["device/cdc_msc", "device/cdc_msc_freertos"] }, "comment": "MSC is slow to enumerated #2602", @@ -69,22 +80,24 @@ { "name": "raspberry_pi_pico", "uid": "E6614C311B764A37", - "flasher": "openocd", - "flasher_sn": "E6614103E72C1D2F", - "flasher_args": "-f interface/cmsis-dap.cfg -f target/rp2040.cfg -c \"adapter speed 5000\"", "tests": { + "device": true, "host": false, "dual": false, "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002470"}] - } + }, + "flasher": "openocd", + "flasher_sn": "E6614103E72C1D2F", + "flasher_args": "-f interface/cmsis-dap.cfg -f target/rp2040.cfg -c \"adapter speed 5000\"" }, { "name": "raspberry_pi_pico2", "uid": "560AE75E1C7152C9", - "flasher": "openocd", - "flasher_sn": "E6633861A3978538", - "flasher_args": "-f interface/cmsis-dap.cfg -f target/rp2350.cfg -c \"adapter speed 5000\"", "tests": { + "device": true, "host": false, "dual": false, "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "533D004242"}] - } + }, + "flasher": "openocd", + "flasher_sn": "E6633861A3978538", + "flasher_args": "-f interface/cmsis-dap.cfg -f target/rp2350.cfg -c \"adapter speed 5000\"" }, { "name": "stm32f072disco", @@ -93,12 +106,29 @@ "flasher_sn": "779541626", "flasher_args": "-device stm32f072rb" }, + { + "name": "stm32f723disco", + "uid": "460029001951373031313335", + "build" : { + "flags_on": ["", "CFG_TUD_DWC2_DMA"] + }, + "tests": { + "device": true, "host": true, "dual": false, + "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2003414"}] + }, + "flasher": "jlink", + "flasher_sn": "000776606156", + "flasher_args": "-device stm32f723ie" + }, { "name": "stm32h743nucleo", "uid": "110018000951383432343236", "build" : { "flags_on": ["", "CFG_TUD_DWC2_DMA"] }, + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "stlink", "flasher_sn": "004C00343137510F39383538", "flasher_args": "" @@ -106,6 +136,9 @@ { "name": "stm32g0b1nucleo", "uid": "4D0038000450434E37343120", + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "openocd", "flasher_sn": "066FFF495087534867063844", "flasher_args": "-f interface/stlink.cfg -f target/stm32g0x.cfg" @@ -118,6 +151,9 @@ "build" : { "flags_on": ["", "CFG_TUD_DWC2_DMA"] }, + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "jlink", "flasher_sn": "000778170924", "flasher_args": "-device stm32f769ni" @@ -125,6 +161,9 @@ { "name": "mimxrt1015_evk", "uid": "DC28F865D2111D228D00B0543A70463C", + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "jlink", "flasher_sn": "000726284213", "flasher_args": "-device MIMXRT1015DAF5A" @@ -132,6 +171,9 @@ { "name": "nanoch32v203", "uid": "CDAB277B0FBC03E339E339E3", + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "openocd_wch", "flasher_sn": "EBCA8F0670AF", "flasher_args": "" @@ -139,6 +181,9 @@ { "name": "stm32f407disco", "uid": "30001A000647313332353735", + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "jlink", "flasher_sn": "000773661813", "flasher_args": "-device stm32f407vg" -- cgit v1.3.1 From d37707d6dd6147511cfaa10f21bdc4e28f2cdf69 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 18 Nov 2024 23:00:16 +0700 Subject: move handle ep slave/dma wihtin compiler macro --- hw/bsp/family_support.cmake | 5 + src/portable/synopsys/dwc2/dcd_dwc2.c | 262 ++++++++++++++++++---------------- 2 files changed, 141 insertions(+), 126 deletions(-) (limited to 'hw') diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index aa5e037d1..57fa63261 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -289,6 +289,11 @@ function(family_add_tinyusb TARGET OPT_MCU RTOS) ) endif () + # compile define from command line + if(DEFINED CFLAGS_CLI) + target_compile_options(${TARGET}-tinyusb PUBLIC ${CFLAGS_CLI}) + endif() + endfunction() # Add bin/hex output diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 2ca4dc88d..b1cb8c3ea 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -217,24 +217,32 @@ static void dfifo_device_init(uint8_t rhport) { //-------------------------------------------------------------------- static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); + const uint8_t epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); + const uint8_t dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); xfer->max_size = tu_edpt_packet_size(p_endpoint_desc); xfer->interval = p_endpoint_desc->bInterval; - // USBAEP, EPTYP, SD0PID_SEVNFRM, MPSIZ are the same for IN and OUT endpoints. - uint32_t epctl = (1 << DOEPCTL_USBAEP_Pos) | - (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) | - (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << DOEPCTL_MPSIZ_Pos); + // Endpoint control + union { + uint32_t value; + dwc2_depctl_t bm; + } depctl; + depctl.value = 0; + + depctl.bm.mps = xfer->max_size; + depctl.bm.active = 1; + depctl.bm.type = p_endpoint_desc->bmAttributes.xfer; + if (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS) { + depctl.bm.set_data0_iso_even = 1; + } if (dir == TUSB_DIR_IN) { - epctl |= (epnum << DIEPCTL_TXFNUM_Pos); + depctl.bm.tx_fifo_num = epnum; } dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum]; - dep->ctl = epctl; + dep->ctl = depctl.value; dwc2->daintmsk |= TU_BIT(epnum + DAINT_SHIFT(dir)); } @@ -288,7 +296,7 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { } } -static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir) { +static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uint8_t dir) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir); const uint8_t is_epout = dir ? 0 : 1; @@ -571,6 +579,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t xfer->total_len = total_bytes; // Schedule packets to be sent within interrupt + // TODO xfer fifo may only available for slave mode edpt_schedule_packets(rhport, epnum, dir); return true; @@ -654,6 +663,48 @@ static void handle_bus_reset(uint8_t rhport) { dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT; } +static void handle_enum_done(uint8_t rhport) { + dwc2_regs_t *dwc2 = DWC2_REG(rhport); + tusb_speed_t speed; + switch (dwc2->dsts_bm.enum_speed) { + case DCFG_SPEED_HIGH: + speed = TUSB_SPEED_HIGH; + break; + + case DCFG_SPEED_LOW: + speed = TUSB_SPEED_LOW; + break; + + case DCFG_SPEED_FULL_30_60MHZ: + case DCFG_SPEED_FULL_48MHZ: + default: + speed = TUSB_SPEED_FULL; + break; + } + + // TODO must update GUSBCFG_TRDT according to link speed + dcd_event_bus_reset(rhport, speed, true); +} + +#if 0 +TU_ATTR_ALWAYS_INLINE static inline void print_doepint(uint32_t doepint) { + const char* str[] = { + "XFRC", "DIS", "AHBERR", "SETUP_DONE", + "ORXED", "STATUS_RX", "SETUP_B2B", "RSV7", + "OPERR", "BNA", "RSV10", "ISODROP", + "BBLERR", "NAK", "NYET", "SETUP_RX" + }; + + for(uint32_t i=0; itotal_len, XFER_RESULT_SUCCESS, true); - } - } - } -} - -static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) { - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - - if (doepint_bm.setup_phase_done) { - dma_setup_prepare(rhport); - dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); - return; - } - - // OUT XFER complete - if (doepint_bm.xfer_complete) { - // only handle data skip if it is setup or status related - // Normal OUT transfer complete - if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) { if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { - // EP0 can only handle one packet Schedule another packet to be received. + // EP0 can only handle one packet, Schedule another packet to be received. edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT); } else { - dwc2_dep_t* epout = &dwc2->epout[epnum]; - xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - - // determine actual received bytes - const uint16_t remain = epout->tsiz_bm.xfer_size; - xfer->total_len -= remain; - - // this is ZLP, so prepare EP0 for next setup - // TODO use status phase rx - if(epnum == 0 && xfer->total_len == 0) { - dma_setup_prepare(rhport); - } - dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); } } } } -#if 0 -TU_ATTR_ALWAYS_INLINE static inline void print_doepint(uint32_t doepint) { - const char* str[] = { - "XFRC", "DIS", "AHBERR", "SETUP_DONE", - "ORXED", "STATUS_RX", "SETUP_B2B", "RSV7", - "OPERR", "BNA", "RSV10", "ISODROP", - "BBLERR", "NAK", "NYET", "SETUP_RX" - }; - - for(uint32_t i=0; idaint & TU_BIT(DAINT_OEPINT_Pos + epnum)) { - dwc2_dep_t* epout = &dwc2->epout[epnum]; - const uint32_t doepint = epout->intr; - const dwc2_doepint_t doepint_bm = epout->doepint_bm; - - epout->intr = doepint; // Clear interrupt - - // print_doepint(doepint); - if (is_dma) { - handle_epout_dma(rhport, epnum, doepint_bm); - } else { - handle_epout_slave(rhport, epnum, doepint_bm); - } - } - } -} - static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepint_bm) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); dwc2_dep_t* epin = &dwc2->epin[epnum]; @@ -872,6 +842,45 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep } } } +#endif + +#if CFG_TUD_DWC2_DMA_ENABLE +static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + + if (doepint_bm.setup_phase_done) { + dma_setup_prepare(rhport); + dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); + return; + } + + // OUT XFER complete + if (doepint_bm.xfer_complete) { + // only handle data skip if it is setup or status related + // Normal OUT transfer complete + if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) { + if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { + // EP0 can only handle one packet Schedule another packet to be received. + edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT); + } else { + dwc2_dep_t* epout = &dwc2->epout[epnum]; + xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); + + // determine actual received bytes + const uint16_t remain = epout->tsiz_bm.xfer_size; + xfer->total_len -= remain; + + // this is ZLP, so prepare EP0 for next setup + // TODO use status phase rx + if(epnum == 0 && xfer->total_len == 0) { + dma_setup_prepare(rhport); + } + + dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); + } + } + } +} static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepint_bm) { // dwc2_regs_t* dwc2 = DWC2_REG(rhport); @@ -890,27 +899,45 @@ static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepin } } } +#endif -static void handle_epin_irq(uint8_t rhport) { +static void handle_ep_irq(uint8_t rhport, uint8_t dir) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); const bool is_dma = dma_device_enabled(dwc2); const uint8_t ep_count = DWC2_EP_COUNT(dwc2); + const uint8_t daint_offset = (dir == TUSB_DIR_IN) ? DAINT_IEPINT_Pos : DAINT_OEPINT_Pos; - // DAINT for a given EP clears when DIEPINTx is cleared. - // IEPINT will be cleared when DAINT's out bits are cleared. + // DAINT for a given EP clears when DEPINTx is cleared. + // EPINT will be cleared when DAINT bits are cleared. for (uint8_t epnum = 0; epnum < ep_count; epnum++) { - if (dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + epnum)) { - dwc2_dep_t* epin = &dwc2->epin[epnum]; - const uint32_t diepint = epin->intr; - const dwc2_diepint_t diepint_bm = epin->diepint_bm; + if (dwc2->daint & TU_BIT(daint_offset + epnum)) { + dwc2_dep_t* epout = &dwc2->ep[1-dir][epnum]; + union { + uint32_t value; + dwc2_diepint_t diepint_bm; + dwc2_doepint_t doepint_bm; + } intr; + intr.value = epout->intr; - epin->intr = diepint; // Clear interrupt + epout->intr = intr.value; // Clear interrupt // print_doepint(doepint); if (is_dma) { - handle_epin_dma(rhport, epnum, diepint_bm); + #if CFG_TUD_DWC2_DMA_ENABLE + if (dir == TUSB_DIR_IN) { + handle_epin_dma(rhport, epnum, intr.diepint_bm); + } else { + handle_epout_dma(rhport, epnum, intr.doepint_bm); + } + #endif } else { - handle_epin_slave(rhport, epnum, diepint_bm); + #if CFG_TUD_DWC2_SLAVE_ENABLE + if (dir == TUSB_DIR_IN) { + handle_epin_slave(rhport, epnum, intr.diepint_bm); + } else { + handle_epout_slave(rhport, epnum, intr.doepint_bm); + } + #endif } } } @@ -931,8 +958,8 @@ static void handle_epin_irq(uint8_t rhport) { void dcd_int_handler(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint32_t const int_mask = dwc2->gintmsk; - uint32_t const gintsts = dwc2->gintsts & int_mask; + const uint32_t gintmask = dwc2->gintmsk; + const uint32_t gintsts = dwc2->gintsts & gintmask; if (gintsts & GINTSTS_USBRST) { // USBRST is start of reset. @@ -943,26 +970,7 @@ void dcd_int_handler(uint8_t rhport) { if (gintsts & GINTSTS_ENUMDNE) { // ENUMDNE is the end of reset where speed of the link is detected dwc2->gintsts = GINTSTS_ENUMDNE; - - tusb_speed_t speed; - switch (dwc2->dsts_bm.enum_speed) { - case DCFG_SPEED_HIGH: - speed = TUSB_SPEED_HIGH; - break; - - case DCFG_SPEED_LOW: - speed = TUSB_SPEED_LOW; - break; - - case DCFG_SPEED_FULL_30_60MHZ: - case DCFG_SPEED_FULL_48MHZ: - default: - speed = TUSB_SPEED_FULL; - break; - } - - // TODO must update GUSBCFG_TRDT according to link speed - dcd_event_bus_reset(rhport, speed, true); + handle_enum_done(rhport); } if (gintsts & GINTSTS_USBSUSP) { @@ -1001,6 +1009,7 @@ void dcd_int_handler(uint8_t rhport) { dcd_event_sof(rhport, frame, true); } +#if CFG_TUD_DWC2_SLAVE_ENABLE // RxFIFO non-empty interrupt handling. if (gintsts & GINTSTS_RXFLVL) { // RXFLVL bit is read-only @@ -1012,17 +1021,18 @@ void dcd_int_handler(uint8_t rhport) { dwc2->gintmsk |= GINTMSK_RXFLVLM; } +#endif // OUT endpoint interrupt handling. if (gintsts & GINTSTS_OEPINT) { // OEPINT is read-only, clear using DOEPINTn - handle_epout_irq(rhport); + handle_ep_irq(rhport, TUSB_DIR_OUT); } // IN endpoint interrupt handling. if (gintsts & GINTSTS_IEPINT) { // IEPINT bit read-only, clear using DIEPINTn - handle_epin_irq(rhport); + handle_ep_irq(rhport, TUSB_DIR_IN); } // // Check for Incomplete isochronous IN transfer -- cgit v1.3.1 From 4da5de707b53389c8fe35f6b448f3d1bfe7c91e8 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 20 Nov 2024 18:03:42 +0700 Subject: have p4 dma somewhat working but having issue with buffer that does not occupy the whole cache line --- .../components/tinyusb_src/CMakeLists.txt | 8 ++++ src/device/dcd.h | 6 +-- src/device/usbd.c | 20 +++++++--- src/portable/synopsys/dwc2/dcd_dwc2.c | 42 ++++++++++++++++----- src/portable/synopsys/dwc2/dwc2_common.c | 2 + src/portable/synopsys/dwc2/dwc2_esp32.h | 44 ++++++++++++++++++++++ 6 files changed, 104 insertions(+), 18 deletions(-) (limited to 'hw') diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt index 900f620fd..9f55c8d5a 100644 --- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt +++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt @@ -15,6 +15,13 @@ list(APPEND compile_definitions BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} ) +if (target STREQUAL esp32p4) + # P4 change alignment to 64 (DCache line size) for possible DMA configuration + list(APPEND compile_definitions + CFG_TUSB_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\) + ) +endif () + list(APPEND srcs # common ${tusb_src}/tusb.c @@ -68,6 +75,7 @@ endif() idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${tusb_src} REQUIRES src + PRIV_REQUIRES esp_mm ) target_compile_definitions(${COMPONENT_LIB} PUBLIC ${compile_definitions}) diff --git a/src/device/dcd.h b/src/device/dcd.h index d01f82e01..0ecdec4ed 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -93,15 +93,15 @@ typedef struct TU_ATTR_ALIGNED(4) { // clean/flush data cache: write cache -> memory. // Required before an DMA TX transfer to make sure data is in memory -void dcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +void dcd_dcache_clean(const void* addr, uint32_t data_size); // invalidate data cache: mark cache as invalid, next read will read from memory // Required BOTH before and after an DMA RX transfer -void dcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +void dcd_dcache_invalidate(const void* addr, uint32_t data_size); // clean and invalidate data cache // Required before an DMA transfer where memory is both read/write by DMA -void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size); //--------------------------------------------------------------------+ // Controller API diff --git a/src/device/usbd.c b/src/device/usbd.c index a730b745b..f485b6872 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -46,9 +46,7 @@ // Weak stubs: invoked if no strong implementation is available //--------------------------------------------------------------------+ TU_ATTR_WEAK void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) { - (void) rhport; - (void) eventid; - (void) in_isr; + (void) rhport; (void) eventid; (void) in_isr; } TU_ATTR_WEAK void tud_sof_cb(uint32_t frame_count) { @@ -82,9 +80,7 @@ TU_ATTR_WEAK void tud_resume_cb(void) { } TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const* request) { - (void) rhport; - (void) stage; - (void) request; + (void) rhport; (void) stage; (void) request; return false; } @@ -101,6 +97,18 @@ TU_ATTR_WEAK void dcd_disconnect(uint8_t rhport) { (void) rhport; } +TU_ATTR_WEAK void dcd_dcache_clean(const void* addr, uint32_t data_size) { + (void) addr; (void) data_size; +} + +TU_ATTR_WEAK void dcd_dcache_invalidate(const void* addr, uint32_t data_size) { + (void) addr; (void) data_size; +} + +TU_ATTR_WEAK void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) { + (void) addr; (void) data_size; +} + //--------------------------------------------------------------------+ // Device Data //--------------------------------------------------------------------+ diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 2b3ef096f..a4ebacfcb 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -46,8 +46,7 @@ //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ - -static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2]; +static CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN uint32_t _setup_packet[2]; typedef struct { uint8_t* buffer; @@ -73,6 +72,25 @@ static bool _sof_en; //-------------------------------------------------------------------- // DMA //-------------------------------------------------------------------- +#if DWC2_ENABLE_MEM_CACHE +void dcd_dcache_clean(const void* addr, uint32_t data_size) { + if (addr && data_size) { + dwc2_dcache_clean(addr, data_size); + } +} + +void dcd_dcache_invalidate(const void* addr, uint32_t data_size) { + if (addr && data_size) { + dwc2_dcache_invalidate(addr, data_size); + } +} + +void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) { + if (addr && data_size) { + dwc2_dcache_clean_invalidate(addr, data_size); + } +} +#endif TU_ATTR_ALWAYS_INLINE static inline bool dma_device_enabled(const dwc2_regs_t* dwc2) { (void) dwc2; @@ -180,7 +198,7 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { // Check if free space is available TU_ASSERT(_dfifo_top >= fifo_size + dwc2->grxfsiz); _dfifo_top -= fifo_size; - TU_LOG(DWC2_DEBUG, " TX FIFO %u: allocated %u words at offset %u\r\n", epnum, fifo_size, _dfifo_top); + // TU_LOG(DWC2_DEBUG, " TX FIFO %u: allocated %u words at offset %u\r\n", epnum, fifo_size, _dfifo_top); // Both TXFD and TXSA are in unit of 32-bit words. if (epnum == 0) { @@ -348,14 +366,18 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin const bool is_dma = dma_device_enabled(dwc2); if(is_dma) { + if (dir == TUSB_DIR_IN && total_bytes != 0) { + dcd_dcache_clean(xfer->buffer, total_bytes); + } dep->diepdma = (uintptr_t) xfer->buffer; - } - - dep->diepctl = depctl.value; // enable endpoint + dep->diepctl = depctl.value; // enable endpoint + } else { + dep->diepctl = depctl.value; // enable endpoint - // Slave: enable tx fifo empty interrupt only if there is data. Note must after depctl enable - if (!is_dma && dir == TUSB_DIR_IN && total_bytes != 0) { - dwc2->diepempmsk |= (1 << epnum); + // Enable tx fifo empty interrupt only if there is data. Note must after depctl enable + if (dir == TUSB_DIR_IN && total_bytes != 0) { + dwc2->diepempmsk |= (1 << epnum); + } } } @@ -847,6 +869,7 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi if (doepint_bm.setup_phase_done) { dma_setup_prepare(rhport); + dcd_dcache_invalidate(_setup_packet, 8); dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); return; } @@ -873,6 +896,7 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi dma_setup_prepare(rhport); } + dcd_dcache_invalidate(xfer->buffer, xfer->total_len); dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); } } diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index ef155c8f7..f80ae9acb 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -229,6 +229,8 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) { dwc2->gotgint = 0xFFFFFFFFU; dwc2->gintmsk = 0; + TU_LOG(DWC2_COMMON_DEBUG, "DMA = %u\r\n", is_dma); + if (is_dma) { // DMA seems to be only settable after a core reset, and not possible to switch on-the-fly dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2; diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index 42ab4b80f..24ff80bce 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -111,6 +111,50 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint // maybe usb_utmi_hal_disable() } +//--------------------------------------------------------------------+ +// Data Cache +//--------------------------------------------------------------------+ +#if defined(SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE) && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE +#include "sdkconfig.h" +#include "hal/cache_hal.h" +#include "esp_cache.h" +#include "esp_log.h" + +#define DWC2_MEM_CACHE_LINE_SIZE CONFIG_CACHE_L1_CACHE_LINE_SIZE +#define DWC2_ENABLE_MEM_CACHE 1 + +TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) { + if (size & (CONFIG_CACHE_L1_CACHE_LINE_SIZE-1)) { + size = (size & ~(CONFIG_CACHE_L1_CACHE_LINE_SIZE-1)) + CONFIG_CACHE_L1_CACHE_LINE_SIZE; + } + return size; +} + +TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_clean(const void* addr, uint32_t data_size) { + // round up to cache line size + const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M; + data_size = round_up_to_cache_line_size(data_size); + //ESP_EARLY_LOGI("ESP32_DWC", "dcache clean, addr 0x%"PRIx32", size %d (%s)", (uintptr_t)addr, data_size); + assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag)); +} + +TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_invalidate(const void* addr, uint32_t data_size) { + const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_M2C; + data_size = round_up_to_cache_line_size(data_size); + //ESP_EARLY_LOGI("ESP32_DWC", "dcache invalidate, addr 0x%"PRIx32", size %d (%s)", (uintptr_t)addr, data_size); + assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag)); +} + +TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_clean_invalidate(const void* addr, uint32_t data_size) { + const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_DIR_M2C; + data_size = round_up_to_cache_line_size(data_size); + //ESP_EARLY_LOGI("ESP32_DWC", "dcache clean_invalidate, addr 0x%"PRIx32", size %d (%s)", (uintptr_t)addr, data_size); + assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag)); +} + +#endif // SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE + + #ifdef __cplusplus } #endif -- cgit v1.3.1 From fa523a5682d8dc91cc1c7a63475623743e37ac83 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 21 Nov 2024 10:15:30 +0700 Subject: make sure usb buffer occupies whole cache line when DCACHE is enabled for msc,cdc,hid HIL enable device DMA for p4 --- .../boards/espressif_p4_function_ev/board.h | 4 +- src/class/cdc/cdc_device.c | 10 +- src/class/hid/hid_device.c | 15 ++- src/class/msc/msc_device.c | 125 +++++++++------------ src/common/tusb_common.h | 3 + src/common/tusb_compiler.h | 5 +- src/device/usbd_control.c | 29 ++--- src/portable/synopsys/dwc2/dcd_dwc2.c | 8 +- src/tusb_option.h | 6 +- test/hil/tinyusb.json | 3 + 10 files changed, 105 insertions(+), 103 deletions(-) (limited to 'hw') diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h index 0022f0d2d..c4f73c72e 100644 --- a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h +++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h @@ -8,7 +8,7 @@ * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: + * furnished to do so, subject to the following conditions:aaaaa * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. @@ -33,7 +33,7 @@ // #define NEOPIXEL_PIN 48 -#define BUTTON_PIN 0 +#define BUTTON_PIN 35 #define BUTTON_STATE_ACTIVE 0 // For CI hardware test, to test both device and host on the same HS port with help of diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index ebc408f5a..3e856383e 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -69,8 +69,14 @@ typedef struct { OSAL_MUTEX_DEF(tx_ff_mutex); // Endpoint Transfer buffer - CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE]; - CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE]; + union { + CFG_TUD_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; + union { + CFG_TUD_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; } cdcd_interface_t; #define ITF_MEM_RESET_SIZE offsetof(cdcd_interface_t, wanted_char) diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c index ef6c7f3af..257af86e0 100644 --- a/src/class/hid/hid_device.c +++ b/src/class/hid/hid_device.c @@ -53,9 +53,18 @@ typedef struct { // Note: HID descriptor may be not available from application after enumeration tusb_hid_descriptor_hid_t const *hid_descriptor; - uint8_t ctrl_buf[CFG_TUD_HID_EP_BUFSIZE]; - CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_HID_EP_BUFSIZE]; - CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_HID_EP_BUFSIZE]; + union { + CFG_TUD_MEM_ALIGN uint8_t ctrl_buf[CFG_TUD_HID_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; + union { + CFG_TUD_MEM_ALIGN uint8_t epin_buf[CFG_TUD_HID_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; + union { + CFG_TUD_MEM_ALIGN uint8_t epout_buf[CFG_TUD_HID_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; } hidd_interface_t; CFG_TUD_MEM_SECTION tu_static hidd_interface_t _hidd_itf[CFG_TUD_HID]; diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 447560b4d..af035bcf3 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -44,8 +44,7 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ -enum -{ +enum { MSC_STAGE_CMD = 0, MSC_STAGE_DATA, MSC_STAGE_STATUS, @@ -53,11 +52,19 @@ enum MSC_STAGE_NEED_RESET, }; -typedef struct -{ - // TODO optimize alignment - CFG_TUSB_MEM_ALIGN msc_cbw_t cbw; - CFG_TUSB_MEM_ALIGN msc_csw_t csw; +typedef struct { + union { + CFG_TUD_MEM_ALIGN msc_cbw_t cbw; + TUD_DCACHE_PADDING; + }; + union { + CFG_TUD_MEM_ALIGN msc_csw_t csw; + TUD_DCACHE_PADDING; + }; + union { + CFG_TUD_MEM_ALIGN uint8_t ep_buf[CFG_TUD_MSC_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; uint8_t itf_num; uint8_t ep_in; @@ -74,8 +81,7 @@ typedef struct uint8_t add_sense_qualifier; }mscd_interface_t; -CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static mscd_interface_t _mscd_itf; -CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE]; +CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN static mscd_interface_t _mscd_itf; //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION @@ -86,13 +92,11 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc); static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc); static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint32_t xferred_bytes); -TU_ATTR_ALWAYS_INLINE static inline bool is_data_in(uint8_t dir) -{ +TU_ATTR_ALWAYS_INLINE static inline bool is_data_in(uint8_t dir) { return tu_bit_test(dir, 7); } -static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc) -{ +static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc) { // Data residue is always = host expect - actual transferred p_msc->csw.data_residue = p_msc->cbw.total_bytes - p_msc->xferred_len; @@ -100,14 +104,12 @@ static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc) return usbd_edpt_xfer(rhport, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)); } -static inline bool prepare_cbw(uint8_t rhport, mscd_interface_t* p_msc) -{ +static inline bool prepare_cbw(uint8_t rhport, mscd_interface_t* p_msc) { p_msc->stage = MSC_STAGE_CMD; return usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)); } -static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status) -{ +static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status) { msc_cbw_t const * p_cbw = &p_msc->cbw; msc_csw_t * p_csw = &p_msc->csw; @@ -116,24 +118,21 @@ static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status p_msc->stage = MSC_STAGE_STATUS; // failed but sense key is not set: default to Illegal Request - if ( p_msc->sense_key == 0 ) tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); + if (p_msc->sense_key == 0) { + tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); + } // If there is data stage and not yet complete, stall it - if ( p_cbw->total_bytes && p_csw->data_residue ) - { - if ( is_data_in(p_cbw->dir) ) - { + if (p_cbw->total_bytes && p_csw->data_residue) { + if (is_data_in(p_cbw->dir)) { usbd_edpt_stall(rhport, p_msc->ep_in); - } - else - { + } else { usbd_edpt_stall(rhport, p_msc->ep_out); } } } -static inline uint32_t rdwr10_get_lba(uint8_t const command[]) -{ +static inline uint32_t rdwr10_get_lba(uint8_t const command[]) { // use offsetof to avoid pointer to the odd/unaligned address uint32_t const lba = tu_unaligned_read32(command + offsetof(scsi_write10_t, lba)); @@ -141,14 +140,12 @@ static inline uint32_t rdwr10_get_lba(uint8_t const command[]) return tu_ntohl(lba); } -static inline uint16_t rdwr10_get_blockcount(msc_cbw_t const* cbw) -{ +static inline uint16_t rdwr10_get_blockcount(msc_cbw_t const* cbw) { uint16_t const block_count = tu_unaligned_read16(cbw->command + offsetof(scsi_write10_t, block_count)); return tu_ntohs(block_count); } -static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) -{ +static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) { // first extract block count in the command uint16_t const block_count = rdwr10_get_blockcount(cbw); @@ -158,40 +155,28 @@ static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) return (uint16_t) (cbw->total_bytes / block_count); } -uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) -{ +uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) { uint8_t status = MSC_CSW_STATUS_PASSED; uint16_t const block_count = rdwr10_get_blockcount(cbw); - if ( cbw->total_bytes == 0 ) - { - if ( block_count ) - { + if (cbw->total_bytes == 0) { + if (block_count) { TU_LOG_DRV(" SCSI case 2 (Hn < Di) or case 3 (Hn < Do) \r\n"); status = MSC_CSW_STATUS_PHASE_ERROR; - }else - { + } else { // no data transfer, only exist in complaint test suite } - }else - { - if ( SCSI_CMD_READ_10 == cbw->command[0] && !is_data_in(cbw->dir) ) - { + } else { + if (SCSI_CMD_READ_10 == cbw->command[0] && !is_data_in(cbw->dir)) { TU_LOG_DRV(" SCSI case 10 (Ho <> Di)\r\n"); status = MSC_CSW_STATUS_PHASE_ERROR; - } - else if ( SCSI_CMD_WRITE_10 == cbw->command[0] && is_data_in(cbw->dir) ) - { + } else if (SCSI_CMD_WRITE_10 == cbw->command[0] && is_data_in(cbw->dir)) { TU_LOG_DRV(" SCSI case 8 (Hi <> Do)\r\n"); status = MSC_CSW_STATUS_PHASE_ERROR; - } - else if ( 0 == block_count ) - { + } else if (0 == block_count) { TU_LOG_DRV(" SCSI case 4 Hi > Dn (READ10) or case 9 Ho > Dn (WRITE10) \r\n"); - status = MSC_CSW_STATUS_FAILED; - } - else if ( cbw->total_bytes / block_count == 0 ) - { + status = MSC_CSW_STATUS_FAILED; + } else if (cbw->total_bytes / block_count == 0) { TU_LOG_DRV(" Computed block size = 0. SCSI case 7 Hi < Di (READ10) or case 13 Ho < Do (WRIT10)\r\n"); status = MSC_CSW_STATUS_PHASE_ERROR; } @@ -205,8 +190,7 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG >= CFG_TUD_MSC_LOG_LEVEL -TU_ATTR_UNUSED tu_static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = -{ +TU_ATTR_UNUSED tu_static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = { { .key = SCSI_CMD_TEST_UNIT_READY , .data = "Test Unit Ready" }, { .key = SCSI_CMD_INQUIRY , .data = "Inquiry" }, { .key = SCSI_CMD_MODE_SELECT_6 , .data = "Mode_Select 6" }, @@ -220,8 +204,7 @@ TU_ATTR_UNUSED tu_static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = { .key = SCSI_CMD_WRITE_10 , .data = "Write10" } }; -TU_ATTR_UNUSED tu_static tu_lookup_table_t const _msc_scsi_cmd_table = -{ +TU_ATTR_UNUSED tu_static tu_lookup_table_t const _msc_scsi_cmd_table = { .count = TU_ARRAY_SIZE(_msc_scsi_cmd_lookup), .items = _msc_scsi_cmd_lookup }; @@ -462,7 +445,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // 2. IN & Zero: Process if is built-in, else Invoke app callback. Skip DATA if zero length if ( (p_cbw->total_bytes > 0 ) && !is_data_in(p_cbw->dir) ) { - if (p_cbw->total_bytes > sizeof(_mscd_buf)) + if (p_cbw->total_bytes > CFG_TUD_MSC_EP_BUFSIZE) { TU_LOG_DRV(" SCSI reject non READ10/WRITE10 with large data\r\n"); fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); @@ -470,17 +453,17 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t { // Didn't check for case 9 (Ho > Dn), which requires examining scsi command first // but it is OK to just receive data then responded with failed status - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, (uint16_t) p_msc->total_len) ); + TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, p_msc->ep_buf, (uint16_t) p_msc->total_len) ); } }else { // First process if it is a built-in commands - int32_t resplen = proc_builtin_scsi(p_cbw->lun, p_cbw->command, _mscd_buf, sizeof(_mscd_buf)); + int32_t resplen = proc_builtin_scsi(p_cbw->lun, p_cbw->command, p_msc->ep_buf, CFG_TUD_MSC_EP_BUFSIZE); // Invoke user callback if not built-in if ( (resplen < 0) && (p_msc->sense_key == 0) ) { - resplen = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, (uint16_t) p_msc->total_len); + resplen = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, p_msc->ep_buf, (uint16_t) p_msc->total_len); } if ( resplen < 0 ) @@ -513,7 +496,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t { // cannot return more than host expect p_msc->total_len = tu_min32((uint32_t) resplen, p_cbw->total_bytes); - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_buf, (uint16_t) p_msc->total_len) ); + TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, p_msc->ep_buf, (uint16_t) p_msc->total_len) ); } } } @@ -522,7 +505,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t case MSC_STAGE_DATA: TU_LOG_DRV(" SCSI Data [Lun%u]\r\n", p_cbw->lun); - //TU_LOG_MEM(MSC_DEBUG, _mscd_buf, xferred_bytes, 2); + //TU_LOG_MEM(MSC_DEBUG, p_msc->ep_buf, xferred_bytes, 2); if (SCSI_CMD_READ_10 == p_cbw->command[0]) { @@ -548,7 +531,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // OUT transfer, invoke callback if needed if ( !is_data_in(p_cbw->dir) ) { - int32_t cb_result = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, (uint16_t) p_msc->total_len); + int32_t cb_result = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, p_msc->ep_buf, (uint16_t) p_msc->total_len); if ( cb_result < 0 ) { @@ -861,11 +844,11 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz); // remaining bytes capped at class buffer - int32_t nbytes = (int32_t) tu_min32(sizeof(_mscd_buf), p_cbw->total_bytes-p_msc->xferred_len); + int32_t nbytes = (int32_t) tu_min32(CFG_TUD_MSC_EP_BUFSIZE, p_cbw->total_bytes-p_msc->xferred_len); // Application can consume smaller bytes uint32_t const offset = p_msc->xferred_len % block_sz; - nbytes = tud_msc_read10_cb(p_cbw->lun, lba, offset, _mscd_buf, (uint32_t) nbytes); + nbytes = tud_msc_read10_cb(p_cbw->lun, lba, offset, p_msc->ep_buf, (uint32_t) nbytes); if ( nbytes < 0 ) { @@ -884,7 +867,7 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) } else { - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_buf, (uint16_t) nbytes), ); + TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, p_msc->ep_buf, (uint16_t) nbytes), ); } } @@ -908,10 +891,10 @@ static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc) } // remaining bytes capped at class buffer - uint16_t nbytes = (uint16_t) tu_min32(sizeof(_mscd_buf), p_cbw->total_bytes-p_msc->xferred_len); + uint16_t nbytes = (uint16_t) tu_min32(CFG_TUD_MSC_EP_BUFSIZE, p_cbw->total_bytes-p_msc->xferred_len); // Write10 callback will be called later when usb transfer complete - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, nbytes), ); + TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, p_msc->ep_buf, nbytes), ); } // process new data arrived from WRITE10 @@ -927,7 +910,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 // Invoke callback to consume new data uint32_t const offset = p_msc->xferred_len % block_sz; - int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, offset, _mscd_buf, xferred_bytes); + int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, offset, p_msc->ep_buf, xferred_bytes); if ( nbytes < 0 ) { @@ -950,7 +933,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 if ( nbytes > 0 ) { p_msc->xferred_len += (uint16_t) nbytes; - memmove(_mscd_buf, _mscd_buf+nbytes, left_over); + memmove(p_msc->ep_buf, p_msc->ep_buf+nbytes, left_over); } // simulate an transfer complete with adjusted parameters --> callback will be invoked with adjusted parameter diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 59cc0fb48..416bad296 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -58,6 +58,9 @@ // Generate a mask with bit from high (31) to low (0) set, e.g TU_GENMASK(3, 0) = 0b1111 #define TU_GENMASK(h, l) ( (UINT32_MAX << (l)) & (UINT32_MAX >> (31 - (h))) ) +// DCache padding for variable to occupy full cache line +#define TUD_DCACHE_PADDING uint8_t TU_XSTRCAT(dcache_padding_, _TU_COUNTER_)[CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1] + //--------------------------------------------------------------------+ // Includes //--------------------------------------------------------------------+ diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h index 646c22b29..9b33a6f61 100644 --- a/src/common/tusb_compiler.h +++ b/src/common/tusb_compiler.h @@ -136,7 +136,7 @@ #define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name))) #define TU_ATTR_PACKED __attribute__ ((packed)) #define TU_ATTR_WEAK __attribute__ ((weak)) - // #define TU_ATTR_WEAK_ALIAS(f) __attribute__ ((weak, alias(#f)) + // #define TU_ATTR_WEAK_ALIAS(f) __attribute__ ((weak, alias(#f))) #ifndef TU_ATTR_ALWAYS_INLINE // allow to override for debug #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline)) #endif @@ -189,6 +189,7 @@ #define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name))) #define TU_ATTR_PACKED __attribute__ ((packed)) #define TU_ATTR_WEAK __attribute__ ((weak)) + // #define TU_ATTR_WEAK_ALIAS(f) __attribute__ ((weak, alias(#f))) #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline)) #define TU_ATTR_DEPRECATED(mess) __attribute__ ((deprecated(mess))) // warn if function with this attribute is used #define TU_ATTR_UNUSED __attribute__ ((unused)) // Function/Variable is meant to be possibly unused @@ -216,6 +217,7 @@ #define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name))) #define TU_ATTR_PACKED __attribute__ ((packed)) #define TU_ATTR_WEAK __attribute__ ((weak)) + // #define TU_ATTR_WEAK_ALIAS(f) __attribute__ ((weak, alias(#f))) #ifndef TU_ATTR_ALWAYS_INLINE // allow to override for debug #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline)) #endif @@ -244,6 +246,7 @@ #define TU_ATTR_SECTION(sec_name) #define TU_ATTR_PACKED #define TU_ATTR_WEAK + // #define TU_ATTR_WEAK_ALIAS(f) #define TU_ATTR_ALWAYS_INLINE #define TU_ATTR_DEPRECATED(mess) #define TU_ATTR_UNUSED diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index b1fd357aa..59c66eb1e 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -54,6 +54,10 @@ enum { }; typedef struct { + union { + CFG_TUD_MEM_ALIGN uint8_t ep_buf[CFG_TUD_ENDPOINT0_SIZE]; + TUD_DCACHE_PADDING; + }; tusb_control_request_t request; uint8_t* buffer; uint16_t data_len; @@ -61,17 +65,14 @@ typedef struct { usbd_control_xfer_cb_t complete_cb; } usbd_control_xfer_t; -tu_static usbd_control_xfer_t _ctrl_xfer; - -CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN -tu_static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE]; +CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN static usbd_control_xfer_t _ctrl_xfer; //--------------------------------------------------------------------+ // Application API //--------------------------------------------------------------------+ // Queue ZLP status transaction -static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t const* request) { +static inline bool status_stage_xact(uint8_t rhport, tusb_control_request_t const* request) { // Opposite to endpoint in Data Phase uint8_t const ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN; return usbd_edpt_xfer(rhport, ep_addr, NULL, 0); @@ -84,13 +85,13 @@ bool tud_control_status(uint8_t rhport, tusb_control_request_t const* request) { _ctrl_xfer.total_xferred = 0; _ctrl_xfer.data_len = 0; - return _status_stage_xact(rhport, request); + return status_stage_xact(rhport, request); } // Queue a transaction in Data Stage // Each transaction has up to Endpoint0's max packet size. // This function can also transfer an zero-length packet -static bool _data_stage_xact(uint8_t rhport) { +static bool data_stage_xact(uint8_t rhport) { uint16_t const xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred, CFG_TUD_ENDPOINT0_SIZE); @@ -99,11 +100,11 @@ static bool _data_stage_xact(uint8_t rhport) { if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN) { ep_addr = EDPT_CTRL_IN; if (xact_len) { - TU_VERIFY(0 == tu_memcpy_s(_usbd_ctrl_buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len)); + TU_VERIFY(0 == tu_memcpy_s(_ctrl_xfer.ep_buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len)); } } - return usbd_edpt_xfer(rhport, ep_addr, xact_len ? _usbd_ctrl_buf : NULL, xact_len); + return usbd_edpt_xfer(rhport, ep_addr, xact_len ? _ctrl_xfer.ep_buf : NULL, xact_len); } // Transmit data to/from the control endpoint. @@ -122,10 +123,10 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const* request, voi // TU_LOG2(" Control total data length is %u bytes\r\n", _ctrl_xfer.data_len); // Data stage - TU_ASSERT(_data_stage_xact(rhport)); + TU_ASSERT(data_stage_xact(rhport)); } else { // Status stage - TU_ASSERT(_status_stage_xact(rhport, request)); + TU_ASSERT(status_stage_xact(rhport, request)); } return true; @@ -179,7 +180,7 @@ bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT) { TU_VERIFY(_ctrl_xfer.buffer); - memcpy(_ctrl_xfer.buffer, _usbd_ctrl_buf, xferred_bytes); + memcpy(_ctrl_xfer.buffer, _ctrl_xfer.ep_buf, xferred_bytes); TU_LOG_MEM(CFG_TUD_LOG_LEVEL, _usbd_ctrl_buf, xferred_bytes, 2); } @@ -205,7 +206,7 @@ bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, if (is_ok) { // Send status - TU_ASSERT(_status_stage_xact(rhport, &_ctrl_xfer.request)); + TU_ASSERT(status_stage_xact(rhport, &_ctrl_xfer.request)); } else { // Stall both IN and OUT control endpoint dcd_edpt_stall(rhport, EDPT_CTRL_OUT); @@ -213,7 +214,7 @@ bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, } } else { // More data to transfer - TU_ASSERT(_data_stage_xact(rhport)); + TU_ASSERT(data_stage_xact(rhport)); } return true; diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 363c77761..f2eb80e12 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -58,11 +58,9 @@ static xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir]) typedef struct { - CFG_TUD_MEM_ALIGN union { - uint32_t setup_packet[2]; -#if CFG_TUD_MEM_DCACHE_ENABLE - uint8_t setup_packet_cache_padding[CFG_TUD_MEM_DCACHE_LINE_SIZE]; -#endif + union { + CFG_TUD_MEM_ALIGN uint32_t setup_packet[2]; + TUD_DCACHE_PADDING; }; // EP0 transfers are limited to 1 packet - larger sizes has to be split diff --git a/src/tusb_option.h b/src/tusb_option.h index 500d74903..1c8e8aff4 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -252,11 +252,7 @@ #define CFG_TUD_DWC2_SLAVE_ENABLE 1 #endif -// DWC2 controller: use DMA for data transfer -// For processors with data cache enabled, USB endpoint buffer region -// (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable. -// For example, on Cortex-M7 the MPU region can be configured as normal -// non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0. +// Enable DWC2 DMA for device #ifndef CFG_TUD_DWC2_DMA_ENABLE #define CFG_TUD_DWC2_DMA_ENABLE 0 #endif diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json index b6c9b540a..8b4ef6d3a 100644 --- a/test/hil/tinyusb.json +++ b/test/hil/tinyusb.json @@ -3,6 +3,9 @@ { "name": "espressif_p4_function_ev", "uid": "6055F9F98715", + "build" : { + "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE"] + }, "tests": { "only": ["device/cdc_msc_freertos", "device/hid_composite_freertos", "host/device_info"], "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002427"}] -- cgit v1.3.1 From dbdc5a239c42e96eeeb8759a121798fa9b3f39c3 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 21 Nov 2024 17:49:38 +0700 Subject: - move freertos_hooks to board.c - add device/midi_test_freertos example - update bth/dfu/midi device for cache line size --- .../audio_4_channel_mic_freertos/CMakeLists.txt | 1 - .../device/audio_4_channel_mic_freertos/Makefile | 1 - .../src/freertos_hook.c | 115 ---------- examples/device/audio_test_freertos/CMakeLists.txt | 1 - examples/device/audio_test_freertos/Makefile | 1 - .../device/audio_test_freertos/src/freertos_hook.c | 115 ---------- examples/device/cdc_msc_freertos/CMakeLists.txt | 1 - examples/device/cdc_msc_freertos/Makefile | 1 - .../device/cdc_msc_freertos/src/freertos_hook.c | 115 ---------- examples/device/cdc_msc_freertos/src/main.c | 23 +- .../device/hid_composite_freertos/CMakeLists.txt | 1 - examples/device/hid_composite_freertos/Makefile | 1 - .../hid_composite_freertos/src/freertos_hook.c | 115 ---------- examples/device/midi_test/CMakeLists.txt | 12 +- examples/device/midi_test/src/main.c | 39 ++-- examples/device/midi_test/src/usb_descriptors.c | 34 ++- examples/device/midi_test_freertos/CMakeLists.txt | 33 +++ examples/device/midi_test_freertos/Makefile | 25 +++ .../device/midi_test_freertos/src/CMakeLists.txt | 4 + examples/device/midi_test_freertos/src/main.c | 239 +++++++++++++++++++++ .../device/midi_test_freertos/src/tusb_config.h | 108 ++++++++++ .../midi_test_freertos/src/usb_descriptors.c | 199 +++++++++++++++++ hw/bsp/board.c | 88 ++++++++ .../boards/espressif_p4_function_ev/board.h | 2 +- src/class/bth/bth_device.c | 10 +- src/class/dfu/dfu_device.c | 11 +- src/class/dfu/dfu_rt_device.c | 5 +- src/class/midi/midi_device.c | 22 +- src/common/tusb_mcu.h | 5 + src/tusb_option.h | 6 +- 30 files changed, 778 insertions(+), 555 deletions(-) delete mode 100644 examples/device/audio_4_channel_mic_freertos/src/freertos_hook.c delete mode 100644 examples/device/audio_test_freertos/src/freertos_hook.c delete mode 100644 examples/device/cdc_msc_freertos/src/freertos_hook.c delete mode 100644 examples/device/hid_composite_freertos/src/freertos_hook.c create mode 100644 examples/device/midi_test_freertos/CMakeLists.txt create mode 100644 examples/device/midi_test_freertos/Makefile create mode 100644 examples/device/midi_test_freertos/src/CMakeLists.txt create mode 100644 examples/device/midi_test_freertos/src/main.c create mode 100644 examples/device/midi_test_freertos/src/tusb_config.h create mode 100644 examples/device/midi_test_freertos/src/usb_descriptors.c (limited to 'hw') diff --git a/examples/device/audio_4_channel_mic_freertos/CMakeLists.txt b/examples/device/audio_4_channel_mic_freertos/CMakeLists.txt index e8ca3751d..285d4490b 100644 --- a/examples/device/audio_4_channel_mic_freertos/CMakeLists.txt +++ b/examples/device/audio_4_channel_mic_freertos/CMakeLists.txt @@ -19,7 +19,6 @@ add_executable(${PROJECT}) # Example source target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src/freertos_hook.c ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c ) diff --git a/examples/device/audio_4_channel_mic_freertos/Makefile b/examples/device/audio_4_channel_mic_freertos/Makefile index df2cdef4e..0202f631c 100644 --- a/examples/device/audio_4_channel_mic_freertos/Makefile +++ b/examples/device/audio_4_channel_mic_freertos/Makefile @@ -12,7 +12,6 @@ INC += \ # Example source EXAMPLE_SOURCE = \ - src/freertos_hook.c \ src/main.c \ src/usb_descriptors.c diff --git a/examples/device/audio_4_channel_mic_freertos/src/freertos_hook.c b/examples/device/audio_4_channel_mic_freertos/src/freertos_hook.c deleted file mode 100644 index 4920e3fae..000000000 --- a/examples/device/audio_4_channel_mic_freertos/src/freertos_hook.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - */ - -//--------------------------------------------------------------------+ -// INCLUDE -//--------------------------------------------------------------------+ -#include "FreeRTOS.h" -#include "task.h" -#include "common/tusb_common.h" - - -void vApplicationMallocFailedHook(void) -{ - taskDISABLE_INTERRUPTS(); - TU_ASSERT(false, ); -} - -void vApplicationStackOverflowHook(xTaskHandle pxTask, char *pcTaskName) -{ - (void) pxTask; - (void) pcTaskName; - - taskDISABLE_INTERRUPTS(); - TU_ASSERT(false, ); -} - -/* configSUPPORT_STATIC_ALLOCATION is set to 1, so the application must provide an - * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is - * used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) -{ - /* If the buffers to be provided to the Idle task are declared inside this - * function then they must be declared static - otherwise they will be allocated on - * the stack and so not exists after this function exits. */ - static StaticTask_t xIdleTaskTCB; - static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; -} - -/* configSUPPORT_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the - * application must provide an implementation of vApplicationGetTimerTaskMemory() - * to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) -{ - /* If the buffers to be provided to the Timer task are declared inside this - * function then they must be declared static - otherwise they will be allocated on - * the stack and so not exists after this function exits. */ - static StaticTask_t xTimerTaskTCB; - static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; -} - -#if CFG_TUSB_MCU == OPT_MCU_RX63X | CFG_TUSB_MCU == OPT_MCU_RX65X -#include "iodefine.h" -void vApplicationSetupTimerInterrupt(void) -{ - /* Enable CMT0 */ - unsigned short oldPRCR = SYSTEM.PRCR.WORD; - SYSTEM.PRCR.WORD = (0xA5u<<8) | TU_BIT(1); - MSTP(CMT0) = 0; - SYSTEM.PRCR.WORD = (0xA5u<<8) | oldPRCR; - - CMT0.CMCNT = 0; - CMT0.CMCOR = (unsigned short)(((configPERIPHERAL_CLOCK_HZ/configTICK_RATE_HZ)-1)/128); - CMT0.CMCR.WORD = TU_BIT(6) | 2; - IR(CMT0, CMI0) = 0; - IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY; - IEN(CMT0, CMI0) = 1; - CMT.CMSTR0.BIT.STR0 = 1; -} -#endif diff --git a/examples/device/audio_test_freertos/CMakeLists.txt b/examples/device/audio_test_freertos/CMakeLists.txt index eb22014fb..33f3b915f 100644 --- a/examples/device/audio_test_freertos/CMakeLists.txt +++ b/examples/device/audio_test_freertos/CMakeLists.txt @@ -19,7 +19,6 @@ add_executable(${PROJECT}) # Example source target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src/freertos_hook.c ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c ) diff --git a/examples/device/audio_test_freertos/Makefile b/examples/device/audio_test_freertos/Makefile index df2cdef4e..0202f631c 100644 --- a/examples/device/audio_test_freertos/Makefile +++ b/examples/device/audio_test_freertos/Makefile @@ -12,7 +12,6 @@ INC += \ # Example source EXAMPLE_SOURCE = \ - src/freertos_hook.c \ src/main.c \ src/usb_descriptors.c diff --git a/examples/device/audio_test_freertos/src/freertos_hook.c b/examples/device/audio_test_freertos/src/freertos_hook.c deleted file mode 100644 index 4920e3fae..000000000 --- a/examples/device/audio_test_freertos/src/freertos_hook.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - */ - -//--------------------------------------------------------------------+ -// INCLUDE -//--------------------------------------------------------------------+ -#include "FreeRTOS.h" -#include "task.h" -#include "common/tusb_common.h" - - -void vApplicationMallocFailedHook(void) -{ - taskDISABLE_INTERRUPTS(); - TU_ASSERT(false, ); -} - -void vApplicationStackOverflowHook(xTaskHandle pxTask, char *pcTaskName) -{ - (void) pxTask; - (void) pcTaskName; - - taskDISABLE_INTERRUPTS(); - TU_ASSERT(false, ); -} - -/* configSUPPORT_STATIC_ALLOCATION is set to 1, so the application must provide an - * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is - * used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) -{ - /* If the buffers to be provided to the Idle task are declared inside this - * function then they must be declared static - otherwise they will be allocated on - * the stack and so not exists after this function exits. */ - static StaticTask_t xIdleTaskTCB; - static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; -} - -/* configSUPPORT_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the - * application must provide an implementation of vApplicationGetTimerTaskMemory() - * to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) -{ - /* If the buffers to be provided to the Timer task are declared inside this - * function then they must be declared static - otherwise they will be allocated on - * the stack and so not exists after this function exits. */ - static StaticTask_t xTimerTaskTCB; - static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; -} - -#if CFG_TUSB_MCU == OPT_MCU_RX63X | CFG_TUSB_MCU == OPT_MCU_RX65X -#include "iodefine.h" -void vApplicationSetupTimerInterrupt(void) -{ - /* Enable CMT0 */ - unsigned short oldPRCR = SYSTEM.PRCR.WORD; - SYSTEM.PRCR.WORD = (0xA5u<<8) | TU_BIT(1); - MSTP(CMT0) = 0; - SYSTEM.PRCR.WORD = (0xA5u<<8) | oldPRCR; - - CMT0.CMCNT = 0; - CMT0.CMCOR = (unsigned short)(((configPERIPHERAL_CLOCK_HZ/configTICK_RATE_HZ)-1)/128); - CMT0.CMCR.WORD = TU_BIT(6) | 2; - IR(CMT0, CMI0) = 0; - IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY; - IEN(CMT0, CMI0) = 1; - CMT.CMSTR0.BIT.STR0 = 1; -} -#endif diff --git a/examples/device/cdc_msc_freertos/CMakeLists.txt b/examples/device/cdc_msc_freertos/CMakeLists.txt index 33c7a1ec0..32a9e2930 100644 --- a/examples/device/cdc_msc_freertos/CMakeLists.txt +++ b/examples/device/cdc_msc_freertos/CMakeLists.txt @@ -19,7 +19,6 @@ add_executable(${PROJECT}) # Example source target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src/freertos_hook.c ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c diff --git a/examples/device/cdc_msc_freertos/Makefile b/examples/device/cdc_msc_freertos/Makefile index fe3fb6482..c90922b0c 100644 --- a/examples/device/cdc_msc_freertos/Makefile +++ b/examples/device/cdc_msc_freertos/Makefile @@ -12,7 +12,6 @@ INC += \ # Example source EXAMPLE_SOURCE = \ - src/freertos_hook.c \ src/main.c \ src/msc_disk.c \ src/usb_descriptors.c diff --git a/examples/device/cdc_msc_freertos/src/freertos_hook.c b/examples/device/cdc_msc_freertos/src/freertos_hook.c deleted file mode 100644 index 4920e3fae..000000000 --- a/examples/device/cdc_msc_freertos/src/freertos_hook.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - */ - -//--------------------------------------------------------------------+ -// INCLUDE -//--------------------------------------------------------------------+ -#include "FreeRTOS.h" -#include "task.h" -#include "common/tusb_common.h" - - -void vApplicationMallocFailedHook(void) -{ - taskDISABLE_INTERRUPTS(); - TU_ASSERT(false, ); -} - -void vApplicationStackOverflowHook(xTaskHandle pxTask, char *pcTaskName) -{ - (void) pxTask; - (void) pcTaskName; - - taskDISABLE_INTERRUPTS(); - TU_ASSERT(false, ); -} - -/* configSUPPORT_STATIC_ALLOCATION is set to 1, so the application must provide an - * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is - * used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) -{ - /* If the buffers to be provided to the Idle task are declared inside this - * function then they must be declared static - otherwise they will be allocated on - * the stack and so not exists after this function exits. */ - static StaticTask_t xIdleTaskTCB; - static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; -} - -/* configSUPPORT_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the - * application must provide an implementation of vApplicationGetTimerTaskMemory() - * to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) -{ - /* If the buffers to be provided to the Timer task are declared inside this - * function then they must be declared static - otherwise they will be allocated on - * the stack and so not exists after this function exits. */ - static StaticTask_t xTimerTaskTCB; - static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; -} - -#if CFG_TUSB_MCU == OPT_MCU_RX63X | CFG_TUSB_MCU == OPT_MCU_RX65X -#include "iodefine.h" -void vApplicationSetupTimerInterrupt(void) -{ - /* Enable CMT0 */ - unsigned short oldPRCR = SYSTEM.PRCR.WORD; - SYSTEM.PRCR.WORD = (0xA5u<<8) | TU_BIT(1); - MSTP(CMT0) = 0; - SYSTEM.PRCR.WORD = (0xA5u<<8) | oldPRCR; - - CMT0.CMCNT = 0; - CMT0.CMCOR = (unsigned short)(((configPERIPHERAL_CLOCK_HZ/configTICK_RATE_HZ)-1)/128); - CMT0.CMCR.WORD = TU_BIT(6) | 2; - IR(CMT0, CMI0) = 0; - IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY; - IEN(CMT0, CMI0) = 1; - CMT.CMSTR0.BIT.STR0 = 1; -} -#endif diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index a05ceff58..c51e8ea81 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -31,23 +31,8 @@ #include "tusb.h" #if TUSB_MCU_VENDOR_ESPRESSIF - // ESP-IDF need "freertos/" prefix in include path. - // CFG_TUSB_OS_INC_PATH should be defined accordingly. - #include "freertos/FreeRTOS.h" - #include "freertos/semphr.h" - #include "freertos/queue.h" - #include "freertos/task.h" - #include "freertos/timers.h" - #define USBD_STACK_SIZE 4096 #else - - #include "FreeRTOS.h" - #include "semphr.h" - #include "queue.h" - #include "task.h" - #include "timers.h" - // Increase stack size when debug log is enabled #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1) #endif @@ -95,14 +80,10 @@ void cdc_task(void *params); int main(void) { board_init(); + // Create task for: tinyusb, blinky, cdc #if configSUPPORT_STATIC_ALLOCATION - // blinky task xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef); - - // Create a task for tinyusb device stack xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef); - - // Create CDC task xTaskCreateStatic(cdc_task, "cdc", CDC_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, cdc_stack, &cdc_taskdef); #else xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL); @@ -110,8 +91,8 @@ int main(void) { xTaskCreate(cdc_task, "cdc", CDC_STACK_SZIE, NULL, configMAX_PRIORITIES - 2, NULL); #endif - // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 #if !TUSB_MCU_VENDOR_ESPRESSIF + // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 vTaskStartScheduler(); #endif diff --git a/examples/device/hid_composite_freertos/CMakeLists.txt b/examples/device/hid_composite_freertos/CMakeLists.txt index eb22014fb..33f3b915f 100644 --- a/examples/device/hid_composite_freertos/CMakeLists.txt +++ b/examples/device/hid_composite_freertos/CMakeLists.txt @@ -19,7 +19,6 @@ add_executable(${PROJECT}) # Example source target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src/freertos_hook.c ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c ) diff --git a/examples/device/hid_composite_freertos/Makefile b/examples/device/hid_composite_freertos/Makefile index 88d602393..38d842b3a 100644 --- a/examples/device/hid_composite_freertos/Makefile +++ b/examples/device/hid_composite_freertos/Makefile @@ -14,7 +14,6 @@ INC += \ # Example source EXAMPLE_SOURCE = \ - src/freertos_hook.c \ src/main.c \ src/usb_descriptors.c diff --git a/examples/device/hid_composite_freertos/src/freertos_hook.c b/examples/device/hid_composite_freertos/src/freertos_hook.c deleted file mode 100644 index 4920e3fae..000000000 --- a/examples/device/hid_composite_freertos/src/freertos_hook.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2019 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - */ - -//--------------------------------------------------------------------+ -// INCLUDE -//--------------------------------------------------------------------+ -#include "FreeRTOS.h" -#include "task.h" -#include "common/tusb_common.h" - - -void vApplicationMallocFailedHook(void) -{ - taskDISABLE_INTERRUPTS(); - TU_ASSERT(false, ); -} - -void vApplicationStackOverflowHook(xTaskHandle pxTask, char *pcTaskName) -{ - (void) pxTask; - (void) pcTaskName; - - taskDISABLE_INTERRUPTS(); - TU_ASSERT(false, ); -} - -/* configSUPPORT_STATIC_ALLOCATION is set to 1, so the application must provide an - * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is - * used by the Idle task. */ -void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) -{ - /* If the buffers to be provided to the Idle task are declared inside this - * function then they must be declared static - otherwise they will be allocated on - * the stack and so not exists after this function exits. */ - static StaticTask_t xIdleTaskTCB; - static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Idle task's - state will be stored. */ - *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; - - /* Pass out the array that will be used as the Idle task's stack. */ - *ppxIdleTaskStackBuffer = uxIdleTaskStack; - - /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configMINIMAL_STACK_SIZE is specified in words, not bytes. */ - *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; -} - -/* configSUPPORT_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the - * application must provide an implementation of vApplicationGetTimerTaskMemory() - * to provide the memory that is used by the Timer service task. */ -void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) -{ - /* If the buffers to be provided to the Timer task are declared inside this - * function then they must be declared static - otherwise they will be allocated on - * the stack and so not exists after this function exits. */ - static StaticTask_t xTimerTaskTCB; - static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; - - /* Pass out a pointer to the StaticTask_t structure in which the Timer - task's state will be stored. */ - *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; - - /* Pass out the array that will be used as the Timer task's stack. */ - *ppxTimerTaskStackBuffer = uxTimerTaskStack; - - /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. - Note that, as the array is necessarily of type StackType_t, - configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */ - *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; -} - -#if CFG_TUSB_MCU == OPT_MCU_RX63X | CFG_TUSB_MCU == OPT_MCU_RX65X -#include "iodefine.h" -void vApplicationSetupTimerInterrupt(void) -{ - /* Enable CMT0 */ - unsigned short oldPRCR = SYSTEM.PRCR.WORD; - SYSTEM.PRCR.WORD = (0xA5u<<8) | TU_BIT(1); - MSTP(CMT0) = 0; - SYSTEM.PRCR.WORD = (0xA5u<<8) | oldPRCR; - - CMT0.CMCNT = 0; - CMT0.CMCOR = (unsigned short)(((configPERIPHERAL_CLOCK_HZ/configTICK_RATE_HZ)-1)/128); - CMT0.CMCR.WORD = TU_BIT(6) | 2; - IR(CMT0, CMI0) = 0; - IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY; - IEN(CMT0, CMI0) = 1; - CMT.CMSTR0.BIT.STR0 = 1; -} -#endif diff --git a/examples/device/midi_test/CMakeLists.txt b/examples/device/midi_test/CMakeLists.txt index e51f14c02..f61e1b640 100644 --- a/examples/device/midi_test/CMakeLists.txt +++ b/examples/device/midi_test/CMakeLists.txt @@ -9,22 +9,24 @@ project(${PROJECT} C CXX ASM) # Checks this example is valid for the family and initializes the project family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) + # Espressif has its own cmake build system if(FAMILY STREQUAL "espressif") return() endif() add_executable(${PROJECT}) + # Example source target_sources(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c - ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c + ) # Example include target_include_directories(${PROJECT} PUBLIC - ${CMAKE_CURRENT_SOURCE_DIR}/src - ) + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) # Configure compilation flags and libraries for the example without RTOS. # See the corresponding function in hw/bsp/FAMILY/family.cmake for details. diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c index d7849a2c4..e5c47bdb2 100644 --- a/examples/device/midi_test/src/main.c +++ b/examples/device/midi_test/src/main.c @@ -58,8 +58,7 @@ void led_blinking_task(void); void midi_task(void); /*------------- MAIN -------------*/ -int main(void) -{ +int main(void) { board_init(); // init device stack on configured roothub port @@ -73,8 +72,7 @@ int main(void) board_init_after_tusb(); } - while (1) - { + while (1) { tud_task(); // tinyusb device task led_blinking_task(); midi_task(); @@ -86,29 +84,25 @@ int main(void) //--------------------------------------------------------------------+ // Invoked when device is mounted -void tud_mount_cb(void) -{ +void tud_mount_cb(void) { blink_interval_ms = BLINK_MOUNTED; } // Invoked when device is unmounted -void tud_umount_cb(void) -{ +void tud_umount_cb(void) { blink_interval_ms = BLINK_NOT_MOUNTED; } // Invoked when usb bus is suspended // remote_wakeup_en : if host allow us to perform remote wakeup // Within 7ms, device must draw an average of current less than 2.5 mA from bus -void tud_suspend_cb(bool remote_wakeup_en) -{ +void tud_suspend_cb(bool remote_wakeup_en) { (void) remote_wakeup_en; blink_interval_ms = BLINK_SUSPENDED; } // Invoked when usb bus is resumed -void tud_resume_cb(void) -{ +void tud_resume_cb(void) { blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED; } @@ -120,8 +114,7 @@ void tud_resume_cb(void) uint32_t note_pos = 0; // Store example melody as an array of note values -uint8_t note_sequence[] = -{ +const uint8_t note_sequence[] = { 74,78,81,86,90,93,98,102,57,61,66,69,73,78,81,85,88,92,97,100,97,92,88,85,81,78, 74,69,66,62,57,62,66,69,74,78,81,86,90,93,97,102,97,93,90,85,81,78,73,68,64,61, 56,61,64,68,74,78,81,86,90,93,98,102 @@ -137,11 +130,15 @@ void midi_task(void) // The MIDI interface always creates input and output port/jack descriptors // regardless of these being used or not. Therefore incoming traffic should be read // (possibly just discarded) to avoid the sender blocking in IO - uint8_t packet[4]; - while ( tud_midi_available() ) tud_midi_packet_read(packet); + while (tud_midi_available()) { + uint8_t packet[4]; + tud_midi_packet_read(packet); + } // send note periodically - if (board_millis() - start_ms < 286) return; // not enough time + if (board_millis() - start_ms < 286) { + return; // not enough time + } start_ms += 286; // Previous positions in the note sequence. @@ -149,7 +146,9 @@ void midi_task(void) // If we currently are at position 0, set the // previous position to the last note in the sequence. - if (previous < 0) previous = sizeof(note_sequence) - 1; + if (previous < 0) { + previous = sizeof(note_sequence) - 1; + } // Send Note On for current position at full velocity (127) on channel 1. uint8_t note_on[3] = { 0x90 | channel, note_sequence[note_pos], 127 }; @@ -163,7 +162,9 @@ void midi_task(void) note_pos++; // If we are at the end of the sequence, start over. - if (note_pos >= sizeof(note_sequence)) note_pos = 0; + if (note_pos >= sizeof(note_sequence)) { + note_pos = 0; + } } //--------------------------------------------------------------------+ diff --git a/examples/device/midi_test/src/usb_descriptors.c b/examples/device/midi_test/src/usb_descriptors.c index 3870eaaf0..384742ae8 100644 --- a/examples/device/midi_test/src/usb_descriptors.c +++ b/examples/device/midi_test/src/usb_descriptors.c @@ -39,8 +39,7 @@ //--------------------------------------------------------------------+ // Device Descriptors //--------------------------------------------------------------------+ -tusb_desc_device_t const desc_device = -{ +tusb_desc_device_t const desc_device = { .bLength = sizeof(tusb_desc_device_t), .bDescriptorType = TUSB_DESC_DEVICE, .bcdUSB = 0x0200, @@ -62,18 +61,13 @@ tusb_desc_device_t const desc_device = // Invoked when received GET DEVICE DESCRIPTOR // Application return pointer to descriptor -uint8_t const * tud_descriptor_device_cb(void) -{ +uint8_t const * tud_descriptor_device_cb(void) { return (uint8_t const *) &desc_device; } - - //--------------------------------------------------------------------+ // Configuration Descriptor //--------------------------------------------------------------------+ - -enum -{ +enum { ITF_NUM_MIDI = 0, ITF_NUM_MIDI_STREAMING, ITF_NUM_TOTAL @@ -104,8 +98,7 @@ enum #define EPNUM_MIDI_IN 0x81 #endif -uint8_t const desc_fs_configuration[] = -{ +uint8_t const desc_fs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), @@ -114,8 +107,7 @@ uint8_t const desc_fs_configuration[] = }; #if TUD_OPT_HIGH_SPEED -uint8_t const desc_hs_configuration[] = -{ +uint8_t const desc_hs_configuration[] = { // Config number, interface count, string index, total length, attribute, power in mA TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), @@ -127,8 +119,7 @@ uint8_t const desc_hs_configuration[] = // Invoked when received GET CONFIGURATION DESCRIPTOR // Application return pointer to descriptor // Descriptor contents must exist long enough for transfer to complete -uint8_t const * tud_descriptor_configuration_cb(uint8_t index) -{ +uint8_t const * tud_descriptor_configuration_cb(uint8_t index) { (void) index; // for multiple configurations #if TUD_OPT_HIGH_SPEED @@ -152,8 +143,7 @@ enum { }; // array of pointer to string descriptors -char const *string_desc_arr[] = -{ +char const *string_desc_arr[] = { (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409) "TinyUSB", // 1: Manufacturer "TinyUSB Device", // 2: Product @@ -182,14 +172,18 @@ uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors. // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors - if ( !(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0])) ) return NULL; + if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) { + return NULL; + } const char *str = string_desc_arr[index]; // Cap at max char chr_count = strlen(str); - size_t const max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type - if ( chr_count > max_count ) chr_count = max_count; + const size_t max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type + if ( chr_count > max_count ) { + chr_count = max_count; + } // Convert ASCII string into UTF-16 for ( size_t i = 0; i < chr_count; i++ ) { diff --git a/examples/device/midi_test_freertos/CMakeLists.txt b/examples/device/midi_test_freertos/CMakeLists.txt new file mode 100644 index 000000000..eb2f0fe21 --- /dev/null +++ b/examples/device/midi_test_freertos/CMakeLists.txt @@ -0,0 +1,33 @@ +cmake_minimum_required(VERSION 3.17) + +include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) + +# gets PROJECT name for the example (e.g. -) +family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR}) + +project(${PROJECT} C CXX ASM) + +# Checks this example is valid for the family and initializes the project +family_initialize_project(${PROJECT} ${CMAKE_CURRENT_LIST_DIR}) + +# Espressif has its own cmake build system +if(FAMILY STREQUAL "espressif") + return() +endif() + +add_executable(${PROJECT}) + +# Example source +target_sources(${PROJECT} PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c + ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c + ) + +# Example include +target_include_directories(${PROJECT} PUBLIC + ${CMAKE_CURRENT_SOURCE_DIR}/src + ) + +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +family_configure_device_example(${PROJECT} freertos) diff --git a/examples/device/midi_test_freertos/Makefile b/examples/device/midi_test_freertos/Makefile new file mode 100644 index 000000000..7d45405a2 --- /dev/null +++ b/examples/device/midi_test_freertos/Makefile @@ -0,0 +1,25 @@ +include ../../build_system/make/make.mk + +INC += \ + src \ + $(TOP)/hw \ + +# Example source +EXAMPLE_SOURCE += \ + src/main.c \ + src/usb_descriptors.c \ + +SRC_C += $(addprefix $(CURRENT_PATH)/, $(EXAMPLE_SOURCE)) + +# FreeRTOS source, all files in port folder +SRC_C += \ + $(FREERTOS_SRC)/list.c \ + $(FREERTOS_SRC)/queue.c \ + $(FREERTOS_SRC)/tasks.c \ + $(FREERTOS_SRC)/timers.c \ + $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.c)) + +SRC_S += \ + $(subst $(TOP)/,,$(wildcard $(TOP)/$(FREERTOS_PORTABLE_SRC)/*.s)) + +include ../../build_system/make/rules.mk diff --git a/examples/device/midi_test_freertos/src/CMakeLists.txt b/examples/device/midi_test_freertos/src/CMakeLists.txt new file mode 100644 index 000000000..9bd427c89 --- /dev/null +++ b/examples/device/midi_test_freertos/src/CMakeLists.txt @@ -0,0 +1,4 @@ +# This file is for ESP-IDF only +idf_component_register(SRCS main.c usb_descriptors.c + INCLUDE_DIRS "." + REQUIRES boards tinyusb_src) diff --git a/examples/device/midi_test_freertos/src/main.c b/examples/device/midi_test_freertos/src/main.c new file mode 100644 index 000000000..dbe89080c --- /dev/null +++ b/examples/device/midi_test_freertos/src/main.c @@ -0,0 +1,239 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include +#include +#include + +#include "bsp/board_api.h" +#include "tusb.h" + +/* This MIDI example send sequence of note (on/off) repeatedly. To test on PC, you need to install + * synth software and midi connection management software. On + * - Linux (Ubuntu): install qsynth, qjackctl. Then connect TinyUSB output port to FLUID Synth input port + * - Windows: install MIDI-OX + * - MacOS: SimpleSynth + */ + +//--------------------------------------------------------------------+ +// MACRO CONSTANT TYPEDEF PROTYPES +//--------------------------------------------------------------------+ +#if TUSB_MCU_VENDOR_ESPRESSIF + #define USBD_STACK_SIZE 4096 +#else + // Increase stack size when debug log is enabled + #define USBD_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1) +#endif + +#define BLINKY_STACK_SIZE configMINIMAL_STACK_SIZE +#define MIDI_STACK_SIZE configMINIMAL_STACK_SIZE + +// static task +#if configSUPPORT_STATIC_ALLOCATION +StackType_t blinky_stack[BLINKY_STACK_SIZE]; +StaticTask_t blinky_taskdef; + +StackType_t usb_device_stack[USBD_STACK_SIZE]; +StaticTask_t usb_device_taskdef; + +StackType_t midi_stack[MIDI_STACK_SIZE]; +StaticTask_t midi_taskdef; +#endif + +/* Blink pattern + * - 250 ms : device not mounted + * - 1000 ms : device mounted + * - 2500 ms : device is suspended + */ +enum { + BLINK_NOT_MOUNTED = 250, + BLINK_MOUNTED = 1000, + BLINK_SUSPENDED = 2500, +}; + +static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED; + +void usb_device_task(void *param); +void led_blinking_task(void* param); +void midi_task(void* param); + +//--------------------------------------------------------------------+ +// Main +//--------------------------------------------------------------------+ +int main(void) { + board_init(); + +#if configSUPPORT_STATIC_ALLOCATION + xTaskCreateStatic(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, blinky_stack, &blinky_taskdef); + xTaskCreateStatic(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES-1, usb_device_stack, &usb_device_taskdef); + xTaskCreateStatic(midi_task, "midi", MIDI_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, midi_stack, &midi_taskdef); +#else + xTaskCreate(led_blinking_task, "blinky", BLINKY_STACK_SIZE, NULL, 1, NULL); + xTaskCreate(usb_device_task, "usbd", USBD_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL); + xTaskCreate(midi_task, "midi", MIDI_STACK_SIZE, NULL, configMAX_PRIORITIES - 2, NULL); +#endif + +#if !TUSB_MCU_VENDOR_ESPRESSIF + // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 + vTaskStartScheduler(); +#endif + + return 0; +} + +#if TUSB_MCU_VENDOR_ESPRESSIF +void app_main(void) { + main(); +} +#endif + +// USB Device Driver task +// This top level thread process all usb events and invoke callbacks +void usb_device_task(void *param) { + (void) param; + + // init device stack on configured roothub port + // This should be called after scheduler/kernel is started. + // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. + tusb_rhport_init_t dev_init = { + .role = TUSB_ROLE_DEVICE, + .speed = TUSB_SPEED_AUTO + }; + tusb_init(BOARD_TUD_RHPORT, &dev_init); + + if (board_init_after_tusb) { + board_init_after_tusb(); + } + + // RTOS forever loop + while (1) { + // put this thread to waiting state until there is new events + tud_task(); + } +} + +//--------------------------------------------------------------------+ +// Device callbacks +//--------------------------------------------------------------------+ + +// Invoked when device is mounted +void tud_mount_cb(void) { + blink_interval_ms = BLINK_MOUNTED; +} + +// Invoked when device is unmounted +void tud_umount_cb(void) { + blink_interval_ms = BLINK_NOT_MOUNTED; +} + +// Invoked when usb bus is suspended +// remote_wakeup_en : if host allow us to perform remote wakeup +// Within 7ms, device must draw an average of current less than 2.5 mA from bus +void tud_suspend_cb(bool remote_wakeup_en) { + (void) remote_wakeup_en; + blink_interval_ms = BLINK_SUSPENDED; +} + +// Invoked when usb bus is resumed +void tud_resume_cb(void) { + blink_interval_ms = tud_mounted() ? BLINK_MOUNTED : BLINK_NOT_MOUNTED; +} + +//--------------------------------------------------------------------+ +// MIDI Task +//--------------------------------------------------------------------+ + +// Store example melody as an array of note values +const uint8_t note_sequence[] = { + 74,78,81,86,90,93,98,102,57,61,66,69,73,78,81,85,88,92,97,100,97,92,88,85,81,78, + 74,69,66,62,57,62,66,69,74,78,81,86,90,93,97,102,97,93,90,85,81,78,73,68,64,61, + 56,61,64,68,74,78,81,86,90,93,98,102 +}; + +void midi_task(void* param) { + (void) param; + + const uint8_t cable_num = 0; // MIDI jack associated with USB endpoint + const uint8_t channel = 0; // 0 for channel 1 + + // Variable that holds the current position in the sequence. + uint32_t note_pos = 0; + + while (1) { + // send note periodically + vTaskDelay(286 / portTICK_PERIOD_MS); + + // Previous positions in the note sequence. + int previous = (int) (note_pos - 1); + + // If we currently are at position 0, set the + // previous position to the last note in the sequence. + if (previous < 0) { + previous = sizeof(note_sequence) - 1; + } + + // Send Note On for current position at full velocity (127) on channel 1. + uint8_t note_on[3] = { 0x90 | channel, note_sequence[note_pos], 127 }; + tud_midi_stream_write(cable_num, note_on, 3); + + // Send Note Off for previous note. + uint8_t note_off[3] = { 0x80 | channel, note_sequence[previous], 0}; + tud_midi_stream_write(cable_num, note_off, 3); + + // Increment position + note_pos++; + + // If we are at the end of the sequence, start over. + if (note_pos >= sizeof(note_sequence)) { + note_pos = 0; + } + + // The MIDI interface always creates input and output port/jack descriptors + // regardless of these being used or not. Therefore incoming traffic should be read + // (possibly just discarded) to avoid the sender blocking in IO + while (tud_midi_available()) { + uint8_t packet[4]; + tud_midi_packet_read(packet); + } + } +} + +//--------------------------------------------------------------------+ +// BLINKING TASK +//--------------------------------------------------------------------+ +void led_blinking_task(void* param) { + (void) param; + static uint32_t start_ms = 0; + static bool led_state = false; + + while (1) { + // Blink every interval ms + vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS); + start_ms += blink_interval_ms; + + board_led_write(led_state); + led_state = 1 - led_state; // toggle + } +} diff --git a/examples/device/midi_test_freertos/src/tusb_config.h b/examples/device/midi_test_freertos/src/tusb_config.h new file mode 100644 index 000000000..314dde438 --- /dev/null +++ b/examples/device/midi_test_freertos/src/tusb_config.h @@ -0,0 +1,108 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#ifndef _TUSB_CONFIG_H_ +#define _TUSB_CONFIG_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +//--------------------------------------------------------------------+ +// Board Specific Configuration +//--------------------------------------------------------------------+ + +// RHPort number used for device can be defined by board.mk, default to port 0 +#ifndef BOARD_TUD_RHPORT +#define BOARD_TUD_RHPORT 0 +#endif + +// RHPort max operational speed can defined by board.mk +#ifndef BOARD_TUD_MAX_SPEED +#define BOARD_TUD_MAX_SPEED OPT_MODE_DEFAULT_SPEED +#endif + +//-------------------------------------------------------------------- +// COMMON CONFIGURATION +//-------------------------------------------------------------------- + +// defined by compiler flags for flexibility +#ifndef CFG_TUSB_MCU +#error CFG_TUSB_MCU must be defined +#endif + +#ifndef CFG_TUSB_OS +#define CFG_TUSB_OS OPT_OS_NONE +#endif + +#ifndef CFG_TUSB_DEBUG +#define CFG_TUSB_DEBUG 0 +#endif + +// Enable Device stack +#define CFG_TUD_ENABLED 1 + +// Default is max speed that hardware controller could support with on-chip PHY +#define CFG_TUD_MAX_SPEED BOARD_TUD_MAX_SPEED + +/* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. + * Tinyusb use follows macros to declare transferring memory so that they can be put + * into those specific section. + * e.g + * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) + * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) + */ +#ifndef CFG_TUSB_MEM_SECTION +#define CFG_TUSB_MEM_SECTION +#endif + +#ifndef CFG_TUSB_MEM_ALIGN +#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4))) +#endif + +//-------------------------------------------------------------------- +// DEVICE CONFIGURATION +//-------------------------------------------------------------------- + +#ifndef CFG_TUD_ENDPOINT0_SIZE +#define CFG_TUD_ENDPOINT0_SIZE 64 +#endif + +//------------- CLASS -------------// +#define CFG_TUD_CDC 0 +#define CFG_TUD_MSC 0 +#define CFG_TUD_HID 0 +#define CFG_TUD_MIDI 1 +#define CFG_TUD_VENDOR 0 + +// MIDI FIFO size of TX and RX +#define CFG_TUD_MIDI_RX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) +#define CFG_TUD_MIDI_TX_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64) + +#ifdef __cplusplus + } +#endif + +#endif /* _TUSB_CONFIG_H_ */ diff --git a/examples/device/midi_test_freertos/src/usb_descriptors.c b/examples/device/midi_test_freertos/src/usb_descriptors.c new file mode 100644 index 000000000..384742ae8 --- /dev/null +++ b/examples/device/midi_test_freertos/src/usb_descriptors.c @@ -0,0 +1,199 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + */ + +#include "bsp/board_api.h" +#include "tusb.h" + +/* A combination of interfaces must have a unique product id, since PC will save device driver after the first plug. + * Same VID/PID with different interface e.g MSC (first), then CDC (later) will possibly cause system error on PC. + * + * Auto ProductID layout's Bitmap: + * [MSB] HID | MSC | CDC [LSB] + */ +#define _PID_MAP(itf, n) ( (CFG_TUD_##itf) << (n) ) +#define USB_PID (0x4000 | _PID_MAP(CDC, 0) | _PID_MAP(MSC, 1) | _PID_MAP(HID, 2) | \ + _PID_MAP(MIDI, 3) | _PID_MAP(VENDOR, 4) ) + +//--------------------------------------------------------------------+ +// Device Descriptors +//--------------------------------------------------------------------+ +tusb_desc_device_t const desc_device = { + .bLength = sizeof(tusb_desc_device_t), + .bDescriptorType = TUSB_DESC_DEVICE, + .bcdUSB = 0x0200, + .bDeviceClass = 0x00, + .bDeviceSubClass = 0x00, + .bDeviceProtocol = 0x00, + .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE, + + .idVendor = 0xCafe, + .idProduct = USB_PID, + .bcdDevice = 0x0100, + + .iManufacturer = 0x01, + .iProduct = 0x02, + .iSerialNumber = 0x03, + + .bNumConfigurations = 0x01 +}; + +// Invoked when received GET DEVICE DESCRIPTOR +// Application return pointer to descriptor +uint8_t const * tud_descriptor_device_cb(void) { + return (uint8_t const *) &desc_device; +} +//--------------------------------------------------------------------+ +// Configuration Descriptor +//--------------------------------------------------------------------+ +enum { + ITF_NUM_MIDI = 0, + ITF_NUM_MIDI_STREAMING, + ITF_NUM_TOTAL +}; + +#define CONFIG_TOTAL_LEN (TUD_CONFIG_DESC_LEN + TUD_MIDI_DESC_LEN) + +#if CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX + // LPC 17xx and 40xx endpoint type (bulk/interrupt/iso) are fixed by its number + // 0 control, 1 In, 2 Bulk, 3 Iso, 4 In etc ... + #define EPNUM_MIDI_OUT 0x02 + #define EPNUM_MIDI_IN 0x82 + +#elif CFG_TUSB_MCU == OPT_MCU_CXD56 + // CXD56 USB driver has fixed endpoint type (bulk/interrupt/iso) and direction (IN/OUT) by its number + // 0 control (IN/OUT), 1 Bulk (IN), 2 Bulk (OUT), 3 In (IN), 4 Bulk (IN), 5 Bulk (OUT), 6 In (IN) + #define EPNUM_MIDI_OUT 0x02 + #define EPNUM_MIDI_IN 0x81 + +#elif defined(TUD_ENDPOINT_ONE_DIRECTION_ONLY) + // MCUs that don't support a same endpoint number with different direction IN and OUT defined in tusb_mcu.h + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_MIDI_OUT 0x01 + #define EPNUM_MIDI_IN 0x82 + +#else + #define EPNUM_MIDI_OUT 0x01 + #define EPNUM_MIDI_IN 0x81 +#endif + +uint8_t const desc_fs_configuration[] = { + // Config number, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), + + // Interface number, string index, EP Out & EP In address, EP size + TUD_MIDI_DESCRIPTOR(ITF_NUM_MIDI, 0, EPNUM_MIDI_OUT, (0x80 | EPNUM_MIDI_IN), 64) +}; + +#if TUD_OPT_HIGH_SPEED +uint8_t const desc_hs_configuration[] = { + // Config number, interface count, string index, total length, attribute, power in mA + TUD_CONFIG_DESCRIPTOR(1, ITF_NUM_TOTAL, 0, CONFIG_TOTAL_LEN, 0x00, 100), + + // Interface number, string index, EP Out & EP In address, EP size + TUD_MIDI_DESCRIPTOR(ITF_NUM_MIDI, 0, EPNUM_MIDI_OUT, (0x80 | EPNUM_MIDI_IN), 512) +}; +#endif + +// Invoked when received GET CONFIGURATION DESCRIPTOR +// Application return pointer to descriptor +// Descriptor contents must exist long enough for transfer to complete +uint8_t const * tud_descriptor_configuration_cb(uint8_t index) { + (void) index; // for multiple configurations + +#if TUD_OPT_HIGH_SPEED + // Although we are highspeed, host may be fullspeed. + return (tud_speed_get() == TUSB_SPEED_HIGH) ? desc_hs_configuration : desc_fs_configuration; +#else + return desc_fs_configuration; +#endif +} + +//--------------------------------------------------------------------+ +// String Descriptors +//--------------------------------------------------------------------+ + +// String Descriptor Index +enum { + STRID_LANGID = 0, + STRID_MANUFACTURER, + STRID_PRODUCT, + STRID_SERIAL, +}; + +// array of pointer to string descriptors +char const *string_desc_arr[] = { + (const char[]) { 0x09, 0x04 }, // 0: is supported language is English (0x0409) + "TinyUSB", // 1: Manufacturer + "TinyUSB Device", // 2: Product + NULL, // 3: Serials will use unique ID if possible +}; + +static uint16_t _desc_str[32 + 1]; + +// Invoked when received GET STRING DESCRIPTOR request +// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete +uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) { + (void) langid; + size_t chr_count; + + switch ( index ) { + case STRID_LANGID: + memcpy(&_desc_str[1], string_desc_arr[0], 2); + chr_count = 1; + break; + + case STRID_SERIAL: + chr_count = board_usb_get_serial(_desc_str + 1, 32); + break; + + default: + // Note: the 0xEE index string is a Microsoft OS 1.0 Descriptors. + // https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/microsoft-defined-usb-descriptors + + if (!(index < sizeof(string_desc_arr) / sizeof(string_desc_arr[0]))) { + return NULL; + } + + const char *str = string_desc_arr[index]; + + // Cap at max char + chr_count = strlen(str); + const size_t max_count = sizeof(_desc_str) / sizeof(_desc_str[0]) - 1; // -1 for string type + if ( chr_count > max_count ) { + chr_count = max_count; + } + + // Convert ASCII string into UTF-16 + for ( size_t i = 0; i < chr_count; i++ ) { + _desc_str[1 + i] = str[i]; + } + break; + } + + // first byte is length (including header), second byte is string type + _desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * chr_count + 2)); + + return _desc_str; +} diff --git a/hw/bsp/board.c b/hw/bsp/board.c index 6d9488431..e3a4be461 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -139,3 +139,91 @@ int board_getchar(void) { uint32_t tusb_time_millis_api(void) { return board_millis(); } + +//-------------------------------------------------------------------- +// FreeRTOS hooks +//-------------------------------------------------------------------- +#if CFG_TUSB_OS == OPT_OS_FREERTOS && !TUSB_MCU_VENDOR_ESPRESSIF +#include "FreeRTOS.h" +#include "task.h" + +void vApplicationMallocFailedHook(void) { + taskDISABLE_INTERRUPTS(); + TU_ASSERT(false, ); +} + +void vApplicationStackOverflowHook(xTaskHandle pxTask, char *pcTaskName) { + (void) pxTask; + (void) pcTaskName; + + taskDISABLE_INTERRUPTS(); + TU_ASSERT(false, ); +} + +/* configSUPPORT_STATIC_ALLOCATION is set to 1, so the application must provide an + * implementation of vApplicationGetIdleTaskMemory() to provide the memory that is + * used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) { + /* If the buffers to be provided to the Idle task are declared inside this + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xIdleTaskTCB; + static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + Note that, as the array is necessarily of type StackType_t, + configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} + +/* configSUPPORT_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the + * application must provide an implementation of vApplicationGetTimerTaskMemory() + * to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) { + /* If the buffers to be provided to the Timer task are declared inside this + * function then they must be declared static - otherwise they will be allocated on + * the stack and so not exists after this function exits. */ + static StaticTask_t xTimerTaskTCB; + static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + Note that, as the array is necessarily of type StackType_t, + configTIMER_TASK_STACK_DEPTH is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; +} + +#if CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X +#include "iodefine.h" +void vApplicationSetupTimerInterrupt(void) { + /* Enable CMT0 */ + unsigned short oldPRCR = SYSTEM.PRCR.WORD; + SYSTEM.PRCR.WORD = (0xA5u<<8) | TU_BIT(1); + MSTP(CMT0) = 0; + SYSTEM.PRCR.WORD = (0xA5u<<8) | oldPRCR; + + CMT0.CMCNT = 0; + CMT0.CMCOR = (unsigned short)(((configPERIPHERAL_CLOCK_HZ/configTICK_RATE_HZ)-1)/128); + CMT0.CMCR.WORD = TU_BIT(6) | 2; + IR(CMT0, CMI0) = 0; + IPR(CMT0, CMI0) = configKERNEL_INTERRUPT_PRIORITY; + IEN(CMT0, CMI0) = 1; + CMT.CMSTR0.BIT.STR0 = 1; +} +#endif + + +#endif diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h index c4f73c72e..e57f7c51f 100644 --- a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h +++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h @@ -8,7 +8,7 @@ * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions:aaaaa + * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c index a79908627..ea577db03 100755 --- a/src/class/bth/bth_device.c +++ b/src/class/bth/bth_device.c @@ -51,8 +51,14 @@ typedef struct uint32_t prev_xferred_bytes; // Endpoint Transfer buffer - CFG_TUSB_MEM_ALIGN bt_hci_cmd_t hci_cmd; - CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_BTH_DATA_EPSIZE]; + union { + CFG_TUD_MEM_ALIGN bt_hci_cmd_t hci_cmd; + TUD_DCACHE_PADDING; + }; + union { + CFG_TUD_MEM_ALIGN uint8_t epout_buf[CFG_TUD_BTH_DATA_EPSIZE]; + TUD_DCACHE_PADDING; + }; } btd_interface_t; diff --git a/src/class/dfu/dfu_device.c b/src/class/dfu/dfu_device.c index 71e7ac2b3..875bd4e09 100644 --- a/src/class/dfu/dfu_device.c +++ b/src/class/dfu/dfu_device.c @@ -47,8 +47,7 @@ //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -typedef struct -{ +typedef struct { uint8_t attrs; uint8_t alt; @@ -59,14 +58,16 @@ typedef struct uint16_t block; uint16_t length; - CFG_TUSB_MEM_ALIGN uint8_t transfer_buf[CFG_TUD_DFU_XFER_BUFSIZE]; + union { + CFG_TUD_MEM_ALIGN uint8_t transfer_buf[CFG_TUD_DFU_XFER_BUFSIZE]; + TUD_DCACHE_PADDING; + }; } dfu_state_ctx_t; // Only a single dfu state is allowed CFG_TUD_MEM_SECTION tu_static dfu_state_ctx_t _dfu_ctx; -static void reset_state(void) -{ +static void reset_state(void) { _dfu_ctx.state = DFU_IDLE; _dfu_ctx.status = DFU_STATUS_OK; _dfu_ctx.flashing_in_progress = false; diff --git a/src/class/dfu/dfu_rt_device.c b/src/class/dfu/dfu_rt_device.c index 3b801b787..a63c23d9a 100644 --- a/src/class/dfu/dfu_rt_device.c +++ b/src/class/dfu/dfu_rt_device.c @@ -58,9 +58,8 @@ bool dfu_rtd_deinit(void) { return true; } -void dfu_rtd_reset(uint8_t rhport) -{ - (void) rhport; +void dfu_rtd_reset(uint8_t rhport) { + (void) rhport; } uint16_t dfu_rtd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len) diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c index 42905ab0d..7e30e5ea4 100644 --- a/src/class/midi/midi_device.c +++ b/src/class/midi/midi_device.c @@ -40,15 +40,13 @@ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ -typedef struct -{ +typedef struct { uint8_t buffer[4]; uint8_t index; uint8_t total; -}midid_stream_t; +} midid_stream_t; -typedef struct -{ +typedef struct { uint8_t itf_num; uint8_t ep_in; uint8_t ep_out; @@ -72,9 +70,14 @@ typedef struct #endif // Endpoint Transfer buffer - CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_MIDI_EP_BUFSIZE]; - CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_MIDI_EP_BUFSIZE]; - + union { + CFG_TUD_MEM_ALIGN uint8_t epout_buf[CFG_TUD_MIDI_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; + union { + CFG_TUD_MEM_ALIGN uint8_t epin_buf[CFG_TUD_MIDI_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; } midid_interface_t; #define ITF_MEM_RESET_SIZE offsetof(midid_interface_t, rx_ff) @@ -84,8 +87,7 @@ typedef struct //--------------------------------------------------------------------+ CFG_TUD_MEM_SECTION midid_interface_t _midid_itf[CFG_TUD_MIDI]; -bool tud_midi_n_mounted (uint8_t itf) -{ +bool tud_midi_n_mounted (uint8_t itf) { midid_interface_t* midi = &_midid_itf[itf]; return midi->ep_in && midi->ep_out; } diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index dfa6c7151..f6f90c592 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -355,6 +355,7 @@ #define TUP_USBIP_DWC2_ESP32 #define TUP_DCD_ENDPOINT_MAX 7 // only 5 TX FIFO for endpoint IN #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0 // TODO currently have issue with buffer DMA with espressif + #define CFG_TUSB_OS_INC_PATH_DEFAULT freertos/ #elif TU_CHECK_MCU(OPT_MCU_ESP32P4) #define TUP_USBIP_DWC2 @@ -362,6 +363,8 @@ #define TUP_RHPORT_HIGHSPEED 1 // port0 FS, port1 HS #define TUP_DCD_ENDPOINT_MAX 16 // FS 7 ep, HS 16 ep + #define CFG_TUSB_OS_INC_PATH_DEFAULT freertos/ + #if defined(CFG_TUD_DWC2_DMA_ENABLE) && CFG_TUD_DWC2_DMA_ENABLE == 1 #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1 #endif @@ -379,7 +382,9 @@ #if (CFG_TUD_ENABLED || !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)) #error "MCUs are only supported with CFG_TUH_MAX3421 enabled" #endif + #define TUP_DCD_ENDPOINT_MAX 0 + #define CFG_TUSB_OS_INC_PATH_DEFAULT freertos/ //--------------------------------------------------------------------+ // Dialog diff --git a/src/tusb_option.h b/src/tusb_option.h index 1c8e8aff4..68fd90de9 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -403,7 +403,11 @@ #endif #ifndef CFG_TUSB_OS_INC_PATH - #define CFG_TUSB_OS_INC_PATH + #ifndef CFG_TUSB_OS_INC_PATH_DEFAULT + #define CFG_TUSB_OS_INC_PATH_DEFAULT + #endif + + #define CFG_TUSB_OS_INC_PATH CFG_TUSB_OS_INC_PATH_DEFAULT #endif //-------------------------------------------------------------------- -- cgit v1.3.1 From 01df8c36de16b21463085a96c3fb073237f968c5 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 21 Nov 2024 19:36:52 +0700 Subject: fix ci --- examples/device/midi_test_freertos/skip.txt | 16 ++ .../kinetis_k32l2/FreeRTOSConfig/FreeRTOSConfig.h | 1 + hw/bsp/lpc11/FreeRTOSConfig/FreeRTOSConfig.h | 1 + hw/bsp/lpc51/FreeRTOSConfig/FreeRTOSConfig.h | 6 +- hw/bsp/rx/FreeRTOSConfig/FreeRTOSConfig.h | 177 +++++++++++++++++++++ hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h | 7 +- 6 files changed, 201 insertions(+), 7 deletions(-) create mode 100644 examples/device/midi_test_freertos/skip.txt create mode 100644 hw/bsp/rx/FreeRTOSConfig/FreeRTOSConfig.h (limited to 'hw') diff --git a/examples/device/midi_test_freertos/skip.txt b/examples/device/midi_test_freertos/skip.txt new file mode 100644 index 000000000..650bf355b --- /dev/null +++ b/examples/device/midi_test_freertos/skip.txt @@ -0,0 +1,16 @@ +mcu:CH32V103 +mcu:CH32V20X +mcu:CH32V307 +mcu:CXD56 +mcu:F1C100S +mcu:GD32VF103 +mcu:MCXA15 +mcu:MKL25ZXX +mcu:MSP430x5xx +mcu:RP2040 +mcu:SAMD11 +mcu:SAMX7X +mcu:VALENTYUSB_EPTRI +mcu:RAXXX +family:broadcom_32bit +family:broadcom_64bit diff --git a/hw/bsp/kinetis_k32l2/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/kinetis_k32l2/FreeRTOSConfig/FreeRTOSConfig.h index e6604d360..0225abe8d 100644 --- a/hw/bsp/kinetis_k32l2/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/kinetis_k32l2/FreeRTOSConfig/FreeRTOSConfig.h @@ -85,6 +85,7 @@ #define configUSE_TICK_HOOK 0 #define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning #define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 /* Run time and task stats gathering related definitions. */ #define configGENERATE_RUN_TIME_STATS 0 diff --git a/hw/bsp/lpc11/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc11/FreeRTOSConfig/FreeRTOSConfig.h index 27b2d76f5..0e0721674 100644 --- a/hw/bsp/lpc11/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/lpc11/FreeRTOSConfig/FreeRTOSConfig.h @@ -94,6 +94,7 @@ #define configUSE_TICK_HOOK 0 #define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning #define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 /* Run time and task stats gathering related definitions. */ #define configGENERATE_RUN_TIME_STATS 0 diff --git a/hw/bsp/lpc51/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/lpc51/FreeRTOSConfig/FreeRTOSConfig.h index e6604d360..3bc226667 100644 --- a/hw/bsp/lpc51/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/lpc51/FreeRTOSConfig/FreeRTOSConfig.h @@ -85,6 +85,7 @@ #define configUSE_TICK_HOOK 0 #define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning #define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 /* Run time and task stats gathering related definitions. */ #define configGENERATE_RUN_TIME_STATS 0 @@ -122,7 +123,8 @@ /* Define to trap errors during development. */ // Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7 -#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) +#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \ + defined(__ARM7M__) || defined (__ARM7EM__) || defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) #define configASSERT(_exp) \ do {\ if ( !(_exp) ) { \ @@ -133,8 +135,6 @@ }\ }\ } while(0) -#else - #define configASSERT( x ) #endif /* FreeRTOS hooks to NVIC vectors */ diff --git a/hw/bsp/rx/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/rx/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..edf0a8433 --- /dev/null +++ b/hw/bsp/rx/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,177 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ +// FIXME cause redundant-decls warnings +extern uint32_t SystemCoreClock; +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 0 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE ( 1024 ) +#define configRUN_FREERTOS_SECURE_ONLY 1 + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 0 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +#ifdef __RX__ +/* Renesas RX series */ +#define vSoftwareInterruptISR INT_Excep_ICU_SWINT +#define vTickISR INT_Excep_CMT0_CMI0 +#define configPERIPHERAL_CLOCK_HZ (configCPU_CLOCK_HZ/2) +#define configKERNEL_INTERRUPT_PRIORITY 1 +#define configMAX_SYSCALL_INTERRUPT_PRIORITY 4 + +#else + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ +#if defined(__NVIC_PRIO_BITS) + // For Cortex-M specific: __NVIC_PRIO_BITS is defined in core_cmx.h + #define configPRIO_BITS __NVIC_PRIO_BITS + +#elif defined(__ECLIC_INTCTLBITS) + // RISC-V Bumblebee core from nuclei + #define configPRIO_BITS __ECLIC_INTCTLBITS + +#elif defined(__IASMARM__) + // FIXME: IAR Assembler cannot include mcu header directly to get __NVIC_PRIO_BITS. + // Therefore we will hard coded it to minimum value of 2 to get pass ci build. + // IAR user must update this to correct value of the target MCU + #message "configPRIO_BITS is hard coded to 2 to pass IAR build only. User should update it per MCU" + #define configPRIO_BITS 2 + +#else + #error "FreeRTOS configPRIO_BITS to be defined" +#endif + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<DHCSR */ \ @@ -130,8 +131,6 @@ }\ }\ } while(0) -#else -#define configASSERT( x ) #endif /* FreeRTOS hooks to NVIC vectors */ -- cgit v1.3.1 From c09eedaf24ad609a1b12bf9c1c7f631b8374f222 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 22 Nov 2024 20:22:00 +0700 Subject: try to fix circleci with kinetis --- .circleci/config2.yml | 2 +- .github/actions/setup_toolchain/action.yml | 2 +- .idea/cmake.xml | 6 +++--- examples/build_system/cmake/toolchain/aarch64_gcc.cmake | 6 +++--- examples/build_system/cmake/toolchain/arm_clang.cmake | 6 +++--- examples/build_system/cmake/toolchain/arm_gcc.cmake | 6 +++--- examples/build_system/cmake/toolchain/arm_iar.cmake | 6 +++--- examples/build_system/cmake/toolchain/msp430_gcc.cmake | 6 +++--- examples/build_system/cmake/toolchain/riscv_gcc.cmake | 6 +++--- hw/bsp/family_support.cmake | 1 + hw/bsp/kinetis_k/FreeRTOSConfig/FreeRTOSConfig.h | 2 -- hw/bsp/kinetis_k/boards/teensy_35/board.cmake | 1 - hw/bsp/kinetis_k/family.cmake | 1 - src/class/midi/midi_device.c | 2 +- 14 files changed, 25 insertions(+), 28 deletions(-) (limited to 'hw') diff --git a/.circleci/config2.yml b/.circleci/config2.yml index 6655fe45d..e811ef3ed 100644 --- a/.circleci/config2.yml +++ b/.circleci/config2.yml @@ -12,7 +12,7 @@ commands: command: | TOOLCHAIN_JSON='{ "aarch64-gcc": "https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz", - "arm-clang": "https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-17.0.1/LLVMEmbeddedToolchainForArm-17.0.1-Linux-x86_64.tar.xz", + "arm-clang": "https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-19.1.1/LLVM-ET-Arm-19.1.1-Linux-x86_64.tar.xz", "arm-gcc": "https://github.com/xpack-dev-tools/arm-none-eabi-gcc-xpack/releases/download/v13.2.1-1.1/xpack-arm-none-eabi-gcc-13.2.1-1.1-linux-x64.tar.gz", "msp430-gcc": "http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2", "riscv-gcc": "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz", diff --git a/.github/actions/setup_toolchain/action.yml b/.github/actions/setup_toolchain/action.yml index 40dbd87b2..8406a812d 100644 --- a/.github/actions/setup_toolchain/action.yml +++ b/.github/actions/setup_toolchain/action.yml @@ -38,7 +38,7 @@ runs: run: | TOOLCHAIN_JSON='{ "aarch64-gcc": "https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz", - "arm-clang": "https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-17.0.1/LLVMEmbeddedToolchainForArm-17.0.1-Linux-x86_64.tar.xz", + "arm-clang": "https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-19.1.1/LLVM-ET-Arm-19.1.1-Linux-x86_64.tar.xz", "msp430-gcc": "http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2", "riscv-gcc": "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz", "rx-gcc": "http://gcc-renesas.com/downloads/get.php?f=rx/8.3.0.202004-gnurx/gcc-8.3.0.202004-GNURX-ELF.run" diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 1210c49e7..aa15374b9 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -61,7 +61,7 @@ - + @@ -100,7 +100,7 @@ - + @@ -108,7 +108,7 @@ - + diff --git a/examples/build_system/cmake/toolchain/aarch64_gcc.cmake b/examples/build_system/cmake/toolchain/aarch64_gcc.cmake index 2d30a0b71..ac1e482eb 100644 --- a/examples/build_system/cmake/toolchain/aarch64_gcc.cmake +++ b/examples/build_system/cmake/toolchain/aarch64_gcc.cmake @@ -7,9 +7,9 @@ if (NOT DEFINED CMAKE_CXX_COMPILER) endif () set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) -set(CMAKE_SIZE "aarch64-none-elf-size" CACHE FILEPATH "") -set(CMAKE_OBJCOPY "aarch64-none-elf-objcopy" CACHE FILEPATH "") -set(CMAKE_OBJDUMP "aarch64-none-elf-objdump" CACHE FILEPATH "") +find_program(CMAKE_SIZE aarch64-none-elf-size) +find_program(CMAKE_OBJCOPY aarch64-none-elf-objcopy) +find_program(CMAKE_OBJDUMP aarch64-none-elf-objdump) include(${CMAKE_CURRENT_LIST_DIR}/common.cmake) diff --git a/examples/build_system/cmake/toolchain/arm_clang.cmake b/examples/build_system/cmake/toolchain/arm_clang.cmake index 754d672fd..fe3c2b453 100644 --- a/examples/build_system/cmake/toolchain/arm_clang.cmake +++ b/examples/build_system/cmake/toolchain/arm_clang.cmake @@ -7,9 +7,9 @@ if (NOT DEFINED CMAKE_CXX_COMPILER) endif () set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) -set(CMAKE_SIZE "llvm-size" CACHE FILEPATH "") -set(CMAKE_OBJCOPY "llvm-objcopy" CACHE FILEPATH "") -set(CMAKE_OBJDUMP "llvm-objdump" CACHE FILEPATH "") +find_program(CMAKE_SIZE llvm-size) +find_program(CMAKE_OBJCOPY llvm-objcopy) +find_program(CMAKE_OBJDUMP llvm-objdump) include(${CMAKE_CURRENT_LIST_DIR}/common.cmake) diff --git a/examples/build_system/cmake/toolchain/arm_gcc.cmake b/examples/build_system/cmake/toolchain/arm_gcc.cmake index d3d73c629..0b0949dd8 100644 --- a/examples/build_system/cmake/toolchain/arm_gcc.cmake +++ b/examples/build_system/cmake/toolchain/arm_gcc.cmake @@ -7,9 +7,9 @@ if (NOT DEFINED CMAKE_CXX_COMPILER) endif () set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) -set(CMAKE_SIZE "arm-none-eabi-size" CACHE FILEPATH "") -set(CMAKE_OBJCOPY "arm-none-eabi-objcopy" CACHE FILEPATH "") -set(CMAKE_OBJDUMP "arm-none-eabi-objdump" CACHE FILEPATH "") +find_program(CMAKE_SIZE arm-none-eabi-size) +find_program(CMAKE_OBJCOPY arm-none-eabi-objcopy) +find_program(CMAKE_OBJDUMP arm-none-eabi-objdump) include(${CMAKE_CURRENT_LIST_DIR}/common.cmake) diff --git a/examples/build_system/cmake/toolchain/arm_iar.cmake b/examples/build_system/cmake/toolchain/arm_iar.cmake index 6d2219ca8..083815715 100644 --- a/examples/build_system/cmake/toolchain/arm_iar.cmake +++ b/examples/build_system/cmake/toolchain/arm_iar.cmake @@ -10,8 +10,8 @@ if (NOT DEFINED CMAKE_ASM_COMPILER) set(CMAKE_ASM_COMPILER "iasmarm") endif() -set(CMAKE_SIZE "size" CACHE FILEPATH "") -set(CMAKE_OBJCOPY "ielftool" CACHE FILEPATH "") -set(CMAKE_OBJDUMP "iefdumparm" CACHE FILEPATH "") +find_program(CMAKE_SIZE size) +find_program(CMAKE_OBJCOPY ielftool) +find_program(CMAKE_OBJDUMP iefdumparm) include(${CMAKE_CURRENT_LIST_DIR}/common.cmake) diff --git a/examples/build_system/cmake/toolchain/msp430_gcc.cmake b/examples/build_system/cmake/toolchain/msp430_gcc.cmake index 73368adba..799518931 100644 --- a/examples/build_system/cmake/toolchain/msp430_gcc.cmake +++ b/examples/build_system/cmake/toolchain/msp430_gcc.cmake @@ -8,8 +8,8 @@ endif () set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) -set(CMAKE_SIZE "msp430-elf-size" CACHE FILEPATH "") -set(CMAKE_OBJCOPY "msp430-elf-objcopy" CACHE FILEPATH "") -set(CMAKE_OBJDUMP "msp430-elf-objdump" CACHE FILEPATH "") +find_program(CMAKE_SIZE msp430-elf-size) +find_program(CMAKE_OBJCOPY msp430-elf-objcopy) +find_program(CMAKE_OBJDUMP msp430-elf-objdump) include(${CMAKE_CURRENT_LIST_DIR}/common.cmake) diff --git a/examples/build_system/cmake/toolchain/riscv_gcc.cmake b/examples/build_system/cmake/toolchain/riscv_gcc.cmake index d788df023..60a24528b 100644 --- a/examples/build_system/cmake/toolchain/riscv_gcc.cmake +++ b/examples/build_system/cmake/toolchain/riscv_gcc.cmake @@ -16,9 +16,9 @@ if (NOT DEFINED CMAKE_CXX_COMPILER) endif () set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) -set(CMAKE_SIZE ${CROSS_COMPILE}size CACHE FILEPATH "") -set(CMAKE_OBJCOPY ${CROSS_COMPILE}objcopy CACHE FILEPATH "") -set(CMAKE_OBJDUMP ${CROSS_COMPILE}objdump CACHE FILEPATH "") +find_program(CMAKE_SIZE ${CROSS_COMPILE}size) +find_program(CMAKE_OBJCOPY ${CROSS_COMPILE}objcopy) +find_program(CMAKE_OBJDUMP ${CROSS_COMPILE}objdump) include(${CMAKE_CURRENT_LIST_DIR}/common.cmake) diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 57fa63261..3f2872a30 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -553,6 +553,7 @@ function(family_flash_teensy TARGET) add_custom_target(${TARGET}-teensy DEPENDS ${TARGET} + COMMAND ${CMAKE_OBJCOPY} -Oihex $ $/${TARGET}.hex COMMAND ${TEENSY_CLI} --mcu=${TEENSY_MCU} -w -s $/${TARGET}.hex ) endfunction() diff --git a/hw/bsp/kinetis_k/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/kinetis_k/FreeRTOSConfig/FreeRTOSConfig.h index ed46508a4..76004241a 100644 --- a/hw/bsp/kinetis_k/FreeRTOSConfig/FreeRTOSConfig.h +++ b/hw/bsp/kinetis_k/FreeRTOSConfig/FreeRTOSConfig.h @@ -129,8 +129,6 @@ }\ }\ } while(0) -#else - #define configASSERT( x ) #endif /* FreeRTOS hooks to NVIC vectors */ diff --git a/hw/bsp/kinetis_k/boards/teensy_35/board.cmake b/hw/bsp/kinetis_k/boards/teensy_35/board.cmake index bd253d996..ae4409e12 100644 --- a/hw/bsp/kinetis_k/boards/teensy_35/board.cmake +++ b/hw/bsp/kinetis_k/boards/teensy_35/board.cmake @@ -2,7 +2,6 @@ set(MCU_VARIANT MK64F12) set(JLINK_DEVICE MK64FX512xxx12) set(TEENSY_MCU TEENSY35) -set(PYOCD_TARGET k64f) set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/MK64FX512xxx12_flash.ld) diff --git a/hw/bsp/kinetis_k/family.cmake b/hw/bsp/kinetis_k/family.cmake index 771754ebd..c30268629 100644 --- a/hw/bsp/kinetis_k/family.cmake +++ b/hw/bsp/kinetis_k/family.cmake @@ -111,7 +111,6 @@ function(family_configure_example TARGET RTOS) family_flash_jlink(${TARGET}) if (DEFINED TEENSY_MCU) - family_add_bin_hex(${TARGET}) family_flash_teensy(${TARGET}) endif () endfunction() diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c index 5be4cb993..c545f8287 100644 --- a/src/class/midi/midi_device.c +++ b/src/class/midi/midi_device.c @@ -97,7 +97,7 @@ static void _prep_out_transaction(uint8_t idx) { // TODO Actually we can still carry out the transfer, keeping count of received bytes // and slowly move it to the FIFO when read(). // This pre-check reduces endpoint claiming - TU_VERIFY(available >= sizeof(_midid_epbuf[idx].epout), ); + TU_VERIFY(available >= CFG_TUD_MIDI_EP_BUFSIZE, ); // claim endpoint TU_VERIFY(usbd_edpt_claim(rhport, p_midi->ep_out), ); -- cgit v1.3.1 From be25aa31f6720e0efe96e8656f46adf0ccbbce50 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Nov 2024 10:20:38 +0700 Subject: hcd dwc2 add dcache support, usbh correctly use cache line size with TUH_EPBUF_DEF --- .../components/tinyusb_src/CMakeLists.txt | 3 +- src/host/hcd.h | 6 +- src/host/usbh.c | 72 ++++++++++++++-------- src/portable/synopsys/dwc2/dcd_dwc2.c | 2 +- src/portable/synopsys/dwc2/hcd_dwc2.c | 28 ++++++++- 5 files changed, 78 insertions(+), 33 deletions(-) (limited to 'hw') diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt index 9f55c8d5a..95fb2e440 100644 --- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt +++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt @@ -18,7 +18,8 @@ list(APPEND compile_definitions if (target STREQUAL esp32p4) # P4 change alignment to 64 (DCache line size) for possible DMA configuration list(APPEND compile_definitions - CFG_TUSB_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\) + CFG_TUD_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\) + CFG_TUH_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\) ) endif () diff --git a/src/host/hcd.h b/src/host/hcd.h index 6518e6fd2..56b6fdb5d 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -103,15 +103,15 @@ typedef struct { // clean/flush data cache: write cache -> memory. // Required before an DMA TX transfer to make sure data is in memory -bool hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_clean(void const* addr, uint32_t data_size); // invalidate data cache: mark cache as invalid, next read will read from memory // Required BOTH before and after an DMA RX transfer -bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_invalidate(void const* addr, uint32_t data_size); // clean and invalidate data cache // Required before an DMA transfer where memory is both read/write by DMA -bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size); //--------------------------------------------------------------------+ // Controller API diff --git a/src/host/usbh.c b/src/host/usbh.c index b0a2b2160..f2683e235 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -65,6 +65,21 @@ TU_ATTR_WEAK void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_is (void) in_isr; } +TU_ATTR_WEAK bool hcd_dcache_clean(const void* addr, uint32_t data_size) { + (void) addr; (void) data_size; + return false; +} + +TU_ATTR_WEAK bool hcd_dcache_invalidate(const void* addr, uint32_t data_size) { + (void) addr; (void) data_size; + return false; +} + +TU_ATTR_WEAK bool hcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) { + (void) addr; (void) data_size; + return false; +} + //--------------------------------------------------------------------+ // USBH-HCD common data structure //--------------------------------------------------------------------+ @@ -249,14 +264,10 @@ static usbh_device_t _usbh_devices[TOTAL_DEVICES]; OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t); static osal_queue_t _usbh_q; -CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN -static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE]; - // Control transfers: since most controllers do not support multiple control transfers // on multiple devices concurrently and control transfers are not used much except for // enumeration, we will only execute control transfers one at a time. -CFG_TUH_MEM_SECTION struct { - CFG_TUH_MEM_ALIGN tusb_control_request_t request; +static struct { uint8_t* buffer; tuh_xfer_cb_t complete_cb; uintptr_t user_data; @@ -264,7 +275,14 @@ CFG_TUH_MEM_SECTION struct { uint8_t daddr; volatile uint8_t stage; volatile uint16_t actual_len; -}_ctrl_xfer; +} _ctrl_xfer; + +typedef struct { + TUH_EPBUF_TYPE_DEF(request, tusb_control_request_t); + TUH_EPBUF_DEF(ctrl, CFG_TUH_ENUMERATION_BUFSIZE); +} usbh_epbuf_t; + +CFG_TUH_MEM_SECTION static usbh_epbuf_t _usbh_epbuf; //------------- Helper Function -------------// @@ -475,7 +493,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { switch (event.event_id) { case HCD_EVENT_DEVICE_ATTACH: - // due to the shared _usbh_ctrl_buf, we must complete enumerating one device before enumerating another one. + // due to the shared control buffer, we must complete enumerating one device before enumerating another one. // TODO better to have an separated queue for newly attached devices if (_dev0.enumerating) { // Some device can cause multiple duplicated attach events @@ -622,10 +640,10 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { _ctrl_xfer.daddr = daddr; _ctrl_xfer.actual_len = 0; - _ctrl_xfer.request = (*xfer->setup); _ctrl_xfer.buffer = xfer->buffer; _ctrl_xfer.complete_cb = xfer->complete_cb; _ctrl_xfer.user_data = xfer->user_data; + _usbh_epbuf.request = (*xfer->setup); } (void) osal_mutex_unlock(_usbh_mutex); @@ -639,7 +657,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { TU_LOG_BUF_USBH(xfer->setup, 8); if (xfer->complete_cb) { - TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request) ); + TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_usbh_epbuf.request) ); }else { // blocking if complete callback is not provided // change callback to internal blocking, and result as user argument @@ -649,7 +667,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { _ctrl_xfer.user_data = (uintptr_t) &result; _ctrl_xfer.complete_cb = _control_blocking_complete_cb; - TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.request) ); + TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_usbh_epbuf.request) ); while (result == XFER_RESULT_INVALID) { // Note: this can be called within an callback ie. part of tuh_task() @@ -681,7 +699,7 @@ static void _control_xfer_complete(uint8_t daddr, xfer_result_t result) { TU_LOG_USBH("\r\n"); // duplicate xfer since user can execute control transfer within callback - tusb_control_request_t const request = _ctrl_xfer.request; + tusb_control_request_t const request = _usbh_epbuf.request; tuh_xfer_t xfer_temp = { .daddr = daddr, .ep_addr = 0, @@ -704,7 +722,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t (void) ep_addr; const uint8_t rhport = usbh_get_rhport(daddr); - tusb_control_request_t const * request = &_ctrl_xfer.request; + tusb_control_request_t const * request = &_usbh_epbuf.request; if (XFER_RESULT_SUCCESS != result) { TU_LOG_USBH("[%u:%u] Control %s, xferred_bytes = %" PRIu32 "\r\n", rhport, daddr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes); @@ -817,7 +835,7 @@ uint8_t usbh_get_rhport(uint8_t dev_addr) { } uint8_t *usbh_get_enum_buf(void) { - return _usbh_ctrl_buf; + return _usbh_epbuf.ctrl; } void usbh_int_set(bool enabled) { @@ -1279,7 +1297,7 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu // Enumeration Process // is a lengthy process with a series of control transfer to configure // newly attached device. -// NOTE: due to the shared _usbh_ctrl_buf, we must complete enumerating +// NOTE: due to the shared control buffer, we must complete enumerating // one device before enumerating another one. //--------------------------------------------------------------------+ @@ -1347,7 +1365,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { case ENUM_HUB_CLEAR_RESET_1: { hub_port_status_response_t port_status; - memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t)); + memcpy(&port_status, _usbh_epbuf.ctrl, sizeof(hub_port_status_response_t)); if (!port_status.status.connection) { // device unplugged while delaying, nothing else to do @@ -1368,13 +1386,13 @@ static void process_enumeration(tuh_xfer_t* xfer) { case ENUM_HUB_GET_STATUS_2: tusb_time_delay_ms_api(ENUM_RESET_DELAY_MS); - TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, + TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_epbuf.ctrl, process_enumeration, ENUM_HUB_CLEAR_RESET_2),); break; case ENUM_HUB_CLEAR_RESET_2: { hub_port_status_response_t port_status; - memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t)); + memcpy(&port_status, _usbh_epbuf.ctrl, sizeof(hub_port_status_response_t)); // Acknowledge Port Reset Change if Reset Successful if (port_status.change.reset) { @@ -1392,7 +1410,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { // Get first 8 bytes of device descriptor for Control Endpoint size TU_LOG_USBH("Get 8 byte of Device Descriptor\r\n"); - TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8, + TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_epbuf.ctrl, 8, process_enumeration, ENUM_SET_ADDR),); break; } @@ -1443,13 +1461,13 @@ static void process_enumeration(tuh_xfer_t* xfer) { // Get full device descriptor TU_LOG_USBH("Get Device Descriptor\r\n"); - TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t), + TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_epbuf.ctrl, sizeof(tusb_desc_device_t), process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC),); break; } case ENUM_GET_9BYTE_CONFIG_DESC: { - tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf; + tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_epbuf.ctrl; usbh_device_t* dev = get_device(daddr); TU_ASSERT(dev,); @@ -1459,18 +1477,18 @@ static void process_enumeration(tuh_xfer_t* xfer) { dev->i_product = desc_device->iProduct; dev->i_serial = desc_device->iSerialNumber; - // if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_ctrl_buf); + // if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_epbuf.ctrl); // Get 9-byte for total length uint8_t const config_idx = CONFIG_NUM - 1; TU_LOG_USBH("Get Configuration[0] Descriptor (9 bytes)\r\n"); - TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, 9, + TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, 9, process_enumeration, ENUM_GET_FULL_CONFIG_DESC),); break; } case ENUM_GET_FULL_CONFIG_DESC: { - uint8_t const* desc_config = _usbh_ctrl_buf; + uint8_t const* desc_config = _usbh_epbuf.ctrl; // Use offsetof to avoid pointer to the odd/misaligned address uint16_t const total_len = tu_le16toh( @@ -1482,7 +1500,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { // Get full configuration descriptor uint8_t const config_idx = CONFIG_NUM - 1; TU_LOG_USBH("Get Configuration[0] Descriptor\r\n"); - TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, total_len, + TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, total_len, process_enumeration, ENUM_SET_CONFIG),); break; } @@ -1500,7 +1518,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { // Parse configuration & set up drivers // driver_open() must not make any usb transfer - TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_ctrl_buf),); + TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_epbuf.ctrl),); // Start the Set Configuration process for interfaces (itf = TUSB_INDEX_INVALID_8) // Since driver can perform control transfer within its set_config, this is done asynchronously. @@ -1561,7 +1579,7 @@ static bool enum_new_device(hcd_event_t* event) { tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); // ENUM_HUB_GET_STATUS - TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, + TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_epbuf.ctrl, process_enumeration, ENUM_HUB_CLEAR_RESET_1)); } #endif // hub @@ -1589,7 +1607,7 @@ static uint8_t get_new_address(bool is_hub) { } static bool enum_request_set_addr(void) { - tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf; + tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_epbuf.ctrl; // Get new address uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB); diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 8a9d06bc2..04108499d 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -31,7 +31,7 @@ #if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2) -#if !CFG_TUD_DWC2_SLAVE_ENABLE && !CFG_TUH_DWC2_DMA_ENABLE +#if !(CFG_TUD_DWC2_SLAVE_ENABLE || CFG_TUH_DWC2_DMA_ENABLE) #error DWC2 require either CFG_TUD_DWC2_SLAVE_ENABLE or CFG_TUH_DWC2_DMA_ENABLE to be enabled #endif diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 8e0162ed6..ebbb6200a 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -28,6 +28,10 @@ #if CFG_TUH_ENABLED && defined(TUP_USBIP_DWC2) +#if !(CFG_TUH_DWC2_SLAVE_ENABLE || CFG_TUH_DWC2_DMA_ENABLE) +#error DWC2 require either CFG_TUH_DWC2_SLAVE_ENABLE or CFG_TUH_DWC2_DMA_ENABLE to be enabled +#endif + // Debug level for DWC2 #define DWC2_DEBUG 2 @@ -132,6 +136,23 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc return CFG_TUH_DWC2_DMA_ENABLE && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; } +#if CFG_TUH_MEM_DCACHE_ENABLE +bool hcd_dcache_clean(const void* addr, uint32_t data_size) { + TU_VERIFY(addr && data_size); + return dwc2_dcache_clean(addr, data_size); +} + +bool hcd_dcache_invalidate(const void* addr, uint32_t data_size) { + TU_VERIFY(addr && data_size); + return dwc2_dcache_invalidate(addr, data_size); +} + +bool hcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) { + TU_VERIFY(addr && data_size); + return dwc2_dcache_clean_invalidate(addr, data_size); +} +#endif + // Allocate a channel for new transfer TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) { const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); @@ -555,6 +576,7 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { if (hcchar_bm->ep_dir == TUSB_DIR_IN) { channel_send_in_token(dwc2, channel); } else { + hcd_dcache_clean(edpt->buffer, edpt->buflen); channel->hcchar |= HCCHAR_CHENA; } } else { @@ -1119,13 +1141,17 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) { const uint32_t hcint = channel->hcint; channel->hcint = hcint; // clear interrupt - bool is_done; + bool is_done = false; if (is_dma) { #if CFG_TUH_DWC2_DMA_ENABLE if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { is_done = handle_channel_out_dma(dwc2, ch_id, hcint); } else { is_done = handle_channel_in_dma(dwc2, ch_id, hcint); + if (is_done && (channel->hcdma > xfer->xferred_bytes)) { + // hcdma is increased by word --> need to align4 + hcd_dcache_invalidate((void*) tu_align4(channel->hcdma - xfer->xferred_bytes), xfer->xferred_bytes); + } } #endif } else { -- cgit v1.3.1 From 67e92e6688e609098270ba249f15a8dc7f051cbf Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Nov 2024 22:07:28 +0700 Subject: add TUH_EPBUF_DEF for cdc host --- examples/host/cdc_msc_hid_freertos/src/cdc_app.c | 14 --------- examples/host/cdc_msc_hid_freertos/src/main.c | 14 --------- hw/bsp/espressif/boards/family.c | 40 ++++++++---------------- src/class/cdc/cdc_host.c | 36 +++++++++++++-------- src/class/cdc/cdc_host.h | 3 +- 5 files changed, 37 insertions(+), 70 deletions(-) (limited to 'hw') diff --git a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c index dfe1418f6..7cbe1e03a 100644 --- a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c +++ b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c @@ -28,22 +28,8 @@ #include "bsp/board_api.h" #if TUSB_MCU_VENDOR_ESPRESSIF -// ESP-IDF need "freertos/" prefix in include path. -// CFG_TUSB_OS_INC_PATH should be defined accordingly. - #include "freertos/FreeRTOS.h" - #include "freertos/semphr.h" - #include "freertos/queue.h" - #include "freertos/task.h" - #include "freertos/timers.h" - #define CDC_STACK_SZIE 2048 #else - #include "FreeRTOS.h" - #include "semphr.h" - #include "queue.h" - #include "task.h" - #include "timers.h" - #define CDC_STACK_SZIE (3*configMINIMAL_STACK_SIZE/2) #endif diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c index fe050d334..10d1b120b 100644 --- a/examples/host/cdc_msc_hid_freertos/src/main.c +++ b/examples/host/cdc_msc_hid_freertos/src/main.c @@ -31,22 +31,8 @@ #include "tusb.h" #if TUSB_MCU_VENDOR_ESPRESSIF - // ESP-IDF need "freertos/" prefix in include path. - // CFG_TUSB_OS_INC_PATH should be defined accordingly. - #include "freertos/FreeRTOS.h" - #include "freertos/semphr.h" - #include "freertos/queue.h" - #include "freertos/task.h" - #include "freertos/timers.h" - #define USBH_STACK_SIZE 4096 #else - #include "FreeRTOS.h" - #include "semphr.h" - #include "queue.h" - #include "task.h" - #include "timers.h" - // Increase stack size when debug log is enabled #define USBH_STACK_SIZE (3*configMINIMAL_STACK_SIZE/2) * (CFG_TUSB_DEBUG ? 2 : 1) #endif diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index 729b3539d..048b431fb 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -35,10 +35,6 @@ #include "driver/uart.h" #include "esp_private/periph_ctrl.h" -// Note; current code use UART0 can cause device to reset while monitoring -#define USE_UART 0 -#define UART_ID UART_NUM_0 - #ifdef NEOPIXEL_PIN #include "led_strip.h" static led_strip_handle_t led_strip; @@ -57,19 +53,6 @@ static bool usb_init(void); // Initialize on-board peripherals : led, button, uart and USB void board_init(void) { -#if USE_UART - // uart init - uart_config_t uart_config = { - .baud_rate = 115200, - .data_bits = UART_DATA_8_BITS, - .parity = UART_PARITY_DISABLE, - .stop_bits = UART_STOP_BITS_1, - .flow_ctrl = UART_HW_FLOWCTRL_DISABLE - }; - uart_driver_install(UART_ID, 1024, 0, 0, NULL, 0); - uart_param_config(UART_ID, &uart_config); -#endif - #ifdef NEOPIXEL_PIN #ifdef NEOPIXEL_POWER_PIN gpio_reset_pin(NEOPIXEL_POWER_PIN); @@ -145,23 +128,26 @@ uint32_t board_button_read(void) { // Get characters from UART int board_uart_read(uint8_t* buf, int len) { -#if USE_UART - return uart_read_bytes(UART_ID, buf, len, 0); -#else - return -1; -#endif + for (int i=0; i 0 ? (int) c : (-1); + return getchar(); } //-------------------------------------------------------------------- diff --git a/src/class/cdc/cdc_host.c b/src/class/cdc/cdc_host.c index 8717970e6..d92fd875d 100644 --- a/src/class/cdc/cdc_host.c +++ b/src/class/cdc/cdc_host.c @@ -73,15 +73,17 @@ typedef struct { tu_edpt_stream_t rx; uint8_t tx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE]; - CFG_TUH_MEM_ALIGN uint8_t tx_ep_buf[CFG_TUH_CDC_TX_EPSIZE]; - uint8_t rx_ff_buf[CFG_TUH_CDC_TX_BUFSIZE]; - CFG_TUH_MEM_ALIGN uint8_t rx_ep_buf[CFG_TUH_CDC_TX_EPSIZE]; } stream; } cdch_interface_t; -CFG_TUH_MEM_SECTION +typedef struct { + TUH_EPBUF_DEF(tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE); + TUH_EPBUF_DEF(rx_ep_buf, CFG_TUH_CDC_TX_EPSIZE); +} cdch_epbuf_t; + static cdch_interface_t cdch_data[CFG_TUH_CDC]; +CFG_TUH_MEM_SECTION static cdch_epbuf_t cdch_epbuf[CFG_TUH_CDC]; //--------------------------------------------------------------------+ // Serial Driver @@ -626,13 +628,14 @@ bool cdch_init(void) { tu_memclr(cdch_data, sizeof(cdch_data)); for (size_t i = 0; i < CFG_TUH_CDC; i++) { cdch_interface_t* p_cdc = &cdch_data[i]; + cdch_epbuf_t* epbuf = &cdch_epbuf[i]; tu_edpt_stream_init(&p_cdc->stream.tx, true, true, false, p_cdc->stream.tx_ff_buf, CFG_TUH_CDC_TX_BUFSIZE, - p_cdc->stream.tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE); + epbuf->tx_ep_buf, CFG_TUH_CDC_TX_EPSIZE); tu_edpt_stream_init(&p_cdc->stream.rx, true, false, false, p_cdc->stream.rx_ff_buf, CFG_TUH_CDC_RX_BUFSIZE, - p_cdc->stream.rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE); + epbuf->rx_ep_buf, CFG_TUH_CDC_RX_EPSIZE); } return true; @@ -654,7 +657,9 @@ void cdch_close(uint8_t daddr) { TU_LOG_DRV(" CDCh close addr = %u index = %u\r\n", daddr, idx); // Invoke application callback - if (tuh_cdc_umount_cb) tuh_cdc_umount_cb(idx); + if (tuh_cdc_umount_cb) { + tuh_cdc_umount_cb(idx); + } p_cdc->daddr = 0; p_cdc->bInterfaceNumber = 0; @@ -675,7 +680,9 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t if ( ep_addr == p_cdc->stream.tx.ep_addr ) { // invoke tx complete callback to possibly refill tx fifo - if (tuh_cdc_tx_complete_cb) tuh_cdc_tx_complete_cb(idx); + if (tuh_cdc_tx_complete_cb) { + tuh_cdc_tx_complete_cb(idx); + } if ( 0 == tu_edpt_stream_write_xfer(daddr, &p_cdc->stream.tx) ) { // If there is no data left, a ZLP should be sent if: @@ -695,7 +702,9 @@ bool cdch_xfer_cb(uint8_t daddr, uint8_t ep_addr, xfer_result_t event, uint32_t } // invoke receive callback - if (tuh_cdc_rx_cb) tuh_cdc_rx_cb(idx); + if (tuh_cdc_rx_cb) { + tuh_cdc_rx_cb(idx); + } // prepare for next transfer if needed tu_edpt_stream_read_xfer(daddr, &p_cdc->stream.rx); @@ -738,9 +747,8 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d if (TUSB_CLASS_CDC == itf_desc->bInterfaceClass && CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass) { return acm_open(daddr, itf_desc, max_len); - } - else if (SERIAL_DRIVER_COUNT > 1 && - TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) { + } else if (SERIAL_DRIVER_COUNT > 1 && + TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass) { uint16_t vid, pid; TU_VERIFY(tuh_vid_pid_get(daddr, &vid, &pid)); @@ -760,7 +768,9 @@ bool cdch_open(uint8_t rhport, uint8_t daddr, tusb_desc_interface_t const *itf_d static void set_config_complete(cdch_interface_t * p_cdc, uint8_t idx, uint8_t itf_num) { TU_LOG_DRV("CDCh Set Configure complete\r\n"); p_cdc->mounted = true; - if (tuh_cdc_mount_cb) tuh_cdc_mount_cb(idx); + if (tuh_cdc_mount_cb) { + tuh_cdc_mount_cb(idx); + } // Prepare for incoming data tu_edpt_stream_read_xfer(p_cdc->daddr, &p_cdc->stream.rx); diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index b63dd1530..df975b2f0 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -89,8 +89,7 @@ bool tuh_cdc_get_dtr(uint8_t idx); bool tuh_cdc_get_rts(uint8_t idx); // Check if interface is connected (DTR active) -TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_connected(uint8_t idx) -{ +TU_ATTR_ALWAYS_INLINE static inline bool tuh_cdc_connected(uint8_t idx) { return tuh_cdc_get_dtr(idx); } -- cgit v1.3.1 From 453d69517b8f7f019ac855531e9e433d9d158f37 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 27 Nov 2024 11:10:06 +0700 Subject: fix multiple flag on compiling --- hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt | 1 + hw/bsp/family_support.cmake | 2 ++ hw/bsp/rp2040/family.cmake | 1 + src/class/msc/msc_device.c | 2 +- test/hil/tinyusb.json | 10 ++++++---- 5 files changed, 11 insertions(+), 5 deletions(-) (limited to 'hw') diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt index 95fb2e440..00e288bad 100644 --- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt +++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt @@ -69,6 +69,7 @@ if (DEFINED LOG) endif() if(DEFINED CFLAGS_CLI) + separate_arguments(CFLAGS_CLI) list(APPEND compile_definitions ${CFLAGS_CLI}) endif() diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 3f2872a30..82e3badb3 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -206,6 +206,7 @@ function(family_configure_common TARGET RTOS) # compile define from command line if(DEFINED CFLAGS_CLI) + separate_arguments(CFLAGS_CLI) target_compile_options(${TARGET} PUBLIC ${CFLAGS_CLI}) endif() @@ -291,6 +292,7 @@ function(family_add_tinyusb TARGET OPT_MCU RTOS) # compile define from command line if(DEFINED CFLAGS_CLI) + separate_arguments(CFLAGS_CLI) target_compile_options(${TARGET}-tinyusb PUBLIC ${CFLAGS_CLI}) endif() diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index 8f01eac74..b2b01b1cf 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -191,6 +191,7 @@ function(family_configure_target TARGET RTOS) # compile define from command line if(DEFINED CFLAGS_CLI) + separate_arguments(CFLAGS_CLI) target_compile_options(${TARGET} PUBLIC ${CFLAGS_CLI}) endif() diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index cfae646a1..dd66bfb6f 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -147,7 +147,7 @@ static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) { return (uint16_t) (cbw->total_bytes / block_count); } -uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) { +static uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) { uint8_t status = MSC_CSW_STATUS_PASSED; uint16_t const block_count = rdwr10_get_blockcount(cbw); diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json index 580481b61..7393226eb 100644 --- a/test/hil/tinyusb.json +++ b/test/hil/tinyusb.json @@ -14,13 +14,14 @@ "name": "esptool", "uid": "4ea4f48f6bc3ee11bbb9d00f9e1b1c54", "args": "-b 1500000" - } + }, + "comment": "Use TS3USB30 mux to test both device and host" }, { "name": "espressif_s3_devkitm", "uid": "84F703C084E4", "build" : { - "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE CFG_TUH_DWC2_DMA_ENABLE"] + "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE"] }, "tests": { "only": ["device/cdc_msc_freertos", "device/hid_composite_freertos"] @@ -133,7 +134,7 @@ "name": "stm32f723disco", "uid": "460029001951373031313335", "build" : { - "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE CFG_TUH_DWC2_DMA_ENABLE"] + "flags_on": ["", "CFG_TUH_DWC2_DMA_ENABLE"] }, "tests": { "device": true, "host": true, "dual": false, @@ -143,7 +144,8 @@ "name": "jlink", "uid": "000776606156", "args": "-device stm32f723ie" - } + }, + "comment": "Device port0 FS (slave only), Host port1 HS with DMA" }, { "name": "stm32h743nucleo", -- cgit v1.3.1 From dbc2c8d9720593ce4b0bbd0c96b3b91f81ce15bb Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Wed, 27 Nov 2024 18:28:12 +0700 Subject: Fix missing protoype warning, change TUD_EPBUF_TYPE_DEF order (#2889) * change TUD_EPBUF_TYPE_DEF order * add and fix -Wmissing-prototypes warnings for cmake (skip make) --- .github/workflows/build.yml | 5 +++ .idea/cmake.xml | 8 ++--- examples/build_system/make/toolchain/gcc_common.mk | 1 + hw/bsp/board.c | 19 +++++----- src/CMakeLists.txt | 1 + src/class/audio/audio_device.c | 2 +- src/class/bth/bth_device.c | 2 +- src/class/net/ncm_device.c | 8 ++--- src/class/usbtmc/usbtmc_device.c | 2 +- src/class/video/video_device.h | 2 ++ src/common/tusb_types.h | 2 +- src/portable/dialog/da146xx/dcd_da146xx.c | 1 + src/portable/microchip/samd/dcd_samd.c | 2 +- src/portable/microchip/samg/dcd_samg.c | 40 ++++++++-------------- src/portable/nordic/nrf5x/dcd_nrf5x.c | 3 +- src/portable/nxp/khci/hcd_khci.c | 2 +- src/portable/nxp/lpc17_40/hcd_lpc17_40.c | 1 + src/portable/renesas/rusb2/rusb2_common.c | 1 + 18 files changed, 54 insertions(+), 48 deletions(-) (limited to 'hw') diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 8d5bcbc67..283b72061 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -118,6 +118,8 @@ jobs: runs-on: [self-hosted, Linux, X64, hifiphile] env: BUILD_ARGS: ${{ join(fromJSON(needs.set-matrix.outputs.json)['arm-iar'], ' ') }} + IAR_LMS_CLOUD_URL: https://license.cloud.iar.com + IAR_LMS_BEARER_TOKEN: ${{ secrets.IAR_LMS_BEARER_TOKEN }} steps: - name: Clean workspace run: | @@ -125,6 +127,9 @@ jobs: rm -rf "${{ github.workspace }}" mkdir -p "${{ github.workspace }}" + - name: Toolchain version + run: iccarm --version + - name: Checkout TinyUSB uses: actions/checkout@v4 diff --git a/.idea/cmake.xml b/.idea/cmake.xml index aa15374b9..25a8513ca 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -61,7 +61,7 @@ - + @@ -83,7 +83,7 @@ - + @@ -100,7 +100,7 @@ - + @@ -108,7 +108,7 @@ - + diff --git a/examples/build_system/make/toolchain/gcc_common.mk b/examples/build_system/make/toolchain/gcc_common.mk index 6986d8bba..0cbb6774d 100644 --- a/examples/build_system/make/toolchain/gcc_common.mk +++ b/examples/build_system/make/toolchain/gcc_common.mk @@ -31,6 +31,7 @@ CFLAGS += \ -Wreturn-type \ -Wredundant-decls \ +# -Wmissing-prototypes \ # conversion is too strict for most mcu driver, may be disable sign/int/arith-conversion # -Wconversion diff --git a/hw/bsp/board.c b/hw/bsp/board.c index e3a4be461..5bcdb7f15 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -39,6 +39,9 @@ #define sys_read _read #endif +int sys_write(int fhdl, const char *buf, size_t count) TU_ATTR_USED; +int sys_read(int fhdl, char *buf, size_t count) TU_ATTR_USED; + #if defined(LOGGER_RTT) // Logging with RTT @@ -46,13 +49,13 @@ #if !(defined __SES_ARM) && !(defined __SES_RISCV) && !(defined __CROSSWORKS_ARM) #include "SEGGER_RTT.h" -TU_ATTR_USED int sys_write(int fhdl, const char *buf, size_t count) { +int sys_write(int fhdl, const char *buf, size_t count) { (void) fhdl; SEGGER_RTT_Write(0, (const char *) buf, (int) count); return (int) count; } -TU_ATTR_USED int sys_read(int fhdl, char *buf, size_t count) { +int sys_read(int fhdl, char *buf, size_t count) { (void) fhdl; int rd = (int) SEGGER_RTT_Read(0, buf, count); return (rd > 0) ? rd : -1; @@ -64,7 +67,7 @@ TU_ATTR_USED int sys_read(int fhdl, char *buf, size_t count) { // Logging with SWO for ARM Cortex #include "board_mcu.h" -TU_ATTR_USED int sys_write (int fhdl, const char *buf, size_t count) { +int sys_write (int fhdl, const char *buf, size_t count) { (void) fhdl; uint8_t const* buf8 = (uint8_t const*) buf; @@ -75,7 +78,7 @@ TU_ATTR_USED int sys_write (int fhdl, const char *buf, size_t count) { return (int) count; } -TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) { +int sys_read (int fhdl, char *buf, size_t count) { (void) fhdl; (void) buf; (void) count; @@ -85,12 +88,12 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) { #else // Default logging with on-board UART -TU_ATTR_USED int sys_write (int fhdl, const char *buf, size_t count) { +int sys_write (int fhdl, const char *buf, size_t count) { (void) fhdl; return board_uart_write(buf, (int) count); } -TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) { +int sys_read (int fhdl, char *buf, size_t count) { (void) fhdl; int rd = board_uart_read((uint8_t*) buf, (int) count); return (rd > 0) ? rd : -1; @@ -98,12 +101,12 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) { #endif -//TU_ATTR_USED int _close(int fhdl) { +//int _close(int fhdl) { // (void) fhdl; // return 0; //} -//TU_ATTR_USED int _fstat(int file, struct stat *st) { +//int _fstat(int file, struct stat *st) { // memset(st, 0, sizeof(*st)); // st->st_mode = S_IFCHR; //} diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 272962332..cf6878389 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -67,6 +67,7 @@ function(add_tinyusb TARGET) -Wunused-function -Wreturn-type -Wredundant-decls + -Wmissing-prototypes ) elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 66430feab..cd4183cc3 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -490,13 +490,13 @@ TU_ATTR_WEAK bool tud_audio_feedback_format_correction_cb(uint8_t func_id) { (void) func_id; return CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION; } -#endif TU_ATTR_WEAK TU_ATTR_FAST_FUNC void tud_audio_feedback_interval_isr(uint8_t func_id, uint32_t frame_number, uint8_t interval_shift) { (void) func_id; (void) frame_number; (void) interval_shift; } +#endif #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP TU_ATTR_WEAK void tud_audio_int_done_cb(uint8_t rhport) { diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c index 5e533cf35..45cbf2d98 100755 --- a/src/class/bth/bth_device.c +++ b/src/class/bth/bth_device.c @@ -52,7 +52,7 @@ typedef struct { typedef struct { TUD_EPBUF_DEF(epout_buf, CFG_TUD_BTH_DATA_EPSIZE); - TUD_EPBUF_TYPE_DEF(hci_cmd, bt_hci_cmd_t); + TUD_EPBUF_TYPE_DEF(bt_hci_cmd_t, hci_cmd); } btd_epbuf_t; //--------------------------------------------------------------------+ diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c index c97c66a4e..4e6088340 100644 --- a/src/class/net/ncm_device.c +++ b/src/class/net/ncm_device.c @@ -118,14 +118,14 @@ typedef struct { typedef struct { struct { - TUD_EPBUF_TYPE_DEF(ntb, recv_ntb_t); + TUD_EPBUF_TYPE_DEF(recv_ntb_t, ntb); } recv[RECV_NTB_N]; struct { - TUD_EPBUF_TYPE_DEF(ntb, xmit_ntb_t); + TUD_EPBUF_TYPE_DEF(xmit_ntb_t, ntb); } xmit[XMIT_NTB_N]; - TUD_EPBUF_TYPE_DEF(epnotif, ncm_notify_t); + TUD_EPBUF_TYPE_DEF(ncm_notify_t, epnotif); } ncm_epbuf_t; static ncm_interface_t ncm_interface; @@ -748,7 +748,7 @@ void tud_network_recv_renew(void) { /** * Same as tud_network_recv_renew() but knows \a rhport */ -void tud_network_recv_renew_r(uint8_t rhport) { +static void tud_network_recv_renew_r(uint8_t rhport) { TU_LOG_DRV("tud_network_recv_renew_r(%d)\n", rhport); ncm_interface.rhport = rhport; diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index 37634c38e..abde9679f 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -180,7 +180,7 @@ osal_mutex_t usbtmcLock; #define criticalEnter() do { (void) osal_mutex_lock(usbtmcLock,OSAL_TIMEOUT_WAIT_FOREVER); } while (0) #define criticalLeave() do { (void) osal_mutex_unlock(usbtmcLock); } while (0) -bool atomicChangeState(usbtmcd_state_enum expectedState, usbtmcd_state_enum newState) +static bool atomicChangeState(usbtmcd_state_enum expectedState, usbtmcd_state_enum newState) { bool ret = true; criticalEnter(); diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h index 92930c013..648a221d5 100644 --- a/src/class/video/video_device.h +++ b/src/class/video/video_device.h @@ -40,6 +40,8 @@ extern "C" { // CFG_TUD_VIDEO > 1 //--------------------------------------------------------------------+ +bool tud_video_n_connected(uint_fast8_t ctl_idx); + /** Return true if streaming * * @param[in] ctl_idx Destination control interface index diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 533c1bcea..9e4d9380c 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -47,7 +47,7 @@ } // Declare an endpoint buffer with a type -#define TUD_EPBUF_TYPE_DEF(_name, _type) \ +#define TUD_EPBUF_TYPE_DEF(_type, _name) \ union { \ CFG_TUD_MEM_ALIGN _type _name; \ uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \ diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index 887f59588..56ecb7575 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -896,6 +896,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void) return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0; } +void tusb_vbus_changed(bool present); void tusb_vbus_changed(bool present) { if (present && !_dcd.vbus_present) diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c index 0c96f6ac4..357aa1549 100644 --- a/src/portable/microchip/samd/dcd_samd.c +++ b/src/portable/microchip/samd/dcd_samd.c @@ -335,7 +335,7 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) //--------------------------------------------------------------------+ // Interrupt Handler //--------------------------------------------------------------------+ -void maybe_transfer_complete(void) { +static void maybe_transfer_complete(void) { uint32_t epints = USB->DEVICE.EPINTSMRY.reg; for (uint8_t epnum = 0; epnum < USB_EPT_NUM; epnum++) { diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c index c88b31514..a5c768839 100644 --- a/src/portable/microchip/samg/dcd_samg.c +++ b/src/portable/microchip/samg/dcd_samg.c @@ -52,37 +52,31 @@ typedef struct // Endpoint 0-5, each can only be either OUT or In xfer_desc_t _dcd_xfer[EP_COUNT]; -void xfer_epsize_set(xfer_desc_t* xfer, uint16_t epsize) -{ +TU_ATTR_ALWAYS_INLINE static inline void xfer_epsize_set(xfer_desc_t* xfer, uint16_t epsize) { xfer->epsize = epsize; } -void xfer_begin(xfer_desc_t* xfer, uint8_t * buffer, uint16_t total_bytes) -{ +TU_ATTR_ALWAYS_INLINE static inline void xfer_begin(xfer_desc_t* xfer, uint8_t * buffer, uint16_t total_bytes) { xfer->buffer = buffer; // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API xfer->total_len = total_bytes; xfer->actual_len = 0; } -void xfer_end(xfer_desc_t* xfer) -{ +TU_ATTR_ALWAYS_INLINE static inline void xfer_end(xfer_desc_t* xfer) { xfer->buffer = NULL; // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API xfer->total_len = 0; xfer->actual_len = 0; } -uint16_t xfer_packet_len(xfer_desc_t* xfer) -{ +TU_ATTR_ALWAYS_INLINE static inline uint16_t xfer_packet_len(xfer_desc_t* xfer) { // also cover zero-length packet return tu_min16(xfer->total_len - xfer->actual_len, xfer->epsize); } -void xfer_packet_done(xfer_desc_t* xfer) -{ +TU_ATTR_ALWAYS_INLINE static inline void xfer_packet_done(xfer_desc_t* xfer) { uint16_t const xact_len = xfer_packet_len(xfer); - xfer->buffer += xact_len; xfer->actual_len += xact_len; } @@ -90,19 +84,15 @@ void xfer_packet_done(xfer_desc_t* xfer) //------------- Transaction helpers -------------// // Write data to EP FIFO, return number of written bytes -static void xact_ep_write(uint8_t epnum, uint8_t* buffer, uint16_t xact_len) -{ - for(uint16_t i=0; iUDP_FDR[epnum] = (uint32_t) buffer[i]; } } // Read data from EP FIFO -static void xact_ep_read(uint8_t epnum, uint8_t* buffer, uint16_t xact_len) -{ - for(uint16_t i=0; iUDP_FDR[epnum]; } } @@ -112,24 +102,24 @@ static void xact_ep_read(uint8_t epnum, uint8_t* buffer, uint16_t xact_len) #define CSR_NO_EFFECT_1_ALL (UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1 | UDP_CSR_STALLSENT | UDP_CSR_RXSETUP | UDP_CSR_TXCOMP) // Per Specs: CSR need synchronization each write -static inline void csr_write(uint8_t epnum, uint32_t value) -{ +TU_ATTR_ALWAYS_INLINE static inline void csr_write(uint8_t epnum, uint32_t value) { uint32_t const csr = value; UDP->UDP_CSR[epnum] = csr; volatile uint32_t nop_count; - for (nop_count = 0; nop_count < 20; nop_count ++) __NOP(); + for (nop_count = 0; nop_count < 20; nop_count ++) { + __NOP(); + } } // Per Specs: CSR need synchronization each write -static inline void csr_set(uint8_t epnum, uint32_t mask) +TU_ATTR_ALWAYS_INLINE static inline void csr_set(uint8_t epnum, uint32_t mask) { csr_write(epnum, UDP->UDP_CSR[epnum] | CSR_NO_EFFECT_1_ALL | mask); } // Per Specs: CSR need synchronization each write -static inline void csr_clear(uint8_t epnum, uint32_t mask) -{ +TU_ATTR_ALWAYS_INLINE static inline void csr_clear(uint8_t epnum, uint32_t mask) { csr_write(epnum, (UDP->UDP_CSR[epnum] | CSR_NO_EFFECT_1_ALL) & ~mask); } diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index 3f53ee26e..5bfedae17 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -530,7 +530,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { /*------------------------------------------------------------------*/ /* Interrupt Handler *------------------------------------------------------------------*/ -void bus_reset(void) { +static void bus_reset(void) { // 6.35.6 USB controller automatically disabled all endpoints (except control) NRF_USBD->EPOUTEN = 1UL; NRF_USBD->EPINEN = 1UL; @@ -901,6 +901,7 @@ static void hfclk_disable(void) { // Therefore this function must be called to handle USB power event by // - nrfx_power_usbevt_init() : if Softdevice is not used or enabled // - SoftDevice SOC event : if SD is used and enabled +void tusb_hal_nrf_power_event(uint32_t event); void tusb_hal_nrf_power_event(uint32_t event) { // Value is chosen to be as same as NRFX_POWER_USB_EVT_* in nrfx_power.h enum { diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c index f5ca73c18..056dbf40b 100644 --- a/src/portable/nxp/khci/hcd_khci.c +++ b/src/portable/nxp/khci/hcd_khci.c @@ -140,7 +140,7 @@ typedef struct CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(512) static hcd_data_t _hcd; //CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t _rx_buf[1024]; -int find_pipe(uint8_t dev_addr, uint8_t ep_addr) +static int find_pipe(uint8_t dev_addr, uint8_t ep_addr) { /* Find the target pipe */ int num; diff --git a/src/portable/nxp/lpc17_40/hcd_lpc17_40.c b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c index 372dcf51f..090d1ba69 100644 --- a/src/portable/nxp/lpc17_40/hcd_lpc17_40.c +++ b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c @@ -30,6 +30,7 @@ (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX) #include "chip.h" +#include "host/hcd.h" void hcd_int_enable(uint8_t rhport) { diff --git a/src/portable/renesas/rusb2/rusb2_common.c b/src/portable/renesas/rusb2/rusb2_common.c index 850060777..72e65736b 100644 --- a/src/portable/renesas/rusb2/rusb2_common.c +++ b/src/portable/renesas/rusb2/rusb2_common.c @@ -45,6 +45,7 @@ rusb2_controller_t rusb2_controller[] = { }; // Application API for setting IRQ number. May throw warnings for missing prototypes. +void tusb_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum); void tusb_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) { rusb2_controller[rhport].irqnum = irqnum; } -- cgit v1.3.1 From 568c785da10e35eb8d5298a4cf63854cbf9dbfd4 Mon Sep 17 00:00:00 2001 From: "David (Pololu)" Date: Tue, 8 Oct 2024 12:30:44 -0700 Subject: Add support for the STM32C0 and the NUCLEO-C071RB. --- README.rst | 2 +- docs/reference/supported.rst | 2 +- hw/bsp/board_mcu.h | 3 + .../boards/stm32c071nucleo/STM32C071RBTX_FLASH.ld | 187 ++++++++++++++ hw/bsp/stm32c0/boards/stm32c071nucleo/board.cmake | 10 + hw/bsp/stm32c0/boards/stm32c071nucleo/board.h | 58 +++++ hw/bsp/stm32c0/boards/stm32c071nucleo/board.mk | 13 + hw/bsp/stm32c0/family.c | 199 +++++++++++++++ hw/bsp/stm32c0/family.cmake | 118 +++++++++ hw/bsp/stm32c0/family.mk | 52 ++++ hw/bsp/stm32c0/stm32c0xx_hal_conf.h | 284 +++++++++++++++++++++ src/common/tusb_mcu.h | 5 + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 1 + src/portable/st/stm32_fsdev/fsdev_stm32.h | 16 ++ src/tusb_option.h | 1 + tools/get_deps.py | 18 +- 16 files changed, 961 insertions(+), 8 deletions(-) create mode 100644 hw/bsp/stm32c0/boards/stm32c071nucleo/STM32C071RBTX_FLASH.ld create mode 100644 hw/bsp/stm32c0/boards/stm32c071nucleo/board.cmake create mode 100644 hw/bsp/stm32c0/boards/stm32c071nucleo/board.h create mode 100644 hw/bsp/stm32c0/boards/stm32c071nucleo/board.mk create mode 100644 hw/bsp/stm32c0/family.c create mode 100644 hw/bsp/stm32c0/family.cmake create mode 100644 hw/bsp/stm32c0/family.mk create mode 100644 hw/bsp/stm32c0/stm32c0xx_hal_conf.h (limited to 'hw') diff --git a/README.rst b/README.rst index 502115c25..db36cad3b 100644 --- a/README.rst +++ b/README.rst @@ -153,7 +153,7 @@ Following CPUs are supported, check out `Supported Devices`_ for comprehensive l +--------------+------------------------------------------------------------+ | Sony | CXD56 | +--------------+------------------------------------------------------------+ -| ST STM32 | F0, F1, F2, F3, F4, F7, G0, G4, H5, H7, | +| ST STM32 | C0, F0, F1, F2, F3, F4, F7, G0, G4, H5, H7, | | | | | | L0, L1, L4, L4+, L5, U5, WB | +--------------+------------------------------------------------------------+ diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index da2431415..cbd6c4786 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -97,7 +97,7 @@ Supported MCUs | +-----------------------------+--------+------+-----------+------------------------+-------------------+ | | F3 | âś” | âś– | âś– | stm32_fsdev | | | +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | G0, H5 | âś” | âś– | âś– | stm32_fsdev | | +| | C0, G0, H5 | âś” | | âś– | stm32_fsdev | | | +-----------------------------+--------+------+-----------+------------------------+-------------------+ | | G4 | âś” | âś– | âś– | stm32_fsdev | | | +-----------------------------+--------+------+-----------+------------------------+-------------------+ diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index d3a33cf36..e720cd747 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -107,6 +107,9 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32G0 #include "stm32g0xx.h" +#elif CFG_TUSB_MCU == OPT_MCU_STM32C0 + #include "stm32c0xx.h" + #elif CFG_TUSB_MCU == OPT_MCU_CXD56 // no header needed diff --git a/hw/bsp/stm32c0/boards/stm32c071nucleo/STM32C071RBTX_FLASH.ld b/hw/bsp/stm32c0/boards/stm32c071nucleo/STM32C071RBTX_FLASH.ld new file mode 100644 index 000000000..bd2968889 --- /dev/null +++ b/hw/bsp/stm32c0/boards/stm32c071nucleo/STM32C071RBTX_FLASH.ld @@ -0,0 +1,187 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** Abstract : Linker script for NUCLEO-C071RB Board embedding STM32C071RBTx Device from stm32c0 series +** 128KBytes FLASH +** 24KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 24K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/stm32c0/boards/stm32c071nucleo/board.cmake b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.cmake new file mode 100644 index 000000000..2a319a73c --- /dev/null +++ b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.cmake @@ -0,0 +1,10 @@ +set(MCU_VARIANT stm32c071xx) +set(JLINK_DEVICE stm32c071rb) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32C071RBTx_FLASH.ld) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + STM32C071xx + ) +endfunction() diff --git a/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h new file mode 100644 index 000000000..f08762736 --- /dev/null +++ b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h @@ -0,0 +1,58 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * Copyright (c) 2023, HiFiPhile + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +// Green LED +#define GREEN_LED_PORT GPIOA +#define GREEN_LED_PIN GPIO_PIN_5 +#define GREEN_LED_STATE_ON 1 + +// Blue LED +#define BLUE_LED_PORT GPIOC +#define BLUE_LED_PIN GPIO_PIN_9 +#define BLUE_LED_STATE_ON 0 + +// Generic LED +#define LED_PORT GREEN_LED_PORT +#define LED_PIN GREEN_LED_PIN +#define LED_STATE_ON GREEN_LED_STATE_ON + +// Button +#define BUTTON_PORT GPIOC +#define BUTTON_PIN GPIO_PIN_13 +#define BUTTON_STATE_ACTIVE 0 + +// Enable UART serial communication with the ST-Link +#define UART_DEV USART2 +#define UART_GPIO_PORT GPIOA +#define UART_GPIO_AF GPIO_AF1_USART2 +#define UART_TX_PIN GPIO_PIN_2 +#define UART_RX_PIN GPIO_PIN_3 + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/stm32c0/boards/stm32c071nucleo/board.mk b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.mk new file mode 100644 index 000000000..67a9b59a8 --- /dev/null +++ b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.mk @@ -0,0 +1,13 @@ +CFLAGS += \ + -DSTM32C071xx + +# GCC +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32c071xx.s +LD_FILE_GCC = $(BOARD_PATH)/STM32C071RBTx_FLASH.ld + +# IAR +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32c071xx.s +LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32c071xx_flash.icf + +# For flash-jlink target +JLINK_DEVICE = stm32c071rb diff --git a/hw/bsp/stm32c0/family.c b/hw/bsp/stm32c0/family.c new file mode 100644 index 000000000..dba6a8af1 --- /dev/null +++ b/hw/bsp/stm32c0/family.c @@ -0,0 +1,199 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * Copyright (c) 2023 HiFiPhile + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "stm32c0xx_hal.h" +#include "bsp/board_api.h" +#include "board.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB_DRD_FS_IRQHandler(void) { + tud_int_handler(0); +} + +// Startup code generated by STM32CubeIDE uses USB_IRQHandler, while +// stm32c071xx.s from cmsis_device_c0 uses USB_DRD_FS_IRQHandler. +void USB_IRQHandler(void) { + USB_DRD_FS_IRQHandler(); +} + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ +UART_HandleTypeDef UartHandle; + +void board_init(void) { + HAL_Init(); + + // Enable the HSIUSB48 48 MHz oscillator. + RCC->CR |= RCC_CR_HSIUSB48ON; + + // Wait for HSIUSB48 to be ready. + while (!(RCC->CR & RCC_CR_HSIUSB48RDY)) { } + + // Change the SYSCLK source to HSIUSB48. + RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_SYSCLKSOURCE_HSIUSB48; + + // Wait for the SYSCLK source to change. + while ((RCC->CFGR & RCC_CFGR_SWS) >> RCC_CFGR_SWS_Pos != RCC_SYSCLKSOURCE_HSIUSB48) { } + + // Disable HSI48 to save power. + RCC->CR &= ~RCC_CR_HSION; + + // Enable peripheral clocks. + RCC->APBENR1 = RCC_APBENR1_USBEN | RCC_APBENR1_CRSEN | RCC_APBENR1_USART2EN; + RCC->APBENR2 = RCC_APBENR2_USART1EN; + + // Enable all GPIO clocks. + RCC->IOPENR = 0x2F; + + // Turn on CRS to make the HSIUSB48 clock more precise when USB is connected. + CRS->CR |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // Explicitly disable systick to prevent its ISR runs before scheduler start + SysTick->CTRL &= ~1U; + + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB_DRD_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + + // LED + { + GPIO_InitTypeDef gpio_init = { 0 }; + gpio_init.Pin = LED_PIN; + gpio_init.Mode = GPIO_MODE_OUTPUT_PP; + HAL_GPIO_Init(LED_PORT, &gpio_init); + board_led_write(false); + } + + // Button + { + GPIO_InitTypeDef gpio_init = { 0 }; + gpio_init.Pin = BUTTON_PIN; + gpio_init.Mode = GPIO_MODE_INPUT; + gpio_init.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP; + HAL_GPIO_Init(BUTTON_PORT, &gpio_init); + } + +#ifdef UART_DEV + // UART + { + GPIO_InitTypeDef gpio_init = { 0 }; + gpio_init.Pin = UART_TX_PIN | UART_RX_PIN; + gpio_init.Mode = GPIO_MODE_AF_PP; + gpio_init.Pull = GPIO_PULLUP; + gpio_init.Speed = GPIO_SPEED_FREQ_HIGH; + gpio_init.Alternate = UART_GPIO_AF; + HAL_GPIO_Init(UART_GPIO_PORT, &gpio_init); + } + + UartHandle = (UART_HandleTypeDef){ + .Instance = UART_DEV, + .Init.BaudRate = CFG_BOARD_UART_BAUDRATE, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.OverSampling = UART_OVERSAMPLING_16, + .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT + }; + HAL_UART_Init(&UartHandle); +#endif +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) { + GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON)); + HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state); +} + +uint32_t board_button_read(void) { + return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + (void) max_len; + volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE; + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = stm32_uuid[0]; + id32[1] = stm32_uuid[1]; + id32[2] = stm32_uuid[2]; + + return len; +} + +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) { +#ifdef UART_DEV + HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff); + return len; +#else + (void) buf; + (void) len; + (void) UartHandle; + return 0; +#endif +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) { + system_ticks++; + HAL_IncTick(); +} + +uint32_t board_millis(void) { + return system_ticks; +} +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { + +} diff --git a/hw/bsp/stm32c0/family.cmake b/hw/bsp/stm32c0/family.cmake new file mode 100644 index 000000000..ebfb532c7 --- /dev/null +++ b/hw/bsp/stm32c0/family.cmake @@ -0,0 +1,118 @@ +include_guard() + +set(ST_FAMILY c0) +set(ST_PREFIX stm32${ST_FAMILY}xx) + +set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver) +set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY}) +set(CMSIS_5 ${TOP}/lib/CMSIS_5) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS STM32C0 CACHE INTERNAL "") +set(OPENOCD_OPTION "-f interface/stlink.cfg -f target/stm32c0x.cfg") + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s) + + set(LD_FILE_Clang ${LD_FILE_GNU}) + set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) + + add_library(${BOARD_TARGET} STATIC + ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMSIS_5}/CMSIS/Core/Include + ${ST_CMSIS}/Include + ${ST_HAL_DRIVER}/Inc + ) +# target_compile_options(${BOARD_TARGET} PUBLIC) +# target_compile_definitions(${BOARD_TARGET} PUBLIC) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_STM32C0 ${RTOS}) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + ${TOP}/src/portable/st/typec/typec_stm32.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + + # Link dependencies + target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + + # Flashing + family_flash_jlink(${TARGET}) + family_flash_stlink(${TARGET}) + #family_flash_openocd(${TARGET}) +endfunction() diff --git a/hw/bsp/stm32c0/family.mk b/hw/bsp/stm32c0/family.mk new file mode 100644 index 000000000..2380d76c3 --- /dev/null +++ b/hw/bsp/stm32c0/family.mk @@ -0,0 +1,52 @@ +ST_FAMILY = c0 +DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver + +ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) +ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver + +include $(TOP)/$(BOARD_PATH)/board.mk +CPU_CORE ?= cortex-m0plus + +# -------------- +# Compiler Flags +# -------------- +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_STM32C0 + +# GCC Flags +CFLAGS_GCC += \ + -flto \ + +# suppress warning caused by vendor mcu driver +CFLAGS_GCC += -Wno-error=cast-align -Wno-error=unused-parameter + +LDFLAGS_GCC += \ + -nostdlib -nostartfiles \ + --specs=nosys.specs --specs=nano.specs + +# ----------------- +# Sources & Include +# ----------------- + +SRC_C += \ + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ + $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(ST_CMSIS)/Include \ + $(TOP)/$(ST_HAL_DRIVER)/Inc + +# flash target using on-board stlink +flash: flash-stlink diff --git a/hw/bsp/stm32c0/stm32c0xx_hal_conf.h b/hw/bsp/stm32c0/stm32c0xx_hal_conf.h new file mode 100644 index 000000000..678b6ee0d --- /dev/null +++ b/hw/bsp/stm32c0/stm32c0xx_hal_conf.h @@ -0,0 +1,284 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32c0xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32c0xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_CONF_H +#define STM32C0xx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED + +/* ########################## Register Callbacks selection ############################## */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32c0xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE (48000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz +The real value may vary depending on the variations +in voltage and temperature.*/ +#if !defined (LSI_STARTUP_TIME) +#define LSI_STARTUP_TIME 130UL /*!< Time out for LSI start up, in ms */ +#endif /* LSI_STARTUP_TIME */ +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S1 peripheral + * This value is used by the RCC HAL module to compute the I2S1 clock source + * frequency. + */ +#if !defined (EXTERNAL_I2S1_CLOCK_VALUE) +#define EXTERNAL_I2S1_CLOCK_VALUE (12288000UL) /*!< Value of the I2S1 External clock source in Hz*/ +#endif /* EXTERNAL_I2S1_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 3U /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include modules header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32c0xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32c0xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32c0xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32c0xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32c0xx_hal_adc.h" + #include "stm32c0xx_hal_adc_ex.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32c0xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32c0xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32c0xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32c0xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32c0xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32c0xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32c0xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32c0xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32c0xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32c0xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32c0xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32c0xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32c0xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32c0xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32c0xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32c0xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32c0xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32c0xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for functions parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index d43e5f2ba..0c64c041c 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -238,6 +238,11 @@ #define TUP_USBIP_FSDEV_STM32 #define TUP_DCD_ENDPOINT_MAX 8 +#elif TU_CHECK_MCU(OPT_MCU_STM32C0) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_STM32 + #define TUP_DCD_ENDPOINT_MAX 8 + #elif TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1) #define TUP_USBIP_FSDEV #define TUP_USBIP_FSDEV_STM32 diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index d921429e2..ef58957bb 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -40,6 +40,7 @@ * F102, F103 512 byte buffer; no internal D+ pull-up (maybe many more changes?) * F302xB/C, F303xB/C, F373 512 byte buffer; no internal D+ pull-up * F302x6/8, F302xD/E2, F303xD/E 1024 byte buffer; no internal D+ pull-up + * C0 2048 byte buffer; 32-bit bus; host mode * G0 2048 byte buffer; 32-bit bus; host mode * G4 1024 byte buffer * H5 2048 byte buffer; 32-bit bus; host mode diff --git a/src/portable/st/stm32_fsdev/fsdev_stm32.h b/src/portable/st/stm32_fsdev/fsdev_stm32.h index 03ea4c67e..ccf31e035 100644 --- a/src/portable/st/stm32_fsdev/fsdev_stm32.h +++ b/src/portable/st/stm32_fsdev/fsdev_stm32.h @@ -104,6 +104,20 @@ #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY #define USB_CNTR_FSUSP USB_CNTR_SUSPEN +#elif CFG_TUSB_MCU == OPT_MCU_STM32C0 + #include "stm32c0xx.h" + #define FSDEV_PMA_SIZE (2048u) + #define USB USB_DRD_FS + #define USB_EP_CTR_RX USB_CHEP_VTRX + #define USB_EP_CTR_TX USB_CHEP_VTTX + #define USB_EPREG_MASK USB_CHEP_REG_MASK + #define USB_CNTR_FRES USB_CNTR_USBRST + #define USB_CNTR_RESUME USB_CNTR_L2RES + #define USB_ISTR_EP_ID USB_ISTR_IDN + #define USB_EPADDR_FIELD USB_CHEP_ADDR + #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY + #define USB_CNTR_FSUSP USB_CNTR_SUSPEN + #elif CFG_TUSB_MCU == OPT_MCU_STM32H5 #include "stm32h5xx.h" #define FSDEV_PMA_SIZE (2048u) @@ -260,6 +274,8 @@ static const IRQn_Type fsdev_irq[] = { #else USB_UCPD1_2_IRQn, #endif + #elif CFG_TUSB_MCU == OPT_MCU_STM32C0 + USB_DRD_FS_IRQn, #elif TU_CHECK_MCU(OPT_MCU_STM32G4, OPT_MCU_STM32L1) USB_HP_IRQn, USB_LP_IRQn, diff --git a/src/tusb_option.h b/src/tusb_option.h index 42994cb03..dca1e4109 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -93,6 +93,7 @@ #define OPT_MCU_STM32H5 315 ///< ST H5 #define OPT_MCU_STM32U0 316 ///< ST U0 #define OPT_MCU_STM32H7RS 317 ///< ST F7RS +#define OPT_MCU_STM32C0 318 ///< ST C0 // Sony #define OPT_MCU_CXD56 400 ///< SONY CXD56 diff --git a/tools/get_deps.py b/tools/get_deps.py index 6d0ef9d0c..58709414c 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -73,6 +73,9 @@ deps_optional = { 'hw/mcu/sony/cxd56/spresense-exported-sdk': ['https://github.com/sonydevworld/spresense-exported-sdk.git', '2ec2a1538362696118dc3fdf56f33dacaf8f4067', 'spresense'], + 'hw/mcu/st/cmsis_device_c0': ['https://github.com/STMicroelectronics/cmsis_device_c0.git', + 'fb56b1b70c73b74eacda2a4bcc36886444364ab3', + 'stm32c0'], 'hw/mcu/st/cmsis_device_f0': ['https://github.com/STMicroelectronics/cmsis_device_f0.git', '2fc25ee22264bc27034358be0bd400b893ef837e', 'stm32f0'], @@ -124,6 +127,9 @@ deps_optional = { 'hw/mcu/st/stm32-mfxstm32l152': ['https://github.com/STMicroelectronics/stm32-mfxstm32l152.git', '7f4389efee9c6a655b55e5df3fceef5586b35f9b', 'stm32h7'], + 'hw/mcu/st/stm32c0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32c0xx_hal_driver.git', + '41253e2f1d7ae4a4d0c379cf63f5bcf71fcf8eb3', + 'stm32c0'], 'hw/mcu/st/stm32f0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git', '0e95cd88657030f640a11e690a8a5186c7712ea5', 'stm32f0'], @@ -189,12 +195,12 @@ deps_optional = { 'ch32f20x'], 'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git', '20285262657d1b482d132d20d755c8c330d55c1f', - 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x' - 'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43' - 'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5' - 'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb' - 'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg' - 'tm4c'], + 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x ' + 'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 ' + 'stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 ' + 'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb ' + 'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg ' + 'tm4c '], 'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git', 'e73e04ca63495672d955f9268e003cffe168fcd8', 'lpc55'], -- cgit v1.3.1 From f090b642271710b33c029e825ee2afe139195c73 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 27 Nov 2024 22:47:19 +0700 Subject: enable ci for stm32c0, fix build issue with video example and clang --- .github/workflows/ci_set_matrix.py | 2 +- hw/bsp/stm32c0/FreeRTOSConfig/FreeRTOSConfig.h | 149 ++++++++++++++++ .../boards/stm32c071nucleo/STM32C071RBTX_FLASH.ld | 187 --------------------- .../boards/stm32c071nucleo/STM32C071RBTx_FLASH.ld | 187 +++++++++++++++++++++ hw/bsp/stm32c0/family.cmake | 5 +- hw/bsp/stm32c0/family.mk | 3 +- 6 files changed, 342 insertions(+), 191 deletions(-) create mode 100644 hw/bsp/stm32c0/FreeRTOSConfig/FreeRTOSConfig.h delete mode 100644 hw/bsp/stm32c0/boards/stm32c071nucleo/STM32C071RBTX_FLASH.ld create mode 100644 hw/bsp/stm32c0/boards/stm32c071nucleo/STM32C071RBTx_FLASH.ld (limited to 'hw') diff --git a/.github/workflows/ci_set_matrix.py b/.github/workflows/ci_set_matrix.py index 705dcac94..78fcac68a 100755 --- a/.github/workflows/ci_set_matrix.py +++ b/.github/workflows/ci_set_matrix.py @@ -36,7 +36,7 @@ family_list = { "samd11 saml2x": ["arm-gcc", "arm-clang"], "samd21": ["arm-gcc", "arm-clang"], "samd5x_e5x samg": ["arm-gcc", "arm-clang"], - "stm32f0 stm32f1 stm32f2 stm32f3": ["arm-gcc", "arm-clang", "arm-iar"], + "stm32c0 stm32f0 stm32f1 stm32f2 stm32f3": ["arm-gcc", "arm-clang", "arm-iar"], "stm32f4": ["arm-gcc", "arm-clang", "arm-iar"], "stm32f7": ["arm-gcc", "arm-clang", "arm-iar"], "stm32g0 stm32g4 stm32h5": ["arm-gcc", "arm-clang", "arm-iar"], diff --git a/hw/bsp/stm32c0/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/stm32c0/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..4996b06cf --- /dev/null +++ b/hw/bsp/stm32c0/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,149 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "stm32c0xx.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 0 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 200 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS 2 + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<FLASH - - /* The program code and other data into "FLASH" Rom type memory */ - .text : - { - . = ALIGN(4); - *(.text) /* .text sections (code) */ - *(.text*) /* .text* sections (code) */ - *(.glue_7) /* glue arm to thumb code */ - *(.glue_7t) /* glue thumb to arm code */ - *(.eh_frame) - - KEEP (*(.init)) - KEEP (*(.fini)) - - . = ALIGN(4); - _etext = .; /* define a global symbols at end of code */ - } >FLASH - - /* Constant data into "FLASH" Rom type memory */ - .rodata : - { - . = ALIGN(4); - *(.rodata) /* .rodata sections (constants, strings, etc.) */ - *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ - . = ALIGN(4); - } >FLASH - - .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - *(.ARM.extab* .gnu.linkonce.armextab.*) - . = ALIGN(4); - } >FLASH - - .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - __exidx_start = .; - *(.ARM.exidx*) - __exidx_end = .; - . = ALIGN(4); - } >FLASH - - .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP (*(.preinit_array*)) - PROVIDE_HIDDEN (__preinit_array_end = .); - . = ALIGN(4); - } >FLASH - - .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - PROVIDE_HIDDEN (__init_array_start = .); - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array*)) - PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(4); - } >FLASH - - .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ - { - . = ALIGN(4); - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP (*(SORT(.fini_array.*))) - KEEP (*(.fini_array*)) - PROVIDE_HIDDEN (__fini_array_end = .); - . = ALIGN(4); - } >FLASH - - /* Used by the startup to initialize data */ - _sidata = LOADADDR(.data); - - /* Initialized data sections into "RAM" Ram type memory */ - .data : - { - . = ALIGN(4); - _sdata = .; /* create a global symbol at data start */ - *(.data) /* .data sections */ - *(.data*) /* .data* sections */ - *(.RamFunc) /* .RamFunc sections */ - *(.RamFunc*) /* .RamFunc* sections */ - - . = ALIGN(4); - _edata = .; /* define a global symbol at data end */ - - } >RAM AT> FLASH - - /* Uninitialized data section into "RAM" Ram type memory */ - . = ALIGN(4); - .bss : - { - /* This is used by the startup in order to initialize the .bss section */ - _sbss = .; /* define a global symbol at bss start */ - __bss_start__ = _sbss; - *(.bss) - *(.bss*) - *(COMMON) - - . = ALIGN(4); - _ebss = .; /* define a global symbol at bss end */ - __bss_end__ = _ebss; - } >RAM - - /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ - ._user_heap_stack : - { - . = ALIGN(8); - PROVIDE ( end = . ); - PROVIDE ( _end = . ); - . = . + _Min_Heap_Size; - . = . + _Min_Stack_Size; - . = ALIGN(8); - } >RAM - - /* Remove information from the compiler libraries */ - /DISCARD/ : - { - libc.a ( * ) - libm.a ( * ) - libgcc.a ( * ) - } - - .ARM.attributes 0 : { *(.ARM.attributes) } -} diff --git a/hw/bsp/stm32c0/boards/stm32c071nucleo/STM32C071RBTx_FLASH.ld b/hw/bsp/stm32c0/boards/stm32c071nucleo/STM32C071RBTx_FLASH.ld new file mode 100644 index 000000000..8acd49f9d --- /dev/null +++ b/hw/bsp/stm32c0/boards/stm32c071nucleo/STM32C071RBTx_FLASH.ld @@ -0,0 +1,187 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** Abstract : Linker script for NUCLEO-C071RB Board embedding STM32C071RBTx Device from stm32c0 series +** 128KBytes FLASH +** 24KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 24K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K +} + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM : + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/stm32c0/family.cmake b/hw/bsp/stm32c0/family.cmake index ebfb532c7..ed237838d 100644 --- a/hw/bsp/stm32c0/family.cmake +++ b/hw/bsp/stm32c0/family.cmake @@ -54,8 +54,9 @@ function(add_board_target BOARD_TARGET) ${ST_CMSIS}/Include ${ST_HAL_DRIVER}/Inc ) -# target_compile_options(${BOARD_TARGET} PUBLIC) -# target_compile_definitions(${BOARD_TARGET} PUBLIC) + target_compile_definitions(${BOARD_TARGET} PUBLIC + CFG_EXAMPLE_VIDEO_READONLY + ) update_board(${BOARD_TARGET}) diff --git a/hw/bsp/stm32c0/family.mk b/hw/bsp/stm32c0/family.mk index 2380d76c3..9ff3a2fdf 100644 --- a/hw/bsp/stm32c0/family.mk +++ b/hw/bsp/stm32c0/family.mk @@ -11,7 +11,8 @@ CPU_CORE ?= cortex-m0plus # Compiler Flags # -------------- CFLAGS += \ - -DCFG_TUSB_MCU=OPT_MCU_STM32C0 + -DCFG_TUSB_MCU=OPT_MCU_STM32C0 \ + -DCFG_EXAMPLE_VIDEO_READONLY \ # GCC Flags CFLAGS_GCC += \ -- cgit v1.3.1 From 486e14ea9b66432396089367e61a0480bbb960a9 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 2 Nov 2024 16:46:42 +0100 Subject: Fix CI. --- hw/bsp/imxrt/family.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'hw') diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index d3a228f0f..ce4a6bbc9 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -47,7 +47,7 @@ #endif /* --- Note about USB buffer RAM --- -For M7 core it's recommanded to put USB buffer in DTCM for better performance (flexspi_nor linker default) +For M7 core it's recommended to put USB buffer in DTCM for better performance (flexspi_nor linker default) Otherwise you have to put the buffer in a non-cacheable section by configurate MPU manually or using BOARD_ConfigMPU(): - Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) - (IAR only) Change __NCACHE_REGION_SIZE in linker script to cover the size of non-cacheable section, multiple of 2^N @@ -266,7 +266,7 @@ static void BOARD_ConfigMPU(void) { MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB); - /* Region 7 setting: Memory with Normal type, not shareable, write trough */ + /* Region 7 setting: Memory with Normal type, not shareable, write through */ MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB); #else @@ -287,7 +287,7 @@ static void BOARD_ConfigMPU(void) { #ifdef USE_SDRAM #if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH - /* Region 9 setting: Memory with Normal type, not shareable, write trough */ + /* Region 9 setting: Memory with Normal type, not shareable, write through */ MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB); #else @@ -418,7 +418,7 @@ void BOARD_ConfigMPU(void) { ARM_MPU_Disable(); #if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH - /* Region 0 setting: Memory with Normal type, not shareable, write trough */ + /* Region 0 setting: Memory with Normal type, not shareable, write through */ MPU->RBAR = ARM_MPU_RBAR(0, 0x20200000U); MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB); -- cgit v1.3.1 From 0074ed7c6756d3543dc2e89b0081039001ad230c Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 30 Nov 2024 21:50:50 +0100 Subject: Add bin & hex output to cmake targets. --- hw/bsp/broadcom_32bit/family.cmake | 1 + hw/bsp/broadcom_64bit/family.cmake | 1 + hw/bsp/f1c100s/family.cmake | 1 + hw/bsp/gd32vf103/family.cmake | 1 + hw/bsp/imxrt/family.cmake | 1 + hw/bsp/kinetis_k/family.cmake | 1 + hw/bsp/kinetis_k32l2/family.cmake | 1 + hw/bsp/kinetis_kl/family.cmake | 1 + hw/bsp/lpc11/family.cmake | 1 + hw/bsp/lpc13/family.cmake | 1 + hw/bsp/lpc15/family.cmake | 1 + hw/bsp/lpc17/family.cmake | 1 + hw/bsp/lpc18/family.cmake | 1 + hw/bsp/lpc40/family.cmake | 1 + hw/bsp/lpc43/family.cmake | 1 + hw/bsp/lpc51/family.cmake | 1 + hw/bsp/lpc54/family.cmake | 1 + hw/bsp/lpc55/family.cmake | 1 + hw/bsp/max32650/family.cmake | 1 + hw/bsp/max32666/family.cmake | 1 + hw/bsp/max32690/family.cmake | 1 + hw/bsp/max78002/family.cmake | 1 + hw/bsp/mcx/family.cmake | 1 + hw/bsp/mm32/family.cmake | 1 + hw/bsp/nrf/family.cmake | 1 + hw/bsp/ra/family.cmake | 1 + hw/bsp/stm32c0/family.cmake | 1 + hw/bsp/stm32f0/family.cmake | 1 + hw/bsp/stm32f1/family.cmake | 1 + hw/bsp/stm32f2/family.cmake | 1 + hw/bsp/stm32f3/family.cmake | 1 + hw/bsp/stm32f4/family.cmake | 1 + hw/bsp/stm32f7/family.cmake | 1 + hw/bsp/stm32g0/family.cmake | 1 + hw/bsp/stm32g4/family.cmake | 1 + hw/bsp/stm32h5/family.cmake | 1 + hw/bsp/stm32h7/family.cmake | 1 + hw/bsp/stm32l0/family.cmake | 1 + hw/bsp/stm32l4/family.cmake | 1 + hw/bsp/stm32u5/family.cmake | 1 + hw/bsp/stm32wb/family.cmake | 1 + hw/bsp/xmc4000/family.cmake | 1 + 42 files changed, 42 insertions(+) (limited to 'hw') diff --git a/hw/bsp/broadcom_32bit/family.cmake b/hw/bsp/broadcom_32bit/family.cmake index 93e7d3545..09c32c7d4 100644 --- a/hw/bsp/broadcom_32bit/family.cmake +++ b/hw/bsp/broadcom_32bit/family.cmake @@ -106,5 +106,6 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/broadcom_64bit/family.cmake b/hw/bsp/broadcom_64bit/family.cmake index d790944bc..566daefb3 100644 --- a/hw/bsp/broadcom_64bit/family.cmake +++ b/hw/bsp/broadcom_64bit/family.cmake @@ -113,5 +113,6 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/f1c100s/family.cmake b/hw/bsp/f1c100s/family.cmake index 0903a0143..032dfb77d 100644 --- a/hw/bsp/f1c100s/family.cmake +++ b/hw/bsp/f1c100s/family.cmake @@ -110,5 +110,6 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/gd32vf103/family.cmake b/hw/bsp/gd32vf103/family.cmake index 1441e41de..5ef551f25 100644 --- a/hw/bsp/gd32vf103/family.cmake +++ b/hw/bsp/gd32vf103/family.cmake @@ -117,5 +117,6 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 85440746c..76b0ff664 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -152,6 +152,7 @@ function(family_configure_example TARGET RTOS) family_add_bin_hex(${TARGET}) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) #family_flash_pyocd(${TARGET}) diff --git a/hw/bsp/kinetis_k/family.cmake b/hw/bsp/kinetis_k/family.cmake index c30268629..c621de388 100644 --- a/hw/bsp/kinetis_k/family.cmake +++ b/hw/bsp/kinetis_k/family.cmake @@ -108,6 +108,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) if (DEFINED TEENSY_MCU) diff --git a/hw/bsp/kinetis_k32l2/family.cmake b/hw/bsp/kinetis_k32l2/family.cmake index 406ae99d3..90d35cce3 100644 --- a/hw/bsp/kinetis_k32l2/family.cmake +++ b/hw/bsp/kinetis_k32l2/family.cmake @@ -103,6 +103,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) if (DEFINED TEENSY_MCU) diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake index 85a913d54..21a264e53 100644 --- a/hw/bsp/kinetis_kl/family.cmake +++ b/hw/bsp/kinetis_kl/family.cmake @@ -107,5 +107,6 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/lpc11/family.cmake b/hw/bsp/lpc11/family.cmake index 818600656..13ed4c922 100644 --- a/hw/bsp/lpc11/family.cmake +++ b/hw/bsp/lpc11/family.cmake @@ -100,6 +100,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) endfunction() diff --git a/hw/bsp/lpc13/family.cmake b/hw/bsp/lpc13/family.cmake index f7f5c0180..4d0f0110f 100644 --- a/hw/bsp/lpc13/family.cmake +++ b/hw/bsp/lpc13/family.cmake @@ -97,6 +97,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) endfunction() diff --git a/hw/bsp/lpc15/family.cmake b/hw/bsp/lpc15/family.cmake index 61b47d852..c87001943 100644 --- a/hw/bsp/lpc15/family.cmake +++ b/hw/bsp/lpc15/family.cmake @@ -99,6 +99,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) endfunction() diff --git a/hw/bsp/lpc17/family.cmake b/hw/bsp/lpc17/family.cmake index cccfdac9f..0f7485f0f 100644 --- a/hw/bsp/lpc17/family.cmake +++ b/hw/bsp/lpc17/family.cmake @@ -98,6 +98,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) endfunction() diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake index 309186667..ed948c6e8 100644 --- a/hw/bsp/lpc18/family.cmake +++ b/hw/bsp/lpc18/family.cmake @@ -96,5 +96,6 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/lpc40/family.cmake b/hw/bsp/lpc40/family.cmake index 4c14da8a7..f1e8fa50d 100644 --- a/hw/bsp/lpc40/family.cmake +++ b/hw/bsp/lpc40/family.cmake @@ -99,6 +99,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) endfunction() diff --git a/hw/bsp/lpc43/family.cmake b/hw/bsp/lpc43/family.cmake index 2bacd9ea4..73842c7e7 100644 --- a/hw/bsp/lpc43/family.cmake +++ b/hw/bsp/lpc43/family.cmake @@ -104,5 +104,6 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/lpc51/family.cmake b/hw/bsp/lpc51/family.cmake index b9dd8829e..bd72c6067 100644 --- a/hw/bsp/lpc51/family.cmake +++ b/hw/bsp/lpc51/family.cmake @@ -116,6 +116,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) #family_flash_pyocd(${TARGET}) diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake index 5c61a07f0..0e4994ab1 100644 --- a/hw/bsp/lpc54/family.cmake +++ b/hw/bsp/lpc54/family.cmake @@ -149,6 +149,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) #family_flash_pyocd(${TARGET}) diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake index 21c57fc1f..367cb3bbd 100644 --- a/hw/bsp/lpc55/family.cmake +++ b/hw/bsp/lpc55/family.cmake @@ -150,6 +150,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) #family_flash_pyocd(${TARGET}) diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake index 48853b92c..3545e1c3a 100644 --- a/hw/bsp/max32650/family.cmake +++ b/hw/bsp/max32650/family.cmake @@ -147,6 +147,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) family_flash_openocd_adi(${TARGET}) diff --git a/hw/bsp/max32666/family.cmake b/hw/bsp/max32666/family.cmake index fb8c32295..b921b71ce 100644 --- a/hw/bsp/max32666/family.cmake +++ b/hw/bsp/max32666/family.cmake @@ -142,6 +142,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) family_flash_openocd_adi(${TARGET}) endfunction() diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake index 96dcfedff..9ce8892f1 100644 --- a/hw/bsp/max32690/family.cmake +++ b/hw/bsp/max32690/family.cmake @@ -147,6 +147,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) family_flash_openocd_adi(${TARGET}) endfunction() diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake index 446930bd8..4c9bf806b 100644 --- a/hw/bsp/max78002/family.cmake +++ b/hw/bsp/max78002/family.cmake @@ -148,6 +148,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) family_flash_msdk(${TARGET}) endfunction() diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake index 223afb9ec..b1d2a18ec 100644 --- a/hw/bsp/mcx/family.cmake +++ b/hw/bsp/mcx/family.cmake @@ -125,6 +125,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) #family_flash_nxplink(${TARGET}) #family_flash_pyocd(${TARGET}) diff --git a/hw/bsp/mm32/family.cmake b/hw/bsp/mm32/family.cmake index bf315acaa..93f297b8e 100644 --- a/hw/bsp/mm32/family.cmake +++ b/hw/bsp/mm32/family.cmake @@ -97,5 +97,6 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 9e86374dc..7a433d82d 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -141,6 +141,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) # family_flash_adafruit_nrfutil(${TARGET}) endfunction() diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 426e1ca8f..a73c7239d 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -124,6 +124,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) if (DEFINED DFU_UTIL_VID_PID) diff --git a/hw/bsp/stm32c0/family.cmake b/hw/bsp/stm32c0/family.cmake index ed237838d..7c5328ab0 100644 --- a/hw/bsp/stm32c0/family.cmake +++ b/hw/bsp/stm32c0/family.cmake @@ -113,6 +113,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) family_flash_stlink(${TARGET}) #family_flash_openocd(${TARGET}) diff --git a/hw/bsp/stm32f0/family.cmake b/hw/bsp/stm32f0/family.cmake index 0af200dd5..8b70411e8 100644 --- a/hw/bsp/stm32f0/family.cmake +++ b/hw/bsp/stm32f0/family.cmake @@ -110,6 +110,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32f1/family.cmake b/hw/bsp/stm32f1/family.cmake index e8cc4db1f..31801c035 100644 --- a/hw/bsp/stm32f1/family.cmake +++ b/hw/bsp/stm32f1/family.cmake @@ -109,6 +109,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32f2/family.cmake b/hw/bsp/stm32f2/family.cmake index 538a6cd66..2bae07b99 100644 --- a/hw/bsp/stm32f2/family.cmake +++ b/hw/bsp/stm32f2/family.cmake @@ -111,6 +111,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32f3/family.cmake b/hw/bsp/stm32f3/family.cmake index dbba1e658..6f4e866f8 100644 --- a/hw/bsp/stm32f3/family.cmake +++ b/hw/bsp/stm32f3/family.cmake @@ -107,6 +107,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32f4/family.cmake b/hw/bsp/stm32f4/family.cmake index c0c9fe902..487f0cf06 100644 --- a/hw/bsp/stm32f4/family.cmake +++ b/hw/bsp/stm32f4/family.cmake @@ -137,6 +137,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32f7/family.cmake b/hw/bsp/stm32f7/family.cmake index dc134e9c0..df1d2a3cf 100644 --- a/hw/bsp/stm32f7/family.cmake +++ b/hw/bsp/stm32f7/family.cmake @@ -139,6 +139,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake index 0dafa9c0a..7129cebd8 100644 --- a/hw/bsp/stm32g0/family.cmake +++ b/hw/bsp/stm32g0/family.cmake @@ -112,6 +112,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) family_flash_stlink(${TARGET}) #family_flash_openocd(${TARGET}) diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake index 4217e4be6..6c4e90d40 100644 --- a/hw/bsp/stm32g4/family.cmake +++ b/hw/bsp/stm32g4/family.cmake @@ -108,6 +108,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32h5/family.cmake b/hw/bsp/stm32h5/family.cmake index 94900f416..804b13768 100644 --- a/hw/bsp/stm32h5/family.cmake +++ b/hw/bsp/stm32h5/family.cmake @@ -112,6 +112,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake index 3e246faed..6af79736d 100644 --- a/hw/bsp/stm32h7/family.cmake +++ b/hw/bsp/stm32h7/family.cmake @@ -144,6 +144,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32l0/family.cmake b/hw/bsp/stm32l0/family.cmake index c04927585..a2324f123 100644 --- a/hw/bsp/stm32l0/family.cmake +++ b/hw/bsp/stm32l0/family.cmake @@ -111,6 +111,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32l4/family.cmake b/hw/bsp/stm32l4/family.cmake index 77876cb8b..67c5be7d8 100644 --- a/hw/bsp/stm32l4/family.cmake +++ b/hw/bsp/stm32l4/family.cmake @@ -114,6 +114,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32u5/family.cmake b/hw/bsp/stm32u5/family.cmake index 3ab7cdf8b..3be6702fd 100644 --- a/hw/bsp/stm32u5/family.cmake +++ b/hw/bsp/stm32u5/family.cmake @@ -115,6 +115,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/stm32wb/family.cmake b/hw/bsp/stm32wb/family.cmake index 071797c20..4f958045d 100644 --- a/hw/bsp/stm32wb/family.cmake +++ b/hw/bsp/stm32wb/family.cmake @@ -114,6 +114,7 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_stlink(${TARGET}) family_flash_jlink(${TARGET}) endfunction() diff --git a/hw/bsp/xmc4000/family.cmake b/hw/bsp/xmc4000/family.cmake index 85444db28..e73f0f216 100644 --- a/hw/bsp/xmc4000/family.cmake +++ b/hw/bsp/xmc4000/family.cmake @@ -95,5 +95,6 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing + family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) endfunction() -- cgit v1.3.1 From f934224351ea4bc14086fb113dc05a5ded707405 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 30 Nov 2024 22:26:33 +0100 Subject: Fix cmake options. Signed-off-by: HiFiPhile --- hw/bsp/family_support.cmake | 15 +++++++++++---- hw/bsp/imxrt/family.cmake | 6 ++---- hw/bsp/kinetis_k32l2/family.cmake | 3 +-- hw/bsp/ra/family.cmake | 3 +-- 4 files changed, 15 insertions(+), 12 deletions(-) (limited to 'hw') diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 82e3badb3..ddb17cbb0 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -300,10 +300,17 @@ endfunction() # Add bin/hex output function(family_add_bin_hex TARGET) - add_custom_command(TARGET ${TARGET} POST_BUILD - COMMAND ${CMAKE_OBJCOPY} -Obinary $ $/${TARGET}.bin - COMMAND ${CMAKE_OBJCOPY} -Oihex $ $/${TARGET}.hex - VERBATIM) + if (CMAKE_C_COMPILER_ID STREQUAL "IAR") + add_custom_command(TARGET ${TARGET} POST_BUILD + COMMAND ${CMAKE_OBJCOPY} --bin $ $/${TARGET}.bin + COMMAND ${CMAKE_OBJCOPY} --ihex $ $/${TARGET}.hex + VERBATIM) + else() + add_custom_command(TARGET ${TARGET} POST_BUILD + COMMAND ${CMAKE_OBJCOPY} -Obinary $ $/${TARGET}.bin + COMMAND ${CMAKE_OBJCOPY} -Oihex $ $/${TARGET}.hex + VERBATIM) + endif() endfunction() # Add uf2 output diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 76b0ff664..27a5f26aa 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -27,13 +27,13 @@ function(add_board_target BOARD_TARGET) # LD_FILE and STARTUP_FILE can be defined in board.cmake if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID}) set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_flexspi_nor.ld) - #set(LD_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx_flexspi_nor.ld) + set(LD_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/iar/${MCU_VARIANT}xxxxx${MCU_CORE}_flexspi_nor.icf) endif () set(LD_FILE_Clang ${LD_FILE_GNU}) if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID}) set(STARTUP_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT_WITH_CORE}.S) - #set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/startup_${MCU_VARIANT_WITH_CORE}.S) + set(STARTUP_FILE_IAR ${SDK_DIR}/devices/${MCU_VARIANT}/iar/startup_${MCU_VARIANT_WITH_CORE}.s) endif () set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) @@ -149,8 +149,6 @@ function(family_configure_example TARGET RTOS) # Link dependencies target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) - family_add_bin_hex(${TARGET}) - # Flashing family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) diff --git a/hw/bsp/kinetis_k32l2/family.cmake b/hw/bsp/kinetis_k32l2/family.cmake index 90d35cce3..e0843b5a4 100644 --- a/hw/bsp/kinetis_k32l2/family.cmake +++ b/hw/bsp/kinetis_k32l2/family.cmake @@ -103,11 +103,10 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing - family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) + family_add_bin_hex(${TARGET}) if (DEFINED TEENSY_MCU) - family_add_bin_hex(${TARGET}) family_flash_teensy(${TARGET}) endif () endfunction() diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index a73c7239d..a685d4118 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -124,11 +124,10 @@ function(family_configure_example TARGET RTOS) target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing - family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) + family_add_bin_hex(${TARGET}) if (DEFINED DFU_UTIL_VID_PID) - family_add_bin_hex(${TARGET}) family_flash_dfu_util(${TARGET} ${DFU_UTIL_VID_PID}) endif () endfunction() -- cgit v1.3.1 From 6cc2c98dafe15d05d20bc53e4fb8d9f8179731c6 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 6 Dec 2024 13:46:48 +0700 Subject: correct clock setting for h563 nucleo --- .idea/cmake.xml | 2 +- .idea/runConfigurations/stlink.xml | 4 +- hw/bsp/stm32h5/boards/stm32h503nucleo/board.cmake | 1 + hw/bsp/stm32h5/boards/stm32h503nucleo/board.mk | 3 +- hw/bsp/stm32h5/boards/stm32h563nucleo/board.cmake | 1 + hw/bsp/stm32h5/boards/stm32h563nucleo/board.h | 49 +++++++++++----------- hw/bsp/stm32h5/boards/stm32h563nucleo/board.mk | 3 +- .../stm32h563nucleo/cubemx/stm32h563nucleo.ioc | 43 +++++++++++-------- 8 files changed, 60 insertions(+), 46 deletions(-) (limited to 'hw') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 25a8513ca..5af6d7722 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -83,7 +83,7 @@ - + diff --git a/.idea/runConfigurations/stlink.xml b/.idea/runConfigurations/stlink.xml index 2d94e66d6..e84445add 100644 --- a/.idea/runConfigurations/stlink.xml +++ b/.idea/runConfigurations/stlink.xml @@ -1,6 +1,6 @@ - - + + diff --git a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.cmake b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.cmake index f0fb1d809..1a44c3f1d 100644 --- a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.cmake +++ b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.cmake @@ -4,5 +4,6 @@ set(JLINK_DEVICE stm32h503rb) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32H503xx + HSE_VALUE=24000000 ) endfunction() diff --git a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.mk b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.mk index cf60098af..0292353ae 100644 --- a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.mk +++ b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.mk @@ -1,7 +1,8 @@ MCU_VARIANT = stm32h503xx CFLAGS += \ - -DSTM32H503xx + -DSTM32H503xx \ + -DHSE_VALUE=24000000 \ # For flash-jlink target JLINK_DEVICE = stm32h503rb diff --git a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.cmake b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.cmake index 694ea41cd..0077bf235 100644 --- a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.cmake +++ b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.cmake @@ -4,5 +4,6 @@ set(JLINK_DEVICE stm32h563zi) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC STM32H563xx + HSE_VALUE=8000000 ) endfunction() diff --git a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h index 8e849f5c8..c4e0f680b 100644 --- a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h +++ b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h @@ -67,9 +67,8 @@ static inline void SystemClock_Config(void) { /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE; RCC_OscInitStruct.PLL.PLLM = 4; @@ -88,8 +87,8 @@ static inline void SystemClock_Config(void) { /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 - |RCC_CLOCKTYPE_PCLK3; + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_PCLK3; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; @@ -101,25 +100,27 @@ static inline void SystemClock_Config(void) { Error_Handler(); } - // Configure CRS clock source - __HAL_RCC_CRS_CLK_ENABLE(); - RCC_CRSInitTypeDef RCC_CRSInitStruct = {0}; - RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1; - RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB; - RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING; - RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000); - RCC_CRSInitStruct.ErrorLimitValue = 34; - RCC_CRSInitStruct.HSI48CalibrationValue = 32; - HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct); - - /* Select HSI48 as USB clock source */ - RCC_PeriphCLKInitTypeDef usb_clk = {0 }; - usb_clk.PeriphClockSelection = RCC_PERIPHCLK_USB; - usb_clk.UsbClockSelection = RCC_USBCLKSOURCE_HSI48; - HAL_RCCEx_PeriphCLKConfig(&usb_clk); - - /* Peripheral clock enable */ - __HAL_RCC_USB_CLK_ENABLE(); + /** Configure the programming delay + */ + __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2); + + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInitStruct.PLL3.PLL3Source = RCC_PLL3_SOURCE_HSE; + PeriphClkInitStruct.PLL3.PLL3M = 1; + PeriphClkInitStruct.PLL3.PLL3N = 18; + PeriphClkInitStruct.PLL3.PLL3P = 2; + PeriphClkInitStruct.PLL3.PLL3Q = 3; + PeriphClkInitStruct.PLL3.PLL3R = 2; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3_VCIRANGE_1; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3_VCORANGE_WIDE; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0.0; + PeriphClkInitStruct.PLL3.PLL3ClockOut = RCC_PLL3_DIVQ; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3Q; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } } #ifdef __cplusplus diff --git a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.mk b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.mk index 091d1e5e3..a7ccbdf39 100644 --- a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.mk +++ b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.mk @@ -1,7 +1,8 @@ MCU_VARIANT = stm32h563xx CFLAGS += \ - -DSTM32H563xx + -DSTM32H563xx \ + -DHSE_VALUE=8000000 \ # For flash-jlink target JLINK_DEVICE = stm32h563zi diff --git a/hw/bsp/stm32h5/boards/stm32h563nucleo/cubemx/stm32h563nucleo.ioc b/hw/bsp/stm32h5/boards/stm32h563nucleo/cubemx/stm32h563nucleo.ioc index 3c83d136d..b9b9605c1 100644 --- a/hw/bsp/stm32h5/boards/stm32h563nucleo/cubemx/stm32h563nucleo.ioc +++ b/hw/bsp/stm32h5/boards/stm32h563nucleo/cubemx/stm32h563nucleo.ioc @@ -2,6 +2,7 @@ BOOTPATH.BootPathName=LEGACY BOOTPATH.IPParameters=BootPathName BOOTPATH.UserSelectedBootPath=LEGACY +BSP_IP_NAME=NUCLEO-H563ZI CAD.formats= CAD.pinconfig= CAD.provider= @@ -16,6 +17,7 @@ Mcu.ContextProject=TrustZoneDisabled Mcu.Family=STM32H5 Mcu.IP0=BOOTPATH Mcu.IP1=CORTEX_M33_NS +Mcu.IP10=NUCLEO-H563ZI Mcu.IP2=DEBUG Mcu.IP3=ICACHE Mcu.IP4=MEMORYMAP @@ -24,7 +26,7 @@ Mcu.IP6=PWR Mcu.IP7=RCC Mcu.IP8=SYS Mcu.IP9=USB -Mcu.IPNb=10 +Mcu.IPNb=11 Mcu.Name=STM32H563ZITx Mcu.Package=LQFP144 Mcu.Pin0=PE2 @@ -74,8 +76,8 @@ Mcu.PinsNb=43 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32H563ZITx -MxCube.Version=6.10.0 -MxDb.Version=DB.6.0.100 +MxCube.Version=6.12.1 +MxDb.Version=DB.6.0.121 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.EXTI13_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true @@ -267,7 +269,7 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32H563ZITx -ProjectManager.FirmwarePackage=STM32Cube FW_H5 V1.1.1 +ProjectManager.FirmwarePackage=STM32Cube FW_H5 V1.3.0 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 @@ -317,7 +319,7 @@ RCC.I2C2Freq_Value=250000000 RCC.I2C3Freq_Value=250000000 RCC.I2C4Freq_Value=250000000 RCC.I3C1Freq_Value=250000000 -RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CECFreq_Value,CKPERFreq_Value,CRSFreq_Value,CSI_VALUE,CortexFreq_Value,DACFreq_Value,EPOD_VALUE,ETHFreq_Value,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSIDiv,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I3C1Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPTIM4Freq_Value,LPTIM5Freq_Value,LPTIM6Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSIRC_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,OCTOSPIMFreq_Value,PLL2PoutputFreq_Value,PLL2QoutputFreq_Value,PLL2RoutputFreq_Value,PLL3PoutputFreq_Value,PLL3QoutputFreq_Value,PLL3RoutputFreq_Value,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC1Freq_Value,SDMMC2Freq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SPI4Freq_Value,SPI5Freq_Value,SPI6Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART12Freq_Value,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,UART9Freq_Value,UCPD1outputFreq_Value,USART10Freq_Value,USART11Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOPLL2OutputFreq_Value,VCOPLL3OutputFreq_Value +RCC.IPParameters=ADCFreq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CECFreq_Value,CKPERFreq_Value,CRSFreq_Value,CSI_VALUE,CortexFreq_Value,DACFreq_Value,EPOD_VALUE,ETHFreq_Value,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSIDiv,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I3C1Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM3Freq_Value,LPTIM4Freq_Value,LPTIM5Freq_Value,LPTIM6Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSIRC_VALUE,MCO1PinFreq_Value,MCO2PinFreq_Value,OCTOSPIMFreq_Value,PLL2PoutputFreq_Value,PLL2QoutputFreq_Value,PLL2RoutputFreq_Value,PLL2Source,PLL3FRACN,PLL3N,PLL3PoutputFreq_Value,PLL3Q,PLL3QoutputFreq_Value,PLL3RoutputFreq_Value,PLL3Source,PLLFRACN,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLSourceVirtual,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMC1Freq_Value,SDMMC2Freq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SPI4Freq_Value,SPI5Freq_Value,SPI6Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART12Freq_Value,UART4Freq_Value,UART5Freq_Value,UART7Freq_Value,UART8Freq_Value,UART9Freq_Value,UCPD1outputFreq_Value,USART10Freq_Value,USART11Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USART6Freq_Value,USBCLockSelection,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOPLL2OutputFreq_Value,VCOPLL3OutputFreq_Value RCC.LPTIM1Freq_Value=250000000 RCC.LPTIM2Freq_Value=250000000 RCC.LPTIM3Freq_Value=250000000 @@ -330,12 +332,18 @@ RCC.LSIRC_VALUE=32000 RCC.MCO1PinFreq_Value=64000000 RCC.MCO2PinFreq_Value=250000000 RCC.OCTOSPIMFreq_Value=250000000 -RCC.PLL2PoutputFreq_Value=258000000 -RCC.PLL2QoutputFreq_Value=258000000 -RCC.PLL2RoutputFreq_Value=258000000 -RCC.PLL3PoutputFreq_Value=258000000 -RCC.PLL3QoutputFreq_Value=258000000 -RCC.PLL3RoutputFreq_Value=258000000 +RCC.PLL2PoutputFreq_Value=516000000 +RCC.PLL2QoutputFreq_Value=516000000 +RCC.PLL2RoutputFreq_Value=516000000 +RCC.PLL2Source=RCC_PLL2_SOURCE_HSE +RCC.PLL3FRACN=0 +RCC.PLL3N=18 +RCC.PLL3PoutputFreq_Value=72000000 +RCC.PLL3Q=3 +RCC.PLL3QoutputFreq_Value=48000000 +RCC.PLL3RoutputFreq_Value=72000000 +RCC.PLL3Source=RCC_PLL3_SOURCE_HSE +RCC.PLLFRACN=0 RCC.PLLM=4 RCC.PLLN=250 RCC.PLLPoutputFreq_Value=250000000 @@ -343,8 +351,8 @@ RCC.PLLQoutputFreq_Value=250000000 RCC.PLLSourceVirtual=RCC_PLL1_SOURCE_HSE RCC.PWRFreq_Value=250000000 RCC.RNGFreq_Value=48000000 -RCC.SAI1Freq_Value=258000000 -RCC.SAI2Freq_Value=258000000 +RCC.SAI1Freq_Value=516000000 +RCC.SAI2Freq_Value=516000000 RCC.SDMMC1Freq_Value=250000000 RCC.SDMMC2Freq_Value=250000000 RCC.SPI1Freq_Value=250000000 @@ -368,13 +376,14 @@ RCC.USART1Freq_Value=250000000 RCC.USART2Freq_Value=250000000 RCC.USART3Freq_Value=250000000 RCC.USART6Freq_Value=250000000 +RCC.USBCLockSelection=RCC_USBCLKSOURCE_PLL3Q RCC.USBFreq_Value=48000000 -RCC.VCOInput2Freq_Value=4000000 -RCC.VCOInput3Freq_Value=4000000 +RCC.VCOInput2Freq_Value=8000000 +RCC.VCOInput3Freq_Value=8000000 RCC.VCOInputFreq_Value=2000000 RCC.VCOOutputFreq_Value=500000000 -RCC.VCOPLL2OutputFreq_Value=516000000 -RCC.VCOPLL3OutputFreq_Value=516000000 +RCC.VCOPLL2OutputFreq_Value=1032000000 +RCC.VCOPLL3OutputFreq_Value=144000000 SH.ADCx_INP18.0=ADC1_INP18 SH.ADCx_INP18.ConfNb=1 SH.GPXTI13.0=GPIO_EXTI13 -- cgit v1.3.1 From b5e84d26c26c47f41e77d8f7fb4f4e2ffb25c1cf Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 10 Dec 2024 21:49:08 +0700 Subject: change ra bsp to match fsp generated directory --- .../ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h | 63 ---- .../portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 - .../fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 - .../portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 387 --------------------- .../ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h | 37 -- .../portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 63 ++++ .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 387 +++++++++++++++++++++ .../portenta_c33/ra_cfg/fsp_cfg/r_ioport_cfg.h | 13 + .../ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h | 37 ++ hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_cfg.h | 62 ---- .../ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 - .../ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 - .../ra2a1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 84 ----- hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp_clock_cfg.h | 17 - .../boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 62 ++++ .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 84 +++++ .../boards/ra2a1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h | 13 + hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h | 17 + hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h | 35 -- .../ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 - .../ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 - .../ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 78 ----- hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h | 21 -- .../boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 35 ++ .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 78 +++++ .../boards/ra4m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h | 13 + hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h | 21 ++ hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h | 63 ---- .../ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 - .../ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 - .../ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 386 -------------------- hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h | 25 -- .../boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 63 ++++ .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 386 ++++++++++++++++++++ .../boards/ra4m3_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h | 13 + hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h | 25 ++ hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h | 68 ---- .../ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 - .../ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 - .../ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 84 ----- hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h | 23 -- .../boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 68 ++++ .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 84 +++++ .../boards/ra6m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h | 13 + hw/bsp/ra/boards/ra6m1_ek/ra_gen/bsp_clock_cfg.h | 23 ++ hw/bsp/ra/boards/ra6m5_ek/board.cmake | 1 + hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h | 63 ---- .../ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 - .../ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 - .../ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 387 --------------------- hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h | 37 -- .../boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 63 ++++ .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 387 +++++++++++++++++++++ .../boards/ra6m5_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h | 13 + hw/bsp/ra/boards/ra6m5_ek/ra_gen/bsp_clock_cfg.h | 37 ++ hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h | 35 -- .../boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 - .../uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 - .../boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 87 ----- hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h | 21 -- .../ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 35 ++ .../uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 + .../uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 87 +++++ .../ra/boards/uno_r4/ra_cfg/fsp_cfg/r_ioport_cfg.h | 13 + hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h | 21 ++ hw/bsp/ra/family.cmake | 5 +- hw/bsp/ra/r_ioport_cfg.h | 7 - 80 files changed, 2270 insertions(+), 2184 deletions(-) delete mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h delete mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h delete mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h delete mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h delete mode 100644 hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h create mode 100644 hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h create mode 100644 hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h create mode 100644 hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h create mode 100644 hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h create mode 100644 hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/r_ioport_cfg.h create mode 100644 hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h delete mode 100644 hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_cfg.h delete mode 100644 hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h delete mode 100644 hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h delete mode 100644 hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h delete mode 100644 hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp_clock_cfg.h create mode 100644 hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h create mode 100644 hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h create mode 100644 hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h create mode 100644 hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h create mode 100644 hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h create mode 100644 hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h delete mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h delete mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h delete mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h delete mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h delete mode 100644 hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h delete mode 100644 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h delete mode 100644 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h delete mode 100644 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h delete mode 100644 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h delete mode 100644 hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h delete mode 100644 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h delete mode 100644 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h delete mode 100644 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h delete mode 100644 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h delete mode 100644 hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h create mode 100644 hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h create mode 100644 hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h create mode 100644 hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h create mode 100644 hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h create mode 100644 hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h create mode 100644 hw/bsp/ra/boards/ra6m1_ek/ra_gen/bsp_clock_cfg.h delete mode 100644 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h delete mode 100644 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h delete mode 100644 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h delete mode 100644 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h delete mode 100644 hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h create mode 100644 hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h create mode 100644 hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h create mode 100644 hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h create mode 100644 hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h create mode 100644 hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h create mode 100644 hw/bsp/ra/boards/ra6m5_ek/ra_gen/bsp_clock_cfg.h delete mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h delete mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h delete mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h delete mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h delete mode 100644 hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h create mode 100644 hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h create mode 100644 hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h create mode 100644 hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h create mode 100644 hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h create mode 100644 hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/r_ioport_cfg.h create mode 100644 hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h delete mode 100644 hw/bsp/ra/r_ioport_cfg.h (limited to 'hw') diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h deleted file mode 100644 index 33d381850..000000000 --- a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_cfg.h +++ /dev/null @@ -1,63 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#define RA_NOT_DEFINED 0 -#ifndef BSP_CFG_RTOS -#if (RA_NOT_DEFINED) != (2) -#define BSP_CFG_RTOS (2) -#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (1) -#else - #define BSP_CFG_RTOS (0) -#endif -#endif -#ifndef BSP_CFG_RTC_USED -#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) -#endif -#undef RA_NOT_DEFINED -#if defined(_RA_BOOT_IMAGE) - #define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x1000) -#define BSP_CFG_HEAP_BYTES (0x1000) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) -#endif - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#endif - -#ifdef __cplusplus -} -#endif -#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h deleted file mode 100644 index bd6a901c3..000000000 --- a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_CFG_H_ -#define BSP_MCU_DEVICE_CFG_H_ -#define BSP_CFG_MCU_PART_SERIES (6) -#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index 6845183db..000000000 --- a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA6M5BH3CFC -#define BSP_MCU_FEATURE_SET ('B') -#define BSP_ROM_SIZE_BYTES (2097152) -#define BSP_RAM_SIZE_BYTES (524288) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (176) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h deleted file mode 100644 index d5428540f..000000000 --- a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,387 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" -#include "bsp_clock_cfg.h" - -#define BSP_MCU_GROUP_RA6M5 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (16000000) -#elif BSP_CFG_HOCO_FREQUENCY == 1 - #define BSP_HOCO_HZ (18000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (20000000) -#else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif - -#define BSP_CFG_FLL_ENABLE (0) - -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) - -#if defined(_RA_TZ_SECURE) - #define BSP_TZ_SECURE_BUILD (1) - #define BSP_TZ_NONSECURE_BUILD (0) - #elif defined(_RA_TZ_NONSECURE) - #define BSP_TZ_SECURE_BUILD (0) - #define BSP_TZ_NONSECURE_BUILD (1) - #else -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (0) -#endif - -/* TrustZone Settings */ -#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) -#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) -#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) - -/* CMSIS TrustZone Settings */ -#define SCB_CSR_AIRCR_INIT (1) -#define SCB_AIRCR_BFHFNMINS_VAL (0) -#define SCB_AIRCR_SYSRESETREQS_VAL (1) -#define SCB_AIRCR_PRIS_VAL (0) -#define TZ_FPU_NS_USAGE (1) -#ifndef SCB_NSACR_CP10_11_VAL -#define SCB_NSACR_CP10_11_VAL (3U) -#endif - -#ifndef FPU_FPCCR_TS_VAL -#define FPU_FPCCR_TS_VAL (1U) -#endif -#define FPU_FPCCR_CLRONRETS_VAL (1) - -#ifndef FPU_FPCCR_CLRONRET_VAL -#define FPU_FPCCR_CLRONRET_VAL (1) -#endif - -/* The C-Cache line size that is configured during startup. */ -#ifndef BSP_CFG_C_CACHE_LINE_SIZE -#define BSP_CFG_C_CACHE_LINE_SIZE (1U) -#endif - -/* Type 1 Peripheral Security Attribution */ - -/* Peripheral Security Attribution Register (PSAR) Settings */ -#ifndef BSP_TZ_CFG_PSARB -#define BSP_TZ_CFG_PSARB (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ - 0x33f4f9) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARC -#define BSP_TZ_CFG_PSARC (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ - 0x7fffcef4) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARD -#define BSP_TZ_CFG_PSARD (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ - 0xffae07f0) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARE -#define BSP_TZ_CFG_PSARE (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ - 0x3f3ff8) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_MSSAR -#define BSP_TZ_CFG_MSSAR (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ - 0xfffffffc) /* Unused */ -#endif - -/* Type 2 Peripheral Security Attribution */ - -/* Security attribution for Cache registers. */ -#ifndef BSP_TZ_CFG_CSAR -#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) -#endif - -/* Security attribution for RSTSRn registers. */ -#ifndef BSP_TZ_CFG_RSTSAR -#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) -#endif - -/* Security attribution for registers of LVD channels. */ -#ifndef BSP_TZ_CFG_LVDSAR -#define BSP_TZ_CFG_LVDSAR (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ - 0xFFFFFFFCU) -#endif - -/* Security attribution for LPM registers. */ -#ifndef BSP_TZ_CFG_LPMSAR -#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) -#endif -/* Deep Standby Interrupt Factor Security Attribution Register. */ -#ifndef BSP_TZ_CFG_DPFSAR -#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) -#endif - -/* Security attribution for CGC registers. */ -#ifndef BSP_TZ_CFG_CGFSAR -#if BSP_CFG_CLOCKS_SECURE -/* Protect all CGC registers from Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) -#endif -#endif - -/* Security attribution for Battery Backup registers. */ -#ifndef BSP_TZ_CFG_BBFSAR -#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) -#endif - -/* Security attribution for registers for IRQ channels. */ -#ifndef BSP_TZ_CFG_ICUSARA -#define BSP_TZ_CFG_ICUSARA (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ - 0xFFFF0000U) -#endif - -/* Security attribution for NMI registers. */ -#ifndef BSP_TZ_CFG_ICUSARB -#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ -#endif - -/* Security attribution for registers for DMAC channels */ -#ifndef BSP_TZ_CFG_ICUSARC -#define BSP_TZ_CFG_ICUSARC (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ - 0xFFFFFF00U) -#endif - -/* Security attribution registers for SELSR0. */ -#ifndef BSP_TZ_CFG_ICUSARD -#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) -#endif - -/* Security attribution registers for WUPEN0. */ -#ifndef BSP_TZ_CFG_ICUSARE -#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) -#endif - -/* Security attribution registers for WUPEN1. */ -#ifndef BSP_TZ_CFG_ICUSARF -#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) -#endif - -/* Set DTCSTSAR if the Secure program uses the DTC. */ -#if RA_NOT_DEFINED == RA_NOT_DEFINED -#define BSP_TZ_CFG_DTC_USED (0U) -#else - #define BSP_TZ_CFG_DTC_USED (1U) -#endif - -/* Security attribution of FLWT and FCKMHZ registers. */ -#ifndef BSP_TZ_CFG_FSAR -/* If the CGC registers are only accessible in Secure mode, than there is no - * reason for nonsecure applications to access FLWT and FCKMHZ. */ -#if BSP_CFG_CLOCKS_SECURE -/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ -#define BSP_TZ_CFG_FSAR (0xFEFEU) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_FSAR (0xFFFFU) -#endif -#endif - -/* Security attribution for SRAM registers. */ -#ifndef BSP_TZ_CFG_SRAMSAR -/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access - * SRAM0WTEN and therefore there is no reason to access PRCR2. */ -#define BSP_TZ_CFG_SRAMSAR (\ - 1 | \ - ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ - 4 | \ - 0xFFFFFFF8U) -#endif - -/* Security attribution for Standby RAM registers. */ -#ifndef BSP_TZ_CFG_STBRAMSAR -#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) -#endif - -/* Security attribution for the DMAC Bus Master MPU settings. */ -#ifndef BSP_TZ_CFG_MMPUSARA -/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ -#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) -#endif - -/* Security Attribution Register A for BUS Control registers. */ -#ifndef BSP_TZ_CFG_BUSSARA -#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) -#endif -/* Security Attribution Register B for BUS Control registers. */ -#ifndef BSP_TZ_CFG_BUSSARB -#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) -#endif - -/* Enable Uninitialized Non-Secure Application Fallback. */ -#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK -#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) -#endif - -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) - -/* Option Function Select Register 1 Security Attribution */ -#ifndef BSP_CFG_ROM_REG_OFS1_SEL -#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) -#else -#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) -#endif -#endif - -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) - -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) - -/* Dual Mode Select Register */ -#ifndef BSP_CFG_ROM_REG_DUALSEL -#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) -#endif - -/* Block Protection Register 0 */ -#ifndef BSP_CFG_ROM_REG_BPS0 -#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) -#endif -/* Block Protection Register 1 */ -#ifndef BSP_CFG_ROM_REG_BPS1 -#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) -#endif -/* Block Protection Register 2 */ -#ifndef BSP_CFG_ROM_REG_BPS2 -#define BSP_CFG_ROM_REG_BPS2 (~( 0U)) -#endif -/* Block Protection Register 3 */ -#ifndef BSP_CFG_ROM_REG_BPS3 -#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) -#endif -/* Permanent Block Protection Register 0 */ -#ifndef BSP_CFG_ROM_REG_PBPS0 -#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) -#endif -/* Permanent Block Protection Register 1 */ -#ifndef BSP_CFG_ROM_REG_PBPS1 -#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) -#endif -/* Permanent Block Protection Register 2 */ -#ifndef BSP_CFG_ROM_REG_PBPS2 -#define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) -#endif -/* Permanent Block Protection Register 3 */ -#ifndef BSP_CFG_ROM_REG_PBPS3 -#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) -#endif -/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL0 -#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) -#endif -/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL1 -#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) -#endif -/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL2 -#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) -#endif -/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL3 -#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) -#endif -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif - -#ifdef __cplusplus -} -#endif -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h deleted file mode 100644 index 0eb5e0516..000000000 --- a/hw/bsp/ra/boards/portenta_c33/fsp_cfg/bsp_clock_cfg.h +++ /dev/null @@ -1,37 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CLOCK_CFG_H_ -#define BSP_CLOCK_CFG_H_ - -#define BSP_CFG_CLOCKS_SECURE (0) -#define BSP_CFG_CLOCKS_OVERRIDE (0) -#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ -#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ -#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ -#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ -#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(25U,0U)) /* PLL Mul x25.0 */ -#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ -#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ -#define BSP_CFG_PLL2_MUL (BSP_CLOCKS_PLL_MUL(20U,0U)) /* PLL2 Mul x20.0 */ -#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ -#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ -#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ -#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */ -#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ -#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ -#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ -#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ -#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ -#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ -#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ -#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ -#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ -#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ -#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ -#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ -#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ -#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */ -#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ -#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */ -#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ - -#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..33d381850 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,63 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" + +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (2) +#define BSP_CFG_RTOS (2) +#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) +#else + #define BSP_CFG_RTOS (0) +#endif +#endif +#ifndef BSP_CFG_RTC_USED +#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) +#endif +#undef RA_NOT_DEFINED +#if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) +#endif +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x1000) +#define BSP_CFG_HEAP_BYTES (0x1000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif + +#ifdef __cplusplus +} +#endif +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000..bd6a901c3 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (6) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..6845183db --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA6M5BH3CFC +#define BSP_MCU_FEATURE_SET ('B') +#define BSP_ROM_SIZE_BYTES (2097152) +#define BSP_RAM_SIZE_BYTES (524288) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_LQFP +#define BSP_PACKAGE_PINS (176) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..d5428540f --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,387 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" +#include "bsp_clock_cfg.h" + +#define BSP_MCU_GROUP_RA6M5 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (16000000) +#elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) +#else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif + +#define BSP_CFG_FLL_ENABLE (0) + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + +#if defined(_RA_TZ_SECURE) + #define BSP_TZ_SECURE_BUILD (1) + #define BSP_TZ_NONSECURE_BUILD (0) + #elif defined(_RA_TZ_NONSECURE) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (1) + #else +#define BSP_TZ_SECURE_BUILD (0) +#define BSP_TZ_NONSECURE_BUILD (0) +#endif + +/* TrustZone Settings */ +#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) +#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) +#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + +/* CMSIS TrustZone Settings */ +#define SCB_CSR_AIRCR_INIT (1) +#define SCB_AIRCR_BFHFNMINS_VAL (0) +#define SCB_AIRCR_SYSRESETREQS_VAL (1) +#define SCB_AIRCR_PRIS_VAL (0) +#define TZ_FPU_NS_USAGE (1) +#ifndef SCB_NSACR_CP10_11_VAL +#define SCB_NSACR_CP10_11_VAL (3U) +#endif + +#ifndef FPU_FPCCR_TS_VAL +#define FPU_FPCCR_TS_VAL (1U) +#endif +#define FPU_FPCCR_CLRONRETS_VAL (1) + +#ifndef FPU_FPCCR_CLRONRET_VAL +#define FPU_FPCCR_CLRONRET_VAL (1) +#endif + +/* The C-Cache line size that is configured during startup. */ +#ifndef BSP_CFG_C_CACHE_LINE_SIZE +#define BSP_CFG_C_CACHE_LINE_SIZE (1U) +#endif + +/* Type 1 Peripheral Security Attribution */ + +/* Peripheral Security Attribution Register (PSAR) Settings */ +#ifndef BSP_TZ_CFG_PSARB +#define BSP_TZ_CFG_PSARB (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ + (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ + 0x33f4f9) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARC +#define BSP_TZ_CFG_PSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ + 0x7fffcef4) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARD +#define BSP_TZ_CFG_PSARD (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ + 0xffae07f0) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARE +#define BSP_TZ_CFG_PSARE (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ + 0x3f3ff8) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_MSSAR +#define BSP_TZ_CFG_MSSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ + 0xfffffffc) /* Unused */ +#endif + +/* Type 2 Peripheral Security Attribution */ + +/* Security attribution for Cache registers. */ +#ifndef BSP_TZ_CFG_CSAR +#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) +#endif + +/* Security attribution for RSTSRn registers. */ +#ifndef BSP_TZ_CFG_RSTSAR +#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) +#endif + +/* Security attribution for registers of LVD channels. */ +#ifndef BSP_TZ_CFG_LVDSAR +#define BSP_TZ_CFG_LVDSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ + 0xFFFFFFFCU) +#endif + +/* Security attribution for LPM registers. */ +#ifndef BSP_TZ_CFG_LPMSAR +#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) +#endif +/* Deep Standby Interrupt Factor Security Attribution Register. */ +#ifndef BSP_TZ_CFG_DPFSAR +#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) +#endif + +/* Security attribution for CGC registers. */ +#ifndef BSP_TZ_CFG_CGFSAR +#if BSP_CFG_CLOCKS_SECURE +/* Protect all CGC registers from Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) +#endif +#endif + +/* Security attribution for Battery Backup registers. */ +#ifndef BSP_TZ_CFG_BBFSAR +#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) +#endif + +/* Security attribution for registers for IRQ channels. */ +#ifndef BSP_TZ_CFG_ICUSARA +#define BSP_TZ_CFG_ICUSARA (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ + 0xFFFF0000U) +#endif + +/* Security attribution for NMI registers. */ +#ifndef BSP_TZ_CFG_ICUSARB +#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ +#endif + +/* Security attribution for registers for DMAC channels */ +#ifndef BSP_TZ_CFG_ICUSARC +#define BSP_TZ_CFG_ICUSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ + 0xFFFFFF00U) +#endif + +/* Security attribution registers for SELSR0. */ +#ifndef BSP_TZ_CFG_ICUSARD +#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) +#endif + +/* Security attribution registers for WUPEN0. */ +#ifndef BSP_TZ_CFG_ICUSARE +#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) +#endif + +/* Security attribution registers for WUPEN1. */ +#ifndef BSP_TZ_CFG_ICUSARF +#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) +#endif + +/* Set DTCSTSAR if the Secure program uses the DTC. */ +#if RA_NOT_DEFINED == RA_NOT_DEFINED +#define BSP_TZ_CFG_DTC_USED (0U) +#else + #define BSP_TZ_CFG_DTC_USED (1U) +#endif + +/* Security attribution of FLWT and FCKMHZ registers. */ +#ifndef BSP_TZ_CFG_FSAR +/* If the CGC registers are only accessible in Secure mode, than there is no + * reason for nonsecure applications to access FLWT and FCKMHZ. */ +#if BSP_CFG_CLOCKS_SECURE +/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ +#define BSP_TZ_CFG_FSAR (0xFEFEU) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_FSAR (0xFFFFU) +#endif +#endif + +/* Security attribution for SRAM registers. */ +#ifndef BSP_TZ_CFG_SRAMSAR +/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access + * SRAM0WTEN and therefore there is no reason to access PRCR2. */ +#define BSP_TZ_CFG_SRAMSAR (\ + 1 | \ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ + 4 | \ + 0xFFFFFFF8U) +#endif + +/* Security attribution for Standby RAM registers. */ +#ifndef BSP_TZ_CFG_STBRAMSAR +#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) +#endif + +/* Security attribution for the DMAC Bus Master MPU settings. */ +#ifndef BSP_TZ_CFG_MMPUSARA +/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ +#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) +#endif + +/* Security Attribution Register A for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARA +#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) +#endif +/* Security Attribution Register B for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARB +#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) +#endif + +/* Enable Uninitialized Non-Secure Application Fallback. */ +#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK +#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) +#endif + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + +/* Option Function Select Register 1 Security Attribution */ +#ifndef BSP_CFG_ROM_REG_OFS1_SEL +#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) +#else +#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) +#endif +#endif + +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +/* Dual Mode Select Register */ +#ifndef BSP_CFG_ROM_REG_DUALSEL +#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) +#endif + +/* Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_BPS0 +#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) +#endif +/* Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_BPS1 +#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) +#endif +/* Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_BPS2 +#define BSP_CFG_ROM_REG_BPS2 (~( 0U)) +#endif +/* Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_BPS3 +#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) +#endif +/* Permanent Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_PBPS0 +#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) +#endif +/* Permanent Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_PBPS1 +#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) +#endif +/* Permanent Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_PBPS2 +#define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) +#endif +/* Permanent Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_PBPS3 +#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) +#endif +/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL0 +#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) +#endif +/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL1 +#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) +#endif +/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL2 +#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) +#endif +/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL3 +#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..d2688bf5b --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h new file mode 100644 index 000000000..0eb5e0516 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,37 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ + +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ +#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(25U,0U)) /* PLL Mul x25.0 */ +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ +#define BSP_CFG_PLL2_MUL (BSP_CLOCKS_PLL_MUL(20U,0U)) /* PLL2 Mul x20.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ +#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */ +#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ +#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ +#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ +#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */ +#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ +#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */ +#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ + +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_cfg.h deleted file mode 100644 index 30637c17b..000000000 --- a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_cfg.h +++ /dev/null @@ -1,62 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ -#ifdef __cplusplus - extern "C" { - #endif - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" -#define RA_NOT_DEFINED 0 -#ifndef BSP_CFG_RTOS -#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (2) - #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (1) - #else -#define BSP_CFG_RTOS (0) -#endif -#endif -#ifndef BSP_CFG_RTC_USED -#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) -#endif -#undef RA_NOT_DEFINED -#if defined(_RA_BOOT_IMAGE) - #define BSP_CFG_BOOT_IMAGE (1) - #endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -#define BSP_CFG_HEAP_BYTES (0x400) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) -#endif - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#endif - -#ifdef __cplusplus - } - #endif -#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h deleted file mode 100644 index eb82f4697..000000000 --- a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_CFG_H_ -#define BSP_MCU_DEVICE_CFG_H_ -#define BSP_CFG_MCU_PART_SERIES (2) -#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index 710e85b28..000000000 --- a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA2A1AB3CFM -#define BSP_MCU_FEATURE_SET ('A') -#define BSP_ROM_SIZE_BYTES (262144) -#define BSP_RAM_SIZE_BYTES (32768) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (64) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h deleted file mode 100644 index 6caef62cc..000000000 --- a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,84 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ -#ifdef __cplusplus - extern "C" { - #endif - -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "../../../ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h" -#include "bsp_clock_cfg.h" -#define BSP_MCU_GROUP_RA2A1 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (24000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (32000000) - #elif BSP_CFG_HOCO_FREQUENCY == 4 - #define BSP_HOCO_HZ (48000000) - #elif BSP_CFG_HOCO_FREQUENCY == 5 - #define BSP_HOCO_HZ (64000000) - #else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" - #endif - -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) - -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) -#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC0_START (0x000FFFFC) -#define BSP_CFG_ROM_REG_MPU_PC0_END (0x000FFFFF) -#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC1_START (0x000FFFFC) -#define BSP_CFG_ROM_REG_MPU_PC1_END (0x000FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x000FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x000FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) - -/* - ID Code - Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. - WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. - */ -#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) - #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) - #else -/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ -#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) -#endif - -#ifdef __cplusplus - } - #endif -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp_clock_cfg.h deleted file mode 100644 index cd9d135f7..000000000 --- a/hw/bsp/ra/boards/ra2a1_ek/fsp_cfg/bsp_clock_cfg.h +++ /dev/null @@ -1,17 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CLOCK_CFG_H_ -#define BSP_CLOCK_CFG_H_ -#define BSP_CFG_CLOCKS_SECURE (0) -#define BSP_CFG_CLOCKS_OVERRIDE (0) -#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */ -#define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */ -#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */ -#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ -#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ -#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ -#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ -#define BSP_CFG_SDADC_CLOCK_SOURCE (0) /* SDADCCLK Src: HOCO */ -#define BSP_CFG_SDADCCLK_DIV (7) /* SDADCCLK Div /12 */ -#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ -#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ -#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..30637c17b --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,62 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else +#define BSP_CFG_RTOS (0) +#endif +#endif +#ifndef BSP_CFG_RTC_USED +#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) +#endif +#undef RA_NOT_DEFINED +#if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x400) +#define BSP_CFG_HEAP_BYTES (0x400) +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif + +#ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000..eb82f4697 --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (2) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..710e85b28 --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA2A1AB3CFM +#define BSP_MCU_FEATURE_SET ('A') +#define BSP_ROM_SIZE_BYTES (262144) +#define BSP_RAM_SIZE_BYTES (32768) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_LQFP +#define BSP_PACKAGE_PINS (64) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..6caef62cc --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,84 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h" +#include "bsp_clock_cfg.h" +#define BSP_MCU_GROUP_RA2A1 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (24000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (32000000) + #elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (48000000) + #elif BSP_CFG_HOCO_FREQUENCY == 5 + #define BSP_HOCO_HZ (64000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0x000FFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0x000FFFFF) +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0x000FFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0x000FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x000FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x000FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +/* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ +#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) + #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) + #else +/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +#endif + +#ifdef __cplusplus + } + #endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..d2688bf5b --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h new file mode 100644 index 000000000..cd9d135f7 --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,17 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ +#define BSP_CFG_SDADC_CLOCK_SOURCE (0) /* SDADCCLK Src: HOCO */ +#define BSP_CFG_SDADCCLK_DIV (7) /* SDADCCLK Div /12 */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h deleted file mode 100644 index 11d5795df..000000000 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_cfg.h +++ /dev/null @@ -1,35 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#undef RA_NOT_DEFINED -#define BSP_CFG_RTOS (0) -#if defined(_RA_BOOT_IMAGE) -#define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x800) -#define BSP_CFG_HEAP_BYTES (0x1000) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) - -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 - -#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h deleted file mode 100644 index 444d32e56..000000000 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_CFG_H_ -#define BSP_MCU_DEVICE_CFG_H_ -#define BSP_CFG_MCU_PART_SERIES (4) -#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index d810dabb2..000000000 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA4M1AB3CFP -#define BSP_MCU_FEATURE_SET ('A') -#define BSP_ROM_SIZE_BYTES (262144) -#define BSP_RAM_SIZE_BYTES (32768) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (100) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h deleted file mode 100644 index 72cdb89e6..000000000 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,78 +0,0 @@ -/* generated configuration header file through renesas e2 studio */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ - -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "bsp_mcu_info.h" -#include "bsp_clock_cfg.h" - -#define BSP_MCU_GROUP_RA4M1 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 - #define BSP_HOCO_HZ (24000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (32000000) -#elif BSP_CFG_HOCO_FREQUENCY == 4 - #define BSP_HOCO_HZ (48000000) -#elif BSP_CFG_HOCO_FREQUENCY == 5 - #define BSP_HOCO_HZ (64000000) -#else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) - -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) -#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) -#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) - -/* - ID Code - Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. - WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. - */ -#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) - #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) - #else -/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ -#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) -#endif - -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h deleted file mode 100644 index 554126523..000000000 --- a/hw/bsp/ra/boards/ra4m1_ek/fsp_cfg/bsp_clock_cfg.h +++ /dev/null @@ -1,21 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CLOCK_CFG_H_ -#define BSP_CLOCK_CFG_H_ -#define BSP_CFG_CLOCKS_SECURE (0) -#define BSP_CFG_CLOCKS_OVERRIDE (0) -#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */ -#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ -#define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */ -#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ -#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(8u,0u)) /* PLL Mul x8 */ -#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ -#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ -#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ -#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ -#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */ -#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ -#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ -#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ -#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ -#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* UCLK Src: PLL */ -#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..11d5795df --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,35 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" + +#undef RA_NOT_DEFINED +#define BSP_CFG_RTOS (0) +#if defined(_RA_BOOT_IMAGE) +#define BSP_CFG_BOOT_IMAGE (1) +#endif +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x800) +#define BSP_CFG_HEAP_BYTES (0x1000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000..444d32e56 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (4) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..d810dabb2 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA4M1AB3CFP +#define BSP_MCU_FEATURE_SET ('A') +#define BSP_ROM_SIZE_BYTES (262144) +#define BSP_RAM_SIZE_BYTES (32768) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_LQFP +#define BSP_PACKAGE_PINS (100) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..72cdb89e6 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,78 @@ +/* generated configuration header file through renesas e2 studio */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ + +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "bsp_mcu_info.h" +#include "bsp_clock_cfg.h" + +#define BSP_MCU_GROUP_RA4M1 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (24000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (32000000) +#elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (48000000) +#elif BSP_CFG_HOCO_FREQUENCY == 5 + #define BSP_HOCO_HZ (64000000) +#else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) +#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +/* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ +#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) + #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) + #else +/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +#endif + +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..d2688bf5b --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h new file mode 100644 index 000000000..554126523 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,21 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ +#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(8u,0u)) /* PLL Mul x8 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* UCLK Src: PLL */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h deleted file mode 100644 index 862ec25b7..000000000 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_cfg.h +++ /dev/null @@ -1,63 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#define RA_NOT_DEFINED 0 -#ifndef BSP_CFG_RTOS -#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) -#define BSP_CFG_RTOS (2) -#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) -#define BSP_CFG_RTOS (1) -#else -#define BSP_CFG_RTOS (0) -#endif -#endif -#ifndef BSP_CFG_RTC_USED -#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) -#endif -#undef RA_NOT_DEFINED -#if defined(_RA_BOOT_IMAGE) -#define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x800) -#define BSP_CFG_HEAP_BYTES (0x800) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) -#endif - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#endif - -#ifdef __cplusplus -} -#endif -#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h deleted file mode 100644 index 444d32e56..000000000 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_CFG_H_ -#define BSP_MCU_DEVICE_CFG_H_ -#define BSP_CFG_MCU_PART_SERIES (4) -#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index 1a0bc02e2..000000000 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA4M3AF3CFB -#define BSP_MCU_FEATURE_SET ('A') -#define BSP_ROM_SIZE_BYTES (1048576) -#define BSP_RAM_SIZE_BYTES (131072) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (144) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h deleted file mode 100644 index 26e184a94..000000000 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,386 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "../../../ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h" -#include "bsp_clock_cfg.h" -#define BSP_MCU_GROUP_RA4M3 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (16000000) -#elif BSP_CFG_HOCO_FREQUENCY == 1 - #define BSP_HOCO_HZ (18000000) - #elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (20000000) - #else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" - #endif - -#define BSP_CFG_FLL_ENABLE (0) - -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) - -#if defined(_RA_TZ_SECURE) - #define BSP_TZ_SECURE_BUILD (1) - #define BSP_TZ_NONSECURE_BUILD (0) - #elif defined(_RA_TZ_NONSECURE) - #define BSP_TZ_SECURE_BUILD (0) - #define BSP_TZ_NONSECURE_BUILD (1) - #else -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (0) -#endif - -/* TrustZone Settings */ -#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) -#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) -#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) - -/* CMSIS TrustZone Settings */ -#define SCB_CSR_AIRCR_INIT (1) -#define SCB_AIRCR_BFHFNMINS_VAL (0) -#define SCB_AIRCR_SYSRESETREQS_VAL (1) -#define SCB_AIRCR_PRIS_VAL (0) -#define TZ_FPU_NS_USAGE (1) -#ifndef SCB_NSACR_CP10_11_VAL -#define SCB_NSACR_CP10_11_VAL (3U) -#endif - -#ifndef FPU_FPCCR_TS_VAL -#define FPU_FPCCR_TS_VAL (1U) -#endif -#define FPU_FPCCR_CLRONRETS_VAL (1) - -#ifndef FPU_FPCCR_CLRONRET_VAL -#define FPU_FPCCR_CLRONRET_VAL (1) -#endif - -/* The C-Cache line size that is configured during startup. */ -#ifndef BSP_CFG_C_CACHE_LINE_SIZE -#define BSP_CFG_C_CACHE_LINE_SIZE (1U) -#endif - -/* Type 1 Peripheral Security Attribution */ - -/* Peripheral Security Attribution Register (PSAR) Settings */ -#ifndef BSP_TZ_CFG_PSARB -#define BSP_TZ_CFG_PSARB (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ - 0x33f4f9) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARC -#define BSP_TZ_CFG_PSARC (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ - 0x7fffcef4) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARD -#define BSP_TZ_CFG_PSARD (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ - (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ - 0xffae07f0) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARE -#define BSP_TZ_CFG_PSARE (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ - (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ - (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ - (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ - (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ - 0x3f3ff8) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_MSSAR -#define BSP_TZ_CFG_MSSAR (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ - 0xfffffffc) /* Unused */ -#endif - -/* Type 2 Peripheral Security Attribution */ - -/* Security attribution for Cache registers. */ -#ifndef BSP_TZ_CFG_CSAR -#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) -#endif - -/* Security attribution for RSTSRn registers. */ -#ifndef BSP_TZ_CFG_RSTSAR -#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) -#endif - -/* Security attribution for registers of LVD channels. */ -#ifndef BSP_TZ_CFG_LVDSAR -#define BSP_TZ_CFG_LVDSAR (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ - 0xFFFFFFFCU) -#endif - -/* Security attribution for LPM registers. */ -#ifndef BSP_TZ_CFG_LPMSAR -#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) -#endif -/* Deep Standby Interrupt Factor Security Attribution Register. */ -#ifndef BSP_TZ_CFG_DPFSAR -#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) -#endif - -/* Security attribution for CGC registers. */ -#ifndef BSP_TZ_CFG_CGFSAR -#if BSP_CFG_CLOCKS_SECURE -/* Protect all CGC registers from Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) -#endif -#endif - -/* Security attribution for Battery Backup registers. */ -#ifndef BSP_TZ_CFG_BBFSAR -#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) -#endif - -/* Security attribution for registers for IRQ channels. */ -#ifndef BSP_TZ_CFG_ICUSARA -#define BSP_TZ_CFG_ICUSARA (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ - (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ - (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ - 0xFFFF0000U) -#endif - -/* Security attribution for NMI registers. */ -#ifndef BSP_TZ_CFG_ICUSARB -#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ -#endif - -/* Security attribution for registers for DMAC channels */ -#ifndef BSP_TZ_CFG_ICUSARC -#define BSP_TZ_CFG_ICUSARC (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ - 0xFFFFFF00U) -#endif - -/* Security attribution registers for SELSR0. */ -#ifndef BSP_TZ_CFG_ICUSARD -#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) -#endif - -/* Security attribution registers for WUPEN0. */ -#ifndef BSP_TZ_CFG_ICUSARE -#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) -#endif - -/* Security attribution registers for WUPEN1. */ -#ifndef BSP_TZ_CFG_ICUSARF -#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) -#endif - -/* Set DTCSTSAR if the Secure program uses the DTC. */ -#if RA_NOT_DEFINED == RA_NOT_DEFINED -#define BSP_TZ_CFG_DTC_USED (0U) -#else - #define BSP_TZ_CFG_DTC_USED (1U) -#endif - -/* Security attribution of FLWT and FCKMHZ registers. */ -#ifndef BSP_TZ_CFG_FSAR -/* If the CGC registers are only accessible in Secure mode, than there is no - * reason for nonsecure applications to access FLWT and FCKMHZ. */ -#if BSP_CFG_CLOCKS_SECURE -/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ -#define BSP_TZ_CFG_FSAR (0xFEFEU) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_FSAR (0xFFFFU) -#endif -#endif - -/* Security attribution for SRAM registers. */ -#ifndef BSP_TZ_CFG_SRAMSAR -/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access - * SRAM0WTEN and therefore there is no reason to access PRCR2. */ -#define BSP_TZ_CFG_SRAMSAR (\ - 1 | \ - ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ - 4 | \ - 0xFFFFFFF8U) -#endif - -/* Security attribution for Standby RAM registers. */ -#ifndef BSP_TZ_CFG_STBRAMSAR -#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) -#endif - -/* Security attribution for the DMAC Bus Master MPU settings. */ -#ifndef BSP_TZ_CFG_MMPUSARA -/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ -#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) -#endif - -/* Security Attribution Register A for BUS Control registers. */ -#ifndef BSP_TZ_CFG_BUSSARA -#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) -#endif -/* Security Attribution Register B for BUS Control registers. */ -#ifndef BSP_TZ_CFG_BUSSARB -#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) -#endif - -/* Enable Uninitialized Non-Secure Application Fallback. */ -#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK -#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) -#endif - -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) - -/* Option Function Select Register 1 Security Attribution */ -#ifndef BSP_CFG_ROM_REG_OFS1_SEL -#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) -#else -#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) -#endif -#endif - -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) - -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) - -/* Dual Mode Select Register */ -#ifndef BSP_CFG_ROM_REG_DUALSEL -#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU) -#endif - -/* Block Protection Register 0 */ -#ifndef BSP_CFG_ROM_REG_BPS0 -#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) -#endif -/* Block Protection Register 1 */ -#ifndef BSP_CFG_ROM_REG_BPS1 -#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) -#endif -/* Block Protection Register 2 */ -#ifndef BSP_CFG_ROM_REG_BPS2 -#define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU) -#endif -/* Block Protection Register 3 */ -#ifndef BSP_CFG_ROM_REG_BPS3 -#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) -#endif -/* Permanent Block Protection Register 0 */ -#ifndef BSP_CFG_ROM_REG_PBPS0 -#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) -#endif -/* Permanent Block Protection Register 1 */ -#ifndef BSP_CFG_ROM_REG_PBPS1 -#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) -#endif -/* Permanent Block Protection Register 2 */ -#ifndef BSP_CFG_ROM_REG_PBPS2 -#define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU) -#endif -/* Permanent Block Protection Register 3 */ -#ifndef BSP_CFG_ROM_REG_PBPS3 -#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) -#endif -/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL0 -#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) -#endif -/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL1 -#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) -#endif -/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL2 -#define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU) -#endif -/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL3 -#define BSP_CFG_ROM_REG_BPS_SEL3 (0xFFFFFFFFU) -#endif -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif - -#ifdef __cplusplus -} -#endif -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h deleted file mode 100644 index 80641945d..000000000 --- a/hw/bsp/ra/boards/ra4m3_ek/fsp_cfg/bsp_clock_cfg.h +++ /dev/null @@ -1,25 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CLOCK_CFG_H_ -#define BSP_CLOCK_CFG_H_ -#define BSP_CFG_CLOCKS_SECURE (0) -#define BSP_CFG_CLOCKS_OVERRIDE (0) -#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ -#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ -#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ -#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ -#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(24U,0U) /* PLL Mul x24.0 */ -#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ -#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL2 Div /3 */ -#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(24U,0U) /* PLL2 Mul x24.0 */ -#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ -#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ -#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ -#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ -#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ -#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ -#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ -#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ -#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ -#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ -#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_4) /* UCLK Div /4 */ -#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..862ec25b7 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,63 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" + +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (2) +#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (1) +#else +#define BSP_CFG_RTOS (0) +#endif +#endif +#ifndef BSP_CFG_RTC_USED +#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) +#endif +#undef RA_NOT_DEFINED +#if defined(_RA_BOOT_IMAGE) +#define BSP_CFG_BOOT_IMAGE (1) +#endif +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x800) +#define BSP_CFG_HEAP_BYTES (0x800) +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif + +#ifdef __cplusplus +} +#endif +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000..444d32e56 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (4) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..1a0bc02e2 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA4M3AF3CFB +#define BSP_MCU_FEATURE_SET ('A') +#define BSP_ROM_SIZE_BYTES (1048576) +#define BSP_RAM_SIZE_BYTES (131072) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_LQFP +#define BSP_PACKAGE_PINS (144) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..26e184a94 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,386 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h" +#include "bsp_clock_cfg.h" +#define BSP_MCU_GROUP_RA4M3 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (16000000) +#elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif + +#define BSP_CFG_FLL_ENABLE (0) + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + +#if defined(_RA_TZ_SECURE) + #define BSP_TZ_SECURE_BUILD (1) + #define BSP_TZ_NONSECURE_BUILD (0) + #elif defined(_RA_TZ_NONSECURE) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (1) + #else +#define BSP_TZ_SECURE_BUILD (0) +#define BSP_TZ_NONSECURE_BUILD (0) +#endif + +/* TrustZone Settings */ +#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) +#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) +#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + +/* CMSIS TrustZone Settings */ +#define SCB_CSR_AIRCR_INIT (1) +#define SCB_AIRCR_BFHFNMINS_VAL (0) +#define SCB_AIRCR_SYSRESETREQS_VAL (1) +#define SCB_AIRCR_PRIS_VAL (0) +#define TZ_FPU_NS_USAGE (1) +#ifndef SCB_NSACR_CP10_11_VAL +#define SCB_NSACR_CP10_11_VAL (3U) +#endif + +#ifndef FPU_FPCCR_TS_VAL +#define FPU_FPCCR_TS_VAL (1U) +#endif +#define FPU_FPCCR_CLRONRETS_VAL (1) + +#ifndef FPU_FPCCR_CLRONRET_VAL +#define FPU_FPCCR_CLRONRET_VAL (1) +#endif + +/* The C-Cache line size that is configured during startup. */ +#ifndef BSP_CFG_C_CACHE_LINE_SIZE +#define BSP_CFG_C_CACHE_LINE_SIZE (1U) +#endif + +/* Type 1 Peripheral Security Attribution */ + +/* Peripheral Security Attribution Register (PSAR) Settings */ +#ifndef BSP_TZ_CFG_PSARB +#define BSP_TZ_CFG_PSARB (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ + (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ + 0x33f4f9) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARC +#define BSP_TZ_CFG_PSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ + 0x7fffcef4) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARD +#define BSP_TZ_CFG_PSARD (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ + (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ + 0xffae07f0) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARE +#define BSP_TZ_CFG_PSARE (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ + (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ + (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ + (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ + 0x3f3ff8) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_MSSAR +#define BSP_TZ_CFG_MSSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ + 0xfffffffc) /* Unused */ +#endif + +/* Type 2 Peripheral Security Attribution */ + +/* Security attribution for Cache registers. */ +#ifndef BSP_TZ_CFG_CSAR +#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) +#endif + +/* Security attribution for RSTSRn registers. */ +#ifndef BSP_TZ_CFG_RSTSAR +#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) +#endif + +/* Security attribution for registers of LVD channels. */ +#ifndef BSP_TZ_CFG_LVDSAR +#define BSP_TZ_CFG_LVDSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ + 0xFFFFFFFCU) +#endif + +/* Security attribution for LPM registers. */ +#ifndef BSP_TZ_CFG_LPMSAR +#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) +#endif +/* Deep Standby Interrupt Factor Security Attribution Register. */ +#ifndef BSP_TZ_CFG_DPFSAR +#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) +#endif + +/* Security attribution for CGC registers. */ +#ifndef BSP_TZ_CFG_CGFSAR +#if BSP_CFG_CLOCKS_SECURE +/* Protect all CGC registers from Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) +#endif +#endif + +/* Security attribution for Battery Backup registers. */ +#ifndef BSP_TZ_CFG_BBFSAR +#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) +#endif + +/* Security attribution for registers for IRQ channels. */ +#ifndef BSP_TZ_CFG_ICUSARA +#define BSP_TZ_CFG_ICUSARA (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ + (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ + 0xFFFF0000U) +#endif + +/* Security attribution for NMI registers. */ +#ifndef BSP_TZ_CFG_ICUSARB +#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ +#endif + +/* Security attribution for registers for DMAC channels */ +#ifndef BSP_TZ_CFG_ICUSARC +#define BSP_TZ_CFG_ICUSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ + 0xFFFFFF00U) +#endif + +/* Security attribution registers for SELSR0. */ +#ifndef BSP_TZ_CFG_ICUSARD +#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) +#endif + +/* Security attribution registers for WUPEN0. */ +#ifndef BSP_TZ_CFG_ICUSARE +#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) +#endif + +/* Security attribution registers for WUPEN1. */ +#ifndef BSP_TZ_CFG_ICUSARF +#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) +#endif + +/* Set DTCSTSAR if the Secure program uses the DTC. */ +#if RA_NOT_DEFINED == RA_NOT_DEFINED +#define BSP_TZ_CFG_DTC_USED (0U) +#else + #define BSP_TZ_CFG_DTC_USED (1U) +#endif + +/* Security attribution of FLWT and FCKMHZ registers. */ +#ifndef BSP_TZ_CFG_FSAR +/* If the CGC registers are only accessible in Secure mode, than there is no + * reason for nonsecure applications to access FLWT and FCKMHZ. */ +#if BSP_CFG_CLOCKS_SECURE +/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ +#define BSP_TZ_CFG_FSAR (0xFEFEU) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_FSAR (0xFFFFU) +#endif +#endif + +/* Security attribution for SRAM registers. */ +#ifndef BSP_TZ_CFG_SRAMSAR +/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access + * SRAM0WTEN and therefore there is no reason to access PRCR2. */ +#define BSP_TZ_CFG_SRAMSAR (\ + 1 | \ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ + 4 | \ + 0xFFFFFFF8U) +#endif + +/* Security attribution for Standby RAM registers. */ +#ifndef BSP_TZ_CFG_STBRAMSAR +#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) +#endif + +/* Security attribution for the DMAC Bus Master MPU settings. */ +#ifndef BSP_TZ_CFG_MMPUSARA +/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ +#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) +#endif + +/* Security Attribution Register A for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARA +#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) +#endif +/* Security Attribution Register B for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARB +#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) +#endif + +/* Enable Uninitialized Non-Secure Application Fallback. */ +#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK +#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) +#endif + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + +/* Option Function Select Register 1 Security Attribution */ +#ifndef BSP_CFG_ROM_REG_OFS1_SEL +#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) +#else +#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) +#endif +#endif + +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +/* Dual Mode Select Register */ +#ifndef BSP_CFG_ROM_REG_DUALSEL +#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU) +#endif + +/* Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_BPS0 +#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) +#endif +/* Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_BPS1 +#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) +#endif +/* Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_BPS2 +#define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU) +#endif +/* Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_BPS3 +#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) +#endif +/* Permanent Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_PBPS0 +#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) +#endif +/* Permanent Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_PBPS1 +#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) +#endif +/* Permanent Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_PBPS2 +#define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU) +#endif +/* Permanent Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_PBPS3 +#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) +#endif +/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL0 +#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) +#endif +/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL1 +#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) +#endif +/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL2 +#define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU) +#endif +/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL3 +#define BSP_CFG_ROM_REG_BPS_SEL3 (0xFFFFFFFFU) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..d2688bf5b --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h new file mode 100644 index 000000000..80641945d --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,25 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(24U,0U) /* PLL Mul x24.0 */ +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL2 Div /3 */ +#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(24U,0U) /* PLL2 Mul x24.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_4) /* UCLK Div /4 */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h deleted file mode 100644 index 772e5e5b1..000000000 --- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_cfg.h +++ /dev/null @@ -1,68 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#define RA_NOT_DEFINED 0 -#ifndef BSP_CFG_RTOS -#if (RA_NOT_DEFINED) != (2) -#define BSP_CFG_RTOS (2) -#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (1) -#else - #define BSP_CFG_RTOS (0) -#endif -#endif - -#ifndef BSP_CFG_RTC_USED -#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) -#endif - -#undef RA_NOT_DEFINED -#if defined(_RA_BOOT_IMAGE) - #define BSP_CFG_BOOT_IMAGE (1) -#endif - -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x1000) -#define BSP_CFG_HEAP_BYTES (0x1000) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) -#endif - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h deleted file mode 100644 index bd6a901c3..000000000 --- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_CFG_H_ -#define BSP_MCU_DEVICE_CFG_H_ -#define BSP_CFG_MCU_PART_SERIES (6) -#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index 40bb3a3bf..000000000 --- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA6M1AD3CFP -#define BSP_MCU_FEATURE_SET ('A') -#define BSP_ROM_SIZE_BYTES (524288) -#define BSP_RAM_SIZE_BYTES (262144) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (100) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h deleted file mode 100644 index 5fedd754f..000000000 --- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,84 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h" -#include "bsp_clock_cfg.h" - -#define BSP_MCU_GROUP_RA6M1 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (16000000) -#elif BSP_CFG_HOCO_FREQUENCY == 1 - #define BSP_HOCO_HZ (18000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (20000000) -#else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif - -#define BSP_CFG_FLL_ENABLE (0) - -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) - -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) -#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF) -#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) - -/* - ID Code - Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. - WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. - */ -#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) - #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) -#else - /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ - #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) - #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) - #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) - #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) -#endif - -#ifdef __cplusplus -} -#endif -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h deleted file mode 100644 index 945a6010b..000000000 --- a/hw/bsp/ra/boards/ra6m1_ek/fsp_cfg/bsp_clock_cfg.h +++ /dev/null @@ -1,23 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CLOCK_CFG_H_ -#define BSP_CLOCK_CFG_H_ -#define BSP_CFG_CLOCKS_SECURE (0) -#define BSP_CFG_CLOCKS_OVERRIDE (0) -#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */ -#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ -#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ -#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */ -#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL Mul x20.0 */ -#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ -#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ -#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ -#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ -#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ -#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ -#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ -#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ -#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ -#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ -#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ -#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ -#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..772e5e5b1 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,68 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" + +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (2) +#define BSP_CFG_RTOS (2) +#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) +#else + #define BSP_CFG_RTOS (0) +#endif +#endif + +#ifndef BSP_CFG_RTC_USED +#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) +#endif + +#undef RA_NOT_DEFINED +#if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) +#endif + +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x1000) +#define BSP_CFG_HEAP_BYTES (0x1000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000..bd6a901c3 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (6) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..40bb3a3bf --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA6M1AD3CFP +#define BSP_MCU_FEATURE_SET ('A') +#define BSP_ROM_SIZE_BYTES (524288) +#define BSP_RAM_SIZE_BYTES (262144) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_LQFP +#define BSP_PACKAGE_PINS (100) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..5fedd754f --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,84 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h" +#include "bsp_clock_cfg.h" + +#define BSP_MCU_GROUP_RA6M1 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (16000000) +#elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) +#else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif + +#define BSP_CFG_FLL_ENABLE (0) + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF) +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +/* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ +#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) + #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) +#else + /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ + #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..d2688bf5b --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/bsp_clock_cfg.h new file mode 100644 index 000000000..945a6010b --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,23 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL Mul x20.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake index c91d48a32..2adf6e744 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake +++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake @@ -2,6 +2,7 @@ set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra6m5) set(JLINK_DEVICE R7FA6M5BH) +set(JLINK_OPTION "-USB 000831915224") # Device port default to PORT1 Highspeed if (NOT DEFINED PORT) diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h deleted file mode 100644 index 33d381850..000000000 --- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_cfg.h +++ /dev/null @@ -1,63 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#define RA_NOT_DEFINED 0 -#ifndef BSP_CFG_RTOS -#if (RA_NOT_DEFINED) != (2) -#define BSP_CFG_RTOS (2) -#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (1) -#else - #define BSP_CFG_RTOS (0) -#endif -#endif -#ifndef BSP_CFG_RTC_USED -#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) -#endif -#undef RA_NOT_DEFINED -#if defined(_RA_BOOT_IMAGE) - #define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x1000) -#define BSP_CFG_HEAP_BYTES (0x1000) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) -#endif - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#endif - -#ifdef __cplusplus -} -#endif -#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h deleted file mode 100644 index bd6a901c3..000000000 --- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_CFG_H_ -#define BSP_MCU_DEVICE_CFG_H_ -#define BSP_CFG_MCU_PART_SERIES (6) -#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index 6845183db..000000000 --- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA6M5BH3CFC -#define BSP_MCU_FEATURE_SET ('B') -#define BSP_ROM_SIZE_BYTES (2097152) -#define BSP_RAM_SIZE_BYTES (524288) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (176) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h deleted file mode 100644 index d5428540f..000000000 --- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,387 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ -#ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" -#include "bsp_clock_cfg.h" - -#define BSP_MCU_GROUP_RA6M5 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (16000000) -#elif BSP_CFG_HOCO_FREQUENCY == 1 - #define BSP_HOCO_HZ (18000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (20000000) -#else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif - -#define BSP_CFG_FLL_ENABLE (0) - -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) - -#if defined(_RA_TZ_SECURE) - #define BSP_TZ_SECURE_BUILD (1) - #define BSP_TZ_NONSECURE_BUILD (0) - #elif defined(_RA_TZ_NONSECURE) - #define BSP_TZ_SECURE_BUILD (0) - #define BSP_TZ_NONSECURE_BUILD (1) - #else -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (0) -#endif - -/* TrustZone Settings */ -#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) -#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) -#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) - -/* CMSIS TrustZone Settings */ -#define SCB_CSR_AIRCR_INIT (1) -#define SCB_AIRCR_BFHFNMINS_VAL (0) -#define SCB_AIRCR_SYSRESETREQS_VAL (1) -#define SCB_AIRCR_PRIS_VAL (0) -#define TZ_FPU_NS_USAGE (1) -#ifndef SCB_NSACR_CP10_11_VAL -#define SCB_NSACR_CP10_11_VAL (3U) -#endif - -#ifndef FPU_FPCCR_TS_VAL -#define FPU_FPCCR_TS_VAL (1U) -#endif -#define FPU_FPCCR_CLRONRETS_VAL (1) - -#ifndef FPU_FPCCR_CLRONRET_VAL -#define FPU_FPCCR_CLRONRET_VAL (1) -#endif - -/* The C-Cache line size that is configured during startup. */ -#ifndef BSP_CFG_C_CACHE_LINE_SIZE -#define BSP_CFG_C_CACHE_LINE_SIZE (1U) -#endif - -/* Type 1 Peripheral Security Attribution */ - -/* Peripheral Security Attribution Register (PSAR) Settings */ -#ifndef BSP_TZ_CFG_PSARB -#define BSP_TZ_CFG_PSARB (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ - 0x33f4f9) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARC -#define BSP_TZ_CFG_PSARC (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ - 0x7fffcef4) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARD -#define BSP_TZ_CFG_PSARD (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ - 0xffae07f0) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_PSARE -#define BSP_TZ_CFG_PSARE (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ - 0x3f3ff8) /* Unused */ -#endif -#ifndef BSP_TZ_CFG_MSSAR -#define BSP_TZ_CFG_MSSAR (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ - 0xfffffffc) /* Unused */ -#endif - -/* Type 2 Peripheral Security Attribution */ - -/* Security attribution for Cache registers. */ -#ifndef BSP_TZ_CFG_CSAR -#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) -#endif - -/* Security attribution for RSTSRn registers. */ -#ifndef BSP_TZ_CFG_RSTSAR -#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) -#endif - -/* Security attribution for registers of LVD channels. */ -#ifndef BSP_TZ_CFG_LVDSAR -#define BSP_TZ_CFG_LVDSAR (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ - 0xFFFFFFFCU) -#endif - -/* Security attribution for LPM registers. */ -#ifndef BSP_TZ_CFG_LPMSAR -#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) -#endif -/* Deep Standby Interrupt Factor Security Attribution Register. */ -#ifndef BSP_TZ_CFG_DPFSAR -#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) -#endif - -/* Security attribution for CGC registers. */ -#ifndef BSP_TZ_CFG_CGFSAR -#if BSP_CFG_CLOCKS_SECURE -/* Protect all CGC registers from Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) -#endif -#endif - -/* Security attribution for Battery Backup registers. */ -#ifndef BSP_TZ_CFG_BBFSAR -#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) -#endif - -/* Security attribution for registers for IRQ channels. */ -#ifndef BSP_TZ_CFG_ICUSARA -#define BSP_TZ_CFG_ICUSARA (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ - 0xFFFF0000U) -#endif - -/* Security attribution for NMI registers. */ -#ifndef BSP_TZ_CFG_ICUSARB -#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ -#endif - -/* Security attribution for registers for DMAC channels */ -#ifndef BSP_TZ_CFG_ICUSARC -#define BSP_TZ_CFG_ICUSARC (\ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ - 0xFFFFFF00U) -#endif - -/* Security attribution registers for SELSR0. */ -#ifndef BSP_TZ_CFG_ICUSARD -#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) -#endif - -/* Security attribution registers for WUPEN0. */ -#ifndef BSP_TZ_CFG_ICUSARE -#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) -#endif - -/* Security attribution registers for WUPEN1. */ -#ifndef BSP_TZ_CFG_ICUSARF -#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) -#endif - -/* Set DTCSTSAR if the Secure program uses the DTC. */ -#if RA_NOT_DEFINED == RA_NOT_DEFINED -#define BSP_TZ_CFG_DTC_USED (0U) -#else - #define BSP_TZ_CFG_DTC_USED (1U) -#endif - -/* Security attribution of FLWT and FCKMHZ registers. */ -#ifndef BSP_TZ_CFG_FSAR -/* If the CGC registers are only accessible in Secure mode, than there is no - * reason for nonsecure applications to access FLWT and FCKMHZ. */ -#if BSP_CFG_CLOCKS_SECURE -/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ -#define BSP_TZ_CFG_FSAR (0xFEFEU) -#else -/* Allow Secure and Non-secure write access. */ -#define BSP_TZ_CFG_FSAR (0xFFFFU) -#endif -#endif - -/* Security attribution for SRAM registers. */ -#ifndef BSP_TZ_CFG_SRAMSAR -/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access - * SRAM0WTEN and therefore there is no reason to access PRCR2. */ -#define BSP_TZ_CFG_SRAMSAR (\ - 1 | \ - ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ - 4 | \ - 0xFFFFFFF8U) -#endif - -/* Security attribution for Standby RAM registers. */ -#ifndef BSP_TZ_CFG_STBRAMSAR -#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) -#endif - -/* Security attribution for the DMAC Bus Master MPU settings. */ -#ifndef BSP_TZ_CFG_MMPUSARA -/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ -#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) -#endif - -/* Security Attribution Register A for BUS Control registers. */ -#ifndef BSP_TZ_CFG_BUSSARA -#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) -#endif -/* Security Attribution Register B for BUS Control registers. */ -#ifndef BSP_TZ_CFG_BUSSARB -#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) -#endif - -/* Enable Uninitialized Non-Secure Application Fallback. */ -#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK -#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) -#endif - -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) - -/* Option Function Select Register 1 Security Attribution */ -#ifndef BSP_CFG_ROM_REG_OFS1_SEL -#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) -#else -#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) -#endif -#endif - -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) - -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) - -/* Dual Mode Select Register */ -#ifndef BSP_CFG_ROM_REG_DUALSEL -#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) -#endif - -/* Block Protection Register 0 */ -#ifndef BSP_CFG_ROM_REG_BPS0 -#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) -#endif -/* Block Protection Register 1 */ -#ifndef BSP_CFG_ROM_REG_BPS1 -#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) -#endif -/* Block Protection Register 2 */ -#ifndef BSP_CFG_ROM_REG_BPS2 -#define BSP_CFG_ROM_REG_BPS2 (~( 0U)) -#endif -/* Block Protection Register 3 */ -#ifndef BSP_CFG_ROM_REG_BPS3 -#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) -#endif -/* Permanent Block Protection Register 0 */ -#ifndef BSP_CFG_ROM_REG_PBPS0 -#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) -#endif -/* Permanent Block Protection Register 1 */ -#ifndef BSP_CFG_ROM_REG_PBPS1 -#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) -#endif -/* Permanent Block Protection Register 2 */ -#ifndef BSP_CFG_ROM_REG_PBPS2 -#define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) -#endif -/* Permanent Block Protection Register 3 */ -#ifndef BSP_CFG_ROM_REG_PBPS3 -#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) -#endif -/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL0 -#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) -#endif -/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL1 -#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) -#endif -/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL2 -#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) -#endif -/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ -#ifndef BSP_CFG_ROM_REG_BPS_SEL3 -#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) -#endif -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif - -#ifdef __cplusplus -} -#endif -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h deleted file mode 100644 index 0eb5e0516..000000000 --- a/hw/bsp/ra/boards/ra6m5_ek/fsp_cfg/bsp_clock_cfg.h +++ /dev/null @@ -1,37 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CLOCK_CFG_H_ -#define BSP_CLOCK_CFG_H_ - -#define BSP_CFG_CLOCKS_SECURE (0) -#define BSP_CFG_CLOCKS_OVERRIDE (0) -#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ -#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ -#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ -#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ -#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(25U,0U)) /* PLL Mul x25.0 */ -#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ -#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ -#define BSP_CFG_PLL2_MUL (BSP_CLOCKS_PLL_MUL(20U,0U)) /* PLL2 Mul x20.0 */ -#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ -#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ -#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ -#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */ -#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ -#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ -#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ -#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ -#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ -#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ -#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ -#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ -#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ -#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ -#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ -#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ -#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ -#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */ -#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ -#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */ -#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ - -#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..33d381850 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,63 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" + +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (2) +#define BSP_CFG_RTOS (2) +#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) +#else + #define BSP_CFG_RTOS (0) +#endif +#endif +#ifndef BSP_CFG_RTC_USED +#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) +#endif +#undef RA_NOT_DEFINED +#if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) +#endif +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x1000) +#define BSP_CFG_HEAP_BYTES (0x1000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif + +#ifdef __cplusplus +} +#endif +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000..bd6a901c3 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (6) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..6845183db --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA6M5BH3CFC +#define BSP_MCU_FEATURE_SET ('B') +#define BSP_ROM_SIZE_BYTES (2097152) +#define BSP_RAM_SIZE_BYTES (524288) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_LQFP +#define BSP_PACKAGE_PINS (176) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..d5428540f --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,387 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" +#include "bsp_clock_cfg.h" + +#define BSP_MCU_GROUP_RA6M5 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (16000000) +#elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) +#else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif + +#define BSP_CFG_FLL_ENABLE (0) + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + +#if defined(_RA_TZ_SECURE) + #define BSP_TZ_SECURE_BUILD (1) + #define BSP_TZ_NONSECURE_BUILD (0) + #elif defined(_RA_TZ_NONSECURE) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (1) + #else +#define BSP_TZ_SECURE_BUILD (0) +#define BSP_TZ_NONSECURE_BUILD (0) +#endif + +/* TrustZone Settings */ +#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) +#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) +#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + +/* CMSIS TrustZone Settings */ +#define SCB_CSR_AIRCR_INIT (1) +#define SCB_AIRCR_BFHFNMINS_VAL (0) +#define SCB_AIRCR_SYSRESETREQS_VAL (1) +#define SCB_AIRCR_PRIS_VAL (0) +#define TZ_FPU_NS_USAGE (1) +#ifndef SCB_NSACR_CP10_11_VAL +#define SCB_NSACR_CP10_11_VAL (3U) +#endif + +#ifndef FPU_FPCCR_TS_VAL +#define FPU_FPCCR_TS_VAL (1U) +#endif +#define FPU_FPCCR_CLRONRETS_VAL (1) + +#ifndef FPU_FPCCR_CLRONRET_VAL +#define FPU_FPCCR_CLRONRET_VAL (1) +#endif + +/* The C-Cache line size that is configured during startup. */ +#ifndef BSP_CFG_C_CACHE_LINE_SIZE +#define BSP_CFG_C_CACHE_LINE_SIZE (1U) +#endif + +/* Type 1 Peripheral Security Attribution */ + +/* Peripheral Security Attribution Register (PSAR) Settings */ +#ifndef BSP_TZ_CFG_PSARB +#define BSP_TZ_CFG_PSARB (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ + (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* SCI6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* SCI5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */ | \ + 0x33f4f9) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARC +#define BSP_TZ_CFG_PSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* CTSU */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCE9 */ | \ + 0x7fffcef4) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARD +#define BSP_TZ_CFG_PSARD (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* AGT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* AGT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* AGT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* AGT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ + 0xffae07f0) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_PSARE +#define BSP_TZ_CFG_PSARE (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* WDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* IWDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* RTC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* AGT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* AGT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ + 0x3f3ff8) /* Unused */ +#endif +#ifndef BSP_TZ_CFG_MSSAR +#define BSP_TZ_CFG_MSSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ + 0xfffffffc) /* Unused */ +#endif + +/* Type 2 Peripheral Security Attribution */ + +/* Security attribution for Cache registers. */ +#ifndef BSP_TZ_CFG_CSAR +#define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) +#endif + +/* Security attribution for RSTSRn registers. */ +#ifndef BSP_TZ_CFG_RSTSAR +#define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) +#endif + +/* Security attribution for registers of LVD channels. */ +#ifndef BSP_TZ_CFG_LVDSAR +#define BSP_TZ_CFG_LVDSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) | /* LVD Channel 2 */ \ + 0xFFFFFFFCU) +#endif + +/* Security attribution for LPM registers. */ +#ifndef BSP_TZ_CFG_LPMSAR +#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) +#endif +/* Deep Standby Interrupt Factor Security Attribution Register. */ +#ifndef BSP_TZ_CFG_DPFSAR +#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) +#endif + +/* Security attribution for CGC registers. */ +#ifndef BSP_TZ_CFG_CGFSAR +#if BSP_CFG_CLOCKS_SECURE +/* Protect all CGC registers from Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFCE402U) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0xFFFFFFFFU) +#endif +#endif + +/* Security attribution for Battery Backup registers. */ +#ifndef BSP_TZ_CFG_BBFSAR +#define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) +#endif + +/* Security attribution for registers for IRQ channels. */ +#ifndef BSP_TZ_CFG_ICUSARA +#define BSP_TZ_CFG_ICUSARA (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */ | \ + 0xFFFF0000U) +#endif + +/* Security attribution for NMI registers. */ +#ifndef BSP_TZ_CFG_ICUSARB +#define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ +#endif + +/* Security attribution for registers for DMAC channels */ +#ifndef BSP_TZ_CFG_ICUSARC +#define BSP_TZ_CFG_ICUSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */ | \ + 0xFFFFFF00U) +#endif + +/* Security attribution registers for SELSR0. */ +#ifndef BSP_TZ_CFG_ICUSARD +#define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) +#endif + +/* Security attribution registers for WUPEN0. */ +#ifndef BSP_TZ_CFG_ICUSARE +#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) +#endif + +/* Security attribution registers for WUPEN1. */ +#ifndef BSP_TZ_CFG_ICUSARF +#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) +#endif + +/* Set DTCSTSAR if the Secure program uses the DTC. */ +#if RA_NOT_DEFINED == RA_NOT_DEFINED +#define BSP_TZ_CFG_DTC_USED (0U) +#else + #define BSP_TZ_CFG_DTC_USED (1U) +#endif + +/* Security attribution of FLWT and FCKMHZ registers. */ +#ifndef BSP_TZ_CFG_FSAR +/* If the CGC registers are only accessible in Secure mode, than there is no + * reason for nonsecure applications to access FLWT and FCKMHZ. */ +#if BSP_CFG_CLOCKS_SECURE +/* Protect FLWT and FCKMHZ registers from nonsecure write access. */ +#define BSP_TZ_CFG_FSAR (0xFEFEU) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_FSAR (0xFFFFU) +#endif +#endif + +/* Security attribution for SRAM registers. */ +#ifndef BSP_TZ_CFG_SRAMSAR +/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access + * SRAM0WTEN and therefore there is no reason to access PRCR2. */ +#define BSP_TZ_CFG_SRAMSAR (\ + 1 | \ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ + 4 | \ + 0xFFFFFFF8U) +#endif + +/* Security attribution for Standby RAM registers. */ +#ifndef BSP_TZ_CFG_STBRAMSAR +#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) +#endif + +/* Security attribution for the DMAC Bus Master MPU settings. */ +#ifndef BSP_TZ_CFG_MMPUSARA +/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ +#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) +#endif + +/* Security Attribution Register A for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARA +#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) +#endif +/* Security Attribution Register B for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARB +#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) +#endif + +/* Enable Uninitialized Non-Secure Application Fallback. */ +#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK +#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) +#endif + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + +/* Option Function Select Register 1 Security Attribution */ +#ifndef BSP_CFG_ROM_REG_OFS1_SEL +#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) +#else +#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) +#endif +#endif + +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +/* Dual Mode Select Register */ +#ifndef BSP_CFG_ROM_REG_DUALSEL +#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) +#endif + +/* Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_BPS0 +#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) +#endif +/* Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_BPS1 +#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) +#endif +/* Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_BPS2 +#define BSP_CFG_ROM_REG_BPS2 (~( 0U)) +#endif +/* Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_BPS3 +#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) +#endif +/* Permanent Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_PBPS0 +#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) +#endif +/* Permanent Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_PBPS1 +#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) +#endif +/* Permanent Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_PBPS2 +#define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) +#endif +/* Permanent Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_PBPS3 +#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) +#endif +/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL0 +#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) +#endif +/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL1 +#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) +#endif +/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL2 +#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) +#endif +/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL3 +#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif + +#ifdef __cplusplus +} +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..d2688bf5b --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/bsp_clock_cfg.h new file mode 100644 index 000000000..0eb5e0516 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,37 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ + +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ +#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(25U,0U)) /* PLL Mul x25.0 */ +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ +#define BSP_CFG_PLL2_MUL (BSP_CLOCKS_PLL_MUL(20U,0U)) /* PLL2 Mul x20.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ +#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */ +#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ +#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ +#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ +#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */ +#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ +#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */ +#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ + +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h deleted file mode 100644 index c1d1022cc..000000000 --- a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_cfg.h +++ /dev/null @@ -1,35 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CFG_H_ -#define BSP_CFG_H_ - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#undef RA_NOT_DEFINED -#define BSP_CFG_RTOS (0) -#if defined(_RA_BOOT_IMAGE) -#define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x800) -#define BSP_CFG_HEAP_BYTES (0x1000) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0) - -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (0) -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 - -#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h deleted file mode 100644 index 444d32e56..000000000 --- a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_cfg.h +++ /dev/null @@ -1,5 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_CFG_H_ -#define BSP_MCU_DEVICE_CFG_H_ -#define BSP_CFG_MCU_PART_SERIES (4) -#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h deleted file mode 100644 index 336918800..000000000 --- a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ /dev/null @@ -1,11 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_DEVICE_PN_CFG_H_ -#define BSP_MCU_R7FA4M1AB3CNE -#define BSP_MCU_FEATURE_SET ('A') -#define BSP_ROM_SIZE_BYTES (262144) -#define BSP_RAM_SIZE_BYTES (32768) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_QFN -#define BSP_PACKAGE_PINS (48) -#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h deleted file mode 100644 index fc604eb3b..000000000 --- a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ /dev/null @@ -1,87 +0,0 @@ -/* generated configuration header file through renesas e2 studio */ -#ifndef BSP_MCU_FAMILY_CFG_H_ -#define BSP_MCU_FAMILY_CFG_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "bsp_mcu_info.h" -#include "bsp_clock_cfg.h" - -#define BSP_MCU_GROUP_RA4M1 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 - #define BSP_HOCO_HZ (24000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (32000000) -#elif BSP_CFG_HOCO_FREQUENCY == 4 - #define BSP_HOCO_HZ (48000000) -#elif BSP_CFG_HOCO_FREQUENCY == 5 - #define BSP_HOCO_HZ (64000000) -#else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) -#define BSP_MCU_VBATT_SUPPORT (1) - -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) -#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) -#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) - -/* - ID Code - Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. - WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. - */ -#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) - #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) - #else -/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ -#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h b/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h deleted file mode 100644 index 63618ec4b..000000000 --- a/hw/bsp/ra/boards/uno_r4/fsp_cfg/bsp_clock_cfg.h +++ /dev/null @@ -1,21 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef BSP_CLOCK_CFG_H_ -#define BSP_CLOCK_CFG_H_ -#define BSP_CFG_CLOCKS_SECURE (0) -#define BSP_CFG_CLOCKS_OVERRIDE (0) -#define BSP_CFG_XTAL_HZ (0) /* XTAL 0Hz */ -#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL Src: XTAL */ -#define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */ -#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_4) /* PLL Div /4 */ -#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(12, 0) /* PLL Mul x12 */ -#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */ -#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ -#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ -#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ -#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */ -#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ -#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ -#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Src: SUBCLK */ -#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ -#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* UCLK Src: HOCO */ -#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..c1d1022cc --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,35 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ + +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" + +#undef RA_NOT_DEFINED +#define BSP_CFG_RTOS (0) +#if defined(_RA_BOOT_IMAGE) +#define BSP_CFG_BOOT_IMAGE (1) +#endif +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x800) +#define BSP_CFG_HEAP_BYTES (0x1000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (1) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) +#define BSP_CFG_EARLY_INIT ((0)) + +#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0) + +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (0) +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000..444d32e56 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (4) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..336918800 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA4M1AB3CNE +#define BSP_MCU_FEATURE_SET ('A') +#define BSP_ROM_SIZE_BYTES (262144) +#define BSP_RAM_SIZE_BYTES (32768) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_QFN +#define BSP_PACKAGE_PINS (48) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..fc604eb3b --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,87 @@ +/* generated configuration header file through renesas e2 studio */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "bsp_mcu_info.h" +#include "bsp_clock_cfg.h" + +#define BSP_MCU_GROUP_RA4M1 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (24000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (32000000) +#elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (48000000) +#elif BSP_CFG_HOCO_FREQUENCY == 5 + #define BSP_HOCO_HZ (64000000) +#else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) +#define BSP_MCU_VBATT_SUPPORT (1) + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) +#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + +/* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ +#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) + #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) + #else +/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..d2688bf5b --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h new file mode 100644 index 000000000..63618ec4b --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,21 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (0) /* XTAL 0Hz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL Src: XTAL */ +#define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_4) /* PLL Div /4 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(12, 0) /* PLL Mul x12 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Src: SUBCLK */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* UCLK Src: HOCO */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 426e1ca8f..3b35d2e71 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -44,8 +44,9 @@ function(add_board_target BOARD_TARGET) target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/fsp_cfg/bsp + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_cfg/fsp_cfg + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_cfg/fsp_cfg/bsp + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen ${CMSIS_DIR}/CMSIS/Core/Include ${FSP_RA}/inc ${FSP_RA}/inc/api diff --git a/hw/bsp/ra/r_ioport_cfg.h b/hw/bsp/ra/r_ioport_cfg.h deleted file mode 100644 index cb7c07932..000000000 --- a/hw/bsp/ra/r_ioport_cfg.h +++ /dev/null @@ -1,7 +0,0 @@ -/* generated configuration header file - do not edit */ -#ifndef R_IOPORT_CFG_H_ -#define R_IOPORT_CFG_H_ - -#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) - -#endif /* R_IOPORT_CFG_H_ */ -- cgit v1.3.1 From 69dd473a4c7d745bc1b535024b3ed89d2c922dcd Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 12 Dec 2024 12:39:34 +0700 Subject: more migrate to ra smart configurator --- .idea/cmake.xml | 5 +- hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld | 766 +++++++++++++++++++++ hw/bsp/ra/boards/ra6m1_ek/script/memory_regions.ld | 22 + .../ra6m1_ek/smart_configurator/configuration.xml | 299 ++++++++ .../ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 235 +++---- hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld | 766 +++++++++++++++++++++ hw/bsp/ra/boards/ra6m5_ek/script/memory_regions.ld | 22 + .../ra6m5_ek/smart_configurator/configuration.xml | 651 +++++++++++++++++ .../ra8m1_ek/smart_configurator/configuration.xml | 624 +++++++++++++++++ hw/bsp/ra/boards/uno_r4/board.cmake | 4 - .../ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 89 ++- .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 12 +- .../uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 145 ++-- hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h | 6 +- hw/bsp/ra/boards/uno_r4/script/fsp.ld | 766 +++++++++++++++++++++ hw/bsp/ra/boards/uno_r4/script/memory_regions.ld | 25 + .../uno_r4/smart_configurator/configuration.xml | 205 ++++++ hw/bsp/ra/boards/uno_r4/uno_r4.ld | 25 - hw/bsp/ra/family.cmake | 13 +- tools/get_deps.py | 9 +- 20 files changed, 4420 insertions(+), 269 deletions(-) create mode 100644 hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld create mode 100644 hw/bsp/ra/boards/ra6m1_ek/script/memory_regions.ld create mode 100644 hw/bsp/ra/boards/ra6m1_ek/smart_configurator/configuration.xml create mode 100644 hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld create mode 100644 hw/bsp/ra/boards/ra6m5_ek/script/memory_regions.ld create mode 100644 hw/bsp/ra/boards/ra6m5_ek/smart_configurator/configuration.xml create mode 100644 hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml create mode 100644 hw/bsp/ra/boards/uno_r4/script/fsp.ld create mode 100644 hw/bsp/ra/boards/uno_r4/script/memory_regions.ld create mode 100644 hw/bsp/ra/boards/uno_r4/smart_configurator/configuration.xml delete mode 100644 hw/bsp/ra/boards/uno_r4/uno_r4.ld (limited to 'hw') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 5af6d7722..6e58f040c 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -118,9 +118,10 @@ - - + + + diff --git a/hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld new file mode 100644 index 000000000..627ffe4d9 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld @@ -0,0 +1,766 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + +/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ +/* + XIP_SECONDARY_SLOT_IMAGE = 1; +*/ + +QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); +OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); +OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); + +/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ +__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); + +ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; +ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; +DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; +DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; +RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; +RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; +RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; +RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; + +OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; + +/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. + * Bootloader images do not configure option settings because they are owned by the bootloader. + * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ +__bl_FSP_BOOTABLE_IMAGE = 1; +__bln_FSP_BOOTABLE_IMAGE = 1; +PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); + +__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; +__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; +__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; +__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; +__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); +__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; + +XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; +FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : + XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : + FLASH_IMAGE_START; +LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : + DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : + FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; + +/* Define memory regions. */ +MEMORY +{ + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be DEFINED in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * __qspi_flash_start__ + * __qspi_flash_end__ + * __qspi_flash_code_size__ + * __qspi_region_max_size__ + * __qspi_region_start_address__ + * __qspi_region_end_address__ + * __ospi_device_0_start__ + * __ospi_device_0_end__ + * __ospi_device_0_code_size__ + * __ospi_device_0_region_max_size__ + * __ospi_device_0_region_start_address__ + * __ospi_device_0_region_end_address__ + * __ospi_device_1_start__ + * __ospi_device_1_end__ + * __ospi_device_1_code_size__ + * __ospi_device_1_region_max_size__ + * __ospi_device_1_region_start_address__ + * __ospi_device_1_region_end_address__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __tz_FLASH_S = ABSOLUTE(FLASH_START); + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + + /* Some devices have a gap of code flash between the vector table and ROM Registers. + * The flash gap section allows applications to place code and data in this section. */ + *(.flash_gap*) + + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Allocate flash write-boundary-aligned + * space for sce9 wrapped public keys for mcuboot if the module is used. + */ + KEEP(*(.mcuboot_sce9_key*)) + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) + { + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; + + __exidx_start = .; + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); + + /* Initialized DTCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) + { + /* Start of DTCM Secure Trustzone region. */ + __tz_DTCM_S = ABSOLUTE(DTCM_START); + + /* Initialized DTCM data start */ + __dtcm_data_start = .; + + KEEP(*(.dtcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; + /* Uninitialized DTCM data. */ + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : + { + /* Uninitialized DTCM data start */ + __dtcm_bss_start = .; + + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); + + /* Uninitialized DTCM data end */ + __dtcm_bss_end = .; + + /* + * Start of the DTCM Non-Secure Trustzone region. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. + */ + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); + } > DTCM + + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ + . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; + + KEEP(*(.ns_buffer*)) + } > RAM + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. + * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE + * memory region between TrustZone projects. */ + __tz_ID_CODE_N = __tz_ID_CODE_S; + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); + + .option_setting_ofs : + { + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_ofs2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; + } > OPTION_SETTING_OFS = 0xFF + + .option_setting_sas : + { + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; + } > OPTION_SETTING_SAS = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_ofs3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; +} diff --git a/hw/bsp/ra/boards/ra6m1_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra6m1_ek/script/memory_regions.ld new file mode 100644 index 000000000..9d973c737 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/script/memory_regions.ld @@ -0,0 +1,22 @@ + + /* generated memory regions file - do not edit */ + RAM_START = 0x1FFE0000; + RAM_LENGTH = 0x40000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x80000; + DATA_FLASH_START = 0x40100000; + DATA_FLASH_LENGTH = 0x2000; + OPTION_SETTING_START = 0x00000000; + OPTION_SETTING_LENGTH = 0x0; + OPTION_SETTING_S_START = 0x80000000; + OPTION_SETTING_S_LENGTH = 0x0; + ID_CODE_START = 0x0100A150; + ID_CODE_LENGTH = 0x10; + SDRAM_START = 0x80010000; + SDRAM_LENGTH = 0x0; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x4000000; + OSPI_DEVICE_0_START = 0x80020000; + OSPI_DEVICE_0_LENGTH = 0x0; + OSPI_DEVICE_1_START = 0x80030000; + OSPI_DEVICE_1_LENGTH = 0x0; diff --git a/hw/bsp/ra/boards/ra6m1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra6m1_ek/smart_configurator/configuration.xml new file mode 100644 index 000000000..2f373930c --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/smart_configurator/configuration.xml @@ -0,0 +1,299 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Simple application that blinks an LED. No RTOS included. + Renesas.RA_baremetal_blinky.5.6.0.pack + + + Board Support Package Common Files + Renesas.RA.5.6.0.pack + + + I/O Port + Renesas.RA.5.6.0.pack + + + Arm CMSIS Version 6 - Core (M) + Arm.CMSIS6.6.1.0+fsp.5.6.0.pack + + + RA6M1-EK Board Support Files + Renesas.RA_board_ra6m1_ek.5.6.0.pack + + + Board support package for R7FA6M1AD3CFP + Renesas.RA_mcu_ra6m1.5.6.0.pack + + + Board support package for RA6M1 + Renesas.RA_mcu_ra6m1.5.6.0.pack + + + Board support package for RA6M1 - FSP Data + Renesas.RA_mcu_ra6m1.5.6.0.pack + + + Board support package for RA6M1 - Events + Renesas.RA_mcu_ra6m1.5.6.0.pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h index d5428540f..c01219377 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -5,80 +5,80 @@ extern "C" { #endif -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" -#include "bsp_clock_cfg.h" - -#define BSP_MCU_GROUP_RA6M5 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (16000000) -#elif BSP_CFG_HOCO_FREQUENCY == 1 - #define BSP_HOCO_HZ (18000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (20000000) -#else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA6M5 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) + #elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif -#define BSP_CFG_FLL_ENABLE (0) + #define BSP_CFG_FLL_ENABLE (0) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) -#if defined(_RA_TZ_SECURE) + #if defined(_RA_TZ_SECURE) #define BSP_TZ_SECURE_BUILD (1) #define BSP_TZ_NONSECURE_BUILD (0) #elif defined(_RA_TZ_NONSECURE) #define BSP_TZ_SECURE_BUILD (0) #define BSP_TZ_NONSECURE_BUILD (1) #else -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (0) -#endif - -/* TrustZone Settings */ -#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) -#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) -#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) - -/* CMSIS TrustZone Settings */ -#define SCB_CSR_AIRCR_INIT (1) -#define SCB_AIRCR_BFHFNMINS_VAL (0) -#define SCB_AIRCR_SYSRESETREQS_VAL (1) -#define SCB_AIRCR_PRIS_VAL (0) -#define TZ_FPU_NS_USAGE (1) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (0) + #endif + + /* TrustZone Settings */ + #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) + #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) + #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + + /* CMSIS TrustZone Settings */ + #define SCB_CSR_AIRCR_INIT (1) + #define SCB_AIRCR_BFHFNMINS_VAL (0) + #define SCB_AIRCR_SYSRESETREQS_VAL (1) + #define SCB_AIRCR_PRIS_VAL (0) + #define TZ_FPU_NS_USAGE (1) #ifndef SCB_NSACR_CP10_11_VAL -#define SCB_NSACR_CP10_11_VAL (3U) + #define SCB_NSACR_CP10_11_VAL (3U) #endif #ifndef FPU_FPCCR_TS_VAL -#define FPU_FPCCR_TS_VAL (1U) + #define FPU_FPCCR_TS_VAL (1U) #endif -#define FPU_FPCCR_CLRONRETS_VAL (1) + #define FPU_FPCCR_CLRONRETS_VAL (1) #ifndef FPU_FPCCR_CLRONRET_VAL -#define FPU_FPCCR_CLRONRET_VAL (1) + #define FPU_FPCCR_CLRONRET_VAL (1) #endif -/* The C-Cache line size that is configured during startup. */ + /* The C-Cache line size that is configured during startup. */ #ifndef BSP_CFG_C_CACHE_LINE_SIZE -#define BSP_CFG_C_CACHE_LINE_SIZE (1U) + #define BSP_CFG_C_CACHE_LINE_SIZE (1U) #endif -/* Type 1 Peripheral Security Attribution */ + /* Type 1 Peripheral Security Attribution */ -/* Peripheral Security Attribution Register (PSAR) Settings */ + /* Peripheral Security Attribution Register (PSAR) Settings */ #ifndef BSP_TZ_CFG_PSARB #define BSP_TZ_CFG_PSARB (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ @@ -146,19 +146,19 @@ extern "C" { 0xfffffffc) /* Unused */ #endif -/* Type 2 Peripheral Security Attribution */ + /* Type 2 Peripheral Security Attribution */ -/* Security attribution for Cache registers. */ + /* Security attribution for Cache registers. */ #ifndef BSP_TZ_CFG_CSAR #define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) #endif -/* Security attribution for RSTSRn registers. */ + /* Security attribution for RSTSRn registers. */ #ifndef BSP_TZ_CFG_RSTSAR #define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) #endif -/* Security attribution for registers of LVD channels. */ + /* Security attribution for registers of LVD channels. */ #ifndef BSP_TZ_CFG_LVDSAR #define BSP_TZ_CFG_LVDSAR (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ @@ -166,16 +166,16 @@ extern "C" { 0xFFFFFFFCU) #endif -/* Security attribution for LPM registers. */ + /* Security attribution for LPM registers. */ #ifndef BSP_TZ_CFG_LPMSAR #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) #endif -/* Deep Standby Interrupt Factor Security Attribution Register. */ + /* Deep Standby Interrupt Factor Security Attribution Register. */ #ifndef BSP_TZ_CFG_DPFSAR #define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) #endif -/* Security attribution for CGC registers. */ + /* Security attribution for CGC registers. */ #ifndef BSP_TZ_CFG_CGFSAR #if BSP_CFG_CLOCKS_SECURE /* Protect all CGC registers from Non-secure write access. */ @@ -186,12 +186,12 @@ extern "C" { #endif #endif -/* Security attribution for Battery Backup registers. */ + /* Security attribution for Battery Backup registers. */ #ifndef BSP_TZ_CFG_BBFSAR #define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) #endif -/* Security attribution for registers for IRQ channels. */ + /* Security attribution for registers for IRQ channels. */ #ifndef BSP_TZ_CFG_ICUSARA #define BSP_TZ_CFG_ICUSARA (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ @@ -213,12 +213,12 @@ extern "C" { 0xFFFF0000U) #endif -/* Security attribution for NMI registers. */ + /* Security attribution for NMI registers. */ #ifndef BSP_TZ_CFG_ICUSARB #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ #endif -/* Security attribution for registers for DMAC channels */ + /* Security attribution for registers for DMAC channels */ #ifndef BSP_TZ_CFG_ICUSARC #define BSP_TZ_CFG_ICUSARC (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ @@ -232,29 +232,29 @@ extern "C" { 0xFFFFFF00U) #endif -/* Security attribution registers for SELSR0. */ + /* Security attribution registers for SELSR0. */ #ifndef BSP_TZ_CFG_ICUSARD #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) #endif -/* Security attribution registers for WUPEN0. */ + /* Security attribution registers for WUPEN0. */ #ifndef BSP_TZ_CFG_ICUSARE #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) #endif -/* Security attribution registers for WUPEN1. */ + /* Security attribution registers for WUPEN1. */ #ifndef BSP_TZ_CFG_ICUSARF #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) #endif -/* Set DTCSTSAR if the Secure program uses the DTC. */ + /* Set DTCSTSAR if the Secure program uses the DTC. */ #if RA_NOT_DEFINED == RA_NOT_DEFINED -#define BSP_TZ_CFG_DTC_USED (0U) + #define BSP_TZ_CFG_DTC_USED (0U) #else #define BSP_TZ_CFG_DTC_USED (1U) #endif -/* Security attribution of FLWT and FCKMHZ registers. */ + /* Security attribution of FLWT and FCKMHZ registers. */ #ifndef BSP_TZ_CFG_FSAR /* If the CGC registers are only accessible in Secure mode, than there is no * reason for nonsecure applications to access FLWT and FCKMHZ. */ @@ -267,118 +267,123 @@ extern "C" { #endif #endif -/* Security attribution for SRAM registers. */ + /* Security attribution for SRAM registers. */ #ifndef BSP_TZ_CFG_SRAMSAR /* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access * SRAM0WTEN and therefore there is no reason to access PRCR2. */ -#define BSP_TZ_CFG_SRAMSAR (\ + #define BSP_TZ_CFG_SRAMSAR (\ 1 | \ ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ 4 | \ 0xFFFFFFF8U) #endif -/* Security attribution for Standby RAM registers. */ + /* Security attribution for Standby RAM registers. */ #ifndef BSP_TZ_CFG_STBRAMSAR -#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) + #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) #endif -/* Security attribution for the DMAC Bus Master MPU settings. */ + /* Security attribution for the DMAC Bus Master MPU settings. */ #ifndef BSP_TZ_CFG_MMPUSARA -/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ -#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) + /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ + #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) #endif -/* Security Attribution Register A for BUS Control registers. */ + /* Security Attribution Register A for BUS Control registers. */ #ifndef BSP_TZ_CFG_BUSSARA -#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) + #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) #endif -/* Security Attribution Register B for BUS Control registers. */ + /* Security Attribution Register B for BUS Control registers. */ #ifndef BSP_TZ_CFG_BUSSARB -#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) + #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) #endif -/* Enable Uninitialized Non-Secure Application Fallback. */ + /* Enable Uninitialized Non-Secure Application Fallback. */ #ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK -#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) + #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) #endif -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -/* Option Function Select Register 1 Security Attribution */ + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + + /* Option Function Select Register 1 Security Attribution */ #ifndef BSP_CFG_ROM_REG_OFS1_SEL #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U)) #else -#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) #endif #endif -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) -/* Dual Mode Select Register */ + /* Dual Mode Select Register */ #ifndef BSP_CFG_ROM_REG_DUALSEL -#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) + #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) #endif -/* Block Protection Register 0 */ + /* Block Protection Register 0 */ #ifndef BSP_CFG_ROM_REG_BPS0 -#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS0 (~( 0U)) #endif -/* Block Protection Register 1 */ + /* Block Protection Register 1 */ #ifndef BSP_CFG_ROM_REG_BPS1 -#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS1 (~( 0U)) #endif -/* Block Protection Register 2 */ + /* Block Protection Register 2 */ #ifndef BSP_CFG_ROM_REG_BPS2 -#define BSP_CFG_ROM_REG_BPS2 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS2 (~( 0U)) #endif -/* Block Protection Register 3 */ + /* Block Protection Register 3 */ #ifndef BSP_CFG_ROM_REG_BPS3 -#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) #endif -/* Permanent Block Protection Register 0 */ + /* Permanent Block Protection Register 0 */ #ifndef BSP_CFG_ROM_REG_PBPS0 -#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) #endif -/* Permanent Block Protection Register 1 */ + /* Permanent Block Protection Register 1 */ #ifndef BSP_CFG_ROM_REG_PBPS1 -#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) #endif -/* Permanent Block Protection Register 2 */ + /* Permanent Block Protection Register 2 */ #ifndef BSP_CFG_ROM_REG_PBPS2 -#define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) #endif -/* Permanent Block Protection Register 3 */ + /* Permanent Block Protection Register 3 */ #ifndef BSP_CFG_ROM_REG_PBPS3 -#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) #endif -/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL0 -#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) + #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) #endif -/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL1 -#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) + #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) #endif -/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL2 -#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) + #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) #endif -/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL3 -#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) + #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) +#endif + /* Security Attribution for Bank Select Register */ +#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL + #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU) #endif #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) #endif #ifdef __cplusplus diff --git a/hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld b/hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld new file mode 100644 index 000000000..627ffe4d9 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld @@ -0,0 +1,766 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + +/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ +/* + XIP_SECONDARY_SLOT_IMAGE = 1; +*/ + +QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); +OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); +OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); + +/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ +__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); + +ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; +ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; +DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; +DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; +RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; +RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; +RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; +RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; + +OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; + +/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. + * Bootloader images do not configure option settings because they are owned by the bootloader. + * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ +__bl_FSP_BOOTABLE_IMAGE = 1; +__bln_FSP_BOOTABLE_IMAGE = 1; +PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); + +__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; +__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; +__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; +__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; +__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); +__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; + +XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; +FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : + XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : + FLASH_IMAGE_START; +LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : + DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : + FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; + +/* Define memory regions. */ +MEMORY +{ + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be DEFINED in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * __qspi_flash_start__ + * __qspi_flash_end__ + * __qspi_flash_code_size__ + * __qspi_region_max_size__ + * __qspi_region_start_address__ + * __qspi_region_end_address__ + * __ospi_device_0_start__ + * __ospi_device_0_end__ + * __ospi_device_0_code_size__ + * __ospi_device_0_region_max_size__ + * __ospi_device_0_region_start_address__ + * __ospi_device_0_region_end_address__ + * __ospi_device_1_start__ + * __ospi_device_1_end__ + * __ospi_device_1_code_size__ + * __ospi_device_1_region_max_size__ + * __ospi_device_1_region_start_address__ + * __ospi_device_1_region_end_address__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __tz_FLASH_S = ABSOLUTE(FLASH_START); + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + + /* Some devices have a gap of code flash between the vector table and ROM Registers. + * The flash gap section allows applications to place code and data in this section. */ + *(.flash_gap*) + + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Allocate flash write-boundary-aligned + * space for sce9 wrapped public keys for mcuboot if the module is used. + */ + KEEP(*(.mcuboot_sce9_key*)) + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) + { + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; + + __exidx_start = .; + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); + + /* Initialized DTCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) + { + /* Start of DTCM Secure Trustzone region. */ + __tz_DTCM_S = ABSOLUTE(DTCM_START); + + /* Initialized DTCM data start */ + __dtcm_data_start = .; + + KEEP(*(.dtcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; + /* Uninitialized DTCM data. */ + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : + { + /* Uninitialized DTCM data start */ + __dtcm_bss_start = .; + + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); + + /* Uninitialized DTCM data end */ + __dtcm_bss_end = .; + + /* + * Start of the DTCM Non-Secure Trustzone region. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. + */ + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); + } > DTCM + + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ + . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; + + KEEP(*(.ns_buffer*)) + } > RAM + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. + * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE + * memory region between TrustZone projects. */ + __tz_ID_CODE_N = __tz_ID_CODE_S; + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); + + .option_setting_ofs : + { + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_ofs2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; + } > OPTION_SETTING_OFS = 0xFF + + .option_setting_sas : + { + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; + } > OPTION_SETTING_SAS = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_ofs3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; +} diff --git a/hw/bsp/ra/boards/ra6m5_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra6m5_ek/script/memory_regions.ld new file mode 100644 index 000000000..19864683f --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/script/memory_regions.ld @@ -0,0 +1,22 @@ + + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x80000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x2000; + OPTION_SETTING_START = 0x0100A100; + OPTION_SETTING_LENGTH = 0x100; + OPTION_SETTING_S_START = 0x0100A200; + OPTION_SETTING_S_LENGTH = 0x100; + ID_CODE_START = 0x00000000; + ID_CODE_LENGTH = 0x0; + SDRAM_START = 0x80010000; + SDRAM_LENGTH = 0x0; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x4000000; + OSPI_DEVICE_0_START = 0x68000000; + OSPI_DEVICE_0_LENGTH = 0x8000000; + OSPI_DEVICE_1_START = 0x70000000; + OSPI_DEVICE_1_LENGTH = 0x10000000; diff --git a/hw/bsp/ra/boards/ra6m5_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra6m5_ek/smart_configurator/configuration.xml new file mode 100644 index 000000000..f77a8ac63 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/smart_configurator/configuration.xml @@ -0,0 +1,651 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Simple application that blinks an LED. No RTOS included. + Renesas.RA_baremetal_blinky.5.6.0.pack + + + Board Support Package Common Files + Renesas.RA.5.6.0.pack + + + I/O Port + Renesas.RA.5.6.0.pack + + + Arm CMSIS Version 6 - Core (M) + Arm.CMSIS6.6.1.0+fsp.5.6.0.pack + + + RA6M5-EK Board Support Files + Renesas.RA_board_ra6m5_ek.5.6.0.pack + + + Board support package for R7FA6M5BH3CFC + Renesas.RA_mcu_ra6m5.5.6.0.pack + + + Board support package for RA6M5 + Renesas.RA_mcu_ra6m5.5.6.0.pack + + + Board support package for RA6M5 - FSP Data + Renesas.RA_mcu_ra6m5.5.6.0.pack + + + Board support package for RA6M5 - Events + Renesas.RA_mcu_ra6m5.5.6.0.pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml new file mode 100644 index 000000000..0a9393769 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml @@ -0,0 +1,624 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Simple application that blinks an LED. No RTOS included. + Renesas.RA_baremetal_blinky.5.6.0.pack + + + Board Support Package Common Files + Renesas.RA.5.6.0.pack + + + I/O Port + Renesas.RA.5.6.0.pack + + + Arm CMSIS Version 6 - Core (M) + Arm.CMSIS6.6.1.0+fsp.5.6.0.pack + + + RA8M1-EK Board Support Files + Renesas.RA_board_ra8m1_ek.5.6.0.pack + + + Board support package for R7FA8M1AHECBD + Renesas.RA_mcu_ra8m1.5.6.0.pack + + + Board support package for RA8M1 + Renesas.RA_mcu_ra8m1.5.6.0.pack + + + Board support package for RA8M1 - FSP Data + Renesas.RA_mcu_ra8m1.5.6.0.pack + + + Board support package for RA8M1 - Events + Renesas.RA_mcu_ra8m1.5.6.0.pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hw/bsp/ra/boards/uno_r4/board.cmake b/hw/bsp/ra/boards/uno_r4/board.cmake index 9d59bc4f7..3aa6045be 100644 --- a/hw/bsp/ra/boards/uno_r4/board.cmake +++ b/hw/bsp/ra/boards/uno_r4/board.cmake @@ -1,13 +1,9 @@ set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra4m1) - set(JLINK_DEVICE R7FA4M1AB) -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld) function(update_board TARGET) target_compile_definitions(${TARGET} PUBLIC CFG_EXAMPLE_VIDEO_READONLY ) -# target_sources(${TARGET} PRIVATE) -# target_include_directories(${BOARD_TARGET} PUBLIC) endfunction() diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h index c1d1022cc..4eef62a0e 100644 --- a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -1,35 +1,62 @@ /* generated configuration header file - do not edit */ #ifndef BSP_CFG_H_ #define BSP_CFG_H_ - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#undef RA_NOT_DEFINED -#define BSP_CFG_RTOS (0) -#if defined(_RA_BOOT_IMAGE) -#define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x800) -#define BSP_CFG_HEAP_BYTES (0x1000) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0) - -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (0) -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 - +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x800) + #define BSP_CFG_HEAP_BYTES (0x1000) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif #endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h index 336918800..3f1d02b0d 100644 --- a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -2,10 +2,10 @@ #ifndef BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_R7FA4M1AB3CNE -#define BSP_MCU_FEATURE_SET ('A') -#define BSP_ROM_SIZE_BYTES (262144) -#define BSP_RAM_SIZE_BYTES (32768) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_QFN -#define BSP_PACKAGE_PINS (48) + #define BSP_MCU_FEATURE_SET ('A') + #define BSP_ROM_SIZE_BYTES (262144) + #define BSP_RAM_SIZE_BYTES (32768) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) + #define BSP_PACKAGE_QFN + #define BSP_PACKAGE_PINS (48) #endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h index fc604eb3b..3d482b2b6 100644 --- a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -1,87 +1,84 @@ -/* generated configuration header file through renesas e2 studio */ +/* generated configuration header file - do not edit */ #ifndef BSP_MCU_FAMILY_CFG_H_ #define BSP_MCU_FAMILY_CFG_H_ - #ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "bsp_mcu_info.h" -#include "bsp_clock_cfg.h" + extern "C" { + #endif -#define BSP_MCU_GROUP_RA4M1 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 - #define BSP_HOCO_HZ (24000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (32000000) -#elif BSP_CFG_HOCO_FREQUENCY == 4 - #define BSP_HOCO_HZ (48000000) -#elif BSP_CFG_HOCO_FREQUENCY == 5 - #define BSP_HOCO_HZ (64000000) -#else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) -#define BSP_MCU_VBATT_SUPPORT (1) + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA4M1 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (24000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (32000000) + #elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (48000000) + #elif BSP_CFG_HOCO_FREQUENCY == 5 + #define BSP_HOCO_HZ (64000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) -#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) -#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) + #define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) + #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) + #define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) + #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) + #define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) + #endif + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) -/* - ID Code - Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. - WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. - */ -#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) + /* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ + #if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) #else -/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ -#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) -#endif - -#ifdef __cplusplus -} -#endif + /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ + #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) + #endif + #ifdef __cplusplus + } + #endif #endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h index 63618ec4b..559000a7a 100644 --- a/hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/uno_r4/ra_gen/bsp_clock_cfg.h @@ -4,10 +4,10 @@ #define BSP_CFG_CLOCKS_SECURE (0) #define BSP_CFG_CLOCKS_OVERRIDE (0) #define BSP_CFG_XTAL_HZ (0) /* XTAL 0Hz */ -#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL Src: Disabled */ #define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */ #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_4) /* PLL Div /4 */ -#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(12, 0) /* PLL Mul x12 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(12U,0U) /* PLL Mul x12 */ #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */ #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ @@ -15,7 +15,7 @@ #define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */ #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ #define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ -#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Src: SUBCLK */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ #define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ #define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* UCLK Src: HOCO */ #endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/script/fsp.ld b/hw/bsp/ra/boards/uno_r4/script/fsp.ld new file mode 100644 index 000000000..627ffe4d9 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/script/fsp.ld @@ -0,0 +1,766 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + +/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ +/* + XIP_SECONDARY_SLOT_IMAGE = 1; +*/ + +QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); +OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); +OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); + +/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ +__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); + +ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; +ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; +DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; +DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; +RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; +RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; +RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; +RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; + +OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; + +/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. + * Bootloader images do not configure option settings because they are owned by the bootloader. + * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ +__bl_FSP_BOOTABLE_IMAGE = 1; +__bln_FSP_BOOTABLE_IMAGE = 1; +PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); + +__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; +__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; +__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; +__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; +__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); +__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; + +XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; +FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : + XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : + FLASH_IMAGE_START; +LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : + DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : + FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; + +/* Define memory regions. */ +MEMORY +{ + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be DEFINED in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * __qspi_flash_start__ + * __qspi_flash_end__ + * __qspi_flash_code_size__ + * __qspi_region_max_size__ + * __qspi_region_start_address__ + * __qspi_region_end_address__ + * __ospi_device_0_start__ + * __ospi_device_0_end__ + * __ospi_device_0_code_size__ + * __ospi_device_0_region_max_size__ + * __ospi_device_0_region_start_address__ + * __ospi_device_0_region_end_address__ + * __ospi_device_1_start__ + * __ospi_device_1_end__ + * __ospi_device_1_code_size__ + * __ospi_device_1_region_max_size__ + * __ospi_device_1_region_start_address__ + * __ospi_device_1_region_end_address__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __tz_FLASH_S = ABSOLUTE(FLASH_START); + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + + /* Some devices have a gap of code flash between the vector table and ROM Registers. + * The flash gap section allows applications to place code and data in this section. */ + *(.flash_gap*) + + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Allocate flash write-boundary-aligned + * space for sce9 wrapped public keys for mcuboot if the module is used. + */ + KEEP(*(.mcuboot_sce9_key*)) + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) + { + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; + + __exidx_start = .; + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); + + /* Initialized DTCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) + { + /* Start of DTCM Secure Trustzone region. */ + __tz_DTCM_S = ABSOLUTE(DTCM_START); + + /* Initialized DTCM data start */ + __dtcm_data_start = .; + + KEEP(*(.dtcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; + /* Uninitialized DTCM data. */ + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : + { + /* Uninitialized DTCM data start */ + __dtcm_bss_start = .; + + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); + + /* Uninitialized DTCM data end */ + __dtcm_bss_end = .; + + /* + * Start of the DTCM Non-Secure Trustzone region. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. + */ + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); + } > DTCM + + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ + . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; + + KEEP(*(.ns_buffer*)) + } > RAM + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. + * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE + * memory region between TrustZone projects. */ + __tz_ID_CODE_N = __tz_ID_CODE_S; + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); + + .option_setting_ofs : + { + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_ofs2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; + } > OPTION_SETTING_OFS = 0xFF + + .option_setting_sas : + { + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; + } > OPTION_SETTING_SAS = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_ofs3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; +} diff --git a/hw/bsp/ra/boards/uno_r4/script/memory_regions.ld b/hw/bsp/ra/boards/uno_r4/script/memory_regions.ld new file mode 100644 index 000000000..22775395c --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/script/memory_regions.ld @@ -0,0 +1,25 @@ + + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x8000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x40000; + DATA_FLASH_START = 0x40100000; + DATA_FLASH_LENGTH = 0x2000; + OPTION_SETTING_START = 0x00000000; + OPTION_SETTING_LENGTH = 0x0; + OPTION_SETTING_S_START = 0x80000000; + OPTION_SETTING_S_LENGTH = 0x0; + ID_CODE_START = 0x01010018; + ID_CODE_LENGTH = 0x20; + SDRAM_START = 0x80010000; + SDRAM_LENGTH = 0x0; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x0; + OSPI_DEVICE_0_START = 0x80020000; + OSPI_DEVICE_0_LENGTH = 0x0; + OSPI_DEVICE_1_START = 0x80030000; + OSPI_DEVICE_1_LENGTH = 0x0; + +/* Uno R4 has bootloader */ +FLASH_IMAGE_START = 0x4000; diff --git a/hw/bsp/ra/boards/uno_r4/smart_configurator/configuration.xml b/hw/bsp/ra/boards/uno_r4/smart_configurator/configuration.xml new file mode 100644 index 000000000..49603d5bf --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/smart_configurator/configuration.xml @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Board Support Package Common Files + Renesas.RA.5.6.0.pack + + + I/O Port + Renesas.RA.5.6.0.pack + + + Arm CMSIS Version 6 - Core (M) + Arm.CMSIS6.6.1.0+fsp.5.6.0.pack + + + Custom Board Support Files + Renesas.RA_board_custom.5.6.0.pack + + + Board support package for R7FA4M1AB3CNE + Renesas.RA_mcu_ra4m1.5.6.0.pack + + + Board support package for RA4M1 + Renesas.RA_mcu_ra4m1.5.6.0.pack + + + Board support package for RA4M1 - FSP Data + Renesas.RA_mcu_ra4m1.5.6.0.pack + + + Board support package for RA4M1 - Events + Renesas.RA_mcu_ra4m1.5.6.0.pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hw/bsp/ra/boards/uno_r4/uno_r4.ld b/hw/bsp/ra/boards/uno_r4/uno_r4.ld deleted file mode 100644 index 45f11dfb1..000000000 --- a/hw/bsp/ra/boards/uno_r4/uno_r4.ld +++ /dev/null @@ -1,25 +0,0 @@ -RAM_START = 0x20000000; -RAM_LENGTH = 0x8000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x40000; -DATA_FLASH_START = 0x40100000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x00000000; -OPTION_SETTING_LENGTH = 0x0; -OPTION_SETTING_S_START = 0x80000000; -OPTION_SETTING_S_LENGTH = 0x0; -ID_CODE_START = 0x01010018; -ID_CODE_LENGTH = 0x20; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x0; -OSPI_DEVICE_0_START = 0x80020000; -OSPI_DEVICE_0_LENGTH = 0x0; -OSPI_DEVICE_1_START = 0x80030000; -OSPI_DEVICE_1_LENGTH = 0x0; - -/* Uno R4 has bootloader */ -FLASH_IMAGE_START = 0x4000; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 3b35d2e71..00907c598 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -4,7 +4,7 @@ if (NOT BOARD) message(FATAL_ERROR "BOARD not specified") endif () -set(CMSIS_DIR ${TOP}/lib/CMSIS_5) +set(CMSIS_DIR ${TOP}/lib/CMSIS_6) set(FSP_RA ${TOP}/hw/mcu/renesas/fsp/ra/fsp) # include board specific @@ -59,18 +59,19 @@ function(add_board_target BOARD_TARGET) update_board(${BOARD_TARGET}) if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID}) - set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc/${MCU_VARIANT}.ld) + set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/script/fsp.ld) + #set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc/${MCU_VARIANT}.ld) endif () if (CMAKE_C_COMPILER_ID STREQUAL "GNU") target_link_options(${BOARD_TARGET} PUBLIC # linker file "LINKER:--script=${LD_FILE_GNU}" - -L${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc + #-L${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc + -L${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/script + -Wl,--defsym=end=__bss_end__ -nostartfiles - # nanolib - --specs=nano.specs - --specs=nosys.specs + --specs=nano.specs --specs=nosys.specs ) elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") target_link_options(${BOARD_TARGET} PUBLIC diff --git a/tools/get_deps.py b/tools/get_deps.py index 58709414c..c8459c1f1 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -62,7 +62,7 @@ deps_optional = { 'fe9133fc513b82cc3dc62c67cb51f2339cf29ef7', 'rp2040'], 'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git', - 'd52e5a6a59b7c638da860c2bb309b6e78e752ff8', + 'edcc97d684b6f716728a60d7a6fea049d9870bd6', 'ra'], 'hw/mcu/renesas/rx': ['https://github.com/kkitayam/rx_device.git', '706b4e0cf485605c32351e2f90f5698267996023', @@ -194,13 +194,16 @@ deps_optional = { '77c4095087e5ed2c548ec9058e655d0b8757663b', 'ch32f20x'], 'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git', - '20285262657d1b482d132d20d755c8c330d55c1f', - 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x ' + '2b7495b8535bdcb306dac29b9ded4cfb679d7e5c', + 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf saml2x ' 'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 ' 'stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 ' 'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb ' 'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg ' 'tm4c '], + 'lib/CMSIS_6': ['https://github.com/ARM-software/CMSIS_6.git', + 'b0bbb0423b278ca632cfe1474eb227961d835fd2', + 'ra'], 'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git', 'e73e04ca63495672d955f9268e003cffe168fcd8', 'lpc55'], -- cgit v1.3.1 From 8f2b1bc7b9705493e028b9212728ebcc2aaa8abb Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 12 Dec 2024 15:37:07 +0700 Subject: used pin generated by rasc --- hw/bsp/ra/board_cfg.h | 52 +-- hw/bsp/ra/boards/ra6m1_ek/board.h | 12 +- .../boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 120 +++--- .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 12 +- .../ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 146 ++++---- .../ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h | 17 + hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.c | 11 + hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.h | 20 + hw/bsp/ra/boards/ra6m1_ek/ra_gen/pin_data.c | 115 ++++++ .../ra6m1_ek/smart_configurator/configuration.xml | 163 ++++---- hw/bsp/ra/boards/ra6m5_ek/board.h | 26 -- .../boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 115 +++--- .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 12 +- .../ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h | 99 +++++ hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.c | 11 + hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.h | 20 + hw/bsp/ra/boards/ra6m5_ek/ra_gen/pin_data.c | 411 +++++++++++++++++++++ .../ra6m5_ek/smart_configurator/configuration.xml | 63 ++-- hw/bsp/ra/boards/uno_r4/board.h | 16 +- .../boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h | 17 + hw/bsp/ra/boards/uno_r4/ra_gen/common_data.c | 11 + hw/bsp/ra/boards/uno_r4/ra_gen/common_data.h | 20 + hw/bsp/ra/boards/uno_r4/ra_gen/pin_data.c | 75 ++++ .../uno_r4/smart_configurator/configuration.xml | 35 +- hw/bsp/ra/family.c | 25 +- hw/bsp/ra/family.cmake | 4 +- hw/bsp/ra/vector_data.h | 4 + 27 files changed, 1189 insertions(+), 443 deletions(-) create mode 100644 hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h create mode 100644 hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.c create mode 100644 hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.h create mode 100644 hw/bsp/ra/boards/ra6m1_ek/ra_gen/pin_data.c create mode 100644 hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h create mode 100644 hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.c create mode 100644 hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.h create mode 100644 hw/bsp/ra/boards/ra6m5_ek/ra_gen/pin_data.c create mode 100644 hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h create mode 100644 hw/bsp/ra/boards/uno_r4/ra_gen/common_data.c create mode 100644 hw/bsp/ra/boards/uno_r4/ra_gen/common_data.h create mode 100644 hw/bsp/ra/boards/uno_r4/ra_gen/pin_data.c (limited to 'hw') diff --git a/hw/bsp/ra/board_cfg.h b/hw/bsp/ra/board_cfg.h index baed46b5f..825f8cd32 100644 --- a/hw/bsp/ra/board_cfg.h +++ b/hw/bsp/ra/board_cfg.h @@ -1,45 +1,13 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2023 Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - */ - -#ifndef _BOARD_CFG_H -#define _BOARD_CFG_H - +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ #ifdef __cplusplus -extern "C" { -#endif - -#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8) - #define BOARD_HAS_USB_HIGHSPEED -#endif + extern "C" { + #endif -// for SystemInit() -void bsp_init(void * p_args); - - -#ifdef __cplusplus -} -#endif + void bsp_init(void * p_args); -#endif + #ifdef __cplusplus + } + #endif +#endif /* BOARD_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.h b/hw/bsp/ra/boards/ra6m1_ek/board.h index f73a08fc0..ba663d040 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/board.h +++ b/hw/bsp/ra/boards/ra6m1_ek/board.h @@ -31,19 +31,9 @@ extern "C" { #endif -#define LED1 BSP_IO_PORT_01_PIN_12 -#define LED_STATE_ON 1 - -#define SW1 BSP_IO_PORT_04_PIN_15 +#define LED_STATE_ON 1 #define BUTTON_STATE_ACTIVE 0 -static const ioport_pin_cfg_t board_pin_cfg[] = { - { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT }, - { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT }, - // USB FS - { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS }, -}; - #ifdef __cplusplus } #endif diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h index 772e5e5b1..90afbdef3 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -1,68 +1,62 @@ /* generated configuration header file - do not edit */ #ifndef BSP_CFG_H_ #define BSP_CFG_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#define RA_NOT_DEFINED 0 -#ifndef BSP_CFG_RTOS -#if (RA_NOT_DEFINED) != (2) -#define BSP_CFG_RTOS (2) -#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (1) -#else - #define BSP_CFG_RTOS (0) -#endif -#endif - -#ifndef BSP_CFG_RTC_USED -#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) -#endif - -#undef RA_NOT_DEFINED -#if defined(_RA_BOOT_IMAGE) - #define BSP_CFG_BOOT_IMAGE (1) -#endif - -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x1000) -#define BSP_CFG_HEAP_BYTES (0x1000) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) -#endif - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#endif - #ifdef __cplusplus -} -#endif - + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x1000) + #define BSP_CFG_HEAP_BYTES (0x1000) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif #endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h index 40bb3a3bf..5e7841442 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -2,10 +2,10 @@ #ifndef BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_R7FA6M1AD3CFP -#define BSP_MCU_FEATURE_SET ('A') -#define BSP_ROM_SIZE_BYTES (524288) -#define BSP_RAM_SIZE_BYTES (262144) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (100) + #define BSP_MCU_FEATURE_SET ('A') + #define BSP_ROM_SIZE_BYTES (524288) + #define BSP_RAM_SIZE_BYTES (262144) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) + #define BSP_PACKAGE_LQFP + #define BSP_PACKAGE_PINS (100) #endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h index 5fedd754f..16349b5ff 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -2,83 +2,83 @@ #ifndef BSP_MCU_FAMILY_CFG_H_ #define BSP_MCU_FAMILY_CFG_H_ #ifdef __cplusplus -extern "C" { -#endif + extern "C" { + #endif -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h" -#include "bsp_clock_cfg.h" + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA6M1 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) + #elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif -#define BSP_MCU_GROUP_RA6M1 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (16000000) -#elif BSP_CFG_HOCO_FREQUENCY == 1 - #define BSP_HOCO_HZ (18000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (20000000) -#else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif + #define BSP_CFG_FLL_ENABLE (0) -#define BSP_CFG_FLL_ENABLE (0) + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC) + #define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF) + #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC) + #define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) + #endif + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) -#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF) -#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + /* + ID Code + Note: To lock and disable the debug interface define BSP_ID_CODE_LOCKED in compiler settings. + WARNING: This will disable debug access to the part. However, ALeRASE command will be accepted, which will clear (reset) the ID code. After clearing ID code, debug access will be enabled. + */ + #if defined(BSP_ID_CODE_LOCKED) + #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) + #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) + #else + /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ + #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) + #endif -/* - ID Code - Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. - WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. - */ -#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) - #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) - #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) -#else - /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ - #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) - #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) - #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) - #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) -#endif - -#ifdef __cplusplus -} -#endif + #ifdef __cplusplus + } + #endif #endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000..8ba9aafba --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,17 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define LED1 (BSP_IO_PORT_01_PIN_12) +#define SW1 (BSP_IO_PORT_04_PIN_15) +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M1-EK.pincfg */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.c new file mode 100644 index 000000000..50036c0ad --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.c @@ -0,0 +1,11 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.h new file mode 100644 index 000000000..6a08cbee0 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/pin_data.c new file mode 100644 index 000000000..80774b0a5 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m1_ek/ra_gen/pin_data.c @@ -0,0 +1,115 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_00_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_01_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_01_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_01_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_01_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_02_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_02_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU) + }, + { + .pin = BSP_IO_PORT_02_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU) + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_04_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/hw/bsp/ra/boards/ra6m1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra6m1_ek/smart_configurator/configuration.xml index 2f373930c..4c5d77ed0 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/smart_configurator/configuration.xml +++ b/hw/bsp/ra/boards/ra6m1_ek/smart_configurator/configuration.xml @@ -1,7 +1,6 @@ - + - @@ -87,8 +87,8 @@ - - + + @@ -175,125 +175,96 @@ Renesas.RA_mcu_ra6m1.5.6.0.pack + - + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + - - - - - + + + + + + - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + - - - - - - - - - - - - - - - - - + - - + + + - + + - - + - - + - + diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.h b/hw/bsp/ra/boards/ra6m5_ek/board.h index 779f71810..33dda99b4 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.h +++ b/hw/bsp/ra/boards/ra6m5_ek/board.h @@ -31,35 +31,9 @@ extern "C" { #endif -#define LED1 BSP_IO_PORT_00_PIN_08 #define LED_STATE_ON 1 - -#define SW1 BSP_IO_PORT_00_PIN_05 #define BUTTON_STATE_ACTIVE 0 -static const ioport_pin_cfg_t board_pin_cfg[] = { - { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW }, - { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT }, - - // USB FS - { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH }, - { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, - { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, - - // USB HS - { .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS }, - { .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, - { .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, - - // ETM Trace - #ifdef TRACE_ETM - { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - #endif -}; #ifdef __cplusplus } diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h index 33d381850..90afbdef3 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -2,62 +2,61 @@ #ifndef BSP_CFG_H_ #define BSP_CFG_H_ #ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#define RA_NOT_DEFINED 0 -#ifndef BSP_CFG_RTOS -#if (RA_NOT_DEFINED) != (2) -#define BSP_CFG_RTOS (2) -#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (1) -#else - #define BSP_CFG_RTOS (0) -#endif -#endif -#ifndef BSP_CFG_RTC_USED -#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) -#endif -#undef RA_NOT_DEFINED -#if defined(_RA_BOOT_IMAGE) - #define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x1000) -#define BSP_CFG_HEAP_BYTES (0x1000) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) -#endif - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#endif - -#ifdef __cplusplus -} -#endif + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x1000) + #define BSP_CFG_HEAP_BYTES (0x1000) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif #endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h index 6845183db..e532478f8 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -2,10 +2,10 @@ #ifndef BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_R7FA6M5BH3CFC -#define BSP_MCU_FEATURE_SET ('B') -#define BSP_ROM_SIZE_BYTES (2097152) -#define BSP_RAM_SIZE_BYTES (524288) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (176) + #define BSP_MCU_FEATURE_SET ('B') + #define BSP_ROM_SIZE_BYTES (2097152) + #define BSP_RAM_SIZE_BYTES (524288) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) + #define BSP_PACKAGE_LQFP + #define BSP_PACKAGE_PINS (176) #endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000..d2eec08ae --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,99 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define MIKROBUS_AN_ARDUINO_A0 (BSP_IO_PORT_00_PIN_00) +#define ARDUINO_A1 (BSP_IO_PORT_00_PIN_01) +#define ARDUINO_A2 (BSP_IO_PORT_00_PIN_02) +#define ARDUINO_A3 (BSP_IO_PORT_00_PIN_03) +#define SW2 (BSP_IO_PORT_00_PIN_04) +#define SW1 (BSP_IO_PORT_00_PIN_05) +#define LED1 (BSP_IO_PORT_00_PIN_06) +#define LED2 (BSP_IO_PORT_00_PIN_07) +#define LED3 (BSP_IO_PORT_00_PIN_08) +#define ARDUINO_A4 (BSP_IO_PORT_00_PIN_14) +#define ARDUINO_A5 (BSP_IO_PORT_00_PIN_15) +#define OSPI_CLK (BSP_IO_PORT_01_PIN_00) +#define OSPI_SIO7 (BSP_IO_PORT_01_PIN_01) +#define OSPI_SIO1 (BSP_IO_PORT_01_PIN_02) +#define OSPI_SIO6 (BSP_IO_PORT_01_PIN_03) +#define OSPI_DQS (BSP_IO_PORT_01_PIN_04) +#define OSPI_SIO5 (BSP_IO_PORT_01_PIN_05) +#define OSPI_SIO0 (BSP_IO_PORT_01_PIN_06) +#define OSPI_SIO3 (BSP_IO_PORT_01_PIN_07) +#define MIKROBUS_PWM_ARDUINO_D3_PWM (BSP_IO_PORT_01_PIN_11) +#define ARDUINO_D4 (BSP_IO_PORT_01_PIN_12) +#define ARDUINO_D5 (BSP_IO_PORT_01_PIN_13) +#define ARDUINO_D6 (BSP_IO_PORT_01_PIN_14) +#define ARDUINO_D9 (BSP_IO_PORT_01_PIN_15) +#define MIKROBUS_MISO_ARDUINO_MISO_PMOD1_MISO (BSP_IO_PORT_02_PIN_02) +#define MIKROBUS_MOSI_ARDUINO_MOSI_PMOD1_MOSI (BSP_IO_PORT_02_PIN_03) +#define MIKROBUS_SCK_ARDUINO_SCK_PMOD1_SCK (BSP_IO_PORT_02_PIN_04) +#define MIKROBUS_SS_ARDUINO_SS (BSP_IO_PORT_02_PIN_05) +#define PMOD1_SS (BSP_IO_PORT_02_PIN_06) +#define ARDUINO_D8 (BSP_IO_PORT_02_PIN_07) +#define PMOD1_SS2 (BSP_IO_PORT_03_PIN_01) +#define PMOD1_SS3 (BSP_IO_PORT_03_PIN_02) +#define MIKROBUS_RESET_ARDUINO_RESET (BSP_IO_PORT_03_PIN_03) +#define QSPI_CLK (BSP_IO_PORT_03_PIN_05) +#define QSPI_CS (BSP_IO_PORT_03_PIN_06) +#define QSPI_IO0 (BSP_IO_PORT_03_PIN_07) +#define QSPI_IO1 (BSP_IO_PORT_03_PIN_08) +#define QSPI_IO2 (BSP_IO_PORT_03_PIN_09) +#define QSPI_IO3 (BSP_IO_PORT_03_PIN_10) +#define PMOD1_RST (BSP_IO_PORT_03_PIN_11) +#define PMOD2_INT (BSP_IO_PORT_04_PIN_00) +#define ETH_MDC (BSP_IO_PORT_04_PIN_01) +#define ETH_MDIO (BSP_IO_PORT_04_PIN_02) +#define ETH_RST (BSP_IO_PORT_04_PIN_03) +#define PMOD2_RST (BSP_IO_PORT_04_PIN_04) +#define ETH_TXEN (BSP_IO_PORT_04_PIN_05) +#define ETH_TXD1 (BSP_IO_PORT_04_PIN_06) +#define USBFS_VBUS (BSP_IO_PORT_04_PIN_07) +#define PMOD2_SS2 (BSP_IO_PORT_04_PIN_08) +#define MIKROBUS_INT_ARDUINO_INT0 (BSP_IO_PORT_04_PIN_09) +#define PMOD2_MISO (BSP_IO_PORT_04_PIN_10) +#define PMOD2_MOSI (BSP_IO_PORT_04_PIN_11) +#define PMOD2_SCK (BSP_IO_PORT_04_PIN_12) +#define PMOS2_SS (BSP_IO_PORT_04_PIN_13) +#define GROVE1_SDA_QWIIC_SDA (BSP_IO_PORT_04_PIN_14) +#define GROVE1_SCL_QWIIC_SCL (BSP_IO_PORT_04_PIN_15) +#define USBFS_VBUS_EN (BSP_IO_PORT_05_PIN_00) +#define USBFS_OVERCURA (BSP_IO_PORT_05_PIN_01) +#define GROVE2_SCL (BSP_IO_PORT_05_PIN_05) +#define GROVE2_SDA (BSP_IO_PORT_05_PIN_06) +#define MIKROBUS_SDA_ARDUINO_SDA (BSP_IO_PORT_05_PIN_11) +#define MIKROBUS_SCL_ARDUINO_SCL (BSP_IO_PORT_05_PIN_12) +#define OSPI_SIO4 (BSP_IO_PORT_06_PIN_00) +#define OSPI_SIO2 (BSP_IO_PORT_06_PIN_01) +#define OSPI_CS1 (BSP_IO_PORT_06_PIN_02) +#define ARDUINO_D7 (BSP_IO_PORT_06_PIN_08) +#define CAN_TXD (BSP_IO_PORT_06_PIN_09) +#define CAN_RDX (BSP_IO_PORT_06_PIN_10) +#define CAN_STBY (BSP_IO_PORT_06_PIN_11) +#define MIKROBUS_TX_ARDUINO_TX (BSP_IO_PORT_06_PIN_13) +#define MIKROBUS_RX_ARDUINO_RX (BSP_IO_PORT_06_PIN_14) +#define OSPI_RST (BSP_IO_PORT_06_PIN_15) +#define ETH_TXD0 (BSP_IO_PORT_07_PIN_00) +#define ETH_50REF (BSP_IO_PORT_07_PIN_01) +#define ETH_RXD0 (BSP_IO_PORT_07_PIN_02) +#define ETH_RXD1 (BSP_IO_PORT_07_PIN_03) +#define ETH_RXERR (BSP_IO_PORT_07_PIN_04) +#define ETH_CRSDV (BSP_IO_PORT_07_PIN_05) +#define ETH_INT (BSP_IO_PORT_07_PIN_06) +#define USBHS_OVERCURA (BSP_IO_PORT_07_PIN_07) +#define PMOD2_SS3 (BSP_IO_PORT_07_PIN_08) +#define PMOD1_INT (BSP_IO_PORT_09_PIN_05) +#define USBHS_VBUS_EN (BSP_IO_PORT_11_PIN_00) +#define USBHS_VBUS (BSP_IO_PORT_11_PIN_01) +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M5 EK */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.c new file mode 100644 index 000000000..50036c0ad --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.c @@ -0,0 +1,11 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.h new file mode 100644 index 000000000..6a08cbee0 --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/pin_data.c new file mode 100644 index 000000000..6b814d74a --- /dev/null +++ b/hw/bsp/ra/boards/ra6m5_ek/ra_gen/pin_data.c @@ -0,0 +1,411 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_00_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_00_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_00_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_00_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_00_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_00_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_01_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_01_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_GPT1) + }, + { + .pin = BSP_IO_PORT_01_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_13, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_02_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_02_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_02_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_02_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_02_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_02_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_03_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_03_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_04_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_04_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_04_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_HIGH) + }, + { + .pin = BSP_IO_PORT_04_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_04_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_04_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_04_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_13, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) + }, + { + .pin = BSP_IO_PORT_04_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) + }, + { + .pin = BSP_IO_PORT_05_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_05_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_05_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_05_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_05_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) + }, + { + .pin = BSP_IO_PORT_05_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) + }, + { + .pin = BSP_IO_PORT_06_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_06_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_06_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_06_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_06_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CAN) + }, + { + .pin = BSP_IO_PORT_06_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CAN) + }, + { + .pin = BSP_IO_PORT_06_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_06_PIN_13, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_06_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_06_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_HIGH) + }, + { + .pin = BSP_IO_PORT_07_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_07_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_07_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_07_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_07_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_07_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_ETHER_RMII) + }, + { + .pin = BSP_IO_PORT_07_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_07_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS) + }, + { + .pin = BSP_IO_PORT_07_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_09_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_11_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS) + }, + { + .pin = BSP_IO_PORT_11_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/hw/bsp/ra/boards/ra6m5_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra6m5_ek/smart_configurator/configuration.xml index f77a8ac63..4544d0f2a 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/smart_configurator/configuration.xml +++ b/hw/bsp/ra/boards/ra6m5_ek/smart_configurator/configuration.xml @@ -1,7 +1,6 @@ - + - @@ -63,12 +63,12 @@ - - - - - - + + + + + + @@ -93,8 +93,8 @@ - - + + @@ -198,15 +198,23 @@ Renesas.RA_mcu_ra6m5.5.6.0.pack + - + + + + + + + + @@ -427,10 +435,20 @@ + + + + + + + + + + @@ -540,25 +558,20 @@ - - - - - @@ -629,6 +642,12 @@ + + + + + + @@ -638,14 +657,14 @@ - + - - + - + + - + diff --git a/hw/bsp/ra/boards/uno_r4/board.h b/hw/bsp/ra/boards/uno_r4/board.h index 72abda27f..2c262bb9b 100644 --- a/hw/bsp/ra/boards/uno_r4/board.h +++ b/hw/bsp/ra/boards/uno_r4/board.h @@ -31,20 +31,8 @@ extern "C" { #endif -#define LED1 BSP_IO_PORT_01_PIN_11 // D13 -#define LED_STATE_ON 1 - -#define SW1 BSP_IO_PORT_01_PIN_10 // D12 -#define BUTTON_STATE_ACTIVE 0 - -static const ioport_pin_cfg_t board_pin_cfg[] = { - {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT}, - {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT}, - // USB FS D+, D-, VBus - {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, - {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, - {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, -}; +#define LED_STATE_ON 1 +#define BUTTON_STATE_ACTIVE 0 #ifdef __cplusplus } diff --git a/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000..5440b293b --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,17 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define SW1 (BSP_IO_PORT_01_PIN_10) /* active low */ +#define LED1 (BSP_IO_PORT_01_PIN_11) /* active high */ +extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA4M1AB3CNE.pincfg */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.c b/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.c new file mode 100644 index 000000000..50036c0ad --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.c @@ -0,0 +1,11 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.h b/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.h new file mode 100644 index 000000000..6a08cbee0 --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/hw/bsp/ra/boards/uno_r4/ra_gen/pin_data.c b/hw/bsp/ra/boards/uno_r4/ra_gen/pin_data.c new file mode 100644 index 000000000..58262de8b --- /dev/null +++ b/hw/bsp/ra/boards/uno_r4/ra_gen/pin_data.c @@ -0,0 +1,75 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_01_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_01_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_09_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_09_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/hw/bsp/ra/boards/uno_r4/smart_configurator/configuration.xml b/hw/bsp/ra/boards/uno_r4/smart_configurator/configuration.xml index 49603d5bf..b716c8ec9 100644 --- a/hw/bsp/ra/boards/uno_r4/smart_configurator/configuration.xml +++ b/hw/bsp/ra/boards/uno_r4/smart_configurator/configuration.xml @@ -186,20 +186,33 @@ + + + + - - - - - - + + + + - - - - - + + + + + + + + + + + + + + + + diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index 87f7b4a22..c6575e88d 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -30,13 +30,12 @@ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstrict-prototypes" #pragma GCC diagnostic ignored "-Wundef" - -// extra push due to https://github.com/renesas/fsp/pull/278 -#pragma GCC diagnostic push #endif -#include "bsp_api.h" -#include "r_ioport.h" +//#include "bsp_api.h" +//#include "r_ioport.h" +#include "common_data.h" + #include "r_ioport_api.h" #include "renesas.h" @@ -50,11 +49,11 @@ /* Key code for writing PRCR register. */ #define BSP_PRV_PRCR_KEY (0xA500U) -static const ioport_cfg_t family_pin_cfg = { - .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t), - .p_pin_cfg_data = board_pin_cfg, -}; -static ioport_instance_ctrl_t port_ctrl; +// static const ioport_cfg_t family_pin_cfg = { +// .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t), +// .p_pin_cfg_data = board_pin_cfg, +// }; +// static ioport_instance_ctrl_t port_ctrl; //--------------------------------------------------------------------+ // Vector Data @@ -103,7 +102,7 @@ void board_init(void) { __enable_irq(); /* Configure pins. */ - R_IOPORT_Open(&port_ctrl, &family_pin_cfg); + R_IOPORT_Open(&IOPORT_CFG_CTRL, &IOPORT_CFG_NAME); #ifdef TRACE_ETM // TRCKCR is protected by PRCR bit0 register @@ -138,12 +137,12 @@ void board_init_after_tusb(void) { } void board_led_write(bool state) { - R_IOPORT_PinWrite(&port_ctrl, LED1, state ? LED_STATE_ON : !LED_STATE_ON); + R_IOPORT_PinWrite(&IOPORT_CFG_CTRL, LED1, state ? LED_STATE_ON : !LED_STATE_ON); } uint32_t board_button_read(void) { bsp_io_level_t lvl = !BUTTON_STATE_ACTIVE; - R_IOPORT_PinRead(&port_ctrl, SW1, &lvl); + R_IOPORT_PinRead(&IOPORT_CFG_CTRL, SW1, &lvl); return lvl == BUTTON_STATE_ACTIVE; } diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 00907c598..56c0487c1 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -36,6 +36,8 @@ function(add_board_target BOARD_TARGET) ${FSP_RA}/src/bsp/mcu/all/bsp_sbrk.c ${FSP_RA}/src/bsp/mcu/all/bsp_security.c ${FSP_RA}/src/r_ioport/r_ioport.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen/pin_data.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen/common_data.c ) target_compile_options(${BOARD_TARGET} PUBLIC @@ -60,14 +62,12 @@ function(add_board_target BOARD_TARGET) if (NOT DEFINED LD_FILE_${CMAKE_C_COMPILER_ID}) set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/script/fsp.ld) - #set(LD_FILE_GNU ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc/${MCU_VARIANT}.ld) endif () if (CMAKE_C_COMPILER_ID STREQUAL "GNU") target_link_options(${BOARD_TARGET} PUBLIC # linker file "LINKER:--script=${LD_FILE_GNU}" - #-L${CMAKE_CURRENT_FUNCTION_LIST_DIR}/linker/gcc -L${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/script -Wl,--defsym=end=__bss_end__ -nostartfiles diff --git a/hw/bsp/ra/vector_data.h b/hw/bsp/ra/vector_data.h index 2b3b7d837..a85d064bd 100644 --- a/hw/bsp/ra/vector_data.h +++ b/hw/bsp/ra/vector_data.h @@ -6,6 +6,10 @@ extern "C" { #endif +#if defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) || (BSP_CFG_MCU_PART_SERIES == 8) +#define BOARD_HAS_USB_HIGHSPEED +#endif + /* ISR prototypes */ void usbfs_interrupt_handler(void); void usbfs_resume_handler(void); -- cgit v1.3.1 From f294400a11d0aa2b878a19133d9e17b405941d9d Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 12 Dec 2024 16:21:47 +0700 Subject: rasc for ra4m3 ek --- .../boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 115 ++-- .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 12 +- .../ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 230 ++++--- .../ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h | 67 ++ hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h | 8 +- hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.c | 11 + hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.h | 20 + hw/bsp/ra/boards/ra4m3_ek/ra_gen/pin_data.c | 263 +++++++ hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld | 766 +++++++++++++++++++++ hw/bsp/ra/boards/ra4m3_ek/script/memory_regions.ld | 22 + .../ra4m3_ek/smart_configurator/configuration.xml | 432 ++++++++++++ 11 files changed, 1764 insertions(+), 182 deletions(-) create mode 100644 hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.c create mode 100644 hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.h create mode 100644 hw/bsp/ra/boards/ra4m3_ek/ra_gen/pin_data.c create mode 100644 hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld create mode 100644 hw/bsp/ra/boards/ra4m3_ek/script/memory_regions.ld create mode 100644 hw/bsp/ra/boards/ra4m3_ek/smart_configurator/configuration.xml (limited to 'hw') diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h index 862ec25b7..96087fa0d 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -2,62 +2,61 @@ #ifndef BSP_CFG_H_ #define BSP_CFG_H_ #ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#define RA_NOT_DEFINED 0 -#ifndef BSP_CFG_RTOS -#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) -#define BSP_CFG_RTOS (2) -#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) -#define BSP_CFG_RTOS (1) -#else -#define BSP_CFG_RTOS (0) -#endif -#endif -#ifndef BSP_CFG_RTC_USED -#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) -#endif -#undef RA_NOT_DEFINED -#if defined(_RA_BOOT_IMAGE) -#define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x800) -#define BSP_CFG_HEAP_BYTES (0x800) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) -#endif - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#endif - -#ifdef __cplusplus -} -#endif + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x800) + #define BSP_CFG_HEAP_BYTES (0x800) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif #endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h index 1a0bc02e2..1aaa4be0a 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -2,10 +2,10 @@ #ifndef BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_R7FA4M3AF3CFB -#define BSP_MCU_FEATURE_SET ('A') -#define BSP_ROM_SIZE_BYTES (1048576) -#define BSP_RAM_SIZE_BYTES (131072) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (144) + #define BSP_MCU_FEATURE_SET ('A') + #define BSP_ROM_SIZE_BYTES (1048576) + #define BSP_RAM_SIZE_BYTES (131072) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) + #define BSP_PACKAGE_LQFP + #define BSP_PACKAGE_PINS (144) #endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h index 26e184a94..cb9429057 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -5,17 +5,17 @@ extern "C" { #endif -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "../../../ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h" -#include "bsp_clock_cfg.h" -#define BSP_MCU_GROUP_RA4M3 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (16000000) -#elif BSP_CFG_HOCO_FREQUENCY == 1 + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra4m3/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA4M3 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) + #elif BSP_CFG_HOCO_FREQUENCY == 1 #define BSP_HOCO_HZ (18000000) #elif BSP_CFG_HOCO_FREQUENCY == 2 #define BSP_HOCO_HZ (20000000) @@ -23,61 +23,62 @@ extern "C" { #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" #endif -#define BSP_CFG_FLL_ENABLE (0) + #define BSP_CFG_FLL_ENABLE (0) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) -#if defined(_RA_TZ_SECURE) + #if defined(_RA_TZ_SECURE) #define BSP_TZ_SECURE_BUILD (1) #define BSP_TZ_NONSECURE_BUILD (0) #elif defined(_RA_TZ_NONSECURE) #define BSP_TZ_SECURE_BUILD (0) #define BSP_TZ_NONSECURE_BUILD (1) #else -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (0) -#endif - -/* TrustZone Settings */ -#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) -#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) -#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (0) + #endif -/* CMSIS TrustZone Settings */ -#define SCB_CSR_AIRCR_INIT (1) -#define SCB_AIRCR_BFHFNMINS_VAL (0) -#define SCB_AIRCR_SYSRESETREQS_VAL (1) -#define SCB_AIRCR_PRIS_VAL (0) -#define TZ_FPU_NS_USAGE (1) + /* TrustZone Settings */ + #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) + #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) + #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + + /* CMSIS TrustZone Settings */ + #define SCB_CSR_AIRCR_INIT (1) + #define SCB_AIRCR_BFHFNMINS_VAL (0) + #define SCB_AIRCR_SYSRESETREQS_VAL (1) + #define SCB_AIRCR_PRIS_VAL (0) + #define TZ_FPU_NS_USAGE (1) #ifndef SCB_NSACR_CP10_11_VAL -#define SCB_NSACR_CP10_11_VAL (3U) + #define SCB_NSACR_CP10_11_VAL (3U) #endif #ifndef FPU_FPCCR_TS_VAL -#define FPU_FPCCR_TS_VAL (1U) + #define FPU_FPCCR_TS_VAL (1U) #endif -#define FPU_FPCCR_CLRONRETS_VAL (1) + #define FPU_FPCCR_CLRONRETS_VAL (1) #ifndef FPU_FPCCR_CLRONRET_VAL -#define FPU_FPCCR_CLRONRET_VAL (1) + #define FPU_FPCCR_CLRONRET_VAL (1) #endif -/* The C-Cache line size that is configured during startup. */ + /* The C-Cache line size that is configured during startup. */ #ifndef BSP_CFG_C_CACHE_LINE_SIZE -#define BSP_CFG_C_CACHE_LINE_SIZE (1U) + #define BSP_CFG_C_CACHE_LINE_SIZE (1U) #endif -/* Type 1 Peripheral Security Attribution */ + /* Type 1 Peripheral Security Attribution */ -/* Peripheral Security Attribution Register (PSAR) Settings */ + /* Peripheral Security Attribution Register (PSAR) Settings */ #ifndef BSP_TZ_CFG_PSARB #define BSP_TZ_CFG_PSARB (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ @@ -114,7 +115,7 @@ extern "C" { (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC1 */ | \ - (((1 > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ 0xffae07f0) /* Unused */ @@ -129,13 +130,13 @@ extern "C" { (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ - (((1 > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ - (((1 > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ - (((1 > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ - (((1 > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */ | \ 0x3f3ff8) /* Unused */ #endif #ifndef BSP_TZ_CFG_MSSAR @@ -145,19 +146,19 @@ extern "C" { 0xfffffffc) /* Unused */ #endif -/* Type 2 Peripheral Security Attribution */ + /* Type 2 Peripheral Security Attribution */ -/* Security attribution for Cache registers. */ + /* Security attribution for Cache registers. */ #ifndef BSP_TZ_CFG_CSAR #define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) #endif -/* Security attribution for RSTSRn registers. */ + /* Security attribution for RSTSRn registers. */ #ifndef BSP_TZ_CFG_RSTSAR #define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) #endif -/* Security attribution for registers of LVD channels. */ + /* Security attribution for registers of LVD channels. */ #ifndef BSP_TZ_CFG_LVDSAR #define BSP_TZ_CFG_LVDSAR (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ @@ -165,16 +166,16 @@ extern "C" { 0xFFFFFFFCU) #endif -/* Security attribution for LPM registers. */ + /* Security attribution for LPM registers. */ #ifndef BSP_TZ_CFG_LPMSAR #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) #endif -/* Deep Standby Interrupt Factor Security Attribution Register. */ + /* Deep Standby Interrupt Factor Security Attribution Register. */ #ifndef BSP_TZ_CFG_DPFSAR #define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) #endif -/* Security attribution for CGC registers. */ + /* Security attribution for CGC registers. */ #ifndef BSP_TZ_CFG_CGFSAR #if BSP_CFG_CLOCKS_SECURE /* Protect all CGC registers from Non-secure write access. */ @@ -185,12 +186,12 @@ extern "C" { #endif #endif -/* Security attribution for Battery Backup registers. */ + /* Security attribution for Battery Backup registers. */ #ifndef BSP_TZ_CFG_BBFSAR #define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) #endif -/* Security attribution for registers for IRQ channels. */ + /* Security attribution for registers for IRQ channels. */ #ifndef BSP_TZ_CFG_ICUSARA #define BSP_TZ_CFG_ICUSARA (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ @@ -203,8 +204,8 @@ extern "C" { (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ - (((1 > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ - (((1 > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ @@ -212,12 +213,12 @@ extern "C" { 0xFFFF0000U) #endif -/* Security attribution for NMI registers. */ + /* Security attribution for NMI registers. */ #ifndef BSP_TZ_CFG_ICUSARB #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ #endif -/* Security attribution for registers for DMAC channels */ + /* Security attribution for registers for DMAC channels */ #ifndef BSP_TZ_CFG_ICUSARC #define BSP_TZ_CFG_ICUSARC (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ @@ -231,29 +232,29 @@ extern "C" { 0xFFFFFF00U) #endif -/* Security attribution registers for SELSR0. */ + /* Security attribution registers for SELSR0. */ #ifndef BSP_TZ_CFG_ICUSARD #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) #endif -/* Security attribution registers for WUPEN0. */ + /* Security attribution registers for WUPEN0. */ #ifndef BSP_TZ_CFG_ICUSARE #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) #endif -/* Security attribution registers for WUPEN1. */ + /* Security attribution registers for WUPEN1. */ #ifndef BSP_TZ_CFG_ICUSARF #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) #endif -/* Set DTCSTSAR if the Secure program uses the DTC. */ + /* Set DTCSTSAR if the Secure program uses the DTC. */ #if RA_NOT_DEFINED == RA_NOT_DEFINED -#define BSP_TZ_CFG_DTC_USED (0U) + #define BSP_TZ_CFG_DTC_USED (0U) #else #define BSP_TZ_CFG_DTC_USED (1U) #endif -/* Security attribution of FLWT and FCKMHZ registers. */ + /* Security attribution of FLWT and FCKMHZ registers. */ #ifndef BSP_TZ_CFG_FSAR /* If the CGC registers are only accessible in Secure mode, than there is no * reason for nonsecure applications to access FLWT and FCKMHZ. */ @@ -266,118 +267,119 @@ extern "C" { #endif #endif -/* Security attribution for SRAM registers. */ + /* Security attribution for SRAM registers. */ #ifndef BSP_TZ_CFG_SRAMSAR /* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access * SRAM0WTEN and therefore there is no reason to access PRCR2. */ -#define BSP_TZ_CFG_SRAMSAR (\ + #define BSP_TZ_CFG_SRAMSAR (\ 1 | \ ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ 4 | \ 0xFFFFFFF8U) #endif -/* Security attribution for Standby RAM registers. */ + /* Security attribution for Standby RAM registers. */ #ifndef BSP_TZ_CFG_STBRAMSAR -#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) + #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) #endif -/* Security attribution for the DMAC Bus Master MPU settings. */ + /* Security attribution for the DMAC Bus Master MPU settings. */ #ifndef BSP_TZ_CFG_MMPUSARA -/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ -#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) + /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ + #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) #endif -/* Security Attribution Register A for BUS Control registers. */ + /* Security Attribution Register A for BUS Control registers. */ #ifndef BSP_TZ_CFG_BUSSARA -#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) + #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) #endif -/* Security Attribution Register B for BUS Control registers. */ + /* Security Attribution Register B for BUS Control registers. */ #ifndef BSP_TZ_CFG_BUSSARB -#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) + #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) #endif -/* Enable Uninitialized Non-Secure Application Fallback. */ + /* Enable Uninitialized Non-Secure Application Fallback. */ #ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK -#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) + #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) #endif -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -/* Option Function Select Register 1 Security Attribution */ + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + + /* Option Function Select Register 1 Security Attribution */ #ifndef BSP_CFG_ROM_REG_OFS1_SEL #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U)) #else -#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) #endif #endif -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) -/* Dual Mode Select Register */ + /* Dual Mode Select Register */ #ifndef BSP_CFG_ROM_REG_DUALSEL -#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFFFU) #endif -/* Block Protection Register 0 */ + /* Block Protection Register 0 */ #ifndef BSP_CFG_ROM_REG_BPS0 -#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS0 (~( 0U)) #endif -/* Block Protection Register 1 */ + /* Block Protection Register 1 */ #ifndef BSP_CFG_ROM_REG_BPS1 -#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS1 (~( 0U)) #endif -/* Block Protection Register 2 */ + /* Block Protection Register 2 */ #ifndef BSP_CFG_ROM_REG_BPS2 -#define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_BPS2 (0xFFFFFFFFU) #endif -/* Block Protection Register 3 */ + /* Block Protection Register 3 */ #ifndef BSP_CFG_ROM_REG_BPS3 -#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) #endif -/* Permanent Block Protection Register 0 */ + /* Permanent Block Protection Register 0 */ #ifndef BSP_CFG_ROM_REG_PBPS0 -#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) #endif -/* Permanent Block Protection Register 1 */ + /* Permanent Block Protection Register 1 */ #ifndef BSP_CFG_ROM_REG_PBPS1 -#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) #endif -/* Permanent Block Protection Register 2 */ + /* Permanent Block Protection Register 2 */ #ifndef BSP_CFG_ROM_REG_PBPS2 -#define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_PBPS2 (0xFFFFFFFFU) #endif -/* Permanent Block Protection Register 3 */ + /* Permanent Block Protection Register 3 */ #ifndef BSP_CFG_ROM_REG_PBPS3 -#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) #endif -/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL0 -#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) + #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) #endif -/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL1 -#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) + #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) #endif -/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL2 -#define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_BPS_SEL2 (0xFFFFFFFFU) #endif -/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL3 -#define BSP_CFG_ROM_REG_BPS_SEL3 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_BPS_SEL3 (0xFFFFFFFFU) #endif #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) #endif #ifdef __cplusplus diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000..8ed58a11b --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,67 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define ARDUINO_A0_MIKROBUS_AN (BSP_IO_PORT_00_PIN_00) +#define ARDUINO_A1 (BSP_IO_PORT_00_PIN_01) +#define ARDUINO_A2 (BSP_IO_PORT_00_PIN_03) +#define SW1 (BSP_IO_PORT_00_PIN_05) +#define SW2 (BSP_IO_PORT_00_PIN_06) +#define ARDUINO_A3 (BSP_IO_PORT_00_PIN_07) +#define PMOD1_INT (BSP_IO_PORT_00_PIN_08) +#define ARDUINO_A4 (BSP_IO_PORT_00_PIN_14) +#define ARDUINO_A5 (BSP_IO_PORT_00_PIN_15) +#define ARDUINO_RX_MIKROBUS_RX (BSP_IO_PORT_01_PIN_00) +#define ARDUINO_TX_MIKROBUS_TX (BSP_IO_PORT_01_PIN_01) +#define ARDUINO_D2 (BSP_IO_PORT_01_PIN_05) +#define ARDUINO_D3 (BSP_IO_PORT_01_PIN_11) +#define MIKROBUS_RST (BSP_IO_PORT_01_PIN_15) +#define ARDUINO_MISO_MIKROBUS_MISO_PMOD1_MISO (BSP_IO_PORT_02_PIN_02) +#define ARDUINO_MOSI_MIKROBUS_MOSI_PMOD1_MOSI (BSP_IO_PORT_02_PIN_03) +#define ARDUINO_CLK_MIKROBUS_CLK_PMOD1_CLK (BSP_IO_PORT_02_PIN_04) +#define ARDUINO_SS_MIKCRBUS_SS (BSP_IO_PORT_02_PIN_05) +#define PMOD1_SS1 (BSP_IO_PORT_02_PIN_06) +#define PMOD1_SS2 (BSP_IO_PORT_02_PIN_07) +#define PMOD1_SS3 (BSP_IO_PORT_03_PIN_02) +#define ARDUINO_D9 (BSP_IO_PORT_03_PIN_03) +#define ARDUINO_D7 (BSP_IO_PORT_03_PIN_04) +#define QSPI_CLK (BSP_IO_PORT_03_PIN_05) +#define QSPI_SSL (BSP_IO_PORT_03_PIN_06) +#define QSPI_IO0 (BSP_IO_PORT_03_PIN_07) +#define QSPI_IO1 (BSP_IO_PORT_03_PIN_08) +#define QSPI_IO2 (BSP_IO_PORT_03_PIN_09) +#define QSPI_IO3 (BSP_IO_PORT_03_PIN_10) +#define PMOD1_RST (BSP_IO_PORT_03_PIN_11) +#define LED3 (BSP_IO_PORT_04_PIN_00) +#define LED2 (BSP_IO_PORT_04_PIN_04) +#define USB_VBUS (BSP_IO_PORT_04_PIN_07) +#define ARDUINO_D6_MIKROBUS_PWM (BSP_IO_PORT_04_PIN_08) +#define MIKROBUS_INT (BSP_IO_PORT_04_PIN_09) +#define PMOD2_INT (BSP_IO_PORT_04_PIN_14) +#define LED1 (BSP_IO_PORT_04_PIN_15) +#define USB_VBUS_EN (BSP_IO_PORT_05_PIN_00) +#define USB_VBUS_OC (BSP_IO_PORT_05_PIN_01) +#define GROVE2_AN1 (BSP_IO_PORT_05_PIN_05) +#define GROVE2_AN2 (BSP_IO_PORT_05_PIN_06) +#define GROVE1_SDA_QWIIC_SDA (BSP_IO_PORT_05_PIN_11) +#define GROVE1_SCL_QWIIC_SCL (BSP_IO_PORT_05_PIN_12) +#define ARDUINO_SCL_MIKROBUS_SCL (BSP_IO_PORT_06_PIN_01) +#define ARDUINO_SDA_MIKROBUS_SDA (BSP_IO_PORT_06_PIN_02) +#define ARDUINO_D8 (BSP_IO_PORT_06_PIN_11) +#define ARDUINO_RST (BSP_IO_PORT_06_PIN_12) +#define PMOD2_RST (BSP_IO_PORT_07_PIN_08) +#define PMOD2_SS2 (BSP_IO_PORT_07_PIN_09) +#define PMOD2_SS3 (BSP_IO_PORT_07_PIN_10) +#define ARDUINO_D5 (BSP_IO_PORT_07_PIN_12) +#define ARDUINO_D4 (BSP_IO_PORT_07_PIN_13) +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA4M3 EK */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h index 80641945d..3eac2985e 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/bsp_clock_cfg.h @@ -7,10 +7,10 @@ #define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ -#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(24U,0U) /* PLL Mul x24.0 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(25U,0U) /* PLL Mul x25.0 */ #define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ -#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL2 Div /3 */ -#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(24U,0U) /* PLL2 Mul x24.0 */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ +#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL2 Mul x20.0 */ #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ #define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ #define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ @@ -21,5 +21,5 @@ #define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ #define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ #define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ -#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_4) /* UCLK Div /4 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ #endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.c new file mode 100644 index 000000000..50036c0ad --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.c @@ -0,0 +1,11 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.h new file mode 100644 index 000000000..6a08cbee0 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/pin_data.c new file mode 100644 index 000000000..bf30782cf --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/ra_gen/pin_data.c @@ -0,0 +1,263 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_00_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_00_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_00_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_01_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_01_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_01_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_01_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_02_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_03_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_03_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_03_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_QSPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_04_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_GPT1) + }, + { + .pin = BSP_IO_PORT_04_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_04_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_04_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_05_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_05_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_05_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_05_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_05_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) + }, + { + .pin = BSP_IO_PORT_05_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) + }, + { + .pin = BSP_IO_PORT_06_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_06_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_NMOS_ENABLE | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_06_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_06_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_07_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_07_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_07_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_07_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_07_PIN_13, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld b/hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld new file mode 100644 index 000000000..627ffe4d9 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld @@ -0,0 +1,766 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + +/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ +/* + XIP_SECONDARY_SLOT_IMAGE = 1; +*/ + +QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); +OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); +OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); + +/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ +__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); + +ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; +ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; +DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; +DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; +RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; +RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; +RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; +RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; + +OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; + +/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. + * Bootloader images do not configure option settings because they are owned by the bootloader. + * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ +__bl_FSP_BOOTABLE_IMAGE = 1; +__bln_FSP_BOOTABLE_IMAGE = 1; +PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); + +__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; +__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; +__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; +__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; +__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); +__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; + +XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; +FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : + XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : + FLASH_IMAGE_START; +LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : + DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : + FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; + +/* Define memory regions. */ +MEMORY +{ + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be DEFINED in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * __qspi_flash_start__ + * __qspi_flash_end__ + * __qspi_flash_code_size__ + * __qspi_region_max_size__ + * __qspi_region_start_address__ + * __qspi_region_end_address__ + * __ospi_device_0_start__ + * __ospi_device_0_end__ + * __ospi_device_0_code_size__ + * __ospi_device_0_region_max_size__ + * __ospi_device_0_region_start_address__ + * __ospi_device_0_region_end_address__ + * __ospi_device_1_start__ + * __ospi_device_1_end__ + * __ospi_device_1_code_size__ + * __ospi_device_1_region_max_size__ + * __ospi_device_1_region_start_address__ + * __ospi_device_1_region_end_address__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __tz_FLASH_S = ABSOLUTE(FLASH_START); + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + + /* Some devices have a gap of code flash between the vector table and ROM Registers. + * The flash gap section allows applications to place code and data in this section. */ + *(.flash_gap*) + + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Allocate flash write-boundary-aligned + * space for sce9 wrapped public keys for mcuboot if the module is used. + */ + KEEP(*(.mcuboot_sce9_key*)) + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) + { + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; + + __exidx_start = .; + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); + + /* Initialized DTCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) + { + /* Start of DTCM Secure Trustzone region. */ + __tz_DTCM_S = ABSOLUTE(DTCM_START); + + /* Initialized DTCM data start */ + __dtcm_data_start = .; + + KEEP(*(.dtcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; + /* Uninitialized DTCM data. */ + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : + { + /* Uninitialized DTCM data start */ + __dtcm_bss_start = .; + + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); + + /* Uninitialized DTCM data end */ + __dtcm_bss_end = .; + + /* + * Start of the DTCM Non-Secure Trustzone region. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. + */ + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); + } > DTCM + + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ + . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; + + KEEP(*(.ns_buffer*)) + } > RAM + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. + * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE + * memory region between TrustZone projects. */ + __tz_ID_CODE_N = __tz_ID_CODE_S; + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); + + .option_setting_ofs : + { + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_ofs2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; + } > OPTION_SETTING_OFS = 0xFF + + .option_setting_sas : + { + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; + } > OPTION_SETTING_SAS = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_ofs3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; +} diff --git a/hw/bsp/ra/boards/ra4m3_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra4m3_ek/script/memory_regions.ld new file mode 100644 index 000000000..04d7de497 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/script/memory_regions.ld @@ -0,0 +1,22 @@ + + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x20000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x100000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x2000; + OPTION_SETTING_START = 0x0100A100; + OPTION_SETTING_LENGTH = 0x100; + OPTION_SETTING_S_START = 0x0100A200; + OPTION_SETTING_S_LENGTH = 0x100; + ID_CODE_START = 0x00000000; + ID_CODE_LENGTH = 0x0; + SDRAM_START = 0x80010000; + SDRAM_LENGTH = 0x0; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x4000000; + OSPI_DEVICE_0_START = 0x80020000; + OSPI_DEVICE_0_LENGTH = 0x0; + OSPI_DEVICE_1_START = 0x80030000; + OSPI_DEVICE_1_LENGTH = 0x0; diff --git a/hw/bsp/ra/boards/ra4m3_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra4m3_ek/smart_configurator/configuration.xml new file mode 100644 index 000000000..1d75f1b72 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m3_ek/smart_configurator/configuration.xml @@ -0,0 +1,432 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Simple application that blinks an LED. No RTOS included. + Renesas.RA_baremetal_blinky.5.6.0.pack + + + Board Support Package Common Files + Renesas.RA.5.6.0.pack + + + I/O Port + Renesas.RA.5.6.0.pack + + + Arm CMSIS Version 6 - Core (M) + Arm.CMSIS6.6.1.0+fsp.5.6.0.pack + + + Board support package for R7FA4M3AF3CFB + Renesas.RA_mcu_ra4m3.5.6.0.pack + + + Board support package for RA4M3 + Renesas.RA_mcu_ra4m3.5.6.0.pack + + + Board support package for RA4M3 - FSP Data + Renesas.RA_mcu_ra4m3.5.6.0.pack + + + Board support package for RA4M3 - Events + Renesas.RA_mcu_ra4m3.5.6.0.pack + + + RA4M3-EK Board Support Files + Renesas.RA_board_ra4m3_ek.5.6.0.pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.3.1 From ec1c8b99e27e03e0d79da74706034ea184bf8a36 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 12 Dec 2024 16:30:09 +0700 Subject: rasc for ra4m1_ek --- hw/bsp/ra/boards/ra4m1_ek/board.h | 14 +- .../boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 89 ++- .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 12 +- .../ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 138 ++-- .../ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h | 17 + hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h | 2 +- hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.c | 11 + hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.h | 20 + hw/bsp/ra/boards/ra4m1_ek/ra_gen/pin_data.c | 119 ++++ hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld | 766 +++++++++++++++++++++ hw/bsp/ra/boards/ra4m1_ek/script/memory_regions.ld | 22 + 11 files changed, 1093 insertions(+), 117 deletions(-) create mode 100644 hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h create mode 100644 hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.c create mode 100644 hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.h create mode 100644 hw/bsp/ra/boards/ra4m1_ek/ra_gen/pin_data.c create mode 100644 hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld create mode 100644 hw/bsp/ra/boards/ra4m1_ek/script/memory_regions.ld (limited to 'hw') diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.h b/hw/bsp/ra/boards/ra4m1_ek/board.h index c132387bc..ba663d040 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/board.h +++ b/hw/bsp/ra/boards/ra4m1_ek/board.h @@ -31,21 +31,9 @@ extern "C" { #endif -#define LED1 BSP_IO_PORT_01_PIN_06 -#define LED_STATE_ON 1 - -#define SW1 BSP_IO_PORT_01_PIN_05 +#define LED_STATE_ON 1 #define BUTTON_STATE_ACTIVE 0 -static const ioport_pin_cfg_t board_pin_cfg[] = { - {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT}, - {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT}, - // USB FS D+, D-, VBus - {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, - {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, - {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, -}; - #ifdef __cplusplus } #endif diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h index 11d5795df..43b0f5b65 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -1,35 +1,62 @@ /* generated configuration header file - do not edit */ #ifndef BSP_CFG_H_ #define BSP_CFG_H_ - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#undef RA_NOT_DEFINED -#define BSP_CFG_RTOS (0) -#if defined(_RA_BOOT_IMAGE) -#define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x800) -#define BSP_CFG_HEAP_BYTES (0x1000) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) - -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 - +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x800) + #define BSP_CFG_HEAP_BYTES (0x1000) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif #endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h index d810dabb2..243fad9b6 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -2,10 +2,10 @@ #ifndef BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_R7FA4M1AB3CFP -#define BSP_MCU_FEATURE_SET ('A') -#define BSP_ROM_SIZE_BYTES (262144) -#define BSP_RAM_SIZE_BYTES (32768) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (100) + #define BSP_MCU_FEATURE_SET ('A') + #define BSP_ROM_SIZE_BYTES (262144) + #define BSP_RAM_SIZE_BYTES (32768) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) + #define BSP_PACKAGE_LQFP + #define BSP_PACKAGE_PINS (100) #endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h index 72cdb89e6..3d482b2b6 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -1,78 +1,84 @@ -/* generated configuration header file through renesas e2 studio */ +/* generated configuration header file - do not edit */ #ifndef BSP_MCU_FAMILY_CFG_H_ #define BSP_MCU_FAMILY_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "bsp_mcu_info.h" -#include "bsp_clock_cfg.h" - -#define BSP_MCU_GROUP_RA4M1 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 - #define BSP_HOCO_HZ (24000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (32000000) -#elif BSP_CFG_HOCO_FREQUENCY == 4 - #define BSP_HOCO_HZ (48000000) -#elif BSP_CFG_HOCO_FREQUENCY == 5 - #define BSP_HOCO_HZ (64000000) -#else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA4M1 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (24000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (32000000) + #elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (48000000) + #elif BSP_CFG_HOCO_FREQUENCY == 5 + #define BSP_HOCO_HZ (64000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) -#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) -#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) + #define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) + #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) + #define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) + #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) + #define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) + #endif + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) -/* - ID Code - Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. - WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. - */ -#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) + /* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ + #if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) #else -/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ -#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) -#endif + /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ + #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) + #endif + #ifdef __cplusplus + } + #endif #endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000..f77a5bcec --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,17 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define SW1 (BSP_IO_PORT_01_PIN_05) +#define LED1 (BSP_IO_PORT_01_PIN_06) +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA4M1-EK.pincfg */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h index 554126523..81ac5dc11 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/bsp_clock_cfg.h @@ -7,7 +7,7 @@ #define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ #define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */ #define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ -#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(8u,0u)) /* PLL Mul x8 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(8U,0U) /* PLL Mul x8 */ #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ #define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.c new file mode 100644 index 000000000..50036c0ad --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.c @@ -0,0 +1,11 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.h new file mode 100644 index 000000000..6a08cbee0 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/pin_data.c new file mode 100644 index 000000000..baa713443 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/ra_gen/pin_data.c @@ -0,0 +1,119 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_00_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_01_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_01_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_01_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU) + }, + { + .pin = BSP_IO_PORT_02_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU) + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_04_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_04_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_04_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_09_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_09_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld new file mode 100644 index 000000000..627ffe4d9 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld @@ -0,0 +1,766 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + +/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ +/* + XIP_SECONDARY_SLOT_IMAGE = 1; +*/ + +QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); +OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); +OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); + +/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ +__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); + +ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; +ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; +DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; +DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; +RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; +RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; +RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; +RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; + +OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; + +/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. + * Bootloader images do not configure option settings because they are owned by the bootloader. + * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ +__bl_FSP_BOOTABLE_IMAGE = 1; +__bln_FSP_BOOTABLE_IMAGE = 1; +PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); + +__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; +__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; +__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; +__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; +__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); +__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; + +XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; +FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : + XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : + FLASH_IMAGE_START; +LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : + DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : + FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; + +/* Define memory regions. */ +MEMORY +{ + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be DEFINED in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * __qspi_flash_start__ + * __qspi_flash_end__ + * __qspi_flash_code_size__ + * __qspi_region_max_size__ + * __qspi_region_start_address__ + * __qspi_region_end_address__ + * __ospi_device_0_start__ + * __ospi_device_0_end__ + * __ospi_device_0_code_size__ + * __ospi_device_0_region_max_size__ + * __ospi_device_0_region_start_address__ + * __ospi_device_0_region_end_address__ + * __ospi_device_1_start__ + * __ospi_device_1_end__ + * __ospi_device_1_code_size__ + * __ospi_device_1_region_max_size__ + * __ospi_device_1_region_start_address__ + * __ospi_device_1_region_end_address__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __tz_FLASH_S = ABSOLUTE(FLASH_START); + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + + /* Some devices have a gap of code flash between the vector table and ROM Registers. + * The flash gap section allows applications to place code and data in this section. */ + *(.flash_gap*) + + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Allocate flash write-boundary-aligned + * space for sce9 wrapped public keys for mcuboot if the module is used. + */ + KEEP(*(.mcuboot_sce9_key*)) + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) + { + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; + + __exidx_start = .; + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); + + /* Initialized DTCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) + { + /* Start of DTCM Secure Trustzone region. */ + __tz_DTCM_S = ABSOLUTE(DTCM_START); + + /* Initialized DTCM data start */ + __dtcm_data_start = .; + + KEEP(*(.dtcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; + /* Uninitialized DTCM data. */ + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : + { + /* Uninitialized DTCM data start */ + __dtcm_bss_start = .; + + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); + + /* Uninitialized DTCM data end */ + __dtcm_bss_end = .; + + /* + * Start of the DTCM Non-Secure Trustzone region. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. + */ + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); + } > DTCM + + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ + . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; + + KEEP(*(.ns_buffer*)) + } > RAM + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. + * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE + * memory region between TrustZone projects. */ + __tz_ID_CODE_N = __tz_ID_CODE_S; + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); + + .option_setting_ofs : + { + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_ofs2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; + } > OPTION_SETTING_OFS = 0xFF + + .option_setting_sas : + { + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; + } > OPTION_SETTING_SAS = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_ofs3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; +} diff --git a/hw/bsp/ra/boards/ra4m1_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra4m1_ek/script/memory_regions.ld new file mode 100644 index 000000000..2d6992fed --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/script/memory_regions.ld @@ -0,0 +1,22 @@ + + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x8000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x40000; + DATA_FLASH_START = 0x40100000; + DATA_FLASH_LENGTH = 0x2000; + OPTION_SETTING_START = 0x00000000; + OPTION_SETTING_LENGTH = 0x0; + OPTION_SETTING_S_START = 0x80000000; + OPTION_SETTING_S_LENGTH = 0x0; + ID_CODE_START = 0x01010018; + ID_CODE_LENGTH = 0x20; + SDRAM_START = 0x80010000; + SDRAM_LENGTH = 0x0; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x0; + OSPI_DEVICE_0_START = 0x80020000; + OSPI_DEVICE_0_LENGTH = 0x0; + OSPI_DEVICE_1_START = 0x80030000; + OSPI_DEVICE_1_LENGTH = 0x0; -- cgit v1.3.1 From 4d1f9450969146da89aca1e3064c7f27d2645ba9 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 12 Dec 2024 16:45:45 +0700 Subject: rasc ra2a1_ek, but usb does not seem to work. Note fsp.ld need extra 0x100 byte for ROM registers to work. --- .idea/cmake.xml | 7 +- hw/bsp/ra/boards/ra2a1_ek/board.h | 14 +- .../boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 80 +-- .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 12 +- .../ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 119 ++-- .../ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h | 17 + hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h | 2 +- hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.c | 11 + hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.h | 20 + hw/bsp/ra/boards/ra2a1_ek/ra_gen/pin_data.c | 115 +++ hw/bsp/ra/boards/ra2a1_ek/script/fsp.ld | 769 +++++++++++++++++++++ hw/bsp/ra/boards/ra2a1_ek/script/memory_regions.ld | 22 + .../ra2a1_ek/smart_configurator/configuration.xml | 258 +++++++ .../ra4m1_ek/smart_configurator/configuration.xml | 271 ++++++++ hw/bsp/ra/family.c | 6 - 15 files changed, 1597 insertions(+), 126 deletions(-) create mode 100644 hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h create mode 100644 hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.c create mode 100644 hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.h create mode 100644 hw/bsp/ra/boards/ra2a1_ek/ra_gen/pin_data.c create mode 100644 hw/bsp/ra/boards/ra2a1_ek/script/fsp.ld create mode 100644 hw/bsp/ra/boards/ra2a1_ek/script/memory_regions.ld create mode 100644 hw/bsp/ra/boards/ra2a1_ek/smart_configurator/configuration.xml create mode 100644 hw/bsp/ra/boards/ra4m1_ek/smart_configurator/configuration.xml (limited to 'hw') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 6e58f040c..9399a121a 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -118,11 +118,12 @@ - - + + + - + diff --git a/hw/bsp/ra/boards/ra2a1_ek/board.h b/hw/bsp/ra/boards/ra2a1_ek/board.h index 1c2b666d2..ba663d040 100644 --- a/hw/bsp/ra/boards/ra2a1_ek/board.h +++ b/hw/bsp/ra/boards/ra2a1_ek/board.h @@ -31,21 +31,9 @@ extern "C" { #endif -#define LED1 BSP_IO_PORT_02_PIN_05 -#define LED_STATE_ON 1 - -#define SW1 BSP_IO_PORT_02_PIN_06 +#define LED_STATE_ON 1 #define BUTTON_STATE_ACTIVE 0 -static const ioport_pin_cfg_t board_pin_cfg[] = { - {.pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT}, - {.pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT}, - // USB FS D+, D-, VBus - {.pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, - {.pin = BSP_IO_PORT_09_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, - {.pin = BSP_IO_PORT_09_PIN_15, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS}, -}; - #ifdef __cplusplus } #endif diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h index 30637c17b..bf1fe0cc6 100644 --- a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -5,58 +5,58 @@ extern "C" { #endif -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" -#define RA_NOT_DEFINED 0 -#ifndef BSP_CFG_RTOS -#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) #define BSP_CFG_RTOS (2) #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) #define BSP_CFG_RTOS (1) #else -#define BSP_CFG_RTOS (0) -#endif -#endif -#ifndef BSP_CFG_RTC_USED -#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) -#endif -#undef RA_NOT_DEFINED -#if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) #define BSP_CFG_BOOT_IMAGE (1) #endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x400) -#define BSP_CFG_HEAP_BYTES (0x400) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x400) + #define BSP_CFG_HEAP_BYTES (0x400) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) -#define BSP_CFG_PFS_PROTECT ((1)) + #define BSP_CFG_PFS_PROTECT ((1)) -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) -#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) -#endif + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + #endif -#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#endif + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif -#ifdef __cplusplus + #ifdef __cplusplus } #endif #endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h index 710e85b28..6970e4c33 100644 --- a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -2,10 +2,10 @@ #ifndef BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_R7FA2A1AB3CFM -#define BSP_MCU_FEATURE_SET ('A') -#define BSP_ROM_SIZE_BYTES (262144) -#define BSP_RAM_SIZE_BYTES (32768) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (64) + #define BSP_MCU_FEATURE_SET ('A') + #define BSP_ROM_SIZE_BYTES (262144) + #define BSP_RAM_SIZE_BYTES (32768) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) + #define BSP_PACKAGE_LQFP + #define BSP_PACKAGE_PINS (64) #endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h index 6caef62cc..24e3efaa2 100644 --- a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -5,17 +5,17 @@ extern "C" { #endif -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "../../../ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h" -#include "bsp_clock_cfg.h" -#define BSP_MCU_GROUP_RA2A1 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (24000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra2a1/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA2A1 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (24000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 #define BSP_HOCO_HZ (32000000) #elif BSP_CFG_HOCO_FREQUENCY == 4 #define BSP_HOCO_HZ (48000000) @@ -25,60 +25,65 @@ #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" #endif -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (0) -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) -#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC0_START (0x000FFFFC) -#define BSP_CFG_ROM_REG_MPU_PC0_END (0x000FFFFF) -#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_PC1_START (0x000FFFFC) -#define BSP_CFG_ROM_REG_MPU_PC1_END (0x000FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x000FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x000FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) -#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) -#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) -#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) -#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) -#endif -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) + #define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC0_START (0x000FFFFC) + #define BSP_CFG_ROM_REG_MPU_PC0_END (0x000FFFFF) + #define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_PC1_START (0x000FFFFC) + #define BSP_CFG_ROM_REG_MPU_PC1_END (0x000FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION0_START (0x000FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION0_END (0x000FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) + #define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) + #define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) + #define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) + #endif + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) -/* - ID Code - Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. - WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. - */ -#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) + /* + ID Code + Note: To lock and disable the debug interface define BSP_ID_CODE_LOCKED in compiler settings. + WARNING: This will disable debug access to the part. However, ALeRASE command will be accepted, which will clear (reset) the ID code. After clearing ID code, debug access will be enabled. + */ + #if defined(BSP_ID_CODE_LOCKED) #define BSP_CFG_ID_CODE_LONG_1 (0x00000000) #define BSP_CFG_ID_CODE_LONG_2 (0x00000000) #define BSP_CFG_ID_CODE_LONG_3 (0x00000000) #define BSP_CFG_ID_CODE_LONG_4 (0x00000000) #else -/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ -#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) -#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) -#endif + /* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ + #define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) + #define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) + #endif -#ifdef __cplusplus + #if (0) + #define BSP_SECTION_FLASH_GAP BSP_PLACE_IN_SECTION(".flash_gap") + #endif + + #ifdef __cplusplus } #endif #endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000..fc48a5809 --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,17 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define LED1 (BSP_IO_PORT_02_PIN_05) +#define SW1 (BSP_IO_PORT_02_PIN_06) +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA2A1-EK.pincfg */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h index cd9d135f7..6b41669d3 100644 --- a/hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/bsp_clock_cfg.h @@ -8,7 +8,7 @@ #define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */ #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ #define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ -#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ #define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ #define BSP_CFG_SDADC_CLOCK_SOURCE (0) /* SDADCCLK Src: HOCO */ #define BSP_CFG_SDADCCLK_DIV (7) /* SDADCCLK Div /12 */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.c new file mode 100644 index 000000000..50036c0ad --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.c @@ -0,0 +1,11 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.h new file mode 100644 index 000000000..6a08cbee0 --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/hw/bsp/ra/boards/ra2a1_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/pin_data.c new file mode 100644 index 000000000..7fed32687 --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/ra_gen/pin_data.c @@ -0,0 +1,115 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_00_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU) + }, + { + .pin = BSP_IO_PORT_00_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_01_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_02_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_02_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_02_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_02_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_03_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_03_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_04_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_CTSU) + }, + { + .pin = BSP_IO_PORT_04_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_09_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_09_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/hw/bsp/ra/boards/ra2a1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra2a1_ek/script/fsp.ld new file mode 100644 index 000000000..605eef7d2 --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/script/fsp.ld @@ -0,0 +1,769 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + +/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ +/* + XIP_SECONDARY_SLOT_IMAGE = 1; +*/ + +QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); +OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); +OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); + +/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ +__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); + +ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; +ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; +DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; +DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; +RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; +RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; +RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; +RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; + +OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; + +/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. + * Bootloader images do not configure option settings because they are owned by the bootloader. + * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ +__bl_FSP_BOOTABLE_IMAGE = 1; +__bln_FSP_BOOTABLE_IMAGE = 1; +PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); + +__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; +__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; +__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; +__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; +__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); +__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; + +XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; +FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : + XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : + FLASH_IMAGE_START; +LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : + DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : + FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; + +/* Define memory regions. */ +MEMORY +{ + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be DEFINED in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * __qspi_flash_start__ + * __qspi_flash_end__ + * __qspi_flash_code_size__ + * __qspi_region_max_size__ + * __qspi_region_start_address__ + * __qspi_region_end_address__ + * __ospi_device_0_start__ + * __ospi_device_0_end__ + * __ospi_device_0_code_size__ + * __ospi_device_0_region_max_size__ + * __ospi_device_0_region_start_address__ + * __ospi_device_0_region_end_address__ + * __ospi_device_1_start__ + * __ospi_device_1_end__ + * __ospi_device_1_code_size__ + * __ospi_device_1_region_max_size__ + * __ospi_device_1_region_start_address__ + * __ospi_device_1_region_end_address__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __tz_FLASH_S = ABSOLUTE(FLASH_START); + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + + /* Some devices have a gap of code flash between the vector table and ROM Registers. + * The flash gap section allows applications to place code and data in this section. */ + *(.flash_gap*) + + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; + + /* Allocate flash write-boundary-aligned + * space for sce9 wrapped public keys for mcuboot if the module is used. + */ + KEEP(*(.mcuboot_sce9_key*)) + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) + { + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; + + __exidx_start = .; + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); + + /* Initialized DTCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) + { + /* Start of DTCM Secure Trustzone region. */ + __tz_DTCM_S = ABSOLUTE(DTCM_START); + + /* Initialized DTCM data start */ + __dtcm_data_start = .; + + KEEP(*(.dtcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; + /* Uninitialized DTCM data. */ + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : + { + /* Uninitialized DTCM data start */ + __dtcm_bss_start = .; + + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); + + /* Uninitialized DTCM data end */ + __dtcm_bss_end = .; + + /* + * Start of the DTCM Non-Secure Trustzone region. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. + */ + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); + } > DTCM + + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ + . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; + + KEEP(*(.ns_buffer*)) + } > RAM + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. + * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE + * memory region between TrustZone projects. */ + __tz_ID_CODE_N = __tz_ID_CODE_S; + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); + + .option_setting_ofs : + { + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_ofs2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; + } > OPTION_SETTING_OFS = 0xFF + + .option_setting_sas : + { + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; + } > OPTION_SETTING_SAS = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_ofs3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; +} diff --git a/hw/bsp/ra/boards/ra2a1_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra2a1_ek/script/memory_regions.ld new file mode 100644 index 000000000..2d6992fed --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/script/memory_regions.ld @@ -0,0 +1,22 @@ + + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x8000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x40000; + DATA_FLASH_START = 0x40100000; + DATA_FLASH_LENGTH = 0x2000; + OPTION_SETTING_START = 0x00000000; + OPTION_SETTING_LENGTH = 0x0; + OPTION_SETTING_S_START = 0x80000000; + OPTION_SETTING_S_LENGTH = 0x0; + ID_CODE_START = 0x01010018; + ID_CODE_LENGTH = 0x20; + SDRAM_START = 0x80010000; + SDRAM_LENGTH = 0x0; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x0; + OSPI_DEVICE_0_START = 0x80020000; + OSPI_DEVICE_0_LENGTH = 0x0; + OSPI_DEVICE_1_START = 0x80030000; + OSPI_DEVICE_1_LENGTH = 0x0; diff --git a/hw/bsp/ra/boards/ra2a1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra2a1_ek/smart_configurator/configuration.xml new file mode 100644 index 000000000..beeeb67f2 --- /dev/null +++ b/hw/bsp/ra/boards/ra2a1_ek/smart_configurator/configuration.xml @@ -0,0 +1,258 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Simple application that blinks an LED. No RTOS included. + Renesas.RA_baremetal_blinky.5.6.0.pack + + + Board Support Package Common Files + Renesas.RA.5.6.0.pack + + + I/O Port + Renesas.RA.5.6.0.pack + + + Arm CMSIS Version 6 - Core (M) + Arm.CMSIS6.6.1.0+fsp.5.6.0.pack + + + RA2A1-EK Board Support Files + Renesas.RA_board_ra2a1_ek.5.6.0.pack + + + Board support package for R7FA2A1AB3CFM + Renesas.RA_mcu_ra2a1.5.6.0.pack + + + Board support package for RA2A1 + Renesas.RA_mcu_ra2a1.5.6.0.pack + + + Board support package for RA2A1 - FSP Data + Renesas.RA_mcu_ra2a1.5.6.0.pack + + + Board support package for RA2A1 - Events + Renesas.RA_mcu_ra2a1.5.6.0.pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hw/bsp/ra/boards/ra4m1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra4m1_ek/smart_configurator/configuration.xml new file mode 100644 index 000000000..2ca7fe595 --- /dev/null +++ b/hw/bsp/ra/boards/ra4m1_ek/smart_configurator/configuration.xml @@ -0,0 +1,271 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Simple application that blinks an LED. No RTOS included. + Renesas.RA_baremetal_blinky.5.6.0.pack + + + Board Support Package Common Files + Renesas.RA.5.6.0.pack + + + I/O Port + Renesas.RA.5.6.0.pack + + + Arm CMSIS Version 6 - Core (M) + Arm.CMSIS6.6.1.0+fsp.5.6.0.pack + + + RA4M1-EK Board Support Files + Renesas.RA_board_ra4m1_ek.5.6.0.pack + + + Board support package for R7FA4M1AB3CFP + Renesas.RA_mcu_ra4m1.5.6.0.pack + + + Board support package for RA4M1 + Renesas.RA_mcu_ra4m1.5.6.0.pack + + + Board support package for RA4M1 - FSP Data + Renesas.RA_mcu_ra4m1.5.6.0.pack + + + Board support package for RA4M1 - Events + Renesas.RA_mcu_ra4m1.5.6.0.pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index c6575e88d..29dcb912c 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -49,12 +49,6 @@ /* Key code for writing PRCR register. */ #define BSP_PRV_PRCR_KEY (0xA500U) -// static const ioport_cfg_t family_pin_cfg = { -// .number_of_pins = sizeof(board_pin_cfg) / sizeof(ioport_pin_cfg_t), -// .p_pin_cfg_data = board_pin_cfg, -// }; -// static ioport_instance_ctrl_t port_ctrl; - //--------------------------------------------------------------------+ // Vector Data //--------------------------------------------------------------------+ -- cgit v1.3.1 From ec2f2f3523c8a685bb56f5443faf92307f74a308 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 12 Dec 2024 23:50:50 +0700 Subject: rasc for portenta_c33 --- hw/bsp/ra/boards/portenta_c33/board.h | 27 - hw/bsp/ra/boards/portenta_c33/portenta_c33.ld | 25 - .../portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 115 ++-- .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 12 +- .../ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 235 +++---- .../ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h | 62 +- hw/bsp/ra/boards/portenta_c33/script/fsp.ld | 766 +++++++++++++++++++++ .../boards/portenta_c33/script/memory_regions.ld | 25 + .../smart_configurator/configuration.xml | 240 +++++++ hw/bsp/ra/linker/gcc/fsp.ld | 716 ------------------- hw/bsp/ra/linker/gcc/ra2a1.ld | 22 - hw/bsp/ra/linker/gcc/ra4m1.ld | 22 - hw/bsp/ra/linker/gcc/ra4m3.ld | 22 - hw/bsp/ra/linker/gcc/ra6m1.ld | 22 - hw/bsp/ra/linker/gcc/ra6m5.ld | 22 - 15 files changed, 1244 insertions(+), 1089 deletions(-) delete mode 100644 hw/bsp/ra/boards/portenta_c33/portenta_c33.ld create mode 100644 hw/bsp/ra/boards/portenta_c33/script/fsp.ld create mode 100644 hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld create mode 100644 hw/bsp/ra/boards/portenta_c33/smart_configurator/configuration.xml delete mode 100644 hw/bsp/ra/linker/gcc/fsp.ld delete mode 100644 hw/bsp/ra/linker/gcc/ra2a1.ld delete mode 100644 hw/bsp/ra/linker/gcc/ra4m1.ld delete mode 100644 hw/bsp/ra/linker/gcc/ra4m3.ld delete mode 100644 hw/bsp/ra/linker/gcc/ra6m1.ld delete mode 100644 hw/bsp/ra/linker/gcc/ra6m5.ld (limited to 'hw') diff --git a/hw/bsp/ra/boards/portenta_c33/board.h b/hw/bsp/ra/boards/portenta_c33/board.h index 7841ec8b8..ba663d040 100644 --- a/hw/bsp/ra/boards/portenta_c33/board.h +++ b/hw/bsp/ra/boards/portenta_c33/board.h @@ -31,36 +31,9 @@ extern "C" { #endif -#define LED1 BSP_IO_PORT_01_PIN_07 // Red LED #define LED_STATE_ON 1 - -#define SW1 BSP_IO_PORT_04_PIN_08 // D12 #define BUTTON_STATE_ACTIVE 0 -static const ioport_pin_cfg_t board_pin_cfg[] = { - { .pin = LED1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_OUTPUT | IOPORT_CFG_PORT_OUTPUT_LOW }, - { .pin = SW1, .pin_cfg = IOPORT_CFG_PORT_DIRECTION_INPUT }, - - // USB FS - { .pin = BSP_IO_PORT_04_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH }, - { .pin = BSP_IO_PORT_05_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, - { .pin = BSP_IO_PORT_05_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_FS | IOPORT_CFG_DRIVE_HIGH}, - - // USB HS - { .pin = BSP_IO_PORT_07_PIN_07, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS }, - { .pin = BSP_IO_PORT_11_PIN_00, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, - { .pin = BSP_IO_PORT_11_PIN_01, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_USB_HS | IOPORT_CFG_DRIVE_HIGH}, - - // ETM Trace - #ifdef TRACE_ETM - { .pin = BSP_IO_PORT_02_PIN_08, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_09, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_10, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_11, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - { .pin = BSP_IO_PORT_02_PIN_14, .pin_cfg = IOPORT_CFG_PERIPHERAL_PIN | IOPORT_PERIPHERAL_TRACE | IOPORT_CFG_DRIVE_HS_HIGH }, - #endif -}; - #ifdef __cplusplus } #endif diff --git a/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld b/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld deleted file mode 100644 index ba15588e6..000000000 --- a/hw/bsp/ra/boards/portenta_c33/portenta_c33.ld +++ /dev/null @@ -1,25 +0,0 @@ -RAM_START = 0x20000000; -RAM_LENGTH = 0x80000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x200000; -DATA_FLASH_START = 0x08000000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x0100A100; -OPTION_SETTING_LENGTH = 0x100; -OPTION_SETTING_S_START = 0x0100A200; -OPTION_SETTING_S_LENGTH = 0x100; -ID_CODE_START = 0x00000000; -ID_CODE_LENGTH = 0x0; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x4000000; -OSPI_DEVICE_0_START = 0x68000000; -OSPI_DEVICE_0_LENGTH = 0x8000000; -OSPI_DEVICE_1_START = 0x70000000; -OSPI_DEVICE_1_LENGTH = 0x10000000; - -/* Board has bootloader */ -FLASH_IMAGE_START = 0x10000; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h index 33d381850..90afbdef3 100644 --- a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -2,62 +2,61 @@ #ifndef BSP_CFG_H_ #define BSP_CFG_H_ #ifdef __cplusplus -extern "C" { -#endif - -#include "bsp_clock_cfg.h" -#include "bsp_mcu_family_cfg.h" -#include "board_cfg.h" - -#define RA_NOT_DEFINED 0 -#ifndef BSP_CFG_RTOS -#if (RA_NOT_DEFINED) != (2) -#define BSP_CFG_RTOS (2) -#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) - #define BSP_CFG_RTOS (1) -#else - #define BSP_CFG_RTOS (0) -#endif -#endif -#ifndef BSP_CFG_RTC_USED -#define BSP_CFG_RTC_USED (RA_NOT_DEFINED) -#endif -#undef RA_NOT_DEFINED -#if defined(_RA_BOOT_IMAGE) - #define BSP_CFG_BOOT_IMAGE (1) -#endif -#define BSP_CFG_MCU_VCC_MV (3300) -#define BSP_CFG_STACK_MAIN_BYTES (0x1000) -#define BSP_CFG_HEAP_BYTES (0x1000) -#define BSP_CFG_PARAM_CHECKING_ENABLE (1) -#define BSP_CFG_ASSERT (0) -#define BSP_CFG_ERROR_LOG (0) - -#define BSP_CFG_PFS_PROTECT ((1)) - -#define BSP_CFG_C_RUNTIME_INIT ((1)) -#define BSP_CFG_EARLY_INIT ((0)) - -#define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED -#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) -#endif - -#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE -#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE -#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED -#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) -#endif -#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS -#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 -#endif - -#ifdef __cplusplus -} -#endif + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x1000) + #define BSP_CFG_HEAP_BYTES (0x1000) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif #endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h index 6845183db..e532478f8 100644 --- a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -2,10 +2,10 @@ #ifndef BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_DEVICE_PN_CFG_H_ #define BSP_MCU_R7FA6M5BH3CFC -#define BSP_MCU_FEATURE_SET ('B') -#define BSP_ROM_SIZE_BYTES (2097152) -#define BSP_RAM_SIZE_BYTES (524288) -#define BSP_DATA_FLASH_SIZE_BYTES (8192) -#define BSP_PACKAGE_LQFP -#define BSP_PACKAGE_PINS (176) + #define BSP_MCU_FEATURE_SET ('B') + #define BSP_ROM_SIZE_BYTES (2097152) + #define BSP_RAM_SIZE_BYTES (524288) + #define BSP_DATA_FLASH_SIZE_BYTES (8192) + #define BSP_PACKAGE_LQFP + #define BSP_PACKAGE_PINS (176) #endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h index d5428540f..c01219377 100644 --- a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -5,80 +5,80 @@ extern "C" { #endif -#include "bsp_mcu_device_pn_cfg.h" -#include "bsp_mcu_device_cfg.h" -#include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" -#include "bsp_clock_cfg.h" - -#define BSP_MCU_GROUP_RA6M5 (1) -#define BSP_LOCO_HZ (32768) -#define BSP_MOCO_HZ (8000000) -#define BSP_SUB_CLOCK_HZ (32768) -#if BSP_CFG_HOCO_FREQUENCY == 0 -#define BSP_HOCO_HZ (16000000) -#elif BSP_CFG_HOCO_FREQUENCY == 1 - #define BSP_HOCO_HZ (18000000) -#elif BSP_CFG_HOCO_FREQUENCY == 2 - #define BSP_HOCO_HZ (20000000) -#else - #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" -#endif + #include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra6m5/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA6M5 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (32768) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) + #elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif -#define BSP_CFG_FLL_ENABLE (0) + #define BSP_CFG_FLL_ENABLE (0) -#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) -#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) -#if defined(_RA_TZ_SECURE) + #if defined(_RA_TZ_SECURE) #define BSP_TZ_SECURE_BUILD (1) #define BSP_TZ_NONSECURE_BUILD (0) #elif defined(_RA_TZ_NONSECURE) #define BSP_TZ_SECURE_BUILD (0) #define BSP_TZ_NONSECURE_BUILD (1) #else -#define BSP_TZ_SECURE_BUILD (0) -#define BSP_TZ_NONSECURE_BUILD (0) -#endif - -/* TrustZone Settings */ -#define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) -#define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) -#define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) - -/* CMSIS TrustZone Settings */ -#define SCB_CSR_AIRCR_INIT (1) -#define SCB_AIRCR_BFHFNMINS_VAL (0) -#define SCB_AIRCR_SYSRESETREQS_VAL (1) -#define SCB_AIRCR_PRIS_VAL (0) -#define TZ_FPU_NS_USAGE (1) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (0) + #endif + + /* TrustZone Settings */ + #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) + #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) + #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + + /* CMSIS TrustZone Settings */ + #define SCB_CSR_AIRCR_INIT (1) + #define SCB_AIRCR_BFHFNMINS_VAL (0) + #define SCB_AIRCR_SYSRESETREQS_VAL (1) + #define SCB_AIRCR_PRIS_VAL (0) + #define TZ_FPU_NS_USAGE (1) #ifndef SCB_NSACR_CP10_11_VAL -#define SCB_NSACR_CP10_11_VAL (3U) + #define SCB_NSACR_CP10_11_VAL (3U) #endif #ifndef FPU_FPCCR_TS_VAL -#define FPU_FPCCR_TS_VAL (1U) + #define FPU_FPCCR_TS_VAL (1U) #endif -#define FPU_FPCCR_CLRONRETS_VAL (1) + #define FPU_FPCCR_CLRONRETS_VAL (1) #ifndef FPU_FPCCR_CLRONRET_VAL -#define FPU_FPCCR_CLRONRET_VAL (1) + #define FPU_FPCCR_CLRONRET_VAL (1) #endif -/* The C-Cache line size that is configured during startup. */ + /* The C-Cache line size that is configured during startup. */ #ifndef BSP_CFG_C_CACHE_LINE_SIZE -#define BSP_CFG_C_CACHE_LINE_SIZE (1U) + #define BSP_CFG_C_CACHE_LINE_SIZE (1U) #endif -/* Type 1 Peripheral Security Attribution */ + /* Type 1 Peripheral Security Attribution */ -/* Peripheral Security Attribution Register (PSAR) Settings */ + /* Peripheral Security Attribution Register (PSAR) Settings */ #ifndef BSP_TZ_CFG_PSARB #define BSP_TZ_CFG_PSARB (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CAN1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* CAN0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ - (((1 > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ @@ -146,19 +146,19 @@ extern "C" { 0xfffffffc) /* Unused */ #endif -/* Type 2 Peripheral Security Attribution */ + /* Type 2 Peripheral Security Attribution */ -/* Security attribution for Cache registers. */ + /* Security attribution for Cache registers. */ #ifndef BSP_TZ_CFG_CSAR #define BSP_TZ_CFG_CSAR (0xFFFFFFFFU) #endif -/* Security attribution for RSTSRn registers. */ + /* Security attribution for RSTSRn registers. */ #ifndef BSP_TZ_CFG_RSTSAR #define BSP_TZ_CFG_RSTSAR (0xFFFFFFFFU) #endif -/* Security attribution for registers of LVD channels. */ + /* Security attribution for registers of LVD channels. */ #ifndef BSP_TZ_CFG_LVDSAR #define BSP_TZ_CFG_LVDSAR (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) | /* LVD Channel 1 */ \ @@ -166,16 +166,16 @@ extern "C" { 0xFFFFFFFCU) #endif -/* Security attribution for LPM registers. */ + /* Security attribution for LPM registers. */ #ifndef BSP_TZ_CFG_LPMSAR #define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? 0xFFFFFCEAU : 0xFFFFFFFFU) #endif -/* Deep Standby Interrupt Factor Security Attribution Register. */ + /* Deep Standby Interrupt Factor Security Attribution Register. */ #ifndef BSP_TZ_CFG_DPFSAR #define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0xF2E00000U : 0xFFFFFFFFU) #endif -/* Security attribution for CGC registers. */ + /* Security attribution for CGC registers. */ #ifndef BSP_TZ_CFG_CGFSAR #if BSP_CFG_CLOCKS_SECURE /* Protect all CGC registers from Non-secure write access. */ @@ -186,12 +186,12 @@ extern "C" { #endif #endif -/* Security attribution for Battery Backup registers. */ + /* Security attribution for Battery Backup registers. */ #ifndef BSP_TZ_CFG_BBFSAR #define BSP_TZ_CFG_BBFSAR (0x00FFFFFF) #endif -/* Security attribution for registers for IRQ channels. */ + /* Security attribution for registers for IRQ channels. */ #ifndef BSP_TZ_CFG_ICUSARA #define BSP_TZ_CFG_ICUSARA (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ @@ -213,12 +213,12 @@ extern "C" { 0xFFFF0000U) #endif -/* Security attribution for NMI registers. */ + /* Security attribution for NMI registers. */ #ifndef BSP_TZ_CFG_ICUSARB #define BSP_TZ_CFG_ICUSARB (0 | 0xFFFFFFFEU) /* Should match AIRCR.BFHFNMINS. */ #endif -/* Security attribution for registers for DMAC channels */ + /* Security attribution for registers for DMAC channels */ #ifndef BSP_TZ_CFG_ICUSARC #define BSP_TZ_CFG_ICUSARC (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ @@ -232,29 +232,29 @@ extern "C" { 0xFFFFFF00U) #endif -/* Security attribution registers for SELSR0. */ + /* Security attribution registers for SELSR0. */ #ifndef BSP_TZ_CFG_ICUSARD #define BSP_TZ_CFG_ICUSARD ((RA_NOT_DEFINED > 0) ? 0xFFFFFFFEU : 0xFFFFFFFFU) #endif -/* Security attribution registers for WUPEN0. */ + /* Security attribution registers for WUPEN0. */ #ifndef BSP_TZ_CFG_ICUSARE #define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0x04F2FFFFU : 0xFFFFFFFFU) #endif -/* Security attribution registers for WUPEN1. */ + /* Security attribution registers for WUPEN1. */ #ifndef BSP_TZ_CFG_ICUSARF #define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0xFFFFFFF8U : 0xFFFFFFFFU) #endif -/* Set DTCSTSAR if the Secure program uses the DTC. */ + /* Set DTCSTSAR if the Secure program uses the DTC. */ #if RA_NOT_DEFINED == RA_NOT_DEFINED -#define BSP_TZ_CFG_DTC_USED (0U) + #define BSP_TZ_CFG_DTC_USED (0U) #else #define BSP_TZ_CFG_DTC_USED (1U) #endif -/* Security attribution of FLWT and FCKMHZ registers. */ + /* Security attribution of FLWT and FCKMHZ registers. */ #ifndef BSP_TZ_CFG_FSAR /* If the CGC registers are only accessible in Secure mode, than there is no * reason for nonsecure applications to access FLWT and FCKMHZ. */ @@ -267,118 +267,123 @@ extern "C" { #endif #endif -/* Security attribution for SRAM registers. */ + /* Security attribution for SRAM registers. */ #ifndef BSP_TZ_CFG_SRAMSAR /* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access * SRAM0WTEN and therefore there is no reason to access PRCR2. */ -#define BSP_TZ_CFG_SRAMSAR (\ + #define BSP_TZ_CFG_SRAMSAR (\ 1 | \ ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 1U) : 0U) | \ 4 | \ 0xFFFFFFF8U) #endif -/* Security attribution for Standby RAM registers. */ + /* Security attribution for Standby RAM registers. */ #ifndef BSP_TZ_CFG_STBRAMSAR -#define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) + #define BSP_TZ_CFG_STBRAMSAR (0 | 0xFFFFFFF0U) #endif -/* Security attribution for the DMAC Bus Master MPU settings. */ + /* Security attribution for the DMAC Bus Master MPU settings. */ #ifndef BSP_TZ_CFG_MMPUSARA -/* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ -#define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) + /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ + #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_ICUSARC) #endif -/* Security Attribution Register A for BUS Control registers. */ + /* Security Attribution Register A for BUS Control registers. */ #ifndef BSP_TZ_CFG_BUSSARA -#define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) + #define BSP_TZ_CFG_BUSSARA (0xFFFFFFFFU) #endif -/* Security Attribution Register B for BUS Control registers. */ + /* Security Attribution Register B for BUS Control registers. */ #ifndef BSP_TZ_CFG_BUSSARB -#define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) + #define BSP_TZ_CFG_BUSSARB (0xFFFFFFFFU) #endif -/* Enable Uninitialized Non-Secure Application Fallback. */ + /* Enable Uninitialized Non-Secure Application Fallback. */ #ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK -#define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) + #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) #endif -#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) -#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) -#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) -#define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) -#define OFS_SEQ5 (1 << 28) | (1 << 30) -#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) -/* Option Function Select Register 1 Security Attribution */ + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + + /* Option Function Select Register 1 Security Attribution */ #ifndef BSP_CFG_ROM_REG_OFS1_SEL #if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) - #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U) | ((RA_NOT_DEFINED > 0) ? 0U : 0x7U)) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U | ((0U << 0U)) | ((0U << 2U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0x700U : 0U)) #else -#define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) + #define BSP_CFG_ROM_REG_OFS1_SEL (0xFFFFF8F8U) #endif #endif -#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) + #define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) -/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ -#define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) -/* Dual Mode Select Register */ + /* Dual Mode Select Register */ #ifndef BSP_CFG_ROM_REG_DUALSEL -#define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) + #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) #endif -/* Block Protection Register 0 */ + /* Block Protection Register 0 */ #ifndef BSP_CFG_ROM_REG_BPS0 -#define BSP_CFG_ROM_REG_BPS0 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS0 (~( 0U)) #endif -/* Block Protection Register 1 */ + /* Block Protection Register 1 */ #ifndef BSP_CFG_ROM_REG_BPS1 -#define BSP_CFG_ROM_REG_BPS1 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS1 (~( 0U)) #endif -/* Block Protection Register 2 */ + /* Block Protection Register 2 */ #ifndef BSP_CFG_ROM_REG_BPS2 -#define BSP_CFG_ROM_REG_BPS2 (~( 0U)) + #define BSP_CFG_ROM_REG_BPS2 (~( 0U)) #endif -/* Block Protection Register 3 */ + /* Block Protection Register 3 */ #ifndef BSP_CFG_ROM_REG_BPS3 -#define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_BPS3 (0xFFFFFFFFU) #endif -/* Permanent Block Protection Register 0 */ + /* Permanent Block Protection Register 0 */ #ifndef BSP_CFG_ROM_REG_PBPS0 -#define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) #endif -/* Permanent Block Protection Register 1 */ + /* Permanent Block Protection Register 1 */ #ifndef BSP_CFG_ROM_REG_PBPS1 -#define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) #endif -/* Permanent Block Protection Register 2 */ + /* Permanent Block Protection Register 2 */ #ifndef BSP_CFG_ROM_REG_PBPS2 -#define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) + #define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) #endif -/* Permanent Block Protection Register 3 */ + /* Permanent Block Protection Register 3 */ #ifndef BSP_CFG_ROM_REG_PBPS3 -#define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) + #define BSP_CFG_ROM_REG_PBPS3 (0xFFFFFFFFU) #endif -/* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL0 -#define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) + #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) #endif -/* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL1 -#define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) + #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) #endif -/* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL2 -#define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) + #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) #endif -/* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ + /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ #ifndef BSP_CFG_ROM_REG_BPS_SEL3 -#define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) + #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) +#endif + /* Security Attribution for Bank Select Register */ +#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL + #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU) #endif #ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT -#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) #endif #ifdef __cplusplus diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h index 0eb5e0516..91b9de11e 100644 --- a/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/bsp_clock_cfg.h @@ -1,37 +1,35 @@ /* generated configuration header file - do not edit */ #ifndef BSP_CLOCK_CFG_H_ #define BSP_CLOCK_CFG_H_ - -#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_SECURE (0) #define BSP_CFG_CLOCKS_OVERRIDE (0) -#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ -#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ -#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ -#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ -#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL(25U,0U)) /* PLL Mul x25.0 */ -#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ -#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ -#define BSP_CFG_PLL2_MUL (BSP_CLOCKS_PLL_MUL(20U,0U)) /* PLL2 Mul x20.0 */ -#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ -#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ -#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ -#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */ -#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ -#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ -#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ -#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ -#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ -#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ -#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ -#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ -#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ -#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ -#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ -#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ -#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ -#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */ -#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ -#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */ -#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ - +#define BSP_CFG_XTAL_HZ (24000000) /* XTAL 24000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_3) /* PLL Div /3 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(25U,0U) /* PLL Mul x25.0 */ +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL2 Src: XTAL */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ +#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(20U,0U) /* PLL2 Mul x20.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* UCLK Src: PLL2 */ +#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL2) /* U60CK Src: PLL2 */ +#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ +#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ +#define BSP_CFG_CECCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CECCLK Disabled */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ +#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB60_CLOCK_DIV_4) /* U60CK Div /4 */ +#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_1) /* OCTASPICLK Div /1 */ +#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_1) /* CANFDCLK Div /1 */ +#define BSP_CFG_CECCLK_DIV (BSP_CLOCKS_CEC_CLOCK_DIV_1) /* CECCLK Div /1 */ #endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/script/fsp.ld b/hw/bsp/ra/boards/portenta_c33/script/fsp.ld new file mode 100644 index 000000000..627ffe4d9 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/script/fsp.ld @@ -0,0 +1,766 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + +/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ +/* + XIP_SECONDARY_SLOT_IMAGE = 1; +*/ + +QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); +OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); +OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); + +/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ +__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); + +ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; +ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; +DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; +DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; +RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; +RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; +RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; +RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; + +OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; + +/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. + * Bootloader images do not configure option settings because they are owned by the bootloader. + * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ +__bl_FSP_BOOTABLE_IMAGE = 1; +__bln_FSP_BOOTABLE_IMAGE = 1; +PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); + +__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; +__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; +__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; +__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; +__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); +__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; + +XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; +FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : + XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : + FLASH_IMAGE_START; +LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : + DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : + FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; + +/* Define memory regions. */ +MEMORY +{ + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be DEFINED in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * __qspi_flash_start__ + * __qspi_flash_end__ + * __qspi_flash_code_size__ + * __qspi_region_max_size__ + * __qspi_region_start_address__ + * __qspi_region_end_address__ + * __ospi_device_0_start__ + * __ospi_device_0_end__ + * __ospi_device_0_code_size__ + * __ospi_device_0_region_max_size__ + * __ospi_device_0_region_start_address__ + * __ospi_device_0_region_end_address__ + * __ospi_device_1_start__ + * __ospi_device_1_end__ + * __ospi_device_1_code_size__ + * __ospi_device_1_region_max_size__ + * __ospi_device_1_region_start_address__ + * __ospi_device_1_region_end_address__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __tz_FLASH_S = ABSOLUTE(FLASH_START); + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + + /* Some devices have a gap of code flash between the vector table and ROM Registers. + * The flash gap section allows applications to place code and data in this section. */ + *(.flash_gap*) + + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Allocate flash write-boundary-aligned + * space for sce9 wrapped public keys for mcuboot if the module is used. + */ + KEEP(*(.mcuboot_sce9_key*)) + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) + { + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; + + __exidx_start = .; + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); + + /* Initialized DTCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) + { + /* Start of DTCM Secure Trustzone region. */ + __tz_DTCM_S = ABSOLUTE(DTCM_START); + + /* Initialized DTCM data start */ + __dtcm_data_start = .; + + KEEP(*(.dtcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; + /* Uninitialized DTCM data. */ + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : + { + /* Uninitialized DTCM data start */ + __dtcm_bss_start = .; + + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); + + /* Uninitialized DTCM data end */ + __dtcm_bss_end = .; + + /* + * Start of the DTCM Non-Secure Trustzone region. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. + */ + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); + } > DTCM + + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ + . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; + + KEEP(*(.ns_buffer*)) + } > RAM + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. + * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE + * memory region between TrustZone projects. */ + __tz_ID_CODE_N = __tz_ID_CODE_S; + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); + + .option_setting_ofs : + { + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_ofs2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; + } > OPTION_SETTING_OFS = 0xFF + + .option_setting_sas : + { + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; + } > OPTION_SETTING_SAS = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_ofs3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; +} diff --git a/hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld b/hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld new file mode 100644 index 000000000..74c648329 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/script/memory_regions.ld @@ -0,0 +1,25 @@ + + /* generated memory regions file - do not edit */ + RAM_START = 0x20000000; + RAM_LENGTH = 0x80000; + FLASH_START = 0x00000000; + FLASH_LENGTH = 0x200000; + DATA_FLASH_START = 0x08000000; + DATA_FLASH_LENGTH = 0x2000; + OPTION_SETTING_START = 0x0100A100; + OPTION_SETTING_LENGTH = 0x100; + OPTION_SETTING_S_START = 0x0100A200; + OPTION_SETTING_S_LENGTH = 0x100; + ID_CODE_START = 0x00000000; + ID_CODE_LENGTH = 0x0; + SDRAM_START = 0x80010000; + SDRAM_LENGTH = 0x0; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x4000000; + OSPI_DEVICE_0_START = 0x68000000; + OSPI_DEVICE_0_LENGTH = 0x8000000; + OSPI_DEVICE_1_START = 0x70000000; + OSPI_DEVICE_1_LENGTH = 0x10000000; + +/* Board has bootloader */ +FLASH_IMAGE_START = 0x10000; diff --git a/hw/bsp/ra/boards/portenta_c33/smart_configurator/configuration.xml b/hw/bsp/ra/boards/portenta_c33/smart_configurator/configuration.xml new file mode 100644 index 000000000..fcc9d711d --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/smart_configurator/configuration.xml @@ -0,0 +1,240 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Board Support Package Common Files + Renesas.RA.5.6.0.pack + + + I/O Port + Renesas.RA.5.6.0.pack + + + Arm CMSIS Version 6 - Core (M) + Arm.CMSIS6.6.1.0+fsp.5.6.0.pack + + + Custom Board Support Files + Renesas.RA_board_custom.5.6.0.pack + + + Board support package for R7FA6M5BH3CFC + Renesas.RA_mcu_ra6m5.5.6.0.pack + + + Board support package for RA6M5 + Renesas.RA_mcu_ra6m5.5.6.0.pack + + + Board support package for RA6M5 - FSP Data + Renesas.RA_mcu_ra6m5.5.6.0.pack + + + Board support package for RA6M5 - Events + Renesas.RA_mcu_ra6m5.5.6.0.pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hw/bsp/ra/linker/gcc/fsp.ld b/hw/bsp/ra/linker/gcc/fsp.ld deleted file mode 100644 index 453d46f24..000000000 --- a/hw/bsp/ra/linker/gcc/fsp.ld +++ /dev/null @@ -1,716 +0,0 @@ -/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ -/* - XIP_SECONDARY_SLOT_IMAGE = 1; -*/ - -QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); -OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); -OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); - -/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ -__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); - -ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; -ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; -DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; -DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; -NS_OFFSET_START = DEFINED(NS_OFFSET_START) ? NS_OFFSET_START : 0; -NS_IMAGE_OFFSET = DEFINED(PROJECT_NONSECURE) ? NS_OFFSET_START : 0; -RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; -RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; -RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; -RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; - -OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; - -/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. - * Bootloader images do not configure option settings because they are owned by the bootloader. - * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ -__bl_FSP_BOOTABLE_IMAGE = 1; -__bln_FSP_BOOTABLE_IMAGE = 1; -PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); -USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); - -__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : - FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; -__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; -__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; -__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START - FLASH_APPLICATION_NSC_LENGTH; -__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; -__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : - __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; -__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; -__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START; -__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : - FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : - FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; - -XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; -FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : - XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : - FLASH_IMAGE_START; -LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : - DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : - FLASH_LENGTH; - -/* Define memory regions. */ -MEMORY -{ - ITCM (rx) : ORIGIN = ITCM_START + NS_IMAGE_OFFSET, LENGTH = ITCM_LENGTH - DTCM (rwx) : ORIGIN = DTCM_START + NS_IMAGE_OFFSET, LENGTH = DTCM_LENGTH - FLASH (rx) : ORIGIN = FLASH_ORIGIN + NS_IMAGE_OFFSET, LENGTH = LIMITED_FLASH_LENGTH - RAM (rwx) : ORIGIN = RAM_START + NS_IMAGE_OFFSET, LENGTH = RAM_LENGTH - DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START + NS_IMAGE_OFFSET, LENGTH = DATA_FLASH_LENGTH - QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH - OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH - OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH - SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH - OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET, LENGTH = OPTION_SETTING_LENGTH - OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET, LENGTH = 0x18 - OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + NS_IMAGE_OFFSET + 0x34, LENGTH = OPTION_SETTING_LENGTH - 0x34 - OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START + NS_IMAGE_OFFSET, LENGTH = OPTION_SETTING_S_LENGTH - ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH -} - -/* Library configurations */ -GROUP(libgcc.a libc.a libm.a libnosys.a) - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be DEFINED in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __copy_table_start__ - * __copy_table_end__ - * __zero_table_start__ - * __zero_table_end__ - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - * __Vectors_End - * __Vectors_Size - * __qspi_flash_start__ - * __qspi_flash_end__ - * __qspi_flash_code_size__ - * __qspi_region_max_size__ - * __qspi_region_start_address__ - * __qspi_region_end_address__ - * __ospi_device_0_start__ - * __ospi_device_0_end__ - * __ospi_device_0_code_size__ - * __ospi_device_0_region_max_size__ - * __ospi_device_0_region_start_address__ - * __ospi_device_0_region_end_address__ - * __ospi_device_1_start__ - * __ospi_device_1_end__ - * __ospi_device_1_code_size__ - * __ospi_device_1_region_max_size__ - * __ospi_device_1_region_start_address__ - * __ospi_device_1_region_end_address__ - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - /* Initialized ITCM data. */ - .itcm_data : - { - /* Start of ITCM Secure Trustzone region. */ - __tz_ITCM_S = ABSOLUTE(ITCM_START); - - /* All ITCM data start */ - __itcm_data_start__ = .; - - KEEP(*(.itcm_data*)) - - /* All ITCM data end */ - __itcm_data_end__ = .; - - /* - * Start of the ITCM Non-Secure Trustzone region. - * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end__, 8192); - } > ITCM - - .text : - { - __tz_FLASH_S = ABSOLUTE(FLASH_START); - __ROM_Start = .; - - /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much - * space because ROM registers are at address 0x400 and there is very little space - * in between. */ - KEEP(*(.fixed_vectors*)) - KEEP(*(.application_vectors*)) - __Vectors_End = .; - - /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; - KEEP(*(.rom_registers*)) - - /* Reserving 0x100 bytes of space for ROM registers. */ - . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; - - /* Allocate flash write-boundary-aligned - * space for sce9 wrapped public keys for mcuboot if the module is used. - */ - . = ALIGN(128); - KEEP(*(.mcuboot_sce9_key*)) - - *(.text*) - - KEEP(*(.version)) - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - __usb_dev_descriptor_start_fs = .; - KEEP(*(.usb_device_desc_fs*)) - __usb_cfg_descriptor_start_fs = .; - KEEP(*(.usb_config_desc_fs*)) - __usb_interface_descriptor_start_fs = .; - KEEP(*(.usb_interface_desc_fs*)) - __usb_descriptor_end_fs = .; - __usb_dev_descriptor_start_hs = .; - KEEP(*(.usb_device_desc_hs*)) - __usb_cfg_descriptor_start_hs = .; - KEEP(*(.usb_config_desc_hs*)) - __usb_interface_descriptor_start_hs = .; - KEEP(*(.usb_interface_desc_hs*)) - __usb_descriptor_end_hs = .; - - KEEP(*(.eh_frame*)) - - __ROM_End = .; - } > FLASH = 0xFF - - __Vectors_Size = __Vectors_End - __Vectors; - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - /* To copy multiple ROM to RAM sections, - * uncomment .copy.table section and, - * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ - /* - .copy.table : - { - . = ALIGN(4); - __copy_table_start__ = .; - LONG (__etext) - LONG (__data_start__) - LONG (__data_end__ - __data_start__) - LONG (__etext2) - LONG (__data2_start__) - LONG (__data2_end__ - __data2_start__) - __copy_table_end__ = .; - } > FLASH - */ - - /* To clear multiple BSS sections, - * uncomment .zero.table section and, - * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ - /* - .zero.table : - { - . = ALIGN(4); - __zero_table_start__ = .; - LONG (__bss_start__) - LONG (__bss_end__ - __bss_start__) - LONG (__bss2_start__) - LONG (__bss2_end__ - __bss2_start__) - __zero_table_end__ = .; - } > FLASH - */ - - __etext = .; - - __tz_RAM_S = ORIGIN(RAM); - - /* If DTC is used, put the DTC vector table at the start of SRAM. - This avoids memory holes due to 1K alignment required by it. */ - .fsp_dtc_vector_table (NOLOAD) : - { - . = ORIGIN(RAM); - *(.fsp_dtc_vector_table) - } > RAM - - /* Initialized data section. */ - .data : - { - __data_start__ = .; - . = ALIGN(4); - - __Code_In_RAM_Start = .; - - KEEP(*(.code_in_ram*)) - __Code_In_RAM_End = .; - - *(vtable) - /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ - *(.data.*) - *(.data) - - . = ALIGN(4); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(4); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(4); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - KEEP(*(.jcr*)) - - . = ALIGN(4); - - /* All data end */ - __data_end__ = .; - - } > RAM AT > FLASH - - /* Start address of the initial values for .dtcm_data. */ - __dtcm_data_init_start = __etext + __data_end__ - __data_start__; - - /* Initialized DTCM data. */ - .dtcm_data : - { - /* Start of DTCM Secure Trustzone region. */ - __tz_DTCM_S = ABSOLUTE(DTCM_START); - - /* Initialized DTCM data start */ - __dtcm_data_start__ = .; - - KEEP(*(.dtcm_data*)) - - /* Initialized DTCM data end */ - __dtcm_data_end__ = .; - } > DTCM AT > FLASH - - /* Uninitialized DTCM data. */ - .dtcm_noinit (NOLOAD): - { - /* Uninitialized DTCM data start */ - __dtcm_noinit_start = .; - - KEEP(*(.dtcm_noinit*)) - - /* Uninitialized DTCM data end */ - __dtcm_noinit_end = .; - - /* - * Start of the DTCM Non-Secure Trustzone region. - * DTCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. - */ - __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_noinit_end, 8192); - } > DTCM - - /* TrustZone Secure Gateway Stubs Section. */ - - /* Some arithmetic is needed to eliminate unnecessary FILL for secure projects. */ - /* 1. Get the address to the next block after the .data section in FLASH. */ - DATA_END = LOADADDR(.data) + SIZEOF(.data); - /* 2. Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block after .data */ - SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(DATA_END, 1024); - /* 3. Manually specify the start location for .gnu.sgstubs */ - .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) - { - __tz_FLASH_C = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); - _start_sg = .; - *(.gnu.sgstubs*) - . = ALIGN(32); - _end_sg = .; - } > FLASH - - __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); - FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); - - /* QSPI_FLASH section to be downloaded via debugger */ - .qspi_flash : - { - __qspi_flash_start__ = .; - KEEP(*(.qspi_flash*)) - KEEP(*(.code_in_qspi*)) - __qspi_flash_end__ = .; - } > QSPI_FLASH - __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; - - /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ - __qspi_flash_code_addr__ = __etext + (__data_end__ - __data_start__); - .qspi_non_retentive : AT (__qspi_flash_code_addr__) - { - __qspi_non_retentive_start__ = .; - KEEP(*(.qspi_non_retentive*)) - __qspi_non_retentive_end__ = .; - } > QSPI_FLASH - __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; - - __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ - __qspi_region_start_address__ = __qspi_flash_start__; - __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; - - /* Support for OctaRAM */ - .OSPI_DEVICE_0_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_0_start__ = .; - *(.ospi_device_0_no_load*) - . = ALIGN(4); - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0_RAM - - .OSPI_DEVICE_1_NO_LOAD (NOLOAD): - { - . = ALIGN(4); - __ospi_device_1_start__ = .; - *(.ospi_device_1_no_load*) - . = ALIGN(4); - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1_RAM - - /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); - - /* OSPI_DEVICE_0 section to be downloaded via debugger */ - .OSPI_DEVICE_0 : - { - __ospi_device_0_start__ = .; - KEEP(*(.ospi_device_0*)) - KEEP(*(.code_in_ospi_device_0*)) - __ospi_device_0_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; - - /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_0_code_addr__ = __etext + (__data_end__ - __data_start__); - .ospi_device_0_non_retentive : AT (__ospi_device_0_code_addr__) - { - __ospi_device_0_non_retentive_start__ = .; - KEEP(*(.ospi_device_0_non_retentive*)) - __ospi_device_0_non_retentive_end__ = .; - } > OSPI_DEVICE_0 - __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; - - __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_0_region_start_address__ = __ospi_device_0_start__; - __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); - - /* OSPI_DEVICE_1 section to be downloaded via debugger */ - .OSPI_DEVICE_1 : - { - __ospi_device_1_start__ = .; - KEEP(*(.ospi_device_1*)) - KEEP(*(.code_in_ospi_device_1*)) - __ospi_device_1_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; - - /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ - __ospi_device_1_code_addr__ = __etext + (__data_end__ - __data_start__); - .ospi_device_1_non_retentive : AT (__ospi_device_1_code_addr__) - { - __ospi_device_1_non_retentive_start__ = .; - KEEP(*(.ospi_device_1_non_retentive*)) - __ospi_device_1_non_retentive_end__ = .; - } > OSPI_DEVICE_1 - __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; - - __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ - __ospi_device_1_region_start_address__ = __ospi_device_1_start__; - __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; - - /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ - __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; - - .noinit (NOLOAD): - { - . = ALIGN(4); - __noinit_start = .; - KEEP(*(.noinit*)) - . = ALIGN(8); - /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ - KEEP(*(.heap.*)) - __noinit_end = .; - } > RAM - - .bss : - { - . = ALIGN(4); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(4); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - . = ALIGN(8); - __HeapBase = .; - PROVIDE(end = .); - /* Place the STD heap here. */ - KEEP(*(.heap)) - __HeapLimit = .; - } > RAM - - /* Stacks are stored in this section. */ - .stack_dummy (NOLOAD): - { - . = ALIGN(8); - __StackLimit = .; - /* Main stack */ - KEEP(*(.stack)) - __StackTop = .; - /* Thread stacks */ - KEEP(*(.stack*)) - __StackTopAll = .; - } > RAM - - PROVIDE(__stack = __StackTopAll); - - /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used - at run time for things such as ThreadX memory pool allocations. */ - __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); - - /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. - * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_C = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); - - /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. - * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not - * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. - * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ - __tz_RAM_N = DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__tz_RAM_C, 8192); - - /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. - * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ - .ns_buffer (NOLOAD): - { - /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ - . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; - - KEEP(*(.ns_buffer*)) - } > RAM - - /* Data flash. */ - .data_flash : - { - . = ORIGIN(DATA_FLASH); - __tz_DATA_FLASH_S = .; - __Data_Flash_Start = .; - KEEP(*(.data_flash*)) - __Data_Flash_End = .; - - __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); - } > DATA_FLASH - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_S = ORIGIN(SDRAM); - - /* SDRAM */ - .sdram (NOLOAD): - { - __SDRAM_Start = .; - KEEP(*(.sdram*)) - KEEP(*(.frame*)) - __SDRAM_End = .; - } > SDRAM - - /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ - __tz_SDRAM_N = __SDRAM_End; - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ - __tz_ID_CODE_S = ORIGIN(ID_CODE); - - /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. - * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE - * memory region between TrustZone projects. */ - __tz_ID_CODE_N = __tz_ID_CODE_S; - - .id_code : - { - __ID_Code_Start = .; - KEEP(*(.id_code*)) - __ID_Code_End = .; - } > ID_CODE - - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); - - .option_setting_ofs : - { - __OPTION_SETTING_OFS_Start = .; - KEEP(*(.option_setting_ofs0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_ofs2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; - KEEP(*(.option_setting_dualsel)) - __OPTION_SETTING_OFS_End = .; - } > OPTION_SETTING_OFS = 0xFF - - .option_setting_sas : - { - __OPTION_SETTING_SAS_Start = .; - KEEP(*(.option_setting_sas)) - __OPTION_SETTING_SAS_End = .; - } > OPTION_SETTING_SAS = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); - - .option_setting_ns : - { - __OPTION_SETTING_NS_Start = .; - KEEP(*(.option_setting_ofs1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_ofs3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_banksel)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_bps3)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps0)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps1)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps2)) - . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; - KEEP(*(.option_setting_pbps3)) - __OPTION_SETTING_NS_End = .; - } > OPTION_SETTING = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); - - .option_setting_s : - { - __OPTION_SETTING_S_Start = .; - KEEP(*(.option_setting_ofs1_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sec)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_pbps_sec3)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs1_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_ofs3_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_banksel_sel)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel0)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel1)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel2)) - . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; - KEEP(*(.option_setting_bps_sel3)) - __OPTION_SETTING_S_End = .; - } > OPTION_SETTING_S = 0xFF - - /* Symbol required for RA Configuration tool. */ - __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; -} diff --git a/hw/bsp/ra/linker/gcc/ra2a1.ld b/hw/bsp/ra/linker/gcc/ra2a1.ld deleted file mode 100644 index 218acbb2a..000000000 --- a/hw/bsp/ra/linker/gcc/ra2a1.ld +++ /dev/null @@ -1,22 +0,0 @@ -RAM_START = 0x20000000; -RAM_LENGTH = 0x8000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x40000; -DATA_FLASH_START = 0x40100000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x00000000; -OPTION_SETTING_LENGTH = 0x0; -OPTION_SETTING_S_START = 0x80000000; -OPTION_SETTING_S_LENGTH = 0x0; -ID_CODE_START = 0x01010018; -ID_CODE_LENGTH = 0x20; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x0; -OSPI_DEVICE_0_START = 0x80020000; -OSPI_DEVICE_0_LENGTH = 0x0; -OSPI_DEVICE_1_START = 0x80030000; -OSPI_DEVICE_1_LENGTH = 0x0; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/linker/gcc/ra4m1.ld b/hw/bsp/ra/linker/gcc/ra4m1.ld deleted file mode 100644 index 218acbb2a..000000000 --- a/hw/bsp/ra/linker/gcc/ra4m1.ld +++ /dev/null @@ -1,22 +0,0 @@ -RAM_START = 0x20000000; -RAM_LENGTH = 0x8000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x40000; -DATA_FLASH_START = 0x40100000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x00000000; -OPTION_SETTING_LENGTH = 0x0; -OPTION_SETTING_S_START = 0x80000000; -OPTION_SETTING_S_LENGTH = 0x0; -ID_CODE_START = 0x01010018; -ID_CODE_LENGTH = 0x20; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x0; -OSPI_DEVICE_0_START = 0x80020000; -OSPI_DEVICE_0_LENGTH = 0x0; -OSPI_DEVICE_1_START = 0x80030000; -OSPI_DEVICE_1_LENGTH = 0x0; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/linker/gcc/ra4m3.ld b/hw/bsp/ra/linker/gcc/ra4m3.ld deleted file mode 100644 index 7b3a63fbe..000000000 --- a/hw/bsp/ra/linker/gcc/ra4m3.ld +++ /dev/null @@ -1,22 +0,0 @@ -RAM_START = 0x20000000; -RAM_LENGTH = 0x20000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x100000; -DATA_FLASH_START = 0x08000000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x0100A100; -OPTION_SETTING_LENGTH = 0x100; -OPTION_SETTING_S_START = 0x0100A200; -OPTION_SETTING_S_LENGTH = 0x100; -ID_CODE_START = 0x00000000; -ID_CODE_LENGTH = 0x0; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x4000000; -OSPI_DEVICE_0_START = 0x80020000; -OSPI_DEVICE_0_LENGTH = 0x0; -OSPI_DEVICE_1_START = 0x80030000; -OSPI_DEVICE_1_LENGTH = 0x0; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/linker/gcc/ra6m1.ld b/hw/bsp/ra/linker/gcc/ra6m1.ld deleted file mode 100644 index 91d27f74c..000000000 --- a/hw/bsp/ra/linker/gcc/ra6m1.ld +++ /dev/null @@ -1,22 +0,0 @@ -RAM_START = 0x1FFE0000; -RAM_LENGTH = 0x40000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x80000; -DATA_FLASH_START = 0x40100000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x00000000; -OPTION_SETTING_LENGTH = 0x0; -OPTION_SETTING_S_START = 0x80000000; -OPTION_SETTING_S_LENGTH = 0x0; -ID_CODE_START = 0x0100A150; -ID_CODE_LENGTH = 0x10; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x4000000; -OSPI_DEVICE_0_START = 0x80020000; -OSPI_DEVICE_0_LENGTH = 0x0; -OSPI_DEVICE_1_START = 0x80030000; -OSPI_DEVICE_1_LENGTH = 0x0; - -INCLUDE fsp.ld diff --git a/hw/bsp/ra/linker/gcc/ra6m5.ld b/hw/bsp/ra/linker/gcc/ra6m5.ld deleted file mode 100644 index af747fd9b..000000000 --- a/hw/bsp/ra/linker/gcc/ra6m5.ld +++ /dev/null @@ -1,22 +0,0 @@ -RAM_START = 0x20000000; -RAM_LENGTH = 0x80000; -FLASH_START = 0x00000000; -FLASH_LENGTH = 0x200000; -DATA_FLASH_START = 0x08000000; -DATA_FLASH_LENGTH = 0x2000; -OPTION_SETTING_START = 0x0100A100; -OPTION_SETTING_LENGTH = 0x100; -OPTION_SETTING_S_START = 0x0100A200; -OPTION_SETTING_S_LENGTH = 0x100; -ID_CODE_START = 0x00000000; -ID_CODE_LENGTH = 0x0; -SDRAM_START = 0x80010000; -SDRAM_LENGTH = 0x0; -QSPI_FLASH_START = 0x60000000; -QSPI_FLASH_LENGTH = 0x4000000; -OSPI_DEVICE_0_START = 0x68000000; -OSPI_DEVICE_0_LENGTH = 0x8000000; -OSPI_DEVICE_1_START = 0x70000000; -OSPI_DEVICE_1_LENGTH = 0x10000000; - -INCLUDE fsp.ld -- cgit v1.3.1 From 4b39ecc519735e5d4d2d9bfda7f24ae39faab077 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 13 Dec 2024 08:53:54 +0700 Subject: update make build for ra --- hw/bsp/ra/boards/portenta_c33/board.mk | 2 -- hw/bsp/ra/boards/uno_r4/board.mk | 2 -- hw/bsp/ra/family.cmake | 2 +- hw/bsp/ra/family.mk | 16 +++++++++------- 4 files changed, 10 insertions(+), 12 deletions(-) (limited to 'hw') diff --git a/hw/bsp/ra/boards/portenta_c33/board.mk b/hw/bsp/ra/boards/portenta_c33/board.mk index 6a5c2ffce..4da34306e 100644 --- a/hw/bsp/ra/boards/portenta_c33/board.mk +++ b/hw/bsp/ra/boards/portenta_c33/board.mk @@ -1,8 +1,6 @@ CPU_CORE = cortex-m33 MCU_VARIANT = ra6m5 -LD_FILE = ${BOARD_PATH}/${BOARD}.ld - # Port 1 is highspeed PORT ?= 1 diff --git a/hw/bsp/ra/boards/uno_r4/board.mk b/hw/bsp/ra/boards/uno_r4/board.mk index b7075eec0..f257c0000 100644 --- a/hw/bsp/ra/boards/uno_r4/board.mk +++ b/hw/bsp/ra/boards/uno_r4/board.mk @@ -1,8 +1,6 @@ CPU_CORE = cortex-m4 MCU_VARIANT = ra4m1 -LD_FILE = ${BOARD_PATH}/${BOARD}.ld - # For flash-jlink target JLINK_DEVICE = R7FA4M1AB diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 56c0487c1..e234c7b16 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -36,8 +36,8 @@ function(add_board_target BOARD_TARGET) ${FSP_RA}/src/bsp/mcu/all/bsp_sbrk.c ${FSP_RA}/src/bsp/mcu/all/bsp_security.c ${FSP_RA}/src/r_ioport/r_ioport.c - ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen/pin_data.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen/common_data.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD}/ra_gen/pin_data.c ) target_compile_options(${BOARD_TARGET} PUBLIC diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index 4447e8499..5c7305912 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -1,5 +1,3 @@ -DEPS_SUBMODULES += hw/mcu/renesas/fsp lib/CMSIS_5 - FSP_RA = hw/mcu/renesas/fsp/ra/fsp include $(TOP)/$(BOARD_PATH)/board.mk @@ -37,6 +35,8 @@ SRC_C += \ src/portable/renesas/rusb2/dcd_rusb2.c \ src/portable/renesas/rusb2/hcd_rusb2.c \ src/portable/renesas/rusb2/rusb2_common.c \ + ${BOARD_PATH}/ra_gen/common_data.c \ + ${BOARD_PATH}/ra_gen/pin_data.c \ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/startup.c \ $(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Source/system.c \ $(FSP_RA)/src/bsp/mcu/all/bsp_clocks.c \ @@ -53,10 +53,11 @@ SRC_C += \ $(FSP_RA)/src/r_ioport/r_ioport.c \ INC += \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/$(BOARD_PATH)/fsp_cfg \ - $(TOP)/$(BOARD_PATH)/fsp_cfg/bsp \ + $(TOP)/$(BOARD_PATH)/ra_cfg/fsp_cfg \ + $(TOP)/$(BOARD_PATH)/ra_cfg/fsp_cfg/bsp \ + $(TOP)/$(BOARD_PATH)/ra_gen \ + $(TOP)/lib/CMSIS_6/CMSIS/Core/Include \ $(TOP)/$(FSP_RA)/src/bsp/cmsis/Device/RENESAS/Include \ $(TOP)/$(FSP_RA)/inc \ $(TOP)/$(FSP_RA)/inc/api \ @@ -65,10 +66,11 @@ INC += \ $(TOP)/$(FSP_RA)/src/bsp/mcu/$(MCU_VARIANT) \ ifndef LD_FILE -LD_FILE = $(FAMILY_PATH)/linker/gcc/$(MCU_VARIANT).ld +LD_FILE = $(BOARD_PATH)/script/fsp.ld endif -LDFLAGS += -L$(TOP)/$(FAMILY_PATH)/linker/gcc +LDFLAGS += -L$(TOP)/$(BOARD_PATH)/script +LDFLAGS += -Wl,--defsym=end=__bss_end__ # For freeRTOS port source # hack to use the port provided by renesas -- cgit v1.3.1 From c79890c3597dabbe94340542a8c5c7cd168d8aa0 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 13 Dec 2024 12:50:51 +0700 Subject: ra8m1_ek led and button works --- hw/bsp/ra/boards/ra6m5_ek/board.cmake | 2 +- hw/bsp/ra/boards/ra8m1_ek/board.cmake | 8 + hw/bsp/ra/boards/ra8m1_ek/board.h | 42 ++ .../boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h | 62 ++ .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h | 5 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h | 11 + .../ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h | 526 +++++++++++++ .../ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h | 127 ++++ .../boards/ra8m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h | 13 + hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h | 56 ++ hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.c | 11 + hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.h | 20 + hw/bsp/ra/boards/ra8m1_ek/ra_gen/pin_data.c | 275 +++++++ hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld | 820 +++++++++++++++++++++ hw/bsp/ra/boards/ra8m1_ek/script/memory_regions.ld | 30 + .../ra8m1_ek/smart_configurator/configuration.xml | 6 +- 16 files changed, 2010 insertions(+), 4 deletions(-) create mode 100644 hw/bsp/ra/boards/ra8m1_ek/board.cmake create mode 100644 hw/bsp/ra/boards/ra8m1_ek/board.h create mode 100644 hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h create mode 100644 hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h create mode 100644 hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h create mode 100644 hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h create mode 100644 hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h create mode 100644 hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h create mode 100644 hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h create mode 100644 hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.c create mode 100644 hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.h create mode 100644 hw/bsp/ra/boards/ra8m1_ek/ra_gen/pin_data.c create mode 100644 hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld create mode 100644 hw/bsp/ra/boards/ra8m1_ek/script/memory_regions.ld (limited to 'hw') diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake index 2adf6e744..a8220c9c7 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake +++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake @@ -2,7 +2,7 @@ set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra6m5) set(JLINK_DEVICE R7FA6M5BH) -set(JLINK_OPTION "-USB 000831915224") +#set(JLINK_OPTION "-USB 000831915224") # Device port default to PORT1 Highspeed if (NOT DEFINED PORT) diff --git a/hw/bsp/ra/boards/ra8m1_ek/board.cmake b/hw/bsp/ra/boards/ra8m1_ek/board.cmake new file mode 100644 index 000000000..ae5d1d5bb --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/board.cmake @@ -0,0 +1,8 @@ +set(CMAKE_SYSTEM_PROCESSOR cortex-m85 CACHE INTERNAL "System Processor") +set(MCU_VARIANT ra8m1) + +set(JLINK_DEVICE R7FA8M1AH) +#set(JLINK_OPTION "-USB 001083115236") + +function(update_board TARGET) +endfunction() diff --git a/hw/bsp/ra/boards/ra8m1_ek/board.h b/hw/bsp/ra/boards/ra8m1_ek/board.h new file mode 100644 index 000000000..33dda99b4 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/board.h @@ -0,0 +1,42 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2023 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#define LED_STATE_ON 1 +#define BUTTON_STATE_ACTIVE 0 + + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..90afbdef3 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,62 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#ifdef __cplusplus + extern "C" { + #endif + + #include "bsp_clock_cfg.h" + #include "bsp_mcu_family_cfg.h" + #include "board_cfg.h" + #define RA_NOT_DEFINED 0 + #ifndef BSP_CFG_RTOS + #if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (2) + #elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) + #define BSP_CFG_RTOS (1) + #else + #define BSP_CFG_RTOS (0) + #endif + #endif + #ifndef BSP_CFG_RTC_USED + #define BSP_CFG_RTC_USED (RA_NOT_DEFINED) + #endif + #undef RA_NOT_DEFINED + #if defined(_RA_BOOT_IMAGE) + #define BSP_CFG_BOOT_IMAGE (1) + #endif + #define BSP_CFG_MCU_VCC_MV (3300) + #define BSP_CFG_STACK_MAIN_BYTES (0x1000) + #define BSP_CFG_HEAP_BYTES (0x1000) + #define BSP_CFG_PARAM_CHECKING_ENABLE (0) + #define BSP_CFG_ASSERT (0) + #define BSP_CFG_ERROR_LOG (0) + + #define BSP_CFG_PFS_PROTECT ((1)) + + #define BSP_CFG_C_RUNTIME_INIT ((1)) + #define BSP_CFG_EARLY_INIT ((0)) + + #define BSP_CFG_STARTUP_CLOCK_REG_NOT_RESET ((0)) + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED + #define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) + #endif + + #ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE + #define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE + #define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED + #define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) + #endif + #ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS + #define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 + #endif + + #ifdef __cplusplus + } + #endif +#endif /* BSP_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000..92e7ddcdb --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (8) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..a22da075d --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,11 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA8M1AHECBD + #define BSP_MCU_FEATURE_SET ('A') + #define BSP_ROM_SIZE_BYTES (2064384) + #define BSP_RAM_SIZE_BYTES (917504) + #define BSP_DATA_FLASH_SIZE_BYTES (12288) + #define BSP_PACKAGE_BGA + #define BSP_PACKAGE_PINS (224) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..94f09c61f --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,526 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#include "bsp_mcu_device_pn_cfg.h" + #include "bsp_mcu_device_cfg.h" + #include "../../../ra/fsp/src/bsp/mcu/ra8m1/bsp_override.h" + #include "../../../ra/fsp/src/bsp/mcu/ra8m1/bsp_mcu_info.h" + #include "bsp_clock_cfg.h" + #define BSP_MCU_GROUP_RA8M1 (1) + #define BSP_LOCO_HZ (32768) + #define BSP_MOCO_HZ (8000000) + #define BSP_SUB_CLOCK_HZ (0) + #if BSP_CFG_HOCO_FREQUENCY == 0 + #define BSP_HOCO_HZ (16000000) + #elif BSP_CFG_HOCO_FREQUENCY == 1 + #define BSP_HOCO_HZ (18000000) + #elif BSP_CFG_HOCO_FREQUENCY == 2 + #define BSP_HOCO_HZ (20000000) + #elif BSP_CFG_HOCO_FREQUENCY == 4 + #define BSP_HOCO_HZ (32000000) + #elif BSP_CFG_HOCO_FREQUENCY == 7 + #define BSP_HOCO_HZ (48000000) + #else + #error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" + #endif + + #define BSP_CFG_FLL_ENABLE (0) + + #define BSP_CFG_CLOCK_SETTLING_DELAY_ENABLE (1) + #define BSP_CFG_SLEEP_MODE_DELAY_ENABLE (1) + #define BSP_CFG_MSTP_CHANGE_DELAY_ENABLE (1) + #define BSP_CFG_RTOS_IDLE_SLEEP (0) + #define BSP_CFG_CLOCK_SETTLING_DELAY_US (150) + + #if defined(BSP_PACKAGE_LQFP) && (BSP_PACKAGE_PINS == 100) + #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (180000000U) + #elif defined(BSP_PACKAGE_LQFP) + #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (200000000U) + #else + #define BSP_MAX_CLOCK_CHANGE_THRESHOLD (240000000U) + #endif + + #define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) + #define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) + #define BSP_CFG_INLINE_IRQ_FUNCTIONS (1) + + #if defined(_RA_TZ_SECURE) + #define BSP_TZ_SECURE_BUILD (1) + #define BSP_TZ_NONSECURE_BUILD (0) + #elif defined(_RA_TZ_NONSECURE) + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (1) + #else + #define BSP_TZ_SECURE_BUILD (0) + #define BSP_TZ_NONSECURE_BUILD (0) + #endif + + /* TrustZone Settings */ + #define BSP_TZ_CFG_INIT_SECURE_ONLY (BSP_CFG_CLOCKS_SECURE || (!BSP_CFG_CLOCKS_OVERRIDE)) + #define BSP_TZ_CFG_SKIP_INIT (BSP_TZ_NONSECURE_BUILD && BSP_TZ_CFG_INIT_SECURE_ONLY) + #define BSP_TZ_CFG_EXCEPTION_RESPONSE (0) + + /* CMSIS TrustZone Settings */ + #define SCB_CSR_AIRCR_INIT (1) + #define SCB_AIRCR_BFHFNMINS_VAL (0) + #define SCB_AIRCR_SYSRESETREQS_VAL (1) + #define SCB_AIRCR_PRIS_VAL (0) + #define TZ_FPU_NS_USAGE (1) +#ifndef SCB_NSACR_CP10_11_VAL + #define SCB_NSACR_CP10_11_VAL (3U) +#endif + +#ifndef FPU_FPCCR_TS_VAL + #define FPU_FPCCR_TS_VAL (1U) +#endif + #define FPU_FPCCR_CLRONRETS_VAL (1) + +#ifndef FPU_FPCCR_CLRONRET_VAL + #define FPU_FPCCR_CLRONRET_VAL (1) +#endif + + /* Type 1 Peripheral Security Attribution */ + + /* Peripheral Security Attribution Register (PSAR) Settings */ +#ifndef BSP_TZ_CFG_PSARB +#define BSP_TZ_CFG_PSARB (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* I3C */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* IIC1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* USBHS */ | \ + (1 << 15) /* ETHERC/EDMAC */ | \ + (1 << 16) /* OSPI */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* SCI4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* SCI3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* SCI2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* SCI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* SCI0 */) +#endif +#ifndef BSP_TZ_CFG_PSARC +#define BSP_TZ_CFG_PSARC (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* CAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* CRC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7) /* SSIE1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* SSIE0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* SDHI1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* SDHI0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* DOC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* CEU */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* CANFD1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* CANFD0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* RSIP-E51A */) +#endif +#ifndef BSP_TZ_CFG_PSARD +#define BSP_TZ_CFG_PSARD (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4) /* AGT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5) /* AGT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* POEG3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12) /* POEG2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13) /* POEG1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14) /* POEG0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15) /* ADC121 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 16) /* ADC120 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* DAC120 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* TSN */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* ACMPHS1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* ACMPHS0 */) +#endif +#ifndef BSP_TZ_CFG_PSARE +#define BSP_TZ_CFG_PSARE (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* WDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2) /* IWDT */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3) /* RTC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8) /* ULPT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* ULPT0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* GPT13 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* GPT12 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 20) /* GPT11 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 21) /* GPT10 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* GPT9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* GPT8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 24) /* GPT7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 25) /* GPT6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 26) /* GPT5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 27) /* GPT4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 28) /* GPT3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 29) /* GPT2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 30) /* GPT1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* GPT0 */) +#endif +#ifndef BSP_TZ_CFG_MSSAR +#define BSP_TZ_CFG_MSSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* DTC_DMAC */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 31) /* ELC */) +#endif + + /* Type 2 Peripheral Security Attribution */ + + /* Security attribution for RSTSRn registers. */ +#ifndef BSP_TZ_CFG_RSTSAR +#define BSP_TZ_CFG_RSTSAR (0x00000007U) +#endif + + /* Security attribution for registers of LVD channels. */ +#ifndef BSP_TZ_CFG_LVDSAR + /* The LVD driver needs to access both channels. This means that the security attribution for both channels must be the same. */ +#if (RA_NOT_DEFINED > 0) || (RA_NOT_DEFINED > 0) +#define BSP_TZ_CFG_LVDSAR (0U) +#else +#define BSP_TZ_CFG_LVDSAR (3U) +#endif +#endif + + /* Security attribution for LPM registers. + * - OPCCR based on clock security. + * - Set remaining registers based on LPM security. + */ +#ifndef BSP_TZ_CFG_LPMSAR +#define BSP_TZ_CFG_LPMSAR ((RA_NOT_DEFINED > 0) ? BSP_CFG_CLOCKS_SECURE == 0 : (\ + 0x002E0106U | \ + (BSP_CFG_CLOCKS_SECURE == 0))) +#endif + /* Deep Standby Interrupt Factor Security Attribution Register. */ +#ifndef BSP_TZ_CFG_DPFSAR +#define BSP_TZ_CFG_DPFSAR ((RA_NOT_DEFINED > 0) ? 0U : 0xAF1FFFFFU) +#endif + /* RAM Standby Control Security Attribution Register. */ +#ifndef BSP_TZ_CFG_RSCSAR +#define BSP_TZ_CFG_RSCSAR ((RA_NOT_DEFINED > 0) ? 0U : 0x00037FFFU) +#endif + + /* Security attribution for CGC registers. */ +#ifndef BSP_TZ_CFG_CGFSAR +#if BSP_CFG_CLOCKS_SECURE +/* Protect all CGC registers from Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0U) +#else +/* Allow Secure and Non-secure write access. */ +#define BSP_TZ_CFG_CGFSAR (0x047F3BFDU) +#endif +#endif + + /* Security attribution for Battery Backup registers. */ +#ifndef BSP_TZ_CFG_BBFSAR +#if 0 +#define BSP_TZ_CFG_BBFSAR (0U) +#else +#define BSP_TZ_CFG_BBFSAR (0x1FU) +#endif +#endif + + /* Security attribution for Battery Backup registers (VBTBKRn). */ +#ifndef BSP_TZ_CFG_VBRSABAR +#if 0 +#define BSP_TZ_CFG_VBRSABAR (0xFFE0) +#else +#define BSP_TZ_CFG_VBRSABAR (0xED00) +#endif +#endif + + /* Security attribution for registers for IRQ channels. */ +#ifndef BSP_TZ_CFG_ICUSARA +#define BSP_TZ_CFG_ICUSARA (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* External IRQ0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* External IRQ1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* External IRQ2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* External IRQ3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* External IRQ4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* External IRQ5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* External IRQ6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* External IRQ7 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 8U) /* External IRQ8 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9U) /* External IRQ9 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 10U) /* External IRQ10 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11U) /* External IRQ11 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 12U) /* External IRQ12 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 13U) /* External IRQ13 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 14U) /* External IRQ14 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 15U) /* External IRQ15 */) +#endif + + /* Security attribution for NMI registers. */ +#ifndef BSP_TZ_CFG_ICUSARB +#define BSP_TZ_CFG_ICUSARB (0 | 0U) /* Should match AIRCR.BFHFNMINS. */ +#endif + + /* Security attribution for registers for DMAC channels */ +#ifndef BSP_TZ_CFG_DMACCHSAR +#define BSP_TZ_CFG_DMACCHSAR (\ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0U) /* DMAC Channel 0 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1U) /* DMAC Channel 1 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 2U) /* DMAC Channel 2 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 3U) /* DMAC Channel 3 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 4U) /* DMAC Channel 4 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 5U) /* DMAC Channel 5 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 6U) /* DMAC Channel 6 */ | \ + (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 7U) /* DMAC Channel 7 */) +#endif + + /* Security attribution registers for WUPEN0. */ +#ifndef BSP_TZ_CFG_ICUSARE +#define BSP_TZ_CFG_ICUSARE ((RA_NOT_DEFINED > 0) ? 0U : 0xFF1D0000U) +#endif + + /* Security attribution registers for WUPEN1. */ +#ifndef BSP_TZ_CFG_ICUSARF +#define BSP_TZ_CFG_ICUSARF ((RA_NOT_DEFINED > 0) ? 0U : 0x00007F08U) +#endif + + /* Trusted Event Route Control Register for IELSR, DMAC.DELSR and ELC.ELSR. Note that currently Trusted Event Route Control is not supported. */ +#ifndef BSP_TZ_CFG_TEVTRCR +#define BSP_TZ_CFG_TEVTRCR (0) +#endif + + /* Security attribution register for ELCR, ELSEGR0, ELSEGR1 Security Attribution. */ +#ifndef BSP_TZ_CFG_ELCSARA + #define BSP_TZ_CFG_ELCSARA (0x00000007U) +#endif + + /* Set DTCSTSAR if the Secure program uses the DTC. */ +#if RA_NOT_DEFINED == RA_NOT_DEFINED + #define BSP_TZ_CFG_DTC_USED (0U) +#else + #define BSP_TZ_CFG_DTC_USED (1U) +#endif + + /* Security attribution of FLWT and FCKMHZ registers. */ +#ifndef BSP_TZ_CFG_FSAR +/* If the CGC registers are only accessible in Secure mode, than there is no + * reason for nonsecure applications to access FLWT and FCKMHZ. */ +#define BSP_TZ_CFG_FSAR (\ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 0) : 0U) | /* FLWTSA */\ + ((RA_NOT_DEFINED) > 0 ? 0U: (1U << 1)) | /* FCACHESA */\ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8) : 0U) | /* FCKMHZSA */ \ + ((RA_NOT_DEFINED) > 0 ? 0U : (1U << 9U)) | /* FACICMISA */\ + ((RA_NOT_DEFINED) > 0 ? 0U: (1U << 10U)) /* FACICMRSA */) +#endif + + /* Security attribution for SRAM registers. */ +#ifndef BSP_TZ_CFG_SRAMSAR +/* If the CGC registers are only accessible in Secure mode, than there is no reason for Non Secure applications to access + * SRAM0WTEN and therefore there is no reason to access PRCR2. */ + #define BSP_TZ_CFG_SRAMSAR (\ + ((1U) << 0U) | /* SRAMSA0 */\ + ((1U) << 1U) | /* SRAMSA1 */\ + ((1U) << 7U) | /* STBRAMSA */\ + ((BSP_CFG_CLOCKS_SECURE == 0) ? (1U << 8U) : 0U) /* SRAMWTSA */) +#endif + + /* Security attribution for the DMAC Bus Master MPU settings. */ +#ifndef BSP_TZ_CFG_MMPUSARA + /* The DMAC Bus Master MPU settings should align with the DMAC channel settings. */ + #define BSP_TZ_CFG_MMPUSARA (BSP_TZ_CFG_DMACCHSAR) +#endif + + /* Security Attribution Register A for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARA + #define BSP_TZ_CFG_BUSSARA (1U) +#endif + /* Security Attribution Register B for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARB + #define BSP_TZ_CFG_BUSSARB (1U) +#endif + /* Security Attribution Register C for BUS Control registers. */ +#ifndef BSP_TZ_CFG_BUSSARC + #define BSP_TZ_CFG_BUSSARC (1U) +#endif + + /* Enable Uninitialized Non-Secure Application Fallback. */ +#ifndef BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK + #define BSP_TZ_CFG_NON_SECURE_APPLICATION_FALLBACK (1U) +#endif + + + #define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) + #define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) + #define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) + #define OFS_SEQ4 (3 << 18) |(15 << 20) | (3 << 24) | (3 << 26) + #define OFS_SEQ5 (1 << 28) | (1 << 30) + #define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) + + #define BSP_CFG_ROM_REG_OFS2 ((1 << 0) | 0xFFFFFFFEU) + + /* Option Function Select Register 1 Security Attribution */ +#ifndef BSP_CFG_ROM_REG_OFS1_SEL +#if defined(_RA_TZ_SECURE) || defined(_RA_TZ_NONSECURE) + #define BSP_CFG_ROM_REG_OFS1_SEL (0x00000000U | ((0U << 0U)) | ((0U << 3U)) | ((0U << 5U)) | ((BSP_CFG_CLOCKS_SECURE == 0) ? 0xF00U : 0U) | ((0U << 24U)) | ((0U << 25U))) +#else + #define BSP_CFG_ROM_REG_OFS1_SEL (0x00000000U) +#endif +#endif + #define BSP_CFG_ROM_REG_OFS1_INITECCEN (0 << 25) + #define BSP_CFG_ROM_REG_OFS1 (0xFCFFFED0 | (1 << 3) | (7) | (1 << 5) | (1 << 8) | (1 << 24) | (BSP_CFG_ROM_REG_OFS1_INITECCEN)) + + /* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ + #define BSP_PRV_IELS_ENUM(vector) (ELC_ ## vector) + + /* Dual Mode Select Register */ +#ifndef BSP_CFG_ROM_REG_DUALSEL + #define BSP_CFG_ROM_REG_DUALSEL (0xFFFFFFF8U | (0x7U)) +#endif + + /* Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_BPS0 + #define BSP_CFG_ROM_REG_BPS0 (~( 0U)) +#endif + /* Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_BPS1 + #define BSP_CFG_ROM_REG_BPS1 (~( 0U)) +#endif + /* Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_BPS2 + #define BSP_CFG_ROM_REG_BPS2 (~( 0U)) +#endif + /* Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_BPS3 + #define BSP_CFG_ROM_REG_BPS3 (~( 0U)) +#endif + /* Permanent Block Protection Register 0 */ +#ifndef BSP_CFG_ROM_REG_PBPS0 + #define BSP_CFG_ROM_REG_PBPS0 (~( 0U)) +#endif + /* Permanent Block Protection Register 1 */ +#ifndef BSP_CFG_ROM_REG_PBPS1 + #define BSP_CFG_ROM_REG_PBPS1 (~( 0U)) +#endif + /* Permanent Block Protection Register 2 */ +#ifndef BSP_CFG_ROM_REG_PBPS2 + #define BSP_CFG_ROM_REG_PBPS2 (~( 0U)) +#endif + /* Permanent Block Protection Register 3 */ +#ifndef BSP_CFG_ROM_REG_PBPS3 + #define BSP_CFG_ROM_REG_PBPS3 (~( 0U)) +#endif + /* Security Attribution for Block Protection Register 0 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL0 + #define BSP_CFG_ROM_REG_BPS_SEL0 (BSP_CFG_ROM_REG_BPS0 & BSP_CFG_ROM_REG_PBPS0) +#endif + /* Security Attribution for Block Protection Register 1 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL1 + #define BSP_CFG_ROM_REG_BPS_SEL1 (BSP_CFG_ROM_REG_BPS1 & BSP_CFG_ROM_REG_PBPS1) +#endif + /* Security Attribution for Block Protection Register 2 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL2 + #define BSP_CFG_ROM_REG_BPS_SEL2 (BSP_CFG_ROM_REG_BPS2 & BSP_CFG_ROM_REG_PBPS2) +#endif + /* Security Attribution for Block Protection Register 3 (If any blocks are marked as protected in the secure application, then mark them as secure) */ +#ifndef BSP_CFG_ROM_REG_BPS_SEL3 + #define BSP_CFG_ROM_REG_BPS_SEL3 (BSP_CFG_ROM_REG_BPS3 & BSP_CFG_ROM_REG_PBPS3) +#endif + /* Security Attribution for Bank Select Register */ +#ifndef BSP_CFG_ROM_REG_BANKSEL_SEL + #define BSP_CFG_ROM_REG_BANKSEL_SEL (0xFFFFFFFFU) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT + #define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif + + /* FSBL Control Register 0 */ +#ifndef BSP_CFG_ROM_REG_FSBLCTRL0 +#define BSP_CFG_ROM_REG_FSBLCTRL0 ( \ + (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLEN_Pos) | \ + (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPSW_Pos) | \ + (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLSKIPDS_Pos) | \ + (7 << R_OFS_DATAFLASH_FSBLCTRL0_FSBLCLK_Pos) | \ + 0xFFFFF000) +#endif + + /* FSBL Control Register 1 */ +#ifndef BSP_CFG_ROM_REG_FSBLCTRL1 +#define BSP_CFG_ROM_REG_FSBLCTRL1 ( \ + (3 << R_OFS_DATAFLASH_FSBLCTRL1_FSBLEXMD_Pos) | \ + 0xFFFFFFFC) +#endif + + /* FSBL Control Register 2 */ +#ifndef BSP_CFG_ROM_REG_FSBLCTRL2 +#define BSP_CFG_ROM_REG_FSBLCTRL2 ( \ + (15 << R_OFS_DATAFLASH_FSBLCTRL2_PORTPN_Pos) | \ + (0x1F << R_OFS_DATAFLASH_FSBLCTRL2_PORTGN_Pos) | \ + 0xFFFFFE00) +#endif + + /* Start Address of Code Certificate Register 0 */ +#ifndef BSP_CFG_ROM_REG_SACC0 +#define BSP_CFG_ROM_REG_SACC0 (0xFFFFFFFF) +#endif + + /* Start Address of Code Certificate Register 1 */ +#ifndef BSP_CFG_ROM_REG_SACC1 +#define BSP_CFG_ROM_REG_SACC1 (0xFFFFFFFF) +#endif + + /* Start Address of Measurement Report Register */ +#ifndef BSP_CFG_ROM_REG_SAMR +#define BSP_CFG_ROM_REG_SAMR (0xFFFFFFFF) +#endif + +#ifndef BSP_CFG_DCACHE_ENABLED +#define BSP_CFG_DCACHE_ENABLED (0) +#endif + + +#ifndef BSP_CFG_SDRAM_ENABLED + #define BSP_CFG_SDRAM_ENABLED (0) +#endif + +#ifndef BSP_CFG_SDRAM_TRAS + #define BSP_CFG_SDRAM_TRAS (6) +#endif + +#ifndef BSP_CFG_SDRAM_TRCD + #define BSP_CFG_SDRAM_TRCD (3) +#endif + +#ifndef BSP_CFG_SDRAM_TRP + #define BSP_CFG_SDRAM_TRP (3) +#endif + +#ifndef BSP_CFG_SDRAM_TWR + #define BSP_CFG_SDRAM_TWR (2) +#endif + +#ifndef BSP_CFG_SDRAM_TCL + #define BSP_CFG_SDRAM_TCL (3) +#endif + +#ifndef BSP_CFG_SDRAM_TRFC + #define BSP_CFG_SDRAM_TRFC (937) +#endif + +#ifndef BSP_CFG_SDRAM_TREFW + #define BSP_CFG_SDRAM_TREFW (8) +#endif + +#ifndef BSP_CFG_SDRAM_INIT_ARFI + #define BSP_CFG_SDRAM_INIT_ARFI (10) +#endif + +#ifndef BSP_CFG_SDRAM_INIT_ARFC + #define BSP_CFG_SDRAM_INIT_ARFC (8) +#endif + +#ifndef BSP_CFG_SDRAM_INIT_PRC + #define BSP_CFG_SDRAM_INIT_PRC (3) +#endif + +#ifndef BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT + #define BSP_CFG_SDRAM_MULTIPLEX_ADDR_SHIFT (1) +#endif + +#ifndef BSP_CFG_SDRAM_ENDIAN_MODE + #define BSP_CFG_SDRAM_ENDIAN_MODE (0) +#endif + +#ifndef BSP_CFG_SDRAM_ACCESS_MODE + #define BSP_CFG_SDRAM_ACCESS_MODE (1) +#endif + +#ifndef BSP_CFG_SDRAM_BUS_WIDTH + #define BSP_CFG_SDRAM_BUS_WIDTH (0) +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000..883363437 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,127 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define ENET_RMII_INT (BSP_IO_PORT_00_PIN_00) +#define ARDUINO_A3 (BSP_IO_PORT_00_PIN_01) +#define GROVE2_AN102 (BSP_IO_PORT_00_PIN_02) +#define ARDUINO_A1 (BSP_IO_PORT_00_PIN_03) +#define ARDUINO_A0_MIKROBUS_AN000 (BSP_IO_PORT_00_PIN_04) +#define GROVE2_AN001 (BSP_IO_PORT_00_PIN_05) +#define PMOD1_IRQ11 (BSP_IO_PORT_00_PIN_06) +#define ARDUINO_A004 (BSP_IO_PORT_00_PIN_07) +#define USER_S2 (BSP_IO_PORT_00_PIN_08) +#define SW1 (BSP_IO_PORT_00_PIN_09) +#define MIKROBUS_IRQ14 (BSP_IO_PORT_00_PIN_10) +#define ARDUINO_A4 (BSP_IO_PORT_00_PIN_14) +#define ARDUINO_A5 (BSP_IO_PORT_00_PIN_15) +#define OSPI_DQ0 (BSP_IO_PORT_01_PIN_00) +#define OSPI_DQ3 (BSP_IO_PORT_01_PIN_01) +#define OSPI_DQ4 (BSP_IO_PORT_01_PIN_02) +#define OSPI_DQ2 (BSP_IO_PORT_01_PIN_03) +#define OSPI_CS (BSP_IO_PORT_01_PIN_04) +#define OSPI_INT (BSP_IO_PORT_01_PIN_05) +#define OSPI_RESET (BSP_IO_PORT_01_PIN_06) +#define LED3 (BSP_IO_PORT_01_PIN_07) +#define ETH_A_RMII_RMII_RXDV (BSP_IO_PORT_01_PIN_12) +#define ETH_A_LINKSTA (BSP_IO_PORT_01_PIN_14) +#define MPLX_CTRL (BSP_IO_PORT_01_PIN_15) +#define NMI (BSP_IO_PORT_02_PIN_00) +#define MD (BSP_IO_PORT_02_PIN_01) +#define CAN_STB (BSP_IO_PORT_02_PIN_07) +#define TDI (BSP_IO_PORT_02_PIN_08) +#define TDO (BSP_IO_PORT_02_PIN_09) +#define SWDIO (BSP_IO_PORT_02_PIN_10) +#define SWCLK (BSP_IO_PORT_02_PIN_11) +#define EXTAL (BSP_IO_PORT_02_PIN_12) +#define XTAL (BSP_IO_PORT_02_PIN_13) +#define ETH_A_RXER (BSP_IO_PORT_03_PIN_00) +#define ETH_A_RXD1 (BSP_IO_PORT_03_PIN_01) +#define ETH_A_RXD0 (BSP_IO_PORT_03_PIN_02) +#define ETH_A_REFCLK (BSP_IO_PORT_03_PIN_03) +#define ETH_A_TXD0 (BSP_IO_PORT_03_PIN_04) +#define ETH_A_TXD1 (BSP_IO_PORT_03_PIN_05) +#define ETH_A_TXEN (BSP_IO_PORT_03_PIN_06) +#define ETH_A_MDIO (BSP_IO_PORT_03_PIN_07) +#define ETH_A_MDC (BSP_IO_PORT_03_PIN_08) +#define ARDUINO_D0_MIKROBUS_RXD3 (BSP_IO_PORT_03_PIN_09) +#define ARDUINO_D1_MIKROBUS_TXD3 (BSP_IO_PORT_03_PIN_10) +#define CAN_RXD (BSP_IO_PORT_03_PIN_11) +#define CAN_TXD (BSP_IO_PORT_03_PIN_12) +#define I3C_SCL0_ARDUINO_MIKROBUS_PMOD1_3_qwiic (BSP_IO_PORT_04_PIN_00) +#define I3C_SDA0_ARDUINO_MIKROBUS_PMOD1_4_qwiic (BSP_IO_PORT_04_PIN_01) +#define ETH_B_MDIO (BSP_IO_PORT_04_PIN_02) +#define ETH_B_LINKSTA (BSP_IO_PORT_04_PIN_03) +#define ETH_B_RST_N (BSP_IO_PORT_04_PIN_04) +#define ETH_B_TXEN (BSP_IO_PORT_04_PIN_05) +#define ETH_B_TXD1 (BSP_IO_PORT_04_PIN_06) +#define USBFS_VBUS (BSP_IO_PORT_04_PIN_07) +#define USBHS_VBUSEN (BSP_IO_PORT_04_PIN_08) +#define USBHS_OVRCURA (BSP_IO_PORT_04_PIN_09) +#define MISOB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_10) +#define MOSIB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_11) +#define RSPCKB_B_ARDUINO_MIKROBUS (BSP_IO_PORT_04_PIN_12) +#define SSLB0_B_ARDUINO_D10_MIKROBUS (BSP_IO_PORT_04_PIN_13) +#define LED2 (BSP_IO_PORT_04_PIN_14) +#define USBFS_VBUS_EN (BSP_IO_PORT_05_PIN_00) +#define USBFS_OVERCURA (BSP_IO_PORT_05_PIN_01) +#define MIKROBUS_RESET (BSP_IO_PORT_05_PIN_02) +#define PMOD2_7_IRQ1 (BSP_IO_PORT_05_PIN_08) +#define GROVE2_IIC_SDA1 (BSP_IO_PORT_05_PIN_11) +#define GROVE2_IIC_SCL1 (BSP_IO_PORT_05_PIN_12) +#define LED1 (BSP_IO_PORT_06_PIN_00) +#define ARDUINO_D5 (BSP_IO_PORT_06_PIN_01) +#define ARDUINO_D6 (BSP_IO_PORT_06_PIN_02) +#define ARDUINO_D9 (BSP_IO_PORT_06_PIN_03) +#define PMOD1_3_MISO0_RXD0_SCL0 (BSP_IO_PORT_06_PIN_09) +#define PMOD1_2_MOSI0_TXD0 (BSP_IO_PORT_06_PIN_10) +#define PMOD1_4_SCK0 (BSP_IO_PORT_06_PIN_11) +#define PMOD1_1_SSL0_CTS_RTS (BSP_IO_PORT_06_PIN_12) +#define PMOD1_1_CTS0 (BSP_IO_PORT_06_PIN_13) +#define PMOD1_9_GPIO (BSP_IO_PORT_06_PIN_14) +#define PMOD1_10_GPIO (BSP_IO_PORT_06_PIN_15) +#define ETH_B_TXD0 (BSP_IO_PORT_07_PIN_00) +#define ETH_B_REFCLK (BSP_IO_PORT_07_PIN_01) +#define ETH_B_RXD0 (BSP_IO_PORT_07_PIN_02) +#define ETH_B_RXD1 (BSP_IO_PORT_07_PIN_03) +#define ETH_B_RXER (BSP_IO_PORT_07_PIN_04) +#define ETH_B_RMII_RXDV (BSP_IO_PORT_07_PIN_05) +#define I3C_SDA0_PULLUP (BSP_IO_PORT_07_PIN_11) +#define OSPI_DQ5 (BSP_IO_PORT_08_PIN_00) +#define OSPI_DS (BSP_IO_PORT_08_PIN_01) +#define OSPI_DQ6 (BSP_IO_PORT_08_PIN_02) +#define OSPI_DQ1 (BSP_IO_PORT_08_PIN_03) +#define OSPI_DQ7 (BSP_IO_PORT_08_PIN_04) +#define OSPI_CK (BSP_IO_PORT_08_PIN_08) +#define PMOD2_8_RESET (BSP_IO_PORT_08_PIN_09) +#define PMOD2_9_GPIO (BSP_IO_PORT_08_PIN_10) +#define PMOD2_10_GPIO (BSP_IO_PORT_08_PIN_11) +#define ARDUINO_RESET (BSP_IO_PORT_08_PIN_12) +#define USBFS_P (BSP_IO_PORT_08_PIN_14) +#define USBFS_N (BSP_IO_PORT_08_PIN_15) +#define ARDUINO_D4 (BSP_IO_PORT_09_PIN_05) +#define ARDUINO_D2 (BSP_IO_PORT_09_PIN_06) +#define ARDUINO_D3_MIKROBUS_GTIOC13A (BSP_IO_PORT_09_PIN_07) +#define ARDUINO_D7 (BSP_IO_PORT_09_PIN_08) +#define ARDUINO_D8 (BSP_IO_PORT_09_PIN_09) +#define PMOD2_3_MISO2_RXD2 (BSP_IO_PORT_10_PIN_02) +#define PMOD2_2_MOSI2_TXD2 (BSP_IO_PORT_10_PIN_03) +#define PMOD2_4_SCK2 (BSP_IO_PORT_10_PIN_04) +#define PMOD2_1_CTS_RTS_SSL2 (BSP_IO_PORT_10_PIN_05) +#define PMOD2_1_CTS2 (BSP_IO_PORT_10_PIN_06) +#define PMOD1_8_RESET (BSP_IO_PORT_10_PIN_08) +#define JLOB_COMS_TX (BSP_IO_PORT_10_PIN_14) +#define JLOB_COMS_RX (BSP_IO_PORT_10_PIN_15) +#define I3C_SCL0_PULLUP (BSP_IO_PORT_11_PIN_00) +#define USBHS_VBUS (BSP_IO_PORT_11_PIN_01) +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA8M1 EK */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..d2688bf5b --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,13 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#ifdef __cplusplus +extern "C" { +#endif + +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + +#ifdef __cplusplus +} +#endif +#endif /* R_IOPORT_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h new file mode 100644 index 000000000..9f8c76144 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,56 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (20000000) /* XTAL 20000000Hz */ +#define BSP_CFG_HOCO_FREQUENCY (7) /* HOCO 48MHz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL(96,0) /* PLL Mul x80-99|Mul x96|PLL Mul x96.00 */ +#define BSP_CFG_PLL_FREQUENCY_HZ (960000000) /* PLL 960000000Hz */ +#define BSP_CFG_PLODIVP (BSP_CLOCKS_PLL_DIV_2) /* PLL1P Div /2 */ +#define BSP_CFG_PLL1P_FREQUENCY_HZ (480000000) /* PLL1P 480000000Hz */ +#define BSP_CFG_PLODIVQ (BSP_CLOCKS_PLL_DIV_2) /* PLL1Q Div /2 */ +#define BSP_CFG_PLL1Q_FREQUENCY_HZ (480000000) /* PLL1Q 480000000Hz */ +#define BSP_CFG_PLODIVR (BSP_CLOCKS_PLL_DIV_2) /* PLL1R Div /2 */ +#define BSP_CFG_PLL1R_FREQUENCY_HZ (480000000) /* PLL1R 480000000Hz */ +#define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL2 Disabled */ +#define BSP_CFG_PLL2_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL2 Div /2 */ +#define BSP_CFG_PLL2_MUL BSP_CLOCKS_PLL_MUL(96,0) /* PLL2 Mul x80-99|Mul x96|PLL2 Mul x96.00 */ +#define BSP_CFG_PLL2_FREQUENCY_HZ (0) /* PLL2 0Hz */ +#define BSP_CFG_PL2ODIVP (BSP_CLOCKS_PLL_DIV_2) /* PLL2P Div /2 */ +#define BSP_CFG_PLL2P_FREQUENCY_HZ (0) /* PLL2P 0Hz */ +#define BSP_CFG_PL2ODIVQ (BSP_CLOCKS_PLL_DIV_2) /* PLL2Q Div /2 */ +#define BSP_CFG_PLL2Q_FREQUENCY_HZ (0) /* PLL2Q 0Hz */ +#define BSP_CFG_PL2ODIVR (BSP_CLOCKS_PLL_DIV_2) /* PLL2R Div /2 */ +#define BSP_CFG_PLL2R_FREQUENCY_HZ (0) /* PLL2R 0Hz */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* Clock Src: PLL1P */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_SCICLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* SCICLK Disabled */ +#define BSP_CFG_SPICLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* SPICLK Disabled */ +#define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ +#define BSP_CFG_I3CCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* I3CCLK Disabled */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* UCK Disabled */ +#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* U60CK Disabled */ +#define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ +#define BSP_CFG_CPUCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CPUCLK Div /1 */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKA Div /4 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKB Div /8 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* PCLKC Div /8 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKD Div /4 */ +#define BSP_CFG_PCLKE_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKE Div /2 */ +#define BSP_CFG_SDCLK_OUTPUT (1) /* SDCLK Enabled */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* BCLK Div /4 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* EBCLK Div /2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_8) /* FCLK Div /8 */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_SCICLK_DIV (BSP_CLOCKS_SCI_CLOCK_DIV_4) /* SCICLK Div /4 */ +#define BSP_CFG_SPICLK_DIV (BSP_CLOCKS_SPI_CLOCK_DIV_4) /* SPICLK Div /4 */ +#define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_8) /* CANFDCLK Div /8 */ +#define BSP_CFG_I3CCLK_DIV (BSP_CLOCKS_I3C_CLOCK_DIV_3) /* I3CCLK Div /3 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCK Div /5 */ +#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* U60CK Div /5 */ +#define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_4) /* OCTASPICLK Div /4 */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.c b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.c new file mode 100644 index 000000000..50036c0ad --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.c @@ -0,0 +1,11 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.h b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.h new file mode 100644 index 000000000..6a08cbee0 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/pin_data.c b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/pin_data.c new file mode 100644 index 000000000..b92421739 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/pin_data.c @@ -0,0 +1,275 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_00_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_00_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_00_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_IRQ_ENABLE | (uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_00_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_00_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_ANALOG_ENABLE) + }, + { + .pin = BSP_IO_PORT_01_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_01_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_02_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_02_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_02_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_03_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_03_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_03_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_03_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_03_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_TRACE) + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_04_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS) + }, + { + .pin = BSP_IO_PORT_04_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS) + }, + { + .pin = BSP_IO_PORT_04_PIN_10, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_13, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SPI) + }, + { + .pin = BSP_IO_PORT_04_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_05_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_05_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_05_PIN_11, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) + }, + { + .pin = BSP_IO_PORT_05_PIN_12, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_MID | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_IIC) + }, + { + .pin = BSP_IO_PORT_06_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_08_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_08_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_08_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_08_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_08_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_08_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HS_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_OSPI) + }, + { + .pin = BSP_IO_PORT_08_PIN_09, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_08_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_08_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_10_PIN_02, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_10_PIN_03, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_10_PIN_04, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_10_PIN_05, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI0_2_4_6_8) + }, + { + .pin = BSP_IO_PORT_10_PIN_06, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT) + }, + { + .pin = BSP_IO_PORT_10_PIN_14, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_10_PIN_15, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_SCI1_3_5_7_9) + }, + { + .pin = BSP_IO_PORT_11_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_DRIVE_HIGH | (uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif diff --git a/hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld new file mode 100644 index 000000000..32cbf0b22 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld @@ -0,0 +1,820 @@ +/* + Linker File for Renesas FSP +*/ + +INCLUDE memory_regions.ld + +/* Uncomment and set XIP_SECONDARY_SLOT_IMAGE to 1 below for the secondary XIP application image.*/ +/* + XIP_SECONDARY_SLOT_IMAGE = 1; +*/ + +QSPI_FLASH_PRV_LENGTH = DEFINED(QSPI_FLASH_SIZE) ? ABSOLUTE(QSPI_FLASH_SIZE) : ABSOLUTE(QSPI_FLASH_LENGTH); +OSPI_DEVICE_0_PRV_LENGTH = DEFINED(OSPI_DEVICE_0_SIZE) ? ABSOLUTE(OSPI_DEVICE_0_SIZE) : ABSOLUTE(OSPI_DEVICE_0_LENGTH); +OSPI_DEVICE_1_PRV_LENGTH = DEFINED(OSPI_DEVICE_1_SIZE) ? ABSOLUTE(OSPI_DEVICE_1_SIZE) : ABSOLUTE(OSPI_DEVICE_1_LENGTH); + +/* If a flat (secure) project has DEFINED RAM_NS_BUFFER_LENGTH, then emit IDAU symbols to allocate non-secure RAM. */ +__RESERVE_NS_RAM = !DEFINED(PROJECT_NONSECURE) && DEFINED(RAM_NS_BUFFER_LENGTH) && (OPTION_SETTING_S_LENGTH != 0); + +ITCM_START = DEFINED(ITCM_START)? ITCM_START : 0; +ITCM_LENGTH = DEFINED(ITCM_LENGTH)? ITCM_LENGTH : 0; +DTCM_START = DEFINED(DTCM_START)? DTCM_START : 0; +DTCM_LENGTH = DEFINED(DTCM_LENGTH)? DTCM_LENGTH : 0; +RAM_NS_BUFFER_BLOCK_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? ALIGN(RAM_NS_BUFFER_LENGTH, 8192) : 0; +RAM_NS_BUFFER_LENGTH = DEFINED(RAM_NS_BUFFER_LENGTH) ? RAM_NS_BUFFER_LENGTH : 0; +RAM_NS_BUFFER_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_LENGTH; +RAM_NS_BUFFER_BLOCK_START = RAM_START + RAM_LENGTH - RAM_NS_BUFFER_BLOCK_LENGTH; + +OPTION_SETTING_START_NS = DEFINED(PROJECT_NONSECURE) ? OPTION_SETTING_START : OPTION_SETTING_START + 0x80; +OPTION_SETTING_DATA_FLASH_S_START = DEFINED(OPTION_SETTING_DATA_FLASH_S_START) ? OPTION_SETTING_DATA_FLASH_S_START : 0; +OPTION_SETTING_DATA_FLASH_S_LENGTH = DEFINED(OPTION_SETTING_DATA_FLASH_S_LENGTH) ? OPTION_SETTING_DATA_FLASH_S_LENGTH : 0; + +/* This definition is used to avoid moving the counter in OPTION_SETTING regions for projects that should not configure option settings. + * Bootloader images do not configure option settings because they are owned by the bootloader. + * FSP_BOOTABLE_IMAGE is only defined in bootloader images. */ +__bl_FSP_BOOTABLE_IMAGE = 1; +__bln_FSP_BOOTABLE_IMAGE = 1; +PROJECT_SECURE_OR_FLAT = (!DEFINED(PROJECT_NONSECURE) || DEFINED(PROJECT_SECURE)) && OPTION_SETTING_LENGTH && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_NS = DEFINED(PROJECT_NONSECURE) && !DEFINED(FSP_BOOTABLE_IMAGE); +USE_OPTION_SETTING_DATA_FLASH = PROJECT_SECURE_OR_FLAT && (OPTION_SETTING_DATA_FLASH_S_LENGTH != 0); + +__bl_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_IMAGE_NUMBER == 1 ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + (DEFINED(BOOTLOADER_SECONDARY_USE_QSPI) || DEFINED(BOOTLOADER_SECONDARY_USE_OSPI_B)) ? FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_BOOTLOADER_SCRATCH_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_S_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_FLASH_IMAGE_END = __bl_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_START + FLASH_BOOTLOADER_LENGTH + FLASH_APPLICATION_S_LENGTH + FLASH_BOOTLOADER_HEADER_LENGTH; +__bl_XIP_SECONDARY_FLASH_IMAGE_END = __bl_XIP_SECONDARY_FLASH_IMAGE_START + __bl_FLASH_IMAGE_LENGTH; +__bl_FLASH_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_START - FLASH_BOOTLOADER_HEADER_LENGTH + FLASH_APPLICATION_S_LENGTH; +__bl_FLASH_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_IMAGE_END - FLASH_APPLICATION_NSC_LENGTH; +__bl_RAM_NS_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH; +__bl_RAM_NSC_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? RAM_START + RAM_LENGTH : + __bl_RAM_NS_START - RAM_APPLICATION_NSC_LENGTH; +__bl_FLASH_NS_IMAGE_START = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + __bl_FLASH_NS_START + FLASH_BOOTLOADER_HEADER_LENGTH_2; +__bln_FLASH_IMAGE_START = __bl_FLASH_NS_IMAGE_START | (!DEFINED (NS_OFFSET_START) ? 0 : NS_OFFSET_START); +__bln_FLASH_IMAGE_LENGTH = !DEFINED(FLASH_BOOTLOADER_LENGTH) ? 0 : + FLASH_APPLICATION_NS_LENGTH == 0 ? __bl_FLASH_IMAGE_END : + FLASH_APPLICATION_NS_LENGTH - FLASH_BOOTLOADER_HEADER_LENGTH_2; + +XIP_SECONDARY_SLOT_IMAGE = DEFINED(XIP_SECONDARY_SLOT_IMAGE) ? XIP_SECONDARY_SLOT_IMAGE : 0; +FLASH_ORIGIN = !DEFINED(FLASH_IMAGE_START) ? FLASH_START : + XIP_SECONDARY_SLOT_IMAGE == 1 ? XIP_SECONDARY_FLASH_IMAGE_START : + FLASH_IMAGE_START; +LIMITED_FLASH_LENGTH = DEFINED(FLASH_IMAGE_LENGTH) ? FLASH_IMAGE_LENGTH : + DEFINED(FLASH_BOOTLOADER_LENGTH) ? FLASH_BOOTLOADER_LENGTH : + FLASH_LENGTH; +OPTION_SETTING_SAS_SIZE = 0x34; +OPTION_SETTING_SAS_LENGTH = !DEFINED(OPTION_SETTING_LENGTH) ? 0 : + OPTION_SETTING_LENGTH == 0 ? 0 : + OPTION_SETTING_LENGTH - OPTION_SETTING_SAS_SIZE; + +/* Define memory regions. */ +MEMORY +{ + ITCM (rx) : ORIGIN = ITCM_START, LENGTH = ITCM_LENGTH + DTCM (rwx) : ORIGIN = DTCM_START, LENGTH = DTCM_LENGTH + FLASH (rx) : ORIGIN = FLASH_ORIGIN, LENGTH = LIMITED_FLASH_LENGTH + RAM (rwx) : ORIGIN = RAM_START, LENGTH = RAM_LENGTH + DATA_FLASH (rx) : ORIGIN = DATA_FLASH_START, LENGTH = DATA_FLASH_LENGTH + QSPI_FLASH (rx) : ORIGIN = QSPI_FLASH_START, LENGTH = QSPI_FLASH_PRV_LENGTH + OSPI_DEVICE_0 (rx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1 (rx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + OSPI_DEVICE_0_RAM (rwx) : ORIGIN = OSPI_DEVICE_0_START, LENGTH = OSPI_DEVICE_0_PRV_LENGTH + OSPI_DEVICE_1_RAM (rwx) : ORIGIN = OSPI_DEVICE_1_START, LENGTH = OSPI_DEVICE_1_PRV_LENGTH + SDRAM (rwx) : ORIGIN = SDRAM_START, LENGTH = SDRAM_LENGTH + OPTION_SETTING (r) : ORIGIN = OPTION_SETTING_START, LENGTH = OPTION_SETTING_LENGTH + OPTION_SETTING_OFS (r) : ORIGIN = OPTION_SETTING_START, LENGTH = 0x18 + OPTION_SETTING_SAS (r) : ORIGIN = OPTION_SETTING_START + OPTION_SETTING_SAS_SIZE, LENGTH = OPTION_SETTING_SAS_LENGTH + OPTION_SETTING_S (r) : ORIGIN = OPTION_SETTING_S_START, LENGTH = OPTION_SETTING_S_LENGTH + OPTION_SETTING_DATA_FLASH_S (r) : ORIGIN = OPTION_SETTING_DATA_FLASH_S_START, LENGTH = OPTION_SETTING_DATA_FLASH_S_LENGTH + ID_CODE (rx) : ORIGIN = ID_CODE_START, LENGTH = ID_CODE_LENGTH +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be DEFINED in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + * __qspi_flash_start__ + * __qspi_flash_end__ + * __qspi_flash_code_size__ + * __qspi_region_max_size__ + * __qspi_region_start_address__ + * __qspi_region_end_address__ + * __ospi_device_0_start__ + * __ospi_device_0_end__ + * __ospi_device_0_code_size__ + * __ospi_device_0_region_max_size__ + * __ospi_device_0_region_start_address__ + * __ospi_device_0_region_end_address__ + * __ospi_device_1_start__ + * __ospi_device_1_end__ + * __ospi_device_1_code_size__ + * __ospi_device_1_region_max_size__ + * __ospi_device_1_region_start_address__ + * __ospi_device_1_region_end_address__ + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + __tz_FLASH_S = ABSOLUTE(FLASH_START); + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + + /* Some devices have a gap of code flash between the vector table and ROM Registers. + * The flash gap section allows applications to place code and data in this section. */ + *(.flash_gap*) + + /* ROM Registers start at address 0x00000400 for devices that do not have the OPTION_SETTING region. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Allocate flash write-boundary-aligned + * space for sce9 wrapped public keys for mcuboot if the module is used. + */ + KEEP(*(.mcuboot_sce9_key*)) + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + . = .; + __itcm_data_pre_location = .; + + /* Initialized ITCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .itcm_data : ALIGN(16) + { + /* Start of ITCM Secure Trustzone region. */ + __tz_ITCM_S = ABSOLUTE(ITCM_START); + + /* All ITCM data start */ + __itcm_data_start = .; + + KEEP(*(.itcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* All ITCM data end */ + __itcm_data_end = .; + + /* + * Start of the ITCM Non-Secure Trustzone region. + * ITCM_NS_START can be used to set a fixed address for non-secure ITCM in secure projects or flat projects. + */ + __tz_ITCM_N = DEFINED(ITCM_NS_START) ? ABSOLUTE(ITCM_NS_START) : ALIGN(__itcm_data_end, 8192); + } > ITCM AT > FLASH = 0x00 + + /* Addresses exported for ITCM initialization. */ + __itcm_data_init_start = LOADADDR(.itcm_data); + __itcm_data_init_end = LOADADDR(.itcm_data) + SIZEOF(.itcm_data); + + ASSERT(ORIGIN(ITCM) % 8 == 0, "ITCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(ITCM) % 8 == 0, "ITCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.itcm_data) % 16 == 0, ".itcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.itcm_data) % 8 == 0, ".itcm_data section size must be a multiple of 8 bytes.") + + /* Restore location counter. */ + /* If ITCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If ITCM is present, this will be the absolute address that follows the ITCM ROM location. */ + . = (SIZEOF(.itcm_data) > 0) ? __itcm_data_init_end : __itcm_data_pre_location; + + __exidx_start = .; + /DISCARD/ : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + __tz_RAM_S = ORIGIN(RAM); + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + __data_start__ = .; + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + *(vtable) + /* Don't use *(.data*) because it will place data meant for .data_flash in this section. */ + *(.data.*) + *(.data) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + + . = ALIGN(4); + + /* All data end */ + __data_end__ = .; + + } > RAM AT > FLASH + + . = .; + __dtcm_data_pre_location = LOADADDR(.data) + SIZEOF(.data); + + /* Initialized DTCM data. */ + /* Aligned to FCACHE2 for RA8. */ + .dtcm_data : ALIGN(16) + { + /* Start of DTCM Secure Trustzone region. */ + __tz_DTCM_S = ABSOLUTE(DTCM_START); + + /* Initialized DTCM data start */ + __dtcm_data_start = .; + + KEEP(*(.dtcm_data*)) + + /* Pad to eight byte alignment in case of ECC initialization. Fill zero. */ + . = ALIGN(8); + + /* Initialized DTCM data end */ + __dtcm_data_end = .; + } > DTCM AT > FLASH = 0x00 + + . = __dtcm_data_end; + /* Uninitialized DTCM data. */ + /* ALIGN appears on the left side of the colon because it is being used to assign the VMA directly, as opposed to a right side appearance which would control the LMA. */ + .dtcm_bss ALIGN(8) (NOLOAD) : + { + /* Uninitialized DTCM data start */ + __dtcm_bss_start = .; + + KEEP(*(.dtcm_bss*)) + + /* Pad to eight byte alignment in case of ECC initialization. No fill because of NOLOAD. */ + . = ALIGN(8); + + /* Uninitialized DTCM data end */ + __dtcm_bss_end = .; + + /* + * Start of the DTCM Non-Secure Trustzone region. + * DTCM_NS_START can be used to set a fixed address for non-secure DTCM in secure projects or flat projects. + */ + __tz_DTCM_N = DEFINED(DTCM_NS_START) ? ABSOLUTE(DTCM_NS_START) : ALIGN(__dtcm_bss_end, 8192); + } > DTCM + + /* Addresses exported for DTCM initialization. */ + __dtcm_data_init_start = LOADADDR(.dtcm_data); + __dtcm_data_init_end = LOADADDR(.dtcm_data) + SIZEOF(.dtcm_data); + + ASSERT(ORIGIN(DTCM) % 8 == 0, "DTCM memory region origin must be aligned to 8 bytes.") + ASSERT(LENGTH(DTCM) % 8 == 0, "DTCM memory region length must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) == ADDR(.dtcm_bss), ".dtcm_bss has (VMA != LMA) but should be NOLOAD (VMA == LMA).") + ASSERT(LOADADDR(.dtcm_data) % 16 == 0, ".dtcm_data section must be aligned to 16 bytes.") + ASSERT(SIZEOF(.dtcm_data) % 8 == 0, ".dtcm_data section size must be a multiple of 8 bytes.") + ASSERT(LOADADDR(.dtcm_bss) % 8 == 0, ".dtcm_bss section must be aligned to 8 bytes.") + ASSERT(SIZEOF(.dtcm_bss) % 8 == 0, ".dtcm_bss section size must be a multiple of 8 bytes.") + ASSERT(__dtcm_bss_start == __dtcm_data_end, ".dtcm_bss section is not adjacent to .dtcm_data section.") + + /* Restore location counter. */ + /* If DTCM is not present, this will be the address stored in '.' before ALIGN was attempted. */ + /* If DTCM is present, this will be the absolute address that follows the DTCM ROM location. */ + . = (SIZEOF(.dtcm_data) > 0) ? __dtcm_data_init_end : __dtcm_data_pre_location; + + /* TrustZone Secure Gateway Stubs Section */ + + /* Store location counter for SPI non-retentive sections. */ + sgstubs_pre_location = .; + + /* Determine the secure gateway stubs address either by the provided linker variable or the next 1024-byte block. */ + SGSTUBS_LOC = (DEFINED(PROJECT_SECURE) && DEFINED(FLASH_NSC_START)) ? ABSOLUTE(FLASH_NSC_START) : ALIGN(1024); + .gnu.sgstubs SGSTUBS_LOC : ALIGN(1024) + { + __FLASH_NSC_START = DEFINED(FLASH_NSC_START) ? ABSOLUTE(FLASH_NSC_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : ALIGN(1024); + _start_sg = .; + *(.gnu.sgstubs*) + . = ALIGN(32); + _end_sg = .; + } > FLASH + + __tz_FLASH_N = DEFINED(FLASH_NS_START) ? ABSOLUTE(FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(FLASH_START + FLASH_LENGTH) : FLASH_LENGTH < 32768 ? FLASH_LENGTH : ALIGN(32768); + FLASH_NS_IMAGE_START = DEFINED(FLASH_NS_IMAGE_START) ? FLASH_NS_IMAGE_START : __tz_FLASH_N; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_S = ORIGIN(QSPI_FLASH); + + /* QSPI_FLASH section to be downloaded via debugger */ + .qspi_flash : + { + __qspi_flash_start__ = .; + KEEP(*(.qspi_flash*)) + KEEP(*(.code_in_qspi*)) + __qspi_flash_end__ = .; + } > QSPI_FLASH + __qspi_flash_code_size__ = __qspi_flash_end__ - __qspi_flash_start__; + + /* QSPI_FLASH non-retentive section, creates a copy in internal flash that can be copied to QSPI */ + __qspi_flash_code_addr__ = sgstubs_pre_location; + .qspi_non_retentive : AT(__qspi_flash_code_addr__) + { + __qspi_non_retentive_start__ = .; + KEEP(*(.qspi_non_retentive*)) + __qspi_non_retentive_end__ = .; + } > QSPI_FLASH + __qspi_non_retentive_size__ = __qspi_non_retentive_end__ - __qspi_non_retentive_start__; + + __qspi_region_max_size__ = 0x4000000; /* Must be the same as defined in MEMORY above */ + __qspi_region_start_address__ = __qspi_flash_start__; + __qspi_region_end_address__ = __qspi_flash_start__ + __qspi_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_QSPI_FLASH_N = __qspi_non_retentive_end__; + + /* Support for OctaRAM */ + .OSPI_DEVICE_0_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_0_start__ = .; + *(.ospi_device_0_no_load*) + . = ALIGN(4); + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0_RAM + + .OSPI_DEVICE_1_NO_LOAD (NOLOAD): + { + . = ALIGN(4); + __ospi_device_1_start__ = .; + *(.ospi_device_1_no_load*) + . = ALIGN(4); + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1_RAM + + /* Note: There are no secure/non-secure boundaries for QSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_S = ORIGIN(OSPI_DEVICE_0); + + /* OSPI_DEVICE_0 section to be downloaded via debugger */ + .OSPI_DEVICE_0 : + { + __ospi_device_0_start__ = .; + KEEP(*(.ospi_device_0*)) + KEEP(*(.code_in_ospi_device_0*)) + __ospi_device_0_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_code_size__ = __ospi_device_0_end__ - __ospi_device_0_start__; + + /* OSPI_DEVICE_0 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_0_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive)); + .ospi_device_0_non_retentive : AT(__ospi_device_0_code_addr__) + { + __ospi_device_0_non_retentive_start__ = .; + KEEP(*(.ospi_device_0_non_retentive*)) + __ospi_device_0_non_retentive_end__ = .; + } > OSPI_DEVICE_0 + __ospi_device_0_non_retentive_size__ = __ospi_device_0_non_retentive_end__ - __ospi_device_0_non_retentive_start__; + + __ospi_device_0_region_max_size__ = 0x8000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_0_region_start_address__ = __ospi_device_0_start__; + __ospi_device_0_region_end_address__ = __ospi_device_0_start__ + __ospi_device_0_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_0_N = __ospi_device_0_non_retentive_end__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_S = ORIGIN(OSPI_DEVICE_1); + + /* OSPI_DEVICE_1 section to be downloaded via debugger */ + .OSPI_DEVICE_1 : + { + __ospi_device_1_start__ = .; + KEEP(*(.ospi_device_1*)) + KEEP(*(.code_in_ospi_device_1*)) + __ospi_device_1_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_code_size__ = __ospi_device_1_end__ - __ospi_device_1_start__; + + /* OSPI_DEVICE_1 non-retentive section, creates a copy in internal flash that can be copied to OSPI */ + __ospi_device_1_code_addr__ = sgstubs_pre_location + (SIZEOF(.qspi_non_retentive) + SIZEOF(.ospi_device_0_non_retentive)); + .ospi_device_1_non_retentive : AT(__ospi_device_1_code_addr__) + { + __ospi_device_1_non_retentive_start__ = .; + KEEP(*(.ospi_device_1_non_retentive*)) + __ospi_device_1_non_retentive_end__ = .; + } > OSPI_DEVICE_1 + __ospi_device_1_non_retentive_size__ = __ospi_device_1_non_retentive_end__ - __ospi_device_1_non_retentive_start__; + + __ospi_device_1_region_max_size__ = 0x10000000; /* Must be the same as defined in MEMORY above */ + __ospi_device_1_region_start_address__ = __ospi_device_1_start__; + __ospi_device_1_region_end_address__ = __ospi_device_1_start__ + __ospi_device_1_region_max_size__; + + /* Note: There are no secure/non-secure boundaries for OSPI. These symbols are provided for the RA configuration tool. */ + __tz_OSPI_DEVICE_1_N = __ospi_device_1_non_retentive_end__; + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + . = ALIGN(8); + /* Place the FreeRTOS heap here so that the __HeapLimit calculation does not include the freertos heap. */ + KEEP(*(.heap.*)) + __noinit_end = .; + } > RAM + + . = .; + __nocache_pre_location = .; + .nocache ALIGN(32) (NOLOAD): + { + __nocache_start = .; + + KEEP(*(.nocache)) + + . = ALIGN(32); + __nocache_end = .; + } > RAM + . = (SIZEOF(.nocache) > 0) ? __nocache_end : __nocache_pre_location; + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + /* Place the STD heap here. */ + KEEP(*(.heap)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* RAM_NSC_START can be used to set a fixed address for non-secure callable RAM in secure projects. + * If it is not specified, the address for NSC RAM is the end of RAM aligned to a 1K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __RAM_NSC_START = DEFINED(RAM_NSC_START) ? ABSOLUTE(RAM_NSC_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_segment_used_end__, 1024); + + /* RAM_NS_START can be used to set a fixed address for non-secure RAM in secure projects or flat projects. + * RAM_NS_BUFFER_BLOCK_LENGTH is used to allocate non-secure buffers in a flat project. If it is not + * specified, the address for NSC RAM is the end of RAM aligned to an 8K boundary. + * In flat projects that require non-secure RAM, this variable is set to the start of non-secure RAM. */ + __tz_RAM_N = DEFINED(FLASH_BOOTLOADER_LENGTH) ? (RAM_START + RAM_LENGTH - RAM_APPLICATION_NS_LENGTH) : DEFINED(RAM_NS_START) ? ABSOLUTE(RAM_NS_START - RAM_NS_BUFFER_BLOCK_LENGTH) : __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_BLOCK_START) : ALIGN(__RAM_NSC_START, 8192); + + /* Non-secure buffers must be in non-secure RAM. This is primarily used for the EDMAC in flat projects. + * The EDMAC is a non-secure bus master and can only access non-secure RAM. */ + .ns_buffer (NOLOAD): + { + /* Allocate RAM on a 32-byte boundary to help with placement of Ethernet buffers. */ + . = __RESERVE_NS_RAM ? ABSOLUTE(RAM_NS_BUFFER_START & 0xFFFFFFE0) : .; + + KEEP(*(.ns_buffer*)) + } > RAM + + /* Data flash. */ + .data_flash : + { + . = ORIGIN(DATA_FLASH); + __tz_DATA_FLASH_S = .; + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + + __tz_DATA_FLASH_N = DEFINED(DATA_FLASH_NS_START) ? ABSOLUTE(DATA_FLASH_NS_START) : __RESERVE_NS_RAM ? ABSOLUTE(DATA_FLASH_START + DATA_FLASH_LENGTH) : ALIGN(1024); + } > DATA_FLASH + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_S = ORIGIN(SDRAM); + + /* SDRAM */ + .sdram (NOLOAD): + { + __SDRAM_Start = .; + KEEP(*(.sdram*)) + KEEP(*(.frame*)) + __SDRAM_End = .; + } > SDRAM + + . = .; + __nocache_sdram_pre_location = .; + .nocache_sdram ALIGN(32) (NOLOAD): + { + __nocache_sdram_start = .; + + KEEP(*(.nocache_sdram)) + + . = ALIGN(32); + __nocache_sdram_end = .; + } > SDRAM + . = (SIZEOF(.nocache_sdram) > 0) ? __nocache_sdram_end : __nocache_sdram_pre_location; + + /* Note: There are no secure/non-secure boundaries for SDRAM. These symbols are provided for the RA configuration tool. */ + __tz_SDRAM_N = __SDRAM_End; + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. */ + __tz_ID_CODE_S = ORIGIN(ID_CODE); + + /* Note: There are no secure/non-secure boundaries for ID_CODE. These symbols are provided for the RA configuration tool. + * Set this symbol to the same value as __tz_ID_CODE_S so the RA configuration tool does not split the ID_CODE + * memory region between TrustZone projects. */ + __tz_ID_CODE_N = __tz_ID_CODE_S; + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S = ORIGIN(OPTION_SETTING_OFS); + + .option_setting_ofs : + { + __OPTION_SETTING_OFS_Start = .; + KEEP(*(.option_setting_ofs0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x04 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_ofs2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_OFS_Start + 0x10 : __OPTION_SETTING_OFS_Start; + KEEP(*(.option_setting_dualsel)) + __OPTION_SETTING_OFS_End = .; + } > OPTION_SETTING_OFS = 0xFF + + .option_setting_sas : + { + __OPTION_SETTING_SAS_Start = .; + KEEP(*(.option_setting_sas)) + __OPTION_SETTING_SAS_End = .; + } > OPTION_SETTING_SAS = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_N = ABSOLUTE(OPTION_SETTING_START_NS); + + .option_setting_ns : + { + __OPTION_SETTING_NS_Start = .; + KEEP(*(.option_setting_ofs1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x04 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_ofs3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x10 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_banksel)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x40 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x44 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x48 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x4C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_bps3)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x60 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps0)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x64 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps1)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x68 : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps2)) + . = USE_OPTION_SETTING_NS ? __OPTION_SETTING_NS_Start + 0x6C : __OPTION_SETTING_NS_Start; + KEEP(*(.option_setting_pbps3)) + __OPTION_SETTING_NS_End = .; + } > OPTION_SETTING = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_S = ORIGIN(OPTION_SETTING_S); + + .option_setting_s : + { + __OPTION_SETTING_S_Start = .; + KEEP(*(.option_setting_ofs1_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x04 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x10 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sec)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x40 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x44 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x48 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x4C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x60 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x64 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x68 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x6C : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_pbps_sec3)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x80 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs1_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x84 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_ofs3_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0x90 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_banksel_sel)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC0 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel0)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC4 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel1)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xC8 : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel2)) + . = PROJECT_SECURE_OR_FLAT ? __OPTION_SETTING_S_Start + 0xCC : __OPTION_SETTING_S_Start; + KEEP(*(.option_setting_bps_sel3)) + __OPTION_SETTING_S_End = .; + } > OPTION_SETTING_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_S_N = __OPTION_SETTING_S_End; + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_DATA_FLASH_S_S = ORIGIN(OPTION_SETTING_DATA_FLASH_S); + + .option_setting_data_flash_s : + { + __OPTION_SETTING_DATA_FLASH_S_Start = .; + KEEP(*(.option_setting_data_flash_fsblctrl0)) + . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x04 : __OPTION_SETTING_DATA_FLASH_S_Start; + KEEP(*(.option_setting_data_flash_fsblctrl1)) + . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x08 : __OPTION_SETTING_DATA_FLASH_S_Start; + KEEP(*(.option_setting_data_flash_fsblctrl2)) + . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x0C : __OPTION_SETTING_DATA_FLASH_S_Start; + KEEP(*(.option_setting_data_flash_sacc0)) + . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x10 : __OPTION_SETTING_DATA_FLASH_S_Start; + KEEP(*(.option_setting_data_flash_sacc1)) + . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x14 : __OPTION_SETTING_DATA_FLASH_S_Start; + KEEP(*(.option_setting_data_flash_samr)) + . = USE_OPTION_SETTING_DATA_FLASH ? __OPTION_SETTING_DATA_FLASH_S_Start + 0x2E0 : __OPTION_SETTING_DATA_FLASH_S_Start; + KEEP(*(.option_setting_data_flash_hoemrtpk)) + __OPTION_SETTING_DATA_FLASH_S_End = .; + } > OPTION_SETTING_DATA_FLASH_S = 0xFF + + /* Symbol required for RA Configuration tool. */ + __tz_OPTION_SETTING_DATA_FLASH_S_N = __OPTION_SETTING_DATA_FLASH_S_End; +} diff --git a/hw/bsp/ra/boards/ra8m1_ek/script/memory_regions.ld b/hw/bsp/ra/boards/ra8m1_ek/script/memory_regions.ld new file mode 100644 index 000000000..2bc162511 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/script/memory_regions.ld @@ -0,0 +1,30 @@ + + /* generated memory regions file - do not edit */ + RAM_START = 0x22000000; + RAM_LENGTH = 0xE0000; + FLASH_START = 0x02000000; + FLASH_LENGTH = 0x1F8000; + DATA_FLASH_START = 0x27000000; + DATA_FLASH_LENGTH = 0x3000; + OPTION_SETTING_START = 0x0300A100; + OPTION_SETTING_LENGTH = 0x100; + OPTION_SETTING_S_START = 0x0300A200; + OPTION_SETTING_S_LENGTH = 0x100; + OPTION_SETTING_DATA_FLASH_S_START = 0x27030080; + OPTION_SETTING_DATA_FLASH_S_LENGTH = 0x800; + ID_CODE_START = 0x00000000; + ID_CODE_LENGTH = 0x0; + SDRAM_START = 0x68000000; + SDRAM_LENGTH = 0x8000000; + QSPI_FLASH_START = 0x60000000; + QSPI_FLASH_LENGTH = 0x0; + OSPI_DEVICE_0_START = 0x80000000; + OSPI_DEVICE_0_LENGTH = 0x10000000; + OSPI_DEVICE_1_START = 0x90000000; + OSPI_DEVICE_1_LENGTH = 0x10000000; + ITCM_START = 0x00000000; + ITCM_LENGTH = 0x10000; + DTCM_START = 0x20000000; + DTCM_LENGTH = 0x10000; + NS_OFFSET_START = 0x10000000; + NS_OFFSET_LENGTH = 0x0; diff --git a/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml index 0a9393769..cd2ffd8e1 100644 --- a/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml +++ b/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml @@ -133,8 +133,8 @@ - - + + @@ -290,7 +290,7 @@ - + -- cgit v1.3.1 From 0785daecc1a3a11d5bacbd7c4cd7dc4a48b11b49 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 13 Dec 2024 17:24:57 +0700 Subject: update build for ra8m1: usbfs work, but usbhs not working just yet. Probably missing configuration or clock setup --- hw/bsp/ra/boards/ra6m5_ek/board.cmake | 21 +- hw/bsp/ra/boards/ra6m5_ek/board.mk | 3 +- hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug | 4 +- hw/bsp/ra/boards/ra8m1_ek/board.cmake | 8 + hw/bsp/ra/boards/ra8m1_ek/board.mk | 11 + .../ra8m1_ek/ozone/Renesas_RA8_TracePins.pex | Bin 0 -> 588 bytes hw/bsp/ra/boards/ra8m1_ek/ozone/ra8m1.jdebug | 231 +++++++++++++++++++++ hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h | 10 +- .../ra8m1_ek/smart_configurator/configuration.xml | 64 +++++- hw/bsp/ra/family.c | 6 - hw/bsp/ra/family.cmake | 28 +++ hw/bsp/ra/family.mk | 55 +++-- 12 files changed, 393 insertions(+), 48 deletions(-) create mode 100644 hw/bsp/ra/boards/ra8m1_ek/board.mk create mode 100644 hw/bsp/ra/boards/ra8m1_ek/ozone/Renesas_RA8_TracePins.pex create mode 100644 hw/bsp/ra/boards/ra8m1_ek/ozone/ra8m1.jdebug (limited to 'hw') diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake index a8220c9c7..568d5d78f 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake +++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake @@ -2,22 +2,15 @@ set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra6m5) set(JLINK_DEVICE R7FA6M5BH) -#set(JLINK_OPTION "-USB 000831915224") +set(JLINK_OPTION "-USB 000831915224") -# Device port default to PORT1 Highspeed -if (NOT DEFINED PORT) -set(PORT 1) +# device default to PORT 1 High Speed +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) endif() - -# Host port will be the other port -set(HOST_PORT $) function(update_board TARGET) - target_compile_definitions(${TARGET} PUBLIC - BOARD_TUD_RHPORT=${PORT} - BOARD_TUH_RHPORT=${HOST_PORT} - # port 0 is fullspeed, port 1 is highspeed - BOARD_TUD_MAX_SPEED=$ - BOARD_TUH_MAX_SPEED=$ - ) endfunction() diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.mk b/hw/bsp/ra/boards/ra6m5_ek/board.mk index a5c933764..5fcc1d0f1 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.mk +++ b/hw/bsp/ra/boards/ra6m5_ek/board.mk @@ -5,6 +5,7 @@ MCU_VARIANT = ra6m5 JLINK_DEVICE = R7FA6M5BH # Port 1 is highspeed -PORT ?= 1 +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 0 flash: flash-jlink diff --git a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug index 7b8ee9c95..ca18fed7c 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug +++ b/hw/bsp/ra/boards/ra6m5_ek/ozone/ra6m5.jdebug @@ -20,9 +20,7 @@ void OnProjectLoad (void) { Project.SetTraceSource ("Trace Pins"); Project.SetTracePortWidth (4); - //File.Open ("../../../../../../examples/device/cdc_msc/cmake-build-ra6m5/cdc_msc.elf"); - //File.Open ("../../../../../../examples/dual/cmake-build-ra6m5/host_hid_to_device_cdc/host_hid_to_device_cdc.elf"); - File.Open ("../../../../../../examples/cmake-build-ra6m5/host/cdc_msc_hid/cdc_msc_hid.elf"); + File.Open ("../../../../../../examples/cmake-build-ra6m5_ek/device/cdc_msc/cdc_msc.elf"); } /********************************************************************* * diff --git a/hw/bsp/ra/boards/ra8m1_ek/board.cmake b/hw/bsp/ra/boards/ra8m1_ek/board.cmake index ae5d1d5bb..9c797c3b7 100644 --- a/hw/bsp/ra/boards/ra8m1_ek/board.cmake +++ b/hw/bsp/ra/boards/ra8m1_ek/board.cmake @@ -4,5 +4,13 @@ set(MCU_VARIANT ra8m1) set(JLINK_DEVICE R7FA8M1AH) #set(JLINK_OPTION "-USB 001083115236") +# device default to PORT 1 High Speed +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) +endif() + function(update_board TARGET) endfunction() diff --git a/hw/bsp/ra/boards/ra8m1_ek/board.mk b/hw/bsp/ra/boards/ra8m1_ek/board.mk new file mode 100644 index 000000000..2e56b3781 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/board.mk @@ -0,0 +1,11 @@ +CPU_CORE = cortex-m85 +MCU_VARIANT = ra8m1 + +# For flash-jlink target +JLINK_DEVICE = R7FA8M1AH + +# Port 1 is highspeed +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 0 + +flash: flash-jlink diff --git a/hw/bsp/ra/boards/ra8m1_ek/ozone/Renesas_RA8_TracePins.pex b/hw/bsp/ra/boards/ra8m1_ek/ozone/Renesas_RA8_TracePins.pex new file mode 100644 index 000000000..70dd323ec Binary files /dev/null and b/hw/bsp/ra/boards/ra8m1_ek/ozone/Renesas_RA8_TracePins.pex differ diff --git a/hw/bsp/ra/boards/ra8m1_ek/ozone/ra8m1.jdebug b/hw/bsp/ra/boards/ra8m1_ek/ozone/ra8m1.jdebug new file mode 100644 index 000000000..242a15db9 --- /dev/null +++ b/hw/bsp/ra/boards/ra8m1_ek/ozone/ra8m1.jdebug @@ -0,0 +1,231 @@ + +/********************************************************************* +* +* OnProjectLoad +* +* Function description +* Project load routine. Required. +* +********************************************************************** +*/ +void OnProjectLoad (void) { + Project.SetTraceSource ("Trace Pins"); + Project.SetDevice ("R7FA8M1AH"); + Project.SetHostIF ("USB", ""); + Project.SetTargetIF ("SWD"); + Project.SetTIFSpeed ("50 MHz"); + + Project.AddSvdFile ("$(InstallDir)/Config/CPU/Cortex-M85F.svd"); + Project.AddSvdFile ("../../../../../../../cmsis-svd-data/data/Renesas/R7FA6M5BH.svd"); + + File.Open ("../../../../../../examples/cmake-build-ra8m1_ek/device/cdc_msc/cdc_msc.elf"); +} +/********************************************************************* +* +* BeforeTargetConnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +void BeforeTargetConnect (void) { + // Trace pin init is done by J-Link script file as J-Link script files are IDE independent + //Project.SetJLinkScript("../../../debug.jlinkscript"); + Project.SetJLinkScript ("$(ProjectDir)/Renesas_RA8_TracePins.pex"); +} + +/********************************************************************* +* +* AfterTargetConnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetConnect (void) { +//} + +/********************************************************************* +* +* TargetDownload +* +* Function description +* Replaces the default program download routine. Optional. +* +********************************************************************** +*/ +//void TargetDownload (void) { +//} + +/********************************************************************* +* +* BeforeTargetDownload +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetDownload (void) { +//} + +/********************************************************************* +* +* AfterTargetDownload +* +* Function description +* Event handler routine. Optional. +* The default implementation initializes SP and PC to reset values. +* +********************************************************************** +*/ +void AfterTargetDownload (void) { + _SetupTarget(); +} + +/********************************************************************* +* +* BeforeTargetDisconnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetDisconnect (void) { +//} + +/********************************************************************* +* +* AfterTargetDisconnect +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetDisconnect (void) { +//} + +/********************************************************************* +* +* AfterTargetHalt +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void AfterTargetHalt (void) { +//} + +/********************************************************************* +* +* BeforeTargetResume +* +* Function description +* Event handler routine. Optional. +* +********************************************************************** +*/ +//void BeforeTargetResume (void) { +//} + +/********************************************************************* +* +* OnSnapshotLoad +* +* Function description +* Called upon loading a snapshot. Optional. +* +* Additional information +* This function is used to restore the target state in cases +* where values cannot simply be written to the target. +* Typical use: GPIO clock needs to be enabled, before +* GPIO is configured. +* +********************************************************************** +*/ +//void OnSnapshotLoad (void) { +//} + +/********************************************************************* +* +* OnSnapshotSave +* +* Function description +* Called upon saving a snapshot. Optional. +* +* Additional information +* This function is usually used to save values of the target +* state which can either not be trivially read, +* or need to be restored in a specific way or order. +* Typically use: Memory Mapped Registers, +* such as PLL and GPIO configuration. +* +********************************************************************** +*/ +//void OnSnapshotSave (void) { +//} + +/********************************************************************* +* +* OnError +* +* Function description +* Called when an error occurred. Optional. +* +********************************************************************** +*/ +//void OnError (void) { +//} + +/********************************************************************* +* +* AfterProjectLoad +* +* Function description +* After Project load routine. Optional. +* +********************************************************************** +*/ +//void AfterProjectLoad (void) { +//} + +/********************************************************************* +* +* _SetupTarget +* +* Function description +* Setup the target. +* Called by AfterTargetReset() and AfterTargetDownload(). +* +* Auto-generated function. May be overridden by Ozone. +* +********************************************************************** +*/ +void _SetupTarget(void) { + unsigned int SP; + unsigned int PC; + unsigned int VectorTableAddr; + + VectorTableAddr = Elf.GetBaseAddr(); + // + // Set up initial stack pointer + // + SP = Target.ReadU32(VectorTableAddr); + if (SP != 0xFFFFFFFF) { + Target.SetReg("SP", SP); + } + // + // Set up entry point PC + // + PC = Elf.GetEntryPointPC(); + if (PC != 0xFFFFFFFF) { + Target.SetReg("PC", PC); + } else { + Util.Error("Project script error: failed to set up entry point PC", 1); + } +} diff --git a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h index 9f8c76144..f2f1ae0c9 100644 --- a/hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h +++ b/hw/bsp/ra/boards/ra8m1_ek/ra_gen/bsp_clock_cfg.h @@ -11,8 +11,8 @@ #define BSP_CFG_PLL_FREQUENCY_HZ (960000000) /* PLL 960000000Hz */ #define BSP_CFG_PLODIVP (BSP_CLOCKS_PLL_DIV_2) /* PLL1P Div /2 */ #define BSP_CFG_PLL1P_FREQUENCY_HZ (480000000) /* PLL1P 480000000Hz */ -#define BSP_CFG_PLODIVQ (BSP_CLOCKS_PLL_DIV_2) /* PLL1Q Div /2 */ -#define BSP_CFG_PLL1Q_FREQUENCY_HZ (480000000) /* PLL1Q 480000000Hz */ +#define BSP_CFG_PLODIVQ (BSP_CLOCKS_PLL_DIV_4) /* PLL1Q Div /4 */ +#define BSP_CFG_PLL1Q_FREQUENCY_HZ (240000000) /* PLL1Q 240000000Hz */ #define BSP_CFG_PLODIVR (BSP_CLOCKS_PLL_DIV_2) /* PLL1R Div /2 */ #define BSP_CFG_PLL1R_FREQUENCY_HZ (480000000) /* PLL1R 480000000Hz */ #define BSP_CFG_PLL2_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* PLL2 Disabled */ @@ -31,8 +31,8 @@ #define BSP_CFG_SPICLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* SPICLK Disabled */ #define BSP_CFG_CANFDCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CANFDCLK Disabled */ #define BSP_CFG_I3CCLK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* I3CCLK Disabled */ -#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* UCK Disabled */ -#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* U60CK Disabled */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1Q) /* UCK Src: PLL1Q */ +#define BSP_CFG_U60CK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL1P) /* U60CK Src: PLL1P */ #define BSP_CFG_OCTA_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* OCTASPICLK Disabled */ #define BSP_CFG_CPUCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CPUCLK Div /1 */ #define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ @@ -51,6 +51,6 @@ #define BSP_CFG_CANFDCLK_DIV (BSP_CLOCKS_CANFD_CLOCK_DIV_8) /* CANFDCLK Div /8 */ #define BSP_CFG_I3CCLK_DIV (BSP_CLOCKS_I3C_CLOCK_DIV_3) /* I3CCLK Div /3 */ #define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCK Div /5 */ -#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* U60CK Div /5 */ +#define BSP_CFG_U60CK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_8) /* U60CK Div /8 */ #define BSP_CFG_OCTA_DIV (BSP_CLOCKS_OCTA_CLOCK_DIV_4) /* OCTASPICLK Div /4 */ #endif /* BSP_CLOCK_CFG_H_ */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml b/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml index cd2ffd8e1..0f83b4a11 100644 --- a/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml +++ b/hw/bsp/ra/boards/ra8m1_ek/smart_configurator/configuration.xml @@ -162,7 +162,7 @@ - + @@ -182,8 +182,8 @@ - - + + @@ -202,7 +202,7 @@ - + @@ -261,6 +261,14 @@ Board support package for RA8M1 - Events Renesas.RA_mcu_ra8m1.5.6.0.pack + + USB Basic + Renesas.RA.5.6.0.pack + + + USB Peripheral Communications Device Class + Renesas.RA.5.6.0.pack + @@ -273,9 +281,57 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index 29dcb912c..523b6ff55 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -32,11 +32,7 @@ #pragma GCC diagnostic ignored "-Wundef" #endif -//#include "bsp_api.h" -//#include "r_ioport.h" #include "common_data.h" - -#include "r_ioport_api.h" #include "renesas.h" #ifdef __GNUC__ @@ -204,7 +200,6 @@ void usbfs_d1fifo_handler(void) { //------------- USB1 HighSpeed -------------// #ifdef BOARD_HAS_USB_HIGHSPEED - void usbhs_interrupt_handler(void) { IRQn_Type irq = R_FSP_CurrentIrqGet(); R_BSP_IrqStatusClear(irq); @@ -223,7 +218,6 @@ void usbhs_d1fifo_handler(void) { R_BSP_IrqStatusClear(irq); // TODO not used yet } - #endif //--------------------------------------------------------------------+ diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index e234c7b16..9eca93b4d 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -15,6 +15,28 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL set(FAMILY_MCUS RAXXX ${MCU_VARIANT} CACHE INTERNAL "") +# ---------------------- +# Port & Speed Selection +# ---------------------- +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 0) +endif () +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) +endif () + +if (NOT DEFINED RHPORT_SPEED) + set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) +endif () +if (NOT DEFINED RHPORT_DEVICE_SPEED) + list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED) +endif () +if (NOT DEFINED RHPORT_HOST_SPEED) + list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED) +endif () + +cmake_print_variables(RHPORT_DEVICE RHPORT_DEVICE_SPEED RHPORT_HOST RHPORT_HOST_SPEED) + #------------------------------------ # BOARD_TARGET #------------------------------------ @@ -57,6 +79,12 @@ function(add_board_target BOARD_TARGET) ${FSP_RA}/src/bsp/mcu/all ${FSP_RA}/src/bsp/mcu/${MCU_VARIANT} ) + target_compile_definitions(${BOARD_TARGET} PUBLIC + BOARD_TUD_RHPORT=${RHPORT_DEVICE} + BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} + BOARD_TUH_RHPORT=${RHPORT_HOST} + BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} + ) update_board(${BOARD_TARGET}) diff --git a/hw/bsp/ra/family.mk b/hw/bsp/ra/family.mk index 5c7305912..6ac7c262f 100644 --- a/hw/bsp/ra/family.mk +++ b/hw/bsp/ra/family.mk @@ -4,33 +4,58 @@ include $(TOP)/$(BOARD_PATH)/board.mk # Don't include options setting in .bin file since it create unnecessary large file due to padding OBJCOPY_BIN_OPTION = --only-section .text --only-section .data --only-section .rodata --only-section .bss -# Default to port 0 fullspeed, board with port 1 highspeed should override this in board.mk -PORT ?= 0 +# ---------------------- +# Port & Speed Selection +# ---------------------- +RHPORT_SPEED ?= OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED +RHPORT_DEVICE ?= 0 +RHPORT_HOST ?= 0 +# Determine RHPORT_DEVICE_SPEED if not defined +ifndef RHPORT_DEVICE_SPEED +ifeq ($(RHPORT_DEVICE), 0) + RHPORT_DEVICE_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_DEVICE_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif + +# Determine RHPORT_HOST_SPEED if not defined +ifndef RHPORT_HOST_SPEED +ifeq ($(RHPORT_HOST), 0) + RHPORT_HOST_SPEED = $(firstword $(RHPORT_SPEED)) +else + RHPORT_HOST_SPEED = $(lastword $(RHPORT_SPEED)) +endif +endif + +# -------------- +# Compiler Flags +# -------------- CFLAGS += \ - -flto \ -DCFG_TUSB_MCU=OPT_MCU_RAXXX \ - -DBOARD_TUD_RHPORT=$(PORT) \ + -DBOARD_TUD_RHPORT=${RHPORT_DEVICE} \ + -DBOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} \ + -DBOARD_TUH_RHPORT=${RHPORT_HOST} \ + -DBOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} + +CFLAGS_GCC += \ + -flto \ -Wno-error=undef \ -Wno-error=strict-prototypes \ -Wno-error=cast-align \ -Wno-error=cast-qual \ -Wno-error=unused-but-set-variable \ -Wno-error=unused-variable \ - -nostdlib \ - -nostartfiles \ -ffreestanding -ifeq ($(PORT), 1) - CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED - $(info "Using PORT 1 HighSpeed") -else - CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED - $(info "Using PORT 0 FullSpeed") -endif - -LDFLAGS_GCC += -specs=nosys.specs -specs=nano.specs +LDFLAGS_GCC += \ + -nostartfiles -nostdlib \ + -specs=nosys.specs -specs=nano.specs +# ----------------- +# Sources & Include +# ----------------- SRC_C += \ src/portable/renesas/rusb2/dcd_rusb2.c \ src/portable/renesas/rusb2/hcd_rusb2.c \ -- cgit v1.3.1 From 380bfc0a6345f7295e2a5ff60c9712255f04a2dc Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 13 Dec 2024 17:50:00 +0700 Subject: fix portenta build, added core-m85.cmake/mk --- examples/build_system/cmake/cpu/cortex-m85.cmake | 25 ++++++++ examples/build_system/make/cpu/cortex-m85.mk | 27 ++++++++ hw/bsp/ra/boards/portenta_c33/board.cmake | 21 ++----- hw/bsp/ra/boards/portenta_c33/board.mk | 3 +- .../portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h | 17 ++++++ hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c | 11 ++++ hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h | 20 ++++++ hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c | 71 ++++++++++++++++++++++ 8 files changed, 179 insertions(+), 16 deletions(-) create mode 100644 examples/build_system/cmake/cpu/cortex-m85.cmake create mode 100644 examples/build_system/make/cpu/cortex-m85.mk create mode 100644 hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h create mode 100644 hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c create mode 100644 hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h create mode 100644 hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c (limited to 'hw') diff --git a/examples/build_system/cmake/cpu/cortex-m85.cmake b/examples/build_system/cmake/cpu/cortex-m85.cmake new file mode 100644 index 000000000..30314acbc --- /dev/null +++ b/examples/build_system/cmake/cpu/cortex-m85.cmake @@ -0,0 +1,25 @@ +if (TOOLCHAIN STREQUAL "gcc") + set(TOOLCHAIN_COMMON_FLAGS + -mthumb + -mcpu=cortex-m85 + -mfloat-abi=hard + -mfpu=fpv5-d16 + ) + set(FREERTOS_PORT GCC_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "") + +elseif (TOOLCHAIN STREQUAL "clang") + set(TOOLCHAIN_COMMON_FLAGS + --target=arm-none-eabi + -mcpu=cortex-m85 + -mfpu=fpv5-d16 + ) + set(FREERTOS_PORT GCC_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "") + +elseif (TOOLCHAIN STREQUAL "iar") + set(TOOLCHAIN_COMMON_FLAGS + --cpu cortex-m85 + --fpu VFPv5_D16 + ) + set(FREERTOS_PORT IAR_ARM_CM85_NTZ_NONSECURE CACHE INTERNAL "") + +endif () diff --git a/examples/build_system/make/cpu/cortex-m85.mk b/examples/build_system/make/cpu/cortex-m85.mk new file mode 100644 index 000000000..75e8f3aaf --- /dev/null +++ b/examples/build_system/make/cpu/cortex-m85.mk @@ -0,0 +1,27 @@ +ifeq ($(TOOLCHAIN),gcc) + CFLAGS += \ + -mthumb \ + -mcpu=cortex-m85 \ + -mfloat-abi=hard \ + -mfpu=fpv5-d16 \ + +else ifeq ($(TOOLCHAIN),clang) + CFLAGS += \ + --target=arm-none-eabi \ + -mcpu=cortex-m85 \ + -mfpu=fpv5-d16 \ + +else ifeq ($(TOOLCHAIN),iar) + CFLAGS += \ + --cpu cortex-m85 \ + --fpu VFPv5_D16 \ + + ASFLAGS += \ + --cpu cortex-m85 \ + --fpu VFPv5_D16 \ + +else + $(error "TOOLCHAIN is not supported") +endif + +FREERTOS_PORTABLE_SRC ?= $(FREERTOS_PORTABLE_PATH)/ARM_CM85_NTZ/non_secure diff --git a/hw/bsp/ra/boards/portenta_c33/board.cmake b/hw/bsp/ra/boards/portenta_c33/board.cmake index 1837d8450..520686daa 100644 --- a/hw/bsp/ra/boards/portenta_c33/board.cmake +++ b/hw/bsp/ra/boards/portenta_c33/board.cmake @@ -4,22 +4,13 @@ set(MCU_VARIANT ra6m5) set(JLINK_DEVICE R7FA6M5BH) set(DFU_UTIL_VID_PID 2341:0368) -set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${BOARD}.ld) - -# Device port default to PORT1 Highspeed -if (NOT DEFINED PORT) -set(PORT 1) +# device default to PORT 1 High Speed +if (NOT DEFINED RHPORT_DEVICE) + set(RHPORT_DEVICE 1) +endif() +if (NOT DEFINED RHPORT_HOST) + set(RHPORT_HOST 0) endif() - -# Host port will be the other port -set(HOST_PORT $) function(update_board TARGET) - target_compile_definitions(${TARGET} PUBLIC - BOARD_TUD_RHPORT=${PORT} - BOARD_TUH_RHPORT=${HOST_PORT} - # port 0 is fullspeed, port 1 is highspeed - BOARD_TUD_MAX_SPEED=$ - BOARD_TUH_MAX_SPEED=$ - ) endfunction() diff --git a/hw/bsp/ra/boards/portenta_c33/board.mk b/hw/bsp/ra/boards/portenta_c33/board.mk index 4da34306e..ab814cda6 100644 --- a/hw/bsp/ra/boards/portenta_c33/board.mk +++ b/hw/bsp/ra/boards/portenta_c33/board.mk @@ -2,7 +2,8 @@ CPU_CORE = cortex-m33 MCU_VARIANT = ra6m5 # Port 1 is highspeed -PORT ?= 1 +RHPORT_DEVICE ?= 1 +RHPORT_HOST ?= 0 JLINK_DEVICE = R7FA6M5BH DFU_UTIL_OPTION = -d 2341:0368 -a 0 diff --git a/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h new file mode 100644 index 000000000..c411386c1 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/ra_cfg/fsp_cfg/bsp/bsp_pin_cfg.h @@ -0,0 +1,17 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "r_ioport.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +#define LED1 (BSP_IO_PORT_01_PIN_07) +#define SW1 (BSP_IO_PORT_04_PIN_08) +extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA6M5BH3CFC.pincfg */ + +void BSP_PinConfigSecurityInit(); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER +#endif /* BSP_PIN_CFG_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c new file mode 100644 index 000000000..50036c0ad --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.c @@ -0,0 +1,11 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = + { + .p_api = &g_ioport_on_ioport, + .p_ctrl = &g_ioport_ctrl, + .p_cfg = &g_bsp_pin_cfg, + }; +void g_common_init(void) { +} diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h new file mode 100644 index 000000000..6a08cbee0 --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/common_data.h @@ -0,0 +1,20 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +#define IOPORT_CFG_NAME g_bsp_pin_cfg +#define IOPORT_CFG_OPEN R_IOPORT_Open +#define IOPORT_CFG_CTRL g_ioport_ctrl + +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c b/hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c new file mode 100644 index 000000000..fad79741a --- /dev/null +++ b/hw/bsp/ra/boards/portenta_c33/ra_gen/pin_data.c @@ -0,0 +1,71 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport.h" + + +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_01_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t) IOPORT_CFG_PORT_OUTPUT_LOW) + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_DEBUG) + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_FS) + }, + { + .pin = BSP_IO_PORT_04_PIN_08, + .pin_cfg = ((uint32_t) IOPORT_CFG_PORT_DIRECTION_INPUT | (uint32_t) IOPORT_CFG_PULLUP_ENABLE) + }, + { + .pin = BSP_IO_PORT_11_PIN_01, + .pin_cfg = ((uint32_t) IOPORT_CFG_PERIPHERAL_PIN | (uint32_t) IOPORT_PERIPHERAL_USB_HS) + }, +}; + +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data)/sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; + +#if BSP_TZ_SECURE_BUILD + +void R_BSP_PinCfgSecurityInit(void); + +/* Initialize SAR registers for secure pins. */ +void R_BSP_PinCfgSecurityInit(void) +{ + #if (2U == BSP_FEATURE_IOPORT_VERSION) + uint32_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #else + uint16_t pmsar[BSP_FEATURE_BSP_NUM_PMSAR]; + #endif + memset(pmsar, 0xFF, BSP_FEATURE_BSP_NUM_PMSAR * sizeof(R_PMISC->PMSAR[0])); + + + for(uint32_t i = 0; i < g_bsp_pin_cfg.number_of_pins; i++) + { + uint32_t port_pin = g_bsp_pin_cfg.p_pin_cfg_data[i].pin; + uint32_t port = port_pin >> 8U; + uint32_t pin = port_pin & 0xFFU; + pmsar[port] &= (uint16_t) ~(1U << pin); + } + + for(uint32_t i = 0; i < BSP_FEATURE_BSP_NUM_PMSAR; i++) + { + #if (2U == BSP_FEATURE_IOPORT_VERSION) + R_PMISC->PMSAR[i].PMSAR = (uint16_t) pmsar[i]; + #else + R_PMISC->PMSAR[i].PMSAR = pmsar[i]; + #endif + } + +} +#endif -- cgit v1.3.1 From 656772fc9defc73c32443259f866daadc657f23d Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 16 Dec 2024 22:03:06 +0700 Subject: make sure g_bsp_rom_registers is not dropped by linker in cmake build. always reserve 0x100 for option setting in linker to prevent possible bricked mcu --- hw/bsp/ra/boards/portenta_c33/script/fsp.ld | 3 +++ hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld | 3 +++ hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld | 3 +++ hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld | 3 +++ hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld | 3 +++ hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld | 3 +++ hw/bsp/ra/boards/uno_r4/script/fsp.ld | 3 +++ hw/bsp/ra/family.cmake | 6 +++++- 8 files changed, 26 insertions(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/bsp/ra/boards/portenta_c33/script/fsp.ld b/hw/bsp/ra/boards/portenta_c33/script/fsp.ld index 627ffe4d9..605eef7d2 100644 --- a/hw/bsp/ra/boards/portenta_c33/script/fsp.ld +++ b/hw/bsp/ra/boards/portenta_c33/script/fsp.ld @@ -173,6 +173,9 @@ SECTIONS . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; KEEP(*(.rom_registers*)) + /* Reserving 0x100 bytes of space for ROM registers. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; + /* Allocate flash write-boundary-aligned * space for sce9 wrapped public keys for mcuboot if the module is used. */ diff --git a/hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld index 627ffe4d9..605eef7d2 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld +++ b/hw/bsp/ra/boards/ra4m1_ek/script/fsp.ld @@ -173,6 +173,9 @@ SECTIONS . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; KEEP(*(.rom_registers*)) + /* Reserving 0x100 bytes of space for ROM registers. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; + /* Allocate flash write-boundary-aligned * space for sce9 wrapped public keys for mcuboot if the module is used. */ diff --git a/hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld b/hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld index 627ffe4d9..605eef7d2 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld +++ b/hw/bsp/ra/boards/ra4m3_ek/script/fsp.ld @@ -173,6 +173,9 @@ SECTIONS . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; KEEP(*(.rom_registers*)) + /* Reserving 0x100 bytes of space for ROM registers. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; + /* Allocate flash write-boundary-aligned * space for sce9 wrapped public keys for mcuboot if the module is used. */ diff --git a/hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld index 627ffe4d9..605eef7d2 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld +++ b/hw/bsp/ra/boards/ra6m1_ek/script/fsp.ld @@ -173,6 +173,9 @@ SECTIONS . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; KEEP(*(.rom_registers*)) + /* Reserving 0x100 bytes of space for ROM registers. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; + /* Allocate flash write-boundary-aligned * space for sce9 wrapped public keys for mcuboot if the module is used. */ diff --git a/hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld b/hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld index 627ffe4d9..605eef7d2 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld +++ b/hw/bsp/ra/boards/ra6m5_ek/script/fsp.ld @@ -173,6 +173,9 @@ SECTIONS . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; KEEP(*(.rom_registers*)) + /* Reserving 0x100 bytes of space for ROM registers. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; + /* Allocate flash write-boundary-aligned * space for sce9 wrapped public keys for mcuboot if the module is used. */ diff --git a/hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld b/hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld index 32cbf0b22..d7f78a915 100644 --- a/hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld +++ b/hw/bsp/ra/boards/ra8m1_ek/script/fsp.ld @@ -177,6 +177,9 @@ SECTIONS . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; KEEP(*(.rom_registers*)) + /* Reserving 0x100 bytes of space for ROM registers. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; + /* Allocate flash write-boundary-aligned * space for sce9 wrapped public keys for mcuboot if the module is used. */ diff --git a/hw/bsp/ra/boards/uno_r4/script/fsp.ld b/hw/bsp/ra/boards/uno_r4/script/fsp.ld index 627ffe4d9..605eef7d2 100644 --- a/hw/bsp/ra/boards/uno_r4/script/fsp.ld +++ b/hw/bsp/ra/boards/uno_r4/script/fsp.ld @@ -173,6 +173,9 @@ SECTIONS . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x400; KEEP(*(.rom_registers*)) + /* Reserving 0x100 bytes of space for ROM registers. */ + . = OPTION_SETTING_LENGTH > 0 ? . : __ROM_Start + 0x500; + /* Allocate flash write-boundary-aligned * space for sce9 wrapped public keys for mcuboot if the module is used. */ diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 9eca93b4d..d4d795ae5 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -54,7 +54,6 @@ function(add_board_target BOARD_TARGET) ${FSP_RA}/src/bsp/mcu/all/bsp_io.c ${FSP_RA}/src/bsp/mcu/all/bsp_irq.c ${FSP_RA}/src/bsp/mcu/all/bsp_register_protection.c - ${FSP_RA}/src/bsp/mcu/all/bsp_rom_registers.c ${FSP_RA}/src/bsp/mcu/all/bsp_sbrk.c ${FSP_RA}/src/bsp/mcu/all/bsp_security.c ${FSP_RA}/src/r_ioport/r_ioport.c @@ -125,12 +124,17 @@ function(family_configure_example TARGET RTOS) # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + # Explicitly added bsp_rom_registers here, otherwise MCU can be bricked if g_bsp_rom_registers is dropped by linker + ${FSP_RA}/src/bsp/mcu/all/bsp_rom_registers.c ) target_include_directories(${TARGET} PUBLIC # family, hw, board ${CMAKE_CURRENT_FUNCTION_LIST_DIR} ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ ) + target_compile_options(${TARGET} PUBLIC + -Wno-error=undef + ) # # RA has custom freertos port # if (NOT TARGET freertos_kernel_port) -- cgit v1.3.1 From 7e207e4f4a098fddb13efc329e57e6095aa13873 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 16 Dec 2024 23:48:44 +0700 Subject: fix warning due to bsp_rom_registers.c --- .github/workflows/pre-commit.yml | 1 + hw/bsp/ra/family.cmake | 1 + 2 files changed, 2 insertions(+) (limited to 'hw') diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml index 530484079..f751dc44d 100644 --- a/.github/workflows/pre-commit.yml +++ b/.github/workflows/pre-commit.yml @@ -33,6 +33,7 @@ jobs: - name: Build Fuzzer run: | + clang --version export CC=clang export CXX=clang++ fuzz_harness=$(ls -d test/fuzz/device/*/) diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index d4d795ae5..ceb1e48bd 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -134,6 +134,7 @@ function(family_configure_example TARGET RTOS) ) target_compile_options(${TARGET} PUBLIC -Wno-error=undef + -Wno-error=strict-prototypes ) # # RA has custom freertos port -- cgit v1.3.1 From 22a6777c2ddcdd1a3c2241d639d7d771131696d3 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 17 Dec 2024 20:53:50 +0700 Subject: enable CFG_TUD/THU_MEM_DCACHE_ENABLE for imxrt with M7 by default --- .../boards/mimxrt1170_evkb/board/clock_config.c | 14 +- .../boards/mimxrt1170_evkb/board/clock_config.h | 2 +- .../imxrt/boards/mimxrt1170_evkb/board/pin_mux.c | 15 +- .../imxrt/boards/mimxrt1170_evkb/board/pin_mux.h | 2 +- .../boards/mimxrt1170_evkb/mimxrt1170_evkb.mex | 13 +- hw/bsp/imxrt/family.c | 233 +++++++++++---------- src/common/tusb_mcu.h | 8 + 7 files changed, 150 insertions(+), 137 deletions(-) (limited to 'hw') diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c index 88b3b3770..66f1f983a 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c @@ -11,11 +11,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v12.0 +product: Clocks v14.0 processor: MIMXRT1176xxxxx package_id: MIMXRT1176DVMAA mcu_data: ksdk2_0 -processor_version: 14.0.1 +processor_version: 16.3.0 board: MIMXRT1170-EVKB * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ @@ -335,7 +335,6 @@ void BOARD_BootClockRUN(void) /* Init OSC RC 400M */ CLOCK_OSC_EnableOscRc400M(); - CLOCK_OSC_GateOscRc400M(false); /* Init OSC RC 48M */ CLOCK_OSC_EnableOsc48M(true); @@ -349,22 +348,29 @@ void BOARD_BootClockRUN(void) { } - /* Switch both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */ + /* Switch core M7 clock root to OscRC48MDiv2 first */ #if __CORTEX_M == 7 rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); +#endif + /* Switch core M7 systick clock root to OscRC48MDiv2 first */ +#if __CORTEX_M == 7 rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); #endif + /* Switch core M4 clock root to OscRC48MDiv2 first */ #if __CORTEX_M == 4 rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); +#endif + /* Switch the Bus_Lpsr clock root to OscRC48MDiv2 first */ +#if __CORTEX_M == 4 rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h index 4a4d35eaa..f68724314 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.h @@ -48,7 +48,7 @@ void BOARD_InitBootClocks(void); #define BOARD_BOOTCLOCKRUN_ARM_PLL_CLK 996000000UL /* Clock consumers of ARM_PLL_CLK output : N/A */ #define BOARD_BOOTCLOCKRUN_ASRC_CLK_ROOT 24000000UL /* Clock consumers of ASRC_CLK_ROOT output : ASRC */ #define BOARD_BOOTCLOCKRUN_AXI_CLK_ROOT 996000000UL /* Clock consumers of AXI_CLK_ROOT output : FLEXRAM */ -#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL /* Clock consumers of BUS_CLK_ROOT output : ADC_ETC, AOI1, AOI2, CAAM, CAN1, CAN2, CM7_GPIO2, CM7_GPIO3, CMP1, CMP2, CMP3, CMP4, CSI, DAC, DMA0, DMAMUX0, DSI_HOST, EMVSIM1, EMVSIM2, ENC1, ENC2, ENC3, ENC4, ENET, ENET_1G, ENET_QOS, EWM, FLEXIO1, FLEXIO2, FLEXSPI1, FLEXSPI2, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, IEE_APC, IOMUXC, IOMUXC_GPR, KPP, LCDIF, LCDIFV2, LPADC1, LPADC2, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART10, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, MECC1, MECC2, MIPI_CSI2RX, PIT1, PWM1, PWM2, PWM3, PWM4, PXP, RTWDOG3, SAI1, SAI2, SAI3, SPDIF, TMR1, TMR2, TMR3, TMR4, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */ +#define BOARD_BOOTCLOCKRUN_BUS_CLK_ROOT 240000000UL /* Clock consumers of BUS_CLK_ROOT output : ADC_ETC, AOI1, AOI2, CAAM, CAN1, CAN2, CM7_GPIO2, CM7_GPIO3, CMP1, CMP2, CMP3, CMP4, CSI, DAC, DMA0, DMAMUX0, DSI_HOST, EMVSIM1, EMVSIM2, ENC1, ENC2, ENC3, ENC4, ENET, ENET_1G, ENET_QOS, EWM, FLEXIO1, FLEXIO2, FLEXSPI1, FLEXSPI2, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, IEE_APC, IEE__IEE_RT1170, IOMUXC, IOMUXC_GPR, KPP, LCDIF, LCDIFV2, LPADC1, LPADC2, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART10, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, MECC1, MECC2, MIPI_CSI2RX, PIT1, PWM1, PWM2, PWM3, PWM4, PXP, RTWDOG3, SAI1, SAI2, SAI3, SPDIF, TMR1, TMR2, TMR3, TMR4, USBPHY1, USBPHY2, USB_OTG1, USB_OTG2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC, XRDC2_D0, XRDC2_D1 */ #define BOARD_BOOTCLOCKRUN_BUS_LPSR_CLK_ROOT 160000000UL /* Clock consumers of BUS_LPSR_CLK_ROOT output : CAN3, GPIO10, GPIO11, GPIO12, GPIO7, GPIO8, GPIO9, IOMUXC_LPSR, LPI2C5, LPI2C6, LPSPI5, LPSPI6, LPUART11, LPUART12, MUA, MUB, PDM, PIT2, RDC, RTWDOG4, SAI4, SNVS, XRDC2_D0, XRDC2_D1 */ #define BOARD_BOOTCLOCKRUN_CAN1_CLK_ROOT 24000000UL /* Clock consumers of CAN1_CLK_ROOT output : CAN1 */ #define BOARD_BOOTCLOCKRUN_CAN2_CLK_ROOT 24000000UL /* Clock consumers of CAN2_CLK_ROOT output : CAN2 */ diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c index 81ffb35e3..2c83fb55e 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c @@ -6,11 +6,11 @@ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Pins v14.0 +product: Pins v16.0 processor: MIMXRT1176xxxxx package_id: MIMXRT1176DVMAA mcu_data: ksdk2_0 -processor_version: 14.0.1 +processor_version: 16.3.0 board: MIMXRT1170-EVKB external_user_signals: {} pin_labels: @@ -90,7 +90,7 @@ void BOARD_InitPins(void) { IOMUXC_GPIO_AD_04_GPIO9_IO03, /* GPIO_AD_04 PAD functional properties : */ 0x02U); /* Slew Rate Field: Slow Slew Rate Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Disable, Highz + Pull / Keep Select Field: Pull Disable Pull Up / Down Config. Field: Weak pull down Open Drain Field: Disabled Domain write protection: Both cores are allowed @@ -99,7 +99,7 @@ void BOARD_InitPins(void) { IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */ 0x02U); /* Slew Rate Field: Slow Slew Rate Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Disable, Highz + Pull / Keep Select Field: Pull Disable Pull Up / Down Config. Field: Weak pull down Open Drain Field: Disabled Domain write protection: Both cores are allowed @@ -108,22 +108,19 @@ void BOARD_InitPins(void) { IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 PAD functional properties : */ 0x02U); /* Slew Rate Field: Slow Slew Rate Drive Strength Field: high drive strength - Pull / Keep Select Field: Pull Disable, Highz + Pull / Keep Select Field: Pull Disable Pull Up / Down Config. Field: Weak pull down Open Drain Field: Disabled Domain write protection: Both cores are allowed Domain write protection lock: Neither of DWP bits is locked */ IOMUXC_SetPinConfig( IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG PAD functional properties : */ - 0x0EU); /* Slew Rate Field: Slow Slew Rate - Drive Strength Field: high driver - Pull / Keep Select Field: Pull Enable + 0x0EU); /* Pull / Keep Select Field: Pull Enable Pull Up / Down Config. Field: Weak pull up Open Drain SNVS Field: Disabled Domain write protection: Both cores are allowed Domain write protection lock: Neither of DWP bits is locked */ } - /*********************************************************************************************************************** * EOF **********************************************************************************************************************/ diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h index 550bd1474..a5b621476 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h @@ -46,7 +46,7 @@ void BOARD_InitBootPins(void); #define BOARD_INITPINS_USER_LED_GPIO_PIN 3U /*!< GPIO pin number */ #define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */ -/* WAKEUP (coord T8), USER_BUTTON */ +/* WAKEUP (coord T8), USER_BUTTON/SW7 */ /* Routed pin properties */ #define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO13 /*!< Peripheral name */ #define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex b/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex index e68b9ea7e..a4c8917f7 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex @@ -1,5 +1,5 @@ - + MIMXRT1176xxxxx MIMXRT1176DVMAA @@ -19,18 +19,17 @@ false - + - 14.0.1 + 16.3.0 - @@ -44,7 +43,7 @@ true - + true @@ -104,13 +103,13 @@ - + - 14.0.1 + 16.3.0 diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index ce4a6bbc9..f365981f5 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -24,10 +24,10 @@ * This file is part of the TinyUSB stack. */ -#include "board.h" +#include "bsp/board_api.h" #include "board/clock_config.h" #include "board/pin_mux.h" -#include "bsp/board_api.h" +#include "board.h" // Suppress warning caused by mcu driver #ifdef __GNUC__ @@ -47,14 +47,14 @@ #endif /* --- Note about USB buffer RAM --- -For M7 core it's recommended to put USB buffer in DTCM for better performance (flexspi_nor linker default) -Otherwise you have to put the buffer in a non-cacheable section by configurate MPU manually or using BOARD_ConfigMPU(): -- Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) -- (IAR only) Change __NCACHE_REGION_SIZE in linker script to cover the size of non-cacheable section, multiple of 2^N - -For secondary M4 core, the USB controller doesn't support transfer from DTCM so OCRAM must be used: -- __NCACHE_REGION_SIZE is defined by the linker script by default -- Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) + For M7 core it's recommended to put USB buffer in DTCM for better performance (flexspi_nor linker default) + Otherwise you have to put the buffer in a non-cacheable section by configurate MPU manually or using BOARD_ConfigMPU(): + - Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) + - (IAR only) Change __NCACHE_REGION_SIZE in linker script to cover the size of non-cacheable section, multiple of 2^N + + For secondary M4 core, the USB controller doesn't support transfer from DTCM so OCRAM must be used: + - __NCACHE_REGION_SIZE is defined by the linker script by default + - Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) */ static void BOARD_ConfigMPU(void); @@ -148,7 +148,112 @@ void board_init(void) { #endif } -/* MPU configuration. */ +//--------------------------------------------------------------------+ +// USB Interrupt Handler +//--------------------------------------------------------------------+ +void USB_OTG1_IRQHandler(void) { + tusb_int_handler(0, true); +} + +void USB_OTG2_IRQHandler(void) { + tusb_int_handler(1, true); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) { + GPIO_PinWrite(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); +} + +uint32_t board_button_read(void) { + return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + (void) max_len; + +#if FSL_FEATURE_OCOTP_HAS_TIMING_CTRL + OCOTP_Init(OCOTP, CLOCK_GetFreq(kCLOCK_IpgClk)); +#else + OCOTP_Init(OCOTP, 0u); +#endif + + // Reads shadow registers 0x01 - 0x04 (Configuration and Manufacturing Info) + // into 8 bit wide destination, avoiding punning. + for (int i = 0; i < 4; ++i) { + uint32_t wr = OCOTP_ReadFuseShadowRegister(OCOTP, i + 1); + for (int j = 0; j < 4; j++) { + id[i * 4 + j] = wr & 0xff; + wr >>= 8; + } + } + OCOTP_Deinit(OCOTP); + + return 16; +} + +int board_uart_read(uint8_t *buf, int len) { + int count = 0; + + while (count < len) { + uint8_t const rx_count = LPUART_GetRxFifoCount(UART_PORT); + if (!rx_count) { + // clear all error flag if any + uint32_t status_flags = LPUART_GetStatusFlags(UART_PORT); + status_flags &= (kLPUART_RxOverrunFlag | kLPUART_ParityErrorFlag | kLPUART_FramingErrorFlag | + kLPUART_NoiseErrorFlag); + LPUART_ClearStatusFlags(UART_PORT, status_flags); + break; + } + + for (int i = 0; i < rx_count; i++) { + buf[count] = LPUART_ReadByte(UART_PORT); + count++; + } + } + + return count; +} + +int board_uart_write(void const *buf, int len) { + LPUART_WriteBlocking(UART_PORT, (uint8_t const *) buf, len); + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; +void SysTick_Handler(void) { + system_ticks++; +} + +uint32_t board_millis(void) { + return system_ticks; +} +#endif + + +#ifndef __ICCARM__ +// Implement _start() since we use linker flag '-nostartfiles'. +// Requires defined __STARTUP_CLEAR_BSS, +extern int main(void); +TU_ATTR_UNUSED void _start(void) { + // called by startup code + main(); + while (1) {} +} + +#ifdef __clang__ +void _exit(int __status) { + while (1) {} +} +#endif +#endif + +//-------------------------------------------------------------------- +// MPU configuration +//-------------------------------------------------------------------- #if __CORTEX_M == 7 static void BOARD_ConfigMPU(void) { #if defined(__CC_ARM) || defined(__ARMCC_VERSION) @@ -343,7 +448,9 @@ static void BOARD_ConfigMPU(void) { SCB_EnableICache(); #endif } + #elif __CORTEX_M == 4 + void BOARD_ConfigMPU(void) { #if defined(__CC_ARM) || defined(__ARMCC_VERSION) extern uint32_t Image$$RW_m_ncache$$Base[]; @@ -525,107 +632,3 @@ void BOARD_ConfigMPU(void) { LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK; } #endif - -//--------------------------------------------------------------------+ -// USB Interrupt Handler -//--------------------------------------------------------------------+ -void USB_OTG1_IRQHandler(void) { - tusb_int_handler(0, true); -} - -void USB_OTG2_IRQHandler(void) { - tusb_int_handler(1, true); -} - -//--------------------------------------------------------------------+ -// Board porting API -//--------------------------------------------------------------------+ - -void board_led_write(bool state) { - GPIO_PinWrite(LED_PORT, LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); -} - -uint32_t board_button_read(void) { - return BUTTON_STATE_ACTIVE == GPIO_PinRead(BUTTON_PORT, BUTTON_PIN); -} - -size_t board_get_unique_id(uint8_t id[], size_t max_len) { - (void) max_len; - -#if FSL_FEATURE_OCOTP_HAS_TIMING_CTRL - OCOTP_Init(OCOTP, CLOCK_GetFreq(kCLOCK_IpgClk)); -#else - OCOTP_Init(OCOTP, 0u); -#endif - - // Reads shadow registers 0x01 - 0x04 (Configuration and Manufacturing Info) - // into 8 bit wide destination, avoiding punning. - for (int i = 0; i < 4; ++i) { - uint32_t wr = OCOTP_ReadFuseShadowRegister(OCOTP, i + 1); - for (int j = 0; j < 4; j++) { - id[i * 4 + j] = wr & 0xff; - wr >>= 8; - } - } - OCOTP_Deinit(OCOTP); - - return 16; -} - -int board_uart_read(uint8_t *buf, int len) { - int count = 0; - - while (count < len) { - uint8_t const rx_count = LPUART_GetRxFifoCount(UART_PORT); - if (!rx_count) { - // clear all error flag if any - uint32_t status_flags = LPUART_GetStatusFlags(UART_PORT); - status_flags &= (kLPUART_RxOverrunFlag | kLPUART_ParityErrorFlag | kLPUART_FramingErrorFlag | - kLPUART_NoiseErrorFlag); - LPUART_ClearStatusFlags(UART_PORT, status_flags); - break; - } - - for (int i = 0; i < rx_count; i++) { - buf[count] = LPUART_ReadByte(UART_PORT); - count++; - } - } - - return count; -} - -int board_uart_write(void const *buf, int len) { - LPUART_WriteBlocking(UART_PORT, (uint8_t const *) buf, len); - return len; -} - -#if CFG_TUSB_OS == OPT_OS_NONE -volatile uint32_t system_ticks = 0; -void SysTick_Handler(void) { - system_ticks++; -} - -uint32_t board_millis(void) { - return system_ticks; -} -#endif - - -#ifndef __ICCARM__ -// Implement _start() since we use linker flag '-nostartfiles'. -// Requires defined __STARTUP_CLEAR_BSS, -extern int main(void); -TU_ATTR_UNUSED void _start(void) { - // called by startup code - main(); - while (1) {} -} - - #ifdef __clang__ -void _exit(int __status) { - while (1) {} -} - #endif - -#endif diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index d282c890d..a0175d664 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -108,12 +108,20 @@ #define TUP_DCD_ENDPOINT_MAX 16 #elif TU_CHECK_MCU(OPT_MCU_MIMXRT1XXX) + #include "fsl_device_registers.h" + #define TUP_USBIP_CHIPIDEA_HS #define TUP_USBIP_EHCI #define TUP_DCD_ENDPOINT_MAX 8 #define TUP_RHPORT_HIGHSPEED 1 + #if __CORTEX_M == 7 + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1 + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1 + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE 32 + #endif + #elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K) #define TUP_USBIP_CHIPIDEA_FS #define TUP_USBIP_CHIPIDEA_FS_KINETIS -- cgit v1.3.1 From 6a36c74b10b25f1455d83ba473fff52a9dbcc6d2 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Dec 2024 09:11:09 +0700 Subject: embed metadata to family.c and board.h to generate supported boards doc --- docs/info/changelog.rst | 2 - docs/reference/boards.rst | 315 +++++++++++++++++++++ docs/reference/index.rst | 3 +- .../broadcom_32bit/boards/raspberrypi_zero/board.h | 5 + hw/bsp/broadcom_32bit/family.c | 4 + .../broadcom_64bit/boards/raspberrypi_cm4/board.h | 5 + .../boards/raspberrypi_zero2/board.h | 5 + hw/bsp/broadcom_64bit/family.c | 4 + hw/bsp/brtmm90x/boards/mm900evxb/board.h | 5 + hw/bsp/brtmm90x/family.c | 4 + hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h | 5 + hw/bsp/ch32f20x/family.c | 4 + hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.h | 5 + hw/bsp/ch32v10x/family.c | 4 + hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h | 5 + hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h | 5 + hw/bsp/ch32v20x/boards/nanoch32v203/board.h | 5 + hw/bsp/ch32v20x/family.c | 4 + hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h | 5 + hw/bsp/ch32v307/family.c | 4 + hw/bsp/da1469x/boards/da14695_dk_usb/board.h | 5 + hw/bsp/da1469x/boards/da1469x_dk_pro/board.h | 5 + hw/bsp/da1469x/family.c | 4 + .../boards/adafruit_feather_esp32_v2/board.h | 5 + .../boards/adafruit_feather_esp32s2/board.h | 5 + .../boards/adafruit_feather_esp32s3/board.h | 5 + .../boards/adafruit_magtag_29gray/board.h | 5 + .../boards/adafruit_metro_esp32s2/board.h | 5 + hw/bsp/espressif/boards/espressif_addax_1/board.h | 5 + .../espressif/boards/espressif_c3_devkitc/board.h | 5 + .../espressif/boards/espressif_c6_devkitc/board.h | 5 + hw/bsp/espressif/boards/espressif_kaluga_1/board.h | 5 + .../boards/espressif_p4_function_ev/board.h | 5 + .../espressif/boards/espressif_s2_devkitc/board.h | 5 + .../espressif/boards/espressif_s3_devkitc/board.h | 5 + .../espressif/boards/espressif_s3_devkitm/board.h | 5 + hw/bsp/espressif/boards/espressif_saola_1/board.h | 5 + hw/bsp/espressif/boards/family.c | 4 + hw/bsp/f1c100s/boards/f1c100s/board.h | 5 + hw/bsp/f1c100s/family.c | 4 + hw/bsp/fomu/boards/fomu/board.h | 5 + hw/bsp/fomu/family.c | 4 + hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h | 5 + hw/bsp/gd32vf103/family.c | 4 + hw/bsp/imxrt/boards/metro_m7_1011/board.h | 5 + hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h | 5 + hw/bsp/imxrt/boards/mimxrt1010_evk/board.h | 5 + hw/bsp/imxrt/boards/mimxrt1015_evk/board.h | 5 + hw/bsp/imxrt/boards/mimxrt1020_evk/board.h | 5 + hw/bsp/imxrt/boards/mimxrt1024_evk/board.h | 5 + hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h | 5 + hw/bsp/imxrt/boards/mimxrt1060_evk/board.h | 5 + hw/bsp/imxrt/boards/mimxrt1064_evk/board.h | 5 + hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h | 5 + hw/bsp/imxrt/boards/teensy_40/board.h | 5 +- hw/bsp/imxrt/boards/teensy_41/board.h | 5 +- hw/bsp/imxrt/family.c | 4 + hw/bsp/kinetis_k/boards/frdm_k64f/board.h | 5 + hw/bsp/kinetis_k/boards/teensy_35/board.h | 5 + hw/bsp/kinetis_k/family.c | 4 + hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h | 4 + hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h | 4 + hw/bsp/kinetis_k32l2/boards/kuiic/board.h | 4 + hw/bsp/kinetis_k32l2/family.c | 4 + hw/bsp/kinetis_kl/boards/frdm_kl25z/board.h | 5 + hw/bsp/kinetis_kl/family.c | 4 + hw/bsp/lpc11/boards/lpcxpresso11u37/board.h | 5 + hw/bsp/lpc11/boards/lpcxpresso11u68/board.h | 5 + hw/bsp/lpc11/family.c | 4 + hw/bsp/lpc13/boards/lpcxpresso1347/board.h | 5 + hw/bsp/lpc13/family.c | 4 + hw/bsp/lpc15/boards/lpcxpresso1549/board.h | 5 + hw/bsp/lpc15/family.c | 4 + hw/bsp/lpc17/boards/lpcxpresso1769/board.h | 5 + hw/bsp/lpc17/boards/mbed1768/board.h | 5 + hw/bsp/lpc17/family.c | 4 + hw/bsp/lpc18/boards/lpcxpresso18s37/board.h | 5 + hw/bsp/lpc18/boards/mcb1800/board.h | 5 + hw/bsp/lpc18/family.c | 4 + hw/bsp/lpc40/boards/ea4088_quickstart/board.h | 5 + hw/bsp/lpc40/family.c | 4 + hw/bsp/lpc43/boards/ea4357/board.h | 5 + hw/bsp/lpc43/boards/lpcxpresso43s67/board.h | 5 + hw/bsp/lpc43/family.c | 4 + hw/bsp/lpc51/boards/lpcxpresso51u68/board.h | 5 + hw/bsp/lpc51/family.c | 4 + hw/bsp/lpc54/boards/lpcxpresso54114/board.h | 5 + hw/bsp/lpc54/boards/lpcxpresso54608/board.h | 5 + hw/bsp/lpc54/boards/lpcxpresso54628/board.h | 5 + hw/bsp/lpc54/family.c | 4 + hw/bsp/lpc55/boards/double_m33_express/board.h | 5 + hw/bsp/lpc55/boards/lpcxpresso55s28/board.h | 5 + hw/bsp/lpc55/boards/lpcxpresso55s69/board.h | 5 + hw/bsp/lpc55/boards/mcu_link/board.h | 5 + hw/bsp/lpc55/family.c | 4 + hw/bsp/max32650/boards/max32650evkit/board.h | 5 + hw/bsp/max32650/boards/max32650fthr/board.h | 5 + hw/bsp/max32650/boards/max32651evkit/board.h | 5 + hw/bsp/max32650/family.c | 4 + hw/bsp/max32666/boards/max32666evkit/board.h | 5 + hw/bsp/max32666/boards/max32666fthr/board.h | 5 + hw/bsp/max32666/family.c | 4 + hw/bsp/max32690/boards/apard32690/board.h | 5 + hw/bsp/max32690/boards/max32690evkit/board.h | 5 + hw/bsp/max32690/family.c | 4 + hw/bsp/max78002/boards/max78002evkit/board.h | 5 + hw/bsp/max78002/family.c | 4 + hw/bsp/mcx/boards/frdm_mcxa153/board.h | 5 + hw/bsp/mcx/boards/frdm_mcxn947/board.h | 5 + hw/bsp/mcx/boards/mcxn947brk/board.h | 5 + hw/bsp/mcx/family.c | 4 + hw/bsp/mm32/boards/mm32f327x_mb39/board.h | 5 + hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.h | 5 + hw/bsp/mm32/family.c | 4 + hw/bsp/msp430/boards/msp_exp430f5529lp/board.h | 5 + hw/bsp/msp430/family.c | 4 + hw/bsp/msp432e4/boards/msp_exp432e401y/board.h | 5 + hw/bsp/msp432e4/family.c | 4 + hw/bsp/nrf/boards/adafruit_clue/board.h | 5 + hw/bsp/nrf/boards/arduino_nano33_ble/board.h | 5 + .../nrf/boards/circuitplayground_bluefruit/board.h | 5 + hw/bsp/nrf/boards/feather_nrf52840_express/board.h | 5 + hw/bsp/nrf/boards/feather_nrf52840_sense/board.h | 5 + hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h | 5 + hw/bsp/nrf/boards/pca10056/board.h | 5 + hw/bsp/nrf/boards/pca10059/board.h | 5 + hw/bsp/nrf/boards/pca10095/board.h | 5 + hw/bsp/nrf/boards/pca10100/board.h | 5 + hw/bsp/nrf/family.c | 4 + hw/bsp/pic32mz/boards/olimex_emz64/board.h | 43 +++ hw/bsp/pic32mz/boards/olimex_hmz144/board.h | 43 +++ hw/bsp/pic32mz/family.c | 4 + hw/bsp/ra/boards/portenta_c33/board.h | 5 + hw/bsp/ra/boards/ra2a1_ek/board.h | 5 + hw/bsp/ra/boards/ra4m1_ek/board.h | 5 + hw/bsp/ra/boards/ra4m3_ek/board.h | 5 + hw/bsp/ra/boards/ra6m1_ek/board.h | 5 + hw/bsp/ra/boards/ra6m5_ek/board.h | 5 + hw/bsp/ra/boards/ra8m1_ek/board.h | 5 + hw/bsp/ra/boards/uno_r4/board.h | 5 + hw/bsp/ra/family.c | 4 + hw/bsp/rp2040/board.h | 5 + hw/bsp/rp2040/family.c | 4 + hw/bsp/rx/boards/gr_citrus/board.h | 43 +++ hw/bsp/rx/boards/rx65n_target/board.h | 43 +++ hw/bsp/samd11/boards/cynthion_d11/board.h | 5 + hw/bsp/samd11/boards/samd11_xplained/board.h | 5 + hw/bsp/samd11/family.c | 4 + hw/bsp/samd21/boards/atsamd21_xpro/board.h | 5 + .../boards/circuitplayground_express/board.h | 5 + hw/bsp/samd21/boards/curiosity_nano/board.h | 5 + hw/bsp/samd21/boards/cynthion_d21/board.h | 5 + hw/bsp/samd21/boards/feather_m0_express/board.h | 5 + hw/bsp/samd21/boards/itsybitsy_m0/board.h | 5 + hw/bsp/samd21/boards/metro_m0_express/board.h | 5 + hw/bsp/samd21/boards/qtpy/board.h | 5 + hw/bsp/samd21/boards/seeeduino_xiao/board.h | 5 + .../samd21/boards/sparkfun_samd21_mini_usb/board.h | 5 + hw/bsp/samd21/boards/trinket_m0/board.h | 5 + hw/bsp/samd21/family.c | 4 + hw/bsp/samd5x_e5x/boards/d5035_01/board.h | 5 + .../samd5x_e5x/boards/feather_m4_express/board.h | 5 + hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h | 5 + hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h | 5 + hw/bsp/samd5x_e5x/boards/pybadge/board.h | 5 + hw/bsp/samd5x_e5x/boards/pyportal/board.h | 5 + hw/bsp/samd5x_e5x/boards/same54_xplained/board.h | 5 + hw/bsp/samd5x_e5x/family.c | 4 + hw/bsp/samg/boards/samg55_xplained/board.h | 5 + hw/bsp/samg/family.c | 4 + hw/bsp/saml2x/boards/atsaml21_xpro/board.h | 5 + hw/bsp/saml2x/boards/saml22_feather/board.h | 5 + hw/bsp/saml2x/boards/sensorwatch_m0/board.h | 5 + hw/bsp/saml2x/family.c | 4 + hw/bsp/stm32c0/boards/stm32c071nucleo/board.h | 5 + hw/bsp/stm32c0/family.c | 4 + hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h | 5 + hw/bsp/stm32f0/boards/stm32f072disco/board.h | 5 + hw/bsp/stm32f0/boards/stm32f072eval/board.h | 5 + hw/bsp/stm32f0/family.c | 4 + hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h | 5 + hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h | 5 + hw/bsp/stm32f1/boards/stm32f103ze_iar/board.h | 5 + hw/bsp/stm32f1/family.c | 4 + hw/bsp/stm32f2/boards/stm32f207nucleo/board.h | 6 + hw/bsp/stm32f2/family.c | 4 + hw/bsp/stm32f3/boards/stm32f303disco/board.h | 6 + hw/bsp/stm32f3/family.c | 4 + hw/bsp/stm32f4/boards/feather_stm32f405/board.h | 5 + hw/bsp/stm32f4/boards/pyboardv11/board.h | 5 + hw/bsp/stm32f4/boards/stm32f401blackpill/board.h | 5 + hw/bsp/stm32f4/boards/stm32f407blackvet/board.h | 5 + hw/bsp/stm32f4/boards/stm32f407disco/board.h | 5 + hw/bsp/stm32f4/boards/stm32f411blackpill/board.h | 5 + hw/bsp/stm32f4/boards/stm32f411disco/board.h | 5 + hw/bsp/stm32f4/boards/stm32f412disco/board.h | 5 + hw/bsp/stm32f4/boards/stm32f412nucleo/board.h | 5 + hw/bsp/stm32f4/boards/stm32f439nucleo/board.h | 5 + hw/bsp/stm32f4/family.c | 4 + hw/bsp/stm32f7/boards/stlinkv3mini/board.h | 5 + hw/bsp/stm32f7/boards/stm32f723disco/board.h | 5 + hw/bsp/stm32f7/boards/stm32f746disco/board.h | 5 + hw/bsp/stm32f7/boards/stm32f746nucleo/board.h | 5 + hw/bsp/stm32f7/boards/stm32f767nucleo/board.h | 5 + hw/bsp/stm32f7/boards/stm32f769disco/board.h | 5 + hw/bsp/stm32f7/family.c | 4 + hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h | 5 + hw/bsp/stm32g0/family.c | 4 + hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h | 5 + hw/bsp/stm32g4/boards/stm32g474nucleo/board.h | 5 + hw/bsp/stm32g4/boards/stm32g491nucleo/board.h | 5 + hw/bsp/stm32g4/family.c | 4 + hw/bsp/stm32h5/boards/stm32h503nucleo/board.h | 5 + hw/bsp/stm32h5/boards/stm32h563nucleo/board.h | 5 + hw/bsp/stm32h5/boards/stm32h573i_dk/board.h | 5 + hw/bsp/stm32h5/family.c | 3 + hw/bsp/stm32h7/boards/daisyseed/board.h | 5 + hw/bsp/stm32h7/boards/stm32h723nucleo/board.h | 5 + hw/bsp/stm32h7/boards/stm32h743eval/board.h | 6 +- hw/bsp/stm32h7/boards/stm32h743nucleo/board.h | 5 + hw/bsp/stm32h7/boards/stm32h745disco/board.h | 5 + hw/bsp/stm32h7/boards/stm32h750_weact/board.h | 5 + hw/bsp/stm32h7/boards/stm32h750bdk/board.h | 5 + hw/bsp/stm32h7/boards/waveshare_openh743i/board.h | 5 + hw/bsp/stm32h7/family.c | 4 + hw/bsp/stm32l0/boards/stm32l052dap52/board.h | 5 + hw/bsp/stm32l0/boards/stm32l0538disco/board.h | 5 + hw/bsp/stm32l0/family.c | 4 + hw/bsp/stm32l4/boards/stm32l412nucleo/board.h | 5 + hw/bsp/stm32l4/boards/stm32l476disco/board.h | 5 + hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h | 5 + hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h | 5 + hw/bsp/stm32l4/family.c | 4 + hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h | 5 + hw/bsp/stm32u5/boards/stm32u545nucleo/board.h | 5 + hw/bsp/stm32u5/boards/stm32u575eval/board.h | 5 + hw/bsp/stm32u5/boards/stm32u575nucleo/board.h | 5 + hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h | 5 + hw/bsp/stm32u5/family.c | 4 + hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h | 5 + hw/bsp/stm32wb/family.c | 4 + hw/bsp/tm4c/boards/ek_tm4c123gxl/board.h | 5 + hw/bsp/tm4c/family.c | 4 + hw/bsp/xmc4000/boards/xmc4500_relax/board.h | 5 + hw/bsp/xmc4000/boards/xmc4700_relax/board.h | 5 + hw/bsp/xmc4000/family.c | 4 + tools/gen_doc.py | 78 ++++- 247 files changed, 1697 insertions(+), 7 deletions(-) create mode 100644 docs/reference/boards.rst create mode 100644 hw/bsp/pic32mz/boards/olimex_emz64/board.h create mode 100644 hw/bsp/pic32mz/boards/olimex_hmz144/board.h create mode 100644 hw/bsp/rx/boards/gr_citrus/board.h create mode 100644 hw/bsp/rx/boards/rx65n_target/board.h (limited to 'hw') diff --git a/docs/info/changelog.rst b/docs/info/changelog.rst index a69705bde..0a34c0842 100644 --- a/docs/info/changelog.rst +++ b/docs/info/changelog.rst @@ -17,7 +17,6 @@ General - Build ARM IAR with CircleCI - Improve HIL with dual/host_info_to_device_cdc optional for pico/pico2, enable dwc2 dma test - API Changes ----------- @@ -31,7 +30,6 @@ API Changes - ``CFG_TUD/TUH_DWC2_SLAVE_ENABLE`` enable dwc2 slave mode - ``CFG_TUD/TUH_DWC2_DMA_ENABLE`` enable dwc2 dma mode - Controller Driver (DCD & HCD) ----------------------------- diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst new file mode 100644 index 000000000..424336dad --- /dev/null +++ b/docs/reference/boards.rst @@ -0,0 +1,315 @@ +**************** +Supported Boards +**************** + +Following boards are supported and can be used to run stock examples + + + +Analog Devices +============== + +============= ================ ======== =========================================================================================================================== ====== +Board Name Family URL Note +============= ================ ======== =========================================================================================================================== ====== +max32650evkit MAX32650 EVKIT max32650 https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html#eb-overview +max32650fthr MAX32650 Feather max32650 https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html +max32651evkit MAX32651 EVKIT max32650 https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32651-evkit.html +max32666evkit MAX32666 EVKIT max32666 https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html +max32666fthr MAX32666 Feather max32666 https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html +apard32690 APARD32690-SL max32690 https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html +max32690evkit MAX32690 EVKIT max32690 https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html +max78002evkit MAX78002 EVKIT max78002 https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html +============= ================ ======== =========================================================================================================================== ====== + +Bridgetek +========= + +========= ========= ======== ===================================== ====== +Board Name Family URL Note +========= ========= ======== ===================================== ====== +mm900evxb MM900EVxB brtmm90x https://brtchip.com/product/mm900ev1b +========= ========= ======== ===================================== ====== + +Espressif +========= + +========================= ============================== ========= ======================================================================================================== ====== +Board Name Family URL Note +========================= ============================== ========= ======================================================================================================== ====== +adafruit_feather_esp32_v2 Adafruit Feather ESP32 v2 espressif https://www.adafruit.com/product/5400 +adafruit_feather_esp32s2 Adafruit Feather ESP32S2 espressif https://www.adafruit.com/product/5000 +adafruit_feather_esp32s3 Adafruit Feather ESP32S3 espressif https://www.adafruit.com/product/5323 +adafruit_magtag_29gray Adafruit MagTag 2.9" Grayscale espressif https://www.adafruit.com/product/4800 +adafruit_metro_esp32s2 Adafruit Metro ESP32-S2 espressif https://www.adafruit.com/product/4775 +espressif_addax_1 Espresif Addax-1 espressif n/a +espressif_c3_devkitc Espresif C3 DevKitC espressif https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32c3/esp32-c3-devkitc-02/index.html +espressif_c6_devkitc Espresif C6 DevKitC espressif https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32c6/esp32-c6-devkitc-1/index.html +espressif_kaluga_1 Espresif Kaluga 1 espressif https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-kaluga-1/index.html +espressif_p4_function_ev Espresif P4 Function EV espressif https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32p4/esp32-p4-function-ev-board/index.html +espressif_s2_devkitc Espresif S2 DevKitC espressif https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-devkitc-1/index.html +espressif_s3_devkitc Espresif S3 DevKitC espressif https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s3/esp32-s3-devkitc-1/index.html +espressif_s3_devkitm Espresif S3 DevKitM espressif https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s3/esp32-s3-devkitm-1/index.html +espressif_saola_1 Espresif S2 Saola 1 espressif https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-saola-1/index.html +========================= ============================== ========= ======================================================================================================== ====== + +GigaDevice +========== + +================== ================== ========= ============================= ====== +Board Name Family URL Note +================== ================== ========= ============================= ====== +sipeed_longan_nano Sipeed Longan Nano gd32vf103 https://longan.sipeed.com/en/ +================== ================== ========= ============================= ====== + +Infineon +======== + +============= ================= ======== ============================================================================= ====== +Board Name Family URL Note +============= ================= ======== ============================================================================= ====== +xmc4500_relax XMC4500 relax kit xmc4000 https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc45_relax_v1/ +xmc4700_relax XMC4700 relax kit xmc4000 https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc47_relax_v1/ +============= ================= ======== ============================================================================= ====== + +Microchip +========= + +========================= =================================== ========== ================================================================================= ====== +Board Name Family URL Note +========================= =================================== ========== ================================================================================= ====== +olimex_emz64 Olimex PIC32-EMZ64 pic32mz https://www.olimex.com/Products/PIC/Development/PIC32-EMZ64/open-source-hardware +olimex_hmz144 Olimex PIC32-HMZ144 pic32mz https://www.olimex.com/Products/PIC/Development/PIC32-HMZ144/open-source-hardware +cynthion_d11 Great Scott Gadgets Cynthion samd11 https://greatscottgadgets.com/cynthion/ +samd11_xplained SAMD11 Xplained Pro samd11 https://www.microchip.com/en-us/development-tool/ATSAMD11-XPRO +atsamd21_xpro SAMD21 Xplained Pro samd21 https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAMD21-XPRO +circuitplayground_express Adafruit Circuit Playground Express samd21 https://www.adafruit.com/product/3333 +curiosity_nano SAMD21 Curiosty Nano samd21 https://www.microchip.com/en-us/development-tool/dm320119 +cynthion_d21 Great Scott Gadgets Cynthion samd21 https://greatscottgadgets.com/cynthion/ +feather_m0_express Adafruit Feather M0 Express samd21 https://www.adafruit.com/product/3403 +itsybitsy_m0 Adafruit ItsyBitsy M0 samd21 https://www.adafruit.com/product/3727 +metro_m0_express Adafruit Metro M0 Express samd21 https://www.adafruit.com/product/3505 +qtpy Adafruit QT Py samd21 https://www.adafruit.com/product/4600 +seeeduino_xiao Seeeduino XIAO samd21 https://wiki.seeedstudio.com/Seeeduino-XIAO/ +sparkfun_samd21_mini_usb SparkFun SAMD21 Mini samd21 https://www.sparkfun.com/products/13664 +trinket_m0 Adafruit Trinket M0 samd21 https://www.adafruit.com/product/3500 +d5035_01 D5035-01 samd5x_e5x https://github.com/RudolphRiedel/USB_CAN-FD +feather_m4_express Adafruit Feather M4 Express samd5x_e5x https://www.adafruit.com/product/3857 +itsybitsy_m4 Adafruit ItsyBitsy M4 samd5x_e5x https://www.adafruit.com/product/3800 +metro_m4_express Adafruit Metro M4 Express samd5x_e5x https://www.adafruit.com/product/3382 +pybadge Adafruit PyBadge samd5x_e5x https://www.adafruit.com/product/4200 +pyportal Adafruit PyPortal samd5x_e5x https://www.adafruit.com/product/4116 +same54_xplained SAME54 Xplained Pro samd5x_e5x https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAME54-XPRO +samg55_xplained SAMG55 Xplained Pro samg https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAMG55-XPRO +atsaml21_xpro SAML21 Xplained Pro saml2x https://www.microchip.com/en-us/development-tool/atsaml21-xpro-b +saml22_feather SAML22 Feather saml2x https://github.com/joeycastillo/Feather-Projects/tree/main/SAML22%20Feather +sensorwatch_m0 SensorWatch saml2x https://github.com/joeycastillo/Sensor-Watch +========================= =================================== ========== ================================================================================= ====== + +MindMotion +========== + +===================== ====================================== ======== =============================================================================================== ====== +Board Name Family URL Note +===================== ====================================== ======== =============================================================================================== ====== +mm32f327x_mb39 MM32F3273G9P MB-039 mm32 https://www.mindmotion.com.cn/support/development_tools/evaluation_boards/evboard/mm32f3273g9p/ +mm32f327x_pitaya_lite DshanMCU Pitaya Lite with MM32F3273G8P mm32 https://gitee.com/weidongshan/DshanMCU-Pitaya-c +===================== ====================================== ======== =============================================================================================== ====== + +NXP +=== + +================== ========================================= ============= ========================================================================================================================================================================= ====== +Board Name Family URL Note +================== ========================================= ============= ========================================================================================================================================================================= ====== +metro_m7_1011 Adafruit Metro M7 1011 imxrt https://www.adafruit.com/product/5600 +metro_m7_1011_sd Adafruit Metro M7 1011 SD imxrt https://www.adafruit.com/product/5600 +mimxrt1010_evk i.MX RT1010 Evaluation Kit imxrt https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1010-evaluation-kit:MIMXRT1010-EVK +mimxrt1015_evk i.MX RT1015 Evaluation Kit imxrt https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1015-EVK +mimxrt1020_evk i.MX RT1020 Evaluation Kit imxrt https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1020-EVK +mimxrt1024_evk i.MX RT1024 Evaluation Kit imxrt https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1024-evaluation-kit:MIMXRT1024-EVK +mimxrt1050_evkb i.MX RT1050 Evaluation Kit revB imxrt https://www.nxp.com/part/IMXRT1050-EVKB +mimxrt1060_evk i.MX RT1060 Evaluation Kit revB imxrt https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1060-EVKB +mimxrt1064_evk i.MX RT1064 Evaluation Kit imxrt https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1064-EVK +mimxrt1170_evkb i.MX RT1070 Evaluation Kit imxrt https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1170-evaluation-kit:MIMXRT1170-EVKB +teensy_40 Teensy 4.0 imxrt https://www.pjrc.com/store/teensy40.html +teensy_41 Teensy 4.1 imxrt https://www.pjrc.com/store/teensy41.html +frdm_k64f Freedom K64F kinetis_k https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/freedom-development-platform-for-kinetis-k64-k63-and-k24-mcus:FRDM-K64F +teensy_35 Teensy 3.5 kinetis_k https://www.pjrc.com/store/teensy35.html +frdm_k32l2a4s Freedom K32L2A4S kinetis_k32l2 https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-K32L2A4S +frdm_k32l2b Freedom K32L2B3 kinetis_k32l2 https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/nxp-freedom-development-platform-for-k32-l2b-mcus:FRDM-K32L2B3 +kuiic Kuiic kinetis_k32l2 https://github.com/nxf58843/kuiic +frdm_kl25z fomu kinetis_kl https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z +lpcxpresso11u37 LPCXpresso11U37 lpc11 https://www.nxp.com/design/design-center/development-boards-and-designs/OM13074 +lpcxpresso11u68 LPCXpresso11U68 lpc11 https://www.nxp.com/design/design-center/development-boards-and-designs/OM13058 +lpcxpresso1347 LPCXpresso1347 lpc13 https://www.nxp.com/products/no-longer-manufactured/lpcxpresso-board-for-lpc1347:OM13045 +lpcxpresso1549 LPCXpresso1549 lpc15 https://www.nxp.com/design/design-center/development-boards-and-designs/OM13056 +lpcxpresso1769 LPCXpresso1769 lpc17 https://www.nxp.com/design/design-center/development-boards-and-designs/OM13000 +mbed1768 mbed 1768 lpc17 https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc1700-arm-cortex-m3/arm-mbed-lpc1768-board:OM11043 +lpcxpresso18s37 LPCXpresso18s37 lpc18 https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso18s37-development-board:OM13076 +mcb1800 Keil MCB1800 lpc18 https://www.keil.com/arm/mcb1800/ +ea4088_quickstart Embedded Artists LPC4088 QuickStart Board lpc40 https://www.embeddedartists.com/products/lpc4088-quickstart-board/ +ea4357 Embedded Artists LPC4357 Development Kit lpc43 https://www.embeddedartists.com/products/lpc4357-developers-kit/ +lpcxpresso43s67 LPCXpresso43S67 lpc43 https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso43s67-development-board:OM13084 +lpcxpresso51u68 LPCXpresso51u68 lpc51 https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpcxpresso51u68-for-the-lpc51u68-mcus:OM40005 +lpcxpresso54114 LPCXpresso54114 lpc54 https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso54114-board:OM13089 +lpcxpresso54608 LPCXpresso54608 lpc54 https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-development-board-for-lpc5460x-mcus:OM13092 +lpcxpresso54628 LPCXpresso54628 lpc54 https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso54628-development-board:OM13098 +double_m33_express Double M33 Express lpc55 https://www.crowdsupply.com/steiert-solutions/double-m33-express +lpcxpresso55s28 LPCXpresso55s28 lpc55 https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso55s28-development-board:LPC55S28-EVK +lpcxpresso55s69 LPCXpresso55s69 lpc55 https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso55s69-development-board:LPC55S69-EVK +mcu_link MCU Link lpc55 https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcu-link-debug-probe:MCU-LINK +frdm_mcxa153 Freedom MCXA153 mcx https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA153 +frdm_mcxn947 Freedom MCXN947 mcx https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXN947 +mcxn947brk MCXN947 Breakout mcx n/a +================== ========================================= ============= ========================================================================================================================================================================= ====== + +Nordic Semiconductor +==================== + +=========================== ===================================== ======== ============================================================================== ====== +Board Name Family URL Note +=========================== ===================================== ======== ============================================================================== ====== +adafruit_clue Adafruit CLUE nrf https://www.adafruit.com/product/4500 +arduino_nano33_ble Arduino Nano 33 BLE nrf https://store.arduino.cc/arduino-nano-33-ble +circuitplayground_bluefruit Adafruit Circuit Playground Bluefruit nrf https://www.adafruit.com/product/4333 +feather_nrf52840_express Adafruit Feather nRF52840 Express nrf https://www.adafruit.com/product/4062 +feather_nrf52840_sense Adafruit Feather nRF52840 Sense nrf https://www.adafruit.com/product/4516 +itsybitsy_nrf52840 Adafruit ItsyBitsy nRF52840 Express nrf https://www.adafruit.com/product/4481 +pca10056 Nordic nRF52840DK nrf https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-DK +pca10059 Nordic nRF52840 Dongle nrf https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-Dongle +pca10095 Nordic nRF5340 DK nrf https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF5340-DK +pca10100 Nordic nRF52833 DK nrf https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52833-DK +=========================== ===================================== ======== ============================================================================== ====== + +Raspberry Pi +============ + +================= ================= ============== ========================================================== ====== +Board Name Family URL Note +================= ================= ============== ========================================================== ====== +raspberrypi_zero Raspberry Pi Zero broadcom_32bit https://www.raspberrypi.org/products/raspberry-pi-zero/ +raspberrypi_cm4 Raspberry CM4 broadcom_64bit https://www.raspberrypi.org/products/compute-module-4 +raspberrypi_zero2 Raspberry Zero2 broadcom_64bit https://www.raspberrypi.org/products/raspberry-pi-zero-2-w +================= ================= ============== ========================================================== ====== + +Renesas +======= + +============== =========================== ======== ================================================================================================================================================================ ====== +Board Name Family URL Note +============== =========================== ======== ================================================================================================================================================================ ====== +da14695_dk_usb DA14695-00HQDEVKT-U da1469x https://www.renesas.com/en/products/wireless-connectivity/bluetooth-low-energy/da14695-00hqdevkt-u-smartbond-da14695-bluetooth-low-energy-52-usb-development-kit +da1469x_dk_pro DA1469x Development Kit Pro da1469x https://lpccs-docs.renesas.com/um-b-090-da1469x_getting_started/DA1469x_The_hardware/DA1469x_The_hardware.html +portenta_c33 Arduino Portenta C33 ra https://www.arduino.cc/pro/hardware-product-portenta-c33/ +ra2a1_ek RA2A1 EK ra https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra2a1-evaluation-kit-ra2a1-mcu-group +ra4m1_ek RA4M1 EK ra https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m1-evaluation-kit-ra4m1-mcu-group +ra4m3_ek RA4M3 EK ra https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m3-evaluation-kit-ra4m3-mcu-group +ra6m1_ek RA6M1 EK ra https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m1-evaluation-kit-ra6m1-mcu-group +ra6m5_ek RA6M5 EK ra https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m5-evaluation-kit-ra6m5-mcu-group +ra8m1_ek RA8M1 EK ra https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra8m1-evaluation-kit-ra8m1-mcu-group +uno_r4 Arduino UNO R4 ra https://store-usa.arduino.cc/pages/uno-r4 +============== =========================== ======== ================================================================================================================================================================ ====== + +STMicroelectronics +================== + +=================== ================================= ======== ================================================================= ====== +Board Name Family URL Note +=================== ================================= ======== ================================================================= ====== +stm32c071nucleo STM32C071 Nucleo stm32c0 https://www.st.com/en/evaluation-tools/nucleo-g071rb.html +stm32f070rbnucleo STM32 F070 Nucleo stm32f0 https://www.st.com/en/evaluation-tools/nucleo-f070rb.html +stm32f072disco STM32 F072 Discovery stm32f0 https://www.st.com/en/evaluation-tools/32f072bdiscovery.html +stm32f072eval STM32 F072 Eval stm32f0 https://www.st.com/en/evaluation-tools/stm32072b-eval.html +stm32f103_bluepill STM32 F103 Bluepill stm32f1 https://stm32-base.org/boards/STM32F103C8T6-Blue-Pill +stm32f103_mini_2 STM32 F103 Mini v2 stm32f1 https://stm32-base.org/boards/STM32F103RCT6-STM32-Mini-V2.0 +stm32f103ze_iar IAR STM32 F103ze starter kit stm32f1 n/a +stm32f207nucleo STM32 F207 Nucleo stm32f2 https://www.st.com/en/evaluation-tools/nucleo-f207zg.html +stm32f303disco STM32 F303 Discovery stm32f3 https://www.st.com/en/evaluation-tools/stm32f3discovery.html +feather_stm32f405 Adafruit Feather STM32F405 stm32f4 https://www.adafruit.com/product/4382 +pyboardv11 Pyboard v1.1 stm32f4 https://www.adafruit.com/product/2390 +stm32f401blackpill STM32 F401 Blackpill stm32f4 https://stm32-base.org/boards/STM32F401CCU6-WeAct-Black-Pill-V1.2 +stm32f407blackvet STM32 F407 Blackvet stm32f4 https://stm32-base.org/boards/STM32F407VET6-STM32-F4VE-V2.0 +stm32f407disco STM32 F407 Discovery stm32f4 https://www.st.com/en/evaluation-tools/stm32f4discovery.html +stm32f411blackpill STM32 F411 Blackpill stm32f4 https://stm32-base.org/boards/STM32F411CEU6-WeAct-Black-Pill-V2.0 +stm32f411disco STM32 F411 Discovery stm32f4 https://www.st.com/en/evaluation-tools/32f411ediscovery.html +stm32f412disco STM32 F412 Discovery stm32f4 https://www.st.com/en/evaluation-tools/32f412gdiscovery.html +stm32f412nucleo STM32 F412 Nucleo stm32f4 https://www.st.com/en/evaluation-tools/nucleo-f412zg.html +stm32f439nucleo STM32 F439 Nucleo stm32f4 https://www.st.com/en/evaluation-tools/nucleo-f439zi.html +stlinkv3mini Stlink-v3 mini stm32f7 https://www.st.com/en/development-tools/stlink-v3mini.html +stm32f723disco STM32 F723 Discovery stm32f7 https://www.st.com/en/evaluation-tools/32f723ediscovery.html +stm32f746disco STM32 F746 Discovery stm32f7 https://www.st.com/en/evaluation-tools/32f746gdiscovery.html +stm32f746nucleo STM32 F746 Nucleo stm32f7 https://www.st.com/en/evaluation-tools/nucleo-f746zg.html +stm32f767nucleo STM32 F767 Nucleo stm32f7 https://www.st.com/en/evaluation-tools/nucleo-f767zi.html +stm32f769disco STM32 F769 Discovery stm32f7 https://www.st.com/en/evaluation-tools/32f769idiscovery.html +stm32g0b1nucleo STM32 G0B1 Nucleo stm32g0 https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html +b_g474e_dpow1 STM32 B-G474E-DPOW1 Discovery kit stm32g4 https://www.st.com/en/evaluation-tools/b-g474e-dpow1.html +stm32g474nucleo STM32 G474 Nucleo stm32g4 https://www.st.com/en/evaluation-tools/nucleo-g474re.html +stm32g491nucleo STM32 G491 Nucleo stm32g4 https://www.st.com/en/evaluation-tools/nucleo-g491re.html +stm32h503nucleo STM32 H503 Nucleo stm32h5 https://www.st.com/en/evaluation-tools/nucleo-h503rb.html +stm32h563nucleo STM32 H563 Nucleo stm32h5 https://www.st.com/en/evaluation-tools/nucleo-h563zi.html +stm32h573i_dk STM32 H573i Discovery stm32h5 https://www.st.com/en/evaluation-tools/stm32h573i-dk.html +daisyseed Daisy Seed stm32h7 https://electro-smith.com/products/daisy-seed +stm32h723nucleo STM32 H723 Nucleo stm32h7 https://www.st.com/en/evaluation-tools/nucleo-h723zg.html +stm32h743eval STM32 H743 Eval stm32h7 https://www.st.com/en/evaluation-tools/stm32h743i-eval.html +stm32h743nucleo STM32 H743 Nucleo stm32h7 https://www.st.com/en/evaluation-tools/nucleo-h743zi.html +stm32h745disco STM32 H745 Discovery stm32h7 https://www.st.com/en/evaluation-tools/stm32h745i-disco.html +stm32h750_weact STM32 H750 WeAct stm32h7 https://www.adafruit.com/product/5032 +stm32h750bdk STM32 H750b Discovery Kit stm32h7 https://www.st.com/en/evaluation-tools/stm32h750b-dk.html +waveshare_openh743i Waveshare Open H743i stm32h7 https://www.waveshare.com/openh743i-c-standard.htm +stm32l052dap52 STM32 L052 DAP stm32l0 n/a +stm32l0538disco STM32 L0538 Discovery stm32l0 https://www.st.com/en/evaluation-tools/32l0538discovery.html +stm32l412nucleo STM32 L412 Nucleo stm32l4 https://www.st.com/en/evaluation-tools/nucleo-l412kb.html +stm32l476disco STM32 L476 Disco stm32l4 https://www.st.com/en/evaluation-tools/32l476gdiscovery.html +stm32l4p5nucleo STM32 L4P5 Nucleo stm32l4 https://www.st.com/en/evaluation-tools/nucleo-l4p5zg.html +stm32l4r5nucleo STM32 L4R5 Nucleo stm32l4 https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html +b_u585i_iot2a STM32 B-U585i IOT2A Discovery kit stm32u5 https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html +stm32u545nucleo STM32 U545 Nucleo stm32u5 https://www.st.com/en/evaluation-tools/nucleo-u545re-q.html +stm32u575eval STM32 U575 Eval stm32u5 https://www.st.com/en/evaluation-tools/stm32u575i-ev.html +stm32u575nucleo STM32 U575 Nucleo stm32u5 https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html +stm32u5a5nucleo STM32 U5a5 Nucleo stm32u5 https://www.st.com/en/evaluation-tools/nucleo-u5a5zj-q.html +stm32wb55nucleo STM32 P-NUCLEO-WB55 stm32wb https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html +=================== ================================= ======== ================================================================= ====== + +Sunxi +===== + +======= ================= ======== ========================================= ====== +Board Name Family URL Note +======= ================= ======== ========================================= ====== +f1c100s Lctech Pi F1C200s f1c100s https://linux-sunxi.org/Lctech_Pi_F1C200s +======= ================= ======== ========================================= ====== + +Texas Instruments +================= + +================= ===================== ======== ========================================= ====== +Board Name Family URL Note +================= ===================== ======== ========================================= ====== +msp_exp430f5529lp MSP430F5529 LaunchPad msp430 https://www.ti.com/tool/MSP-EXP430F5529LP +msp_exp432e401y MSP432E401Y LaunchPad msp432e4 https://www.ti.com/tool/MSP-EXP432E401Y +ek_tm4c123gxl TM4C123G LaunchPad tm4c https://www.ti.com/tool/EK-TM4C123GXL +================= ===================== ======== ========================================= ====== + +Tomu +==== + +======= ====== ======== ========================= ====== +Board Name Family URL Note +======= ====== ======== ========================= ====== +fomu fomu fomu https://tomu.im/fomu.html +======= ====== ======== ========================= ====== + +WCH +=== + +================ ================ ======== ===================================================================== ====== +Board Name Family URL Note +================ ================ ======== ===================================================================== ====== +ch32f205r-r0 CH32F205r-r0 ch32f20x https://github.com/openwch/ch32f20x +ch32v103r_r1_1v0 CH32V103R-R1-1v1 ch32v10x https://github.com/openwch/ch32v103/tree/main/SCHPCB/CH32V103R-R1-1v1 +ch32v203c_r0_1v0 CH32V203C-R0-1v0 ch32v20x https://github.com/openwch/ch32v20x/tree/main/SCHPCB/CH32V203C-R0 +ch32v203g_r0_1v0 CH32V203G-R0-1v0 ch32v20x https://github.com/openwch/ch32v20x/tree/main/SCHPCB/CH32V203C-R0 +nanoch32v203 nanoCH32V203 ch32v20x https://github.com/wuxx/nanoCH32V203 +ch32v307v_r1_1v0 CH32V307V-R1-1v0 ch32v307 https://github.com/openwch/ch32v307/tree/main/SCHPCB/CH32V307V-R1-1v0 +================ ================ ======== ===================================================================== ====== diff --git a/docs/reference/index.rst b/docs/reference/index.rst index 9ecdf619b..e9b033033 100644 --- a/docs/reference/index.rst +++ b/docs/reference/index.rst @@ -79,7 +79,8 @@ Index .. toctree:: :maxdepth: 2 - supported getting_started + supported + boards dependencies concurrency diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.h b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.h index 84a106346..40a9dd198 100644 --- a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.h +++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Raspberry Pi Zero + url: https://www.raspberrypi.org/products/raspberry-pi-zero/ +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/broadcom_32bit/family.c b/hw/bsp/broadcom_32bit/family.c index 0062e2e83..f8f3b0b70 100644 --- a/hw/bsp/broadcom_32bit/family.c +++ b/hw/bsp/broadcom_32bit/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Raspberry Pi +*/ + #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h index 84a106346..cadad2b27 100644 --- a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h +++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Raspberry CM4 + url: https://www.raspberrypi.org/products/compute-module-4 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.h b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.h index 84a106346..e6caa0294 100644 --- a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.h +++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Raspberry Zero2 + url: https://www.raspberrypi.org/products/raspberry-pi-zero-2-w +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/broadcom_64bit/family.c b/hw/bsp/broadcom_64bit/family.c index 0062e2e83..f8f3b0b70 100644 --- a/hw/bsp/broadcom_64bit/family.c +++ b/hw/bsp/broadcom_64bit/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Raspberry Pi +*/ + #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/brtmm90x/boards/mm900evxb/board.h b/hw/bsp/brtmm90x/boards/mm900evxb/board.h index 771779108..623033c2c 100644 --- a/hw/bsp/brtmm90x/boards/mm900evxb/board.h +++ b/hw/bsp/brtmm90x/boards/mm900evxb/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MM900EVxB + url: https://brtchip.com/product/mm900ev1b +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/brtmm90x/family.c b/hw/bsp/brtmm90x/family.c index 4d81e7d52..15ff4b8ee 100644 --- a/hw/bsp/brtmm90x/family.c +++ b/hw/bsp/brtmm90x/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Bridgetek +*/ + #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h index d5849bddb..b855804a9 100644 --- a/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h +++ b/hw/bsp/ch32f20x/boards/ch32f205r-r0/board.h @@ -22,6 +22,11 @@ * THE SOFTWARE. */ +/* metadata: + name: CH32F205r-r0 + url: https://github.com/openwch/ch32f20x +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/ch32f20x/family.c b/hw/bsp/ch32f20x/family.c index 9717832d6..7fef71d47 100644 --- a/hw/bsp/ch32f20x/family.c +++ b/hw/bsp/ch32f20x/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: WCH +*/ + #include "stdio.h" #include "debug_uart.h" diff --git a/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.h b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.h index 3b1187c3a..1fde4244c 100644 --- a/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.h +++ b/hw/bsp/ch32v10x/boards/ch32v103r_r1_1v0/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: CH32V103R-R1-1v1 + url: https://github.com/openwch/ch32v103/tree/main/SCHPCB/CH32V103R-R1-1v1 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/ch32v10x/family.c b/hw/bsp/ch32v10x/family.c index 15f754e11..f25102494 100644 --- a/hw/bsp/ch32v10x/family.c +++ b/hw/bsp/ch32v10x/family.c @@ -1,3 +1,7 @@ +/* metadata: + manufacturer: WCH +*/ + #include // https://github.com/openwch/ch32v307/pull/90 diff --git a/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h index 692cf11bf..256958088 100644 --- a/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h +++ b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: CH32V203C-R0-1v0 + url: https://github.com/openwch/ch32v20x/tree/main/SCHPCB/CH32V203C-R0 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h index 783831edd..827226d80 100644 --- a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h +++ b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: CH32V203G-R0-1v0 + url: https://github.com/openwch/ch32v20x/tree/main/SCHPCB/CH32V203C-R0 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/ch32v20x/boards/nanoch32v203/board.h b/hw/bsp/ch32v20x/boards/nanoch32v203/board.h index 64eaf931e..f02fceced 100644 --- a/hw/bsp/ch32v20x/boards/nanoch32v203/board.h +++ b/hw/bsp/ch32v20x/boards/nanoch32v203/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: nanoCH32V203 + url: https://github.com/wuxx/nanoCH32V203 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/ch32v20x/family.c b/hw/bsp/ch32v20x/family.c index 43dd7e032..5f52d9447 100644 --- a/hw/bsp/ch32v20x/family.c +++ b/hw/bsp/ch32v20x/family.c @@ -1,3 +1,7 @@ +/* metadata: +manufacturer: WCH +*/ + #include // https://github.com/openwch/ch32v307/pull/90 diff --git a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h index 7b488096e..491347034 100644 --- a/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h +++ b/hw/bsp/ch32v307/boards/ch32v307v_r1_1v0/board.h @@ -22,6 +22,11 @@ * THE SOFTWARE. */ +/* metadata: + name: CH32V307V-R1-1v0 + url: https://github.com/openwch/ch32v307/tree/main/SCHPCB/CH32V307V-R1-1v0 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/ch32v307/family.c b/hw/bsp/ch32v307/family.c index adf2dbea5..48eb8a38c 100644 --- a/hw/bsp/ch32v307/family.c +++ b/hw/bsp/ch32v307/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: WCH +*/ + #include "stdio.h" // https://github.com/openwch/ch32v307/pull/90 diff --git a/hw/bsp/da1469x/boards/da14695_dk_usb/board.h b/hw/bsp/da1469x/boards/da14695_dk_usb/board.h index 5efdd43e0..c0810c2b6 100644 --- a/hw/bsp/da1469x/boards/da14695_dk_usb/board.h +++ b/hw/bsp/da1469x/boards/da14695_dk_usb/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: DA14695-00HQDEVKT-U + url: https://www.renesas.com/en/products/wireless-connectivity/bluetooth-low-energy/da14695-00hqdevkt-u-smartbond-da14695-bluetooth-low-energy-52-usb-development-kit +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/da1469x/boards/da1469x_dk_pro/board.h b/hw/bsp/da1469x/boards/da1469x_dk_pro/board.h index f969acf90..2b61e810e 100644 --- a/hw/bsp/da1469x/boards/da1469x_dk_pro/board.h +++ b/hw/bsp/da1469x/boards/da1469x_dk_pro/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: DA1469x Development Kit Pro + url: https://lpccs-docs.renesas.com/um-b-090-da1469x_getting_started/DA1469x_The_hardware/DA1469x_The_hardware.html +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/da1469x/family.c b/hw/bsp/da1469x/family.c index 70bedf6d9..a64ffce67 100644 --- a/hw/bsp/da1469x/family.c +++ b/hw/bsp/da1469x/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Renesas +*/ + #include "bsp/board_api.h" #include "board.h" #include diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h index 0c53df06b..15e5091f9 100644 --- a/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h +++ b/hw/bsp/espressif/boards/adafruit_feather_esp32_v2/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Feather ESP32 v2 + url: https://www.adafruit.com/product/5400 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.h index 9aa2e7535..0f607c755 100644 --- a/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.h +++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s2/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Feather ESP32S2 + url: https://www.adafruit.com/product/5000 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h b/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h index 9aa2e7535..35c268cf5 100644 --- a/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h +++ b/hw/bsp/espressif/boards/adafruit_feather_esp32s3/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Feather ESP32S3 + url: https://www.adafruit.com/product/5323 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.h b/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.h index 084a7aaf2..b86089400 100644 --- a/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.h +++ b/hw/bsp/espressif/boards/adafruit_magtag_29gray/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit MagTag 2.9" Grayscale + url: https://www.adafruit.com/product/4800 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h index 137ea71ae..bc45678f7 100644 --- a/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h +++ b/hw/bsp/espressif/boards/adafruit_metro_esp32s2/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Metro ESP32-S2 + url: https://www.adafruit.com/product/4775 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/espressif_addax_1/board.h b/hw/bsp/espressif/boards/espressif_addax_1/board.h index d4690f732..4a4a15e1b 100644 --- a/hw/bsp/espressif/boards/espressif_addax_1/board.h +++ b/hw/bsp/espressif/boards/espressif_addax_1/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif Addax-1 + url: n/a +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/espressif_c3_devkitc/board.h b/hw/bsp/espressif/boards/espressif_c3_devkitc/board.h index 243dd47f6..a03cb5052 100644 --- a/hw/bsp/espressif/boards/espressif_c3_devkitc/board.h +++ b/hw/bsp/espressif/boards/espressif_c3_devkitc/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif C3 DevKitC + url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32c3/esp32-c3-devkitc-02/index.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/espressif_c6_devkitc/board.h b/hw/bsp/espressif/boards/espressif_c6_devkitc/board.h index 243dd47f6..eedd36a89 100644 --- a/hw/bsp/espressif/boards/espressif_c6_devkitc/board.h +++ b/hw/bsp/espressif/boards/espressif_c6_devkitc/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif C6 DevKitC + url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32c6/esp32-c6-devkitc-1/index.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/espressif_kaluga_1/board.h b/hw/bsp/espressif/boards/espressif_kaluga_1/board.h index 613e6ae0c..d49dc2af6 100644 --- a/hw/bsp/espressif/boards/espressif_kaluga_1/board.h +++ b/hw/bsp/espressif/boards/espressif_kaluga_1/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif Kaluga 1 + url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-kaluga-1/index.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h index e57f7c51f..6f3229b70 100644 --- a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h +++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif P4 Function EV + url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32p4/esp32-p4-function-ev-board/index.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h index e068efef9..9c197591f 100644 --- a/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h +++ b/hw/bsp/espressif/boards/espressif_s2_devkitc/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif S2 DevKitC + url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-devkitc-1/index.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h index a319fbc61..6d7a94668 100644 --- a/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h +++ b/hw/bsp/espressif/boards/espressif_s3_devkitc/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif S3 DevKitC + url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s3/esp32-s3-devkitc-1/index.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h index a319fbc61..d01fdbe5b 100644 --- a/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h +++ b/hw/bsp/espressif/boards/espressif_s3_devkitm/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif S3 DevKitM + url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s3/esp32-s3-devkitm-1/index.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/espressif_saola_1/board.h b/hw/bsp/espressif/boards/espressif_saola_1/board.h index e068efef9..ea369f19c 100644 --- a/hw/bsp/espressif/boards/espressif_saola_1/board.h +++ b/hw/bsp/espressif/boards/espressif_saola_1/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Espresif S2 Saola 1 + url: https://docs.espressif.com/projects/esp-dev-kits/en/latest/esp32s2/esp32-s2-saola-1/index.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index 048b431fb..26e415d94 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Espressif +*/ + #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/f1c100s/boards/f1c100s/board.h b/hw/bsp/f1c100s/boards/f1c100s/board.h index 3b56a3a57..44b78f8fb 100644 --- a/hw/bsp/f1c100s/boards/f1c100s/board.h +++ b/hw/bsp/f1c100s/boards/f1c100s/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: Lctech Pi F1C200s + url: https://linux-sunxi.org/Lctech_Pi_F1C200s +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/f1c100s/family.c b/hw/bsp/f1c100s/family.c index 6df4a0ed8..9e864363f 100644 --- a/hw/bsp/f1c100s/family.c +++ b/hw/bsp/f1c100s/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Sunxi +*/ + #include #include #include diff --git a/hw/bsp/fomu/boards/fomu/board.h b/hw/bsp/fomu/boards/fomu/board.h index 666ba1d98..2651c823d 100644 --- a/hw/bsp/fomu/boards/fomu/board.h +++ b/hw/bsp/fomu/boards/fomu/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: fomu + url: https://tomu.im/fomu.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/fomu/family.c b/hw/bsp/fomu/family.c index ccf2b12f4..61943cb01 100644 --- a/hw/bsp/fomu/family.c +++ b/hw/bsp/fomu/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Tomu +*/ + #include #include #include "csr.h" diff --git a/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h index fae7c40b7..cb564a340 100644 --- a/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h +++ b/hw/bsp/gd32vf103/boards/sipeed_longan_nano/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: Sipeed Longan Nano + url: https://longan.sipeed.com/en/ +*/ + #ifndef _NUCLEI_SDK_HAL_H #define _NUCLEI_SDK_HAL_H diff --git a/hw/bsp/gd32vf103/family.c b/hw/bsp/gd32vf103/family.c index d4a819fb3..9d15755fc 100644 --- a/hw/bsp/gd32vf103/family.c +++ b/hw/bsp/gd32vf103/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: GigaDevice +*/ + #include "drv_usb_hw.h" #include "drv_usb_dev.h" diff --git a/hw/bsp/imxrt/boards/metro_m7_1011/board.h b/hw/bsp/imxrt/boards/metro_m7_1011/board.h index 24141f5f4..ccc4d6b9a 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011/board.h +++ b/hw/bsp/imxrt/boards/metro_m7_1011/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Metro M7 1011 + url: https://www.adafruit.com/product/5600 +*/ + #ifndef BOARD_M7_1011_H_ #define BOARD_M7_1011_H_ diff --git a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h index 343e17f81..04d5b01b5 100644 --- a/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h +++ b/hw/bsp/imxrt/boards/metro_m7_1011_sd/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Metro M7 1011 SD + url: https://www.adafruit.com/product/5600 +*/ + #ifndef BOARD_METRO_M7_1011_SD_H_ #define BOARD_METRO_M7_1011_SD_H_ diff --git a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h index da12075a0..6b9ec0ae1 100644 --- a/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1010_evk/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: i.MX RT1010 Evaluation Kit + url: https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1010-evaluation-kit:MIMXRT1010-EVK +*/ + #ifndef BOARD_MIMXRT1010_EVK_H_ #define BOARD_MIMXRT1010_EVK_H_ diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h index 6ac78453f..e2ec4e627 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: i.MX RT1015 Evaluation Kit + url: https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1015-EVK +*/ + #ifndef BOARD_MIMXRT1015_EVK_H_ #define BOARD_MIMXRT1015_EVK_H_ diff --git a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h index 4f4593524..3f9c97e11 100644 --- a/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1020_evk/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: i.MX RT1020 Evaluation Kit + url: https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1020-EVK +*/ + #ifndef BOARD_MIMXRT1020_EVK_H_ #define BOARD_MIMXRT1020_EVK_H_ diff --git a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h index 27a64b464..39e63c472 100644 --- a/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1024_evk/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: i.MX RT1024 Evaluation Kit + url: https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1024-evaluation-kit:MIMXRT1024-EVK +*/ + #ifndef BOARD_MIMXRT1024_EVK_H_ #define BOARD_MIMXRT1024_EVK_H_ diff --git a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h index 97d1e446c..de7ab0535 100644 --- a/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1050_evkb/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: i.MX RT1050 Evaluation Kit revB + url: https://www.nxp.com/part/IMXRT1050-EVKB +*/ + #ifndef BOARD_MIMXRT1050_EVKB_H_ #define BOARD_MIMXRT1050_EVKB_H_ diff --git a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h index 40b99860f..5bbacadaf 100644 --- a/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1060_evk/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: i.MX RT1060 Evaluation Kit revB + url: https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1060-EVKB +*/ + #ifndef BOARD_MIMXRT1060_EVKB_H_ #define BOARD_MIMXRT1060_EVKB_H_ diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h index 7fca5adef..6dc01e3e7 100644 --- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: i.MX RT1064 Evaluation Kit + url: https://www.nxp.com/design/design-center/development-boards-and-designs/MIMXRT1064-EVK +*/ + #ifndef BOARD_MIMXRT1064_EVKB_H_ #define BOARD_MIMXRT1064_EVKB_H_ diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h index 303935517..c5d54b7a7 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: i.MX RT1070 Evaluation Kit + url: https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1170-evaluation-kit:MIMXRT1170-EVKB +*/ + #ifndef BOARD_MIMXRT1170_EVKB_H_ #define BOARD_MIMXRT1170_EVKB_H_ diff --git a/hw/bsp/imxrt/boards/teensy_40/board.h b/hw/bsp/imxrt/boards/teensy_40/board.h index 4a173c834..ae749e894 100644 --- a/hw/bsp/imxrt/boards/teensy_40/board.h +++ b/hw/bsp/imxrt/boards/teensy_40/board.h @@ -24,11 +24,14 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Teensy 4.0 + url: https://www.pjrc.com/store/teensy40.html +*/ #ifndef BOARD_H_ #define BOARD_H_ - // required since iMXRT MCUX-SDK include this file for board size #define BOARD_FLASH_SIZE (2 * 1024 * 1024) diff --git a/hw/bsp/imxrt/boards/teensy_41/board.h b/hw/bsp/imxrt/boards/teensy_41/board.h index 358684126..1bc022c54 100644 --- a/hw/bsp/imxrt/boards/teensy_41/board.h +++ b/hw/bsp/imxrt/boards/teensy_41/board.h @@ -24,11 +24,14 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Teensy 4.1 + url: https://www.pjrc.com/store/teensy41.html +*/ #ifndef BOARD_H_ #define BOARD_H_ - // required since iMXRT MCUX-SDK include this file for board size #define BOARD_FLASH_SIZE (8 * 1024 * 1024) diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index f365981f5..ad529a227 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "bsp/board_api.h" #include "board/clock_config.h" #include "board/pin_mux.h" diff --git a/hw/bsp/kinetis_k/boards/frdm_k64f/board.h b/hw/bsp/kinetis_k/boards/frdm_k64f/board.h index ae8c66182..75a10f961 100644 --- a/hw/bsp/kinetis_k/boards/frdm_k64f/board.h +++ b/hw/bsp/kinetis_k/boards/frdm_k64f/board.h @@ -22,6 +22,11 @@ * THE SOFTWARE. */ +/* metadata: + name: Freedom K64F + url: https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/freedom-development-platform-for-kinetis-k64-k63-and-k24-mcus:FRDM-K64F +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/kinetis_k/boards/teensy_35/board.h b/hw/bsp/kinetis_k/boards/teensy_35/board.h index f8173447a..4718a0241 100644 --- a/hw/bsp/kinetis_k/boards/teensy_35/board.h +++ b/hw/bsp/kinetis_k/boards/teensy_35/board.h @@ -22,6 +22,11 @@ * THE SOFTWARE. */ +/* metadata: + name: Teensy 3.5 + url: https://www.pjrc.com/store/teensy35.html +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/kinetis_k/family.c b/hw/bsp/kinetis_k/family.c index 30dfe6d76..59d80fa18 100644 --- a/hw/bsp/kinetis_k/family.c +++ b/hw/bsp/kinetis_k/family.c @@ -23,6 +23,10 @@ * THE SOFTWARE. */ +/* metadata: + manufacturer: NXP +*/ + #include "bsp/board_api.h" #include "board.h" #include "fsl_device_registers.h" diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h index 16f832722..9e2534307 100644 --- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h +++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2a4s/board.h @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Freedom K32L2A4S + url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-K32L2A4S +*/ #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h index 790d6fcb0..854340d6d 100644 --- a/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h +++ b/hw/bsp/kinetis_k32l2/boards/frdm_k32l2b/board.h @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Freedom K32L2B3 + url: https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/nxp-freedom-development-platform-for-k32-l2b-mcus:FRDM-K32L2B3 +*/ #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/kinetis_k32l2/boards/kuiic/board.h b/hw/bsp/kinetis_k32l2/boards/kuiic/board.h index ec3702376..f5895fc65 100644 --- a/hw/bsp/kinetis_k32l2/boards/kuiic/board.h +++ b/hw/bsp/kinetis_k32l2/boards/kuiic/board.h @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Kuiic + url: https://github.com/nxf58843/kuiic +*/ #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/kinetis_k32l2/family.c b/hw/bsp/kinetis_k32l2/family.c index 92f5ba6d3..2fcc1b2af 100644 --- a/hw/bsp/kinetis_k32l2/family.c +++ b/hw/bsp/kinetis_k32l2/family.c @@ -25,6 +25,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "fsl_gpio.h" #include "fsl_port.h" #include "fsl_clock.h" diff --git a/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.h b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.h index 23f144666..b03fe91a8 100644 --- a/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.h +++ b/hw/bsp/kinetis_kl/boards/frdm_kl25z/board.h @@ -22,6 +22,11 @@ * THE SOFTWARE. */ +/* metadata: + name: fomu + url: https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/kinetis_kl/family.c b/hw/bsp/kinetis_kl/family.c index 254a95176..fe864f3a0 100644 --- a/hw/bsp/kinetis_kl/family.c +++ b/hw/bsp/kinetis_kl/family.c @@ -23,6 +23,10 @@ * THE SOFTWARE. */ +/* metadata: + manufacturer: NXP +*/ + #include "bsp/board_api.h" #include "board.h" #include "fsl_device_registers.h" diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u37/board.h b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.h index 930462f28..c8a48eecb 100644 --- a/hw/bsp/lpc11/boards/lpcxpresso11u37/board.h +++ b/hw/bsp/lpc11/boards/lpcxpresso11u37/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: LPCXpresso11U37 + url: https://www.nxp.com/design/design-center/development-boards-and-designs/OM13074 +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/lpc11/boards/lpcxpresso11u68/board.h b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.h index a12fcbef1..50141e4a5 100644 --- a/hw/bsp/lpc11/boards/lpcxpresso11u68/board.h +++ b/hw/bsp/lpc11/boards/lpcxpresso11u68/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: LPCXpresso11U68 + url: https://www.nxp.com/design/design-center/development-boards-and-designs/OM13058 +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/lpc11/family.c b/hw/bsp/lpc11/family.c index e75bc4919..566449ca0 100644 --- a/hw/bsp/lpc11/family.c +++ b/hw/bsp/lpc11/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wunused-parameter" diff --git a/hw/bsp/lpc13/boards/lpcxpresso1347/board.h b/hw/bsp/lpc13/boards/lpcxpresso1347/board.h index 71e608b46..acf29fdc6 100644 --- a/hw/bsp/lpc13/boards/lpcxpresso1347/board.h +++ b/hw/bsp/lpc13/boards/lpcxpresso1347/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: LPCXpresso1347 + url: https://www.nxp.com/products/no-longer-manufactured/lpcxpresso-board-for-lpc1347:OM13045 +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/lpc13/family.c b/hw/bsp/lpc13/family.c index 7e04c1cf5..1faa54485 100644 --- a/hw/bsp/lpc13/family.c +++ b/hw/bsp/lpc13/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "chip.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/lpc15/boards/lpcxpresso1549/board.h b/hw/bsp/lpc15/boards/lpcxpresso1549/board.h index 5ed5b75b2..1be2045a9 100644 --- a/hw/bsp/lpc15/boards/lpcxpresso1549/board.h +++ b/hw/bsp/lpc15/boards/lpcxpresso1549/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso1549 + url: https://www.nxp.com/design/design-center/development-boards-and-designs/OM13056 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc15/family.c b/hw/bsp/lpc15/family.c index b9ce39648..e23fdec43 100644 --- a/hw/bsp/lpc15/family.c +++ b/hw/bsp/lpc15/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstrict-prototypes" diff --git a/hw/bsp/lpc17/boards/lpcxpresso1769/board.h b/hw/bsp/lpc17/boards/lpcxpresso1769/board.h index d6aa98ed9..6f5c12854 100644 --- a/hw/bsp/lpc17/boards/lpcxpresso1769/board.h +++ b/hw/bsp/lpc17/boards/lpcxpresso1769/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso1769 + url: https://www.nxp.com/design/design-center/development-boards-and-designs/OM13000 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc17/boards/mbed1768/board.h b/hw/bsp/lpc17/boards/mbed1768/board.h index 2b3ddc905..2c75cede4 100644 --- a/hw/bsp/lpc17/boards/mbed1768/board.h +++ b/hw/bsp/lpc17/boards/mbed1768/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: mbed 1768 + url: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc1700-arm-cortex-m3/arm-mbed-lpc1768-board:OM11043 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc17/family.c b/hw/bsp/lpc17/family.c index 79281ba41..7d3231f6a 100644 --- a/hw/bsp/lpc17/family.c +++ b/hw/bsp/lpc17/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "chip.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h index f4c85ddc9..2cf4dbdf8 100644 --- a/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h +++ b/hw/bsp/lpc18/boards/lpcxpresso18s37/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso18s37 + url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso18s37-development-board:OM13076 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc18/boards/mcb1800/board.h b/hw/bsp/lpc18/boards/mcb1800/board.h index 93b3cd112..dba7a62a3 100644 --- a/hw/bsp/lpc18/boards/mcb1800/board.h +++ b/hw/bsp/lpc18/boards/mcb1800/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Keil MCB1800 + url: https://www.keil.com/arm/mcb1800/ +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c index 55ef31ee4..8f6dbcd4a 100644 --- a/hw/bsp/lpc18/family.c +++ b/hw/bsp/lpc18/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "chip.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/lpc40/boards/ea4088_quickstart/board.h b/hw/bsp/lpc40/boards/ea4088_quickstart/board.h index d5489c154..ede0a306d 100644 --- a/hw/bsp/lpc40/boards/ea4088_quickstart/board.h +++ b/hw/bsp/lpc40/boards/ea4088_quickstart/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Embedded Artists LPC4088 QuickStart Board + url: https://www.embeddedartists.com/products/lpc4088-quickstart-board/ +*/ + #ifndef EA4088QS__BOARD_H #define EA4088QS__BOARD_H diff --git a/hw/bsp/lpc40/family.c b/hw/bsp/lpc40/family.c index d6c8ef32a..b8bc99452 100644 --- a/hw/bsp/lpc40/family.c +++ b/hw/bsp/lpc40/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "chip.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/lpc43/boards/ea4357/board.h b/hw/bsp/lpc43/boards/ea4357/board.h index fb52e32a7..fca617361 100644 --- a/hw/bsp/lpc43/boards/ea4357/board.h +++ b/hw/bsp/lpc43/boards/ea4357/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Embedded Artists LPC4357 Development Kit + url: https://www.embeddedartists.com/products/lpc4357-developers-kit/ +*/ + #ifndef _BOARD_EA4357_H #define _BOARD_EA4357_H diff --git a/hw/bsp/lpc43/boards/lpcxpresso43s67/board.h b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.h index 4dd90fe29..4427905e8 100644 --- a/hw/bsp/lpc43/boards/lpcxpresso43s67/board.h +++ b/hw/bsp/lpc43/boards/lpcxpresso43s67/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso43S67 + url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso43s67-development-board:OM13084 +*/ + #ifndef _BOARD_LPCXPRESSO43S67_H_ #define _BOARD_LPCXPRESSO43S67_H_ diff --git a/hw/bsp/lpc43/family.c b/hw/bsp/lpc43/family.c index dfee9f5ea..fe6c7b0c8 100644 --- a/hw/bsp/lpc43/family.c +++ b/hw/bsp/lpc43/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + // Suppress warning caused by mcu driver #ifdef __GNUC__ #pragma GCC diagnostic push diff --git a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.h b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.h index 0a3b37fda..151fae24b 100644 --- a/hw/bsp/lpc51/boards/lpcxpresso51u68/board.h +++ b/hw/bsp/lpc51/boards/lpcxpresso51u68/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: LPCXpresso51u68 + url: https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpcxpresso51u68-for-the-lpc51u68-mcus:OM40005 +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/lpc51/family.c b/hw/bsp/lpc51/family.c index a0667a741..0afe33d41 100644 --- a/hw/bsp/lpc51/family.c +++ b/hw/bsp/lpc51/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "fsl_device_registers.h" #include "fsl_gpio.h" #include "fsl_power.h" diff --git a/hw/bsp/lpc54/boards/lpcxpresso54114/board.h b/hw/bsp/lpc54/boards/lpcxpresso54114/board.h index b1ad4258c..c43ca9d7d 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54114/board.h +++ b/hw/bsp/lpc54/boards/lpcxpresso54114/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso54114 + url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso54114-board:OM13089 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc54/boards/lpcxpresso54608/board.h b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h index 8bbe18155..e985e97e0 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54608/board.h +++ b/hw/bsp/lpc54/boards/lpcxpresso54608/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso54608 + url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-development-board-for-lpc5460x-mcus:OM13092 +*/ + #ifndef BOARD_LPCXPRESSO54608_H_ #define BOARD_LPCXPRESSO54608_H_ diff --git a/hw/bsp/lpc54/boards/lpcxpresso54628/board.h b/hw/bsp/lpc54/boards/lpcxpresso54628/board.h index 670277512..837d26aef 100644 --- a/hw/bsp/lpc54/boards/lpcxpresso54628/board.h +++ b/hw/bsp/lpc54/boards/lpcxpresso54628/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso54628 + url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso54628-development-board:OM13098 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc54/family.c b/hw/bsp/lpc54/family.c index 5e6ff2231..9b9b5841b 100644 --- a/hw/bsp/lpc54/family.c +++ b/hw/bsp/lpc54/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "fsl_device_registers.h" #include "fsl_gpio.h" #include "fsl_power.h" diff --git a/hw/bsp/lpc55/boards/double_m33_express/board.h b/hw/bsp/lpc55/boards/double_m33_express/board.h index 975e74e92..dc11e47fc 100644 --- a/hw/bsp/lpc55/boards/double_m33_express/board.h +++ b/hw/bsp/lpc55/boards/double_m33_express/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Double M33 Express + url: https://www.crowdsupply.com/steiert-solutions/double-m33-express +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h index f85701b08..907aee6a4 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h +++ b/hw/bsp/lpc55/boards/lpcxpresso55s28/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso55s28 + url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso55s28-development-board:LPC55S28-EVK +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h index f85701b08..e18d5bbad 100644 --- a/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h +++ b/hw/bsp/lpc55/boards/lpcxpresso55s69/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: LPCXpresso55s69 + url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/lpcxpresso-boards/lpcxpresso55s69-development-board:LPC55S69-EVK +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc55/boards/mcu_link/board.h b/hw/bsp/lpc55/boards/mcu_link/board.h index 5e17cf9fd..1d71b3e79 100644 --- a/hw/bsp/lpc55/boards/mcu_link/board.h +++ b/hw/bsp/lpc55/boards/mcu_link/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MCU Link + url: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcu-link-debug-probe:MCU-LINK +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/lpc55/family.c b/hw/bsp/lpc55/family.c index 68ccf52d5..dbf8d71b7 100644 --- a/hw/bsp/lpc55/family.c +++ b/hw/bsp/lpc55/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "bsp/board_api.h" #include "board.h" #include "fsl_device_registers.h" diff --git a/hw/bsp/max32650/boards/max32650evkit/board.h b/hw/bsp/max32650/boards/max32650evkit/board.h index 196abdaca..65ed2659e 100644 --- a/hw/bsp/max32650/boards/max32650evkit/board.h +++ b/hw/bsp/max32650/boards/max32650evkit/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MAX32650 EVKIT + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html#eb-overview +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/max32650/boards/max32650fthr/board.h b/hw/bsp/max32650/boards/max32650fthr/board.h index d80a8fcae..755fa15b5 100644 --- a/hw/bsp/max32650/boards/max32650fthr/board.h +++ b/hw/bsp/max32650/boards/max32650fthr/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MAX32650 Feather + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/max32650/boards/max32651evkit/board.h b/hw/bsp/max32650/boards/max32651evkit/board.h index 196abdaca..0b49ff309 100644 --- a/hw/bsp/max32650/boards/max32651evkit/board.h +++ b/hw/bsp/max32650/boards/max32651evkit/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MAX32651 EVKIT + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32651-evkit.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/max32650/family.c b/hw/bsp/max32650/family.c index bb382cdd4..8f0e56734 100644 --- a/hw/bsp/max32650/family.c +++ b/hw/bsp/max32650/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Analog Devices +*/ + #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() diff --git a/hw/bsp/max32666/boards/max32666evkit/board.h b/hw/bsp/max32666/boards/max32666evkit/board.h index 0ab1483b8..54589444d 100644 --- a/hw/bsp/max32666/boards/max32666evkit/board.h +++ b/hw/bsp/max32666/boards/max32666evkit/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MAX32666 EVKIT + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666evkit.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/max32666/boards/max32666fthr/board.h b/hw/bsp/max32666/boards/max32666fthr/board.h index c719b748a..0caea5934 100644 --- a/hw/bsp/max32666/boards/max32666fthr/board.h +++ b/hw/bsp/max32666/boards/max32666fthr/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MAX32666 Feather + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32666fthr.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/max32666/family.c b/hw/bsp/max32666/family.c index f96393fe1..05306c6c9 100644 --- a/hw/bsp/max32666/family.c +++ b/hw/bsp/max32666/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Analog Devices +*/ + #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() diff --git a/hw/bsp/max32690/boards/apard32690/board.h b/hw/bsp/max32690/boards/apard32690/board.h index f94097ca9..87b9c4e88 100644 --- a/hw/bsp/max32690/boards/apard32690/board.h +++ b/hw/bsp/max32690/boards/apard32690/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: APARD32690-SL + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/max32690/boards/max32690evkit/board.h b/hw/bsp/max32690/boards/max32690evkit/board.h index 05d60f220..aa8dbb1de 100644 --- a/hw/bsp/max32690/boards/max32690evkit/board.h +++ b/hw/bsp/max32690/boards/max32690evkit/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MAX32690 EVKIT + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32690evkit.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/max32690/family.c b/hw/bsp/max32690/family.c index 2418168d4..7ba5fbef3 100644 --- a/hw/bsp/max32690/family.c +++ b/hw/bsp/max32690/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Analog Devices +*/ + #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() diff --git a/hw/bsp/max78002/boards/max78002evkit/board.h b/hw/bsp/max78002/boards/max78002evkit/board.h index f8102c394..85d55d7de 100644 --- a/hw/bsp/max78002/boards/max78002evkit/board.h +++ b/hw/bsp/max78002/boards/max78002evkit/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MAX78002 EVKIT + url: https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78002evkit.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/max78002/family.c b/hw/bsp/max78002/family.c index 8d51f141c..5c23f40f9 100644 --- a/hw/bsp/max78002/family.c +++ b/hw/bsp/max78002/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Analog Devices +*/ + #ifdef __GNUC__ #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() diff --git a/hw/bsp/mcx/boards/frdm_mcxa153/board.h b/hw/bsp/mcx/boards/frdm_mcxa153/board.h index e207d89d9..fb1290088 100644 --- a/hw/bsp/mcx/boards/frdm_mcxa153/board.h +++ b/hw/bsp/mcx/boards/frdm_mcxa153/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Freedom MCXA153 + url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA153 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/mcx/boards/frdm_mcxn947/board.h b/hw/bsp/mcx/boards/frdm_mcxn947/board.h index acb73363f..a35b6818a 100644 --- a/hw/bsp/mcx/boards/frdm_mcxn947/board.h +++ b/hw/bsp/mcx/boards/frdm_mcxn947/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Freedom MCXN947 + url: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXN947 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/mcx/boards/mcxn947brk/board.h b/hw/bsp/mcx/boards/mcxn947brk/board.h index eae98bfa7..eef281787 100644 --- a/hw/bsp/mcx/boards/mcxn947brk/board.h +++ b/hw/bsp/mcx/boards/mcxn947brk/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MCXN947 Breakout + url: n/a +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/mcx/family.c b/hw/bsp/mcx/family.c index ce54097fe..2b9c60beb 100644 --- a/hw/bsp/mcx/family.c +++ b/hw/bsp/mcx/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: NXP +*/ + #include "bsp/board_api.h" #include "fsl_device_registers.h" #include "fsl_gpio.h" diff --git a/hw/bsp/mm32/boards/mm32f327x_mb39/board.h b/hw/bsp/mm32/boards/mm32f327x_mb39/board.h index 3ac048cf1..ee0800030 100644 --- a/hw/bsp/mm32/boards/mm32f327x_mb39/board.h +++ b/hw/bsp/mm32/boards/mm32f327x_mb39/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: MM32F3273G9P MB-039 + url: https://www.mindmotion.com.cn/support/development_tools/evaluation_boards/evboard/mm32f3273g9p/ +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.h b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.h index 2b3f54a60..522d494a8 100644 --- a/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.h +++ b/hw/bsp/mm32/boards/mm32f327x_pitaya_lite/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: DshanMCU Pitaya Lite with MM32F3273G8P + url: https://gitee.com/weidongshan/DshanMCU-Pitaya-c +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/mm32/family.c b/hw/bsp/mm32/family.c index f0fd6d334..979efb6ca 100644 --- a/hw/bsp/mm32/family.c +++ b/hw/bsp/mm32/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: MindMotion +*/ + #include "hal_conf.h" #include "mm32_device.h" diff --git a/hw/bsp/msp430/boards/msp_exp430f5529lp/board.h b/hw/bsp/msp430/boards/msp_exp430f5529lp/board.h index ccfe321c2..8fbe5cc49 100644 --- a/hw/bsp/msp430/boards/msp_exp430f5529lp/board.h +++ b/hw/bsp/msp430/boards/msp_exp430f5529lp/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MSP430F5529 LaunchPad + url: https://www.ti.com/tool/MSP-EXP430F5529LP +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/msp430/family.c b/hw/bsp/msp430/family.c index 5bb3d3866..a45bd5f93 100644 --- a/hw/bsp/msp430/family.c +++ b/hw/bsp/msp430/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Texas Instruments +*/ + #include "bsp/board_api.h" #include "board.h" #include "msp430.h" diff --git a/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h index 3130d663b..6206bb247 100644 --- a/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h +++ b/hw/bsp/msp432e4/boards/msp_exp432e401y/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: MSP432E401Y LaunchPad + url: https://www.ti.com/tool/MSP-EXP432E401Y +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/msp432e4/family.c b/hw/bsp/msp432e4/family.c index d5ef7f930..9a3b48b66 100644 --- a/hw/bsp/msp432e4/family.c +++ b/hw/bsp/msp432e4/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Texas Instruments +*/ + #include "bsp/board_api.h" #include "board.h" #include "msp.h" diff --git a/hw/bsp/nrf/boards/adafruit_clue/board.h b/hw/bsp/nrf/boards/adafruit_clue/board.h index 8d6df786e..a5d90f608 100644 --- a/hw/bsp/nrf/boards/adafruit_clue/board.h +++ b/hw/bsp/nrf/boards/adafruit_clue/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit CLUE + url: https://www.adafruit.com/product/4500 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/arduino_nano33_ble/board.h b/hw/bsp/nrf/boards/arduino_nano33_ble/board.h index 00fa8d8ea..6e6a079ab 100644 --- a/hw/bsp/nrf/boards/arduino_nano33_ble/board.h +++ b/hw/bsp/nrf/boards/arduino_nano33_ble/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Arduino Nano 33 BLE + url: https://store.arduino.cc/arduino-nano-33-ble +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h index 3dd354efa..4cdac5f9f 100644 --- a/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h +++ b/hw/bsp/nrf/boards/circuitplayground_bluefruit/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Circuit Playground Bluefruit + url: https://www.adafruit.com/product/4333 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h index 3d59516d8..bfbb98677 100644 --- a/hw/bsp/nrf/boards/feather_nrf52840_express/board.h +++ b/hw/bsp/nrf/boards/feather_nrf52840_express/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Feather nRF52840 Express + url: https://www.adafruit.com/product/4062 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h index 605deea24..288a1b52e 100644 --- a/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h +++ b/hw/bsp/nrf/boards/feather_nrf52840_sense/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Feather nRF52840 Sense + url: https://www.adafruit.com/product/4516 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h index 33c370f53..5f065eec0 100644 --- a/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h +++ b/hw/bsp/nrf/boards/itsybitsy_nrf52840/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit ItsyBitsy nRF52840 Express + url: https://www.adafruit.com/product/4481 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/pca10056/board.h b/hw/bsp/nrf/boards/pca10056/board.h index 24d3faa65..ec632e769 100644 --- a/hw/bsp/nrf/boards/pca10056/board.h +++ b/hw/bsp/nrf/boards/pca10056/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Nordic nRF52840DK + url: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-DK +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/pca10059/board.h b/hw/bsp/nrf/boards/pca10059/board.h index ea3f4030d..3b95481ad 100644 --- a/hw/bsp/nrf/boards/pca10059/board.h +++ b/hw/bsp/nrf/boards/pca10059/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Nordic nRF52840 Dongle + url: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52840-Dongle +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/pca10095/board.h b/hw/bsp/nrf/boards/pca10095/board.h index 846c2ee5b..1c7981049 100644 --- a/hw/bsp/nrf/boards/pca10095/board.h +++ b/hw/bsp/nrf/boards/pca10095/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Nordic nRF5340 DK + url: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF5340-DK +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/boards/pca10100/board.h b/hw/bsp/nrf/boards/pca10100/board.h index 2b2579732..8aca6dce9 100644 --- a/hw/bsp/nrf/boards/pca10100/board.h +++ b/hw/bsp/nrf/boards/pca10100/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Nordic nRF52833 DK + url: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52833-DK +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index 885910f9a..f3132eeb1 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Nordic Semiconductor +*/ + #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/pic32mz/boards/olimex_emz64/board.h b/hw/bsp/pic32mz/boards/olimex_emz64/board.h new file mode 100644 index 000000000..7f42e024f --- /dev/null +++ b/hw/bsp/pic32mz/boards/olimex_emz64/board.h @@ -0,0 +1,43 @@ +/* +* The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: Olimex PIC32-EMZ64 + url: https://www.olimex.com/Products/PIC/Development/PIC32-EMZ64/open-source-hardware +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/pic32mz/boards/olimex_hmz144/board.h b/hw/bsp/pic32mz/boards/olimex_hmz144/board.h new file mode 100644 index 000000000..c9c07bf77 --- /dev/null +++ b/hw/bsp/pic32mz/boards/olimex_hmz144/board.h @@ -0,0 +1,43 @@ +/* +* The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: Olimex PIC32-HMZ144 + url: https://www.olimex.com/Products/PIC/Development/PIC32-HMZ144/open-source-hardware +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/pic32mz/family.c b/hw/bsp/pic32mz/family.c index 895e23899..da97f67a9 100644 --- a/hw/bsp/pic32mz/family.c +++ b/hw/bsp/pic32mz/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Microchip +*/ + #include #include #include diff --git a/hw/bsp/ra/boards/portenta_c33/board.h b/hw/bsp/ra/boards/portenta_c33/board.h index ba663d040..7853c2dbd 100644 --- a/hw/bsp/ra/boards/portenta_c33/board.h +++ b/hw/bsp/ra/boards/portenta_c33/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Arduino Portenta C33 + url: https://www.arduino.cc/pro/hardware-product-portenta-c33/ +*/ + #ifndef _BOARD_H_ #define _BOARD_H_ diff --git a/hw/bsp/ra/boards/ra2a1_ek/board.h b/hw/bsp/ra/boards/ra2a1_ek/board.h index ba663d040..d925fc551 100644 --- a/hw/bsp/ra/boards/ra2a1_ek/board.h +++ b/hw/bsp/ra/boards/ra2a1_ek/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: RA2A1 EK + url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra2a1-evaluation-kit-ra2a1-mcu-group +*/ + #ifndef _BOARD_H_ #define _BOARD_H_ diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.h b/hw/bsp/ra/boards/ra4m1_ek/board.h index ba663d040..e146261be 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/board.h +++ b/hw/bsp/ra/boards/ra4m1_ek/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: RA4M1 EK + url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m1-evaluation-kit-ra4m1-mcu-group +*/ + #ifndef _BOARD_H_ #define _BOARD_H_ diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.h b/hw/bsp/ra/boards/ra4m3_ek/board.h index 9dd2545a0..8b277f6f0 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/board.h +++ b/hw/bsp/ra/boards/ra4m3_ek/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: RA4M3 EK + url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m3-evaluation-kit-ra4m3-mcu-group +*/ + #ifndef _BOARD_H_ #define _BOARD_H_ diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.h b/hw/bsp/ra/boards/ra6m1_ek/board.h index ba663d040..2024a0335 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/board.h +++ b/hw/bsp/ra/boards/ra6m1_ek/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: RA6M1 EK + url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m1-evaluation-kit-ra6m1-mcu-group +*/ + #ifndef _BOARD_H_ #define _BOARD_H_ diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.h b/hw/bsp/ra/boards/ra6m5_ek/board.h index 33dda99b4..32ede3a97 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.h +++ b/hw/bsp/ra/boards/ra6m5_ek/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: RA6M5 EK + url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m5-evaluation-kit-ra6m5-mcu-group +*/ + #ifndef _BOARD_H_ #define _BOARD_H_ diff --git a/hw/bsp/ra/boards/ra8m1_ek/board.h b/hw/bsp/ra/boards/ra8m1_ek/board.h index 33dda99b4..54672452f 100644 --- a/hw/bsp/ra/boards/ra8m1_ek/board.h +++ b/hw/bsp/ra/boards/ra8m1_ek/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: RA8M1 EK + url: https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra8m1-evaluation-kit-ra8m1-mcu-group +*/ + #ifndef _BOARD_H_ #define _BOARD_H_ diff --git a/hw/bsp/ra/boards/uno_r4/board.h b/hw/bsp/ra/boards/uno_r4/board.h index 2c262bb9b..4e7ebb5ce 100644 --- a/hw/bsp/ra/boards/uno_r4/board.h +++ b/hw/bsp/ra/boards/uno_r4/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Arduino UNO R4 + url: https://store-usa.arduino.cc/pages/uno-r4 +*/ + #ifndef _BOARD_H_ #define _BOARD_H_ diff --git a/hw/bsp/ra/family.c b/hw/bsp/ra/family.c index 523b6ff55..0fd24e493 100644 --- a/hw/bsp/ra/family.c +++ b/hw/bsp/ra/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Renesas +*/ + #include #ifdef __GNUC__ diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h index 733e93797..5dbb1dd37 100644 --- a/hw/bsp/rp2040/board.h +++ b/hw/bsp/rp2040/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Pico + url: https://www.raspberrypi.org/products/raspberry-pi-pico/ +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c index 452a5568f..24aa0b616 100644 --- a/hw/bsp/rp2040/family.c +++ b/hw/bsp/rp2040/family.c @@ -25,6 +25,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Raspberry Pi +*/ + #include "pico/stdlib.h" #include "pico/binary_info.h" #include "pico/unique_id.h" diff --git a/hw/bsp/rx/boards/gr_citrus/board.h b/hw/bsp/rx/boards/gr_citrus/board.h new file mode 100644 index 000000000..617d309c3 --- /dev/null +++ b/hw/bsp/rx/boards/gr_citrus/board.h @@ -0,0 +1,43 @@ +/* +* The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: GR Citrus + url: https://www.renesas.com/en/products/gadget-renesas/boards/gr-citrus +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/rx/boards/rx65n_target/board.h b/hw/bsp/rx/boards/rx65n_target/board.h new file mode 100644 index 000000000..8c8e7b95f --- /dev/null +++ b/hw/bsp/rx/boards/rx65n_target/board.h @@ -0,0 +1,43 @@ +/* +* The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: RX65N Target Board + url: https://www.renesas.com/en/products/microcontrollers-microprocessors/rx-32-bit-performance-efficiency-mcus/rtk5rx65n0c00000br-target-board-rx65n +*/ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/samd11/boards/cynthion_d11/board.h b/hw/bsp/samd11/boards/cynthion_d11/board.h index b13c8eeea..8916e9b83 100644 --- a/hw/bsp/samd11/boards/cynthion_d11/board.h +++ b/hw/bsp/samd11/boards/cynthion_d11/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Great Scott Gadgets Cynthion + url: https://greatscottgadgets.com/cynthion/ +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd11/boards/samd11_xplained/board.h b/hw/bsp/samd11/boards/samd11_xplained/board.h index 2bbec4958..13045ac1d 100644 --- a/hw/bsp/samd11/boards/samd11_xplained/board.h +++ b/hw/bsp/samd11/boards/samd11_xplained/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: SAMD11 Xplained Pro + url: https://www.microchip.com/en-us/development-tool/ATSAMD11-XPRO +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd11/family.c b/hw/bsp/samd11/family.c index a6588805a..79ca9de02 100644 --- a/hw/bsp/samd11/family.c +++ b/hw/bsp/samd11/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Microchip +*/ + #include "sam.h" // Suppress warning caused by mcu driver diff --git a/hw/bsp/samd21/boards/atsamd21_xpro/board.h b/hw/bsp/samd21/boards/atsamd21_xpro/board.h index 315e40c78..6d2e40c56 100644 --- a/hw/bsp/samd21/boards/atsamd21_xpro/board.h +++ b/hw/bsp/samd21/boards/atsamd21_xpro/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: SAMD21 Xplained Pro + url: https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAMD21-XPRO +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/circuitplayground_express/board.h b/hw/bsp/samd21/boards/circuitplayground_express/board.h index 0037db00d..6a4ec32a9 100644 --- a/hw/bsp/samd21/boards/circuitplayground_express/board.h +++ b/hw/bsp/samd21/boards/circuitplayground_express/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Circuit Playground Express + url: https://www.adafruit.com/product/3333 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/curiosity_nano/board.h b/hw/bsp/samd21/boards/curiosity_nano/board.h index 1a4a833a3..78d701ec9 100644 --- a/hw/bsp/samd21/boards/curiosity_nano/board.h +++ b/hw/bsp/samd21/boards/curiosity_nano/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: SAMD21 Curiosty Nano + url: https://www.microchip.com/en-us/development-tool/dm320119 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/cynthion_d21/board.h b/hw/bsp/samd21/boards/cynthion_d21/board.h index 776063636..6a2b8c5c6 100644 --- a/hw/bsp/samd21/boards/cynthion_d21/board.h +++ b/hw/bsp/samd21/boards/cynthion_d21/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Great Scott Gadgets Cynthion + url: https://greatscottgadgets.com/cynthion/ +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/feather_m0_express/board.h b/hw/bsp/samd21/boards/feather_m0_express/board.h index 56ae3230d..a7f9122ee 100644 --- a/hw/bsp/samd21/boards/feather_m0_express/board.h +++ b/hw/bsp/samd21/boards/feather_m0_express/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Feather M0 Express + url: https://www.adafruit.com/product/3403 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/itsybitsy_m0/board.h b/hw/bsp/samd21/boards/itsybitsy_m0/board.h index 6ee814da5..15a0afb15 100644 --- a/hw/bsp/samd21/boards/itsybitsy_m0/board.h +++ b/hw/bsp/samd21/boards/itsybitsy_m0/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit ItsyBitsy M0 + url: https://www.adafruit.com/product/3727 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/metro_m0_express/board.h b/hw/bsp/samd21/boards/metro_m0_express/board.h index 6dd53e901..405c92b02 100644 --- a/hw/bsp/samd21/boards/metro_m0_express/board.h +++ b/hw/bsp/samd21/boards/metro_m0_express/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Metro M0 Express + url: https://www.adafruit.com/product/3505 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/qtpy/board.h b/hw/bsp/samd21/boards/qtpy/board.h index 9ba39e966..29a9f727f 100644 --- a/hw/bsp/samd21/boards/qtpy/board.h +++ b/hw/bsp/samd21/boards/qtpy/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit QT Py + url: https://www.adafruit.com/product/4600 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/seeeduino_xiao/board.h b/hw/bsp/samd21/boards/seeeduino_xiao/board.h index 1bd63d6d9..0a6d1fc7d 100644 --- a/hw/bsp/samd21/boards/seeeduino_xiao/board.h +++ b/hw/bsp/samd21/boards/seeeduino_xiao/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Seeeduino XIAO + url: https://wiki.seeedstudio.com/Seeeduino-XIAO/ +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.h b/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.h index 60a86d743..85be34008 100644 --- a/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.h +++ b/hw/bsp/samd21/boards/sparkfun_samd21_mini_usb/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: SparkFun SAMD21 Mini + url: https://www.sparkfun.com/products/13664 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd21/boards/trinket_m0/board.h b/hw/bsp/samd21/boards/trinket_m0/board.h index c94a3abb6..22e7cb77f 100644 --- a/hw/bsp/samd21/boards/trinket_m0/board.h +++ b/hw/bsp/samd21/boards/trinket_m0/board.h @@ -23,6 +23,11 @@ * */ +/* metadata: + name: Adafruit Trinket M0 + url: https://www.adafruit.com/product/3500 +*/ + #pragma once // LED diff --git a/hw/bsp/samd21/family.c b/hw/bsp/samd21/family.c index 7ca20c458..c360a4a5a 100644 --- a/hw/bsp/samd21/family.c +++ b/hw/bsp/samd21/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Microchip +*/ + #include "sam.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/samd5x_e5x/boards/d5035_01/board.h b/hw/bsp/samd5x_e5x/boards/d5035_01/board.h index 2cf59f5d1..4eb4a4ebe 100644 --- a/hw/bsp/samd5x_e5x/boards/d5035_01/board.h +++ b/hw/bsp/samd5x_e5x/boards/d5035_01/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: D5035-01 + url: https://github.com/RudolphRiedel/USB_CAN-FD +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.h b/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.h index 83de04266..edb965c9d 100644 --- a/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.h +++ b/hw/bsp/samd5x_e5x/boards/feather_m4_express/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Feather M4 Express + url: https://www.adafruit.com/product/3857 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h index 272315771..d41ca4ac3 100644 --- a/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h +++ b/hw/bsp/samd5x_e5x/boards/itsybitsy_m4/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit ItsyBitsy M4 + url: https://www.adafruit.com/product/3800 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h index b3b80db89..b2eaaa54d 100644 --- a/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h +++ b/hw/bsp/samd5x_e5x/boards/metro_m4_express/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Metro M4 Express + url: https://www.adafruit.com/product/3382 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd5x_e5x/boards/pybadge/board.h b/hw/bsp/samd5x_e5x/boards/pybadge/board.h index 4629643fd..a5d447db6 100644 --- a/hw/bsp/samd5x_e5x/boards/pybadge/board.h +++ b/hw/bsp/samd5x_e5x/boards/pybadge/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit PyBadge + url: https://www.adafruit.com/product/4200 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd5x_e5x/boards/pyportal/board.h b/hw/bsp/samd5x_e5x/boards/pyportal/board.h index ff04c900b..e635e1375 100644 --- a/hw/bsp/samd5x_e5x/boards/pyportal/board.h +++ b/hw/bsp/samd5x_e5x/boards/pyportal/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit PyPortal + url: https://www.adafruit.com/product/4116 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd5x_e5x/boards/same54_xplained/board.h b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.h index faaa52b8e..6c252f9d0 100644 --- a/hw/bsp/samd5x_e5x/boards/same54_xplained/board.h +++ b/hw/bsp/samd5x_e5x/boards/same54_xplained/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: SAME54 Xplained Pro + url: https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAME54-XPRO +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/samd5x_e5x/family.c b/hw/bsp/samd5x_e5x/family.c index abaee353b..8ceddb1be 100644 --- a/hw/bsp/samd5x_e5x/family.c +++ b/hw/bsp/samd5x_e5x/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Microchip +*/ + #include "sam.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/samg/boards/samg55_xplained/board.h b/hw/bsp/samg/boards/samg55_xplained/board.h index c94cda198..53c557ef0 100644 --- a/hw/bsp/samg/boards/samg55_xplained/board.h +++ b/hw/bsp/samg/boards/samg55_xplained/board.h @@ -1,3 +1,8 @@ +/* metadata: + name: SAMG55 Xplained Pro + url: https://www.microchip.com/DevelopmentTools/ProductDetails/ATSAMG55-XPRO +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/samg/family.c b/hw/bsp/samg/family.c index 63db5739d..8db429e79 100644 --- a/hw/bsp/samg/family.c +++ b/hw/bsp/samg/family.c @@ -23,6 +23,10 @@ * */ +/* metadata: + manufacturer: Microchip +*/ + #include "sam.h" // Suppress warning caused by mcu driver diff --git a/hw/bsp/saml2x/boards/atsaml21_xpro/board.h b/hw/bsp/saml2x/boards/atsaml21_xpro/board.h index 315e40c78..b93b4e591 100644 --- a/hw/bsp/saml2x/boards/atsaml21_xpro/board.h +++ b/hw/bsp/saml2x/boards/atsaml21_xpro/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: SAML21 Xplained Pro + url: https://www.microchip.com/en-us/development-tool/atsaml21-xpro-b +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/saml2x/boards/saml22_feather/board.h b/hw/bsp/saml2x/boards/saml22_feather/board.h index 72e9897b6..f8660c3f8 100644 --- a/hw/bsp/saml2x/boards/saml22_feather/board.h +++ b/hw/bsp/saml2x/boards/saml22_feather/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: SAML22 Feather + url: https://github.com/joeycastillo/Feather-Projects/tree/main/SAML22%20Feather +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/saml2x/boards/sensorwatch_m0/board.h b/hw/bsp/saml2x/boards/sensorwatch_m0/board.h index 735f6afc8..502c799db 100644 --- a/hw/bsp/saml2x/boards/sensorwatch_m0/board.h +++ b/hw/bsp/saml2x/boards/sensorwatch_m0/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: SensorWatch + url: https://github.com/joeycastillo/Sensor-Watch +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/saml2x/family.c b/hw/bsp/saml2x/family.c index 11977b036..cdc65baf1 100644 --- a/hw/bsp/saml2x/family.c +++ b/hw/bsp/saml2x/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Microchip +*/ + #include "sam.h" // Suppress warning caused by mcu driver diff --git a/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h index f08762736..c7d809717 100644 --- a/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h +++ b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h @@ -25,6 +25,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32C071 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-g071rb.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32c0/family.c b/hw/bsp/stm32c0/family.c index dba6a8af1..ace3f2a71 100644 --- a/hw/bsp/stm32c0/family.c +++ b/hw/bsp/stm32c0/family.c @@ -25,6 +25,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32c0xx_hal.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h index 9af81e63c..82ad309a3 100644 --- a/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h +++ b/hw/bsp/stm32f0/boards/stm32f070rbnucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F070 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-f070rb.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f0/boards/stm32f072disco/board.h b/hw/bsp/stm32f0/boards/stm32f072disco/board.h index 1febd01e8..3ca1b3641 100644 --- a/hw/bsp/stm32f0/boards/stm32f072disco/board.h +++ b/hw/bsp/stm32f0/boards/stm32f072disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F072 Discovery + url: https://www.st.com/en/evaluation-tools/32f072bdiscovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f0/boards/stm32f072eval/board.h b/hw/bsp/stm32f0/boards/stm32f072eval/board.h index 7dcfa3e85..2828000b9 100644 --- a/hw/bsp/stm32f0/boards/stm32f072eval/board.h +++ b/hw/bsp/stm32f0/boards/stm32f072eval/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F072 Eval + url: https://www.st.com/en/evaluation-tools/stm32072b-eval.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f0/family.c b/hw/bsp/stm32f0/family.c index 3079a1ed3..ea1373e6c 100644 --- a/hw/bsp/stm32f0/family.c +++ b/hw/bsp/stm32f0/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32f0xx_hal.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h index 2f30a09d4..c8a74337f 100644 --- a/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h +++ b/hw/bsp/stm32f1/boards/stm32f103_bluepill/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F103 Bluepill + url: https://stm32-base.org/boards/STM32F103C8T6-Blue-Pill +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h index c8dba4268..d4824686f 100644 --- a/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h +++ b/hw/bsp/stm32f1/boards/stm32f103_mini_2/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F103 Mini v2 + url: https://stm32-base.org/boards/STM32F103RCT6-STM32-Mini-V2.0 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.h b/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.h index d31102d32..1253c5a48 100644 --- a/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.h +++ b/hw/bsp/stm32f1/boards/stm32f103ze_iar/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: IAR STM32 F103ze starter kit + url: n/a +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f1/family.c b/hw/bsp/stm32f1/family.c index 600fc28c0..29785397f 100644 --- a/hw/bsp/stm32f1/family.c +++ b/hw/bsp/stm32f1/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32f1xx_hal.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/stm32f2/boards/stm32f207nucleo/board.h b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.h index 3301ede27..8d8c52f60 100644 --- a/hw/bsp/stm32f2/boards/stm32f207nucleo/board.h +++ b/hw/bsp/stm32f2/boards/stm32f207nucleo/board.h @@ -1,3 +1,9 @@ + +/* metadata: + name: STM32 F207 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-f207zg.html +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/stm32f2/family.c b/hw/bsp/stm32f2/family.c index 62cca327b..c1333382a 100644 --- a/hw/bsp/stm32f2/family.c +++ b/hw/bsp/stm32f2/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32f2xx_hal.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/stm32f3/boards/stm32f303disco/board.h b/hw/bsp/stm32f3/boards/stm32f303disco/board.h index 706149b49..c79dea945 100644 --- a/hw/bsp/stm32f3/boards/stm32f303disco/board.h +++ b/hw/bsp/stm32f3/boards/stm32f303disco/board.h @@ -1,3 +1,9 @@ + +/* metadata: + name: STM32 F303 Discovery + url: https://www.st.com/en/evaluation-tools/stm32f3discovery.html +*/ + #ifndef BOARD_H #define BOARD_H diff --git a/hw/bsp/stm32f3/family.c b/hw/bsp/stm32f3/family.c index f94dd95cf..84612d416 100644 --- a/hw/bsp/stm32f3/family.c +++ b/hw/bsp/stm32f3/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32f3xx_hal.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h index 670ce8012..11e976a42 100644 --- a/hw/bsp/stm32f4/boards/feather_stm32f405/board.h +++ b/hw/bsp/stm32f4/boards/feather_stm32f405/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Feather STM32F405 + url: https://www.adafruit.com/product/4382 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/pyboardv11/board.h b/hw/bsp/stm32f4/boards/pyboardv11/board.h index 077313518..9583a924b 100644 --- a/hw/bsp/stm32f4/boards/pyboardv11/board.h +++ b/hw/bsp/stm32f4/boards/pyboardv11/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Pyboard v1.1 + url: https://www.adafruit.com/product/2390 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h index ef40089c9..8a3fe8409 100644 --- a/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h +++ b/hw/bsp/stm32f4/boards/stm32f401blackpill/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F401 Blackpill + url: https://stm32-base.org/boards/STM32F401CCU6-WeAct-Black-Pill-V1.2 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h index 6879d066b..effbf2be8 100644 --- a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h +++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F407 Blackvet + url: https://stm32-base.org/boards/STM32F407VET6-STM32-F4VE-V2.0 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/stm32f407disco/board.h b/hw/bsp/stm32f4/boards/stm32f407disco/board.h index 380f8e391..19a029768 100644 --- a/hw/bsp/stm32f4/boards/stm32f407disco/board.h +++ b/hw/bsp/stm32f4/boards/stm32f407disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F407 Discovery + url: https://www.st.com/en/evaluation-tools/stm32f4discovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h index efa618b72..61e5de70d 100644 --- a/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h +++ b/hw/bsp/stm32f4/boards/stm32f411blackpill/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F411 Blackpill + url: https://stm32-base.org/boards/STM32F411CEU6-WeAct-Black-Pill-V2.0 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/stm32f411disco/board.h b/hw/bsp/stm32f4/boards/stm32f411disco/board.h index d4bad8e40..d7b02e79d 100644 --- a/hw/bsp/stm32f4/boards/stm32f411disco/board.h +++ b/hw/bsp/stm32f4/boards/stm32f411disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F411 Discovery + url: https://www.st.com/en/evaluation-tools/32f411ediscovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/stm32f412disco/board.h b/hw/bsp/stm32f4/boards/stm32f412disco/board.h index 74e664418..d5146ae3c 100644 --- a/hw/bsp/stm32f4/boards/stm32f412disco/board.h +++ b/hw/bsp/stm32f4/boards/stm32f412disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F412 Discovery + url: https://www.st.com/en/evaluation-tools/32f412gdiscovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h index 8900a1e6b..f7026ce61 100644 --- a/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h +++ b/hw/bsp/stm32f4/boards/stm32f412nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F412 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-f412zg.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h index aa9de4073..9a348f33f 100644 --- a/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h +++ b/hw/bsp/stm32f4/boards/stm32f439nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F439 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-f439zi.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f4/family.c b/hw/bsp/stm32f4/family.c index 866a09d6f..3a1507dbf 100644 --- a/hw/bsp/stm32f4/family.c +++ b/hw/bsp/stm32f4/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32f4xx_hal.h" #include "bsp/board_api.h" diff --git a/hw/bsp/stm32f7/boards/stlinkv3mini/board.h b/hw/bsp/stm32f7/boards/stlinkv3mini/board.h index 632fd99ed..06adb79ad 100644 --- a/hw/bsp/stm32f7/boards/stlinkv3mini/board.h +++ b/hw/bsp/stm32f7/boards/stlinkv3mini/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Stlink-v3 mini + url: https://www.st.com/en/development-tools/stlink-v3mini.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.h b/hw/bsp/stm32f7/boards/stm32f723disco/board.h index d45ceec5c..35102c1f2 100644 --- a/hw/bsp/stm32f7/boards/stm32f723disco/board.h +++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F723 Discovery + url: https://www.st.com/en/evaluation-tools/32f723ediscovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f7/boards/stm32f746disco/board.h b/hw/bsp/stm32f7/boards/stm32f746disco/board.h index d8e92931e..2964ebada 100644 --- a/hw/bsp/stm32f7/boards/stm32f746disco/board.h +++ b/hw/bsp/stm32f7/boards/stm32f746disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F746 Discovery + url: https://www.st.com/en/evaluation-tools/32f746gdiscovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h index 55e77fe5f..b039f5543 100644 --- a/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h +++ b/hw/bsp/stm32f7/boards/stm32f746nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F746 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-f746zg.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h index 81cb60aeb..b5b3841f1 100644 --- a/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h +++ b/hw/bsp/stm32f7/boards/stm32f767nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F767 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-f767zi.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f7/boards/stm32f769disco/board.h b/hw/bsp/stm32f7/boards/stm32f769disco/board.h index 268919b61..8ac520619 100644 --- a/hw/bsp/stm32f7/boards/stm32f769disco/board.h +++ b/hw/bsp/stm32f7/boards/stm32f769disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 F769 Discovery + url: https://www.st.com/en/evaluation-tools/32f769idiscovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c index 527fbfe5c..5f63834d0 100644 --- a/hw/bsp/stm32f7/family.c +++ b/hw/bsp/stm32f7/family.c @@ -26,6 +26,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32f7xx_hal.h" #include "bsp/board_api.h" diff --git a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h index 9ebaf73f0..14d309da1 100644 --- a/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h +++ b/hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h @@ -25,6 +25,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 G0B1 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-g0b1re.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32g0/family.c b/hw/bsp/stm32g0/family.c index d1635be12..86f2af12e 100644 --- a/hw/bsp/stm32g0/family.c +++ b/hw/bsp/stm32g0/family.c @@ -25,6 +25,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32g0xx_hal.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h index e61b13170..d569783fc 100644 --- a/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h +++ b/hw/bsp/stm32g4/boards/b_g474e_dpow1/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 B-G474E-DPOW1 Discovery kit + url: https://www.st.com/en/evaluation-tools/b-g474e-dpow1.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h index aa2bf20bb..cfef1c09f 100644 --- a/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h +++ b/hw/bsp/stm32g4/boards/stm32g474nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 G474 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-g474re.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32g4/boards/stm32g491nucleo/board.h b/hw/bsp/stm32g4/boards/stm32g491nucleo/board.h index 7dd4ed9ae..be3d44645 100644 --- a/hw/bsp/stm32g4/boards/stm32g491nucleo/board.h +++ b/hw/bsp/stm32g4/boards/stm32g491nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 G491 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-g491re.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c index 2259cb9e2..d0ef7e503 100644 --- a/hw/bsp/stm32g4/family.c +++ b/hw/bsp/stm32g4/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32g4xx_hal.h" #include "stm32g4xx_ll_bus.h" diff --git a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h index da20cfa3a..c8b5e31f5 100644 --- a/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h +++ b/hw/bsp/stm32h5/boards/stm32h503nucleo/board.h @@ -25,6 +25,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H503 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-h503rb.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h index c4e0f680b..adc3d751a 100644 --- a/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h +++ b/hw/bsp/stm32h5/boards/stm32h563nucleo/board.h @@ -25,6 +25,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H563 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-h563zi.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h b/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h index 7baef6ca6..d75114397 100644 --- a/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h +++ b/hw/bsp/stm32h5/boards/stm32h573i_dk/board.h @@ -25,6 +25,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H573i Discovery + url: https://www.st.com/en/evaluation-tools/stm32h573i-dk.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h5/family.c b/hw/bsp/stm32h5/family.c index 02500db4e..efc5bb7b1 100644 --- a/hw/bsp/stm32h5/family.c +++ b/hw/bsp/stm32h5/family.c @@ -25,6 +25,9 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ // Suppress warning caused by mcu driver #ifdef __GNUC__ diff --git a/hw/bsp/stm32h7/boards/daisyseed/board.h b/hw/bsp/stm32h7/boards/daisyseed/board.h index 2d681d640..300ecb8b2 100644 --- a/hw/bsp/stm32h7/boards/daisyseed/board.h +++ b/hw/bsp/stm32h7/boards/daisyseed/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Daisy Seed + url: https://electro-smith.com/products/daisy-seed +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h index c5257901d..f623149bd 100644 --- a/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h +++ b/hw/bsp/stm32h7/boards/stm32h723nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H723 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-h723zg.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h index fa9721be3..821c799d7 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h @@ -24,10 +24,14 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H743 Eval + url: https://www.st.com/en/evaluation-tools/stm32h743i-eval.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ -#ifdef __cplusplus extern "C" { #endif diff --git a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h index 0606f395a..0277d05c7 100644 --- a/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h +++ b/hw/bsp/stm32h7/boards/stm32h743nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H743 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-h743zi.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h7/boards/stm32h745disco/board.h b/hw/bsp/stm32h7/boards/stm32h745disco/board.h index b9d9cdea4..ebdd5a17a 100644 --- a/hw/bsp/stm32h7/boards/stm32h745disco/board.h +++ b/hw/bsp/stm32h7/boards/stm32h745disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H745 Discovery + url: https://www.st.com/en/evaluation-tools/stm32h745i-disco.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h7/boards/stm32h750_weact/board.h b/hw/bsp/stm32h7/boards/stm32h750_weact/board.h index f1c363082..e11a55103 100644 --- a/hw/bsp/stm32h7/boards/stm32h750_weact/board.h +++ b/hw/bsp/stm32h7/boards/stm32h750_weact/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H750 WeAct + url: https://www.adafruit.com/product/5032 +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h7/boards/stm32h750bdk/board.h b/hw/bsp/stm32h7/boards/stm32h750bdk/board.h index 2895f0973..ac417601b 100644 --- a/hw/bsp/stm32h7/boards/stm32h750bdk/board.h +++ b/hw/bsp/stm32h7/boards/stm32h750bdk/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 H750b Discovery Kit + url: https://www.st.com/en/evaluation-tools/stm32h750b-dk.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h index 625c6a137..bfaf42784 100644 --- a/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h +++ b/hw/bsp/stm32h7/boards/waveshare_openh743i/board.h @@ -26,6 +26,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Waveshare Open H743i + url: https://www.waveshare.com/openh743i-c-standard.htm +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c index 0be18350c..e5228b29b 100644 --- a/hw/bsp/stm32h7/family.c +++ b/hw/bsp/stm32h7/family.c @@ -27,6 +27,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32h7xx_hal.h" #include "bsp/board_api.h" diff --git a/hw/bsp/stm32l0/boards/stm32l052dap52/board.h b/hw/bsp/stm32l0/boards/stm32l052dap52/board.h index ee83bbcbc..50bbafadb 100644 --- a/hw/bsp/stm32l0/boards/stm32l052dap52/board.h +++ b/hw/bsp/stm32l0/boards/stm32l052dap52/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 L052 DAP + url: n/a +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32l0/boards/stm32l0538disco/board.h b/hw/bsp/stm32l0/boards/stm32l0538disco/board.h index 5cda1c15a..29402f00a 100644 --- a/hw/bsp/stm32l0/boards/stm32l0538disco/board.h +++ b/hw/bsp/stm32l0/boards/stm32l0538disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 L0538 Discovery + url: https://www.st.com/en/evaluation-tools/32l0538discovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32l0/family.c b/hw/bsp/stm32l0/family.c index c8c88d687..b28903e00 100644 --- a/hw/bsp/stm32l0/family.c +++ b/hw/bsp/stm32l0/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32l0xx_hal.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h index 72d17b760..980e1e321 100644 --- a/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h +++ b/hw/bsp/stm32l4/boards/stm32l412nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 L412 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-l412kb.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.h b/hw/bsp/stm32l4/boards/stm32l476disco/board.h index 9d4351b39..8c766d8ea 100644 --- a/hw/bsp/stm32l4/boards/stm32l476disco/board.h +++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 L476 Disco + url: https://www.st.com/en/evaluation-tools/32l476gdiscovery.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h index 47ada6bb9..f522e7522 100644 --- a/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h +++ b/hw/bsp/stm32l4/boards/stm32l4p5nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 L4P5 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-l4p5zg.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h index 47ada6bb9..c181f5d4a 100644 --- a/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h +++ b/hw/bsp/stm32l4/boards/stm32l4r5nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 L4R5 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-l4r5zi.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32l4/family.c b/hw/bsp/stm32l4/family.c index 965c4810a..2b555b5c2 100644 --- a/hw/bsp/stm32l4/family.c +++ b/hw/bsp/stm32l4/family.c @@ -26,6 +26,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32l4xx_hal.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h index 2f1c451db..cf3f63ea5 100644 --- a/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h +++ b/hw/bsp/stm32u5/boards/b_u585i_iot2a/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 B-U585i IOT2A Discovery kit + url: https://www.st.com/en/evaluation-tools/b-u585i-iot02a.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h index 7f3bf462c..0c3439b2c 100644 --- a/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h +++ b/hw/bsp/stm32u5/boards/stm32u545nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 U545 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-u545re-q.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32u5/boards/stm32u575eval/board.h b/hw/bsp/stm32u5/boards/stm32u575eval/board.h index bd91502af..b11f6a747 100644 --- a/hw/bsp/stm32u5/boards/stm32u575eval/board.h +++ b/hw/bsp/stm32u5/boards/stm32u575eval/board.h @@ -25,6 +25,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 U575 Eval + url: https://www.st.com/en/evaluation-tools/stm32u575i-ev.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h index 6d244d418..be037b68a 100644 --- a/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h +++ b/hw/bsp/stm32u5/boards/stm32u575nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 U575 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-u575zi-q.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h index 062fb807f..0785fb36b 100644 --- a/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h +++ b/hw/bsp/stm32u5/boards/stm32u5a5nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 U5a5 Nucleo + url: https://www.st.com/en/evaluation-tools/nucleo-u5a5zj-q.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32u5/family.c b/hw/bsp/stm32u5/family.c index 3cc7cc511..032c01f34 100644 --- a/hw/bsp/stm32u5/family.c +++ b/hw/bsp/stm32u5/family.c @@ -25,6 +25,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + // Suppress warning caused by mcu driver #ifdef __GNUC__ #pragma GCC diagnostic push diff --git a/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h index ea975df03..704592506 100644 --- a/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h +++ b/hw/bsp/stm32wb/boards/stm32wb55nucleo/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: STM32 P-NUCLEO-WB55 + url: https://www.st.com/en/evaluation-tools/p-nucleo-wb55.html +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/stm32wb/family.c b/hw/bsp/stm32wb/family.c index 6051388a7..43e1345c8 100644 --- a/hw/bsp/stm32wb/family.c +++ b/hw/bsp/stm32wb/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: STMicroelectronics +*/ + #include "stm32wbxx_hal.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.h b/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.h index 5732056ae..c0ceb4cd8 100644 --- a/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.h +++ b/hw/bsp/tm4c/boards/ek_tm4c123gxl/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: TM4C123G LaunchPad + url: https://www.ti.com/tool/EK-TM4C123GXL +*/ + #ifndef _BOARD_H_ #define _BOARD_H_ diff --git a/hw/bsp/tm4c/family.c b/hw/bsp/tm4c/family.c index 5e1f6d3ff..4e5491005 100644 --- a/hw/bsp/tm4c/family.c +++ b/hw/bsp/tm4c/family.c @@ -1,3 +1,7 @@ +/* metadata: + manufacturer: Texas Instruments +*/ + #include "TM4C123.h" #include "bsp/board_api.h" #include "board.h" diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.h b/hw/bsp/xmc4000/boards/xmc4500_relax/board.h index 2d4764f40..3d0e92b2c 100644 --- a/hw/bsp/xmc4000/boards/xmc4500_relax/board.h +++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: XMC4500 relax kit + url: https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc45_relax_v1/ +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/xmc4000/boards/xmc4700_relax/board.h b/hw/bsp/xmc4000/boards/xmc4700_relax/board.h index aa12fde3b..f3972980c 100644 --- a/hw/bsp/xmc4000/boards/xmc4700_relax/board.h +++ b/hw/bsp/xmc4000/boards/xmc4700_relax/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: XMC4700 relax kit + url: https://www.infineon.com/cms/en/product/evaluation-boards/kit_xmc47_relax_v1/ +*/ + #ifndef BOARD_H_ #define BOARD_H_ diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c index c776cb58a..1acce024b 100644 --- a/hw/bsp/xmc4000/family.c +++ b/hw/bsp/xmc4000/family.c @@ -24,6 +24,10 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + manufacturer: Infineon +*/ + #include "xmc_gpio.h" #include "xmc_scu.h" #include "xmc_uart.h" diff --git a/tools/gen_doc.py b/tools/gen_doc.py index c69f3ff29..318ff8089 100755 --- a/tools/gen_doc.py +++ b/tools/gen_doc.py @@ -1,4 +1,5 @@ #!/usr/bin/env python3 +import re import pandas as pd from tabulate import tabulate from pathlib import Path @@ -11,7 +12,6 @@ TOP = Path(__file__).parent.parent.resolve() # ----------------------------------------- # Dependencies # ----------------------------------------- - def gen_deps_doc(): deps_rst = Path(TOP) / "docs/reference/dependencies.rst" df = pd.DataFrame.from_dict(deps_all, orient='index', columns=['Repo', 'Commit', 'Required by']) @@ -32,5 +32,81 @@ MCU low-level peripheral driver and external libraries for building TinyUSB exam f.write(outstr) +# ----------------------------------------- +# Dependencies +# ----------------------------------------- +def extract_metadata(file_path): + metadata = {} + try: + with open(file_path, 'r') as file: + content = file.read() + # Match metadata block + match = re.search(r'/\*\s*metadata:(.*?)\*/', content, re.DOTALL) + if match: + block = match.group(1) + # Extract key-value pairs + for line in block.splitlines(): + key_value = re.match(r'\s*(\w+):\s*(.+)', line) + if key_value: + key, value = key_value.groups() + metadata[key] = value.strip() + except FileNotFoundError: + pass + return metadata + + +def gen_boards_doc(): + # 'Manufacturer' : { 'Board' } + vendor_data = {} + # 'Board' : [ 'Name', 'Family', 'url', 'note' ] + all_boards = {} + # extract metadata from family.c + for family_dir in sorted((Path(TOP) / "hw/bsp").iterdir()): + if family_dir.is_dir(): + family_c = family_dir / "family.c" + if not family_c.exists(): + family_c = family_dir / "boards/family.c" + f_meta = extract_metadata(family_c) + if not f_meta: + continue + manuf = f_meta.get('manufacturer', '') + if manuf not in vendor_data: + vendor_data[manuf] = {} + # extract metadata from board.h + for board_dir in sorted((family_dir / "boards").iterdir()): + if board_dir.is_dir(): + b_meta = extract_metadata(board_dir / "board.h") + if not b_meta: + continue + b_entry = [ + b_meta.get('name', ''), + family_dir.name, + b_meta.get('url', ''), + b_meta.get('note', '') + ] + vendor_data[manuf][board_dir.name] = b_entry + boards_rst = Path(TOP) / "docs/reference/boards.rst" + with boards_rst.open('w') as f: + title = f"""\ +**************** +Supported Boards +**************** + +Following boards are supported and can be used to run stock examples + +""" + f.write(title) + for manuf, boards in sorted(vendor_data.items()): + f.write(f"\n\n{manuf}\n") + f.write(f"{'=' * len(manuf)}\n\n") + df = pd.DataFrame.from_dict(boards, orient='index', columns=['Name', 'Family', 'URL', 'Note']) + df = df.rename_axis("Board") + f.write(tabulate(df, headers="keys", tablefmt='rst')) + + +# ----------------------------------------- +# Main +# ----------------------------------------- if __name__ == "__main__": gen_deps_doc() + gen_boards_doc() -- cgit v1.3.1 From 824793a428aea082b4ae887ce7a26b4736e1d2cc Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Dec 2024 09:58:07 +0700 Subject: move mcu supported to README.rst, separated supported boards to boards.rst --- README.rst | 213 +++++++++----- docs/reference/boards.rst | 39 +-- docs/reference/getting_started.rst | 2 +- docs/reference/index.rst | 1 - docs/reference/supported.rst | 442 ---------------------------- hw/bsp/stm32h7/boards/stm32h743eval/board.h | 1 + tools/gen_doc.py | 11 +- 7 files changed, 176 insertions(+), 533 deletions(-) delete mode 100644 docs/reference/supported.rst (limited to 'hw') diff --git a/README.rst b/README.rst index db36cad3b..eb024968e 100644 --- a/README.rst +++ b/README.rst @@ -82,8 +82,8 @@ Host Stack Similar to the Device Stack, if you have a special requirement, `usbh_app_driver_get_cb()` can be used to write your own class driver without modifying the stack. -TypeC PD Stack -============== +Power Delivery Stack +==================== - Power Delivery 3.0 (PD3.0) with USB Type-C support (WIP) - Super early stage, only for testing purpose @@ -102,75 +102,150 @@ TinyUSB is completely thread-safe by pushing all Interrupt Service Request (ISR) Supported CPUs ============== -Following CPUs are supported, check out `Supported Devices`_ for comprehensive list of driver, features for each CPU. - -+--------------+------------------------------------------------------------+ -| Manufacturer | Family | -+==============+============================================================+ -| Allwinner | F1C100s/F1C200s | -+--------------+------------------------------------------------------------+ -| Analog | max32: 650, 666, 690. max78002 | -| | | -| | max3421e (spi host) | -+--------------+------------------------------------------------------------+ -| Brigetek | FT90x | -+--------------+------------------------------------------------------------+ -| Broadcom | BCM2711, BCM2837 | -+--------------+------------------------------------------------------------+ -| Dialog | DA1469x | -+--------------+------------------------------------------------------------+ -| Espressif | ESP32 S2, S3 | -+--------------+------------------------------------------------------------+ -| GigaDevice | GD32VF103 | -+--------------+------------------------------------------------------------+ -| Infineon | XMC4500 | -+--------------+------------------------------------------------------------+ -| | SAM: D11, D21, D51, E5x, G55, L2x, E7x, S7x, V7x | -| MicroChip | | -| | PIC: 24, 32mm, 32mk, 32mx, 32mz, dsPIC33 | -+--------------+------------------------------------------------------------+ -| Mind Montion | mm32 | -+--------------+------------------------------------------------------------+ -| NordicSemi | nRF52833, nRF52840, nRF5340 | -+--------------+------------------------------------------------------------+ -| Nuvoton | NUC 120, 121, 125, 126, 505 | -+--------------+------------------------------------------------------------+ -| NXP | iMXRT: RT10xx, RT11xx | -| | | -| | Kinetis: KL, K32L2 | -| | | -| | LPC: 11u, 13, 15, 17, 18, 40, 43, 51u, 54, 55 | -| | | -| | MCX: A15, N9 | -+--------------+------------------------------------------------------------+ -| Raspberry Pi | RP2040, RP2350 | -+--------------+-----+------------------------------------------------------+ -| Renesas | RA: 4M1, 4M3, 6M1, 6M5 | -| | | -| | RX: 63N, 65N, 72N | -+--------------+-----+------------------------------------------------------+ -| Silabs | EFM32GG12 | -+--------------+------------------------------------------------------------+ -| Sony | CXD56 | -+--------------+------------------------------------------------------------+ -| ST STM32 | C0, F0, F1, F2, F3, F4, F7, G0, G4, H5, H7, | -| | | -| | L0, L1, L4, L4+, L5, U5, WB | -+--------------+------------------------------------------------------------+ -| TI | MSP430, MSP432E4, TM4C123 | -+--------------+------------------------------------------------------------+ -| ValentyUSB | eptri | -+--------------+------------------------------------------------------------+ -| WCH | CH32F: F20x | -| | | -| | CH32V: V20x, V307 | -+--------------+------------------------------------------------------------+ ++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ +| Manufacturer | Family | Device | Host | Highspeed | Driver | Note | ++==============+=============================+========+======+===========+========================+===================+ +| Allwinner | F1C100s/F1C200s | âś” | | âś” | sunxi | musb variant | ++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ +| Analog | MAX3421E | | âś” | âś– | max3421 | via SPI | +| +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| | MAX32 650, 666, 690, | âś” | | âś” | musb | 1-dir ep | +| | MAX78002 | | | | | | ++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ +| Brigetek | FT90x | âś” | | âś” | ft9xx | 1-dir ep | ++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ +| Broadcom | BCM2711, BCM2837 | âś” | | âś” | dwc2 | | ++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ +| Dialog | DA1469x | âś” | âś– | âś– | da146xx | | ++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ +| Espressif | S2, S3 | âś” | âś” | âś– | dwc2 or esp32sx | | +| ESP32 +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| | P4 | âś” | âś” | âś” | dwc2 | | ++--------------+----+------------------------+--------+------+-----------+------------------------+-------------------+ +| GigaDevice | GD32VF103 | âś” | | âś– | dwc2 | | ++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ +| Infineon | XMC4500 | âś” | âś” | âś– | dwc2 | | ++--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+ +| MicroChip | SAM | D11, D21, L21, L22 | âś” | | âś– | samd | | +| | +-----------------------+--------+------+-----------+------------------------+-------------------+ +| | | D51, E5x | âś” | | âś– | samd | | +| | +-----------------------+--------+------+-----------+------------------------+-------------------+ +| | | G55 | âś” | | âś– | samg | 1-dir ep | +| | +-----------------------+--------+------+-----------+------------------------+-------------------+ +| | | E70,S70,V70,V71 | âś” | | âś” | samx7x | 1-dir ep | +| +-----+-----------------------+--------+------+-----------+------------------------+-------------------+ +| | PIC | 24 | âś” | | | pic | ci_fs variant | +| | +-----------------------+--------+------+-----------+------------------------+-------------------+ +| | | 32 mm, mk, mx | âś” | | | pic | ci_fs variant | +| | +-----------------------+--------+------+-----------+------------------------+-------------------+ +| | | dsPIC33 | âś” | | | pic | ci_fs variant | +| | +-----------------------+--------+------+-----------+------------------------+-------------------+ +| | | 32mz | âś” | | | pic32mz | musb variant | ++--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+ +| Mind Montion | mm32 | âś” | | âś– | mm32f327x_otg | ci_fs variant | ++--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+ +| NordicSemi | nRF 52833, 52840, 5340 | âś” | âś– | âś– | nrf5x | only ep8 is ISO | ++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ +| Nuvoton | NUC120 | âś” | âś– | âś– | nuc120 | | +| +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| | NUC121/NUC125 | âś” | âś– | âś– | nuc121 | | +| +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| | NUC126 | âś” | âś– | âś– | nuc121 | | +| +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| | NUC505 | âś” | | âś” | nuc505 | | ++--------------+---------+-------------------+--------+------+-----------+------------------------+-------------------+ +| NXP | iMXRT | RT 10xx, 11xx | âś” | âś” | âś” | ci_hs | | +| +---------+-------------------+--------+------+-----------+------------------------+-------------------+ +| | Kinetis | KL | âś” | âš  | âś– | ci_fs, khci | | +| | +-------------------+--------+------+-----------+------------------------+-------------------+ +| | | K32L2 | âś” | | âś– | khci | ci_fs variant | +| +---------+-------------------+--------+------+-----------+------------------------+-------------------+ +| | LPC | 11u, 13, 15 | âś” | âś– | âś– | lpc_ip3511 | | +| | +-------------------+--------+------+-----------+------------------------+-------------------+ +| | | 17, 40 | âś” | âš  | âś– | lpc17_40 | | +| | +-------------------+--------+------+-----------+------------------------+-------------------+ +| | | 18, 43 | âś” | âś” | âś” | ci_hs | | +| | +-------------------+--------+------+-----------+------------------------+-------------------+ +| | | 51u | âś” | âś– | âś– | lpc_ip3511 | | +| | +-------------------+--------+------+-----------+------------------------+-------------------+ +| | | 54, 55 | âś” | | âś” | lpc_ip3511 | | +| +---------+-------------------+--------+------+-----------+------------------------+-------------------+ +| | MCX | N9, A15 | âś” | | âś” | ci_fs, ci_hs | | ++--------------+---------+-------------------+--------+------+-----------+------------------------+-------------------+ +| Raspberry Pi | RP2040, RP2350 | âś” | âś” | âś– | rp2040, pio_usb | | ++--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+ +| Renesas | RX | 63N, 65N, 72N | âś” | âś” | âś– | rusb2 | | +| +-----+-----------------------+--------+------+-----------+------------------------+-------------------+ +| | RA | 4M1, 4M3, 6M1 | âś” | âś” | âś– | rusb2 | | +| | +-----------------------+--------+------+-----------+------------------------+-------------------+ +| | | 6M5 | âś” | âś” | âś” | rusb2 | | ++--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+ +| Silabs | EFM32GG12 | âś” | | âś– | dwc2 | | ++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ +| Sony | CXD56 | âś” | âś– | âś” | cxd56 | | ++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ +| ST STM32 | F0 | âś” | âś– | âś– | stm32_fsdev | | +| +----+------------------------+--------+------+-----------+------------------------+-------------------+ +| | F1 | 102, 103 | âś” | âś– | âś– | stm32_fsdev | | +| | +------------------------+--------+------+-----------+------------------------+-------------------+ +| | | 105, 107 | âś” | âś” | âś– | dwc2 | | +| +----+------------------------+--------+------+-----------+------------------------+-------------------+ +| | F2, F4, F7, H7 | âś” | âś” | âś” | dwc2 | | +| +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| | F3 | âś” | âś– | âś– | stm32_fsdev | | +| +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| | C0, G0, H5 | âś” | | âś– | stm32_fsdev | | +| +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| | G4 | âś” | âś– | âś– | stm32_fsdev | | +| +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| | L0, L1 | âś” | âś– | âś– | stm32_fsdev | | +| +----+------------------------+--------+------+-----------+------------------------+-------------------+ +| | L4 | 4x2, 4x3 | âś” | âś– | âś– | stm32_fsdev | | +| | +------------------------+--------+------+-----------+------------------------+-------------------+ +| | | 4x5, 4x6 | âś” | âś” | âś– | dwc2 | | +| +----+------------------------+--------+------+-----------+------------------------+-------------------+ +| | L4+ | âś” | âś” | âś– | dwc2 | | +| +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| | L5 | âś” | âś– | âś– | stm32_fsdev | | +| +----+------------------------+--------+------+-----------+------------------------+-------------------+ +| | U5 | 535, 545 | âś” | | âś– | stm32_fsdev | | +| | +------------------------+--------+------+-----------+------------------------+-------------------+ +| | | 575, 585 | âś” | âś” | âś– | dwc2 | | +| | +------------------------+--------+------+-----------+------------------------+-------------------+ +| | | 59x,5Ax,5Fx,5Gx | âś” | âś” | âś” | dwc2 | | +| +----+------------------------+--------+------+-----------+------------------------+-------------------+ +| | WBx5 | âś” | âś– | âś– | stm32_fsdev | | ++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ +| TI | MSP430 | âś” | âś– | âś– | msp430x5xx | | +| +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| | MSP432E4 | âś” | | âś– | musb | | +| +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| | TM4C123 | âś” | | âś– | musb | | ++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ +| ValentyUSB | eptri | âś” | âś– | âś– | eptri | | ++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ +| WCH | CH32F20x | âś” | | âś” | ch32_usbhs | | +| +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| | CH32V20x | âś” | | âś– | stm32_fsdev/ch32_usbfs | | +| +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| | CH32V307 | âś” | | âś” | ch32_usbfs/hs | | ++--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ + +Table Legend +------------ + +========= ========================= +âś” Supported +âš  Partial support +âś– Not supported by hardware +\[empty\] Unknown +========= ========================= License ======= -All TinyUSB sources in the ``src`` folder are licensed under MIT -license, the `Full license is here `__. However, each file can be +All TinyUSB files in the ``src`` folder are licensed under the `MIT +license `__. while other files can be individually licensed especially those in ``lib`` and ``hw/mcu`` folder. Please make sure you understand all the license term for files you use in your project. @@ -186,8 +261,8 @@ Docs - `Reference`_ - - `Supported Devices`_ - `Getting Started`_ + - `Supported Boards`_ - `Dependencies`_ - `Concurrency`_ @@ -213,8 +288,8 @@ Docs .. _Changelog: docs/info/changelog.rst .. _Contributors: CONTRIBUTORS.rst .. _Reference: docs/reference/index.rst -.. _Supported Devices: docs/reference/supported.rst .. _Getting Started: docs/reference/getting_started.rst +.. _Supported Boards: docs/reference/boards.rst .. _Dependencies: docs/reference/dependencies.rst .. _Concurrency: docs/reference/concurrency.rst .. _Contributing: docs/contributing/index.rst diff --git a/docs/reference/boards.rst b/docs/reference/boards.rst index 424336dad..4739467bc 100644 --- a/docs/reference/boards.rst +++ b/docs/reference/boards.rst @@ -2,12 +2,17 @@ Supported Boards **************** -Following boards are supported and can be used to run stock examples +The board support code is only used for self-contained examples and testing. It is not used when TinyUSB is part of a larger project. +It is responsible for getting the MCU started and the USB peripheral clocked with minimal of on-board devices +- One LED : for status +- One Button : to get input from user +- One UART : optional for device, but required for host examples +Following boards are supported Analog Devices -============== +-------------- ============= ================ ======== =========================================================================================================================== ====== Board Name Family URL Note @@ -23,7 +28,7 @@ max78002evkit MAX78002 EVKIT max78002 https://www.analog.com/en/resources/e ============= ================ ======== =========================================================================================================================== ====== Bridgetek -========= +--------- ========= ========= ======== ===================================== ====== Board Name Family URL Note @@ -32,7 +37,7 @@ mm900evxb MM900EVxB brtmm90x https://brtchip.com/product/mm900ev1b ========= ========= ======== ===================================== ====== Espressif -========= +--------- ========================= ============================== ========= ======================================================================================================== ====== Board Name Family URL Note @@ -54,7 +59,7 @@ espressif_saola_1 Espresif S2 Saola 1 espressif https://do ========================= ============================== ========= ======================================================================================================== ====== GigaDevice -========== +---------- ================== ================== ========= ============================= ====== Board Name Family URL Note @@ -63,7 +68,7 @@ sipeed_longan_nano Sipeed Longan Nano gd32vf103 https://longan.sipeed.com/en/ ================== ================== ========= ============================= ====== Infineon -======== +-------- ============= ================= ======== ============================================================================= ====== Board Name Family URL Note @@ -73,7 +78,7 @@ xmc4700_relax XMC4700 relax kit xmc4000 https://www.infineon.com/cms/en/prod ============= ================= ======== ============================================================================= ====== Microchip -========= +--------- ========================= =================================== ========== ================================================================================= ====== Board Name Family URL Note @@ -107,7 +112,7 @@ sensorwatch_m0 SensorWatch saml2x http ========================= =================================== ========== ================================================================================= ====== MindMotion -========== +---------- ===================== ====================================== ======== =============================================================================================== ====== Board Name Family URL Note @@ -117,7 +122,7 @@ mm32f327x_pitaya_lite DshanMCU Pitaya Lite with MM32F3273G8P mm32 https:/ ===================== ====================================== ======== =============================================================================================== ====== NXP -=== +--- ================== ========================================= ============= ========================================================================================================================================================================= ====== Board Name Family URL Note @@ -165,7 +170,7 @@ mcxn947brk MCXN947 Breakout mcx n/ ================== ========================================= ============= ========================================================================================================================================================================= ====== Nordic Semiconductor -==================== +-------------------- =========================== ===================================== ======== ============================================================================== ====== Board Name Family URL Note @@ -183,7 +188,7 @@ pca10100 Nordic nRF52833 DK nrf ht =========================== ===================================== ======== ============================================================================== ====== Raspberry Pi -============ +------------ ================= ================= ============== ========================================================== ====== Board Name Family URL Note @@ -194,7 +199,7 @@ raspberrypi_zero2 Raspberry Zero2 broadcom_64bit https://www.raspberrypi.or ================= ================= ============== ========================================================== ====== Renesas -======= +------- ============== =========================== ======== ================================================================================================================================================================ ====== Board Name Family URL Note @@ -212,7 +217,7 @@ uno_r4 Arduino UNO R4 ra https://store-usa.arduino ============== =========================== ======== ================================================================================================================================================================ ====== STMicroelectronics -================== +------------------ =================== ================================= ======== ================================================================= ====== Board Name Family URL Note @@ -272,7 +277,7 @@ stm32wb55nucleo STM32 P-NUCLEO-WB55 stm32wb https://www.st =================== ================================= ======== ================================================================= ====== Sunxi -===== +----- ======= ================= ======== ========================================= ====== Board Name Family URL Note @@ -281,7 +286,7 @@ f1c100s Lctech Pi F1C200s f1c100s https://linux-sunxi.org/Lctech_Pi_F1C200s ======= ================= ======== ========================================= ====== Texas Instruments -================= +----------------- ================= ===================== ======== ========================================= ====== Board Name Family URL Note @@ -292,7 +297,7 @@ ek_tm4c123gxl TM4C123G LaunchPad tm4c https://www.ti.com/tool/EK-T ================= ===================== ======== ========================================= ====== Tomu -==== +---- ======= ====== ======== ========================= ====== Board Name Family URL Note @@ -301,7 +306,7 @@ fomu fomu fomu https://tomu.im/fomu.html ======= ====== ======== ========================= ====== WCH -=== +--- ================ ================ ======== ===================================================================== ====== Board Name Family URL Note diff --git a/docs/reference/getting_started.rst b/docs/reference/getting_started.rst index 671e9fb11..963420f7b 100644 --- a/docs/reference/getting_started.rst +++ b/docs/reference/getting_started.rst @@ -50,7 +50,7 @@ It is relatively simple to incorporate tinyusb to your project Examples -------- -For your convenience, TinyUSB contains a handful of examples for both host and device with/without RTOS to quickly test the functionality as well as demonstrate how API() should be used. Most examples will work on most of `the supported boards `_. Firstly we need to ``git clone`` if not already +For your convenience, TinyUSB contains a handful of examples for both host and device with/without RTOS to quickly test the functionality as well as demonstrate how API() should be used. Most examples will work on most of `the supported boards `_. Firstly we need to ``git clone`` if not already .. code-block:: diff --git a/docs/reference/index.rst b/docs/reference/index.rst index e9b033033..3a55503b7 100644 --- a/docs/reference/index.rst +++ b/docs/reference/index.rst @@ -80,7 +80,6 @@ Index :maxdepth: 2 getting_started - supported boards dependencies concurrency diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst deleted file mode 100644 index cbd6c4786..000000000 --- a/docs/reference/supported.rst +++ /dev/null @@ -1,442 +0,0 @@ -***************** -Supported Devices -***************** - -Supported MCUs -============== - -+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ -| Manufacturer | Family | Device | Host | Highspeed | Driver | Note | -+==============+=============================+========+======+===========+========================+===================+ -| Allwinner | F1C100s/F1C200s | âś” | | âś” | sunxi | musb variant | -+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ -| Analog | MAX3421E | | âś” | âś– | max3421 | via SPI | -| +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | MAX32 650, 666, 690, | âś” | | âś” | musb | 1-dir ep | -| | MAX78002 | | | | | | -+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ -| Brigetek | FT90x | âś” | | âś” | ft9xx | 1-dir ep | -+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ -| Broadcom | BCM2711, BCM2837 | âś” | | âś” | dwc2 | | -+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ -| Dialog | DA1469x | âś” | âś– | âś– | da146xx | | -+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ -| Espressif | S2, S3 | âś” | âś” | âś– | dwc2 or esp32sx | | -| ESP32 +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | P4 | âś” | âś” | âś” | dwc2 | | -+--------------+----+------------------------+--------+------+-----------+------------------------+-------------------+ -| GigaDevice | GD32VF103 | âś” | | âś– | dwc2 | | -+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ -| Infineon | XMC4500 | âś” | âś” | âś– | dwc2 | | -+--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+ -| MicroChip | SAM | D11, D21, L21, L22 | âś” | | âś– | samd | | -| | +-----------------------+--------+------+-----------+------------------------+-------------------+ -| | | D51, E5x | âś” | | âś– | samd | | -| | +-----------------------+--------+------+-----------+------------------------+-------------------+ -| | | G55 | âś” | | âś– | samg | 1-dir ep | -| | +-----------------------+--------+------+-----------+------------------------+-------------------+ -| | | E70,S70,V70,V71 | âś” | | âś” | samx7x | 1-dir ep | -| +-----+-----------------------+--------+------+-----------+------------------------+-------------------+ -| | PIC | 24 | âś” | | | pic | ci_fs variant | -| | +-----------------------+--------+------+-----------+------------------------+-------------------+ -| | | 32 mm, mk, mx | âś” | | | pic | ci_fs variant | -| | +-----------------------+--------+------+-----------+------------------------+-------------------+ -| | | dsPIC33 | âś” | | | pic | ci_fs variant | -| | +-----------------------+--------+------+-----------+------------------------+-------------------+ -| | | 32mz | âś” | | | pic32mz | musb variant | -+--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+ -| Mind Montion | mm32 | âś” | | âś– | mm32f327x_otg | ci_fs variant | -+--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+ -| NordicSemi | nRF 52833, 52840, 5340 | âś” | âś– | âś– | nrf5x | only ep8 is ISO | -+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ -| Nuvoton | NUC120 | âś” | âś– | âś– | nuc120 | | -| +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | NUC121/NUC125 | âś” | âś– | âś– | nuc121 | | -| +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | NUC126 | âś” | âś– | âś– | nuc121 | | -| +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | NUC505 | âś” | | âś” | nuc505 | | -+--------------+---------+-------------------+--------+------+-----------+------------------------+-------------------+ -| NXP | iMXRT | RT 10xx, 11xx | âś” | âś” | âś” | ci_hs | | -| +---------+-------------------+--------+------+-----------+------------------------+-------------------+ -| | Kinetis | KL | âś” | âš  | âś– | ci_fs, khci | | -| | +-------------------+--------+------+-----------+------------------------+-------------------+ -| | | K32L2 | âś” | | âś– | khci | ci_fs variant | -| +---------+-------------------+--------+------+-----------+------------------------+-------------------+ -| | LPC | 11u, 13, 15 | âś” | âś– | âś– | lpc_ip3511 | | -| | +-------------------+--------+------+-----------+------------------------+-------------------+ -| | | 17, 40 | âś” | âš  | âś– | lpc17_40 | | -| | +-------------------+--------+------+-----------+------------------------+-------------------+ -| | | 18, 43 | âś” | âś” | âś” | ci_hs | | -| | +-------------------+--------+------+-----------+------------------------+-------------------+ -| | | 51u | âś” | âś– | âś– | lpc_ip3511 | | -| | +-------------------+--------+------+-----------+------------------------+-------------------+ -| | | 54, 55 | âś” | | âś” | lpc_ip3511 | | -| +---------+-------------------+--------+------+-----------+------------------------+-------------------+ -| | MCX | N9, A15 | âś” | | âś” | ci_fs, ci_hs | | -+--------------+---------+-------------------+--------+------+-----------+------------------------+-------------------+ -| Raspberry Pi | RP2040, RP2350 | âś” | âś” | âś– | rp2040, pio_usb | | -+--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+ -| Renesas | RX | 63N, 65N, 72N | âś” | âś” | âś– | rusb2 | | -| +-----+-----------------------+--------+------+-----------+------------------------+-------------------+ -| | RA | 4M1, 4M3, 6M1 | âś” | âś” | âś– | rusb2 | | -| | +-----------------------+--------+------+-----------+------------------------+-------------------+ -| | | 6M5 | âś” | âś” | âś” | rusb2 | | -+--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+ -| Silabs | EFM32GG12 | âś” | | âś– | dwc2 | | -+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ -| Sony | CXD56 | âś” | âś– | âś” | cxd56 | | -+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ -| ST STM32 | F0 | âś” | âś– | âś– | stm32_fsdev | | -| +----+------------------------+--------+------+-----------+------------------------+-------------------+ -| | F1 | 102, 103 | âś” | âś– | âś– | stm32_fsdev | | -| | +------------------------+--------+------+-----------+------------------------+-------------------+ -| | | 105, 107 | âś” | âś” | âś– | dwc2 | | -| +----+------------------------+--------+------+-----------+------------------------+-------------------+ -| | F2, F4, F7, H7 | âś” | âś” | âś” | dwc2 | | -| +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | F3 | âś” | âś– | âś– | stm32_fsdev | | -| +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | C0, G0, H5 | âś” | | âś– | stm32_fsdev | | -| +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | G4 | âś” | âś– | âś– | stm32_fsdev | | -| +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | L0, L1 | âś” | âś– | âś– | stm32_fsdev | | -| +----+------------------------+--------+------+-----------+------------------------+-------------------+ -| | L4 | 4x2, 4x3 | âś” | âś– | âś– | stm32_fsdev | | -| | +------------------------+--------+------+-----------+------------------------+-------------------+ -| | | 4x5, 4x6 | âś” | âś” | âś– | dwc2 | | -| +----+------------------------+--------+------+-----------+------------------------+-------------------+ -| | L4+ | âś” | âś” | âś– | dwc2 | | -| +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | L5 | âś” | âś– | âś– | stm32_fsdev | | -| +----+------------------------+--------+------+-----------+------------------------+-------------------+ -| | U5 | 535, 545 | âś” | | âś– | stm32_fsdev | | -| | +------------------------+--------+------+-----------+------------------------+-------------------+ -| | | 575, 585 | âś” | âś” | âś– | dwc2 | | -| | +------------------------+--------+------+-----------+------------------------+-------------------+ -| | | 59x,5Ax,5Fx,5Gx | âś” | âś” | âś” | dwc2 | | -| +----+------------------------+--------+------+-----------+------------------------+-------------------+ -| | WBx5 | âś” | âś– | âś– | stm32_fsdev | | -+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ -| TI | MSP430 | âś” | âś– | âś– | msp430x5xx | | -| +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | MSP432E4 | âś” | | âś– | musb | | -| +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | TM4C123 | âś” | | âś– | musb | | -+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ -| ValentyUSB | eptri | âś” | âś– | âś– | eptri | | -+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ -| WCH | CH32F20x | âś” | | âś” | ch32_usbhs | | -| +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | CH32V20x | âś” | | âś– | stm32_fsdev/ch32_usbfs | | -| +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | CH32V307 | âś” | | âś” | ch32_usbfs/hs | | -+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ - - -Table Legend ------------- - -========= ========================= -âś” Supported -âš  Partial support -âś– Not supported by hardware -\[empty\] Unknown -========= ========================= - -Supported Boards -================ - -The board support code is only used for self-contained examples and testing. It is not used when TinyUSB is part of a larger project. It is responsible for getting the MCU started and the USB peripheral clocked with minimal of on-board devices - -- One LED : for status -- One Button : to get input from user -- One UART : optional for device, but required for host examples - -The following boards are supported (sorted alphabetically): - -Broadcom --------- - -- `Raspberry Pi CM4 `__ - -Dialog DA146xx --------------- - -- `DA14695 Development Kit – USB `__ -- `DA1469x Development Kit – Pro `__ - -Espressif ESP32-S2 ------------------- - -- `Adafruit Feather ESP32-S2 `__ -- `Adafruit Magtag 2.9" E-Ink WiFi Display `__ -- `Adafruit Metro ESP32-S2 `__ -- `ESP32-S2-Kaluga-1 `__ -- `ESP32-S2-Saola-1 `__ - -GigaDevice ----------- - -- `Sipeed Longan Nano `__ - -Infineon ---------- - -XMC4000 -^^^^^^^ - -- `XMC4500 Relax (Lite) Kit `__ - -MicroChip ---------- - -SAMD11 & SAMD21 -^^^^^^^^^^^^^^^ - -- `Adafruit Circuit Playground Express `__ -- `Adafruit Feather M0 Express `__ -- `Adafruit ItsyBitsy M0 Express `__ -- `Adafruit Metro M0 Express `__ -- `Great Scott Gadgets Cynthion `__ -- `Microchip SAMD11 Xplained Pro `__ -- `Microchip SAMD21 Xplained Pro `__ -- `Seeeduino Xiao `__ - -SAMD51 & SAME54 -^^^^^^^^^^^^^^^ - -- `Adafruit Feather M4 Express `__ -- `Adafruit ItsyBitsy M4 Express `__ -- `Adafruit PyBadge `__ -- `Adafruit PyPortal `__ -- `Adafruit Metro M4 Express `__ -- `D5035-01 `__ -- `Microchip SAME54 Xplained Pro `__ - -SAME7x -^^^^^^ - -- `Microchip SAME70 Xplained `_ -- `QMTECH ATSAME70N19 `_ - -SAMG -^^^^ - -- `Microchip SAMG55 Xplained Pro `__ - -SAML2x -^^^^^^ - -- `SAML21 Xplaind Pro `__ -- `SAML22 Feather `__ -- `Sensor Watch `__ - -Nordic nRF5x ------------- - -- `Adafruit Circuit Playground Bluefruit `__ -- `Adafruit CLUE `__ -- `Adafruit Feather nRF52840 Express `__ -- `Adafruit Feather nRF52840 Sense `__ -- `Adafruit ItsyBitsy nRF52840 Express `__ -- `Arduino Nano 33 BLE `__ -- `Arduino Nano 33 BLE Sense `__ -- `Maker Diary nRF52840 MDK Dongle `__ -- `Nordic nRF52840 Development Kit (aka pca10056) `__ -- `Nordic nRF52840 Dongle (aka pca10059) `__ -- `Nordic nRF52833 Development Kit (aka pca10100) `__ -- `Raytac MDBT50Q-RX Dongle `__ - -Nuvoton -------- - -- NuTiny SDK NUC120 -- `NuTiny NUC121S `__ -- `NuTiny NUC125S `__ -- `NuTiny NUC126V `__ -- `NuTiny SDK NUC505Y `__ - -NXP ---- - -iMX RT -^^^^^^ - -- `MIMX RT1010 Evaluation Kit `__ -- `MIMX RT1015 Evaluation Kit `__ -- `MIMX RT1020 Evaluation Kit `__ -- `MIMX RT1050 Evaluation Kit `__ -- `MIMX RT1060 Evaluation Kit `__ -- `MIMX RT1064 Evaluation Kit `__ -- `Teensy 4.0 Development Board `__ -- `Teensy 4.1 Development Board `__ - -Kinetis -^^^^^^^ - -- `Freedom FRDM-KL25Z `__ -- `Freedom FRDM-K32L2A4S `__ -- `Freedom FRDM-K32L2B3 `__ -- `KUIIC `__ - -LPC 11-13-15 -^^^^^^^^^^^^ - -- `LPCXpresso 11u37 `__ -- `LPCXpresso 11u68 `__ -- `LPCXpresso 1347 `__ -- `LPCXpresso 1549 `__ - -LPC 17-40 -^^^^^^^^^ - -- `ARM mbed LPC1768 `__ -- `Embedded Artists LPC4088 Quick Start board `__ -- `LPCXpresso 1769 `__ - -LPC 18-43 -^^^^^^^^^ - -- `Embedded Artists LPC4357 Developer Kit `__ -- `Keil MCB1800 Evaluation Board `__ -- `LPCXpresso18S37 Development Board `__ - -LPC 51 -^^^^^^ - -- `LPCXpresso 51U68 `__ - -LPC 54 -^^^^^^ - -- `LPCXpresso 54114 `__ - -LPC55 -^^^^^ - -- `Double M33 Express `__ -- `LPCXpresso 55s28 EVK `__ -- `LPCXpresso 55s69 EVK `__ -- `MCU-Link `__ - -Renesas -------- - -RA -^^ - -- `Evaluation Kit for RA4M1 `__ -- `Evaluation Kit for RA4M3 `__ - -RX -^^ - -- `GR-CITRUS `__ -- `Renesas RX65N Target Board `__ - -Raspberry Pi RP2040 -------------------- - -- `Adafruit Feather RP2040 `__ -- `Adafruit ItsyBitsy RP2040 `__ -- `Adafruit QT Py RP2040 `__ -- `Raspberry Pi Pico `__ - -Silabs ------- - -- `EFM32GG12 Thunderboard Kit (SLTB009A) `__ - -Sony ----- - -- `Sony Spresense CXD5602 `__ - -ST STM32 --------- - -F0 -^^ -- `STM32 F070rb Nucleo `__ -- `STM32 F072 Evaluation `__ -- `STM32 F072rb Discovery `__ - -F1 -^^ -- `STM32 F103c8 Blue Pill `__ -- `STM32 F103rc Mini v2.0 `__ - -F2 -^^ -- `STM32 F207zg Nucleo `__ - -F3 -^^ -- `STM32 F303vc Discovery `__ - -F4 -^^ -- `Adafruit Feather STM32F405 `__ -- `Micro Python PyBoard v1.1 `__ -- `STM32 F401cc Black Pill `__ -- `STM32 F407vg Discovery `__ -- `STM32 F411ce Black Pill `__ -- `STM32 F411ve Discovery `__ -- `STM32 F412zg Discovery `__ -- `STM32 F412zg Nucleo `__ -- `STM32 F439zi Nucleo `__ - -F7 -^^ - -- `STLink-V3 Mini `__ -- `STM32 F723e Discovery `__ -- `STM32 F746zg Nucleo `__ -- `STM32 F746g Discovery `__ -- `STM32 F767zi Nucleo `__ -- `STM32 F769i Discovery `__ - -H7 -^^ -- `STM32 H743zi Nucleo `__ -- `STM32 H743i Evaluation `__ -- `STM32 H745i Discovery `__ -- `Waveshare OpenH743I-C `__ - -G4 -^^ -- `STM32 G474RE Nucleo `__ - -L0 -^^ -- `STM32 L035c8 Discovery `__ - -L4 -^^ -- `STM32 L476vg Discovery `__ -- `STM32 L4P5zg Nucleo `__ -- `STM32 L4R5zi Nucleo `__ - -WB -^^ -- `STM32 WB55 Nucleo `__ - -TI --- - -- `MSP430F5529 USB LaunchPad Evaluation Kit `__ -- `MSP-EXP432E401Y LaunchPad Evaluation Kit `__ -- `TM4C123GXL LaunchPad Evaluation Kit `__ - -Tomu ----- - -- `Fomu `__ - -WCH ---- - -- `CH32V307V-R1-1v0 `__ -- `CH32F205R-R0-1v0 `__ diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.h b/hw/bsp/stm32h7/boards/stm32h743eval/board.h index 821c799d7..334876e51 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.h +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.h @@ -32,6 +32,7 @@ #ifndef BOARD_H_ #define BOARD_H_ +#ifdef __cplusplus extern "C" { #endif diff --git a/tools/gen_doc.py b/tools/gen_doc.py index 318ff8089..ab07bc116 100755 --- a/tools/gen_doc.py +++ b/tools/gen_doc.py @@ -92,13 +92,18 @@ def gen_boards_doc(): Supported Boards **************** -Following boards are supported and can be used to run stock examples +The board support code is only used for self-contained examples and testing. It is not used when TinyUSB is part of a larger project. +It is responsible for getting the MCU started and the USB peripheral clocked with minimal of on-board devices -""" +- One LED : for status +- One Button : to get input from user +- One UART : needed for logging with LOGGER=uart, maybe required for host/dual examples + +Following boards are supported""" f.write(title) for manuf, boards in sorted(vendor_data.items()): f.write(f"\n\n{manuf}\n") - f.write(f"{'=' * len(manuf)}\n\n") + f.write(f"{'-' * len(manuf)}\n\n") df = pd.DataFrame.from_dict(boards, orient='index', columns=['Name', 'Family', 'URL', 'Note']) df = df.rename_axis("Board") f.write(tabulate(df, headers="keys", tablefmt='rst')) -- cgit v1.3.1 From 5b32df5abd5667bce7541bed62658750d7f68232 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 20 Jan 2025 22:47:32 +0700 Subject: add s3 undefined speed note for racing issue with reset. fix dcd_event_sof() with frame number --- hw/bsp/espressif/boards/family.c | 12 +++--------- src/portable/nxp/khci/dcd_khci.c | 2 +- 2 files changed, 4 insertions(+), 10 deletions(-) (limited to 'hw') diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index 26e415d94..2f9ecfe4d 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -175,20 +175,14 @@ bool usb_init(void) { // maybe we can use USB_OTG_MODE_DEFAULT and switch using dwc2 driver #if CFG_TUD_ENABLED .otg_mode = USB_OTG_MODE_DEVICE, - .otg_speed = BOARD_TUD_RHPORT ? USB_PHY_SPEED_HIGH : USB_PHY_SPEED_FULL, #elif CFG_TUH_ENABLED .otg_mode = USB_OTG_MODE_HOST, - .otg_speed= BOARD_TUH_RHPORT ? USB_PHY_SPEED_HIGH : USB_PHY_SPEED_FULL, #endif + // https://github.com/hathach/tinyusb/issues/2943#issuecomment-2601888322 + // Set speed to undefined (auto-detect) to avoid timinng/racing issue with S3 with host such as macOS + .otg_speed = USB_PHY_SPEED_UNDEFINED, }; - // OTG IOs config - // const usb_phy_otg_io_conf_t otg_io_conf = USB_PHY_SELF_POWERED_DEVICE(config->vbus_monitor_io); - // if (config->self_powered) { - // phy_conf.otg_io_conf = &otg_io_conf; - // } - // ESP_RETURN_ON_ERROR(usb_new_phy(&phy_conf, &phy_hdl), TAG, "Install USB PHY failed"); - usb_new_phy(&phy_conf, &phy_hdl); return true; diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 8398b09bf..3d5e195a9 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -565,7 +565,7 @@ void dcd_int_handler(uint8_t rhport) if (is & USB_ISTAT_SOFTOK_MASK) { KHCI->ISTAT = USB_ISTAT_SOFTOK_MASK; - dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); + dcd_event_sof(rhport, tu_u16(KHCI->FRMNUMH, KHCI->FRMNUML), true); } if (is & USB_ISTAT_STALL_MASK) { -- cgit v1.3.1 From 91214b46142186b6c30ea468779c7ad39e1bc605 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 16 Jan 2025 10:46:37 +0700 Subject: zephyr --- .west/config | 6 + examples/build_system/cmake/toolchain/common.cmake | 4 +- examples/device/board_test/CMakeLists.txt | 22 +++- examples/device/board_test/src/main.c | 54 ++++++++- examples/device/cdc_msc/CMakeLists.txt | 26 ++++- examples/west.yml | 12 ++ hw/bsp/board_api.h | 38 ++++--- hw/bsp/family_support.cmake | 121 ++++++++++---------- hw/bsp/nrf/boards/pca10056/board.cmake | 6 + hw/bsp/nrf/family.c | 16 +++ hw/bsp/nrf/family.cmake | 28 +++-- hw/bsp/nrf/nrfx_glue.h | 20 ++-- src/CMakeLists.txt | 2 +- src/osal/osal.h | 2 + src/osal/osal_zephyr.h | 123 +++++++++++++++++++++ src/tusb_option.h | 1 + 16 files changed, 371 insertions(+), 110 deletions(-) create mode 100644 .west/config create mode 100644 examples/west.yml create mode 100644 src/osal/osal_zephyr.h (limited to 'hw') diff --git a/.west/config b/.west/config new file mode 100644 index 000000000..2518007f6 --- /dev/null +++ b/.west/config @@ -0,0 +1,6 @@ +[manifest] +path = examples +file = west.yml + +[zephyr] +base = lib/zephyr diff --git a/examples/build_system/cmake/toolchain/common.cmake b/examples/build_system/cmake/toolchain/common.cmake index 688715914..ce97664d5 100644 --- a/examples/build_system/cmake/toolchain/common.cmake +++ b/examples/build_system/cmake/toolchain/common.cmake @@ -13,8 +13,8 @@ set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) # pass TOOLCHAIN_CPU to -set(CMAKE_TRY_COMPILE_PLATFORM_VARIABLES CMAKE_SYSTEM_PROCESSOR) -include(${CMAKE_CURRENT_LIST_DIR}/../cpu/${CMAKE_SYSTEM_PROCESSOR}.cmake) +set(CMAKE_TRY_COMPILE_PLATFORM_VARIABLES CMAKE_SYSTEM_CPU) +include(${CMAKE_CURRENT_LIST_DIR}/../cpu/${CMAKE_SYSTEM_CPU}.cmake) # ---------------------------------------------------------------------------- # Compile flags diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt index 837b4996a..adcc3ba3d 100644 --- a/examples/device/board_test/CMakeLists.txt +++ b/examples/device/board_test/CMakeLists.txt @@ -5,6 +5,11 @@ include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) # gets PROJECT name for the example (e.g. -) family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR}) +if (BUILD_ZEPHYR) + set(BOARD_ROOT ${TOP}/hw/bsp/${FAMILY}) + find_package(Zephyr REQUIRED HINTS ${TOP}/lib/zephyr) +endif () + project(${PROJECT} C CXX ASM) # Checks this example is valid for the family and initializes the project @@ -15,18 +20,27 @@ if(FAMILY STREQUAL "espressif") return() endif() -add_executable(${PROJECT}) +if (BUILD_ZEPHYR) + set(EXE_NAME app) +else() + set(EXE_NAME ${PROJECT}) + add_executable(${EXE_NAME}) +endif() # Example source -target_sources(${PROJECT} PUBLIC +target_sources(${EXE_NAME} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c ) # Example include -target_include_directories(${PROJECT} PUBLIC +target_include_directories(${EXE_NAME} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) # Configure compilation flags and libraries for the example without RTOS. # See the corresponding function in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT} noos) +if (BUILD_ZEPHYR) + family_configure_device_example(${EXE_NAME} zephyr) +else() + family_configure_device_example(${EXE_NAME} noos) +endif() diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c index 2269d45f1..321f6638a 100644 --- a/examples/device/board_test/src/main.c +++ b/examples/device/board_test/src/main.c @@ -23,6 +23,7 @@ * */ +#if 1 #include #include #include @@ -51,7 +52,7 @@ int main(void) { // Blink and print every interval ms if (!(board_millis() - start_ms < interval_ms)) { - board_uart_write(HELLO_STR, strlen(HELLO_STR)); + // board_uart_write(HELLO_STR, strlen(HELLO_STR)); start_ms = board_millis(); @@ -60,12 +61,57 @@ int main(void) { } // echo - uint8_t ch; - if (board_uart_read(&ch, 1) > 0) { - board_uart_write(&ch, 1); + // uint8_t ch; + // if (board_uart_read(&ch, 1) > 0) { + // board_uart_write(&ch, 1); + // } + } +} + +#else +#include +#include +#include + +/* 1000 msec = 1 sec */ +#define SLEEP_TIME_MS 200 + +/* The devicetree node identifier for the "led0" alias. */ +#define LED0_NODE DT_ALIAS(led0) + +/* + * A build error on this line means your board is unsupported. + * See the sample documentation for information on how to fix this. + */ +static const struct gpio_dt_spec led = GPIO_DT_SPEC_GET(LED0_NODE, gpios); + +int main(void) +{ + int ret; + bool led_state = true; + + if (!gpio_is_ready_dt(&led)) { + return 0; + } + + ret = gpio_pin_configure_dt(&led, GPIO_OUTPUT_ACTIVE); + if (ret < 0) { + return 0; + } + + while (1) { + ret = gpio_pin_toggle_dt(&led); + if (ret < 0) { + return 0; } + + led_state = !led_state; + printf("LED state: %s\n", led_state ? "ON" : "OFF"); + k_msleep(SLEEP_TIME_MS); } + return 0; } +#endif #if TUSB_MCU_VENDOR_ESPRESSIF void app_main(void) { diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt index fa7090807..754c5deb0 100644 --- a/examples/device/cdc_msc/CMakeLists.txt +++ b/examples/device/cdc_msc/CMakeLists.txt @@ -6,6 +6,11 @@ include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) # gets PROJECT name for the example (e.g. -) family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR}) +if (BUILD_ZEPHYR) + set(BOARD_ROOT ${TOP}/hw/bsp/${FAMILY}) + find_package(Zephyr REQUIRED HINTS ${TOP}/lib/zephyr) +endif () + project(${PROJECT} C CXX ASM) # Checks this example is valid for the family and initializes the project @@ -16,20 +21,29 @@ if(FAMILY STREQUAL "espressif") return() endif() -add_executable(${PROJECT}) +if (BUILD_ZEPHYR) + set(EXE_NAME app) +else() + set(EXE_NAME ${PROJECT}) + add_executable(${EXE_NAME}) +endif() # Example source -target_sources(${PROJECT} PUBLIC +target_sources(${EXE_NAME} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk.c ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c ) # Example include -target_include_directories(${PROJECT} PUBLIC +target_include_directories(${EXE_NAME} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) -# Configure compilation flags and libraries for the example... see the corresponding function -# in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT} noos) +# Configure compilation flags and libraries for the example without RTOS. +# See the corresponding function in hw/bsp/FAMILY/family.cmake for details. +if (BUILD_ZEPHYR) + family_configure_device_example(${EXE_NAME} zephyr) +else() + family_configure_device_example(${EXE_NAME} noos) +endif() diff --git a/examples/west.yml b/examples/west.yml new file mode 100644 index 000000000..4e2160202 --- /dev/null +++ b/examples/west.yml @@ -0,0 +1,12 @@ +manifest: + remotes: + - name: zephyrproject-rtos + url-base: https://github.com/zephyrproject-rtos + projects: + - name: zephyr + remote: zephyrproject-rtos + revision: v4.0.0 + path: lib/zephyr + import: true + self: + path: . diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h index eaee1ee97..9cdbbf0d3 100644 --- a/hw/bsp/board_api.h +++ b/hw/bsp/board_api.h @@ -38,22 +38,24 @@ extern "C" { #include "tusb.h" -#if CFG_TUSB_OS == OPT_OS_FREERTOS -#if TUSB_MCU_VENDOR_ESPRESSIF - // ESP-IDF need "freertos/" prefix in include path. - // CFG_TUSB_OS_INC_PATH should be defined accordingly. - #include "freertos/FreeRTOS.h" - #include "freertos/semphr.h" - #include "freertos/queue.h" - #include "freertos/task.h" - #include "freertos/timers.h" -#else - #include "FreeRTOS.h" - #include "semphr.h" - #include "queue.h" - #include "task.h" - #include "timers.h" -#endif +#if CFG_TUSB_OS == OPT_OS_ZEPHYR + #include +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + #if TUSB_MCU_VENDOR_ESPRESSIF + // ESP-IDF need "freertos/" prefix in include path. + // CFG_TUSB_OS_INC_PATH should be defined accordingly. + #include "freertos/FreeRTOS.h" + #include "freertos/semphr.h" + #include "freertos/queue.h" + #include "freertos/task.h" + #include "freertos/timers.h" + #else + #include "FreeRTOS.h" + #include "semphr.h" + #include "queue.h" + #include "task.h" + #include "timers.h" + #endif #endif // Define the default baudrate @@ -124,6 +126,10 @@ static inline uint32_t board_millis(void) { // Implement your own board_millis() in any of .c file uint32_t board_millis(void); +#elif CFG_TUSB_OS == OPT_OS_ZEPHYR +static inline uint32_t board_millis(void) { + return k_uptime_get_32(); +} #else #error "board_millis() is not implemented for this OS" #endif diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index ddb17cbb0..3820bb51a 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -73,34 +73,39 @@ if (NOT NO_WARN_RWX_SEGMENTS_SUPPORTED) set(NO_WARN_RWX_SEGMENTS_SUPPORTED 1) endif() -set(WARNING_FLAGS_GNU - -Wall - -Wextra - -Werror - -Wfatal-errors - -Wdouble-promotion - -Wstrict-prototypes - -Wstrict-overflow - -Werror-implicit-function-declaration - -Wfloat-equal - -Wundef - -Wshadow - -Wwrite-strings - -Wsign-compare - -Wmissing-format-attribute - -Wunreachable-code - -Wcast-align - -Wcast-function-type - -Wcast-qual - -Wnull-dereference - -Wuninitialized - -Wunused - -Wreturn-type - -Wredundant-decls - ) +#set(WARNING_FLAGS_GNU +# -Wall +# -Wextra +# -Werror +# -Wfatal-errors +# -Wdouble-promotion +# -Wstrict-prototypes +# -Wstrict-overflow +# -Werror-implicit-function-declaration +# -Wfloat-equal +# -Wundef +# -Wshadow +# -Wwrite-strings +# -Wsign-compare +# -Wmissing-format-attribute +# -Wunreachable-code +# -Wcast-align +# -Wcast-function-type +# -Wcast-qual +# -Wnull-dereference +# -Wuninitialized +# -Wunused +# -Wreturn-type +# -Wredundant-decls +# ) set(WARNING_FLAGS_IAR "") +#if (BUILD_ZEPHYR) +# set(BOARD_ROOT ${TOP}/hw/bsp/${FAMILY}) +# find_package(Zephyr REQUIRED HINTS ${TOP}/lib/zephyr) +#endif () + #------------------------------------------------------------- # Functions #------------------------------------------------------------- @@ -216,7 +221,7 @@ function(family_configure_common TARGET RTOS) if (CMAKE_C_COMPILER_ID STREQUAL "GNU") target_link_options(${TARGET} PUBLIC "LINKER:-Map=$.map") if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 AND NO_WARN_RWX_SEGMENTS_SUPPORTED) - target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") +# target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") endif () elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") target_link_options(${TARGET} PUBLIC "LINKER:-Map=$.map") @@ -244,12 +249,12 @@ function(family_configure_common TARGET RTOS) endif () # run size after build - find_program(SIZE_EXE ${CMAKE_SIZE}) - if(NOT ${SIZE_EXE} STREQUAL SIZE_EXE-NOTFOUND) - add_custom_command(TARGET ${TARGET} POST_BUILD - COMMAND ${SIZE_EXE} $ - ) - endif () +# find_program(SIZE_EXE ${CMAKE_SIZE}) +# if(NOT ${SIZE_EXE} STREQUAL SIZE_EXE-NOTFOUND) +# add_custom_command(TARGET ${TARGET} POST_BUILD +# COMMAND ${SIZE_EXE} $ +# ) +# endif () endfunction() # Add tinyusb to example @@ -272,6 +277,8 @@ function(family_add_tinyusb TARGET OPT_MCU RTOS) if (RTOS STREQUAL "freertos") target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_OS=OPT_OS_FREERTOS) + elseif (RTOS STREQUAL "zephyr") + target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_OS=OPT_OS_ZEPHYR) endif () # tinyusb's CMakeList.txt @@ -280,6 +287,8 @@ function(family_add_tinyusb TARGET OPT_MCU RTOS) if (RTOS STREQUAL "freertos") # link tinyusb with freeRTOS kernel target_link_libraries(${TARGET}-tinyusb PUBLIC freertos_kernel) + elseif (RTOS STREQUAL "zephyr") + target_include_directories(${TARGET}-tinyusb PUBLIC ${ZEPHYR_BASE}/include) endif () # use max3421 as host controller @@ -353,33 +362,33 @@ endfunction() # RPI specific: refactor later #---------------------------------- function(family_add_default_example_warnings TARGET) - target_compile_options(${TARGET} PUBLIC - -Wall - -Wextra - -Werror - -Wfatal-errors - -Wdouble-promotion - -Wfloat-equal - # FIXME commented out because of https://github.com/raspberrypi/pico-sdk/issues/1468 - #-Wshadow - -Wwrite-strings - -Wsign-compare - -Wmissing-format-attribute - -Wunreachable-code - -Wcast-align - -Wcast-qual - -Wnull-dereference - -Wuninitialized - -Wunused - -Wredundant-decls - #-Wstrict-prototypes - #-Werror-implicit-function-declaration - #-Wundef - ) +# target_compile_options(${TARGET} PUBLIC +# -Wall +# -Wextra +# -Werror +# -Wfatal-errors +# -Wdouble-promotion +# -Wfloat-equal +# # FIXME commented out because of https://github.com/raspberrypi/pico-sdk/issues/1468 +# #-Wshadow +# -Wwrite-strings +# -Wsign-compare +# -Wmissing-format-attribute +# -Wunreachable-code +# -Wcast-align +# -Wcast-qual +# -Wnull-dereference +# -Wuninitialized +# -Wunused +# -Wredundant-decls +# #-Wstrict-prototypes +# #-Werror-implicit-function-declaration +# #-Wundef +# ) if (CMAKE_C_COMPILER_ID STREQUAL "GNU") if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 AND NO_WARN_RWX_SEGMENTS_SUPPORTED) - target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") +# target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") endif() # GCC 10 diff --git a/hw/bsp/nrf/boards/pca10056/board.cmake b/hw/bsp/nrf/boards/pca10056/board.cmake index cc370aac8..85314f3bc 100644 --- a/hw/bsp/nrf/boards/pca10056/board.cmake +++ b/hw/bsp/nrf/boards/pca10056/board.cmake @@ -2,3 +2,9 @@ set(MCU_VARIANT nrf52840) function(update_board TARGET) endfunction() + +#board_runner_args(jlink "--device=nRF52840_xxAA" "--speed=4000") +#include(${ZEPHYR_BASE}/boards/common/nrfjprog.board.cmake) +#include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) +#include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +#include(${ZEPHYR_BASE}/boards/common/openocd-nrf5.board.cmake) diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index f3132eeb1..2c3413b9e 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -67,6 +67,8 @@ #define NRFX_VER 3 #endif +extern void nrfx_isr(const void *irq_handler); + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ @@ -137,8 +139,22 @@ void board_init(void) { // Button nrf_gpio_cfg_input(BUTTON_PIN, NRF_GPIO_PIN_PULLUP); +#if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_ZEPHYR + #ifdef CONFIG_HAS_HW_NRF_USBREG + // IRQ_CONNECT(USBREGULATOR_IRQn, DT_IRQ(DT_INST(0, nordic_nrf_clock), priority), nrfx_isr, nrfx_usbreg_irq_handler, 0); + // irq_enable(USBREGULATOR_IRQn); + #endif + + // IRQ_CONNECT(CLOCK_POWER_IRQn, 0, nrfx_isr, nrfx_power_irq_handler, 0); + + /* USB device controller access from devicetree */ + // #define DT_DRV_COMPAT nordic_nrf_usbd + // IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), nrfx_isr, nrf_usbd_common_irq_handler, 0); + +#endif // UART #if NRFX_VER <= 2 diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 7a433d82d..0dfc7579c 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -8,10 +8,10 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up if (MCU_VARIANT STREQUAL "nrf5340_application") - set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") + set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") set(JLINK_DEVICE nrf5340_xxaa_app) else () - set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") + set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(JLINK_DEVICE ${MCU_VARIANT}_xxaa) endif () @@ -113,12 +113,16 @@ endfunction() function(family_configure_example TARGET RTOS) family_configure_common(${TARGET} ${RTOS}) - # Board target - add_board_target(board_${BOARD}) + if (BUILD_ZEPHYR) + #target_link_libraries(board_${BOARD} PUBLIC zephyr_interface kernel) + elseif () + # Board target + add_board_target(board_${BOARD}) + endif () #---------- Port Specific ---------- # These files are built for each example since it depends on example's tusb_config.h - target_sources(${TARGET} PUBLIC + target_sources(${TARGET} PRIVATE # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c @@ -132,16 +136,20 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET}-tinyusb PRIVATE ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + if (BUILD_ZEPHYR) + target_link_libraries(${TARGET}-tinyusb PUBLIC zephyr_interface kernel) + target_link_libraries(${TARGET} PUBLIC ${TARGET}-tinyusb) + elseif () + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + endif () # Flashing - family_add_bin_hex(${TARGET}) + #family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) # family_flash_adafruit_nrfutil(${TARGET}) endfunction() diff --git a/hw/bsp/nrf/nrfx_glue.h b/hw/bsp/nrf/nrfx_glue.h index ef756c670..bc3b3689b 100644 --- a/hw/bsp/nrf/nrfx_glue.h +++ b/hw/bsp/nrf/nrfx_glue.h @@ -1,7 +1,9 @@ /* - * Copyright (c) 2017 - 2018, Nordic Semiconductor ASA + * Copyright (c) 2017 - 2024, Nordic Semiconductor ASA * All rights reserved. * + * SPDX-License-Identifier: BSD-3-Clause + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * @@ -60,14 +62,14 @@ extern "C" { /** * @brief Macro for placing a runtime assertion. * - * @param expression Expression to evaluate. + * @param expression Expression to be evaluated. */ #define NRFX_ASSERT(expression) /** * @brief Macro for placing a compile time assertion. * - * @param expression Expression to evaluate. + * @param expression Expression to be evaluated. */ #define NRFX_STATIC_ASSERT(expression) @@ -76,8 +78,8 @@ extern "C" { /** * @brief Macro for setting the priority of a specific IRQ. * - * @param irq_number IRQ number. - * @param priority Priority to set. + * @param irq_number IRQ number. + * @param priority Priority to be set. */ #define NRFX_IRQ_PRIORITY_SET(irq_number, priority) _NRFX_IRQ_PRIORITY_SET(irq_number, priority) static inline void _NRFX_IRQ_PRIORITY_SET(IRQn_Type irq_number, @@ -158,14 +160,10 @@ static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number) return (NVIC_GetPendingIRQ(irq_number) == 1); } -/** - * @brief Macro for entering into a critical section. - */ +/** @brief Macro for entering into a critical section. */ #define NRFX_CRITICAL_SECTION_ENTER() -/** - * @brief Macro for exiting from a critical section. - */ +/** @brief Macro for exiting from a critical section. */ #define NRFX_CRITICAL_SECTION_EXIT() //------------------------------------------------------------------------------ diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index e8488166e..1d2f37b2d 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -45,7 +45,7 @@ function(add_tinyusb TARGET) target_compile_options(${TARGET} PRIVATE -Wall -Wextra - -Werror + #-Werror -Wfatal-errors -Wdouble-promotion -Wstrict-prototypes diff --git a/src/osal/osal.h b/src/osal/osal.h index 8f45ea5c1..38d45da44 100644 --- a/src/osal/osal.h +++ b/src/osal/osal.h @@ -63,6 +63,8 @@ typedef void (*osal_task_func_t)( void * ); #include "osal_rtthread.h" #elif CFG_TUSB_OS == OPT_OS_RTX4 #include "osal_rtx4.h" +#elif CFG_TUSB_OS == OPT_OS_ZEPHYR + #include "osal_zephyr.h" #elif CFG_TUSB_OS == OPT_OS_CUSTOM #include "tusb_os_custom.h" // implemented by application #else diff --git a/src/osal/osal_zephyr.h b/src/osal/osal_zephyr.h new file mode 100644 index 000000000..8ecb13c6d --- /dev/null +++ b/src/osal/osal_zephyr.h @@ -0,0 +1,123 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ +#ifndef TUSB_OSAL_ZEPHYR_H +#define TUSB_OSAL_ZEPHYR_H + +#include + +//--------------------------------------------------------------------+ +// TASK API +//--------------------------------------------------------------------+ +TU_ATTR_ALWAYS_INLINE static inline void osal_task_delay(uint32_t msec) { + k_msleep(msec); +} + +//--------------------------------------------------------------------+ +// Binary Semaphore API +//--------------------------------------------------------------------+ +typedef struct k_sem osal_semaphore_def_t, * osal_semaphore_t; + +TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) { + k_sem_init(semdef, 0, 255); + return semdef; +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_delete(osal_semaphore_t semd_hdl) { + (void) semd_hdl; + return true; // nothing to do +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) { + (void) in_isr; + k_sem_give(sem_hdl); + return true; +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) { + return 0 == k_sem_take(sem_hdl, K_MSEC(msec)); +} + +TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) { + k_sem_reset(sem_hdl); +} + +//--------------------------------------------------------------------+ +// MUTEX API +//--------------------------------------------------------------------+ +typedef struct k_mutex osal_mutex_def_t, *osal_mutex_t; + +TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) { + if ( 0 == k_mutex_init(mdef) ) { + return mdef; + } else { + return NULL; + } +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_delete(osal_mutex_t mutex_hdl) { + (void) mutex_hdl; + return true; // nothing to do +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) { + return 0 == k_mutex_lock(mutex_hdl, K_MSEC(msec)); +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) { + return 0 == k_mutex_unlock(mutex_hdl); +} + +//--------------------------------------------------------------------+ +// QUEUE API +//--------------------------------------------------------------------+ +typedef struct k_msgq osal_queue_def_t, * osal_queue_t; + +// role device/host is used by OS NONE for mutex (disable usb isr) only +#define OSAL_QUEUE_DEF(_int_set, _name, _depth, _type) K_MSGQ_DEFINE(_name, sizeof(_type), _depth, 4) + +TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) { + // K_MSGQ_DEFINE already initializes the queue + return (osal_queue_t) qdef; +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_delete(osal_queue_t qhdl) { + (void) qhdl; + return true; +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) { + return 0 == k_msgq_get(qhdl, data, K_MSEC(msec)); +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const* data, bool in_isr) { + return 0 == k_msgq_put(qhdl, data, in_isr ? K_NO_WAIT : K_FOREVER); +} + +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) { + return 0 == k_msgq_num_used_get(qhdl); +} + +#endif diff --git a/src/tusb_option.h b/src/tusb_option.h index 86cb6d046..29fdcb0d6 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -215,6 +215,7 @@ #define OPT_OS_PICO 5 ///< Raspberry Pi Pico SDK #define OPT_OS_RTTHREAD 6 ///< RT-Thread #define OPT_OS_RTX4 7 ///< Keil RTX 4 +#define OPT_OS_ZEPHYR 8 ///< Zephyr //--------------------------------------------------------------------+ // Mode and Speed -- cgit v1.3.1 From 6080f89f3daae50344e21accf972061240f55ccd Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Jan 2025 22:31:08 +0700 Subject: - change to use CMAKE_SYSTEM_CPU to prevent CMAKE_SYSTEM_PROCESSOR conflict with zephyr - change tinyusb CMakeLists.txt to function tinyusb_target_add() instead of defining tinyusb lib target --- examples/build_system/cmake/toolchain/common.cmake | 3 +- .../boards/raspberrypi_zero/board.cmake | 2 +- .../boards/raspberrypi_cm4/board.cmake | 2 +- .../boards/raspberrypi_zero2/board.cmake | 2 +- hw/bsp/ch32v10x/family.cmake | 2 +- hw/bsp/ch32v20x/family.cmake | 2 +- hw/bsp/ch32v307/family.cmake | 2 +- hw/bsp/da1469x/family.cmake | 2 +- hw/bsp/f1c100s/family.cmake | 2 +- hw/bsp/family_support.cmake | 138 +++++++++------------ hw/bsp/fomu/family.cmake | 2 +- hw/bsp/gd32vf103/family.cmake | 2 +- hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake | 2 +- hw/bsp/imxrt/family.cmake | 4 +- hw/bsp/kinetis_k/family.cmake | 2 +- hw/bsp/kinetis_k32l2/family.cmake | 2 +- hw/bsp/kinetis_kl/family.cmake | 2 +- hw/bsp/lpc11/family.cmake | 2 +- hw/bsp/lpc13/family.cmake | 2 +- hw/bsp/lpc15/family.cmake | 2 +- hw/bsp/lpc17/family.cmake | 2 +- hw/bsp/lpc18/family.cmake | 2 +- hw/bsp/lpc40/family.cmake | 2 +- hw/bsp/lpc43/family.cmake | 2 +- hw/bsp/lpc51/family.cmake | 2 +- hw/bsp/lpc54/family.cmake | 2 +- hw/bsp/lpc55/family.cmake | 2 +- hw/bsp/max32650/family.cmake | 2 +- hw/bsp/max32666/family.cmake | 2 +- hw/bsp/max32690/family.cmake | 2 +- hw/bsp/max78002/family.cmake | 2 +- hw/bsp/mcx/family.cmake | 4 +- hw/bsp/mm32/family.cmake | 2 +- hw/bsp/msp430/family.cmake | 2 +- hw/bsp/msp432e4/family.cmake | 2 +- hw/bsp/nrf/family.cmake | 26 ++-- hw/bsp/ra/boards/portenta_c33/board.cmake | 2 +- hw/bsp/ra/boards/ra2a1_ek/board.cmake | 2 +- hw/bsp/ra/boards/ra4m1_ek/board.cmake | 2 +- hw/bsp/ra/boards/ra4m3_ek/board.cmake | 2 +- hw/bsp/ra/boards/ra6m1_ek/board.cmake | 2 +- hw/bsp/ra/boards/ra6m5_ek/board.cmake | 2 +- hw/bsp/ra/boards/ra8m1_ek/board.cmake | 2 +- hw/bsp/ra/boards/uno_r4/board.cmake | 2 +- hw/bsp/samd11/family.cmake | 2 +- hw/bsp/samd21/family.cmake | 9 +- hw/bsp/samd5x_e5x/family.cmake | 9 +- hw/bsp/samg/family.cmake | 2 +- hw/bsp/saml2x/family.cmake | 2 +- hw/bsp/stm32c0/family.cmake | 2 +- hw/bsp/stm32f0/family.cmake | 2 +- hw/bsp/stm32f1/family.cmake | 2 +- hw/bsp/stm32f2/family.cmake | 2 +- hw/bsp/stm32f3/family.cmake | 2 +- hw/bsp/stm32f4/family.cmake | 2 +- hw/bsp/stm32f7/family.cmake | 2 +- hw/bsp/stm32g0/family.cmake | 2 +- hw/bsp/stm32g4/family.cmake | 2 +- hw/bsp/stm32h5/family.cmake | 2 +- hw/bsp/stm32h7/family.cmake | 2 +- hw/bsp/stm32l0/family.cmake | 2 +- hw/bsp/stm32l4/family.cmake | 2 +- hw/bsp/stm32u5/family.cmake | 2 +- hw/bsp/stm32wb/family.cmake | 2 +- hw/bsp/tm4c/family.cmake | 2 +- hw/bsp/xmc4000/family.cmake | 2 +- src/CMakeLists.txt | 93 +++++--------- 67 files changed, 168 insertions(+), 236 deletions(-) (limited to 'hw') diff --git a/examples/build_system/cmake/toolchain/common.cmake b/examples/build_system/cmake/toolchain/common.cmake index ce97664d5..4c181137b 100644 --- a/examples/build_system/cmake/toolchain/common.cmake +++ b/examples/build_system/cmake/toolchain/common.cmake @@ -4,6 +4,7 @@ include(CMakePrintHelpers) # Common # ---------------------------------------------------------------------------- set(CMAKE_SYSTEM_NAME Generic) +set(CMAKE_SYSTEM_PROCESSOR ${CMAKE_SYSTEM_CPU}) set_property(GLOBAL PROPERTY TARGET_SUPPORTS_SHARED_LIBS FALSE) # Look for includes and libraries only in the target system prefix. @@ -13,7 +14,7 @@ set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY) set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER) # pass TOOLCHAIN_CPU to -set(CMAKE_TRY_COMPILE_PLATFORM_VARIABLES CMAKE_SYSTEM_CPU) +set(CMAKE_TRY_COMPILE_PLATFORM_VARIABLES CMAKE_SYSTEM_PROCESSOR CMAKE_SYSTEM_CPU) include(${CMAKE_CURRENT_LIST_DIR}/../cpu/${CMAKE_SYSTEM_CPU}.cmake) # ---------------------------------------------------------------------------- diff --git a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake index 2b8cc19e0..616a83fe2 100644 --- a/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake +++ b/hw/bsp/broadcom_32bit/boards/raspberrypi_zero/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR arm1176jzf-s CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU arm1176jzf-s CACHE INTERNAL "System Processor") #set(SUFFIX "") function(update_board TARGET) diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.cmake b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.cmake index 919068f1d..6f1fc0225 100644 --- a/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.cmake +++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_cm4/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-a72 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-a72 CACHE INTERNAL "System Processor") set(BCM_VERSION 2711) function(update_board TARGET) diff --git a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.cmake b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.cmake index 85f84e947..80747363a 100644 --- a/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.cmake +++ b/hw/bsp/broadcom_64bit/boards/raspberrypi_zero2/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-a53 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-a53 CACHE INTERNAL "System Processor") set(BCM_VERSION 2837) function(update_board TARGET) diff --git a/hw/bsp/ch32v10x/family.cmake b/hw/bsp/ch32v10x/family.cmake index c0af0ef44..92acaed80 100644 --- a/hw/bsp/ch32v10x/family.cmake +++ b/hw/bsp/ch32v10x/family.cmake @@ -9,7 +9,7 @@ set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR rv32imac-ilp32 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU rv32imac-ilp32 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake) set(FAMILY_MCUS CH32V103 CACHE INTERNAL "") diff --git a/hw/bsp/ch32v20x/family.cmake b/hw/bsp/ch32v20x/family.cmake index 380ef190d..d4f25f25f 100644 --- a/hw/bsp/ch32v20x/family.cmake +++ b/hw/bsp/ch32v20x/family.cmake @@ -9,7 +9,7 @@ set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR rv32imac-ilp32 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU rv32imac-ilp32 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake) set(FAMILY_MCUS CH32V20X CACHE INTERNAL "") diff --git a/hw/bsp/ch32v307/family.cmake b/hw/bsp/ch32v307/family.cmake index d603af62d..0fd78fa03 100644 --- a/hw/bsp/ch32v307/family.cmake +++ b/hw/bsp/ch32v307/family.cmake @@ -8,7 +8,7 @@ set(SDK_SRC_DIR ${SDK_DIR}/EVT/EXAM/SRC) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR rv32imac-ilp32 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU rv32imac-ilp32 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake) set(FAMILY_MCUS CH32V307 CACHE INTERNAL "") diff --git a/hw/bsp/da1469x/family.cmake b/hw/bsp/da1469x/family.cmake index 8c89141fe..ca6b57635 100644 --- a/hw/bsp/da1469x/family.cmake +++ b/hw/bsp/da1469x/family.cmake @@ -5,7 +5,7 @@ set(MCU_DIR ${TOP}/hw/mcu/dialog/da1469x) # include board specific include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) -set(CMAKE_SYSTEM_PROCESSOR cortex-m33-nodsp CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m33-nodsp CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS DA1469X CACHE INTERNAL "") diff --git a/hw/bsp/f1c100s/family.cmake b/hw/bsp/f1c100s/family.cmake index 032dfb77d..013e61dde 100644 --- a/hw/bsp/f1c100s/family.cmake +++ b/hw/bsp/f1c100s/family.cmake @@ -5,7 +5,7 @@ set(SDK_DIR ${TOP}/hw/mcu/allwinner/f1c100s) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR arm926ej-s CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU arm926ej-s CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS F1C100S CACHE INTERNAL "") diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 3820bb51a..15baf0294 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -73,34 +73,6 @@ if (NOT NO_WARN_RWX_SEGMENTS_SUPPORTED) set(NO_WARN_RWX_SEGMENTS_SUPPORTED 1) endif() -#set(WARNING_FLAGS_GNU -# -Wall -# -Wextra -# -Werror -# -Wfatal-errors -# -Wdouble-promotion -# -Wstrict-prototypes -# -Wstrict-overflow -# -Werror-implicit-function-declaration -# -Wfloat-equal -# -Wundef -# -Wshadow -# -Wwrite-strings -# -Wsign-compare -# -Wmissing-format-attribute -# -Wunreachable-code -# -Wcast-align -# -Wcast-function-type -# -Wcast-qual -# -Wnull-dereference -# -Wuninitialized -# -Wunused -# -Wreturn-type -# -Wredundant-decls -# ) - -set(WARNING_FLAGS_IAR "") - #if (BUILD_ZEPHYR) # set(BOARD_ROOT ${TOP}/hw/bsp/${FAMILY}) # find_package(Zephyr REQUIRED HINTS ${TOP}/lib/zephyr) @@ -182,7 +154,6 @@ endfunction() # Add RTOS to example function(family_add_rtos TARGET RTOS) if (RTOS STREQUAL "freertos") - # freertos config if (NOT TARGET freertos_config) add_library(freertos_config INTERFACE) target_include_directories(freertos_config INTERFACE ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/${FAMILY}/FreeRTOSConfig) @@ -190,12 +161,16 @@ function(family_add_rtos TARGET RTOS) target_link_libraries(freertos_config INTERFACE board_${BOARD}) endif() - # freertos kernel if (NOT TARGET freertos_kernel) add_subdirectory(${TOP}/lib/FreeRTOS-Kernel ${CMAKE_BINARY_DIR}/lib/freertos_kernel) endif () target_link_libraries(${TARGET} PUBLIC freertos_kernel) + target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_FREERTOS) + elseif (RTOS STREQUAL "zephyr") + target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_ZEPHYR) + target_include_directories(${TARGET} PUBLIC ${ZEPHYR_BASE}/include) + target_link_libraries(${TARGET} PUBLIC zephyr_interface kernel) endif () endfunction() @@ -203,6 +178,7 @@ endfunction() function(family_configure_common TARGET RTOS) family_add_rtos(${TARGET} ${RTOS}) + # Add BOARD_${BOARD} define string(TOUPPER ${BOARD} BOARD_UPPER) string(REPLACE "-" "_" BOARD_UPPER ${BOARD_UPPER}) target_compile_definitions(${TARGET} PUBLIC @@ -215,20 +191,6 @@ function(family_configure_common TARGET RTOS) target_compile_options(${TARGET} PUBLIC ${CFLAGS_CLI}) endif() - target_compile_options(${TARGET} PUBLIC ${WARNING_FLAGS_${CMAKE_C_COMPILER_ID}}) - - # Generate linker map file - if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_link_options(${TARGET} PUBLIC "LINKER:-Map=$.map") - if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 AND NO_WARN_RWX_SEGMENTS_SUPPORTED) -# target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") - endif () - elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") - target_link_options(${TARGET} PUBLIC "LINKER:-Map=$.map") - elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") - target_link_options(${TARGET} PUBLIC "LINKER:--map=$.map") - endif() - # ETM Trace option if (TRACE_ETM STREQUAL "1") target_compile_definitions(${TARGET} PUBLIC TRACE_ETM) @@ -248,6 +210,42 @@ function(family_configure_common TARGET RTOS) endif () endif () + if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_compile_options(${TARGET} PRIVATE + -Wall + -Wextra + #-Werror + -Wfatal-errors + -Wdouble-promotion + -Wstrict-prototypes + -Wstrict-overflow + -Werror-implicit-function-declaration + -Wfloat-equal + -Wundef + -Wshadow + -Wwrite-strings + -Wsign-compare + -Wmissing-format-attribute + -Wunreachable-code + -Wcast-align + -Wcast-function-type + -Wcast-qual + -Wnull-dereference + -Wuninitialized + -Wunused + -Wunused-function + -Wreturn-type + -Wredundant-decls + -Wmissing-prototypes + ) + target_link_options(${TARGET} PUBLIC "LINKER:-Map=$.map") + if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 AND NO_WARN_RWX_SEGMENTS_SUPPORTED) + target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") + endif () + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${TARGET} PUBLIC "LINKER:--map=$.map") + endif () + # run size after build # find_program(SIZE_EXE ${CMAKE_SIZE}) # if(NOT ${SIZE_EXE} STREQUAL SIZE_EXE-NOTFOUND) @@ -257,54 +255,32 @@ function(family_configure_common TARGET RTOS) # endif () endfunction() -# Add tinyusb to example +# Add tinyusb to target with RTOS function(family_add_tinyusb TARGET OPT_MCU RTOS) - # tinyusb target is built for each example since it depends on example's tusb_config.h - set(TINYUSB_TARGET_PREFIX ${TARGET}-) - add_library(${TARGET}-tinyusb_config INTERFACE) + # tinyusb's CMakeList.txt + add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) + + # Add TinyUSB sources, include and common define + tinyusb_target_add(${TARGET}) # path to tusb_config.h - target_include_directories(${TARGET}-tinyusb_config INTERFACE ${CMAKE_CURRENT_SOURCE_DIR}/src) - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_MCU=${OPT_MCU}) + target_include_directories(${TARGET} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src) + target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_MCU=${OPT_MCU}) if (DEFINED LOG) - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_DEBUG=${LOG}) - if (LOG STREQUAL "4") - # no inline for debug level 4 - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE TU_ATTR_ALWAYS_INLINE=) + target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_DEBUG=${LOG}) + if (LOG STREQUAL "4") # no inline for debug level 4 + target_compile_definitions(${TARGET} PUBLIC TU_ATTR_ALWAYS_INLINE=) endif () endif() - if (RTOS STREQUAL "freertos") - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_OS=OPT_OS_FREERTOS) - elseif (RTOS STREQUAL "zephyr") - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUSB_OS=OPT_OS_ZEPHYR) - endif () - - # tinyusb's CMakeList.txt - add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) - - if (RTOS STREQUAL "freertos") - # link tinyusb with freeRTOS kernel - target_link_libraries(${TARGET}-tinyusb PUBLIC freertos_kernel) - elseif (RTOS STREQUAL "zephyr") - target_include_directories(${TARGET}-tinyusb PUBLIC ${ZEPHYR_BASE}/include) - endif () - # use max3421 as host controller if (MAX3421_HOST STREQUAL "1") - target_compile_definitions(${TARGET}-tinyusb_config INTERFACE CFG_TUH_MAX3421=1) - target_sources(${TARGET}-tinyusb PUBLIC + target_compile_definitions(${TARGET} PUBLIC CFG_TUH_MAX3421=1) + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/analog/max3421/hcd_max3421.c ) endif () - - # compile define from command line - if(DEFINED CFLAGS_CLI) - separate_arguments(CFLAGS_CLI) - target_compile_options(${TARGET}-tinyusb PUBLIC ${CFLAGS_CLI}) - endif() - endfunction() # Add bin/hex output @@ -330,10 +306,10 @@ function(family_add_uf2 TARGET FAMILY_ID) VERBATIM) endfunction() -#---------------------------------- +#------------------------------------------------------- # Example Target Configure (Default rule) # These function can be redefined in FAMILY/family.cmake -#---------------------------------- +#-------------------------------------------------------- function(family_configure_example TARGET RTOS) # empty function, should be redefined in FAMILY/family.cmake diff --git a/hw/bsp/fomu/family.cmake b/hw/bsp/fomu/family.cmake index 8d5ab144c..132730086 100644 --- a/hw/bsp/fomu/family.cmake +++ b/hw/bsp/fomu/family.cmake @@ -4,7 +4,7 @@ include_guard() include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR rv32i-ilp32 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU rv32i-ilp32 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake) set(FAMILY_MCUS VALENTYUSB_EPTRI CACHE INTERNAL "") diff --git a/hw/bsp/gd32vf103/family.cmake b/hw/bsp/gd32vf103/family.cmake index 5ef551f25..273fea39f 100644 --- a/hw/bsp/gd32vf103/family.cmake +++ b/hw/bsp/gd32vf103/family.cmake @@ -7,7 +7,7 @@ set(SOC_DIR ${SDK_DIR}/SoC/gd32vf103) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR rv32imac-ilp32 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU rv32imac-ilp32 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/riscv_${TOOLCHAIN}.cmake) set(FAMILY_MCUS GD32VF103 CACHE INTERNAL "") diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake index 46a97344f..d5629f8ba 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board.cmake @@ -4,7 +4,7 @@ if (M4 STREQUAL "1") set(MCU_CORE _cm4) set(JLINK_CORE _M4) set(LD_FILE_GNU ${SDK_DIR}/devices/${MCU_VARIANT}/gcc/${MCU_VARIANT}xxxxx${MCU_CORE}_ram.ld) - set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") + set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") else () set(MCU_CORE _cm7) set(JLINK_CORE _M7) diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 27a5f26aa..5a31e42a6 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -8,8 +8,8 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) set(MCU_VARIANT_WITH_CORE ${MCU_VARIANT}${MCU_CORE}) # toolchain set up -if (NOT DEFINED CMAKE_SYSTEM_PROCESSOR) - set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor") +if (NOT DEFINED CMAKE_SYSTEM_CPU) + set(CMAKE_SYSTEM_CPU cortex-m7 CACHE INTERNAL "System Processor") endif () set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) diff --git a/hw/bsp/kinetis_k/family.cmake b/hw/bsp/kinetis_k/family.cmake index c621de388..7fd3f6353 100644 --- a/hw/bsp/kinetis_k/family.cmake +++ b/hw/bsp/kinetis_k/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS KINETIS_K CACHE INTERNAL "") diff --git a/hw/bsp/kinetis_k32l2/family.cmake b/hw/bsp/kinetis_k32l2/family.cmake index e0843b5a4..25710a4c2 100644 --- a/hw/bsp/kinetis_k32l2/family.cmake +++ b/hw/bsp/kinetis_k32l2/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS KINETIS_K32L CACHE INTERNAL "") diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake index 21a264e53..d8d8d3631 100644 --- a/hw/bsp/kinetis_kl/family.cmake +++ b/hw/bsp/kinetis_kl/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS KINETIS_KL CACHE INTERNAL "") diff --git a/hw/bsp/lpc11/family.cmake b/hw/bsp/lpc11/family.cmake index 13ed4c922..a3efecb99 100644 --- a/hw/bsp/lpc11/family.cmake +++ b/hw/bsp/lpc11/family.cmake @@ -11,7 +11,7 @@ else() endif() # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC11UXX CACHE INTERNAL "") diff --git a/hw/bsp/lpc13/family.cmake b/hw/bsp/lpc13/family.cmake index 4d0f0110f..d360048ed 100644 --- a/hw/bsp/lpc13/family.cmake +++ b/hw/bsp/lpc13/family.cmake @@ -8,7 +8,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC13XX CACHE INTERNAL "") diff --git a/hw/bsp/lpc15/family.cmake b/hw/bsp/lpc15/family.cmake index c87001943..5ad12501a 100644 --- a/hw/bsp/lpc15/family.cmake +++ b/hw/bsp/lpc15/family.cmake @@ -8,7 +8,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC15XX CACHE INTERNAL "") diff --git a/hw/bsp/lpc17/family.cmake b/hw/bsp/lpc17/family.cmake index 0f7485f0f..4f2aae19b 100644 --- a/hw/bsp/lpc17/family.cmake +++ b/hw/bsp/lpc17/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC175X_6X CACHE INTERNAL "") diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake index ed948c6e8..70dad48c3 100644 --- a/hw/bsp/lpc18/family.cmake +++ b/hw/bsp/lpc18/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC18XX CACHE INTERNAL "") diff --git a/hw/bsp/lpc40/family.cmake b/hw/bsp/lpc40/family.cmake index f1e8fa50d..0bcdc6037 100644 --- a/hw/bsp/lpc40/family.cmake +++ b/hw/bsp/lpc40/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC40XX CACHE INTERNAL "") diff --git a/hw/bsp/lpc43/family.cmake b/hw/bsp/lpc43/family.cmake index 73842c7e7..9ed937c24 100644 --- a/hw/bsp/lpc43/family.cmake +++ b/hw/bsp/lpc43/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC43XX CACHE INTERNAL "") diff --git a/hw/bsp/lpc51/family.cmake b/hw/bsp/lpc51/family.cmake index bd72c6067..94d6b0bf0 100644 --- a/hw/bsp/lpc51/family.cmake +++ b/hw/bsp/lpc51/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC51 CACHE INTERNAL "") diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake index 0e4994ab1..eb76de6b6 100644 --- a/hw/bsp/lpc54/family.cmake +++ b/hw/bsp/lpc54/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC54 CACHE INTERNAL "") diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake index 367cb3bbd..6a06846c4 100644 --- a/hw/bsp/lpc55/family.cmake +++ b/hw/bsp/lpc55/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS LPC55 CACHE INTERNAL "") diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake index 3545e1c3a..0978bf0dc 100644 --- a/hw/bsp/max32650/family.cmake +++ b/hw/bsp/max32650/family.cmake @@ -11,7 +11,7 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) set(LD_FILE_Clang ${LD_FILE_GNU}) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(JLINK_DEVICE max32650) set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32650.cfg") diff --git a/hw/bsp/max32666/family.cmake b/hw/bsp/max32666/family.cmake index b921b71ce..0ef9bcdcc 100644 --- a/hw/bsp/max32666/family.cmake +++ b/hw/bsp/max32666/family.cmake @@ -12,7 +12,7 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32666.ld) set(LD_FILE_Clang ${LD_FILE_GNU}) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(JLINK_DEVICE max32666) set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32665.cfg") diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake index 9ce8892f1..d5d1bb3ba 100644 --- a/hw/bsp/max32690/family.cmake +++ b/hw/bsp/max32690/family.cmake @@ -12,7 +12,7 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32690.ld) set(LD_FILE_Clang ${LD_FILE_GNU}) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(JLINK_DEVICE max32690) set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32690.cfg") diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake index 4c9bf806b..b836408fc 100644 --- a/hw/bsp/max78002/family.cmake +++ b/hw/bsp/max78002/family.cmake @@ -12,7 +12,7 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max78002.ld) set(LD_FILE_Clang ${LD_FILE_GNU}) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(JLINK_DEVICE max78000) diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake index b1d2a18ec..0a7501ca3 100644 --- a/hw/bsp/mcx/family.cmake +++ b/hw/bsp/mcx/family.cmake @@ -8,10 +8,10 @@ include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up if (MCU_VARIANT STREQUAL "MCXA153") - set(CMAKE_SYSTEM_PROCESSOR cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor") + set(CMAKE_SYSTEM_CPU cortex-m33-nodsp-nofp CACHE INTERNAL "System Processor") set(FAMILY_MCUS MCXA15 CACHE INTERNAL "") elseif (MCU_VARIANT STREQUAL "MCXN947") - set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") + set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") set(FAMILY_MCUS MCXN9 CACHE INTERNAL "") else() message(FATAL_ERROR "MCU_VARIANT not supported") diff --git a/hw/bsp/mm32/family.cmake b/hw/bsp/mm32/family.cmake index 93f297b8e..e0fb0ca93 100644 --- a/hw/bsp/mm32/family.cmake +++ b/hw/bsp/mm32/family.cmake @@ -7,7 +7,7 @@ set(SDK_DIR ${TOP}/hw/mcu/mindmotion/mm32sdk/${MCU_VARIANT_UPPER}) set(CMSIS_5 ${TOP}/lib/CMSIS_5) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS MM32F327X CACHE INTERNAL "") diff --git a/hw/bsp/msp430/family.cmake b/hw/bsp/msp430/family.cmake index e0b4ed28a..64bcb3fd2 100644 --- a/hw/bsp/msp430/family.cmake +++ b/hw/bsp/msp430/family.cmake @@ -6,7 +6,7 @@ set(SDK_DIR ${TOP}/hw/mcu/ti/msp430/msp430-gcc-support-files/include) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR msp430 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU msp430 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/msp430_${TOOLCHAIN}.cmake) set(FAMILY_MCUS MSP430x5xx CACHE INTERNAL "") diff --git a/hw/bsp/msp432e4/family.cmake b/hw/bsp/msp432e4/family.cmake index f06e0d4c9..6a6650e28 100644 --- a/hw/bsp/msp432e4/family.cmake +++ b/hw/bsp/msp432e4/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS MSP432E4 CACHE INTERNAL "") diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 0dfc7579c..30561cdf5 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -111,14 +111,10 @@ endfunction() function(family_configure_example TARGET RTOS) - family_configure_common(${TARGET} ${RTOS}) + # Board target + add_board_target(board_${BOARD}) - if (BUILD_ZEPHYR) - #target_link_libraries(board_${BOARD} PUBLIC zephyr_interface kernel) - elseif () - # Board target - add_board_target(board_${BOARD}) - endif () + family_configure_common(${TARGET} ${RTOS}) #---------- Port Specific ---------- # These files are built for each example since it depends on example's tusb_config.h @@ -136,20 +132,18 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS}) - target_sources(${TARGET}-tinyusb PRIVATE + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c ) - if (BUILD_ZEPHYR) - target_link_libraries(${TARGET}-tinyusb PUBLIC zephyr_interface kernel) - target_link_libraries(${TARGET} PUBLIC ${TARGET}-tinyusb) - elseif () - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) - endif () +# if (BUILD_ZEPHYR) +# target_link_libraries(${TARGET} PUBLIC zephyr_interface kernel) +# elseif () + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) +# endif () # Flashing - #family_add_bin_hex(${TARGET}) +# family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) # family_flash_adafruit_nrfutil(${TARGET}) endfunction() diff --git a/hw/bsp/ra/boards/portenta_c33/board.cmake b/hw/bsp/ra/boards/portenta_c33/board.cmake index 520686daa..a1545f070 100644 --- a/hw/bsp/ra/boards/portenta_c33/board.cmake +++ b/hw/bsp/ra/boards/portenta_c33/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra6m5) set(JLINK_DEVICE R7FA6M5BH) diff --git a/hw/bsp/ra/boards/ra2a1_ek/board.cmake b/hw/bsp/ra/boards/ra2a1_ek/board.cmake index 4d083ca98..9c679c4b5 100644 --- a/hw/bsp/ra/boards/ra2a1_ek/board.cmake +++ b/hw/bsp/ra/boards/ra2a1_ek/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-m23 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m23 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra2a1) set(JLINK_DEVICE R7FA2A1AB) diff --git a/hw/bsp/ra/boards/ra4m1_ek/board.cmake b/hw/bsp/ra/boards/ra4m1_ek/board.cmake index 7bb48bf44..247dea619 100644 --- a/hw/bsp/ra/boards/ra4m1_ek/board.cmake +++ b/hw/bsp/ra/boards/ra4m1_ek/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra4m1) set(JLINK_DEVICE R7FA4M1AB) diff --git a/hw/bsp/ra/boards/ra4m3_ek/board.cmake b/hw/bsp/ra/boards/ra4m3_ek/board.cmake index dfd5fc95a..b413abc36 100644 --- a/hw/bsp/ra/boards/ra4m3_ek/board.cmake +++ b/hw/bsp/ra/boards/ra4m3_ek/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra4m3) set(JLINK_DEVICE R7FA4M3AF) diff --git a/hw/bsp/ra/boards/ra6m1_ek/board.cmake b/hw/bsp/ra/boards/ra6m1_ek/board.cmake index b2f41a354..957e8394d 100644 --- a/hw/bsp/ra/boards/ra6m1_ek/board.cmake +++ b/hw/bsp/ra/boards/ra6m1_ek/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra6m1) set(JLINK_DEVICE R7FA6M1AD) diff --git a/hw/bsp/ra/boards/ra6m5_ek/board.cmake b/hw/bsp/ra/boards/ra6m5_ek/board.cmake index 568d5d78f..bc99845a1 100644 --- a/hw/bsp/ra/boards/ra6m5_ek/board.cmake +++ b/hw/bsp/ra/boards/ra6m5_ek/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra6m5) set(JLINK_DEVICE R7FA6M5BH) diff --git a/hw/bsp/ra/boards/ra8m1_ek/board.cmake b/hw/bsp/ra/boards/ra8m1_ek/board.cmake index 9c797c3b7..c61166f38 100644 --- a/hw/bsp/ra/boards/ra8m1_ek/board.cmake +++ b/hw/bsp/ra/boards/ra8m1_ek/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-m85 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m85 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra8m1) set(JLINK_DEVICE R7FA8M1AH) diff --git a/hw/bsp/ra/boards/uno_r4/board.cmake b/hw/bsp/ra/boards/uno_r4/board.cmake index 3aa6045be..735a93035 100644 --- a/hw/bsp/ra/boards/uno_r4/board.cmake +++ b/hw/bsp/ra/boards/uno_r4/board.cmake @@ -1,4 +1,4 @@ -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(MCU_VARIANT ra4m1) set(JLINK_DEVICE R7FA4M1AB) diff --git a/hw/bsp/samd11/family.cmake b/hw/bsp/samd11/family.cmake index c9ccc86f8..c794d8f37 100644 --- a/hw/bsp/samd11/family.cmake +++ b/hw/bsp/samd11/family.cmake @@ -7,7 +7,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS SAMD11 CACHE INTERNAL "") diff --git a/hw/bsp/samd21/family.cmake b/hw/bsp/samd21/family.cmake index c836b85d9..b946dc4c0 100644 --- a/hw/bsp/samd21/family.cmake +++ b/hw/bsp/samd21/family.cmake @@ -6,7 +6,7 @@ set(SDK_DIR ${TOP}/hw/mcu/microchip/samd21) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS SAMD21 CACHE INTERNAL "") @@ -97,13 +97,10 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_SAMD21 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/microchip/samd/dcd_samd.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) - - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/samd5x_e5x/family.cmake b/hw/bsp/samd5x_e5x/family.cmake index fd95ce10e..1153a5fbd 100644 --- a/hw/bsp/samd5x_e5x/family.cmake +++ b/hw/bsp/samd5x_e5x/family.cmake @@ -6,7 +6,7 @@ set(SDK_DIR ${TOP}/hw/mcu/microchip/${SAM_FAMILY}) set(CMSIS_5 ${TOP}/lib/CMSIS_5) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS SAMD51 SAME54 CACHE INTERNAL "") @@ -94,13 +94,10 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_SAMD51 ${RTOS}) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/microchip/samd/dcd_samd.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) - - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/samg/family.cmake b/hw/bsp/samg/family.cmake index 1cc715ce6..4a1cbd730 100644 --- a/hw/bsp/samg/family.cmake +++ b/hw/bsp/samg/family.cmake @@ -7,7 +7,7 @@ set(SDK_DIR ${TOP}/hw/mcu/microchip/samg55) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS SAMG CACHE INTERNAL "") diff --git a/hw/bsp/saml2x/family.cmake b/hw/bsp/saml2x/family.cmake index 2338d1916..bf6b0e251 100644 --- a/hw/bsp/saml2x/family.cmake +++ b/hw/bsp/saml2x/family.cmake @@ -7,7 +7,7 @@ set(SDK_DIR ${TOP}/hw/mcu/microchip/${SAM_FAMILY}) set(CMSIS_5 ${TOP}/lib/CMSIS_5) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS SAML21 SAML22 CACHE INTERNAL "") diff --git a/hw/bsp/stm32c0/family.cmake b/hw/bsp/stm32c0/family.cmake index 7c5328ab0..dd0fd4074 100644 --- a/hw/bsp/stm32c0/family.cmake +++ b/hw/bsp/stm32c0/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32C0 CACHE INTERNAL "") diff --git a/hw/bsp/stm32f0/family.cmake b/hw/bsp/stm32f0/family.cmake index 8b70411e8..7187d0573 100644 --- a/hw/bsp/stm32f0/family.cmake +++ b/hw/bsp/stm32f0/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32F0 CACHE INTERNAL "") diff --git a/hw/bsp/stm32f1/family.cmake b/hw/bsp/stm32f1/family.cmake index 31801c035..09a93e483 100644 --- a/hw/bsp/stm32f1/family.cmake +++ b/hw/bsp/stm32f1/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32F1 CACHE INTERNAL "") diff --git a/hw/bsp/stm32f2/family.cmake b/hw/bsp/stm32f2/family.cmake index 2bae07b99..7f9839442 100644 --- a/hw/bsp/stm32f2/family.cmake +++ b/hw/bsp/stm32f2/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32F2 CACHE INTERNAL "") diff --git a/hw/bsp/stm32f3/family.cmake b/hw/bsp/stm32f3/family.cmake index 6f4e866f8..50fede817 100644 --- a/hw/bsp/stm32f3/family.cmake +++ b/hw/bsp/stm32f3/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m3 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m3 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32F3 CACHE INTERNAL "") diff --git a/hw/bsp/stm32f4/family.cmake b/hw/bsp/stm32f4/family.cmake index 487f0cf06..10b98b7a6 100644 --- a/hw/bsp/stm32f4/family.cmake +++ b/hw/bsp/stm32f4/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32F4 CACHE INTERNAL "") diff --git a/hw/bsp/stm32f7/family.cmake b/hw/bsp/stm32f7/family.cmake index df1d2a3cf..f7001a2ed 100644 --- a/hw/bsp/stm32f7/family.cmake +++ b/hw/bsp/stm32f7/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m7-fpsp CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m7-fpsp CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32F7 CACHE INTERNAL "") diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake index 7129cebd8..7ac19693c 100644 --- a/hw/bsp/stm32g0/family.cmake +++ b/hw/bsp/stm32g0/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32G0 CACHE INTERNAL "") diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake index 6c4e90d40..e0fca4b30 100644 --- a/hw/bsp/stm32g4/family.cmake +++ b/hw/bsp/stm32g4/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32G4 CACHE INTERNAL "") diff --git a/hw/bsp/stm32h5/family.cmake b/hw/bsp/stm32h5/family.cmake index 804b13768..a2e4c6e8e 100644 --- a/hw/bsp/stm32h5/family.cmake +++ b/hw/bsp/stm32h5/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32H5 CACHE INTERNAL "") diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake index 6af79736d..65f6884da 100644 --- a/hw/bsp/stm32h7/family.cmake +++ b/hw/bsp/stm32h7/family.cmake @@ -12,7 +12,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m7 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m7 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32H7 CACHE INTERNAL "") diff --git a/hw/bsp/stm32l0/family.cmake b/hw/bsp/stm32l0/family.cmake index a2324f123..5f29d254d 100644 --- a/hw/bsp/stm32l0/family.cmake +++ b/hw/bsp/stm32l0/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m0plus CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32L0 CACHE INTERNAL "") diff --git a/hw/bsp/stm32l4/family.cmake b/hw/bsp/stm32l4/family.cmake index 67c5be7d8..6a967de6f 100644 --- a/hw/bsp/stm32l4/family.cmake +++ b/hw/bsp/stm32l4/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32L4 CACHE INTERNAL "") diff --git a/hw/bsp/stm32u5/family.cmake b/hw/bsp/stm32u5/family.cmake index 3be6702fd..0a2ad568d 100644 --- a/hw/bsp/stm32u5/family.cmake +++ b/hw/bsp/stm32u5/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m33 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m33 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32U5 CACHE INTERNAL "") diff --git a/hw/bsp/stm32wb/family.cmake b/hw/bsp/stm32wb/family.cmake index 4f958045d..868b58f71 100644 --- a/hw/bsp/stm32wb/family.cmake +++ b/hw/bsp/stm32wb/family.cmake @@ -11,7 +11,7 @@ set(CMSIS_5 ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS STM32WB CACHE INTERNAL "") diff --git a/hw/bsp/tm4c/family.cmake b/hw/bsp/tm4c/family.cmake index 9c083759b..110bd9f10 100644 --- a/hw/bsp/tm4c/family.cmake +++ b/hw/bsp/tm4c/family.cmake @@ -9,7 +9,7 @@ set(SDK_DIR ${TOP}/hw/mcu/ti/${MCU_VARIANT}xx) set(CMSIS_DIR ${TOP}/lib/CMSIS_5) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS TM4C123 CACHE INTERNAL "") diff --git a/hw/bsp/xmc4000/family.cmake b/hw/bsp/xmc4000/family.cmake index e73f0f216..6266f8f94 100644 --- a/hw/bsp/xmc4000/family.cmake +++ b/hw/bsp/xmc4000/family.cmake @@ -6,7 +6,7 @@ set(CMSIS_DIR ${TOP}/lib/CMSIS_5) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) # toolchain set up -set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_SYSTEM_CPU cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(FAMILY_MCUS XMC4000 CACHE INTERNAL "") diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 1d2f37b2d..bf926fd09 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -1,11 +1,10 @@ # TODO more docs and example on how to use this file -# Usage: requires target tinyusb_config which expose tusb_config.h file # TINYUSB_TARGET_PREFIX and TINYUSB_TARGET_SUFFIX can be used to change the name of the target cmake_minimum_required(VERSION 3.20) -# Add tinyusb to a target, if user don't want to compile tinyusb as a library -function(add_tinyusb TARGET) +# Add tinyusb to a existing target +function(tinyusb_target_add TARGET) target_sources(${TARGET} PRIVATE # common ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/tusb.c @@ -40,68 +39,36 @@ function(add_tinyusb TARGET) # TODO for net driver, should be removed/changed ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../lib/networking ) - - if (CMAKE_C_COMPILER_ID STREQUAL "GNU" OR CMAKE_C_COMPILER_ID STREQUAL "Clang") - target_compile_options(${TARGET} PRIVATE - -Wall - -Wextra - #-Werror - -Wfatal-errors - -Wdouble-promotion - -Wstrict-prototypes - -Wstrict-overflow - -Werror-implicit-function-declaration - -Wfloat-equal - -Wundef - -Wshadow - -Wwrite-strings - -Wsign-compare - -Wmissing-format-attribute - -Wunreachable-code - -Wcast-align - -Wcast-function-type - -Wcast-qual - -Wnull-dereference - -Wuninitialized - -Wunused - -Wunused-function - -Wreturn-type - -Wredundant-decls - -Wmissing-prototypes - ) - elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") - - endif () endfunction() #------------------------------------ # TinyUSB as library target #------------------------------------ -if (NOT DEFINED TINYUSB_TARGET) - set(TINYUSB_TARGET "tinyusb") -endif () - -set(TINYUSB_CONFIG_TARGET "${TINYUSB_TARGET}_config") - -if (DEFINED TINYUSB_TARGET_PREFIX) - set(TINYUSB_TARGET "${TINYUSB_TARGET_PREFIX}${TINYUSB_TARGET}") - set(TINYUSB_CONFIG_TARGET "${TINYUSB_TARGET_PREFIX}${TINYUSB_CONFIG_TARGET}") -endif () - -if (DEFINED TINYUSB_TARGET_SUFFIX) - set(TINYUSB_TARGET "${TINYUSB_TARGET}${TINYUSB_TARGET_SUFFIX}") - set(TINYUSB_CONFIG_TARGET "${TINYUSB_CONFIG_TARGET}${TINYUSB_TARGET_SUFFIX}") -endif () - -add_library(${TINYUSB_TARGET} STATIC) -add_tinyusb(${TINYUSB_TARGET}) - -# Check if tinyusb_config target is defined -if (NOT TARGET ${TINYUSB_CONFIG_TARGET}) - message(FATAL_ERROR "${TINYUSB_CONFIG_TARGET} target is not defined") -endif() - -# Link with tinyusb_config target -target_link_libraries(${TINYUSB_TARGET} PUBLIC - ${TINYUSB_CONFIG_TARGET} - ) +#if (NOT DEFINED TINYUSB_TARGET) +# set(TINYUSB_TARGET "tinyusb") +#endif () +# +#set(TINYUSB_CONFIG_TARGET "${TINYUSB_TARGET}_config") +# +#if (DEFINED TINYUSB_TARGET_PREFIX) +# set(TINYUSB_TARGET "${TINYUSB_TARGET_PREFIX}${TINYUSB_TARGET}") +# set(TINYUSB_CONFIG_TARGET "${TINYUSB_TARGET_PREFIX}${TINYUSB_CONFIG_TARGET}") +#endif () +# +#if (DEFINED TINYUSB_TARGET_SUFFIX) +# set(TINYUSB_TARGET "${TINYUSB_TARGET}${TINYUSB_TARGET_SUFFIX}") +# set(TINYUSB_CONFIG_TARGET "${TINYUSB_CONFIG_TARGET}${TINYUSB_TARGET_SUFFIX}") +#endif () +# +#add_library(${TINYUSB_TARGET} STATIC) +#tinyusb_target_add(${TINYUSB_TARGET}) +# +## Check if tinyusb_config target is defined +#if (NOT TARGET ${TINYUSB_CONFIG_TARGET}) +# message(FATAL_ERROR "${TINYUSB_CONFIG_TARGET} target is not defined") +#endif() +# +## Link with tinyusb_config target +#target_link_libraries(${TINYUSB_TARGET} PUBLIC +# ${TINYUSB_CONFIG_TARGET} +# ) -- cgit v1.3.1 From 31071ccf0e27cc8b77ddb41417665ea82b2b9b35 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 23 Jan 2025 17:10:01 +0700 Subject: kind of work with zephyr with pca10056 with cmake -DBUILD_ZEPHYR --- .idea/cmake.xml | 3 +- .west/config | 2 +- examples/build_system/cmake/toolchain/common.cmake | 4 + examples/device/video_capture/src/main.c | 2 +- examples/host/msc_file_explorer/src/main.c | 6 +- examples/host/msc_file_explorer/src/msc_app.c | 20 +- examples/host/msc_file_explorer/src/msc_app.h | 35 +++ examples/west.yml | 12 - hw/bsp/family_support.cmake | 18 +- hw/bsp/nrf/boards/pca10095/board.cmake | 2 +- hw/bsp/nrf/family.c | 29 +- hw/bsp/nrf/family.cmake | 47 ++-- hw/bsp/nrf/family.mk | 32 +-- hw/bsp/nrf/nrfx_config.h | 46 ---- hw/bsp/nrf/nrfx_config/nrfx_config.h | 46 ++++ hw/bsp/nrf/nrfx_config/nrfx_glue.h | 294 +++++++++++++++++++++ hw/bsp/nrf/nrfx_config/nrfx_log.h | 135 ++++++++++ hw/bsp/nrf/nrfx_glue.h | 294 --------------------- hw/bsp/nrf/nrfx_log.h | 135 ---------- src/portable/nordic/nrf5x/dcd_nrf5x.c | 14 +- 20 files changed, 597 insertions(+), 579 deletions(-) create mode 100644 examples/host/msc_file_explorer/src/msc_app.h delete mode 100644 examples/west.yml delete mode 100644 hw/bsp/nrf/nrfx_config.h create mode 100644 hw/bsp/nrf/nrfx_config/nrfx_config.h create mode 100644 hw/bsp/nrf/nrfx_config/nrfx_glue.h create mode 100644 hw/bsp/nrf/nrfx_config/nrfx_log.h delete mode 100644 hw/bsp/nrf/nrfx_glue.h delete mode 100644 hw/bsp/nrf/nrfx_log.h (limited to 'hw') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index e4c189251..b1a987a24 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -85,7 +85,8 @@ - + + diff --git a/.west/config b/.west/config index 2518007f6..f6f0d7a3d 100644 --- a/.west/config +++ b/.west/config @@ -1,5 +1,5 @@ [manifest] -path = examples +path = lib/zephyr file = west.yml [zephyr] diff --git a/examples/build_system/cmake/toolchain/common.cmake b/examples/build_system/cmake/toolchain/common.cmake index 4c181137b..7fe0aac4b 100644 --- a/examples/build_system/cmake/toolchain/common.cmake +++ b/examples/build_system/cmake/toolchain/common.cmake @@ -1,3 +1,7 @@ +if (BUILD_ZEPHYR) + return() +endif() + include(CMakePrintHelpers) # ---------------------------------------------------------------------------- diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index 8bb924c61..04d4af4e5 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -185,7 +185,7 @@ static void fill_color_bar(uint8_t* buffer, unsigned start_position) { #endif -void video_send_frame(void) { +static void video_send_frame(void) { static unsigned start_ms = 0; static unsigned already_sent = 0; diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c index 9509035b4..8197c3c8d 100644 --- a/examples/host/msc_file_explorer/src/main.c +++ b/examples/host/msc_file_explorer/src/main.c @@ -62,15 +62,13 @@ #include "bsp/board_api.h" #include "tusb.h" +#include "msc_app.h" + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTYPES //--------------------------------------------------------------------+ void led_blinking_task(void); -// from msc_app.c -extern bool msc_app_init(void); -extern void msc_app_task(void); - /*------------- MAIN -------------*/ int main(void) { board_init(); diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c index 035d74689..226c870ea 100644 --- a/examples/host/msc_file_explorer/src/msc_app.c +++ b/examples/host/msc_file_explorer/src/msc_app.c @@ -67,7 +67,9 @@ bool cli_init(void); bool msc_app_init(void) { - for(size_t i=0; i 0 ) @@ -99,8 +103,7 @@ void msc_app_task(void) // //--------------------------------------------------------------------+ -bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) -{ +static bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) { msc_cbw_t const* cbw = cb_data->cbw; msc_csw_t const* csw = cb_data->csw; @@ -294,18 +297,11 @@ void cli_cmd_mkdir(EmbeddedCli *cli, char *args, void *context); void cli_cmd_mv(EmbeddedCli *cli, char *args, void *context); void cli_cmd_rm(EmbeddedCli *cli, char *args, void *context); -void cli_write_char(EmbeddedCli *cli, char c) -{ +static void cli_write_char(EmbeddedCli *cli, char c) { (void) cli; putchar((int) c); } -void cli_cmd_unknown(EmbeddedCli *cli, CliCommand *command) -{ - (void) cli; - printf("%s: command not found\r\n", command->name); -} - bool cli_init(void) { EmbeddedCliConfig *config = embeddedCliDefaultConfig(); diff --git a/examples/host/msc_file_explorer/src/msc_app.h b/examples/host/msc_file_explorer/src/msc_app.h new file mode 100644 index 000000000..3ba03d0dc --- /dev/null +++ b/examples/host/msc_file_explorer/src/msc_app.h @@ -0,0 +1,35 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ +#ifndef MSC_APP_H +#define MSC_APP_H + +#include + +bool msc_app_init(void); +void msc_app_task(void); + + +#endif diff --git a/examples/west.yml b/examples/west.yml deleted file mode 100644 index 4e2160202..000000000 --- a/examples/west.yml +++ /dev/null @@ -1,12 +0,0 @@ -manifest: - remotes: - - name: zephyrproject-rtos - url-base: https://github.com/zephyrproject-rtos - projects: - - name: zephyr - remote: zephyrproject-rtos - revision: v4.0.0 - path: lib/zephyr - import: true - self: - path: . diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 15baf0294..e32bb1689 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -170,7 +170,7 @@ function(family_add_rtos TARGET RTOS) elseif (RTOS STREQUAL "zephyr") target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_ZEPHYR) target_include_directories(${TARGET} PUBLIC ${ZEPHYR_BASE}/include) - target_link_libraries(${TARGET} PUBLIC zephyr_interface kernel) +# target_link_libraries(${TARGET} PUBLIC kernel) endif () endfunction() @@ -201,12 +201,9 @@ function(family_configure_common TARGET RTOS) target_compile_definitions(${TARGET} PUBLIC LOGGER_${LOGGER}) # Add segger rtt to example if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt") - if (NOT TARGET segger_rtt) - add_library(segger_rtt STATIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c) - target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT) -# target_compile_definitions(segger_rtt PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) - endif() - target_link_libraries(${TARGET} PUBLIC segger_rtt) + target_sources(${TARGET} PUBLIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c) + target_include_directories(${TARGET} PUBLIC ${TOP}/lib/SEGGER_RTT/RTT) +# target_compile_definitions(${TARGET} PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) endif () endif () @@ -239,7 +236,8 @@ function(family_configure_common TARGET RTOS) -Wmissing-prototypes ) target_link_options(${TARGET} PUBLIC "LINKER:-Map=$.map") - if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 AND NO_WARN_RWX_SEGMENTS_SUPPORTED) + if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 + AND NO_WARN_RWX_SEGMENTS_SUPPORTED AND (NOT BUILD_ZEPHYR)) target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") endif () elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") @@ -255,7 +253,7 @@ function(family_configure_common TARGET RTOS) # endif () endfunction() -# Add tinyusb to target with RTOS +# Add tinyusb to target (TODO remove RTOS) function(family_add_tinyusb TARGET OPT_MCU RTOS) # tinyusb's CMakeList.txt add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) @@ -364,7 +362,7 @@ function(family_add_default_example_warnings TARGET) if (CMAKE_C_COMPILER_ID STREQUAL "GNU") if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 AND NO_WARN_RWX_SEGMENTS_SUPPORTED) -# target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") + target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") endif() # GCC 10 diff --git a/hw/bsp/nrf/boards/pca10095/board.cmake b/hw/bsp/nrf/boards/pca10095/board.cmake index 95dd30969..6d183dde6 100644 --- a/hw/bsp/nrf/boards/pca10095/board.cmake +++ b/hw/bsp/nrf/boards/pca10095/board.cmake @@ -2,6 +2,6 @@ set(MCU_VARIANT nrf5340_application) function(update_board TARGET) target_sources(${TARGET} PRIVATE - ${NRFX_DIR}/drivers/src/nrfx_usbreg.c + ${NRFX_PATH}/drivers/src/nrfx_usbreg.c ) endfunction() diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index 2c3413b9e..298ca2302 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -44,10 +44,10 @@ #include "nrfx.h" #include "hal/nrf_gpio.h" -#include "drivers/include/nrfx_gpiote.h" -#include "drivers/include/nrfx_power.h" -#include "drivers/include/nrfx_uarte.h" -#include "drivers/include/nrfx_spim.h" +#include "nrfx_gpiote.h" +#include "nrfx_power.h" +#include "nrfx_uarte.h" +#include "nrfx_spim.h" #ifdef SOFTDEVICE_PRESENT #include "nrf_sdm.h" @@ -67,8 +67,6 @@ #define NRFX_VER 3 #endif -extern void nrfx_isr(const void *irq_handler); - //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ @@ -148,12 +146,10 @@ void board_init(void) { // irq_enable(USBREGULATOR_IRQn); #endif - // IRQ_CONNECT(CLOCK_POWER_IRQn, 0, nrfx_isr, nrfx_power_irq_handler, 0); - /* USB device controller access from devicetree */ - // #define DT_DRV_COMPAT nordic_nrf_usbd - // IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), nrfx_isr, nrf_usbd_common_irq_handler, 0); - + #define DT_DRV_COMPAT nordic_nrf_usbd + IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), nrfx_isr, USBD_IRQHandler, 0); + irq_enable(DT_INST_IRQN(0)); #endif // UART @@ -187,7 +183,7 @@ void board_init(void) { }; #endif - nrfx_uarte_init(&_uart_id, &uart_cfg, NULL); //uart_handler); + nrfx_uarte_init(&_uart_id, &uart_cfg, NULL); //------------- USB -------------// #if CFG_TUD_ENABLED @@ -231,8 +227,12 @@ void board_init(void) { #endif } - if ( usb_reg & VBUSDETECT_Msk ) tusb_hal_nrf_power_event(USB_EVT_DETECTED); - if ( usb_reg & OUTPUTRDY_Msk ) tusb_hal_nrf_power_event(USB_EVT_READY); + if ( usb_reg & VBUSDETECT_Msk ) { + tusb_hal_nrf_power_event(USB_EVT_DETECTED); + } + if ( usb_reg & OUTPUTRDY_Msk ) { + tusb_hal_nrf_power_event(USB_EVT_READY); + } #endif #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 @@ -244,7 +244,6 @@ void board_init(void) { //--------------------------------------------------------------------+ // Board porting API //--------------------------------------------------------------------+ - void board_led_write(bool state) { nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); } diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 30561cdf5..1e7a4fe82 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -1,6 +1,6 @@ include_guard() -set(NRFX_DIR ${TOP}/hw/mcu/nordic/nrfx) +set(NRFX_PATH ${TOP}/hw/mcu/nordic/nrfx) set(CMSIS_DIR ${TOP}/lib/CMSIS_5) # include board specific @@ -25,6 +25,10 @@ set(FAMILY_MCUS NRF5X CACHE INTERNAL "") #------------------------------------ # only need to be built ONCE for all examples function(add_board_target BOARD_TARGET) + if (BUILD_ZEPHYR) + return() + endif () + if (TARGET ${BOARD_TARGET}) return() endif () @@ -40,18 +44,18 @@ function(add_board_target BOARD_TARGET) endif () if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID}) - set(STARTUP_FILE_GNU ${NRFX_DIR}/mdk/gcc_startup_${MCU_VARIANT}.S) + set(STARTUP_FILE_GNU ${NRFX_PATH}/mdk/gcc_startup_${MCU_VARIANT}.S) set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) endif () add_library(${BOARD_TARGET} STATIC - ${NRFX_DIR}/helpers/nrfx_flag32_allocator.c - ${NRFX_DIR}/drivers/src/nrfx_gpiote.c - ${NRFX_DIR}/drivers/src/nrfx_power.c - ${NRFX_DIR}/drivers/src/nrfx_spim.c - ${NRFX_DIR}/drivers/src/nrfx_uarte.c - ${NRFX_DIR}/mdk/system_${MCU_VARIANT}.c - ${NRFX_DIR}/soc/nrfx_atomic.c + ${NRFX_PATH}/helpers/nrfx_flag32_allocator.c + ${NRFX_PATH}/drivers/src/nrfx_gpiote.c + ${NRFX_PATH}/drivers/src/nrfx_power.c + ${NRFX_PATH}/drivers/src/nrfx_spim.c + ${NRFX_PATH}/drivers/src/nrfx_uarte.c + ${NRFX_PATH}/mdk/system_${MCU_VARIANT}.c + ${NRFX_PATH}/soc/nrfx_atomic.c ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} ) string(TOUPPER "${MCU_VARIANT_XXAA}" MCU_VARIANT_XXAA_UPPER) @@ -67,12 +71,10 @@ function(add_board_target BOARD_TARGET) endif () target_include_directories(${BOARD_TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${NRFX_DIR} - ${NRFX_DIR}/mdk - ${NRFX_DIR}/hal - ${NRFX_DIR}/drivers/include - ${NRFX_DIR}/drivers/src + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/nrfx_config + ${NRFX_PATH} + ${NRFX_PATH}/mdk + ${NRFX_PATH}/drivers/include ${CMSIS_DIR}/CMSIS/Core/Include ) @@ -81,14 +83,14 @@ function(add_board_target BOARD_TARGET) if (CMAKE_C_COMPILER_ID STREQUAL "GNU") target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" - -L${NRFX_DIR}/mdk + -L${NRFX_PATH}/mdk --specs=nosys.specs --specs=nano.specs -nostartfiles ) elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" - -L${NRFX_DIR}/mdk + -L${NRFX_PATH}/mdk ) elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") target_link_options(${BOARD_TARGET} PUBLIC @@ -113,6 +115,9 @@ endfunction() function(family_configure_example TARGET RTOS) # Board target add_board_target(board_${BOARD}) + if (NOT BUILD_ZEPHYR) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + endif () family_configure_common(${TARGET} ${RTOS}) @@ -132,16 +137,10 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS}) - target_sources(${TARGET} PUBLIC + target_sources(${TARGET} PRIVATE ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c ) -# if (BUILD_ZEPHYR) -# target_link_libraries(${TARGET} PUBLIC zephyr_interface kernel) -# elseif () - target_link_libraries(${TARGET} PUBLIC board_${BOARD}) -# endif () - # Flashing # family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk index b3c05e6db..f5a3f5c45 100644 --- a/hw/bsp/nrf/family.mk +++ b/hw/bsp/nrf/family.mk @@ -1,6 +1,6 @@ UF2_FAMILY_ID = 0xADA52840 -NRFX_DIR = hw/mcu/nordic/nrfx +NRFX_PATH = hw/mcu/nordic/nrfx include $(TOP)/$(BOARD_PATH)/board.mk @@ -28,31 +28,31 @@ CFLAGS_GCC += \ LDFLAGS_GCC += \ -nostartfiles \ --specs=nosys.specs --specs=nano.specs \ - -L$(TOP)/${NRFX_DIR}/mdk + -L$(TOP)/${NRFX_PATH}/mdk LDFLAGS_CLANG += \ - -L$(TOP)/${NRFX_DIR}/mdk \ + -L$(TOP)/${NRFX_PATH}/mdk \ SRC_C += \ src/portable/nordic/nrf5x/dcd_nrf5x.c \ - ${NRFX_DIR}/helpers/nrfx_flag32_allocator.c \ - ${NRFX_DIR}/drivers/src/nrfx_gpiote.c \ - ${NRFX_DIR}/drivers/src/nrfx_power.c \ - ${NRFX_DIR}/drivers/src/nrfx_spim.c \ - ${NRFX_DIR}/drivers/src/nrfx_uarte.c \ - ${NRFX_DIR}/mdk/system_$(MCU_VARIANT).c \ - ${NRFX_DIR}/soc/nrfx_atomic.c + ${NRFX_PATH}/helpers/nrfx_flag32_allocator.c \ + ${NRFX_PATH}/drivers/src/nrfx_gpiote.c \ + ${NRFX_PATH}/drivers/src/nrfx_power.c \ + ${NRFX_PATH}/drivers/src/nrfx_spim.c \ + ${NRFX_PATH}/drivers/src/nrfx_uarte.c \ + ${NRFX_PATH}/mdk/system_$(MCU_VARIANT).c \ + ${NRFX_PATH}/soc/nrfx_atomic.c INC += \ $(TOP)/$(BOARD_PATH) \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ - $(TOP)/${NRFX_DIR} \ - $(TOP)/${NRFX_DIR}/mdk \ - $(TOP)/${NRFX_DIR}/hal \ - $(TOP)/${NRFX_DIR}/drivers/include \ - $(TOP)/${NRFX_DIR}/drivers/src \ + $(TOP)/${NRFX_PATH} \ + $(TOP)/${NRFX_PATH}/mdk \ + $(TOP)/${NRFX_PATH}/hal \ + $(TOP)/${NRFX_PATH}/drivers/include \ + $(TOP)/${NRFX_PATH}/drivers/src \ -SRC_S += ${NRFX_DIR}/mdk/gcc_startup_$(MCU_VARIANT).S +SRC_S += ${NRFX_PATH}/mdk/gcc_startup_$(MCU_VARIANT).S ASFLAGS += -D__HEAP_SIZE=0 diff --git a/hw/bsp/nrf/nrfx_config.h b/hw/bsp/nrf/nrfx_config.h deleted file mode 100644 index fbec4192b..000000000 --- a/hw/bsp/nrf/nrfx_config.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef NRFX_CONFIG_H__ -#define NRFX_CONFIG_H__ - -#define NRFX_POWER_ENABLED 1 -#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7 - -#define NRFX_CLOCK_ENABLED 0 -#define NRFX_GPIOTE_ENABLED 1 -#define NRFX_GPIOTE0_ENABLED 1 - -#define NRFX_UARTE_ENABLED 1 -#define NRFX_UARTE0_ENABLED 1 - -#define NRFX_SPIM_ENABLED 1 -#define NRFX_SPIM1_ENABLED 1 // use SPI1 since nrf5340 share uart with spi - -#define NRFX_PRS_ENABLED 0 -#define NRFX_USBREG_ENABLED 1 - -#if defined(NRF51) -#include -#elif defined(NRF52805_XXAA) -#include -#elif defined(NRF52810_XXAA) -#include -#elif defined(NRF52811_XXAA) -#include -#elif defined(NRF52820_XXAA) -#include -#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) -#include -#elif defined(NRF52833_XXAA) -#include -#elif defined(NRF52840_XXAA) -#include -#elif defined(NRF5340_XXAA_APPLICATION) -#include -#elif defined(NRF5340_XXAA_NETWORK) - #include -#elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA) - #include -#else - #error "Unknown device." -#endif - -#endif // NRFX_CONFIG_H__ diff --git a/hw/bsp/nrf/nrfx_config/nrfx_config.h b/hw/bsp/nrf/nrfx_config/nrfx_config.h new file mode 100644 index 000000000..fbec4192b --- /dev/null +++ b/hw/bsp/nrf/nrfx_config/nrfx_config.h @@ -0,0 +1,46 @@ +#ifndef NRFX_CONFIG_H__ +#define NRFX_CONFIG_H__ + +#define NRFX_POWER_ENABLED 1 +#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7 + +#define NRFX_CLOCK_ENABLED 0 +#define NRFX_GPIOTE_ENABLED 1 +#define NRFX_GPIOTE0_ENABLED 1 + +#define NRFX_UARTE_ENABLED 1 +#define NRFX_UARTE0_ENABLED 1 + +#define NRFX_SPIM_ENABLED 1 +#define NRFX_SPIM1_ENABLED 1 // use SPI1 since nrf5340 share uart with spi + +#define NRFX_PRS_ENABLED 0 +#define NRFX_USBREG_ENABLED 1 + +#if defined(NRF51) +#include +#elif defined(NRF52805_XXAA) +#include +#elif defined(NRF52810_XXAA) +#include +#elif defined(NRF52811_XXAA) +#include +#elif defined(NRF52820_XXAA) +#include +#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) +#include +#elif defined(NRF52833_XXAA) +#include +#elif defined(NRF52840_XXAA) +#include +#elif defined(NRF5340_XXAA_APPLICATION) +#include +#elif defined(NRF5340_XXAA_NETWORK) + #include +#elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA) + #include +#else + #error "Unknown device." +#endif + +#endif // NRFX_CONFIG_H__ diff --git a/hw/bsp/nrf/nrfx_config/nrfx_glue.h b/hw/bsp/nrf/nrfx_config/nrfx_glue.h new file mode 100644 index 000000000..bc3b3689b --- /dev/null +++ b/hw/bsp/nrf/nrfx_config/nrfx_glue.h @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2017 - 2024, Nordic Semiconductor ASA + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_GLUE_H__ +#define NRFX_GLUE_H__ + +// THIS IS A TEMPLATE FILE. +// It should be copied to a suitable location within the host environment into +// which nrfx is integrated, and the following macros should be provided with +// appropriate implementations. +// And this comment should be removed from the customized file. + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_glue nrfx_glue.h + * @{ + * @ingroup nrfx + * + * @brief This file contains macros that should be implemented according to + * the needs of the host environment into which @em nrfx is integrated. + */ + +// Uncomment this line to use the standard MDK way of binding IRQ handlers +// at linking time. +#include + +//------------------------------------------------------------------------------ + +/** + * @brief Macro for placing a runtime assertion. + * + * @param expression Expression to be evaluated. + */ +#define NRFX_ASSERT(expression) + +/** + * @brief Macro for placing a compile time assertion. + * + * @param expression Expression to be evaluated. + */ +#define NRFX_STATIC_ASSERT(expression) + +//------------------------------------------------------------------------------ + +/** + * @brief Macro for setting the priority of a specific IRQ. + * + * @param irq_number IRQ number. + * @param priority Priority to be set. + */ +#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) _NRFX_IRQ_PRIORITY_SET(irq_number, priority) +static inline void _NRFX_IRQ_PRIORITY_SET(IRQn_Type irq_number, + uint8_t priority) +{ + NRFX_ASSERT(INTERRUPT_PRIORITY_IS_VALID(priority)); + NVIC_SetPriority(irq_number, priority); +} + +/** + * @brief Macro for enabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_ENABLE(irq_number) _NRFX_IRQ_ENABLE(irq_number) +static inline void _NRFX_IRQ_ENABLE(IRQn_Type irq_number) +{ + NVIC_ClearPendingIRQ(irq_number); + NVIC_EnableIRQ(irq_number); +} + +/** + * @brief Macro for checking if a specific IRQ is enabled. + * + * @param irq_number IRQ number. + * + * @retval true If the IRQ is enabled. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_ENABLED(irq_number) _NRFX_IRQ_IS_ENABLED(irq_number) +static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number) +{ + return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32))); +} + +/** + * @brief Macro for disabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_DISABLE(irq_number) _NRFX_IRQ_DISABLE(irq_number) +static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number) +{ + NVIC_DisableIRQ(irq_number); +} + +/** + * @brief Macro for setting a specific IRQ as pending. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_SET(irq_number) _NRFX_IRQ_PENDING_SET(irq_number) +static inline void _NRFX_IRQ_PENDING_SET(IRQn_Type irq_number) +{ + NVIC_SetPendingIRQ(irq_number); +} + +/** + * @brief Macro for clearing the pending status of a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_CLEAR(irq_number) _NRFX_IRQ_PENDING_CLEAR(irq_number) +static inline void _NRFX_IRQ_PENDING_CLEAR(IRQn_Type irq_number) +{ + NVIC_ClearPendingIRQ(irq_number); +} + +/** + * @brief Macro for checking the pending status of a specific IRQ. + * + * @retval true If the IRQ is pending. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_PENDING(irq_number) _NRFX_IRQ_IS_PENDING(irq_number) +static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number) +{ + return (NVIC_GetPendingIRQ(irq_number) == 1); +} + +/** @brief Macro for entering into a critical section. */ +#define NRFX_CRITICAL_SECTION_ENTER() + +/** @brief Macro for exiting from a critical section. */ +#define NRFX_CRITICAL_SECTION_EXIT() + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that + * @ref nrfx_coredep_delay_us uses a precise DWT-based solution. + * A compilation error is generated if the DWT unit is not present + * in the SoC used. + */ +#define NRFX_DELAY_DWT_BASED 0 + +/** + * @brief Macro for delaying the code execution for at least the specified time. + * + * @param us_time Number of microseconds to wait. + */ +#include +#define NRFX_DELAY_US(us_time) nrfx_coredep_delay_us(us_time) + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that the + * @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined + * in a customized way and the default definitions from @c + * should not be used. + */ +#define NRFX_CUSTOM_ERROR_CODES 0 + +//------------------------------------------------------------------------------ + +/** + * @brief Bitmask defining PPI channels reserved to be used outside of nrfx. + */ +#define NRFX_PPI_CHANNELS_USED 0 + +/** + * @brief Bitmask defining PPI groups reserved to be used outside of nrfx. + */ +#define NRFX_PPI_GROUPS_USED 0 + +/** + * @brief Bitmask defining SWI instances reserved to be used outside of nrfx. + */ +#define NRFX_SWI_USED 0 + +/** + * @brief Bitmask defining TIMER instances reserved to be used outside of nrfx. + */ +#define NRFX_TIMERS_USED 0 + +/** @} */ + +//------------------------------------------------------------------------------ + +#include + +/** + * @brief Atomic 32 bit unsigned type. + */ +#define nrfx_atomic_t nrfx_atomic_u32_t + +/** + * @brief Stores value to an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value to store. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_STORE(p_data, value) nrfx_atomic_u32_fetch_store(p_data, value) + +/** + * @brief Performs logical OR operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of OR operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_OR(p_data, value) nrfx_atomic_u32_fetch_or(p_data, value) + +/** + * @brief Performs logical AND operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of AND operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_AND(p_data, value) nrfx_atomic_u32_fetch_and(p_data, value) + +/** + * @brief Performs logical XOR operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of XOR operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_XOR(p_data, value) nrfx_atomic_u32_fetch_xor(p_data, value) + +/** + * @brief Performs logical ADD operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of ADD operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_ADD(p_data, value) nrfx_atomic_u32_fetch_add(p_data, value) + +/** + * @brief Performs logical SUB operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of SUB operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_SUB(p_data, value) nrfx_atomic_u32_fetch_sub(p_data, value) + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_GLUE_H__ diff --git a/hw/bsp/nrf/nrfx_config/nrfx_log.h b/hw/bsp/nrf/nrfx_config/nrfx_log.h new file mode 100644 index 000000000..3bc1b424e --- /dev/null +++ b/hw/bsp/nrf/nrfx_config/nrfx_log.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_LOG_H__ +#define NRFX_LOG_H__ + +// THIS IS A TEMPLATE FILE. +// It should be copied to a suitable location within the host environment into +// which nrfx is integrated, and the following macros should be provided with +// appropriate implementations. +// And this comment should be removed from the customized file. + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_log nrfx_log.h + * @{ + * @ingroup nrfx + * + * @brief This file contains macros that should be implemented according to + * the needs of the host environment into which @em nrfx is integrated. + */ + +/** + * @brief Macro for logging a message with the severity level ERROR. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_ERROR(format, ...) + +/** + * @brief Macro for logging a message with the severity level WARNING. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_WARNING(format, ...) + +/** + * @brief Macro for logging a message with the severity level INFO. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_INFO(format, ...) + +/** + * @brief Macro for logging a message with the severity level DEBUG. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_DEBUG(format, ...) + + +/** + * @brief Macro for logging a memory dump with the severity level ERROR. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level WARNING. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level INFO. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_INFO(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level DEBUG. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length) + + +/** + * @brief Macro for getting the textual representation of a given error code. + * + * @param[in] error_code Error code. + * + * @return String containing the textual representation of the error code. + */ +#define NRFX_LOG_ERROR_STRING_GET(error_code) + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_LOG_H__ diff --git a/hw/bsp/nrf/nrfx_glue.h b/hw/bsp/nrf/nrfx_glue.h deleted file mode 100644 index bc3b3689b..000000000 --- a/hw/bsp/nrf/nrfx_glue.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Copyright (c) 2017 - 2024, Nordic Semiconductor ASA - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef NRFX_GLUE_H__ -#define NRFX_GLUE_H__ - -// THIS IS A TEMPLATE FILE. -// It should be copied to a suitable location within the host environment into -// which nrfx is integrated, and the following macros should be provided with -// appropriate implementations. -// And this comment should be removed from the customized file. - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_glue nrfx_glue.h - * @{ - * @ingroup nrfx - * - * @brief This file contains macros that should be implemented according to - * the needs of the host environment into which @em nrfx is integrated. - */ - -// Uncomment this line to use the standard MDK way of binding IRQ handlers -// at linking time. -#include - -//------------------------------------------------------------------------------ - -/** - * @brief Macro for placing a runtime assertion. - * - * @param expression Expression to be evaluated. - */ -#define NRFX_ASSERT(expression) - -/** - * @brief Macro for placing a compile time assertion. - * - * @param expression Expression to be evaluated. - */ -#define NRFX_STATIC_ASSERT(expression) - -//------------------------------------------------------------------------------ - -/** - * @brief Macro for setting the priority of a specific IRQ. - * - * @param irq_number IRQ number. - * @param priority Priority to be set. - */ -#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) _NRFX_IRQ_PRIORITY_SET(irq_number, priority) -static inline void _NRFX_IRQ_PRIORITY_SET(IRQn_Type irq_number, - uint8_t priority) -{ - NRFX_ASSERT(INTERRUPT_PRIORITY_IS_VALID(priority)); - NVIC_SetPriority(irq_number, priority); -} - -/** - * @brief Macro for enabling a specific IRQ. - * - * @param irq_number IRQ number. - */ -#define NRFX_IRQ_ENABLE(irq_number) _NRFX_IRQ_ENABLE(irq_number) -static inline void _NRFX_IRQ_ENABLE(IRQn_Type irq_number) -{ - NVIC_ClearPendingIRQ(irq_number); - NVIC_EnableIRQ(irq_number); -} - -/** - * @brief Macro for checking if a specific IRQ is enabled. - * - * @param irq_number IRQ number. - * - * @retval true If the IRQ is enabled. - * @retval false Otherwise. - */ -#define NRFX_IRQ_IS_ENABLED(irq_number) _NRFX_IRQ_IS_ENABLED(irq_number) -static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number) -{ - return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32))); -} - -/** - * @brief Macro for disabling a specific IRQ. - * - * @param irq_number IRQ number. - */ -#define NRFX_IRQ_DISABLE(irq_number) _NRFX_IRQ_DISABLE(irq_number) -static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number) -{ - NVIC_DisableIRQ(irq_number); -} - -/** - * @brief Macro for setting a specific IRQ as pending. - * - * @param irq_number IRQ number. - */ -#define NRFX_IRQ_PENDING_SET(irq_number) _NRFX_IRQ_PENDING_SET(irq_number) -static inline void _NRFX_IRQ_PENDING_SET(IRQn_Type irq_number) -{ - NVIC_SetPendingIRQ(irq_number); -} - -/** - * @brief Macro for clearing the pending status of a specific IRQ. - * - * @param irq_number IRQ number. - */ -#define NRFX_IRQ_PENDING_CLEAR(irq_number) _NRFX_IRQ_PENDING_CLEAR(irq_number) -static inline void _NRFX_IRQ_PENDING_CLEAR(IRQn_Type irq_number) -{ - NVIC_ClearPendingIRQ(irq_number); -} - -/** - * @brief Macro for checking the pending status of a specific IRQ. - * - * @retval true If the IRQ is pending. - * @retval false Otherwise. - */ -#define NRFX_IRQ_IS_PENDING(irq_number) _NRFX_IRQ_IS_PENDING(irq_number) -static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number) -{ - return (NVIC_GetPendingIRQ(irq_number) == 1); -} - -/** @brief Macro for entering into a critical section. */ -#define NRFX_CRITICAL_SECTION_ENTER() - -/** @brief Macro for exiting from a critical section. */ -#define NRFX_CRITICAL_SECTION_EXIT() - -//------------------------------------------------------------------------------ - -/** - * @brief When set to a non-zero value, this macro specifies that - * @ref nrfx_coredep_delay_us uses a precise DWT-based solution. - * A compilation error is generated if the DWT unit is not present - * in the SoC used. - */ -#define NRFX_DELAY_DWT_BASED 0 - -/** - * @brief Macro for delaying the code execution for at least the specified time. - * - * @param us_time Number of microseconds to wait. - */ -#include -#define NRFX_DELAY_US(us_time) nrfx_coredep_delay_us(us_time) - -//------------------------------------------------------------------------------ - -/** - * @brief When set to a non-zero value, this macro specifies that the - * @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined - * in a customized way and the default definitions from @c - * should not be used. - */ -#define NRFX_CUSTOM_ERROR_CODES 0 - -//------------------------------------------------------------------------------ - -/** - * @brief Bitmask defining PPI channels reserved to be used outside of nrfx. - */ -#define NRFX_PPI_CHANNELS_USED 0 - -/** - * @brief Bitmask defining PPI groups reserved to be used outside of nrfx. - */ -#define NRFX_PPI_GROUPS_USED 0 - -/** - * @brief Bitmask defining SWI instances reserved to be used outside of nrfx. - */ -#define NRFX_SWI_USED 0 - -/** - * @brief Bitmask defining TIMER instances reserved to be used outside of nrfx. - */ -#define NRFX_TIMERS_USED 0 - -/** @} */ - -//------------------------------------------------------------------------------ - -#include - -/** - * @brief Atomic 32 bit unsigned type. - */ -#define nrfx_atomic_t nrfx_atomic_u32_t - -/** - * @brief Stores value to an atomic object and returns previously stored value. - * - * @param[in] p_data Atomic memory pointer. - * @param[in] value Value to store. - * - * @return Old value stored into atomic object. - */ -#define NRFX_ATOMIC_FETCH_STORE(p_data, value) nrfx_atomic_u32_fetch_store(p_data, value) - -/** - * @brief Performs logical OR operation on an atomic object and returns previously stored value. - * - * @param[in] p_data Atomic memory pointer. - * @param[in] value Value of second operand of OR operation. - * - * @return Old value stored into atomic object. - */ -#define NRFX_ATOMIC_FETCH_OR(p_data, value) nrfx_atomic_u32_fetch_or(p_data, value) - -/** - * @brief Performs logical AND operation on an atomic object and returns previously stored value. - * - * @param[in] p_data Atomic memory pointer. - * @param[in] value Value of second operand of AND operation. - * - * @return Old value stored into atomic object. - */ -#define NRFX_ATOMIC_FETCH_AND(p_data, value) nrfx_atomic_u32_fetch_and(p_data, value) - -/** - * @brief Performs logical XOR operation on an atomic object and returns previously stored value. - * - * @param[in] p_data Atomic memory pointer. - * @param[in] value Value of second operand of XOR operation. - * - * @return Old value stored into atomic object. - */ -#define NRFX_ATOMIC_FETCH_XOR(p_data, value) nrfx_atomic_u32_fetch_xor(p_data, value) - -/** - * @brief Performs logical ADD operation on an atomic object and returns previously stored value. - * - * @param[in] p_data Atomic memory pointer. - * @param[in] value Value of second operand of ADD operation. - * - * @return Old value stored into atomic object. - */ -#define NRFX_ATOMIC_FETCH_ADD(p_data, value) nrfx_atomic_u32_fetch_add(p_data, value) - -/** - * @brief Performs logical SUB operation on an atomic object and returns previously stored value. - * - * @param[in] p_data Atomic memory pointer. - * @param[in] value Value of second operand of SUB operation. - * - * @return Old value stored into atomic object. - */ -#define NRFX_ATOMIC_FETCH_SUB(p_data, value) nrfx_atomic_u32_fetch_sub(p_data, value) - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_GLUE_H__ diff --git a/hw/bsp/nrf/nrfx_log.h b/hw/bsp/nrf/nrfx_log.h deleted file mode 100644 index 3bc1b424e..000000000 --- a/hw/bsp/nrf/nrfx_log.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef NRFX_LOG_H__ -#define NRFX_LOG_H__ - -// THIS IS A TEMPLATE FILE. -// It should be copied to a suitable location within the host environment into -// which nrfx is integrated, and the following macros should be provided with -// appropriate implementations. -// And this comment should be removed from the customized file. - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_log nrfx_log.h - * @{ - * @ingroup nrfx - * - * @brief This file contains macros that should be implemented according to - * the needs of the host environment into which @em nrfx is integrated. - */ - -/** - * @brief Macro for logging a message with the severity level ERROR. - * - * @param format printf-style format string, optionally followed by arguments - * to be formatted and inserted in the resulting string. - */ -#define NRFX_LOG_ERROR(format, ...) - -/** - * @brief Macro for logging a message with the severity level WARNING. - * - * @param format printf-style format string, optionally followed by arguments - * to be formatted and inserted in the resulting string. - */ -#define NRFX_LOG_WARNING(format, ...) - -/** - * @brief Macro for logging a message with the severity level INFO. - * - * @param format printf-style format string, optionally followed by arguments - * to be formatted and inserted in the resulting string. - */ -#define NRFX_LOG_INFO(format, ...) - -/** - * @brief Macro for logging a message with the severity level DEBUG. - * - * @param format printf-style format string, optionally followed by arguments - * to be formatted and inserted in the resulting string. - */ -#define NRFX_LOG_DEBUG(format, ...) - - -/** - * @brief Macro for logging a memory dump with the severity level ERROR. - * - * @param[in] p_memory Pointer to the memory region to be dumped. - * @param[in] length Length of the memory region in bytes. - */ -#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length) - -/** - * @brief Macro for logging a memory dump with the severity level WARNING. - * - * @param[in] p_memory Pointer to the memory region to be dumped. - * @param[in] length Length of the memory region in bytes. - */ -#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length) - -/** - * @brief Macro for logging a memory dump with the severity level INFO. - * - * @param[in] p_memory Pointer to the memory region to be dumped. - * @param[in] length Length of the memory region in bytes. - */ -#define NRFX_LOG_HEXDUMP_INFO(p_memory, length) - -/** - * @brief Macro for logging a memory dump with the severity level DEBUG. - * - * @param[in] p_memory Pointer to the memory region to be dumped. - * @param[in] length Length of the memory region in bytes. - */ -#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length) - - -/** - * @brief Macro for getting the textual representation of a given error code. - * - * @param[in] error_code Error code. - * - * @return String containing the textual representation of the error code. - */ -#define NRFX_LOG_ERROR_STRING_GET(error_code) - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_LOG_H__ diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index 5bfedae17..9e5f5117f 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -39,8 +39,8 @@ #endif #include "nrf.h" -#include "nrf_clock.h" -#include "nrfx_usbd_errata.h" +#include "nrfx_clock.h" +#include "nrf_erratas.h" #ifdef __GNUC__ #pragma GCC diagnostic pop @@ -926,7 +926,7 @@ void tusb_hal_nrf_power_event(uint32_t event) { #ifdef NRF52_SERIES // NRF53 does not need this errata // ERRATA 171, 187, 166 - if (nrfx_usbd_errata_187()) { + if (nrf52_errata_187()) { // CRITICAL_REGION_ENTER(); if (*((volatile uint32_t*) (0x4006EC00)) == 0x00000000) { *((volatile uint32_t*) (0x4006EC00)) = 0x00009375; @@ -938,7 +938,7 @@ void tusb_hal_nrf_power_event(uint32_t event) { // CRITICAL_REGION_EXIT(); } - if (nrfx_usbd_errata_171()) { + if (nrf52_errata_171()) { // CRITICAL_REGION_ENTER(); if (*((volatile uint32_t*) (0x4006EC00)) == 0x00000000) { *((volatile uint32_t*) (0x4006EC00)) = 0x00009375; @@ -974,7 +974,7 @@ void tusb_hal_nrf_power_event(uint32_t event) { __DSB(); // for sync #ifdef NRF52_SERIES - if (nrfx_usbd_errata_171()) { + if (nrf52_errata_171()) { // CRITICAL_REGION_ENTER(); if (*((volatile uint32_t*) (0x4006EC00)) == 0x00000000) { *((volatile uint32_t*) (0x4006EC00)) = 0x00009375; @@ -987,7 +987,7 @@ void tusb_hal_nrf_power_event(uint32_t event) { // CRITICAL_REGION_EXIT(); } - if (nrfx_usbd_errata_187()) { + if (nrf52_errata_187()) { // CRITICAL_REGION_ENTER(); if (*((volatile uint32_t*) (0x4006EC00)) == 0x00000000) { *((volatile uint32_t*) (0x4006EC00)) = 0x00009375; @@ -999,7 +999,7 @@ void tusb_hal_nrf_power_event(uint32_t event) { // CRITICAL_REGION_EXIT(); } - if (nrfx_usbd_errata_166()) { + if (nrf52_errata_166()) { *((volatile uint32_t*) (NRF_USBD_BASE + 0x800)) = 0x7E3; *((volatile uint32_t*) (NRF_USBD_BASE + 0x804)) = 0x40; -- cgit v1.3.1 From 0162d6ab326cb1903e62664b0e18913dbf8ed823 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 23 Jan 2025 17:26:32 +0700 Subject: kind of work with zephyr with pca10056 with cmake -DBUILD_ZEPHYR --- .west/config | 2 +- examples/device/cdc_msc/prj.conf | 6 ++++++ examples/west.yml | 12 ++++++++++++ hw/bsp/nrf/boards/pca10056/board_aliases.cmake | 1 + 4 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 examples/device/cdc_msc/prj.conf create mode 100644 examples/west.yml create mode 100644 hw/bsp/nrf/boards/pca10056/board_aliases.cmake (limited to 'hw') diff --git a/.west/config b/.west/config index f6f0d7a3d..2518007f6 100644 --- a/.west/config +++ b/.west/config @@ -1,5 +1,5 @@ [manifest] -path = lib/zephyr +path = examples file = west.yml [zephyr] diff --git a/examples/device/cdc_msc/prj.conf b/examples/device/cdc_msc/prj.conf new file mode 100644 index 000000000..2f5139d9d --- /dev/null +++ b/examples/device/cdc_msc/prj.conf @@ -0,0 +1,6 @@ +CONFIG_GPIO=y +CONFIG_FPU=y +CONFIG_NO_OPTIMIZATIONS=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_NRFX_POWER=y +CONFIG_NRFX_UARTE0=y diff --git a/examples/west.yml b/examples/west.yml new file mode 100644 index 000000000..383815c45 --- /dev/null +++ b/examples/west.yml @@ -0,0 +1,12 @@ +manifest: + remotes: + - name: zephyrproject-rtos + url-base: https://github.com/zephyrproject-rtos + projects: + - name: zephyr + remote: zephyrproject-rtos + revision: main + path: lib/zephyr + import: true + self: + path: . diff --git a/hw/bsp/nrf/boards/pca10056/board_aliases.cmake b/hw/bsp/nrf/boards/pca10056/board_aliases.cmake new file mode 100644 index 000000000..91ffc3a39 --- /dev/null +++ b/hw/bsp/nrf/boards/pca10056/board_aliases.cmake @@ -0,0 +1 @@ +set(pca10056_BOARD_ALIAS nrf52840dk/nrf52840) -- cgit v1.3.1 From 9f45e25b1c322202084d80f1fd88567fe0b0a3e2 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 24 Jan 2025 00:39:48 +0700 Subject: msc_dual_lun and cdc_msc work with zephyr on pca10056 --- examples/device/cdc_msc/CMakeLists.txt | 5 ----- examples/device/msc_dual_lun/CMakeLists.txt | 17 +++++++++++---- hw/bsp/family_support.cmake | 32 +++++++++++++++-------------- 3 files changed, 30 insertions(+), 24 deletions(-) (limited to 'hw') diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt index 754c5deb0..1c00ae0b2 100644 --- a/examples/device/cdc_msc/CMakeLists.txt +++ b/examples/device/cdc_msc/CMakeLists.txt @@ -6,11 +6,6 @@ include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) # gets PROJECT name for the example (e.g. -) family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR}) -if (BUILD_ZEPHYR) - set(BOARD_ROOT ${TOP}/hw/bsp/${FAMILY}) - find_package(Zephyr REQUIRED HINTS ${TOP}/lib/zephyr) -endif () - project(${PROJECT} C CXX ASM) # Checks this example is valid for the family and initializes the project diff --git a/examples/device/msc_dual_lun/CMakeLists.txt b/examples/device/msc_dual_lun/CMakeLists.txt index 58a7bd30b..8c39168e8 100644 --- a/examples/device/msc_dual_lun/CMakeLists.txt +++ b/examples/device/msc_dual_lun/CMakeLists.txt @@ -15,20 +15,29 @@ if(FAMILY STREQUAL "espressif") return() endif() -add_executable(${PROJECT}) +if (BUILD_ZEPHYR) + set(EXE_NAME app) +else() + set(EXE_NAME ${PROJECT}) + add_executable(${EXE_NAME}) +endif() # Example source -target_sources(${PROJECT} PUBLIC +target_sources(${EXE_NAME} PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/src/main.c ${CMAKE_CURRENT_SOURCE_DIR}/src/msc_disk_dual.c ${CMAKE_CURRENT_SOURCE_DIR}/src/usb_descriptors.c ) # Example include -target_include_directories(${PROJECT} PUBLIC +target_include_directories(${EXE_NAME} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src ) # Configure compilation flags and libraries for the example without RTOS. # See the corresponding function in hw/bsp/FAMILY/family.cmake for details. -family_configure_device_example(${PROJECT} noos) +if (BUILD_ZEPHYR) + family_configure_device_example(${EXE_NAME} zephyr) +else() + family_configure_device_example(${EXE_NAME} noos) +endif() diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index e32bb1689..6ba7cb1c7 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -73,10 +73,10 @@ if (NOT NO_WARN_RWX_SEGMENTS_SUPPORTED) set(NO_WARN_RWX_SEGMENTS_SUPPORTED 1) endif() -#if (BUILD_ZEPHYR) -# set(BOARD_ROOT ${TOP}/hw/bsp/${FAMILY}) -# find_package(Zephyr REQUIRED HINTS ${TOP}/lib/zephyr) -#endif () +if (BUILD_ZEPHYR) + set(BOARD_ROOT ${TOP}/hw/bsp/${FAMILY}) + find_package(Zephyr REQUIRED HINTS ${TOP}/lib/zephyr) +endif () #------------------------------------------------------------- # Functions @@ -401,26 +401,28 @@ function(family_flash_jlink TARGET) endif () separate_arguments(OPTION_LIST UNIX_COMMAND ${JLINK_OPTION}) + if (BUILD_ZEPHYR) + set(BINARY_TARGET zephyr_final) + set(NAME_TARGET ${CMAKE_PROJECT_NAME}) + else () + set(BINARY_TARGET ${TARGET}) + set(NAME_TARGET ${TARGET}) + endif () + file(GENERATE - OUTPUT $/${TARGET}.jlink + OUTPUT $/${BINARY_TARGET}.jlink CONTENT "halt -loadfile $ +loadfile $ r go exit" ) - add_custom_target(${TARGET}-jlink - DEPENDS ${TARGET} - COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} ${OPTION_LIST} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $/${TARGET}.jlink + add_custom_target(${NAME_TARGET}-jlink + DEPENDS ${BINARY_TARGET} + COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} ${OPTION_LIST} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $/${BINARY_TARGET}.jlink VERBATIM ) - - # optional flash post build -# add_custom_command(TARGET ${TARGET} POST_BUILD -# COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} ${OPTION_LIST} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $/${TARGET}.jlink -# VERBATIM -# ) endfunction() -- cgit v1.3.1 From 5ca38228308271dda7fdcdeb085de9bb4d6d8f6a Mon Sep 17 00:00:00 2001 From: hohoho Date: Thu, 23 Jan 2025 19:56:57 +0100 Subject: stm32: fix conditional compilation error when not using uart --- hw/bsp/stm32g0/family.c | 7 ++++--- hw/bsp/stm32g4/family.c | 7 ++++--- hw/bsp/stm32h5/family.c | 7 ++++--- hw/bsp/stm32wb/family.c | 8 +++++--- 4 files changed, 17 insertions(+), 12 deletions(-) (limited to 'hw') diff --git a/hw/bsp/stm32g0/family.c b/hw/bsp/stm32g0/family.c index 86f2af12e..67b0b3f1c 100644 --- a/hw/bsp/stm32g0/family.c +++ b/hw/bsp/stm32g0/family.c @@ -43,7 +43,9 @@ void USB_UCPD1_2_IRQHandler(void) { //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ +#ifdef UART_DEV UART_HandleTypeDef UartHandle; +#endif void board_init(void) { HAL_Init(); // required for HAL_RCC_Osc TODO check with freeRTOS @@ -59,8 +61,6 @@ void board_init(void) { __HAL_RCC_SYSCFG_CLK_ENABLE(); __HAL_RCC_PWR_CLK_ENABLE(); - UART_CLK_EN(); - #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); @@ -91,6 +91,8 @@ void board_init(void) { HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); #ifdef UART_DEV + UART_CLK_EN(); + // UART GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -167,7 +169,6 @@ int board_uart_write(void const *buf, int len) { #else (void) buf; (void) len; - (void) UartHandle; return 0; #endif } diff --git a/hw/bsp/stm32g4/family.c b/hw/bsp/stm32g4/family.c index d0ef7e503..49ef86db9 100644 --- a/hw/bsp/stm32g4/family.c +++ b/hw/bsp/stm32g4/family.c @@ -57,7 +57,9 @@ void UCPD1_IRQHandler(void) { //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ +#ifdef UART_DEV UART_HandleTypeDef UartHandle; +#endif void board_init(void) { HAL_Init(); @@ -71,8 +73,6 @@ void board_init(void) { __HAL_RCC_GPIOE_CLK_ENABLE(); __HAL_RCC_GPIOG_CLK_ENABLE(); - UART_CLK_EN(); - #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); @@ -107,6 +107,8 @@ void board_init(void) { HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); #ifdef UART_DEV + UART_CLK_EN(); + // UART memset(&GPIO_InitStruct, 0, sizeof(GPIO_InitStruct)); GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; @@ -197,7 +199,6 @@ int board_uart_write(void const *buf, int len) { #else (void) buf; (void) len; - (void) UartHandle; return 0; #endif } diff --git a/hw/bsp/stm32h5/family.c b/hw/bsp/stm32h5/family.c index efc5bb7b1..26ba34ac3 100644 --- a/hw/bsp/stm32h5/family.c +++ b/hw/bsp/stm32h5/family.c @@ -58,7 +58,9 @@ void USB_DRD_FS_IRQHandler(void) { //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ +#ifdef UART_DEV UART_HandleTypeDef UartHandle; +#endif void board_init(void) { HAL_Init(); // required for HAL_RCC_Osc TODO check with freeRTOS @@ -82,8 +84,6 @@ void board_init(void) { __HAL_RCC_GPIOI_CLK_ENABLE(); #endif - UART_CLK_EN(); - #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); @@ -114,6 +114,8 @@ void board_init(void) { HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); #ifdef UART_DEV + UART_CLK_EN(); + // UART GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -192,7 +194,6 @@ int board_uart_write(void const* buf, int len) { #else (void) buf; (void) len; - (void) UartHandle; return 0; #endif } diff --git a/hw/bsp/stm32wb/family.c b/hw/bsp/stm32wb/family.c index 43e1345c8..ba37b7cc3 100644 --- a/hw/bsp/stm32wb/family.c +++ b/hw/bsp/stm32wb/family.c @@ -46,7 +46,9 @@ void USB_LP_IRQHandler(void) { //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ +#ifdef UART_DEV UART_HandleTypeDef UartHandle; +#endif void board_init(void) { board_clock_init(); @@ -58,8 +60,6 @@ void board_init(void) { __HAL_RCC_GPIOD_CLK_ENABLE(); __HAL_RCC_GPIOE_CLK_ENABLE(); - UART_CLK_EN(); - #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); @@ -102,6 +102,8 @@ void board_init(void) { HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); #ifdef UART_DEV + UART_CLK_EN(); + // UART GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; @@ -159,7 +161,7 @@ int board_uart_write(void const* buf, int len) { HAL_UART_Transmit(&UartHandle, (uint8_t*) (uintptr_t) buf, len, 0xffff); return len; #else - (void) buf; (void) len; (void) UartHandle; + (void) buf; (void) len; return 0; #endif } -- cgit v1.3.1 From 201b9707b9e6ce576fd534347b36652f2c6173f0 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 24 Jan 2025 00:52:24 +0700 Subject: try build zephyr with ci --- .github/workflows/build.yml | 27 ++++++++++++++++++++++++--- .west/config | 6 ------ examples/west.yml | 2 +- hw/bsp/family_support.cmake | 2 +- 4 files changed, 26 insertions(+), 11 deletions(-) delete mode 100644 .west/config (limited to 'hw') diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 170f73fae..060129d0f 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -59,7 +59,7 @@ jobs: toolchain: # - 'arm-clang' is built by circle-ci in PR - 'aarch64-gcc' - - 'arm-gcc' +# - 'arm-gcc' - 'msp430-gcc' - 'riscv-gcc' with: @@ -72,7 +72,7 @@ jobs: # Build Make (built by circle-ci in PR, only build on push here) # --------------------------------------- make: - if: github.event_name == 'push' + if: github.event_name == 'push' && false needs: set-matrix uses: ./.github/workflows/build_util.yml strategy: @@ -113,7 +113,7 @@ jobs: # Build IAR on HFP self-hosted # --------------------------------------- arm-iar: - if: github.repository_owner == 'hathach' && github.event_name == 'push' + if: github.repository_owner == 'hathach' && github.event_name == 'push' && false needs: set-matrix runs-on: [self-hosted, Linux, X64, hifiphile] env: @@ -137,3 +137,24 @@ jobs: - name: Build run: python3 tools/build.py --one-per-family --toolchain iar $BUILD_ARGS + + # --------------------------------------- + # Zephyr + # --------------------------------------- + zephyr: + if: github.event_name == 'push' + runs-on: ubuntu-latest + steps: + - name: Checkout TinyUSB + uses: actions/checkout@v4 + + - name: Setup Zephyr project + uses: zephyrproject-rtos/action-zephyr-setup@v1 + with: + app-path: examples + toolchains: arm-zephyr-eabi + + - name: Build + run: | + west build -b pca10056 examples/device/cdc_msc + west build -b pca10056 examples/device/msc_dual_lun diff --git a/.west/config b/.west/config deleted file mode 100644 index 2518007f6..000000000 --- a/.west/config +++ /dev/null @@ -1,6 +0,0 @@ -[manifest] -path = examples -file = west.yml - -[zephyr] -base = lib/zephyr diff --git a/examples/west.yml b/examples/west.yml index 383815c45..0683f6861 100644 --- a/examples/west.yml +++ b/examples/west.yml @@ -6,7 +6,7 @@ manifest: - name: zephyr remote: zephyrproject-rtos revision: main - path: lib/zephyr + path: zephyr import: true self: path: . diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 6ba7cb1c7..14916f771 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -75,7 +75,7 @@ endif() if (BUILD_ZEPHYR) set(BOARD_ROOT ${TOP}/hw/bsp/${FAMILY}) - find_package(Zephyr REQUIRED HINTS ${TOP}/lib/zephyr) + find_package(Zephyr REQUIRED HINTS ${TOP}/zephyr) endif () #------------------------------------------------------------- -- cgit v1.3.1 From b53801a8acc710e969b50849747585903b5b3025 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 24 Jan 2025 15:06:05 +0700 Subject: add cmake RTOS=zephyr (default noos) for zephyr build --- .../build_system/cmake/toolchain/arm_gcc.cmake | 36 ++++++++++++---------- examples/build_system/cmake/toolchain/common.cmake | 4 --- examples/device/board_test/CMakeLists.txt | 13 ++------ examples/device/cdc_msc/CMakeLists.txt | 8 ++--- examples/device/msc_dual_lun/CMakeLists.txt | 8 ++--- hw/bsp/broadcom_32bit/family.cmake | 2 +- hw/bsp/broadcom_64bit/family.cmake | 2 +- hw/bsp/ch32v10x/family.cmake | 2 +- hw/bsp/ch32v20x/family.cmake | 2 +- hw/bsp/ch32v307/family.cmake | 2 +- hw/bsp/da1469x/family.cmake | 2 +- hw/bsp/f1c100s/family.cmake | 2 +- hw/bsp/family_support.cmake | 19 +++++++----- hw/bsp/fomu/family.cmake | 2 +- hw/bsp/gd32vf103/family.cmake | 2 +- hw/bsp/imxrt/family.cmake | 2 +- hw/bsp/kinetis_k/family.cmake | 2 +- hw/bsp/kinetis_k32l2/family.cmake | 2 +- hw/bsp/kinetis_kl/family.cmake | 2 +- hw/bsp/lpc11/family.cmake | 2 +- hw/bsp/lpc13/family.cmake | 2 +- hw/bsp/lpc15/family.cmake | 2 +- hw/bsp/lpc17/family.cmake | 2 +- hw/bsp/lpc18/family.cmake | 2 +- hw/bsp/lpc40/family.cmake | 2 +- hw/bsp/lpc43/family.cmake | 2 +- hw/bsp/lpc51/family.cmake | 2 +- hw/bsp/lpc54/family.cmake | 2 +- hw/bsp/lpc55/family.cmake | 2 +- hw/bsp/max32650/family.cmake | 2 +- hw/bsp/max32666/family.cmake | 2 +- hw/bsp/max32690/family.cmake | 2 +- hw/bsp/max78002/family.cmake | 2 +- hw/bsp/mcx/family.cmake | 4 +-- hw/bsp/mm32/family.cmake | 2 +- hw/bsp/msp430/family.cmake | 2 +- hw/bsp/msp432e4/family.cmake | 2 +- hw/bsp/nrf/family.cmake | 10 ++---- hw/bsp/ra/family.cmake | 2 +- hw/bsp/samd11/family.cmake | 2 +- hw/bsp/samd21/family.cmake | 2 +- hw/bsp/samd5x_e5x/family.cmake | 2 +- hw/bsp/samg/family.cmake | 2 +- hw/bsp/saml2x/family.cmake | 2 +- hw/bsp/stm32c0/family.cmake | 2 +- hw/bsp/stm32f0/family.cmake | 2 +- hw/bsp/stm32f1/family.cmake | 2 +- hw/bsp/stm32f2/family.cmake | 2 +- hw/bsp/stm32f3/family.cmake | 2 +- hw/bsp/stm32f4/family.cmake | 2 +- hw/bsp/stm32f7/family.cmake | 2 +- hw/bsp/stm32g0/family.cmake | 2 +- hw/bsp/stm32g4/family.cmake | 2 +- hw/bsp/stm32h5/family.cmake | 2 +- hw/bsp/stm32h7/family.cmake | 2 +- hw/bsp/stm32l0/family.cmake | 2 +- hw/bsp/stm32l4/family.cmake | 2 +- hw/bsp/stm32u5/family.cmake | 2 +- hw/bsp/stm32wb/family.cmake | 2 +- hw/bsp/tm4c/family.cmake | 2 +- hw/bsp/xmc4000/family.cmake | 2 +- 61 files changed, 96 insertions(+), 112 deletions(-) (limited to 'hw') diff --git a/examples/build_system/cmake/toolchain/arm_gcc.cmake b/examples/build_system/cmake/toolchain/arm_gcc.cmake index 0b0949dd8..4cef07ff5 100644 --- a/examples/build_system/cmake/toolchain/arm_gcc.cmake +++ b/examples/build_system/cmake/toolchain/arm_gcc.cmake @@ -1,21 +1,25 @@ -if (NOT DEFINED CMAKE_C_COMPILER) - set(CMAKE_C_COMPILER "arm-none-eabi-gcc") -endif () +if (RTOS STREQUAL zephyr) -if (NOT DEFINED CMAKE_CXX_COMPILER) - set(CMAKE_CXX_COMPILER "arm-none-eabi-g++") -endif () +else () + if (NOT DEFINED CMAKE_C_COMPILER) + set(CMAKE_C_COMPILER "arm-none-eabi-gcc") + endif () + + if (NOT DEFINED CMAKE_CXX_COMPILER) + set(CMAKE_CXX_COMPILER "arm-none-eabi-g++") + endif () -set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) -find_program(CMAKE_SIZE arm-none-eabi-size) -find_program(CMAKE_OBJCOPY arm-none-eabi-objcopy) -find_program(CMAKE_OBJDUMP arm-none-eabi-objdump) + set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) + find_program(CMAKE_SIZE arm-none-eabi-size) + find_program(CMAKE_OBJCOPY arm-none-eabi-objcopy) + find_program(CMAKE_OBJDUMP arm-none-eabi-objdump) -include(${CMAKE_CURRENT_LIST_DIR}/common.cmake) + include(${CMAKE_CURRENT_LIST_DIR}/common.cmake) -get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE) -if (IS_IN_TRY_COMPILE) - set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib") - set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib") - cmake_print_variables(CMAKE_C_LINK_FLAGS) + get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE) + if (IS_IN_TRY_COMPILE) + set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib") + set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib") + cmake_print_variables(CMAKE_C_LINK_FLAGS) + endif () endif () diff --git a/examples/build_system/cmake/toolchain/common.cmake b/examples/build_system/cmake/toolchain/common.cmake index 7fe0aac4b..4c181137b 100644 --- a/examples/build_system/cmake/toolchain/common.cmake +++ b/examples/build_system/cmake/toolchain/common.cmake @@ -1,7 +1,3 @@ -if (BUILD_ZEPHYR) - return() -endif() - include(CMakePrintHelpers) # ---------------------------------------------------------------------------- diff --git a/examples/device/board_test/CMakeLists.txt b/examples/device/board_test/CMakeLists.txt index adcc3ba3d..9a604a732 100644 --- a/examples/device/board_test/CMakeLists.txt +++ b/examples/device/board_test/CMakeLists.txt @@ -5,11 +5,6 @@ include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) # gets PROJECT name for the example (e.g. -) family_get_project_name(PROJECT ${CMAKE_CURRENT_LIST_DIR}) -if (BUILD_ZEPHYR) - set(BOARD_ROOT ${TOP}/hw/bsp/${FAMILY}) - find_package(Zephyr REQUIRED HINTS ${TOP}/lib/zephyr) -endif () - project(${PROJECT} C CXX ASM) # Checks this example is valid for the family and initializes the project @@ -20,7 +15,7 @@ if(FAMILY STREQUAL "espressif") return() endif() -if (BUILD_ZEPHYR) +if (RTOS STREQUAL zephyr) set(EXE_NAME app) else() set(EXE_NAME ${PROJECT}) @@ -39,8 +34,4 @@ target_include_directories(${EXE_NAME} PUBLIC # Configure compilation flags and libraries for the example without RTOS. # See the corresponding function in hw/bsp/FAMILY/family.cmake for details. -if (BUILD_ZEPHYR) - family_configure_device_example(${EXE_NAME} zephyr) -else() - family_configure_device_example(${EXE_NAME} noos) -endif() +family_configure_device_example(${EXE_NAME} ${RTOS}) diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt index 1c00ae0b2..b07f92342 100644 --- a/examples/device/cdc_msc/CMakeLists.txt +++ b/examples/device/cdc_msc/CMakeLists.txt @@ -16,7 +16,7 @@ if(FAMILY STREQUAL "espressif") return() endif() -if (BUILD_ZEPHYR) +if (RTOS STREQUAL zephyr) set(EXE_NAME app) else() set(EXE_NAME ${PROJECT}) @@ -37,8 +37,4 @@ target_include_directories(${EXE_NAME} PUBLIC # Configure compilation flags and libraries for the example without RTOS. # See the corresponding function in hw/bsp/FAMILY/family.cmake for details. -if (BUILD_ZEPHYR) - family_configure_device_example(${EXE_NAME} zephyr) -else() - family_configure_device_example(${EXE_NAME} noos) -endif() +family_configure_device_example(${EXE_NAME} ${RTOS}) diff --git a/examples/device/msc_dual_lun/CMakeLists.txt b/examples/device/msc_dual_lun/CMakeLists.txt index 8c39168e8..3955bfb49 100644 --- a/examples/device/msc_dual_lun/CMakeLists.txt +++ b/examples/device/msc_dual_lun/CMakeLists.txt @@ -15,7 +15,7 @@ if(FAMILY STREQUAL "espressif") return() endif() -if (BUILD_ZEPHYR) +if (RTOS STREQUAL zephyr) set(EXE_NAME app) else() set(EXE_NAME ${PROJECT}) @@ -36,8 +36,4 @@ target_include_directories(${EXE_NAME} PUBLIC # Configure compilation flags and libraries for the example without RTOS. # See the corresponding function in hw/bsp/FAMILY/family.cmake for details. -if (BUILD_ZEPHYR) - family_configure_device_example(${EXE_NAME} zephyr) -else() - family_configure_device_example(${EXE_NAME} noos) -endif() +family_configure_device_example(${EXE_NAME} ${RTOS}) diff --git a/hw/bsp/broadcom_32bit/family.cmake b/hw/bsp/broadcom_32bit/family.cmake index 09c32c7d4..18227f702 100644 --- a/hw/bsp/broadcom_32bit/family.cmake +++ b/hw/bsp/broadcom_32bit/family.cmake @@ -94,7 +94,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_BCM2835 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_BCM2835) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c diff --git a/hw/bsp/broadcom_64bit/family.cmake b/hw/bsp/broadcom_64bit/family.cmake index 566daefb3..f5245be36 100644 --- a/hw/bsp/broadcom_64bit/family.cmake +++ b/hw/bsp/broadcom_64bit/family.cmake @@ -101,7 +101,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_BCM${BCM_VERSION} ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_BCM${BCM_VERSION}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c diff --git a/hw/bsp/ch32v10x/family.cmake b/hw/bsp/ch32v10x/family.cmake index 92acaed80..9b395e92d 100644 --- a/hw/bsp/ch32v10x/family.cmake +++ b/hw/bsp/ch32v10x/family.cmake @@ -98,7 +98,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_CH32V103 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_CH32V103) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/wch/dcd_ch32_usbfs.c diff --git a/hw/bsp/ch32v20x/family.cmake b/hw/bsp/ch32v20x/family.cmake index d4f25f25f..9748184c2 100644 --- a/hw/bsp/ch32v20x/family.cmake +++ b/hw/bsp/ch32v20x/family.cmake @@ -123,7 +123,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_CH32V20X ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_CH32V20X) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/wch/dcd_ch32_usbfs.c diff --git a/hw/bsp/ch32v307/family.cmake b/hw/bsp/ch32v307/family.cmake index 0fd78fa03..e4b84198c 100644 --- a/hw/bsp/ch32v307/family.cmake +++ b/hw/bsp/ch32v307/family.cmake @@ -113,7 +113,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_CH32V307 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_CH32V307) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/wch/dcd_ch32_usbhs.c ${TOP}/src/portable/wch/dcd_ch32_usbfs.c diff --git a/hw/bsp/da1469x/family.cmake b/hw/bsp/da1469x/family.cmake index ca6b57635..7bb6f5d86 100644 --- a/hw/bsp/da1469x/family.cmake +++ b/hw/bsp/da1469x/family.cmake @@ -126,7 +126,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_DA1469X ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_DA1469X) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/dialog/da146xx/dcd_da146xx.c ) diff --git a/hw/bsp/f1c100s/family.cmake b/hw/bsp/f1c100s/family.cmake index 013e61dde..0565f7545 100644 --- a/hw/bsp/f1c100s/family.cmake +++ b/hw/bsp/f1c100s/family.cmake @@ -100,7 +100,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_F1C100S ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_F1C100S) target_sources(${TARGET}-tinyusb PRIVATE ${TOP}/src/portable/sunxi/dcd_sunxi_musb.c ) diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 14916f771..1e86529ed 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -8,6 +8,13 @@ get_filename_component(TOP ${TOP} ABSOLUTE) set(UF2CONV_PY ${TOP}/tools/uf2/utils/uf2conv.py) +#------------------------------------------------------------- +# RTOS +#------------------------------------------------------------- +if (NOT DEFINED RTOS) + set(RTOS noos) +endif () + #------------------------------------------------------------- # Toolchain # Can be changed via -DTOOLCHAIN=gcc|iar or -DCMAKE_C_COMPILER= @@ -27,7 +34,6 @@ if (DEFINED CMAKE_C_COMPILER) endif () endif () -# default to gcc if (NOT DEFINED TOOLCHAIN) set(TOOLCHAIN gcc) endif () @@ -73,7 +79,7 @@ if (NOT NO_WARN_RWX_SEGMENTS_SUPPORTED) set(NO_WARN_RWX_SEGMENTS_SUPPORTED 1) endif() -if (BUILD_ZEPHYR) +if (RTOS STREQUAL zephyr) set(BOARD_ROOT ${TOP}/hw/bsp/${FAMILY}) find_package(Zephyr REQUIRED HINTS ${TOP}/zephyr) endif () @@ -170,7 +176,6 @@ function(family_add_rtos TARGET RTOS) elseif (RTOS STREQUAL "zephyr") target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_ZEPHYR) target_include_directories(${TARGET} PUBLIC ${ZEPHYR_BASE}/include) -# target_link_libraries(${TARGET} PUBLIC kernel) endif () endfunction() @@ -237,7 +242,7 @@ function(family_configure_common TARGET RTOS) ) target_link_options(${TARGET} PUBLIC "LINKER:-Map=$.map") if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 - AND NO_WARN_RWX_SEGMENTS_SUPPORTED AND (NOT BUILD_ZEPHYR)) + AND NO_WARN_RWX_SEGMENTS_SUPPORTED AND (NOT RTOS STREQUAL zephyr)) target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") endif () elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") @@ -253,8 +258,8 @@ function(family_configure_common TARGET RTOS) # endif () endfunction() -# Add tinyusb to target (TODO remove RTOS) -function(family_add_tinyusb TARGET OPT_MCU RTOS) +# Add tinyusb to target +function(family_add_tinyusb TARGET OPT_MCU) # tinyusb's CMakeList.txt add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) @@ -401,7 +406,7 @@ function(family_flash_jlink TARGET) endif () separate_arguments(OPTION_LIST UNIX_COMMAND ${JLINK_OPTION}) - if (BUILD_ZEPHYR) + if (RTOS STREQUAL zephyr) set(BINARY_TARGET zephyr_final) set(NAME_TARGET ${CMAKE_PROJECT_NAME}) else () diff --git a/hw/bsp/fomu/family.cmake b/hw/bsp/fomu/family.cmake index 132730086..d8141a7b3 100644 --- a/hw/bsp/fomu/family.cmake +++ b/hw/bsp/fomu/family.cmake @@ -77,7 +77,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_VALENTYUSB_EPTRI ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_VALENTYUSB_EPTRI) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/valentyusb/eptri/dcd_eptri.c ) diff --git a/hw/bsp/gd32vf103/family.cmake b/hw/bsp/gd32vf103/family.cmake index 273fea39f..5b145692f 100644 --- a/hw/bsp/gd32vf103/family.cmake +++ b/hw/bsp/gd32vf103/family.cmake @@ -105,7 +105,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_GD32VF103 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_GD32VF103) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 5a31e42a6..8ec96bf33 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -138,7 +138,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX) target_sources(${TARGET}-tinyusb PRIVATE ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c diff --git a/hw/bsp/kinetis_k/family.cmake b/hw/bsp/kinetis_k/family.cmake index 7fd3f6353..e9993ed7b 100644 --- a/hw/bsp/kinetis_k/family.cmake +++ b/hw/bsp/kinetis_k/family.cmake @@ -97,7 +97,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_K ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_K) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c ${TOP}/src/portable/nxp/khci/hcd_khci.c diff --git a/hw/bsp/kinetis_k32l2/family.cmake b/hw/bsp/kinetis_k32l2/family.cmake index 25710a4c2..a76b05745 100644 --- a/hw/bsp/kinetis_k32l2/family.cmake +++ b/hw/bsp/kinetis_k32l2/family.cmake @@ -92,7 +92,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_K32L ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_K32L) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/nxp/khci/dcd_khci.c ${TOP}/src/portable/nxp/khci/hcd_khci.c diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake index d8d8d3631..c0ca0e77a 100644 --- a/hw/bsp/kinetis_kl/family.cmake +++ b/hw/bsp/kinetis_kl/family.cmake @@ -96,7 +96,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_KL ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_KL) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c ${TOP}/src/portable/nxp/khci/hcd_khci.c diff --git a/hw/bsp/lpc11/family.cmake b/hw/bsp/lpc11/family.cmake index a3efecb99..e11268bb2 100644 --- a/hw/bsp/lpc11/family.cmake +++ b/hw/bsp/lpc11/family.cmake @@ -90,7 +90,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC11UXX ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_LPC11UXX) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) diff --git a/hw/bsp/lpc13/family.cmake b/hw/bsp/lpc13/family.cmake index d360048ed..500ddb3b0 100644 --- a/hw/bsp/lpc13/family.cmake +++ b/hw/bsp/lpc13/family.cmake @@ -87,7 +87,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC13XX ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_LPC13XX) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) diff --git a/hw/bsp/lpc15/family.cmake b/hw/bsp/lpc15/family.cmake index 5ad12501a..daad44bc0 100644 --- a/hw/bsp/lpc15/family.cmake +++ b/hw/bsp/lpc15/family.cmake @@ -89,7 +89,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC15XX ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_LPC15XX) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) diff --git a/hw/bsp/lpc17/family.cmake b/hw/bsp/lpc17/family.cmake index 4f2aae19b..7e7f036de 100644 --- a/hw/bsp/lpc17/family.cmake +++ b/hw/bsp/lpc17/family.cmake @@ -86,7 +86,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC175X_6X ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_LPC175X_6X) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/nxp/lpc17_40/dcd_lpc17_40.c ${TOP}/src/portable/nxp/lpc17_40/hcd_lpc17_40.c diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake index 70dad48c3..5542496f0 100644 --- a/hw/bsp/lpc18/family.cmake +++ b/hw/bsp/lpc18/family.cmake @@ -84,7 +84,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC18XX ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_LPC18XX) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c diff --git a/hw/bsp/lpc40/family.cmake b/hw/bsp/lpc40/family.cmake index 0bcdc6037..afbf6a22f 100644 --- a/hw/bsp/lpc40/family.cmake +++ b/hw/bsp/lpc40/family.cmake @@ -87,7 +87,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC40XX ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_LPC40XX) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/nxp/lpc17_40/dcd_lpc17_40.c ${TOP}/src/portable/nxp/lpc17_40/hcd_lpc17_40.c diff --git a/hw/bsp/lpc43/family.cmake b/hw/bsp/lpc43/family.cmake index 9ed937c24..620b4baa2 100644 --- a/hw/bsp/lpc43/family.cmake +++ b/hw/bsp/lpc43/family.cmake @@ -92,7 +92,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC43XX ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_LPC43XX) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c diff --git a/hw/bsp/lpc51/family.cmake b/hw/bsp/lpc51/family.cmake index 94d6b0bf0..be3e9f02d 100644 --- a/hw/bsp/lpc51/family.cmake +++ b/hw/bsp/lpc51/family.cmake @@ -106,7 +106,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC51 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_LPC51) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake index eb76de6b6..af5ee823b 100644 --- a/hw/bsp/lpc54/family.cmake +++ b/hw/bsp/lpc54/family.cmake @@ -139,7 +139,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC54 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_LPC54) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake index 6a06846c4..2d99daf21 100644 --- a/hw/bsp/lpc55/family.cmake +++ b/hw/bsp/lpc55/family.cmake @@ -140,7 +140,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_LPC55 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_LPC55) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake index 0978bf0dc..d114e0948 100644 --- a/hw/bsp/max32650/family.cmake +++ b/hw/bsp/max32650/family.cmake @@ -130,7 +130,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MAX32650 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_MAX32650) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/mentor/musb/dcd_musb.c ) diff --git a/hw/bsp/max32666/family.cmake b/hw/bsp/max32666/family.cmake index 0ef9bcdcc..a78e74670 100644 --- a/hw/bsp/max32666/family.cmake +++ b/hw/bsp/max32666/family.cmake @@ -125,7 +125,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MAX32666 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_MAX32666) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/mentor/musb/dcd_musb.c ) diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake index d5d1bb3ba..d79403dee 100644 --- a/hw/bsp/max32690/family.cmake +++ b/hw/bsp/max32690/family.cmake @@ -130,7 +130,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MAX32690 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_MAX32690) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/mentor/musb/dcd_musb.c ) diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake index b836408fc..7e65f58ed 100644 --- a/hw/bsp/max78002/family.cmake +++ b/hw/bsp/max78002/family.cmake @@ -134,7 +134,7 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MAX78002 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_MAX78002) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/mentor/musb/dcd_musb.c ) diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake index 0a7501ca3..8eed8f19b 100644 --- a/hw/bsp/mcx/family.cmake +++ b/hw/bsp/mcx/family.cmake @@ -110,9 +110,9 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source if (${FAMILY_MCUS} STREQUAL "MCXN9") - family_add_tinyusb(${TARGET} OPT_MCU_MCXN9 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_MCXN9) elseif(${FAMILY_MCUS} STREQUAL "MCXA15") - family_add_tinyusb(${TARGET} OPT_MCU_MCXA15 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_MCXA15) endif() target_sources(${TARGET}-tinyusb PUBLIC diff --git a/hw/bsp/mm32/family.cmake b/hw/bsp/mm32/family.cmake index e0fb0ca93..eea1ae85e 100644 --- a/hw/bsp/mm32/family.cmake +++ b/hw/bsp/mm32/family.cmake @@ -87,7 +87,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MM32F327X ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_MM32F327X) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c ) diff --git a/hw/bsp/msp430/family.cmake b/hw/bsp/msp430/family.cmake index 64bcb3fd2..94e045ae5 100644 --- a/hw/bsp/msp430/family.cmake +++ b/hw/bsp/msp430/family.cmake @@ -69,7 +69,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MSP430x5xx ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_MSP430x5xx) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c ) diff --git a/hw/bsp/msp432e4/family.cmake b/hw/bsp/msp432e4/family.cmake index 6a6650e28..b46af45fa 100644 --- a/hw/bsp/msp432e4/family.cmake +++ b/hw/bsp/msp432e4/family.cmake @@ -85,7 +85,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_MSP432E4 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_MSP432E4) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/mentor/musb/dcd_musb.c ${TOP}/src/portable/mentor/musb/hcd_musb.c diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 1e7a4fe82..2d2a12e7e 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -25,10 +25,6 @@ set(FAMILY_MCUS NRF5X CACHE INTERNAL "") #------------------------------------ # only need to be built ONCE for all examples function(add_board_target BOARD_TARGET) - if (BUILD_ZEPHYR) - return() - endif () - if (TARGET ${BOARD_TARGET}) return() endif () @@ -114,8 +110,8 @@ endfunction() function(family_configure_example TARGET RTOS) # Board target - add_board_target(board_${BOARD}) - if (NOT BUILD_ZEPHYR) + if (NOT RTOS STREQUAL zephyr) + add_board_target(board_${BOARD}) target_link_libraries(${TARGET} PUBLIC board_${BOARD}) endif () @@ -136,7 +132,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_NRF5X) target_sources(${TARGET} PRIVATE ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c ) diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index f920a8219..8ae8e9b59 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -147,7 +147,7 @@ function(family_configure_example TARGET RTOS) # endif () # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_RAXXX ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_RAXXX) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c diff --git a/hw/bsp/samd11/family.cmake b/hw/bsp/samd11/family.cmake index c794d8f37..4a40ca063 100644 --- a/hw/bsp/samd11/family.cmake +++ b/hw/bsp/samd11/family.cmake @@ -100,7 +100,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_SAMD11 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_SAMD11) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/microchip/samd/dcd_samd.c ) diff --git a/hw/bsp/samd21/family.cmake b/hw/bsp/samd21/family.cmake index b946dc4c0..4a10d6224 100644 --- a/hw/bsp/samd21/family.cmake +++ b/hw/bsp/samd21/family.cmake @@ -96,7 +96,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_SAMD21 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_SAMD21) target_sources(${TARGET} PUBLIC ${TOP}/src/portable/microchip/samd/dcd_samd.c ) diff --git a/hw/bsp/samd5x_e5x/family.cmake b/hw/bsp/samd5x_e5x/family.cmake index 1153a5fbd..50e0ec66d 100644 --- a/hw/bsp/samd5x_e5x/family.cmake +++ b/hw/bsp/samd5x_e5x/family.cmake @@ -93,7 +93,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_SAMD51 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_SAMD51) target_sources(${TARGET} PUBLIC ${TOP}/src/portable/microchip/samd/dcd_samd.c ) diff --git a/hw/bsp/samg/family.cmake b/hw/bsp/samg/family.cmake index 4a1cbd730..aef17d379 100644 --- a/hw/bsp/samg/family.cmake +++ b/hw/bsp/samg/family.cmake @@ -98,7 +98,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_SAMG ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_SAMG) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/microchip/samg/dcd_samg.c ) diff --git a/hw/bsp/saml2x/family.cmake b/hw/bsp/saml2x/family.cmake index bf6b0e251..37e282a18 100644 --- a/hw/bsp/saml2x/family.cmake +++ b/hw/bsp/saml2x/family.cmake @@ -100,7 +100,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_SAML22 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_SAML22) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/microchip/samd/dcd_samd.c ) diff --git a/hw/bsp/stm32c0/family.cmake b/hw/bsp/stm32c0/family.cmake index dd0fd4074..ca6a93adf 100644 --- a/hw/bsp/stm32c0/family.cmake +++ b/hw/bsp/stm32c0/family.cmake @@ -102,7 +102,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32C0 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_STM32C0) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ${TOP}/src/portable/st/typec/typec_stm32.c diff --git a/hw/bsp/stm32f0/family.cmake b/hw/bsp/stm32f0/family.cmake index 7187d0573..c0da094d7 100644 --- a/hw/bsp/stm32f0/family.cmake +++ b/hw/bsp/stm32f0/family.cmake @@ -100,7 +100,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32F0 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_STM32F0) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) diff --git a/hw/bsp/stm32f1/family.cmake b/hw/bsp/stm32f1/family.cmake index 09a93e483..4eba6df93 100644 --- a/hw/bsp/stm32f1/family.cmake +++ b/hw/bsp/stm32f1/family.cmake @@ -99,7 +99,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32F1 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_STM32F1) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) diff --git a/hw/bsp/stm32f2/family.cmake b/hw/bsp/stm32f2/family.cmake index 7f9839442..6a22d1550 100644 --- a/hw/bsp/stm32f2/family.cmake +++ b/hw/bsp/stm32f2/family.cmake @@ -99,7 +99,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32F2 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_STM32F2) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c diff --git a/hw/bsp/stm32f3/family.cmake b/hw/bsp/stm32f3/family.cmake index 50fede817..053bbbacc 100644 --- a/hw/bsp/stm32f3/family.cmake +++ b/hw/bsp/stm32f3/family.cmake @@ -97,7 +97,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32F3 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_STM32F3) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) diff --git a/hw/bsp/stm32f4/family.cmake b/hw/bsp/stm32f4/family.cmake index 10b98b7a6..5f12eb8b2 100644 --- a/hw/bsp/stm32f4/family.cmake +++ b/hw/bsp/stm32f4/family.cmake @@ -125,7 +125,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32F4 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_STM32F4) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c diff --git a/hw/bsp/stm32f7/family.cmake b/hw/bsp/stm32f7/family.cmake index f7001a2ed..8cc18935d 100644 --- a/hw/bsp/stm32f7/family.cmake +++ b/hw/bsp/stm32f7/family.cmake @@ -127,7 +127,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32F7 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_STM32F7) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake index 7ac19693c..2ab5719bc 100644 --- a/hw/bsp/stm32g0/family.cmake +++ b/hw/bsp/stm32g0/family.cmake @@ -101,7 +101,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32G0 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_STM32G0) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ${TOP}/src/portable/st/typec/typec_stm32.c diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake index e0fca4b30..d51b3599a 100644 --- a/hw/bsp/stm32g4/family.cmake +++ b/hw/bsp/stm32g4/family.cmake @@ -97,7 +97,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32G4 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_STM32G4) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ${TOP}/src/portable/st/typec/typec_stm32.c diff --git a/hw/bsp/stm32h5/family.cmake b/hw/bsp/stm32h5/family.cmake index a2e4c6e8e..54392fe1a 100644 --- a/hw/bsp/stm32h5/family.cmake +++ b/hw/bsp/stm32h5/family.cmake @@ -101,7 +101,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32H5 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_STM32H5) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ${TOP}/src/portable/st/typec/typec_stm32.c diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake index 65f6884da..e50bbf4a2 100644 --- a/hw/bsp/stm32h7/family.cmake +++ b/hw/bsp/stm32h7/family.cmake @@ -132,7 +132,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32H7 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_STM32H7) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c diff --git a/hw/bsp/stm32l0/family.cmake b/hw/bsp/stm32l0/family.cmake index 5f29d254d..435c658ec 100644 --- a/hw/bsp/stm32l0/family.cmake +++ b/hw/bsp/stm32l0/family.cmake @@ -101,7 +101,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32L0 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_STM32L0) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) diff --git a/hw/bsp/stm32l4/family.cmake b/hw/bsp/stm32l4/family.cmake index 6a967de6f..4d2ccf178 100644 --- a/hw/bsp/stm32l4/family.cmake +++ b/hw/bsp/stm32l4/family.cmake @@ -101,7 +101,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS} ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c diff --git a/hw/bsp/stm32u5/family.cmake b/hw/bsp/stm32u5/family.cmake index 0a2ad568d..2cbe5cf38 100644 --- a/hw/bsp/stm32u5/family.cmake +++ b/hw/bsp/stm32u5/family.cmake @@ -101,7 +101,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_STM32U5 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_STM32U5) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c diff --git a/hw/bsp/stm32wb/family.cmake b/hw/bsp/stm32wb/family.cmake index 868b58f71..d6d841baa 100644 --- a/hw/bsp/stm32wb/family.cmake +++ b/hw/bsp/stm32wb/family.cmake @@ -104,7 +104,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS} ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) diff --git a/hw/bsp/tm4c/family.cmake b/hw/bsp/tm4c/family.cmake index 110bd9f10..833b6c5e4 100644 --- a/hw/bsp/tm4c/family.cmake +++ b/hw/bsp/tm4c/family.cmake @@ -79,7 +79,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_TM4C123 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_TM4C123) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/mentor/musb/dcd_musb.c ${TOP}/src/portable/mentor/musb/hcd_musb.c diff --git a/hw/bsp/xmc4000/family.cmake b/hw/bsp/xmc4000/family.cmake index 6266f8f94..be72d349f 100644 --- a/hw/bsp/xmc4000/family.cmake +++ b/hw/bsp/xmc4000/family.cmake @@ -83,7 +83,7 @@ function(family_configure_example TARGET RTOS) ) # Add TinyUSB target and port source - family_add_tinyusb(${TARGET} OPT_MCU_XMC4000 ${RTOS}) + family_add_tinyusb(${TARGET} OPT_MCU_XMC4000) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c -- cgit v1.3.1 From 13856af9350965e5d67e1e76d16e3702e77aa77e Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 24 Jan 2025 15:15:31 +0700 Subject: add -DRTOS=zephyr to ci west build --- .github/workflows/build.yml | 4 +- examples/device/msc_dual_lun/prj.conf | 6 + hw/bsp/family_support.cmake | 1 + hw/bsp/nrf/boards/pca10056/zephyr/Kconfig.pca10056 | 5 + hw/bsp/nrf/boards/pca10056/zephyr/board.yml | 6 + .../pca10056/zephyr/pca10056_nrf52840-pinctrl.dtsi | 187 ++++++++++++++ .../boards/pca10056/zephyr/pca10056_nrf52840.dts | 278 +++++++++++++++++++++ .../boards/pca10056/zephyr/pca10056_nrf52840.yaml | 28 +++ 8 files changed, 513 insertions(+), 2 deletions(-) create mode 100644 examples/device/msc_dual_lun/prj.conf create mode 100644 hw/bsp/nrf/boards/pca10056/zephyr/Kconfig.pca10056 create mode 100644 hw/bsp/nrf/boards/pca10056/zephyr/board.yml create mode 100644 hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840-pinctrl.dtsi create mode 100644 hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840.dts create mode 100644 hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840.yaml (limited to 'hw') diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 060129d0f..90bc10883 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -156,5 +156,5 @@ jobs: - name: Build run: | - west build -b pca10056 examples/device/cdc_msc - west build -b pca10056 examples/device/msc_dual_lun + west -v build -b pca10056 -d examples/device/cdc_msc/build examples/device/cdc_msc -- -DRTOS=zephyr + west -v build -b pca10056 -d examples/device/msc_dual_lun/build examples/device/msc_dual_lun -- -DRTOS=zephyr diff --git a/examples/device/msc_dual_lun/prj.conf b/examples/device/msc_dual_lun/prj.conf new file mode 100644 index 000000000..2f5139d9d --- /dev/null +++ b/examples/device/msc_dual_lun/prj.conf @@ -0,0 +1,6 @@ +CONFIG_GPIO=y +CONFIG_FPU=y +CONFIG_NO_OPTIMIZATIONS=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_NRFX_POWER=y +CONFIG_NRFX_UARTE0=y diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 1e86529ed..1725f0de6 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -81,6 +81,7 @@ endif() if (RTOS STREQUAL zephyr) set(BOARD_ROOT ${TOP}/hw/bsp/${FAMILY}) + cmake_print_variables(BOARD_ROOT BOARD) find_package(Zephyr REQUIRED HINTS ${TOP}/zephyr) endif () diff --git a/hw/bsp/nrf/boards/pca10056/zephyr/Kconfig.pca10056 b/hw/bsp/nrf/boards/pca10056/zephyr/Kconfig.pca10056 new file mode 100644 index 000000000..a4d9619b3 --- /dev/null +++ b/hw/bsp/nrf/boards/pca10056/zephyr/Kconfig.pca10056 @@ -0,0 +1,5 @@ +# Copyright (c) 2022 Zephyr Project members and individual contributors +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_PCA10056 + select SOC_NRF52840_QIAA diff --git a/hw/bsp/nrf/boards/pca10056/zephyr/board.yml b/hw/bsp/nrf/boards/pca10056/zephyr/board.yml new file mode 100644 index 000000000..e45a33365 --- /dev/null +++ b/hw/bsp/nrf/boards/pca10056/zephyr/board.yml @@ -0,0 +1,6 @@ +board: + name: pca10056 + full_name: nRF52840 DK + vendor: nordic + socs: + - name: nrf52840 diff --git a/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840-pinctrl.dtsi b/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840-pinctrl.dtsi new file mode 100644 index 000000000..779d0d518 --- /dev/null +++ b/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840-pinctrl.dtsi @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2022 Nordic Semiconductor + * SPDX-License-Identifier: Apache-2.0 + */ + +&pinctrl { + uart0_default: uart0_default { + group1 { + psels = , + ; + }; + group2 { + psels = , + ; + bias-pull-up; + }; + }; + + uart0_sleep: uart0_sleep { + group1 { + psels = , + , + , + ; + low-power-enable; + }; + }; + + uart1_default: uart1_default { + group1 { + psels = ; + bias-pull-up; + }; + group2 { + psels = ; + }; + }; + + uart1_sleep: uart1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + i2c0_default: i2c0_default { + group1 { + psels = , + ; + }; + }; + + i2c0_sleep: i2c0_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + i2c1_default: i2c1_default { + group1 { + psels = , + ; + }; + }; + + i2c1_sleep: i2c1_sleep { + group1 { + psels = , + ; + low-power-enable; + }; + }; + + pwm0_default: pwm0_default { + group1 { + psels = ; + nordic,invert; + }; + }; + + pwm0_sleep: pwm0_sleep { + group1 { + psels = ; + low-power-enable; + }; + }; + + spi0_default: spi0_default { + group1 { + psels = , + , + ; + }; + }; + + spi0_sleep: spi0_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + spi1_default: spi1_default { + group1 { + psels = , + , + ; + }; + }; + + spi1_sleep: spi1_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + spi2_default: spi2_default { + group1 { + psels = , + , + ; + }; + }; + + spi2_sleep: spi2_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + + qspi_default: qspi_default { + group1 { + psels = , + , + , + , + , + ; + nordic,drive-mode = ; + }; + }; + + qspi_sleep: qspi_sleep { + group1 { + psels = , + , + , + , + ; + low-power-enable; + }; + group2 { + psels = ; + low-power-enable; + bias-pull-up; + }; + }; + + spi3_default: spi3_default { + group1 { + psels = , + , + ; + }; + }; + + spi3_sleep: spi3_sleep { + group1 { + psels = , + , + ; + low-power-enable; + }; + }; + +}; diff --git a/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840.dts b/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840.dts new file mode 100644 index 000000000..d7c9266d2 --- /dev/null +++ b/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840.dts @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2017 Linaro Limited + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include "pca10056_nrf52840-pinctrl.dtsi" +#include + +/ { + model = "Nordic nRF52840 DK NRF52840"; + compatible = "nordic,nrf52840-dk-nrf52840"; + + chosen { + zephyr,console = &uart0; + zephyr,shell-uart = &uart0; + zephyr,uart-mcumgr = &uart0; + zephyr,bt-mon-uart = &uart0; + zephyr,bt-c2h-uart = &uart0; + zephyr,ieee802154 = &ieee802154; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; + label = "Green LED 0"; + }; + led1: led_1 { + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; + label = "Green LED 1"; + }; + led2: led_2 { + gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + label = "Green LED 2"; + }; + led3: led_3 { + gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; + label = "Green LED 3"; + }; + }; + + pwmleds { + compatible = "pwm-leds"; + pwm_led0: pwm_led_0 { + pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 0"; + zephyr,code = ; + }; + button1: button_1 { + gpios = <&gpio0 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 1"; + zephyr,code = ; + }; + button2: button_2 { + gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 2"; + zephyr,code = ; + }; + button3: button_3 { + gpios = <&gpio0 25 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; + label = "Push button switch 3"; + zephyr,code = ; + }; + }; + + arduino_header: connector { + compatible = "arduino-header-r3"; + #gpio-cells = <2>; + gpio-map-mask = <0xffffffff 0xffffffc0>; + gpio-map-pass-thru = <0 0x3f>; + gpio-map = <0 0 &gpio0 3 0>, /* A0 */ + <1 0 &gpio0 4 0>, /* A1 */ + <2 0 &gpio0 28 0>, /* A2 */ + <3 0 &gpio0 29 0>, /* A3 */ + <4 0 &gpio0 30 0>, /* A4 */ + <5 0 &gpio0 31 0>, /* A5 */ + <6 0 &gpio1 1 0>, /* D0 */ + <7 0 &gpio1 2 0>, /* D1 */ + <8 0 &gpio1 3 0>, /* D2 */ + <9 0 &gpio1 4 0>, /* D3 */ + <10 0 &gpio1 5 0>, /* D4 */ + <11 0 &gpio1 6 0>, /* D5 */ + <12 0 &gpio1 7 0>, /* D6 */ + <13 0 &gpio1 8 0>, /* D7 */ + <14 0 &gpio1 10 0>, /* D8 */ + <15 0 &gpio1 11 0>, /* D9 */ + <16 0 &gpio1 12 0>, /* D10 */ + <17 0 &gpio1 13 0>, /* D11 */ + <18 0 &gpio1 14 0>, /* D12 */ + <19 0 &gpio1 15 0>, /* D13 */ + <20 0 &gpio0 26 0>, /* D14 */ + <21 0 &gpio0 27 0>; /* D15 */ + }; + + arduino_adc: analog-connector { + compatible = "arduino,uno-adc"; + #io-channel-cells = <1>; + io-channel-map = <0 &adc 1>, /* A0 = P0.3 = AIN1 */ + <1 &adc 2>, /* A1 = P0.4 = AIN2 */ + <2 &adc 4>, /* A2 = P0.28 = AIN4 */ + <3 &adc 5>, /* A3 = P0.29 = AIN5 */ + <4 &adc 6>, /* A4 = P0.30 = AIN6 */ + <5 &adc 7>; /* A5 = P0.31 = AIN7 */ + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + led2 = &led2; + led3 = &led3; + pwm-led0 = &pwm_led0; + sw0 = &button0; + sw1 = &button1; + sw2 = &button2; + sw3 = &button3; + bootloader-led0 = &led0; + mcuboot-button0 = &button0; + mcuboot-led0 = &led0; + watchdog0 = &wdt0; + }; +}; + +®0 { + status = "okay"; +}; + +®1 { + regulator-initial-mode = ; +}; + +&adc { + status = "okay"; +}; + +&uicr { + gpio-as-nreset; +}; + +&gpiote { + status = "okay"; +}; + +&gpio0 { + status = "okay"; + gpio-reserved-ranges = <0 2>, <6 1>, <8 3>, <17 7>; + gpio-line-names = "XL1", "XL2", "AREF", "A0", "A1", "RTS", "TXD", + "CTS", "RXD", "NFC1", "NFC2", "BUTTON1", "BUTTON2", "LED1", + "LED2", "LED3", "LED4", "QSPI CS", "RESET", "QSPI CLK", + "QSPI DIO0", "QSPI DIO1", "QSPI DIO2", "QSPI DIO3","BUTTON3", + "BUTTON4", "SDA", "SCL", "A2", "A3", "A4", "A5"; +}; + +&gpio1 { + status = "okay"; + gpio-line-names = "", "D0", "D1", "D2", "D3", "D4", "D5", "D6", + "D7", "", "D8", "D9", "D10", "D11", "D12", "D13"; +}; + +&uart0 { + compatible = "nordic,nrf-uarte"; + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&uart0_default>; + pinctrl-1 = <&uart0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +arduino_serial: &uart1 { + current-speed = <115200>; + pinctrl-0 = <&uart1_default>; + pinctrl-1 = <&uart1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +arduino_i2c: &i2c0 { + compatible = "nordic,nrf-twi"; + status = "okay"; + pinctrl-0 = <&i2c0_default>; + pinctrl-1 = <&i2c0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&i2c1 { + compatible = "nordic,nrf-twi"; + /* Cannot be used together with spi1. */ + /* status = "okay"; */ + pinctrl-0 = <&i2c1_default>; + pinctrl-1 = <&i2c1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&pwm0 { + status = "okay"; + pinctrl-0 = <&pwm0_default>; + pinctrl-1 = <&pwm0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi0 { + compatible = "nordic,nrf-spi"; + /* Cannot be used together with i2c0. */ + /* status = "okay"; */ + pinctrl-0 = <&spi0_default>; + pinctrl-1 = <&spi0_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi1 { + compatible = "nordic,nrf-spi"; + status = "okay"; + pinctrl-0 = <&spi1_default>; + pinctrl-1 = <&spi1_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&spi2 { + compatible = "nordic,nrf-spi"; + status = "disabled"; + pinctrl-0 = <&spi2_default>; + pinctrl-1 = <&spi2_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&qspi { + status = "okay"; + pinctrl-0 = <&qspi_default>; + pinctrl-1 = <&qspi_sleep>; + pinctrl-names = "default", "sleep"; + mx25r64: mx25r6435f@0 { + compatible = "nordic,qspi-nor"; + reg = <0>; + /* MX25R64 supports only pp and pp4io */ + writeoc = "pp4io"; + /* MX25R64 supports all readoc options */ + readoc = "read4io"; + sck-frequency = <8000000>; + jedec-id = [c2 28 17]; + sfdp-bfp = [ + e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb + ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 + 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 + 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff + ]; + size = <67108864>; + has-dpd; + t-enter-dpd = <10000>; + t-exit-dpd = <35000>; + }; +}; + +arduino_spi: &spi3 { + status = "okay"; + cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ + pinctrl-0 = <&spi3_default>; + pinctrl-1 = <&spi3_sleep>; + pinctrl-names = "default", "sleep"; +}; + +&ieee802154 { + status = "okay"; +}; + +zephyr_udc0: &usbd { + compatible = "nordic,nrf-usbd"; + status = "okay"; +}; diff --git a/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840.yaml b/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840.yaml new file mode 100644 index 000000000..74b077dce --- /dev/null +++ b/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840.yaml @@ -0,0 +1,28 @@ +identifier: pca10056/nrf52840 +name: nRF52840-DK-NRF52840 +type: mcu +arch: arm +ram: 256 +flash: 1024 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - adc + - arduino_gpio + - arduino_i2c + - arduino_serial + - arduino_spi + - ble + - counter + - gpio + - i2c + - i2s + - pwm + - spi + - usb_device + - usbd + - watchdog + - netif:openthread +vendor: nordic -- cgit v1.3.1 From 1003aba69066b87db67b0d90318aa79630afb338 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 25 Jan 2025 12:39:08 +0700 Subject: use board alias for pca10056 --- .github/workflows/build.yml | 4 +- hw/bsp/family_support.cmake | 16 +- hw/bsp/nrf/boards/pca10056/board_aliases.cmake | 1 - hw/bsp/nrf/boards/pca10056/zephyr/Kconfig.pca10056 | 5 - hw/bsp/nrf/boards/pca10056/zephyr/board.yml | 6 - .../pca10056/zephyr/pca10056_nrf52840-pinctrl.dtsi | 187 -------------- .../boards/pca10056/zephyr/pca10056_nrf52840.dts | 278 --------------------- .../boards/pca10056/zephyr/pca10056_nrf52840.yaml | 28 --- hw/bsp/nrf/family.cmake | 4 + hw/bsp/zephyr_board_aliases.cmake | 1 + 10 files changed, 16 insertions(+), 514 deletions(-) delete mode 100644 hw/bsp/nrf/boards/pca10056/board_aliases.cmake delete mode 100644 hw/bsp/nrf/boards/pca10056/zephyr/Kconfig.pca10056 delete mode 100644 hw/bsp/nrf/boards/pca10056/zephyr/board.yml delete mode 100644 hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840-pinctrl.dtsi delete mode 100644 hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840.dts delete mode 100644 hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840.yaml create mode 100644 hw/bsp/zephyr_board_aliases.cmake (limited to 'hw') diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 90bc10883..cd5619a44 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -156,5 +156,5 @@ jobs: - name: Build run: | - west -v build -b pca10056 -d examples/device/cdc_msc/build examples/device/cdc_msc -- -DRTOS=zephyr - west -v build -b pca10056 -d examples/device/msc_dual_lun/build examples/device/msc_dual_lun -- -DRTOS=zephyr + west build -b pca10056 -d examples/device/cdc_msc/build examples/device/cdc_msc -- -DRTOS=zephyr + west build -b pca10056 -d examples/device/msc_dual_lun/build examples/device/msc_dual_lun -- -DRTOS=zephyr diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 1725f0de6..ccf07f21f 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -79,12 +79,6 @@ if (NOT NO_WARN_RWX_SEGMENTS_SUPPORTED) set(NO_WARN_RWX_SEGMENTS_SUPPORTED 1) endif() -if (RTOS STREQUAL zephyr) - set(BOARD_ROOT ${TOP}/hw/bsp/${FAMILY}) - cmake_print_variables(BOARD_ROOT BOARD) - find_package(Zephyr REQUIRED HINTS ${TOP}/zephyr) -endif () - #------------------------------------------------------------- # Functions #------------------------------------------------------------- @@ -604,7 +598,6 @@ function(family_flash_msp430flasher TARGET) ) endfunction() - function(family_flash_uniflash TARGET) if (NOT DEFINED DSLITE) set(DSLITE dslite.sh) @@ -637,3 +630,12 @@ endif () # save it in case of re-inclusion set(FAMILY_MCUS ${FAMILY_MCUS} CACHE INTERNAL "") + +#---------------------------------- +# Zephyr +#---------------------------------- +if (RTOS STREQUAL zephyr) + set(BOARD_ROOT ${TOP}/hw/bsp/${FAMILY}) + set(ZEPHYR_BOARD_ALIASES ${CMAKE_CURRENT_LIST_DIR}/zephyr_board_aliases.cmake) + find_package(Zephyr REQUIRED HINTS ${TOP}/zephyr) +endif () diff --git a/hw/bsp/nrf/boards/pca10056/board_aliases.cmake b/hw/bsp/nrf/boards/pca10056/board_aliases.cmake deleted file mode 100644 index 91ffc3a39..000000000 --- a/hw/bsp/nrf/boards/pca10056/board_aliases.cmake +++ /dev/null @@ -1 +0,0 @@ -set(pca10056_BOARD_ALIAS nrf52840dk/nrf52840) diff --git a/hw/bsp/nrf/boards/pca10056/zephyr/Kconfig.pca10056 b/hw/bsp/nrf/boards/pca10056/zephyr/Kconfig.pca10056 deleted file mode 100644 index a4d9619b3..000000000 --- a/hw/bsp/nrf/boards/pca10056/zephyr/Kconfig.pca10056 +++ /dev/null @@ -1,5 +0,0 @@ -# Copyright (c) 2022 Zephyr Project members and individual contributors -# SPDX-License-Identifier: Apache-2.0 - -config BOARD_PCA10056 - select SOC_NRF52840_QIAA diff --git a/hw/bsp/nrf/boards/pca10056/zephyr/board.yml b/hw/bsp/nrf/boards/pca10056/zephyr/board.yml deleted file mode 100644 index e45a33365..000000000 --- a/hw/bsp/nrf/boards/pca10056/zephyr/board.yml +++ /dev/null @@ -1,6 +0,0 @@ -board: - name: pca10056 - full_name: nRF52840 DK - vendor: nordic - socs: - - name: nrf52840 diff --git a/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840-pinctrl.dtsi b/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840-pinctrl.dtsi deleted file mode 100644 index 779d0d518..000000000 --- a/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840-pinctrl.dtsi +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2022 Nordic Semiconductor - * SPDX-License-Identifier: Apache-2.0 - */ - -&pinctrl { - uart0_default: uart0_default { - group1 { - psels = , - ; - }; - group2 { - psels = , - ; - bias-pull-up; - }; - }; - - uart0_sleep: uart0_sleep { - group1 { - psels = , - , - , - ; - low-power-enable; - }; - }; - - uart1_default: uart1_default { - group1 { - psels = ; - bias-pull-up; - }; - group2 { - psels = ; - }; - }; - - uart1_sleep: uart1_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; - - i2c0_default: i2c0_default { - group1 { - psels = , - ; - }; - }; - - i2c0_sleep: i2c0_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; - - i2c1_default: i2c1_default { - group1 { - psels = , - ; - }; - }; - - i2c1_sleep: i2c1_sleep { - group1 { - psels = , - ; - low-power-enable; - }; - }; - - pwm0_default: pwm0_default { - group1 { - psels = ; - nordic,invert; - }; - }; - - pwm0_sleep: pwm0_sleep { - group1 { - psels = ; - low-power-enable; - }; - }; - - spi0_default: spi0_default { - group1 { - psels = , - , - ; - }; - }; - - spi0_sleep: spi0_sleep { - group1 { - psels = , - , - ; - low-power-enable; - }; - }; - - spi1_default: spi1_default { - group1 { - psels = , - , - ; - }; - }; - - spi1_sleep: spi1_sleep { - group1 { - psels = , - , - ; - low-power-enable; - }; - }; - - spi2_default: spi2_default { - group1 { - psels = , - , - ; - }; - }; - - spi2_sleep: spi2_sleep { - group1 { - psels = , - , - ; - low-power-enable; - }; - }; - - qspi_default: qspi_default { - group1 { - psels = , - , - , - , - , - ; - nordic,drive-mode = ; - }; - }; - - qspi_sleep: qspi_sleep { - group1 { - psels = , - , - , - , - ; - low-power-enable; - }; - group2 { - psels = ; - low-power-enable; - bias-pull-up; - }; - }; - - spi3_default: spi3_default { - group1 { - psels = , - , - ; - }; - }; - - spi3_sleep: spi3_sleep { - group1 { - psels = , - , - ; - low-power-enable; - }; - }; - -}; diff --git a/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840.dts b/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840.dts deleted file mode 100644 index d7c9266d2..000000000 --- a/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840.dts +++ /dev/null @@ -1,278 +0,0 @@ -/* - * Copyright (c) 2017 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -/dts-v1/; -#include -#include -#include "pca10056_nrf52840-pinctrl.dtsi" -#include - -/ { - model = "Nordic nRF52840 DK NRF52840"; - compatible = "nordic,nrf52840-dk-nrf52840"; - - chosen { - zephyr,console = &uart0; - zephyr,shell-uart = &uart0; - zephyr,uart-mcumgr = &uart0; - zephyr,bt-mon-uart = &uart0; - zephyr,bt-c2h-uart = &uart0; - zephyr,ieee802154 = &ieee802154; - }; - - leds { - compatible = "gpio-leds"; - led0: led_0 { - gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; - label = "Green LED 0"; - }; - led1: led_1 { - gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; - label = "Green LED 1"; - }; - led2: led_2 { - gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; - label = "Green LED 2"; - }; - led3: led_3 { - gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; - label = "Green LED 3"; - }; - }; - - pwmleds { - compatible = "pwm-leds"; - pwm_led0: pwm_led_0 { - pwms = <&pwm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>; - }; - }; - - buttons { - compatible = "gpio-keys"; - button0: button_0 { - gpios = <&gpio0 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button switch 0"; - zephyr,code = ; - }; - button1: button_1 { - gpios = <&gpio0 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button switch 1"; - zephyr,code = ; - }; - button2: button_2 { - gpios = <&gpio0 24 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button switch 2"; - zephyr,code = ; - }; - button3: button_3 { - gpios = <&gpio0 25 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; - label = "Push button switch 3"; - zephyr,code = ; - }; - }; - - arduino_header: connector { - compatible = "arduino-header-r3"; - #gpio-cells = <2>; - gpio-map-mask = <0xffffffff 0xffffffc0>; - gpio-map-pass-thru = <0 0x3f>; - gpio-map = <0 0 &gpio0 3 0>, /* A0 */ - <1 0 &gpio0 4 0>, /* A1 */ - <2 0 &gpio0 28 0>, /* A2 */ - <3 0 &gpio0 29 0>, /* A3 */ - <4 0 &gpio0 30 0>, /* A4 */ - <5 0 &gpio0 31 0>, /* A5 */ - <6 0 &gpio1 1 0>, /* D0 */ - <7 0 &gpio1 2 0>, /* D1 */ - <8 0 &gpio1 3 0>, /* D2 */ - <9 0 &gpio1 4 0>, /* D3 */ - <10 0 &gpio1 5 0>, /* D4 */ - <11 0 &gpio1 6 0>, /* D5 */ - <12 0 &gpio1 7 0>, /* D6 */ - <13 0 &gpio1 8 0>, /* D7 */ - <14 0 &gpio1 10 0>, /* D8 */ - <15 0 &gpio1 11 0>, /* D9 */ - <16 0 &gpio1 12 0>, /* D10 */ - <17 0 &gpio1 13 0>, /* D11 */ - <18 0 &gpio1 14 0>, /* D12 */ - <19 0 &gpio1 15 0>, /* D13 */ - <20 0 &gpio0 26 0>, /* D14 */ - <21 0 &gpio0 27 0>; /* D15 */ - }; - - arduino_adc: analog-connector { - compatible = "arduino,uno-adc"; - #io-channel-cells = <1>; - io-channel-map = <0 &adc 1>, /* A0 = P0.3 = AIN1 */ - <1 &adc 2>, /* A1 = P0.4 = AIN2 */ - <2 &adc 4>, /* A2 = P0.28 = AIN4 */ - <3 &adc 5>, /* A3 = P0.29 = AIN5 */ - <4 &adc 6>, /* A4 = P0.30 = AIN6 */ - <5 &adc 7>; /* A5 = P0.31 = AIN7 */ - }; - - /* These aliases are provided for compatibility with samples */ - aliases { - led0 = &led0; - led1 = &led1; - led2 = &led2; - led3 = &led3; - pwm-led0 = &pwm_led0; - sw0 = &button0; - sw1 = &button1; - sw2 = &button2; - sw3 = &button3; - bootloader-led0 = &led0; - mcuboot-button0 = &button0; - mcuboot-led0 = &led0; - watchdog0 = &wdt0; - }; -}; - -®0 { - status = "okay"; -}; - -®1 { - regulator-initial-mode = ; -}; - -&adc { - status = "okay"; -}; - -&uicr { - gpio-as-nreset; -}; - -&gpiote { - status = "okay"; -}; - -&gpio0 { - status = "okay"; - gpio-reserved-ranges = <0 2>, <6 1>, <8 3>, <17 7>; - gpio-line-names = "XL1", "XL2", "AREF", "A0", "A1", "RTS", "TXD", - "CTS", "RXD", "NFC1", "NFC2", "BUTTON1", "BUTTON2", "LED1", - "LED2", "LED3", "LED4", "QSPI CS", "RESET", "QSPI CLK", - "QSPI DIO0", "QSPI DIO1", "QSPI DIO2", "QSPI DIO3","BUTTON3", - "BUTTON4", "SDA", "SCL", "A2", "A3", "A4", "A5"; -}; - -&gpio1 { - status = "okay"; - gpio-line-names = "", "D0", "D1", "D2", "D3", "D4", "D5", "D6", - "D7", "", "D8", "D9", "D10", "D11", "D12", "D13"; -}; - -&uart0 { - compatible = "nordic,nrf-uarte"; - status = "okay"; - current-speed = <115200>; - pinctrl-0 = <&uart0_default>; - pinctrl-1 = <&uart0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -arduino_serial: &uart1 { - current-speed = <115200>; - pinctrl-0 = <&uart1_default>; - pinctrl-1 = <&uart1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -arduino_i2c: &i2c0 { - compatible = "nordic,nrf-twi"; - status = "okay"; - pinctrl-0 = <&i2c0_default>; - pinctrl-1 = <&i2c0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&i2c1 { - compatible = "nordic,nrf-twi"; - /* Cannot be used together with spi1. */ - /* status = "okay"; */ - pinctrl-0 = <&i2c1_default>; - pinctrl-1 = <&i2c1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&pwm0 { - status = "okay"; - pinctrl-0 = <&pwm0_default>; - pinctrl-1 = <&pwm0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&spi0 { - compatible = "nordic,nrf-spi"; - /* Cannot be used together with i2c0. */ - /* status = "okay"; */ - pinctrl-0 = <&spi0_default>; - pinctrl-1 = <&spi0_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&spi1 { - compatible = "nordic,nrf-spi"; - status = "okay"; - pinctrl-0 = <&spi1_default>; - pinctrl-1 = <&spi1_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&spi2 { - compatible = "nordic,nrf-spi"; - status = "disabled"; - pinctrl-0 = <&spi2_default>; - pinctrl-1 = <&spi2_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&qspi { - status = "okay"; - pinctrl-0 = <&qspi_default>; - pinctrl-1 = <&qspi_sleep>; - pinctrl-names = "default", "sleep"; - mx25r64: mx25r6435f@0 { - compatible = "nordic,qspi-nor"; - reg = <0>; - /* MX25R64 supports only pp and pp4io */ - writeoc = "pp4io"; - /* MX25R64 supports all readoc options */ - readoc = "read4io"; - sck-frequency = <8000000>; - jedec-id = [c2 28 17]; - sfdp-bfp = [ - e5 20 f1 ff ff ff ff 03 44 eb 08 6b 08 3b 04 bb - ee ff ff ff ff ff 00 ff ff ff 00 ff 0c 20 0f 52 - 10 d8 00 ff 23 72 f5 00 82 ed 04 cc 44 83 68 44 - 30 b0 30 b0 f7 c4 d5 5c 00 be 29 ff f0 d0 ff ff - ]; - size = <67108864>; - has-dpd; - t-enter-dpd = <10000>; - t-exit-dpd = <35000>; - }; -}; - -arduino_spi: &spi3 { - status = "okay"; - cs-gpios = <&arduino_header 16 GPIO_ACTIVE_LOW>; /* D10 */ - pinctrl-0 = <&spi3_default>; - pinctrl-1 = <&spi3_sleep>; - pinctrl-names = "default", "sleep"; -}; - -&ieee802154 { - status = "okay"; -}; - -zephyr_udc0: &usbd { - compatible = "nordic,nrf-usbd"; - status = "okay"; -}; diff --git a/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840.yaml b/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840.yaml deleted file mode 100644 index 74b077dce..000000000 --- a/hw/bsp/nrf/boards/pca10056/zephyr/pca10056_nrf52840.yaml +++ /dev/null @@ -1,28 +0,0 @@ -identifier: pca10056/nrf52840 -name: nRF52840-DK-NRF52840 -type: mcu -arch: arm -ram: 256 -flash: 1024 -toolchain: - - zephyr - - gnuarmemb - - xtools -supported: - - adc - - arduino_gpio - - arduino_i2c - - arduino_serial - - arduino_spi - - ble - - counter - - gpio - - i2c - - i2s - - pwm - - spi - - usb_device - - usbd - - watchdog - - netif:openthread -vendor: nordic diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 2d2a12e7e..f4c9bd63f 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -130,6 +130,10 @@ function(family_configure_example TARGET RTOS) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} ) + if (RTOS STREQUAL zephyr AND DEFINED BOARD_ALIAS AND NOT BOARD STREQUAL BOARD_ALIAS) + target_include_directories(${TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD_ALIAS}) + endif () + # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_NRF5X) diff --git a/hw/bsp/zephyr_board_aliases.cmake b/hw/bsp/zephyr_board_aliases.cmake new file mode 100644 index 000000000..91ffc3a39 --- /dev/null +++ b/hw/bsp/zephyr_board_aliases.cmake @@ -0,0 +1 @@ +set(pca10056_BOARD_ALIAS nrf52840dk/nrf52840) -- cgit v1.3.1 From dc514c6230975eceb359644d4b60a1a99a5218bf Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 25 Jan 2025 15:12:57 +0700 Subject: use board alias for pca10056 --- .../build_system/cmake/toolchain/arm_gcc.cmake | 36 +++++++++++----------- hw/bsp/family_support.cmake | 19 ++++++------ hw/bsp/nrf/family.cmake | 10 +++--- 3 files changed, 34 insertions(+), 31 deletions(-) (limited to 'hw') diff --git a/examples/build_system/cmake/toolchain/arm_gcc.cmake b/examples/build_system/cmake/toolchain/arm_gcc.cmake index 4cef07ff5..6a660e259 100644 --- a/examples/build_system/cmake/toolchain/arm_gcc.cmake +++ b/examples/build_system/cmake/toolchain/arm_gcc.cmake @@ -1,25 +1,25 @@ if (RTOS STREQUAL zephyr) + return() +endif () -else () - if (NOT DEFINED CMAKE_C_COMPILER) - set(CMAKE_C_COMPILER "arm-none-eabi-gcc") - endif () +if (NOT DEFINED CMAKE_C_COMPILER) + set(CMAKE_C_COMPILER "arm-none-eabi-gcc") +endif () - if (NOT DEFINED CMAKE_CXX_COMPILER) - set(CMAKE_CXX_COMPILER "arm-none-eabi-g++") - endif () +if (NOT DEFINED CMAKE_CXX_COMPILER) + set(CMAKE_CXX_COMPILER "arm-none-eabi-g++") +endif () - set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) - find_program(CMAKE_SIZE arm-none-eabi-size) - find_program(CMAKE_OBJCOPY arm-none-eabi-objcopy) - find_program(CMAKE_OBJDUMP arm-none-eabi-objdump) +set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER}) +find_program(CMAKE_SIZE arm-none-eabi-size) +find_program(CMAKE_OBJCOPY arm-none-eabi-objcopy) +find_program(CMAKE_OBJDUMP arm-none-eabi-objdump) - include(${CMAKE_CURRENT_LIST_DIR}/common.cmake) +include(${CMAKE_CURRENT_LIST_DIR}/common.cmake) - get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE) - if (IS_IN_TRY_COMPILE) - set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib") - set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib") - cmake_print_variables(CMAKE_C_LINK_FLAGS) - endif () +get_property(IS_IN_TRY_COMPILE GLOBAL PROPERTY IN_TRY_COMPILE) +if (IS_IN_TRY_COMPILE) + set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -nostdlib") + set(CMAKE_CXX_LINK_FLAGS "${CMAKE_CXX_LINK_FLAGS} -nostdlib") + cmake_print_variables(CMAKE_C_LINK_FLAGS) endif () diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index ccf07f21f..f9ce47173 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -59,6 +59,7 @@ if (NOT DEFINED FAMILY) # replace / with ; so that we can get the first element as FAMILY string(REPLACE "/" ";" BOARD_PATH ${BOARD_PATH}) list(GET BOARD_PATH 0 FAMILY) + set(FAMILY ${FAMILY} CACHE STRING "Board family") endif () if (NOT EXISTS ${CMAKE_CURRENT_LIST_DIR}/${FAMILY}/family.cmake) @@ -79,6 +80,15 @@ if (NOT NO_WARN_RWX_SEGMENTS_SUPPORTED) set(NO_WARN_RWX_SEGMENTS_SUPPORTED 1) endif() +#---------------------------------- +# Zephyr +#---------------------------------- +if (RTOS STREQUAL zephyr) + set(BOARD_ROOT ${TOP}/hw/bsp/${FAMILY}) + set(ZEPHYR_BOARD_ALIASES ${CMAKE_CURRENT_LIST_DIR}/zephyr_board_aliases.cmake) + find_package(Zephyr REQUIRED HINTS ${TOP}/zephyr) +endif () + #------------------------------------------------------------- # Functions #------------------------------------------------------------- @@ -630,12 +640,3 @@ endif () # save it in case of re-inclusion set(FAMILY_MCUS ${FAMILY_MCUS} CACHE INTERNAL "") - -#---------------------------------- -# Zephyr -#---------------------------------- -if (RTOS STREQUAL zephyr) - set(BOARD_ROOT ${TOP}/hw/bsp/${FAMILY}) - set(ZEPHYR_BOARD_ALIASES ${CMAKE_CURRENT_LIST_DIR}/zephyr_board_aliases.cmake) - find_package(Zephyr REQUIRED HINTS ${TOP}/zephyr) -endif () diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index f4c9bd63f..abfab1609 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -3,8 +3,12 @@ include_guard() set(NRFX_PATH ${TOP}/hw/mcu/nordic/nrfx) set(CMSIS_DIR ${TOP}/lib/CMSIS_5) -# include board specific -include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) +# include board specific, for zephyr BOARD_ALIAS may be used instead +if (EXISTS ${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) +else () + include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD_ALIAS}/board.cmake) +endif () # toolchain set up if (MCU_VARIANT STREQUAL "nrf5340_application") @@ -19,7 +23,6 @@ set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOL set(FAMILY_MCUS NRF5X CACHE INTERNAL "") - #------------------------------------ # BOARD_TARGET #------------------------------------ @@ -134,7 +137,6 @@ function(family_configure_example TARGET RTOS) target_include_directories(${TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD_ALIAS}) endif () - # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_NRF5X) target_sources(${TARGET} PRIVATE -- cgit v1.3.1 From 6b3a5957c2e84a093854eaf6afea352d67324136 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 25 Jan 2025 16:08:40 +0700 Subject: cmake remove EXAMPLE-tinyusb target as library --- .github/workflows/build.yml | 6 +++--- hw/bsp/broadcom_32bit/family.cmake | 7 +++---- hw/bsp/broadcom_64bit/family.cmake | 7 +++---- hw/bsp/ch32v10x/family.cmake | 7 +++---- hw/bsp/ch32v20x/family.cmake | 7 +++---- hw/bsp/ch32v307/family.cmake | 7 +++---- hw/bsp/da1469x/family.cmake | 7 +++---- hw/bsp/f1c100s/family.cmake | 7 +++---- hw/bsp/fomu/family.cmake | 7 +++---- hw/bsp/gd32vf103/family.cmake | 7 +++---- hw/bsp/imxrt/family.cmake | 7 +++---- hw/bsp/kinetis_k/family.cmake | 7 +++---- hw/bsp/kinetis_k32l2/family.cmake | 7 +++---- hw/bsp/kinetis_kl/family.cmake | 7 +++---- hw/bsp/lpc11/family.cmake | 7 +++---- hw/bsp/lpc13/family.cmake | 7 +++---- hw/bsp/lpc15/family.cmake | 7 +++---- hw/bsp/lpc17/family.cmake | 7 +++---- hw/bsp/lpc18/family.cmake | 7 +++---- hw/bsp/lpc40/family.cmake | 7 +++---- hw/bsp/lpc43/family.cmake | 7 +++---- hw/bsp/lpc51/family.cmake | 7 +++---- hw/bsp/lpc54/family.cmake | 7 +++---- hw/bsp/lpc55/family.cmake | 7 +++---- hw/bsp/max32650/family.cmake | 9 ++++----- hw/bsp/max32666/family.cmake | 9 ++++----- hw/bsp/max32690/family.cmake | 9 ++++----- hw/bsp/max78002/family.cmake | 9 ++++----- hw/bsp/mcx/family.cmake | 7 +++---- hw/bsp/mm32/family.cmake | 7 +++---- hw/bsp/msp430/family.cmake | 6 ++---- hw/bsp/msp432e4/family.cmake | 7 +++---- hw/bsp/nrf/family.cmake | 5 ++--- hw/bsp/ra/family.cmake | 7 +++---- hw/bsp/samd11/family.cmake | 7 +++---- hw/bsp/samg/family.cmake | 7 +++---- hw/bsp/saml2x/family.cmake | 7 +++---- hw/bsp/stm32c0/family.cmake | 7 +++---- hw/bsp/stm32f0/family.cmake | 7 +++---- hw/bsp/stm32f1/family.cmake | 7 +++---- hw/bsp/stm32f2/family.cmake | 7 +++---- hw/bsp/stm32f3/family.cmake | 7 +++---- hw/bsp/stm32f4/family.cmake | 7 +++---- hw/bsp/stm32f7/family.cmake | 7 +++---- hw/bsp/stm32g0/family.cmake | 7 +++---- hw/bsp/stm32g4/family.cmake | 7 +++---- hw/bsp/stm32h5/family.cmake | 7 +++---- hw/bsp/stm32h7/family.cmake | 7 +++---- hw/bsp/stm32l0/family.cmake | 7 +++---- hw/bsp/stm32l4/family.cmake | 7 +++---- hw/bsp/stm32u5/family.cmake | 7 +++---- hw/bsp/stm32wb/family.cmake | 7 +++---- hw/bsp/tm4c/family.cmake | 7 +++---- hw/bsp/xmc4000/family.cmake | 7 +++---- 54 files changed, 164 insertions(+), 218 deletions(-) (limited to 'hw') diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index cd5619a44..355b6b5c4 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -59,7 +59,7 @@ jobs: toolchain: # - 'arm-clang' is built by circle-ci in PR - 'aarch64-gcc' -# - 'arm-gcc' + - 'arm-gcc' - 'msp430-gcc' - 'riscv-gcc' with: @@ -72,7 +72,7 @@ jobs: # Build Make (built by circle-ci in PR, only build on push here) # --------------------------------------- make: - if: github.event_name == 'push' && false + if: github.event_name == 'push' needs: set-matrix uses: ./.github/workflows/build_util.yml strategy: @@ -113,7 +113,7 @@ jobs: # Build IAR on HFP self-hosted # --------------------------------------- arm-iar: - if: github.repository_owner == 'hathach' && github.event_name == 'push' && false + if: github.repository_owner == 'hathach' && github.event_name == 'push' needs: set-matrix runs-on: [self-hosted, Linux, X64, hifiphile] env: diff --git a/hw/bsp/broadcom_32bit/family.cmake b/hw/bsp/broadcom_32bit/family.cmake index 18227f702..5e57d8b1e 100644 --- a/hw/bsp/broadcom_32bit/family.cmake +++ b/hw/bsp/broadcom_32bit/family.cmake @@ -95,15 +95,14 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_BCM2835) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/broadcom_64bit/family.cmake b/hw/bsp/broadcom_64bit/family.cmake index f5245be36..1a088c2c0 100644 --- a/hw/bsp/broadcom_64bit/family.cmake +++ b/hw/bsp/broadcom_64bit/family.cmake @@ -102,15 +102,14 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_BCM${BCM_VERSION}) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/ch32v10x/family.cmake b/hw/bsp/ch32v10x/family.cmake index 9b395e92d..a73898050 100644 --- a/hw/bsp/ch32v10x/family.cmake +++ b/hw/bsp/ch32v10x/family.cmake @@ -100,13 +100,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_CH32V103) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/wch/dcd_ch32_usbfs.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/ch32v20x/family.cmake b/hw/bsp/ch32v20x/family.cmake index 9748184c2..a5976e0ea 100644 --- a/hw/bsp/ch32v20x/family.cmake +++ b/hw/bsp/ch32v20x/family.cmake @@ -125,14 +125,13 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_CH32V20X) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/wch/dcd_ch32_usbfs.c ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/ch32v307/family.cmake b/hw/bsp/ch32v307/family.cmake index e4b84198c..446e850c5 100644 --- a/hw/bsp/ch32v307/family.cmake +++ b/hw/bsp/ch32v307/family.cmake @@ -114,14 +114,13 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_CH32V307) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/wch/dcd_ch32_usbhs.c ${TOP}/src/portable/wch/dcd_ch32_usbfs.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/da1469x/family.cmake b/hw/bsp/da1469x/family.cmake index 7bb6f5d86..20d6cbc44 100644 --- a/hw/bsp/da1469x/family.cmake +++ b/hw/bsp/da1469x/family.cmake @@ -127,13 +127,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_DA1469X) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/dialog/da146xx/dcd_da146xx.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/f1c100s/family.cmake b/hw/bsp/f1c100s/family.cmake index 0565f7545..211c6645c 100644 --- a/hw/bsp/f1c100s/family.cmake +++ b/hw/bsp/f1c100s/family.cmake @@ -101,13 +101,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_F1C100S) - target_sources(${TARGET}-tinyusb PRIVATE + target_sources(${TARGET} PRIVATE ${TOP}/src/portable/sunxi/dcd_sunxi_musb.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/fomu/family.cmake b/hw/bsp/fomu/family.cmake index d8141a7b3..639373695 100644 --- a/hw/bsp/fomu/family.cmake +++ b/hw/bsp/fomu/family.cmake @@ -78,13 +78,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_VALENTYUSB_EPTRI) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/valentyusb/eptri/dcd_eptri.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/gd32vf103/family.cmake b/hw/bsp/gd32vf103/family.cmake index 5b145692f..a47871b38 100644 --- a/hw/bsp/gd32vf103/family.cmake +++ b/hw/bsp/gd32vf103/family.cmake @@ -106,15 +106,14 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_GD32VF103) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index 8ec96bf33..f08ccb3e5 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -139,15 +139,14 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MIMXRT1XXX) - target_sources(${TARGET}-tinyusb PRIVATE + target_sources(${TARGET} PRIVATE ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c ${TOP}/src/portable/ehci/ehci.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/kinetis_k/family.cmake b/hw/bsp/kinetis_k/family.cmake index e9993ed7b..ce91777c9 100644 --- a/hw/bsp/kinetis_k/family.cmake +++ b/hw/bsp/kinetis_k/family.cmake @@ -98,14 +98,13 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_K) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c ${TOP}/src/portable/nxp/khci/hcd_khci.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/kinetis_k32l2/family.cmake b/hw/bsp/kinetis_k32l2/family.cmake index a76b05745..946614a03 100644 --- a/hw/bsp/kinetis_k32l2/family.cmake +++ b/hw/bsp/kinetis_k32l2/family.cmake @@ -93,14 +93,13 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_K32L) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/khci/dcd_khci.c ${TOP}/src/portable/nxp/khci/hcd_khci.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_flash_jlink(${TARGET}) diff --git a/hw/bsp/kinetis_kl/family.cmake b/hw/bsp/kinetis_kl/family.cmake index c0ca0e77a..51a646258 100644 --- a/hw/bsp/kinetis_kl/family.cmake +++ b/hw/bsp/kinetis_kl/family.cmake @@ -97,14 +97,13 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_KINETIS_KL) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/chipidea/ci_fs/dcd_ci_fs.c ${TOP}/src/portable/nxp/khci/hcd_khci.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/lpc11/family.cmake b/hw/bsp/lpc11/family.cmake index e11268bb2..a9febfc7f 100644 --- a/hw/bsp/lpc11/family.cmake +++ b/hw/bsp/lpc11/family.cmake @@ -91,13 +91,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_LPC11UXX) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/lpc13/family.cmake b/hw/bsp/lpc13/family.cmake index 500ddb3b0..e3c0b18c7 100644 --- a/hw/bsp/lpc13/family.cmake +++ b/hw/bsp/lpc13/family.cmake @@ -88,13 +88,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_LPC13XX) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/lpc15/family.cmake b/hw/bsp/lpc15/family.cmake index daad44bc0..761c5a619 100644 --- a/hw/bsp/lpc15/family.cmake +++ b/hw/bsp/lpc15/family.cmake @@ -90,13 +90,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_LPC15XX) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/lpc17/family.cmake b/hw/bsp/lpc17/family.cmake index 7e7f036de..771a0f405 100644 --- a/hw/bsp/lpc17/family.cmake +++ b/hw/bsp/lpc17/family.cmake @@ -87,15 +87,14 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_LPC175X_6X) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/lpc17_40/dcd_lpc17_40.c ${TOP}/src/portable/nxp/lpc17_40/hcd_lpc17_40.c ${TOP}/src/portable/ohci/ohci.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/lpc18/family.cmake b/hw/bsp/lpc18/family.cmake index 5542496f0..6af1149bf 100644 --- a/hw/bsp/lpc18/family.cmake +++ b/hw/bsp/lpc18/family.cmake @@ -85,15 +85,14 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_LPC18XX) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c ${TOP}/src/portable/ehci/ehci.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/lpc40/family.cmake b/hw/bsp/lpc40/family.cmake index afbf6a22f..3a680eae6 100644 --- a/hw/bsp/lpc40/family.cmake +++ b/hw/bsp/lpc40/family.cmake @@ -88,15 +88,14 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_LPC40XX) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/lpc17_40/dcd_lpc17_40.c ${TOP}/src/portable/nxp/lpc17_40/hcd_lpc17_40.c ${TOP}/src/portable/ohci/ohci.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/lpc43/family.cmake b/hw/bsp/lpc43/family.cmake index 620b4baa2..9d993a698 100644 --- a/hw/bsp/lpc43/family.cmake +++ b/hw/bsp/lpc43/family.cmake @@ -93,15 +93,14 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_LPC43XX) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/chipidea/ci_hs/dcd_ci_hs.c ${TOP}/src/portable/chipidea/ci_hs/hcd_ci_hs.c ${TOP}/src/portable/ehci/ehci.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/lpc51/family.cmake b/hw/bsp/lpc51/family.cmake index be3e9f02d..2146c29f7 100644 --- a/hw/bsp/lpc51/family.cmake +++ b/hw/bsp/lpc51/family.cmake @@ -107,13 +107,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_LPC51) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/lpc54/family.cmake b/hw/bsp/lpc54/family.cmake index af5ee823b..90497b9fb 100644 --- a/hw/bsp/lpc54/family.cmake +++ b/hw/bsp/lpc54/family.cmake @@ -140,13 +140,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_LPC54) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/lpc55/family.cmake b/hw/bsp/lpc55/family.cmake index 2d99daf21..cd1eb5f78 100644 --- a/hw/bsp/lpc55/family.cmake +++ b/hw/bsp/lpc55/family.cmake @@ -141,13 +141,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_LPC55) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake index d114e0948..b1d5dded7 100644 --- a/hw/bsp/max32650/family.cmake +++ b/hw/bsp/max32650/family.cmake @@ -131,20 +131,19 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MAX32650) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/mentor/musb/dcd_musb.c ) target_compile_options(${TARGET} PRIVATE -Wno-error=strict-prototypes ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) - target_compile_options(${TARGET}-tinyusb PRIVATE + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + target_compile_options(${TARGET} PRIVATE -Wno-error=strict-prototypes ) - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/max32666/family.cmake b/hw/bsp/max32666/family.cmake index a78e74670..49798729a 100644 --- a/hw/bsp/max32666/family.cmake +++ b/hw/bsp/max32666/family.cmake @@ -126,20 +126,19 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MAX32666) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/mentor/musb/dcd_musb.c ) target_compile_options(${TARGET} PRIVATE -Wno-error=strict-prototypes ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) - target_compile_options(${TARGET}-tinyusb PRIVATE + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + target_compile_options(${TARGET} PRIVATE -Wno-error=strict-prototypes ) - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake index d79403dee..0d544d9e6 100644 --- a/hw/bsp/max32690/family.cmake +++ b/hw/bsp/max32690/family.cmake @@ -131,20 +131,19 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MAX32690) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/mentor/musb/dcd_musb.c ) target_compile_options(${TARGET} PRIVATE -Wno-error=strict-prototypes ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) - target_compile_options(${TARGET}-tinyusb PRIVATE + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + target_compile_options(${TARGET} PRIVATE -Wno-error=strict-prototypes ) - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake index 7e65f58ed..ce0fcfa08 100644 --- a/hw/bsp/max78002/family.cmake +++ b/hw/bsp/max78002/family.cmake @@ -135,17 +135,16 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MAX78002) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/mentor/musb/dcd_musb.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) - target_compile_options(${TARGET}-tinyusb PRIVATE + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + target_compile_options(${TARGET} PRIVATE -Wno-error=strict-prototypes -Wno-error=redundant-decls ) - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/mcx/family.cmake b/hw/bsp/mcx/family.cmake index 8eed8f19b..413c1b372 100644 --- a/hw/bsp/mcx/family.cmake +++ b/hw/bsp/mcx/family.cmake @@ -115,14 +115,13 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_MCXA15) endif() - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC # TinyUSB: Port0 is chipidea FS, Port1 is chipidea HS ${TOP}/src/portable/chipidea/$ ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/mm32/family.cmake b/hw/bsp/mm32/family.cmake index eea1ae85e..0561a63a0 100644 --- a/hw/bsp/mm32/family.cmake +++ b/hw/bsp/mm32/family.cmake @@ -88,13 +88,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MM32F327X) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/msp430/family.cmake b/hw/bsp/msp430/family.cmake index 94e045ae5..ddd54b675 100644 --- a/hw/bsp/msp430/family.cmake +++ b/hw/bsp/msp430/family.cmake @@ -70,13 +70,11 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MSP430x5xx) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/msp432e4/family.cmake b/hw/bsp/msp432e4/family.cmake index b46af45fa..f6939ecfe 100644 --- a/hw/bsp/msp432e4/family.cmake +++ b/hw/bsp/msp432e4/family.cmake @@ -86,14 +86,13 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MSP432E4) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/mentor/musb/dcd_musb.c ${TOP}/src/portable/mentor/musb/hcd_musb.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index abfab1609..7d0a9f6de 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -4,9 +4,8 @@ set(NRFX_PATH ${TOP}/hw/mcu/nordic/nrfx) set(CMSIS_DIR ${TOP}/lib/CMSIS_5) # include board specific, for zephyr BOARD_ALIAS may be used instead -if (EXISTS ${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) - include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) -else () +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake OPTIONAL RESULT_VARIABLE board_cmake_included) +if (NOT board_cmake_included) include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD_ALIAS}/board.cmake) endif () diff --git a/hw/bsp/ra/family.cmake b/hw/bsp/ra/family.cmake index 8ae8e9b59..42a32631c 100644 --- a/hw/bsp/ra/family.cmake +++ b/hw/bsp/ra/family.cmake @@ -148,15 +148,14 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_RAXXX) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/renesas/rusb2/dcd_rusb2.c ${TOP}/src/portable/renesas/rusb2/hcd_rusb2.c ${TOP}/src/portable/renesas/rusb2/rusb2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_flash_jlink(${TARGET}) diff --git a/hw/bsp/samd11/family.cmake b/hw/bsp/samd11/family.cmake index 4a40ca063..965b1cfb5 100644 --- a/hw/bsp/samd11/family.cmake +++ b/hw/bsp/samd11/family.cmake @@ -101,13 +101,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_SAMD11) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/microchip/samd/dcd_samd.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/samg/family.cmake b/hw/bsp/samg/family.cmake index aef17d379..eb00c8c52 100644 --- a/hw/bsp/samg/family.cmake +++ b/hw/bsp/samg/family.cmake @@ -99,13 +99,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_SAMG) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/microchip/samg/dcd_samg.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/saml2x/family.cmake b/hw/bsp/saml2x/family.cmake index 37e282a18..49f2e3e75 100644 --- a/hw/bsp/saml2x/family.cmake +++ b/hw/bsp/saml2x/family.cmake @@ -101,13 +101,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_SAML22) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/microchip/samd/dcd_samd.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/stm32c0/family.cmake b/hw/bsp/stm32c0/family.cmake index ca6a93adf..c6a90fff6 100644 --- a/hw/bsp/stm32c0/family.cmake +++ b/hw/bsp/stm32c0/family.cmake @@ -103,14 +103,13 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_STM32C0) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ${TOP}/src/portable/st/typec/typec_stm32.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/stm32f0/family.cmake b/hw/bsp/stm32f0/family.cmake index c0da094d7..12c7b592c 100644 --- a/hw/bsp/stm32f0/family.cmake +++ b/hw/bsp/stm32f0/family.cmake @@ -101,13 +101,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_STM32F0) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/stm32f1/family.cmake b/hw/bsp/stm32f1/family.cmake index 4eba6df93..cbb9c3568 100644 --- a/hw/bsp/stm32f1/family.cmake +++ b/hw/bsp/stm32f1/family.cmake @@ -100,13 +100,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_STM32F1) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/stm32f2/family.cmake b/hw/bsp/stm32f2/family.cmake index 6a22d1550..dc6bc2885 100644 --- a/hw/bsp/stm32f2/family.cmake +++ b/hw/bsp/stm32f2/family.cmake @@ -100,15 +100,14 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_STM32F2) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/stm32f3/family.cmake b/hw/bsp/stm32f3/family.cmake index 053bbbacc..0ba2920d5 100644 --- a/hw/bsp/stm32f3/family.cmake +++ b/hw/bsp/stm32f3/family.cmake @@ -98,13 +98,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_STM32F3) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/stm32f4/family.cmake b/hw/bsp/stm32f4/family.cmake index 5f12eb8b2..db5736192 100644 --- a/hw/bsp/stm32f4/family.cmake +++ b/hw/bsp/stm32f4/family.cmake @@ -126,15 +126,14 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_STM32F4) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/stm32f7/family.cmake b/hw/bsp/stm32f7/family.cmake index 8cc18935d..1a3365332 100644 --- a/hw/bsp/stm32f7/family.cmake +++ b/hw/bsp/stm32f7/family.cmake @@ -128,15 +128,14 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_STM32F7) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/stm32g0/family.cmake b/hw/bsp/stm32g0/family.cmake index 2ab5719bc..4da26f27e 100644 --- a/hw/bsp/stm32g0/family.cmake +++ b/hw/bsp/stm32g0/family.cmake @@ -102,14 +102,13 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_STM32G0) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ${TOP}/src/portable/st/typec/typec_stm32.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/stm32g4/family.cmake b/hw/bsp/stm32g4/family.cmake index d51b3599a..5ec9926fe 100644 --- a/hw/bsp/stm32g4/family.cmake +++ b/hw/bsp/stm32g4/family.cmake @@ -98,14 +98,13 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_STM32G4) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ${TOP}/src/portable/st/typec/typec_stm32.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/stm32h5/family.cmake b/hw/bsp/stm32h5/family.cmake index 54392fe1a..1df6bcb90 100644 --- a/hw/bsp/stm32h5/family.cmake +++ b/hw/bsp/stm32h5/family.cmake @@ -102,14 +102,13 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_STM32H5) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ${TOP}/src/portable/st/typec/typec_stm32.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake index e50bbf4a2..b4f0bebbf 100644 --- a/hw/bsp/stm32h7/family.cmake +++ b/hw/bsp/stm32h7/family.cmake @@ -133,15 +133,14 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_STM32H7) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/stm32l0/family.cmake b/hw/bsp/stm32l0/family.cmake index 435c658ec..954bdb158 100644 --- a/hw/bsp/stm32l0/family.cmake +++ b/hw/bsp/stm32l0/family.cmake @@ -102,13 +102,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_STM32L0) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/stm32l4/family.cmake b/hw/bsp/stm32l4/family.cmake index 4d2ccf178..eebcff4f3 100644 --- a/hw/bsp/stm32l4/family.cmake +++ b/hw/bsp/stm32l4/family.cmake @@ -102,16 +102,15 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS}) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/stm32u5/family.cmake b/hw/bsp/stm32u5/family.cmake index 2cbe5cf38..7a5935961 100644 --- a/hw/bsp/stm32u5/family.cmake +++ b/hw/bsp/stm32u5/family.cmake @@ -102,17 +102,16 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_STM32U5) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c #${TOP}/src/portable/st/typec/typec_stm32.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/stm32wb/family.cmake b/hw/bsp/stm32wb/family.cmake index d6d841baa..0ea937257 100644 --- a/hw/bsp/stm32wb/family.cmake +++ b/hw/bsp/stm32wb/family.cmake @@ -105,13 +105,12 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS}) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/tm4c/family.cmake b/hw/bsp/tm4c/family.cmake index 833b6c5e4..e1cf94e96 100644 --- a/hw/bsp/tm4c/family.cmake +++ b/hw/bsp/tm4c/family.cmake @@ -80,14 +80,13 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_TM4C123) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/mentor/musb/dcd_musb.c ${TOP}/src/portable/mentor/musb/hcd_musb.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) diff --git a/hw/bsp/xmc4000/family.cmake b/hw/bsp/xmc4000/family.cmake index be72d349f..6edd72caf 100644 --- a/hw/bsp/xmc4000/family.cmake +++ b/hw/bsp/xmc4000/family.cmake @@ -84,15 +84,14 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_XMC4000) - target_sources(${TARGET}-tinyusb PUBLIC + target_sources(${TARGET} PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) - target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + - # Link dependencies - target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) # Flashing family_add_bin_hex(${TARGET}) -- cgit v1.3.1 From 8c7998b0e9783a8f44e544c08cb89a81dcf66b6f Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 25 Jan 2025 16:29:56 +0700 Subject: fix ci --- examples/device/board_test/src/main.c | 54 +++-------------------------------- hw/bsp/family_support.cmake | 46 ++++++++++++++--------------- hw/bsp/lpc11/family.c | 4 +++ hw/bsp/lpc11/family.cmake | 5 +++- hw/bsp/lpc18/family.c | 5 ++++ hw/bsp/lpc18/family.mk | 2 +- hw/bsp/lpc43/family.c | 5 ++++ hw/bsp/lpc43/family.cmake | 5 +++- hw/bsp/lpc43/family.mk | 1 - hw/bsp/nrf/family.mk | 1 + src/CMakeLists.txt | 32 --------------------- 11 files changed, 51 insertions(+), 109 deletions(-) (limited to 'hw') diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c index 321f6638a..2269d45f1 100644 --- a/examples/device/board_test/src/main.c +++ b/examples/device/board_test/src/main.c @@ -23,7 +23,6 @@ * */ -#if 1 #include #include #include @@ -52,7 +51,7 @@ int main(void) { // Blink and print every interval ms if (!(board_millis() - start_ms < interval_ms)) { - // board_uart_write(HELLO_STR, strlen(HELLO_STR)); + board_uart_write(HELLO_STR, strlen(HELLO_STR)); start_ms = board_millis(); @@ -61,57 +60,12 @@ int main(void) { } // echo - // uint8_t ch; - // if (board_uart_read(&ch, 1) > 0) { - // board_uart_write(&ch, 1); - // } - } -} - -#else -#include -#include -#include - -/* 1000 msec = 1 sec */ -#define SLEEP_TIME_MS 200 - -/* The devicetree node identifier for the "led0" alias. */ -#define LED0_NODE DT_ALIAS(led0) - -/* - * A build error on this line means your board is unsupported. - * See the sample documentation for information on how to fix this. - */ -static const struct gpio_dt_spec led = GPIO_DT_SPEC_GET(LED0_NODE, gpios); - -int main(void) -{ - int ret; - bool led_state = true; - - if (!gpio_is_ready_dt(&led)) { - return 0; - } - - ret = gpio_pin_configure_dt(&led, GPIO_OUTPUT_ACTIVE); - if (ret < 0) { - return 0; - } - - while (1) { - ret = gpio_pin_toggle_dt(&led); - if (ret < 0) { - return 0; + uint8_t ch; + if (board_uart_read(&ch, 1) > 0) { + board_uart_write(&ch, 1); } - - led_state = !led_state; - printf("LED state: %s\n", led_state ? "ON" : "OFF"); - k_msleep(SLEEP_TIME_MS); } - return 0; } -#endif #if TUSB_MCU_VENDOR_ESPRESSIF void app_main(void) { diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index f9ce47173..04d537376 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -346,29 +346,29 @@ endfunction() # RPI specific: refactor later #---------------------------------- function(family_add_default_example_warnings TARGET) -# target_compile_options(${TARGET} PUBLIC -# -Wall -# -Wextra -# -Werror -# -Wfatal-errors -# -Wdouble-promotion -# -Wfloat-equal -# # FIXME commented out because of https://github.com/raspberrypi/pico-sdk/issues/1468 -# #-Wshadow -# -Wwrite-strings -# -Wsign-compare -# -Wmissing-format-attribute -# -Wunreachable-code -# -Wcast-align -# -Wcast-qual -# -Wnull-dereference -# -Wuninitialized -# -Wunused -# -Wredundant-decls -# #-Wstrict-prototypes -# #-Werror-implicit-function-declaration -# #-Wundef -# ) + target_compile_options(${TARGET} PUBLIC + -Wall + -Wextra + -Werror + -Wfatal-errors + -Wdouble-promotion + -Wfloat-equal + # FIXME commented out because of https://github.com/raspberrypi/pico-sdk/issues/1468 + #-Wshadow + -Wwrite-strings + -Wsign-compare + -Wmissing-format-attribute + -Wunreachable-code + -Wcast-align + -Wcast-qual + -Wnull-dereference + -Wuninitialized + -Wunused + -Wredundant-decls + #-Wstrict-prototypes + #-Werror-implicit-function-declaration + #-Wundef + ) if (CMAKE_C_COMPILER_ID STREQUAL "GNU") if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 AND NO_WARN_RWX_SEGMENTS_SUPPORTED) diff --git a/hw/bsp/lpc11/family.c b/hw/bsp/lpc11/family.c index 566449ca0..b5371632c 100644 --- a/hw/bsp/lpc11/family.c +++ b/hw/bsp/lpc11/family.c @@ -42,6 +42,10 @@ #include "bsp/board_api.h" #include "board.h" +extern void USB_IRQHandler(void); +extern void SysTick_Handler(void); +void SystemInit(void); + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ diff --git a/hw/bsp/lpc11/family.cmake b/hw/bsp/lpc11/family.cmake index a9febfc7f..6781b20c6 100644 --- a/hw/bsp/lpc11/family.cmake +++ b/hw/bsp/lpc11/family.cmake @@ -49,7 +49,10 @@ function(add_board_target BOARD_TARGET) update_board(${BOARD_TARGET}) if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_compile_options(${BOARD_TARGET} PUBLIC -nostdlib) + target_compile_options(${BOARD_TARGET} PUBLIC + -nostdlib + -Wno-error=incompatible-pointer-types + ) target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" --specs=nosys.specs --specs=nano.specs diff --git a/hw/bsp/lpc18/family.c b/hw/bsp/lpc18/family.c index 8f6dbcd4a..0db5c83b6 100644 --- a/hw/bsp/lpc18/family.c +++ b/hw/bsp/lpc18/family.c @@ -32,6 +32,11 @@ #include "bsp/board_api.h" #include "board.h" +extern void USB0_IRQHandler(void); +extern void USB1_IRQHandler(void); +extern void SysTick_Handler(void); +void SystemInit(void); + //--------------------------------------------------------------------+ // USB Interrupt Handler //--------------------------------------------------------------------+ diff --git a/hw/bsp/lpc18/family.mk b/hw/bsp/lpc18/family.mk index f625e926a..f120f63b2 100644 --- a/hw/bsp/lpc18/family.mk +++ b/hw/bsp/lpc18/family.mk @@ -12,7 +12,7 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_LPC18XX # mcu driver cause following warnings -CFLAGS += -Wno-error=unused-parameter -Wno-error=strict-prototypes -Wno-error=cast-qual +CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-qual LDFLAGS_GCC += --specs=nosys.specs --specs=nano.specs diff --git a/hw/bsp/lpc43/family.c b/hw/bsp/lpc43/family.c index fe6c7b0c8..591090c36 100644 --- a/hw/bsp/lpc43/family.c +++ b/hw/bsp/lpc43/family.c @@ -47,6 +47,11 @@ const uint32_t OscRateIn = 12000000; const uint32_t ExtRateIn = 0; +extern void USB0_IRQHandler(void); +extern void USB1_IRQHandler(void); +extern void SysTick_Handler(void); +void SystemInit(void); + /*------------------------------------------------------------------*/ /* BOARD API *------------------------------------------------------------------*/ diff --git a/hw/bsp/lpc43/family.cmake b/hw/bsp/lpc43/family.cmake index 9d993a698..23c4aecea 100644 --- a/hw/bsp/lpc43/family.cmake +++ b/hw/bsp/lpc43/family.cmake @@ -51,7 +51,10 @@ function(add_board_target BOARD_TARGET) update_board(${BOARD_TARGET}) if (CMAKE_C_COMPILER_ID STREQUAL "GNU") - target_compile_options(${BOARD_TARGET} PUBLIC -nostdlib) + target_compile_options(${BOARD_TARGET} PUBLIC + -nostdlib + -Wno-error=incompatible-pointer-types + ) target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" --specs=nosys.specs --specs=nano.specs diff --git a/hw/bsp/lpc43/family.mk b/hw/bsp/lpc43/family.mk index 84e7c30b3..e1406aae7 100644 --- a/hw/bsp/lpc43/family.mk +++ b/hw/bsp/lpc43/family.mk @@ -14,7 +14,6 @@ CFLAGS += \ # mcu driver cause following warnings CFLAGS += \ -Wno-error=unused-parameter \ - -Wno-error=strict-prototypes \ -Wno-error=cast-qual \ -Wno-error=incompatible-pointer-types \ diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk index f5a3f5c45..a8acb1624 100644 --- a/hw/bsp/nrf/family.mk +++ b/hw/bsp/nrf/family.mk @@ -45,6 +45,7 @@ SRC_C += \ INC += \ $(TOP)/$(BOARD_PATH) \ + $(TOP)/$(FAMILY_PATH)/nrfx_config \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/${NRFX_PATH} \ $(TOP)/${NRFX_PATH}/mdk \ diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index bf926fd09..7b3ab4d42 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -40,35 +40,3 @@ function(tinyusb_target_add TARGET) ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../lib/networking ) endfunction() - -#------------------------------------ -# TinyUSB as library target -#------------------------------------ -#if (NOT DEFINED TINYUSB_TARGET) -# set(TINYUSB_TARGET "tinyusb") -#endif () -# -#set(TINYUSB_CONFIG_TARGET "${TINYUSB_TARGET}_config") -# -#if (DEFINED TINYUSB_TARGET_PREFIX) -# set(TINYUSB_TARGET "${TINYUSB_TARGET_PREFIX}${TINYUSB_TARGET}") -# set(TINYUSB_CONFIG_TARGET "${TINYUSB_TARGET_PREFIX}${TINYUSB_CONFIG_TARGET}") -#endif () -# -#if (DEFINED TINYUSB_TARGET_SUFFIX) -# set(TINYUSB_TARGET "${TINYUSB_TARGET}${TINYUSB_TARGET_SUFFIX}") -# set(TINYUSB_CONFIG_TARGET "${TINYUSB_CONFIG_TARGET}${TINYUSB_TARGET_SUFFIX}") -#endif () -# -#add_library(${TINYUSB_TARGET} STATIC) -#tinyusb_target_add(${TINYUSB_TARGET}) -# -## Check if tinyusb_config target is defined -#if (NOT TARGET ${TINYUSB_CONFIG_TARGET}) -# message(FATAL_ERROR "${TINYUSB_CONFIG_TARGET} target is not defined") -#endif() -# -## Link with tinyusb_config target -#target_link_libraries(${TINYUSB_TARGET} PUBLIC -# ${TINYUSB_CONFIG_TARGET} -# ) -- cgit v1.3.1 From efd29349191b5124d8f998417d31919fec49a4a4 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 6 Feb 2025 12:19:29 +0700 Subject: fix build for 407blackvet --- hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'hw') diff --git a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk index 2593978ec..c46a78f81 100644 --- a/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk +++ b/hw/bsp/stm32f4/boards/stm32f407blackvet/board.mk @@ -1,12 +1,12 @@ CFLAGS += -DSTM32F407xx # GCC -GCC_SRC_S += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f407xx.s -GCC_LD_FILE = $(BOARD_PATH)/STM32F407VETX_FLASH.ld +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32f407xx.s +LD_FILE_GCC = $(BOARD_PATH)/STM32F407VETx_FLASH.ld # IAR -IAR_SRC_S += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f407xx.s -IAR_LD_FILE = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f407xx_flash.icf +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32f407xx.s +LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32f407xx_flash.icf # For flash-jlink target -- cgit v1.3.1 From 09bce3532c9279b54f5dc1e48c51959344df6c56 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sun, 9 Feb 2025 00:04:16 +0100 Subject: Add CMake presets. Signed-off-by: HiFiPhile --- .gitignore | 8 +- examples/CMakePresets.json | 6 + examples/device/CMakePresets.json | 6 + .../device/audio_4_channel_mic/CMakePresets.json | 6 + .../audio_4_channel_mic_freertos/CMakePresets.json | 6 + .../src/CMakePresets.json | 6 + examples/device/audio_test/CMakePresets.json | 6 + .../device/audio_test_freertos/CMakePresets.json | 6 + .../audio_test_freertos/src/CMakePresets.json | 6 + .../device/audio_test_multi_rate/CMakePresets.json | 6 + examples/device/board_test/CMakePresets.json | 6 + examples/device/board_test/src/CMakePresets.json | 6 + examples/device/cdc_dual_ports/CMakePresets.json | 6 + examples/device/cdc_msc/CMakePresets.json | 6 + examples/device/cdc_msc_freertos/CMakePresets.json | 6 + .../device/cdc_msc_freertos/src/CMakePresets.json | 6 + examples/device/cdc_uac2/CMakePresets.json | 6 + examples/device/dfu/CMakePresets.json | 6 + examples/device/dfu_runtime/CMakePresets.json | 6 + .../device/dynamic_configuration/CMakePresets.json | 6 + .../device/hid_boot_interface/CMakePresets.json | 6 + examples/device/hid_composite/CMakePresets.json | 6 + .../hid_composite_freertos/CMakePresets.json | 6 + .../hid_composite_freertos/src/CMakePresets.json | 6 + .../device/hid_generic_inout/CMakePresets.json | 6 + .../hid_multiple_interface/CMakePresets.json | 6 + examples/device/midi_test/CMakePresets.json | 6 + .../device/midi_test_freertos/CMakePresets.json | 6 + .../midi_test_freertos/src/CMakePresets.json | 6 + examples/device/msc_dual_lun/CMakePresets.json | 6 + .../device/net_lwip_webserver/CMakePresets.json | 6 + examples/device/uac2_headset/CMakePresets.json | 6 + examples/device/uac2_speaker_fb/CMakePresets.json | 6 + examples/device/usbtmc/CMakePresets.json | 6 + examples/device/video_capture/CMakePresets.json | 6 + .../device/video_capture/src/CMakePresets.json | 6 + .../device/video_capture_2ch/CMakePresets.json | 6 + .../device/video_capture_2ch/src/CMakePresets.json | 6 + examples/device/webusb_serial/CMakePresets.json | 6 + examples/dual/CMakePresets.json | 6 + .../dual/host_hid_to_device_cdc/CMakePresets.json | 6 + .../dual/host_info_to_device_cdc/CMakePresets.json | 6 + examples/host/CMakePresets.json | 6 + examples/host/bare_api/CMakePresets.json | 6 + examples/host/cdc_msc_hid/CMakePresets.json | 6 + .../host/cdc_msc_hid_freertos/CMakePresets.json | 6 + .../cdc_msc_hid_freertos/src/CMakePresets.json | 6 + examples/host/device_info/CMakePresets.json | 6 + examples/host/device_info/src/CMakePresets.json | 6 + examples/host/hid_controller/CMakePresets.json | 6 + examples/host/msc_file_explorer/CMakePresets.json | 6 + examples/typec/CMakePresets.json | 6 + examples/typec/power_delivery/CMakePresets.json | 6 + hw/bsp/BoardPresets.json | 4002 ++++++++++++++++++++ hw/bsp/family_support.cmake | 6 +- tools/gen_presets.py | 91 + 56 files changed, 4417 insertions(+), 2 deletions(-) create mode 100644 examples/CMakePresets.json create mode 100644 examples/device/CMakePresets.json create mode 100644 examples/device/audio_4_channel_mic/CMakePresets.json create mode 100644 examples/device/audio_4_channel_mic_freertos/CMakePresets.json create mode 100644 examples/device/audio_4_channel_mic_freertos/src/CMakePresets.json create mode 100644 examples/device/audio_test/CMakePresets.json create mode 100644 examples/device/audio_test_freertos/CMakePresets.json create mode 100644 examples/device/audio_test_freertos/src/CMakePresets.json create mode 100644 examples/device/audio_test_multi_rate/CMakePresets.json create mode 100644 examples/device/board_test/CMakePresets.json create mode 100644 examples/device/board_test/src/CMakePresets.json create mode 100644 examples/device/cdc_dual_ports/CMakePresets.json create mode 100644 examples/device/cdc_msc/CMakePresets.json create mode 100644 examples/device/cdc_msc_freertos/CMakePresets.json create mode 100644 examples/device/cdc_msc_freertos/src/CMakePresets.json create mode 100644 examples/device/cdc_uac2/CMakePresets.json create mode 100644 examples/device/dfu/CMakePresets.json create mode 100644 examples/device/dfu_runtime/CMakePresets.json create mode 100644 examples/device/dynamic_configuration/CMakePresets.json create mode 100644 examples/device/hid_boot_interface/CMakePresets.json create mode 100644 examples/device/hid_composite/CMakePresets.json create mode 100644 examples/device/hid_composite_freertos/CMakePresets.json create mode 100644 examples/device/hid_composite_freertos/src/CMakePresets.json create mode 100644 examples/device/hid_generic_inout/CMakePresets.json create mode 100644 examples/device/hid_multiple_interface/CMakePresets.json create mode 100644 examples/device/midi_test/CMakePresets.json create mode 100644 examples/device/midi_test_freertos/CMakePresets.json create mode 100644 examples/device/midi_test_freertos/src/CMakePresets.json create mode 100644 examples/device/msc_dual_lun/CMakePresets.json create mode 100644 examples/device/net_lwip_webserver/CMakePresets.json create mode 100644 examples/device/uac2_headset/CMakePresets.json create mode 100644 examples/device/uac2_speaker_fb/CMakePresets.json create mode 100644 examples/device/usbtmc/CMakePresets.json create mode 100644 examples/device/video_capture/CMakePresets.json create mode 100644 examples/device/video_capture/src/CMakePresets.json create mode 100644 examples/device/video_capture_2ch/CMakePresets.json create mode 100644 examples/device/video_capture_2ch/src/CMakePresets.json create mode 100644 examples/device/webusb_serial/CMakePresets.json create mode 100644 examples/dual/CMakePresets.json create mode 100644 examples/dual/host_hid_to_device_cdc/CMakePresets.json create mode 100644 examples/dual/host_info_to_device_cdc/CMakePresets.json create mode 100644 examples/host/CMakePresets.json create mode 100644 examples/host/bare_api/CMakePresets.json create mode 100644 examples/host/cdc_msc_hid/CMakePresets.json create mode 100644 examples/host/cdc_msc_hid_freertos/CMakePresets.json create mode 100644 examples/host/cdc_msc_hid_freertos/src/CMakePresets.json create mode 100644 examples/host/device_info/CMakePresets.json create mode 100644 examples/host/device_info/src/CMakePresets.json create mode 100644 examples/host/hid_controller/CMakePresets.json create mode 100644 examples/host/msc_file_explorer/CMakePresets.json create mode 100644 examples/typec/CMakePresets.json create mode 100644 examples/typec/power_delivery/CMakePresets.json create mode 100644 hw/bsp/BoardPresets.json create mode 100755 tools/gen_presets.py (limited to 'hw') diff --git a/.gitignore b/.gitignore index 010b5c9ed..f981110b2 100644 --- a/.gitignore +++ b/.gitignore @@ -37,4 +37,10 @@ cmake-build-* sdkconfig .PVS-Studio .vscode/ -build/ +build +CMakeFiles +Debug +RelWithDebInfo +Release +BrowseInfo +.cmake_build diff --git a/examples/CMakePresets.json b/examples/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/CMakePresets.json b/examples/device/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/audio_4_channel_mic/CMakePresets.json b/examples/device/audio_4_channel_mic/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/audio_4_channel_mic/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/audio_4_channel_mic_freertos/CMakePresets.json b/examples/device/audio_4_channel_mic_freertos/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/audio_4_channel_mic_freertos/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/audio_4_channel_mic_freertos/src/CMakePresets.json b/examples/device/audio_4_channel_mic_freertos/src/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/audio_4_channel_mic_freertos/src/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/audio_test/CMakePresets.json b/examples/device/audio_test/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/audio_test/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/audio_test_freertos/CMakePresets.json b/examples/device/audio_test_freertos/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/audio_test_freertos/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/audio_test_freertos/src/CMakePresets.json b/examples/device/audio_test_freertos/src/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/audio_test_freertos/src/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/audio_test_multi_rate/CMakePresets.json b/examples/device/audio_test_multi_rate/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/audio_test_multi_rate/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/board_test/CMakePresets.json b/examples/device/board_test/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/board_test/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/board_test/src/CMakePresets.json b/examples/device/board_test/src/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/board_test/src/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/cdc_dual_ports/CMakePresets.json b/examples/device/cdc_dual_ports/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/cdc_dual_ports/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/cdc_msc/CMakePresets.json b/examples/device/cdc_msc/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/cdc_msc/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/cdc_msc_freertos/CMakePresets.json b/examples/device/cdc_msc_freertos/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/cdc_msc_freertos/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/cdc_msc_freertos/src/CMakePresets.json b/examples/device/cdc_msc_freertos/src/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/cdc_msc_freertos/src/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/cdc_uac2/CMakePresets.json b/examples/device/cdc_uac2/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/cdc_uac2/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/dfu/CMakePresets.json b/examples/device/dfu/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/dfu/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/dfu_runtime/CMakePresets.json b/examples/device/dfu_runtime/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/dfu_runtime/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/dynamic_configuration/CMakePresets.json b/examples/device/dynamic_configuration/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/dynamic_configuration/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/hid_boot_interface/CMakePresets.json b/examples/device/hid_boot_interface/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/hid_boot_interface/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/hid_composite/CMakePresets.json b/examples/device/hid_composite/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/hid_composite/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/hid_composite_freertos/CMakePresets.json b/examples/device/hid_composite_freertos/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/hid_composite_freertos/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/hid_composite_freertos/src/CMakePresets.json b/examples/device/hid_composite_freertos/src/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/hid_composite_freertos/src/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/hid_generic_inout/CMakePresets.json b/examples/device/hid_generic_inout/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/hid_generic_inout/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/hid_multiple_interface/CMakePresets.json b/examples/device/hid_multiple_interface/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/hid_multiple_interface/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/midi_test/CMakePresets.json b/examples/device/midi_test/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/midi_test/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/midi_test_freertos/CMakePresets.json b/examples/device/midi_test_freertos/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/midi_test_freertos/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/midi_test_freertos/src/CMakePresets.json b/examples/device/midi_test_freertos/src/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/midi_test_freertos/src/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/msc_dual_lun/CMakePresets.json b/examples/device/msc_dual_lun/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/msc_dual_lun/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/net_lwip_webserver/CMakePresets.json b/examples/device/net_lwip_webserver/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/net_lwip_webserver/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/uac2_headset/CMakePresets.json b/examples/device/uac2_headset/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/uac2_headset/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/uac2_speaker_fb/CMakePresets.json b/examples/device/uac2_speaker_fb/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/uac2_speaker_fb/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/usbtmc/CMakePresets.json b/examples/device/usbtmc/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/usbtmc/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/video_capture/CMakePresets.json b/examples/device/video_capture/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/video_capture/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/video_capture/src/CMakePresets.json b/examples/device/video_capture/src/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/video_capture/src/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/video_capture_2ch/CMakePresets.json b/examples/device/video_capture_2ch/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/video_capture_2ch/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/video_capture_2ch/src/CMakePresets.json b/examples/device/video_capture_2ch/src/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/video_capture_2ch/src/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/device/webusb_serial/CMakePresets.json b/examples/device/webusb_serial/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/device/webusb_serial/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/dual/CMakePresets.json b/examples/dual/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/dual/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/dual/host_hid_to_device_cdc/CMakePresets.json b/examples/dual/host_hid_to_device_cdc/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/dual/host_hid_to_device_cdc/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/dual/host_info_to_device_cdc/CMakePresets.json b/examples/dual/host_info_to_device_cdc/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/dual/host_info_to_device_cdc/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/host/CMakePresets.json b/examples/host/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/host/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/host/bare_api/CMakePresets.json b/examples/host/bare_api/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/host/bare_api/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/host/cdc_msc_hid/CMakePresets.json b/examples/host/cdc_msc_hid/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/host/cdc_msc_hid/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/host/cdc_msc_hid_freertos/CMakePresets.json b/examples/host/cdc_msc_hid_freertos/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/host/cdc_msc_hid_freertos/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/host/cdc_msc_hid_freertos/src/CMakePresets.json b/examples/host/cdc_msc_hid_freertos/src/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/host/cdc_msc_hid_freertos/src/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/host/device_info/CMakePresets.json b/examples/host/device_info/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/host/device_info/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/host/device_info/src/CMakePresets.json b/examples/host/device_info/src/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/host/device_info/src/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/host/hid_controller/CMakePresets.json b/examples/host/hid_controller/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/host/hid_controller/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/host/msc_file_explorer/CMakePresets.json b/examples/host/msc_file_explorer/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/host/msc_file_explorer/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/typec/CMakePresets.json b/examples/typec/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/typec/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git a/examples/typec/power_delivery/CMakePresets.json b/examples/typec/power_delivery/CMakePresets.json new file mode 100644 index 000000000..5cd8971e9 --- /dev/null +++ b/examples/typec/power_delivery/CMakePresets.json @@ -0,0 +1,6 @@ +{ + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] +} diff --git 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"default" + }, + { + "name": "stm32h563nucleo", + "inherits": "default" + }, + { + "name": "stm32h573i_dk", + "inherits": "default" + }, + { + "name": "daisyseed", + "inherits": "default" + }, + { + "name": "stm32h723nucleo", + "inherits": "default" + }, + { + "name": "stm32h743eval", + "inherits": "default" + }, + { + "name": "stm32h743nucleo", + "inherits": "default" + }, + { + "name": "stm32h745disco", + "inherits": "default" + }, + { + "name": "stm32h750bdk", + "inherits": "default" + }, + { + "name": "stm32h750_weact", + "inherits": "default" + }, + { + "name": "waveshare_openh743i", + "inherits": "default" + }, + { + "name": "stm32h7s3nucleo", + "inherits": "default" + }, + { + "name": "stm32l052dap52", + "inherits": "default" + }, + { + "name": "stm32l0538disco", + "inherits": "default" + }, + { + "name": "stm32l412nucleo", + "inherits": "default" + }, + { + "name": "stm32l476disco", + "inherits": "default" + }, + { + "name": "stm32l4p5nucleo", + "inherits": "default" + }, + { + "name": "stm32l4r5nucleo", + "inherits": "default" + }, + { + "name": "b_u585i_iot2a", + "inherits": "default" + }, + { + "name": "stm32u545nucleo", + "inherits": "default" + }, + { + "name": "stm32u575eval", + "inherits": "default" + }, + { + "name": "stm32u575nucleo", + "inherits": "default" + }, + { + "name": "stm32u5a5nucleo", + "inherits": "default" + }, + { + "name": "stm32wb55nucleo", + "inherits": "default" + }, + { + "name": "ek_tm4c123gxl", + "inherits": "default" + }, + { + "name": "xmc4500_relax", + "inherits": "default" + }, + { + "name": "xmc4700_relax", + "inherits": "default" + } + ], + "buildPresets": [ + { + "name": "raspberrypi_zero", + "description": "Build preset for the raspberrypi_zero board", + "configurePreset": "raspberrypi_zero" + }, + { + "name": "raspberrypi_cm4", + "description": "Build preset for the raspberrypi_cm4 board", + "configurePreset": "raspberrypi_cm4" + }, + { + "name": "raspberrypi_zero2", + "description": "Build preset for the raspberrypi_zero2 board", + "configurePreset": "raspberrypi_zero2" + }, + { + "name": "ch32v103r_r1_1v0", + "description": "Build preset for the ch32v103r_r1_1v0 board", + "configurePreset": "ch32v103r_r1_1v0" + }, + { + "name": "ch32v203c_r0_1v0", + "description": "Build preset for the ch32v203c_r0_1v0 board", + "configurePreset": "ch32v203c_r0_1v0" + }, + { + "name": "ch32v203g_r0_1v0", + "description": "Build preset for the ch32v203g_r0_1v0 board", + "configurePreset": "ch32v203g_r0_1v0" + }, + { + "name": "nanoch32v203", + "description": "Build preset for the nanoch32v203 board", + "configurePreset": "nanoch32v203" + }, + { + "name": "ch32v307v_r1_1v0", + "description": "Build preset for the ch32v307v_r1_1v0 board", + "configurePreset": "ch32v307v_r1_1v0" + }, + { + "name": "da14695_dk_usb", + "description": "Build preset for the da14695_dk_usb board", + "configurePreset": "da14695_dk_usb" + }, + { + "name": "da1469x_dk_pro", + "description": "Build preset for the da1469x_dk_pro board", + "configurePreset": "da1469x_dk_pro" + }, + { + "name": "adafruit_feather_esp32s2", + "description": "Build preset for the adafruit_feather_esp32s2 board", + "configurePreset": "adafruit_feather_esp32s2" + }, + { + "name": "adafruit_feather_esp32s3", + "description": "Build preset for the adafruit_feather_esp32s3 board", + "configurePreset": "adafruit_feather_esp32s3" + }, + { + "name": "adafruit_feather_esp32_v2", + "description": "Build preset for the adafruit_feather_esp32_v2 board", + "configurePreset": "adafruit_feather_esp32_v2" + }, + { + "name": "adafruit_magtag_29gray", + "description": "Build preset for the adafruit_magtag_29gray board", + "configurePreset": "adafruit_magtag_29gray" + }, + { + "name": "adafruit_metro_esp32s2", + "description": "Build preset for the adafruit_metro_esp32s2 board", + "configurePreset": "adafruit_metro_esp32s2" + }, + { + "name": "espressif_addax_1", + "description": "Build preset for the espressif_addax_1 board", + "configurePreset": "espressif_addax_1" + }, + { + "name": "espressif_c3_devkitc", + "description": "Build preset for the espressif_c3_devkitc board", + "configurePreset": "espressif_c3_devkitc" + }, + { + "name": "espressif_c6_devkitc", + "description": "Build preset for the espressif_c6_devkitc board", + "configurePreset": "espressif_c6_devkitc" + }, + { + "name": "espressif_kaluga_1", + "description": "Build preset for the espressif_kaluga_1 board", + "configurePreset": "espressif_kaluga_1" + }, + { + "name": "espressif_p4_function_ev", + "description": "Build preset for the espressif_p4_function_ev board", + "configurePreset": "espressif_p4_function_ev" + }, + { + "name": "espressif_s2_devkitc", + "description": "Build preset for the espressif_s2_devkitc board", + "configurePreset": "espressif_s2_devkitc" + }, + { + "name": "espressif_s3_devkitc", + "description": "Build preset for the espressif_s3_devkitc board", + "configurePreset": "espressif_s3_devkitc" + }, + { + "name": "espressif_s3_devkitm", + "description": "Build preset for the espressif_s3_devkitm board", + "configurePreset": "espressif_s3_devkitm" + }, + { + "name": "espressif_saola_1", + "description": "Build preset for the espressif_saola_1 board", + "configurePreset": "espressif_saola_1" + }, + { + "name": "f1c100s", + "description": "Build preset for the f1c100s board", + "configurePreset": "f1c100s" + }, + { + "name": "fomu", + "description": "Build preset for the fomu board", + "configurePreset": "fomu" + }, + { + "name": "sipeed_longan_nano", + "description": "Build preset for the sipeed_longan_nano board", + "configurePreset": "sipeed_longan_nano" + }, + { + "name": "metro_m7_1011", + "description": "Build preset for the metro_m7_1011 board", + "configurePreset": "metro_m7_1011" + }, + { + "name": "metro_m7_1011_sd", + "description": "Build preset for the metro_m7_1011_sd board", + "configurePreset": "metro_m7_1011_sd" + }, + { + "name": "mimxrt1010_evk", + "description": "Build preset for the mimxrt1010_evk board", + "configurePreset": "mimxrt1010_evk" + }, + { + "name": "mimxrt1015_evk", + "description": "Build preset for the mimxrt1015_evk board", + "configurePreset": "mimxrt1015_evk" + }, + { + "name": "mimxrt1020_evk", + "description": "Build preset for the mimxrt1020_evk board", + "configurePreset": "mimxrt1020_evk" + }, + { + "name": "mimxrt1024_evk", + "description": "Build preset for the mimxrt1024_evk board", + "configurePreset": "mimxrt1024_evk" + }, + { + "name": "mimxrt1050_evkb", + "description": "Build preset for the mimxrt1050_evkb board", + "configurePreset": "mimxrt1050_evkb" + }, + { + "name": "mimxrt1060_evk", + "description": "Build preset for the mimxrt1060_evk board", + "configurePreset": "mimxrt1060_evk" + }, + { + "name": "mimxrt1064_evk", + "description": "Build preset for the mimxrt1064_evk board", + "configurePreset": "mimxrt1064_evk" + }, + { + "name": "mimxrt1170_evkb", + "description": "Build preset for the mimxrt1170_evkb board", + "configurePreset": "mimxrt1170_evkb" + }, + { + "name": "teensy_40", + "description": "Build preset for the teensy_40 board", + "configurePreset": "teensy_40" + }, + { + "name": "teensy_41", + "description": "Build preset for the teensy_41 board", + "configurePreset": "teensy_41" + }, + { + "name": "frdm_k64f", + "description": "Build preset for the frdm_k64f board", + "configurePreset": "frdm_k64f" + }, + { + "name": "teensy_35", + "description": "Build preset for the teensy_35 board", + "configurePreset": "teensy_35" + }, + { + "name": "frdm_k32l2a4s", + "description": "Build preset for the frdm_k32l2a4s board", + "configurePreset": "frdm_k32l2a4s" + }, + { + "name": "frdm_k32l2b", + "description": "Build preset for the frdm_k32l2b board", + "configurePreset": "frdm_k32l2b" + }, + { + "name": "kuiic", + "description": "Build preset for the kuiic board", + "configurePreset": "kuiic" + }, + { + "name": "frdm_kl25z", + "description": "Build preset for the frdm_kl25z board", + "configurePreset": "frdm_kl25z" + }, + { + "name": "lpcxpresso11u37", + "description": "Build preset for the lpcxpresso11u37 board", + "configurePreset": "lpcxpresso11u37" + }, + { + "name": "lpcxpresso11u68", + "description": "Build preset for the lpcxpresso11u68 board", + "configurePreset": "lpcxpresso11u68" + }, + { + "name": "lpcxpresso1347", + "description": "Build preset for the lpcxpresso1347 board", + "configurePreset": "lpcxpresso1347" + }, + { + "name": "lpcxpresso1549", + "description": "Build preset for the lpcxpresso1549 board", + "configurePreset": "lpcxpresso1549" + }, + { + "name": "lpcxpresso1769", + "description": "Build preset for the lpcxpresso1769 board", + "configurePreset": "lpcxpresso1769" + }, + { + "name": "mbed1768", + "description": "Build preset for the mbed1768 board", + "configurePreset": "mbed1768" + }, + { + "name": "lpcxpresso18s37", + "description": "Build preset for the lpcxpresso18s37 board", + "configurePreset": "lpcxpresso18s37" + }, + { + "name": "mcb1800", + "description": "Build preset for the mcb1800 board", + "configurePreset": "mcb1800" + }, + { + "name": "ea4088_quickstart", + "description": "Build preset for the ea4088_quickstart board", + "configurePreset": "ea4088_quickstart" + }, + { + "name": "ea4357", + "description": "Build preset for the ea4357 board", + "configurePreset": "ea4357" + }, + { + "name": "lpcxpresso43s67", + "description": "Build preset for the lpcxpresso43s67 board", + "configurePreset": "lpcxpresso43s67" + }, + { + "name": "lpcxpresso51u68", + "description": "Build preset for the lpcxpresso51u68 board", + "configurePreset": "lpcxpresso51u68" + }, + { + "name": "lpcxpresso54114", + "description": "Build preset for the lpcxpresso54114 board", + "configurePreset": "lpcxpresso54114" + }, + { + "name": "lpcxpresso54608", + "description": "Build preset for the lpcxpresso54608 board", + "configurePreset": "lpcxpresso54608" + }, + { + "name": "lpcxpresso54628", + "description": "Build preset for the lpcxpresso54628 board", + "configurePreset": "lpcxpresso54628" + }, + { + "name": "double_m33_express", + "description": "Build preset for the double_m33_express board", + "configurePreset": "double_m33_express" + }, + { + "name": "lpcxpresso55s28", + "description": "Build preset for the lpcxpresso55s28 board", + "configurePreset": "lpcxpresso55s28" + }, + { + "name": "lpcxpresso55s69", + "description": "Build preset for the lpcxpresso55s69 board", + "configurePreset": "lpcxpresso55s69" + }, + { + "name": "mcu_link", + "description": "Build preset for the mcu_link board", + "configurePreset": "mcu_link" + }, + { + "name": "max32650evkit", + "description": "Build preset for the max32650evkit board", + "configurePreset": "max32650evkit" + }, + { + "name": "max32650fthr", + "description": "Build preset for the max32650fthr board", + "configurePreset": "max32650fthr" + }, + { + "name": "max32651evkit", + "description": "Build preset for the max32651evkit board", + "configurePreset": "max32651evkit" + }, + { + "name": "max32666evkit", + "description": "Build preset for the max32666evkit board", + "configurePreset": "max32666evkit" + }, + { + "name": "max32666fthr", + "description": "Build preset for the max32666fthr board", + "configurePreset": "max32666fthr" + }, + { + "name": "apard32690", + "description": "Build preset for the apard32690 board", + "configurePreset": "apard32690" + }, + { + "name": "max32690evkit", + "description": "Build preset for the max32690evkit board", + "configurePreset": "max32690evkit" + }, + { + "name": "max78002evkit", + "description": "Build preset for the max78002evkit board", + "configurePreset": "max78002evkit" + }, + { + "name": "frdm_mcxa153", + "description": "Build preset for the frdm_mcxa153 board", + "configurePreset": "frdm_mcxa153" + }, + { + "name": "frdm_mcxn947", + "description": "Build preset for the frdm_mcxn947 board", + "configurePreset": "frdm_mcxn947" + }, + { + "name": "mcxn947brk", + "description": "Build preset for the mcxn947brk board", + "configurePreset": "mcxn947brk" + }, + { + "name": "mm32f327x_mb39", + "description": "Build preset for the mm32f327x_mb39 board", + "configurePreset": "mm32f327x_mb39" + }, + { + "name": "mm32f327x_pitaya_lite", + "description": "Build preset for the mm32f327x_pitaya_lite board", + "configurePreset": "mm32f327x_pitaya_lite" + }, + { + "name": "msp_exp430f5529lp", + "description": "Build preset for the msp_exp430f5529lp board", + "configurePreset": "msp_exp430f5529lp" + }, + { + "name": "msp_exp432e401y", + "description": "Build preset for the msp_exp432e401y board", + "configurePreset": "msp_exp432e401y" + }, + { + "name": "adafruit_clue", + "description": "Build preset for the adafruit_clue board", + "configurePreset": "adafruit_clue" + }, + { + "name": "arduino_nano33_ble", + "description": "Build preset for the arduino_nano33_ble board", + "configurePreset": "arduino_nano33_ble" + }, + { + "name": "circuitplayground_bluefruit", + "description": "Build preset for the circuitplayground_bluefruit board", + "configurePreset": "circuitplayground_bluefruit" + }, + { + "name": "feather_nrf52840_express", + "description": "Build preset for the feather_nrf52840_express board", + "configurePreset": "feather_nrf52840_express" + }, + { + "name": "feather_nrf52840_sense", + "description": "Build preset for the feather_nrf52840_sense board", + "configurePreset": "feather_nrf52840_sense" + }, + { + "name": "itsybitsy_nrf52840", + "description": "Build preset for the itsybitsy_nrf52840 board", + "configurePreset": "itsybitsy_nrf52840" + }, + { + "name": "pca10056", + "description": "Build preset for the pca10056 board", + "configurePreset": "pca10056" + }, + { + "name": "pca10059", + "description": "Build preset for the pca10059 board", + "configurePreset": "pca10059" + }, + { + "name": "pca10095", + "description": "Build preset for the pca10095 board", + "configurePreset": "pca10095" + }, + { + "name": "pca10100", + "description": "Build preset for the pca10100 board", + "configurePreset": "pca10100" + }, + { + "name": "portenta_c33", + "description": "Build preset for the portenta_c33 board", + "configurePreset": "portenta_c33" + }, + { + "name": "ra2a1_ek", + "description": "Build preset for the ra2a1_ek board", + "configurePreset": "ra2a1_ek" + }, + { + "name": "ra4m1_ek", + "description": "Build preset for the ra4m1_ek board", + "configurePreset": "ra4m1_ek" + }, + { + "name": "ra4m3_ek", + "description": "Build preset for the ra4m3_ek board", + "configurePreset": "ra4m3_ek" + }, + { + "name": "ra6m1_ek", + "description": "Build preset for the ra6m1_ek board", + "configurePreset": "ra6m1_ek" + }, + { + "name": "ra6m5_ek", + "description": "Build preset for the ra6m5_ek board", + "configurePreset": "ra6m5_ek" + }, + { + "name": "ra8m1_ek", + "description": "Build preset for the ra8m1_ek board", + "configurePreset": "ra8m1_ek" + }, + { + "name": "uno_r4", + "description": "Build preset for the uno_r4 board", + "configurePreset": "uno_r4" + }, + { + "name": "feather_rp2040_max3421", + "description": "Build preset for the feather_rp2040_max3421 board", + "configurePreset": "feather_rp2040_max3421" + }, + { + "name": "pico_sdk", + "description": "Build preset for the pico_sdk board", + "configurePreset": "pico_sdk" + }, + { + "name": "raspberry_pi_pico", + "description": "Build preset for the raspberry_pi_pico board", + "configurePreset": "raspberry_pi_pico" + }, + { + "name": "raspberry_pi_pico2", + "description": "Build preset for the raspberry_pi_pico2 board", + "configurePreset": "raspberry_pi_pico2" + }, + { + "name": "cynthion_d11", + "description": "Build preset for the cynthion_d11 board", + "configurePreset": "cynthion_d11" + }, + { + "name": "samd11_xplained", + "description": "Build preset for the samd11_xplained board", + "configurePreset": "samd11_xplained" + }, + { + "name": "atsamd21_xpro", + "description": "Build preset for the atsamd21_xpro board", + "configurePreset": "atsamd21_xpro" + }, + { + "name": "circuitplayground_express", + "description": "Build preset for the circuitplayground_express board", + "configurePreset": "circuitplayground_express" + }, + { + "name": "curiosity_nano", + "description": "Build preset for the curiosity_nano board", + "configurePreset": "curiosity_nano" + }, + { + "name": "cynthion_d21", + "description": "Build preset for the cynthion_d21 board", + "configurePreset": "cynthion_d21" + }, + { + "name": "feather_m0_express", + "description": "Build preset for the feather_m0_express board", + "configurePreset": "feather_m0_express" + }, + { + "name": "itsybitsy_m0", + "description": "Build preset for the itsybitsy_m0 board", + "configurePreset": "itsybitsy_m0" + }, + { + "name": "metro_m0_express", + "description": "Build preset for the metro_m0_express board", + "configurePreset": "metro_m0_express" + }, + { + "name": "qtpy", + "description": "Build preset for the qtpy board", + "configurePreset": "qtpy" + }, + { + "name": "seeeduino_xiao", + "description": "Build preset for the seeeduino_xiao board", + "configurePreset": "seeeduino_xiao" + }, + { + "name": "sparkfun_samd21_mini_usb", + "description": "Build preset for the sparkfun_samd21_mini_usb board", + "configurePreset": "sparkfun_samd21_mini_usb" + }, + { + "name": "trinket_m0", + "description": "Build preset for the trinket_m0 board", + "configurePreset": "trinket_m0" + }, + { + "name": "d5035_01", + "description": "Build preset for the d5035_01 board", + "configurePreset": "d5035_01" + }, + { + "name": "feather_m4_express", + "description": "Build preset for the feather_m4_express board", + "configurePreset": "feather_m4_express" + }, + { + "name": "itsybitsy_m4", + "description": "Build preset for the itsybitsy_m4 board", + "configurePreset": "itsybitsy_m4" + }, + { + "name": "metro_m4_express", + "description": "Build preset for the metro_m4_express board", + "configurePreset": "metro_m4_express" + }, + { + "name": "pybadge", + "description": "Build preset for the pybadge board", + "configurePreset": "pybadge" + }, + { + "name": "pyportal", + "description": "Build preset for the pyportal board", + "configurePreset": "pyportal" + }, + { + "name": "same54_xplained", + "description": "Build preset for the same54_xplained board", + "configurePreset": "same54_xplained" + }, + { + "name": "samg55_xplained", + "description": "Build preset for the samg55_xplained board", + "configurePreset": "samg55_xplained" + }, + { + "name": "atsaml21_xpro", + "description": "Build preset for the atsaml21_xpro board", + "configurePreset": "atsaml21_xpro" + }, + { + "name": "saml22_feather", + "description": "Build preset for the saml22_feather board", + "configurePreset": "saml22_feather" + }, + { + "name": "sensorwatch_m0", + "description": "Build preset for the sensorwatch_m0 board", + "configurePreset": "sensorwatch_m0" + }, + { + "name": "stm32c071nucleo", + "description": "Build preset for the stm32c071nucleo board", + "configurePreset": "stm32c071nucleo" + }, + { + "name": "stm32f070rbnucleo", + "description": "Build preset for the stm32f070rbnucleo board", + "configurePreset": "stm32f070rbnucleo" + }, + { + "name": "stm32f072disco", + "description": "Build preset for the stm32f072disco board", + "configurePreset": "stm32f072disco" + }, + { + "name": "stm32f072eval", + "description": "Build preset for the stm32f072eval board", + "configurePreset": "stm32f072eval" + }, + { + "name": "stm32f103ze_iar", + "description": "Build preset for the stm32f103ze_iar board", + "configurePreset": "stm32f103ze_iar" + }, + { + "name": "stm32f103_bluepill", + "description": "Build preset for the stm32f103_bluepill board", + "configurePreset": "stm32f103_bluepill" + }, + { + "name": "stm32f103_mini_2", + "description": "Build preset for the stm32f103_mini_2 board", + "configurePreset": "stm32f103_mini_2" + }, + { + "name": "stm32f207nucleo", + "description": "Build preset for the stm32f207nucleo board", + "configurePreset": "stm32f207nucleo" + }, + { + "name": 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"name": "stm32h750bdk" + }, + { + "type": "build", + "name": "stm32h750bdk" + } + ] + }, + { + "name": "stm32h750_weact", + "steps": [ + { + "type": "configure", + "name": "stm32h750_weact" + }, + { + "type": "build", + "name": "stm32h750_weact" + } + ] + }, + { + "name": "waveshare_openh743i", + "steps": [ + { + "type": "configure", + "name": "waveshare_openh743i" + }, + { + "type": "build", + "name": "waveshare_openh743i" + } + ] + }, + { + "name": "stm32h7s3nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32h7s3nucleo" + }, + { + "type": "build", + "name": "stm32h7s3nucleo" + } + ] + }, + { + "name": "stm32l052dap52", + "steps": [ + { + "type": "configure", + "name": "stm32l052dap52" + }, + { + "type": "build", + "name": "stm32l052dap52" + } + ] + }, + { + "name": "stm32l0538disco", + "steps": [ + { + "type": "configure", + "name": "stm32l0538disco" + }, + { + "type": "build", + "name": "stm32l0538disco" + } + ] + }, + { + "name": "stm32l412nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32l412nucleo" + }, + { + "type": "build", + "name": "stm32l412nucleo" + } + ] + }, + { + "name": "stm32l476disco", + "steps": [ + { + "type": "configure", + "name": "stm32l476disco" + }, + { + "type": "build", + "name": "stm32l476disco" + } + ] + }, + { + "name": "stm32l4p5nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32l4p5nucleo" + }, + { + "type": "build", + "name": "stm32l4p5nucleo" + } + ] + }, + { + "name": "stm32l4r5nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32l4r5nucleo" + }, + { + "type": "build", + "name": "stm32l4r5nucleo" + } + ] + }, + { + "name": "b_u585i_iot2a", + "steps": [ + { + "type": "configure", + "name": "b_u585i_iot2a" + }, + { + "type": "build", + "name": "b_u585i_iot2a" + } + ] + }, + { + "name": "stm32u545nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32u545nucleo" + }, + { + "type": "build", + "name": "stm32u545nucleo" + } + ] + }, + { + "name": "stm32u575eval", + "steps": [ + { + "type": "configure", + "name": "stm32u575eval" + }, + { + "type": "build", + "name": "stm32u575eval" + } + ] + }, + { + "name": "stm32u575nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32u575nucleo" + }, + { + "type": "build", + "name": "stm32u575nucleo" + } + ] + }, + { + "name": "stm32u5a5nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32u5a5nucleo" + }, + { + "type": "build", + "name": "stm32u5a5nucleo" + } + ] + }, + { + "name": "stm32wb55nucleo", + "steps": [ + { + "type": "configure", + "name": "stm32wb55nucleo" + }, + { + "type": "build", + "name": "stm32wb55nucleo" + } + ] + }, + { + "name": "ek_tm4c123gxl", + "steps": [ + { + "type": "configure", + "name": "ek_tm4c123gxl" + }, + { + "type": "build", + "name": "ek_tm4c123gxl" + } + ] + }, + { + "name": "xmc4500_relax", + "steps": [ + { + "type": "configure", + "name": "xmc4500_relax" + }, + { + "type": "build", + "name": "xmc4500_relax" + } + ] + }, + { + "name": "xmc4700_relax", + "steps": [ + { + "type": "configure", + "name": "xmc4700_relax" + }, + { + "type": "build", + "name": "xmc4700_relax" + } + ] + } + ] +} diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 04d537376..409fb9c75 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -399,7 +399,11 @@ endfunction() # Add flash jlink target function(family_flash_jlink TARGET) if (NOT DEFINED JLINKEXE) - set(JLINKEXE JLinkExe) + if(CMAKE_HOST_WIN32) + set(JLINKEXE JLink.exe) + else() + set(JLINKEXE JLinkExe) + endif() endif () if (NOT DEFINED JLINK_IF) diff --git a/tools/gen_presets.py b/tools/gen_presets.py new file mode 100755 index 000000000..98b1a7d46 --- /dev/null +++ b/tools/gen_presets.py @@ -0,0 +1,91 @@ +#!/usr/bin/env python3 +import os +import json + + +def main(): + board_list = [] + + # Find all board.cmake files + for root, dirs, files in os.walk("hw/bsp"): + for file in files: + if file == "board.cmake": + board_list.append(os.path.basename(root)) + + print('Generating presets for the following boards:') + print(board_list) + + # Generate the presets + presets = {} + presets['version'] = 6 + + # Configure presets + presets['configurePresets'] = [ + {"name": "default", + "hidden": True, + "description": r"Configure preset for the ${presetName} board", + "generator": "Ninja", + "binaryDir": r"${sourceDir}/build/${presetName}", + "cacheVariables": { + "CMAKE_BUILD_TYPE": "RelWithDebInfo", + "BOARD": r"${presetName}" + } + }] + + presets['configurePresets'].extend( + [{'name': board, 'inherits': 'default'} for board in board_list] + ) + + # Build presets + # no inheritance since 'name' doesn't support macro expansion + presets['buildPresets'] = [ + { + 'name': board, + 'description': "Build preset for the " + board + " board", + 'configurePreset': board + } + for board in board_list + ] + + # Workflow presets + presets['workflowPresets'] = [ + { + "name": board, + "steps": [ + { + "type": "configure", + "name": board + }, + { + "type": "build", + "name": board + } + ] + } + for board in board_list + ] + + with open("hw/bsp/BoardPresets.json", "w") as f: + f.write('{}\n'.format(json.dumps(presets, indent=2))) + + # Generate presets for examples + presets = { + "version": 6, + "include": [ + "../../../hw/bsp/BoardPresets.json" + ] + } + + example_list = [] + for root, dirs, files in os.walk("examples"): + for file in files: + if file == "CMakeLists.txt": + with open(os.path.join(root, 'CMakePresets.json'), 'w') as f: + f.write('{}\n'.format(json.dumps(presets, indent=2))) + example_list.append(os.path.basename(root)) + + print('Generating presets for the following examples:') + print(example_list) + +if __name__ == "__main__": + main() -- cgit v1.3.1 From 1208f88b6ecc899bfac908aaf90a8be0997efb5d Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sun, 9 Feb 2025 18:40:30 +0100 Subject: Sort list (bettter for Clion) Signed-off-by: HiFiPhile --- hw/bsp/BoardPresets.json | 1952 +++++++++++++++++++++++----------------------- tools/gen_presets.py | 70 +- 2 files changed, 1017 insertions(+), 1005 deletions(-) (limited to 'hw') diff --git a/hw/bsp/BoardPresets.json b/hw/bsp/BoardPresets.json index c295efbdd..fee8f2c97 100644 --- a/hw/bsp/BoardPresets.json +++ b/hw/bsp/BoardPresets.json @@ -5,175 +5,195 @@ "name": "default", "hidden": true, "description": "Configure preset for the ${presetName} board", - "generator": "Ninja", + "generator": "Ninja Multi-Config", "binaryDir": "${sourceDir}/build/${presetName}", "cacheVariables": { - "CMAKE_BUILD_TYPE": "RelWithDebInfo", + "CMAKE_DEFAULT_BUILD_TYPE": "RelWithDebInfo", "BOARD": "${presetName}" } }, { - "name": "raspberrypi_zero", + "name": "adafruit_clue", "inherits": "default" }, { - "name": "raspberrypi_cm4", + "name": "adafruit_feather_esp32_v2", "inherits": "default" }, { - "name": "raspberrypi_zero2", + "name": "adafruit_feather_esp32s2", "inherits": "default" }, { - "name": "ch32v103r_r1_1v0", + "name": "adafruit_feather_esp32s3", "inherits": "default" }, { - "name": "ch32v203c_r0_1v0", + "name": "adafruit_magtag_29gray", "inherits": "default" }, { - "name": "ch32v203g_r0_1v0", + "name": "adafruit_metro_esp32s2", "inherits": "default" }, { - "name": "nanoch32v203", + "name": "apard32690", "inherits": "default" }, { - "name": "ch32v307v_r1_1v0", + "name": "arduino_nano33_ble", "inherits": "default" }, { - "name": "da14695_dk_usb", + "name": "atsamd21_xpro", "inherits": "default" }, { - "name": "da1469x_dk_pro", + "name": "atsaml21_xpro", "inherits": "default" }, { - "name": "adafruit_feather_esp32s2", + "name": "b_g474e_dpow1", "inherits": "default" }, { - "name": "adafruit_feather_esp32s3", + "name": "b_u585i_iot2a", "inherits": "default" }, { - "name": "adafruit_feather_esp32_v2", + "name": "ch32v103r_r1_1v0", "inherits": "default" }, { - "name": "adafruit_magtag_29gray", + "name": "ch32v203c_r0_1v0", "inherits": "default" }, { - "name": "adafruit_metro_esp32s2", + "name": "ch32v203g_r0_1v0", "inherits": "default" }, { - "name": "espressif_addax_1", + "name": "ch32v307v_r1_1v0", "inherits": "default" }, { - "name": "espressif_c3_devkitc", + "name": "circuitplayground_bluefruit", "inherits": "default" }, { - "name": "espressif_c6_devkitc", + "name": "circuitplayground_express", "inherits": "default" }, { - "name": "espressif_kaluga_1", + "name": "curiosity_nano", "inherits": "default" }, { - "name": "espressif_p4_function_ev", + "name": "cynthion_d11", "inherits": "default" }, { - "name": "espressif_s2_devkitc", + "name": "cynthion_d21", "inherits": "default" }, { - "name": "espressif_s3_devkitc", + "name": "d5035_01", "inherits": "default" }, { - "name": "espressif_s3_devkitm", + "name": "da14695_dk_usb", "inherits": "default" }, { - "name": "espressif_saola_1", + "name": "da1469x_dk_pro", "inherits": "default" }, { - "name": "f1c100s", + "name": "daisyseed", "inherits": "default" }, { - "name": "fomu", + "name": "double_m33_express", "inherits": "default" }, { - "name": "sipeed_longan_nano", + "name": "ea4088_quickstart", "inherits": "default" }, { - "name": "metro_m7_1011", + "name": "ea4357", "inherits": "default" }, { - "name": "metro_m7_1011_sd", + "name": "ek_tm4c123gxl", "inherits": "default" }, { - "name": "mimxrt1010_evk", + "name": "espressif_addax_1", "inherits": "default" }, { - "name": "mimxrt1015_evk", + "name": "espressif_c3_devkitc", "inherits": "default" }, { - "name": "mimxrt1020_evk", + "name": "espressif_c6_devkitc", "inherits": "default" }, { - "name": "mimxrt1024_evk", + "name": "espressif_kaluga_1", "inherits": "default" }, { - "name": "mimxrt1050_evkb", + "name": "espressif_p4_function_ev", "inherits": "default" }, { - "name": "mimxrt1060_evk", + "name": "espressif_s2_devkitc", "inherits": "default" }, { - "name": "mimxrt1064_evk", + "name": "espressif_s3_devkitc", "inherits": "default" }, { - "name": "mimxrt1170_evkb", + "name": "espressif_s3_devkitm", "inherits": "default" }, { - "name": "teensy_40", + "name": "espressif_saola_1", "inherits": "default" }, { - "name": "teensy_41", + "name": "f1c100s", "inherits": "default" }, { - "name": "frdm_k64f", + "name": "feather_m0_express", "inherits": "default" }, { - "name": "teensy_35", + "name": "feather_m4_express", + "inherits": "default" + }, + { + "name": "feather_nrf52840_express", + "inherits": "default" + }, + { + "name": "feather_nrf52840_sense", + "inherits": "default" + }, + { + "name": "feather_rp2040_max3421", + "inherits": "default" + }, + { + "name": "feather_stm32f405", + "inherits": "default" + }, + { + "name": "fomu", "inherits": "default" }, { @@ -185,7 +205,7 @@ "inherits": "default" }, { - "name": "kuiic", + "name": "frdm_k64f", "inherits": "default" }, { @@ -193,43 +213,51 @@ "inherits": "default" }, { - "name": "lpcxpresso11u37", + "name": "frdm_mcxa153", "inherits": "default" }, { - "name": "lpcxpresso11u68", + "name": "frdm_mcxn947", "inherits": "default" }, { - "name": "lpcxpresso1347", + "name": "itsybitsy_m0", "inherits": "default" }, { - "name": "lpcxpresso1549", + "name": "itsybitsy_m4", "inherits": "default" }, { - "name": "lpcxpresso1769", + "name": "itsybitsy_nrf52840", "inherits": "default" }, { - "name": "mbed1768", + "name": "kuiic", "inherits": "default" }, { - "name": "lpcxpresso18s37", + "name": "lpcxpresso11u37", "inherits": "default" }, { - "name": "mcb1800", + "name": "lpcxpresso11u68", "inherits": "default" }, { - "name": "ea4088_quickstart", + "name": "lpcxpresso1347", "inherits": "default" }, { - "name": "ea4357", + "name": "lpcxpresso1549", + "inherits": "default" + }, + { + "name": "lpcxpresso1769", + "inherits": "default" + }, + { + "name": "lpcxpresso18s37", "inherits": "default" }, { @@ -252,10 +280,6 @@ "name": "lpcxpresso54628", "inherits": "default" }, - { - "name": "double_m33_express", - "inherits": "default" - }, { "name": "lpcxpresso55s28", "inherits": "default" @@ -264,10 +288,6 @@ "name": "lpcxpresso55s69", "inherits": "default" }, - { - "name": "mcu_link", - "inherits": "default" - }, { "name": "max32650evkit", "inherits": "default" @@ -288,10 +308,6 @@ "name": "max32666fthr", "inherits": "default" }, - { - "name": "apard32690", - "inherits": "default" - }, { "name": "max32690evkit", "inherits": "default" @@ -301,107 +317,103 @@ "inherits": "default" }, { - "name": "frdm_mcxa153", - "inherits": "default" - }, - { - "name": "frdm_mcxn947", + "name": "mbed1768", "inherits": "default" }, { - "name": "mcxn947brk", + "name": "mcb1800", "inherits": "default" }, { - "name": "mm32f327x_mb39", + "name": "mcu_link", "inherits": "default" }, { - "name": "mm32f327x_pitaya_lite", + "name": "mcxn947brk", "inherits": "default" }, { - "name": "msp_exp430f5529lp", + "name": "metro_m0_express", "inherits": "default" }, { - "name": "msp_exp432e401y", + "name": "metro_m4_express", "inherits": "default" }, { - "name": "adafruit_clue", + "name": "metro_m7_1011", "inherits": "default" }, { - "name": "arduino_nano33_ble", + "name": "metro_m7_1011_sd", "inherits": "default" }, { - "name": "circuitplayground_bluefruit", + "name": "mimxrt1010_evk", "inherits": "default" }, { - "name": "feather_nrf52840_express", + "name": "mimxrt1015_evk", "inherits": "default" }, { - "name": "feather_nrf52840_sense", + "name": "mimxrt1020_evk", "inherits": "default" }, { - "name": "itsybitsy_nrf52840", + "name": "mimxrt1024_evk", "inherits": "default" }, { - "name": "pca10056", + "name": "mimxrt1050_evkb", "inherits": "default" }, { - "name": "pca10059", + "name": "mimxrt1060_evk", "inherits": "default" }, { - "name": "pca10095", + "name": "mimxrt1064_evk", "inherits": "default" }, { - "name": "pca10100", + "name": "mimxrt1170_evkb", "inherits": "default" }, { - "name": "portenta_c33", + "name": "mm32f327x_mb39", "inherits": "default" }, { - "name": "ra2a1_ek", + "name": "mm32f327x_pitaya_lite", "inherits": "default" }, { - "name": "ra4m1_ek", + "name": "msp_exp430f5529lp", "inherits": "default" }, { - "name": "ra4m3_ek", + "name": "msp_exp432e401y", "inherits": "default" }, { - "name": "ra6m1_ek", + "name": "nanoch32v203", "inherits": "default" }, { - "name": "ra6m5_ek", + "name": "pca10056", "inherits": "default" }, { - "name": "ra8m1_ek", + "name": "pca10059", "inherits": "default" }, { - "name": "uno_r4", + "name": "pca10095", "inherits": "default" }, { - "name": "feather_rp2040_max3421", + "name": "pca10100", "inherits": "default" }, { @@ -409,107 +421,103 @@ "inherits": "default" }, { - "name": "raspberry_pi_pico", - "inherits": "default" - }, - { - "name": "raspberry_pi_pico2", + "name": "portenta_c33", "inherits": "default" }, { - "name": "cynthion_d11", + "name": "pybadge", "inherits": "default" }, { - "name": "samd11_xplained", + "name": "pyboardv11", "inherits": "default" }, { - "name": "atsamd21_xpro", + "name": "pyportal", "inherits": "default" }, { - "name": "circuitplayground_express", + "name": "qtpy", "inherits": "default" }, { - "name": "curiosity_nano", + "name": "ra2a1_ek", "inherits": "default" }, { - "name": "cynthion_d21", + "name": "ra4m1_ek", "inherits": "default" }, { - "name": "feather_m0_express", + "name": "ra4m3_ek", "inherits": "default" }, { - "name": "itsybitsy_m0", + "name": "ra6m1_ek", "inherits": "default" }, { - "name": "metro_m0_express", + "name": "ra6m5_ek", "inherits": "default" }, { - "name": "qtpy", + "name": "ra8m1_ek", "inherits": "default" }, { - "name": "seeeduino_xiao", + "name": "raspberry_pi_pico", "inherits": "default" }, { - "name": "sparkfun_samd21_mini_usb", + "name": "raspberry_pi_pico2", "inherits": "default" }, { - "name": "trinket_m0", + "name": "raspberrypi_cm4", "inherits": "default" }, { - "name": "d5035_01", + "name": "raspberrypi_zero", "inherits": "default" }, { - "name": "feather_m4_express", + "name": "raspberrypi_zero2", "inherits": "default" }, { - "name": "itsybitsy_m4", + "name": "samd11_xplained", "inherits": "default" }, { - "name": "metro_m4_express", + "name": "same54_xplained", "inherits": "default" }, { - "name": "pybadge", + "name": "samg55_xplained", "inherits": "default" }, { - "name": "pyportal", + "name": "saml22_feather", "inherits": "default" }, { - "name": "same54_xplained", + "name": "seeeduino_xiao", "inherits": "default" }, { - "name": "samg55_xplained", + "name": "sensorwatch_m0", "inherits": "default" }, { - "name": "atsaml21_xpro", + "name": "sipeed_longan_nano", "inherits": "default" }, { - "name": "saml22_feather", + "name": "sparkfun_samd21_mini_usb", "inherits": "default" }, { - "name": "sensorwatch_m0", + "name": "stlinkv3mini", "inherits": "default" }, { @@ -528,10 +536,6 @@ "name": "stm32f072eval", "inherits": "default" }, - { - "name": "stm32f103ze_iar", - "inherits": "default" - }, { "name": "stm32f103_bluepill", "inherits": "default" @@ -541,19 +545,15 @@ "inherits": "default" }, { - "name": "stm32f207nucleo", - "inherits": "default" - }, - { - "name": "stm32f303disco", + "name": "stm32f103ze_iar", "inherits": "default" }, { - "name": "feather_stm32f405", + "name": "stm32f207nucleo", "inherits": "default" }, { - "name": "pyboardv11", + "name": "stm32f303disco", "inherits": "default" }, { @@ -588,10 +588,6 @@ "name": "stm32f439nucleo", "inherits": "default" }, - { - "name": "stlinkv3mini", - "inherits": "default" - }, { "name": "stm32f723disco", "inherits": "default" @@ -616,10 +612,6 @@ "name": "stm32g0b1nucleo", "inherits": "default" }, - { - "name": "b_g474e_dpow1", - "inherits": "default" - }, { "name": "stm32g474nucleo", "inherits": "default" @@ -640,10 +632,6 @@ "name": "stm32h573i_dk", "inherits": "default" }, - { - "name": "daisyseed", - "inherits": "default" - }, { "name": "stm32h723nucleo", "inherits": "default" @@ -660,16 +648,12 @@ "name": "stm32h745disco", "inherits": "default" }, - { - "name": "stm32h750bdk", - "inherits": "default" - }, { "name": "stm32h750_weact", "inherits": "default" }, { - "name": "waveshare_openh743i", + "name": "stm32h750bdk", "inherits": "default" }, { @@ -700,10 +684,6 @@ "name": "stm32l4r5nucleo", "inherits": "default" }, - { - "name": "b_u585i_iot2a", - "inherits": "default" - }, { "name": "stm32u545nucleo", "inherits": "default" @@ -725,7 +705,27 @@ "inherits": "default" }, { - "name": "ek_tm4c123gxl", + "name": "teensy_35", + "inherits": "default" + }, + { + "name": "teensy_40", + "inherits": "default" + }, + { + "name": "teensy_41", + "inherits": "default" + }, + { + "name": "trinket_m0", + "inherits": "default" + }, + { + "name": "uno_r4", + "inherits": "default" + }, + { + "name": "waveshare_openh743i", "inherits": "default" }, { @@ -739,19 +739,64 @@ ], "buildPresets": [ { - "name": "raspberrypi_zero", - "description": "Build preset for the raspberrypi_zero board", - "configurePreset": "raspberrypi_zero" + "name": "adafruit_clue", + "description": "Build preset for the adafruit_clue board", + "configurePreset": "adafruit_clue" }, { - "name": "raspberrypi_cm4", - "description": "Build preset for the raspberrypi_cm4 board", - "configurePreset": "raspberrypi_cm4" + "name": "adafruit_feather_esp32_v2", + "description": "Build preset for the adafruit_feather_esp32_v2 board", + "configurePreset": "adafruit_feather_esp32_v2" }, { - "name": "raspberrypi_zero2", - "description": "Build preset for the raspberrypi_zero2 board", - "configurePreset": "raspberrypi_zero2" + "name": "adafruit_feather_esp32s2", + "description": "Build preset for the adafruit_feather_esp32s2 board", + "configurePreset": "adafruit_feather_esp32s2" + }, + { + "name": "adafruit_feather_esp32s3", + "description": "Build preset for the adafruit_feather_esp32s3 board", + "configurePreset": "adafruit_feather_esp32s3" + }, + { + "name": "adafruit_magtag_29gray", + "description": "Build preset for the adafruit_magtag_29gray board", + "configurePreset": "adafruit_magtag_29gray" + }, + { + "name": "adafruit_metro_esp32s2", + "description": "Build preset for the adafruit_metro_esp32s2 board", + "configurePreset": "adafruit_metro_esp32s2" + }, + { + "name": "apard32690", + "description": "Build preset for the apard32690 board", + "configurePreset": "apard32690" + }, + { + "name": "arduino_nano33_ble", + "description": "Build preset for the arduino_nano33_ble board", + "configurePreset": "arduino_nano33_ble" + }, + { + "name": "atsamd21_xpro", + "description": "Build preset for the atsamd21_xpro board", + "configurePreset": "atsamd21_xpro" + }, + { + "name": "atsaml21_xpro", + "description": "Build preset for the atsaml21_xpro board", + "configurePreset": "atsaml21_xpro" + }, + { + "name": "b_g474e_dpow1", + "description": "Build preset for the b_g474e_dpow1 board", + "configurePreset": "b_g474e_dpow1" + }, + { + "name": "b_u585i_iot2a", + "description": "Build preset for the b_u585i_iot2a board", + "configurePreset": "b_u585i_iot2a" }, { "name": "ch32v103r_r1_1v0", @@ -768,16 +813,41 @@ "description": "Build preset for the ch32v203g_r0_1v0 board", "configurePreset": "ch32v203g_r0_1v0" }, - { - "name": "nanoch32v203", - "description": "Build preset for the nanoch32v203 board", - "configurePreset": "nanoch32v203" - }, { "name": "ch32v307v_r1_1v0", "description": "Build preset for the ch32v307v_r1_1v0 board", "configurePreset": "ch32v307v_r1_1v0" }, + { + "name": "circuitplayground_bluefruit", + "description": "Build preset for the circuitplayground_bluefruit board", + "configurePreset": "circuitplayground_bluefruit" + }, + { + "name": "circuitplayground_express", + "description": "Build preset for the circuitplayground_express board", + "configurePreset": "circuitplayground_express" + }, + { + "name": "curiosity_nano", + "description": "Build preset for the curiosity_nano board", + "configurePreset": "curiosity_nano" + }, + { + "name": "cynthion_d11", + "description": "Build preset for the cynthion_d11 board", + "configurePreset": "cynthion_d11" + }, + { + "name": "cynthion_d21", + "description": "Build preset for the cynthion_d21 board", + "configurePreset": "cynthion_d21" + }, + { + "name": "d5035_01", + "description": "Build preset for the d5035_01 board", + "configurePreset": "d5035_01" + }, { "name": "da14695_dk_usb", "description": "Build preset for the da14695_dk_usb board", @@ -789,29 +859,29 @@ "configurePreset": "da1469x_dk_pro" }, { - "name": "adafruit_feather_esp32s2", - "description": "Build preset for the adafruit_feather_esp32s2 board", - "configurePreset": "adafruit_feather_esp32s2" + "name": "daisyseed", + "description": "Build preset for the daisyseed board", + "configurePreset": "daisyseed" }, { - "name": "adafruit_feather_esp32s3", - "description": "Build preset for the adafruit_feather_esp32s3 board", - "configurePreset": "adafruit_feather_esp32s3" + "name": "double_m33_express", + "description": "Build preset for the double_m33_express board", + "configurePreset": "double_m33_express" }, { - "name": "adafruit_feather_esp32_v2", - "description": "Build preset for the adafruit_feather_esp32_v2 board", - "configurePreset": "adafruit_feather_esp32_v2" + "name": "ea4088_quickstart", + "description": "Build preset for the ea4088_quickstart board", + "configurePreset": "ea4088_quickstart" }, { - "name": "adafruit_magtag_29gray", - "description": "Build preset for the adafruit_magtag_29gray board", - "configurePreset": "adafruit_magtag_29gray" + "name": "ea4357", + "description": "Build preset for the ea4357 board", + "configurePreset": "ea4357" }, { - "name": "adafruit_metro_esp32s2", - "description": "Build preset for the adafruit_metro_esp32s2 board", - "configurePreset": "adafruit_metro_esp32s2" + "name": "ek_tm4c123gxl", + "description": "Build preset for the ek_tm4c123gxl board", + "configurePreset": "ek_tm4c123gxl" }, { "name": "espressif_addax_1", @@ -864,105 +934,90 @@ "configurePreset": "f1c100s" }, { - "name": "fomu", - "description": "Build preset for the fomu board", - "configurePreset": "fomu" + "name": "feather_m0_express", + "description": "Build preset for the feather_m0_express board", + "configurePreset": "feather_m0_express" }, { - "name": "sipeed_longan_nano", - "description": "Build preset for the sipeed_longan_nano board", - "configurePreset": "sipeed_longan_nano" + "name": "feather_m4_express", + "description": "Build preset for the feather_m4_express board", + "configurePreset": "feather_m4_express" }, { - "name": "metro_m7_1011", - "description": "Build preset for the metro_m7_1011 board", - "configurePreset": "metro_m7_1011" + "name": "feather_nrf52840_express", + "description": "Build preset for the feather_nrf52840_express board", + "configurePreset": "feather_nrf52840_express" }, { - "name": "metro_m7_1011_sd", - "description": "Build preset for the metro_m7_1011_sd board", - "configurePreset": "metro_m7_1011_sd" + "name": "feather_nrf52840_sense", + "description": "Build preset for the feather_nrf52840_sense board", + "configurePreset": "feather_nrf52840_sense" }, { - "name": "mimxrt1010_evk", - "description": "Build preset for the mimxrt1010_evk board", - "configurePreset": "mimxrt1010_evk" + "name": "feather_rp2040_max3421", + "description": "Build preset for the feather_rp2040_max3421 board", + "configurePreset": "feather_rp2040_max3421" }, { - "name": "mimxrt1015_evk", - "description": "Build preset for the mimxrt1015_evk board", - "configurePreset": "mimxrt1015_evk" + "name": "feather_stm32f405", + "description": "Build preset for the feather_stm32f405 board", + "configurePreset": "feather_stm32f405" }, { - "name": "mimxrt1020_evk", - "description": "Build preset for the mimxrt1020_evk board", - "configurePreset": "mimxrt1020_evk" + "name": "fomu", + "description": "Build preset for the fomu board", + "configurePreset": "fomu" }, { - "name": "mimxrt1024_evk", - "description": "Build preset for the mimxrt1024_evk board", - "configurePreset": "mimxrt1024_evk" + "name": "frdm_k32l2a4s", + "description": "Build preset for the frdm_k32l2a4s board", + "configurePreset": "frdm_k32l2a4s" }, { - "name": "mimxrt1050_evkb", - "description": "Build preset for the mimxrt1050_evkb board", - "configurePreset": "mimxrt1050_evkb" + "name": "frdm_k32l2b", + "description": "Build preset for the frdm_k32l2b board", + "configurePreset": "frdm_k32l2b" }, { - "name": "mimxrt1060_evk", - "description": "Build preset for the mimxrt1060_evk board", - "configurePreset": "mimxrt1060_evk" + "name": "frdm_k64f", + "description": "Build preset for the frdm_k64f board", + "configurePreset": "frdm_k64f" }, { - "name": "mimxrt1064_evk", - "description": "Build preset for the mimxrt1064_evk board", - "configurePreset": "mimxrt1064_evk" + "name": "frdm_kl25z", + "description": "Build preset for the frdm_kl25z board", + "configurePreset": "frdm_kl25z" }, { - "name": "mimxrt1170_evkb", - "description": "Build preset for the mimxrt1170_evkb board", - "configurePreset": "mimxrt1170_evkb" + "name": "frdm_mcxa153", + "description": "Build preset for the frdm_mcxa153 board", + "configurePreset": "frdm_mcxa153" }, { - "name": "teensy_40", - "description": "Build preset for the teensy_40 board", - "configurePreset": "teensy_40" - }, - { - "name": "teensy_41", - "description": "Build preset for the teensy_41 board", - "configurePreset": "teensy_41" - }, - { - "name": "frdm_k64f", - "description": "Build preset for the frdm_k64f board", - "configurePreset": "frdm_k64f" + "name": "frdm_mcxn947", + "description": "Build preset for the frdm_mcxn947 board", + "configurePreset": "frdm_mcxn947" }, { - "name": "teensy_35", - "description": "Build preset for the teensy_35 board", - "configurePreset": "teensy_35" + "name": "itsybitsy_m0", + "description": "Build preset for the itsybitsy_m0 board", + "configurePreset": "itsybitsy_m0" }, { - "name": "frdm_k32l2a4s", - "description": "Build preset for the frdm_k32l2a4s board", - "configurePreset": "frdm_k32l2a4s" + "name": "itsybitsy_m4", + "description": "Build preset for the itsybitsy_m4 board", + "configurePreset": "itsybitsy_m4" }, { - "name": "frdm_k32l2b", - "description": "Build preset for the frdm_k32l2b board", - "configurePreset": "frdm_k32l2b" + "name": "itsybitsy_nrf52840", + "description": "Build preset for the itsybitsy_nrf52840 board", + "configurePreset": "itsybitsy_nrf52840" }, { "name": "kuiic", "description": "Build preset for the kuiic board", "configurePreset": "kuiic" }, - { - "name": "frdm_kl25z", - "description": "Build preset for the frdm_kl25z board", - "configurePreset": "frdm_kl25z" - }, { "name": "lpcxpresso11u37", "description": "Build preset for the lpcxpresso11u37 board", @@ -988,31 +1043,11 @@ "description": "Build preset for the lpcxpresso1769 board", "configurePreset": "lpcxpresso1769" }, - { - "name": "mbed1768", - "description": "Build preset for the mbed1768 board", - "configurePreset": "mbed1768" - }, { "name": "lpcxpresso18s37", "description": "Build preset for the lpcxpresso18s37 board", "configurePreset": "lpcxpresso18s37" }, - { - "name": "mcb1800", - "description": "Build preset for the mcb1800 board", - "configurePreset": "mcb1800" - }, - { - "name": "ea4088_quickstart", - "description": "Build preset for the ea4088_quickstart board", - "configurePreset": "ea4088_quickstart" - }, - { - "name": "ea4357", - "description": "Build preset for the ea4357 board", - "configurePreset": "ea4357" - }, { "name": "lpcxpresso43s67", "description": "Build preset for the lpcxpresso43s67 board", @@ -1038,11 +1073,6 @@ "description": "Build preset for the lpcxpresso54628 board", "configurePreset": "lpcxpresso54628" }, - { - "name": "double_m33_express", - "description": "Build preset for the double_m33_express board", - "configurePreset": "double_m33_express" - }, { "name": "lpcxpresso55s28", "description": "Build preset for the lpcxpresso55s28 board", @@ -1053,11 +1083,6 @@ "description": "Build preset for the lpcxpresso55s69 board", "configurePreset": "lpcxpresso55s69" }, - { - "name": "mcu_link", - "description": "Build preset for the mcu_link board", - "configurePreset": "mcu_link" - }, { "name": "max32650evkit", "description": "Build preset for the max32650evkit board", @@ -1083,11 +1108,6 @@ "description": "Build preset for the max32666fthr board", "configurePreset": "max32666fthr" }, - { - "name": "apard32690", - "description": "Build preset for the apard32690 board", - "configurePreset": "apard32690" - }, { "name": "max32690evkit", "description": "Build preset for the max32690evkit board", @@ -1099,20 +1119,85 @@ "configurePreset": "max78002evkit" }, { - "name": "frdm_mcxa153", - "description": "Build preset for the frdm_mcxa153 board", - "configurePreset": "frdm_mcxa153" + "name": "mbed1768", + "description": "Build preset for the mbed1768 board", + "configurePreset": "mbed1768" }, { - "name": "frdm_mcxn947", - "description": "Build preset for the frdm_mcxn947 board", - "configurePreset": "frdm_mcxn947" + "name": "mcb1800", + "description": "Build preset for the mcb1800 board", + "configurePreset": "mcb1800" + }, + { + "name": "mcu_link", + "description": "Build preset for the mcu_link board", + "configurePreset": "mcu_link" }, { "name": "mcxn947brk", "description": "Build preset for the mcxn947brk board", "configurePreset": "mcxn947brk" }, + { + "name": "metro_m0_express", + "description": "Build preset for the metro_m0_express board", + "configurePreset": "metro_m0_express" + }, + { + "name": "metro_m4_express", + "description": "Build preset for the metro_m4_express board", + "configurePreset": "metro_m4_express" + }, + { + "name": "metro_m7_1011", + "description": "Build preset for the metro_m7_1011 board", + "configurePreset": "metro_m7_1011" + }, + { + "name": "metro_m7_1011_sd", + "description": "Build preset for the metro_m7_1011_sd board", + "configurePreset": "metro_m7_1011_sd" + }, + { + "name": "mimxrt1010_evk", + "description": "Build preset for the mimxrt1010_evk board", + "configurePreset": "mimxrt1010_evk" + }, + { + "name": "mimxrt1015_evk", + "description": "Build preset for the mimxrt1015_evk board", + "configurePreset": "mimxrt1015_evk" + }, + { + "name": "mimxrt1020_evk", + "description": "Build preset for the mimxrt1020_evk board", + "configurePreset": "mimxrt1020_evk" + }, + { + "name": "mimxrt1024_evk", + "description": "Build preset for the mimxrt1024_evk board", + "configurePreset": "mimxrt1024_evk" + }, + { + "name": "mimxrt1050_evkb", + "description": "Build preset for the mimxrt1050_evkb board", + "configurePreset": "mimxrt1050_evkb" + }, + { + "name": "mimxrt1060_evk", + "description": "Build preset for the mimxrt1060_evk board", + "configurePreset": "mimxrt1060_evk" + }, + { + "name": "mimxrt1064_evk", + "description": "Build preset for the mimxrt1064_evk board", + "configurePreset": "mimxrt1064_evk" + }, + { + "name": "mimxrt1170_evkb", + "description": "Build preset for the mimxrt1170_evkb board", + "configurePreset": "mimxrt1170_evkb" + }, { "name": "mm32f327x_mb39", "description": "Build preset for the mm32f327x_mb39 board", @@ -1134,34 +1219,9 @@ "configurePreset": "msp_exp432e401y" }, { - "name": "adafruit_clue", - "description": "Build preset for the adafruit_clue board", - "configurePreset": "adafruit_clue" - }, - { - "name": "arduino_nano33_ble", - "description": "Build preset for the arduino_nano33_ble board", - "configurePreset": "arduino_nano33_ble" - }, - { - "name": "circuitplayground_bluefruit", - "description": "Build preset for the circuitplayground_bluefruit board", - "configurePreset": "circuitplayground_bluefruit" - }, - { - "name": "feather_nrf52840_express", - "description": "Build preset for the feather_nrf52840_express board", - "configurePreset": "feather_nrf52840_express" - }, - { - "name": "feather_nrf52840_sense", - "description": "Build preset for the feather_nrf52840_sense board", - "configurePreset": "feather_nrf52840_sense" - }, - { - "name": "itsybitsy_nrf52840", - "description": "Build preset for the itsybitsy_nrf52840 board", - "configurePreset": "itsybitsy_nrf52840" + "name": "nanoch32v203", + "description": "Build preset for the nanoch32v203 board", + "configurePreset": "nanoch32v203" }, { "name": "pca10056", @@ -1183,11 +1243,36 @@ "description": "Build preset for the pca10100 board", "configurePreset": "pca10100" }, + { + "name": "pico_sdk", + "description": "Build preset for the pico_sdk board", + "configurePreset": "pico_sdk" + }, { "name": "portenta_c33", "description": "Build preset for the portenta_c33 board", "configurePreset": "portenta_c33" }, + { + "name": "pybadge", + "description": "Build preset for the pybadge board", + "configurePreset": "pybadge" + }, + { + "name": "pyboardv11", + "description": "Build preset for the pyboardv11 board", + "configurePreset": "pyboardv11" + }, + { + "name": "pyportal", + "description": "Build preset for the pyportal board", + "configurePreset": "pyportal" + }, + { + "name": "qtpy", + "description": "Build preset for the qtpy board", + "configurePreset": "qtpy" + }, { "name": "ra2a1_ek", "description": "Build preset for the ra2a1_ek board", @@ -1218,21 +1303,6 @@ "description": "Build preset for the ra8m1_ek board", "configurePreset": "ra8m1_ek" }, - { - "name": "uno_r4", - "description": "Build preset for the uno_r4 board", - "configurePreset": "uno_r4" - }, - { - "name": "feather_rp2040_max3421", - "description": "Build preset for the feather_rp2040_max3421 board", - "configurePreset": "feather_rp2040_max3421" - }, - { - "name": "pico_sdk", - "description": "Build preset for the pico_sdk board", - "configurePreset": "pico_sdk" - }, { "name": "raspberry_pi_pico", "description": "Build preset for the raspberry_pi_pico board", @@ -1244,9 +1314,19 @@ "configurePreset": "raspberry_pi_pico2" }, { - "name": "cynthion_d11", - "description": "Build preset for the cynthion_d11 board", - "configurePreset": "cynthion_d11" + "name": "raspberrypi_cm4", + "description": "Build preset for the raspberrypi_cm4 board", + "configurePreset": "raspberrypi_cm4" + }, + { + "name": "raspberrypi_zero", + "description": "Build preset for the raspberrypi_zero board", + "configurePreset": "raspberrypi_zero" + }, + { + "name": "raspberrypi_zero2", + "description": "Build preset for the raspberrypi_zero2 board", + "configurePreset": "raspberrypi_zero2" }, { "name": "samd11_xplained", @@ -1254,44 +1334,19 @@ "configurePreset": "samd11_xplained" }, { - "name": "atsamd21_xpro", - "description": "Build preset for the atsamd21_xpro board", - "configurePreset": "atsamd21_xpro" + "name": "same54_xplained", + "description": "Build preset for the same54_xplained board", + "configurePreset": "same54_xplained" }, { - "name": "circuitplayground_express", - "description": "Build preset for the circuitplayground_express board", - "configurePreset": "circuitplayground_express" + "name": "samg55_xplained", + "description": "Build preset for the samg55_xplained board", + "configurePreset": "samg55_xplained" }, { - "name": "curiosity_nano", - "description": "Build preset for the curiosity_nano board", - "configurePreset": "curiosity_nano" - }, - { - "name": "cynthion_d21", - "description": "Build preset for the cynthion_d21 board", - "configurePreset": "cynthion_d21" - }, - { - "name": "feather_m0_express", - "description": "Build preset for the feather_m0_express board", - "configurePreset": "feather_m0_express" - }, - { - "name": "itsybitsy_m0", - "description": "Build preset for the itsybitsy_m0 board", - "configurePreset": "itsybitsy_m0" - }, - { - "name": "metro_m0_express", - "description": "Build preset for the metro_m0_express board", - "configurePreset": "metro_m0_express" - }, - { - "name": "qtpy", - "description": "Build preset for the qtpy board", - "configurePreset": "qtpy" + "name": "saml22_feather", + "description": "Build preset for the saml22_feather board", + "configurePreset": "saml22_feather" }, { "name": "seeeduino_xiao", @@ -1299,69 +1354,24 @@ "configurePreset": "seeeduino_xiao" }, { - "name": "sparkfun_samd21_mini_usb", - "description": "Build preset for the sparkfun_samd21_mini_usb board", - "configurePreset": "sparkfun_samd21_mini_usb" - }, - { - "name": "trinket_m0", - "description": "Build preset for the trinket_m0 board", - "configurePreset": "trinket_m0" - }, - { - "name": "d5035_01", - "description": "Build preset for the d5035_01 board", - "configurePreset": "d5035_01" - }, - { - "name": "feather_m4_express", - "description": "Build preset for the feather_m4_express board", - "configurePreset": "feather_m4_express" - }, - { - "name": "itsybitsy_m4", - "description": "Build preset for the itsybitsy_m4 board", - "configurePreset": "itsybitsy_m4" - }, - { - "name": "metro_m4_express", - "description": "Build preset for the metro_m4_express board", - "configurePreset": "metro_m4_express" - }, - { - "name": "pybadge", - "description": "Build preset for the pybadge board", - "configurePreset": "pybadge" - }, - { - "name": "pyportal", - "description": "Build preset for the pyportal board", - "configurePreset": "pyportal" - }, - { - "name": "same54_xplained", - "description": "Build preset for the same54_xplained board", - "configurePreset": "same54_xplained" - }, - { - "name": "samg55_xplained", - "description": "Build preset for the samg55_xplained board", - "configurePreset": "samg55_xplained" + "name": "sensorwatch_m0", + "description": "Build preset for the sensorwatch_m0 board", + "configurePreset": "sensorwatch_m0" }, { - "name": "atsaml21_xpro", - "description": "Build preset for the atsaml21_xpro board", - "configurePreset": "atsaml21_xpro" + "name": "sipeed_longan_nano", + "description": "Build preset for the sipeed_longan_nano board", + "configurePreset": "sipeed_longan_nano" }, { - "name": "saml22_feather", - "description": "Build preset for the saml22_feather board", - "configurePreset": "saml22_feather" + "name": "sparkfun_samd21_mini_usb", + "description": "Build preset for the sparkfun_samd21_mini_usb board", + "configurePreset": "sparkfun_samd21_mini_usb" }, { - "name": "sensorwatch_m0", - "description": "Build preset for the sensorwatch_m0 board", - "configurePreset": "sensorwatch_m0" + "name": "stlinkv3mini", + "description": "Build preset for the stlinkv3mini board", + "configurePreset": "stlinkv3mini" }, { "name": "stm32c071nucleo", @@ -1383,11 +1393,6 @@ "description": "Build preset for the stm32f072eval board", "configurePreset": "stm32f072eval" }, - { - "name": "stm32f103ze_iar", - "description": "Build preset for the stm32f103ze_iar board", - "configurePreset": "stm32f103ze_iar" - }, { "name": "stm32f103_bluepill", "description": "Build preset for the stm32f103_bluepill board", @@ -1398,6 +1403,11 @@ "description": "Build preset for the stm32f103_mini_2 board", "configurePreset": "stm32f103_mini_2" }, + { + "name": "stm32f103ze_iar", + "description": "Build preset for the stm32f103ze_iar board", + "configurePreset": "stm32f103ze_iar" + }, { "name": "stm32f207nucleo", "description": "Build preset for the stm32f207nucleo board", @@ -1408,16 +1418,6 @@ "description": "Build preset for the stm32f303disco board", "configurePreset": "stm32f303disco" }, - { - "name": "feather_stm32f405", - "description": "Build preset for the feather_stm32f405 board", - "configurePreset": "feather_stm32f405" - }, - { - "name": "pyboardv11", - "description": "Build preset for the pyboardv11 board", - "configurePreset": "pyboardv11" - }, { "name": "stm32f401blackpill", "description": "Build preset for the stm32f401blackpill board", @@ -1458,11 +1458,6 @@ "description": "Build preset for the stm32f439nucleo board", "configurePreset": "stm32f439nucleo" }, - { - "name": "stlinkv3mini", - "description": "Build preset for the stlinkv3mini board", - "configurePreset": "stlinkv3mini" - }, { "name": "stm32f723disco", "description": "Build preset for the stm32f723disco board", @@ -1493,11 +1488,6 @@ "description": "Build preset for the stm32g0b1nucleo board", "configurePreset": "stm32g0b1nucleo" }, - { - "name": "b_g474e_dpow1", - "description": "Build preset for the b_g474e_dpow1 board", - "configurePreset": "b_g474e_dpow1" - }, { "name": "stm32g474nucleo", "description": "Build preset for the stm32g474nucleo board", @@ -1523,11 +1513,6 @@ "description": "Build preset for the stm32h573i_dk board", "configurePreset": "stm32h573i_dk" }, - { - "name": "daisyseed", - "description": "Build preset for the daisyseed board", - "configurePreset": "daisyseed" - }, { "name": "stm32h723nucleo", "description": "Build preset for the stm32h723nucleo board", @@ -1548,20 +1533,15 @@ "description": "Build preset for the stm32h745disco board", "configurePreset": "stm32h745disco" }, - { - "name": "stm32h750bdk", - "description": "Build preset for the stm32h750bdk board", - "configurePreset": "stm32h750bdk" - }, { "name": "stm32h750_weact", "description": "Build preset for the stm32h750_weact board", "configurePreset": "stm32h750_weact" }, { - "name": "waveshare_openh743i", - "description": "Build preset for the waveshare_openh743i board", - "configurePreset": "waveshare_openh743i" + "name": "stm32h750bdk", + "description": "Build preset for the stm32h750bdk board", + "configurePreset": "stm32h750bdk" }, { "name": "stm32h7s3nucleo", @@ -1598,11 +1578,6 @@ "description": "Build preset for the stm32l4r5nucleo board", "configurePreset": "stm32l4r5nucleo" }, - { - "name": "b_u585i_iot2a", - "description": "Build preset for the b_u585i_iot2a board", - "configurePreset": "b_u585i_iot2a" - }, { "name": "stm32u545nucleo", "description": "Build preset for the stm32u545nucleo board", @@ -1629,9 +1604,34 @@ "configurePreset": "stm32wb55nucleo" }, { - "name": "ek_tm4c123gxl", - "description": "Build preset for the ek_tm4c123gxl board", - "configurePreset": "ek_tm4c123gxl" + "name": "teensy_35", + "description": "Build preset for the teensy_35 board", + "configurePreset": "teensy_35" + }, + { + "name": "teensy_40", + "description": "Build preset for the teensy_40 board", + "configurePreset": "teensy_40" + }, + { + "name": "teensy_41", + "description": "Build preset for the teensy_41 board", + "configurePreset": "teensy_41" + }, + { + "name": "trinket_m0", + "description": "Build preset for the trinket_m0 board", + "configurePreset": "trinket_m0" + }, + { + "name": "uno_r4", + "description": "Build preset for the uno_r4 board", + "configurePreset": "uno_r4" + }, + { + "name": "waveshare_openh743i", + "description": "Build preset for the waveshare_openh743i board", + "configurePreset": "waveshare_openh743i" }, { "name": "xmc4500_relax", @@ -1646,41 +1646,158 @@ ], "workflowPresets": [ { - "name": "raspberrypi_zero", + "name": "adafruit_clue", "steps": [ { "type": "configure", - "name": "raspberrypi_zero" + "name": "adafruit_clue" }, { "type": "build", - "name": "raspberrypi_zero" + "name": "adafruit_clue" } ] }, { - "name": "raspberrypi_cm4", + "name": "adafruit_feather_esp32_v2", "steps": [ { "type": "configure", - "name": "raspberrypi_cm4" + "name": "adafruit_feather_esp32_v2" }, { "type": "build", - "name": "raspberrypi_cm4" + "name": "adafruit_feather_esp32_v2" } ] }, { - "name": "raspberrypi_zero2", + "name": "adafruit_feather_esp32s2", "steps": [ { "type": "configure", - "name": "raspberrypi_zero2" + "name": "adafruit_feather_esp32s2" }, { "type": "build", - "name": "raspberrypi_zero2" + "name": "adafruit_feather_esp32s2" + } + ] + }, + { + "name": "adafruit_feather_esp32s3", + "steps": [ + { + "type": "configure", + "name": "adafruit_feather_esp32s3" + }, + { + "type": "build", + "name": "adafruit_feather_esp32s3" + } + ] + }, + { + "name": "adafruit_magtag_29gray", + "steps": [ + { + "type": "configure", + "name": "adafruit_magtag_29gray" + }, + { + "type": "build", + "name": "adafruit_magtag_29gray" + } + ] + }, + { + "name": "adafruit_metro_esp32s2", + "steps": [ + { + "type": "configure", + "name": "adafruit_metro_esp32s2" + }, + { + "type": "build", + "name": "adafruit_metro_esp32s2" + } + ] + }, + { + "name": "apard32690", + "steps": [ + { + "type": "configure", + "name": "apard32690" + }, + { + "type": "build", + "name": "apard32690" + } + ] + }, + { + "name": "arduino_nano33_ble", + "steps": [ + { + "type": "configure", + "name": "arduino_nano33_ble" + }, + { + "type": "build", + "name": "arduino_nano33_ble" + } + ] + }, + { + "name": "atsamd21_xpro", + "steps": [ + { + "type": "configure", + "name": "atsamd21_xpro" + }, + { + "type": "build", + "name": "atsamd21_xpro" + } + ] + }, + { + "name": "atsaml21_xpro", + "steps": [ + { + "type": "configure", + "name": "atsaml21_xpro" + }, + { + "type": "build", + "name": "atsaml21_xpro" + } + ] + }, + { + "name": "b_g474e_dpow1", + "steps": [ + { + "type": "configure", + "name": "b_g474e_dpow1" + }, + { + "type": "build", + "name": "b_g474e_dpow1" + } + ] + }, + { + "name": "b_u585i_iot2a", + "steps": [ + { + "type": "configure", + "name": "b_u585i_iot2a" + }, + { + "type": "build", + "name": "b_u585i_iot2a" } ] }, @@ -1724,28 +1841,93 @@ ] }, { - "name": "nanoch32v203", + "name": "ch32v307v_r1_1v0", "steps": [ { "type": "configure", - "name": "nanoch32v203" + "name": "ch32v307v_r1_1v0" }, { "type": "build", - "name": "nanoch32v203" + "name": "ch32v307v_r1_1v0" } ] }, { - "name": "ch32v307v_r1_1v0", + "name": "circuitplayground_bluefruit", "steps": [ { "type": "configure", - "name": "ch32v307v_r1_1v0" + "name": "circuitplayground_bluefruit" }, { "type": "build", - "name": "ch32v307v_r1_1v0" + "name": "circuitplayground_bluefruit" + } + ] + }, + { + "name": "circuitplayground_express", + "steps": [ + { + "type": "configure", + "name": "circuitplayground_express" + }, + { + "type": "build", + "name": "circuitplayground_express" + } + ] + }, + { + "name": "curiosity_nano", + "steps": [ + { + "type": "configure", + "name": "curiosity_nano" + }, + { + "type": "build", + "name": "curiosity_nano" + } + ] + }, + { + "name": "cynthion_d11", + "steps": [ + { + "type": "configure", + "name": "cynthion_d11" + }, + { + "type": "build", + "name": "cynthion_d11" + } + ] + }, + { + "name": "cynthion_d21", + "steps": [ + { + "type": "configure", + "name": "cynthion_d21" + }, + { + "type": "build", + "name": "cynthion_d21" + } + ] + }, + { + "name": "d5035_01", + "steps": [ + { + "type": "configure", + "name": "d5035_01" + }, + { + "type": "build", + "name": "d5035_01" } ] }, @@ -1776,67 +1958,67 @@ ] }, { - "name": "adafruit_feather_esp32s2", + "name": "daisyseed", "steps": [ { "type": "configure", - "name": "adafruit_feather_esp32s2" + "name": "daisyseed" }, { "type": "build", - "name": "adafruit_feather_esp32s2" + "name": "daisyseed" } ] }, { - "name": "adafruit_feather_esp32s3", + "name": "double_m33_express", "steps": [ { "type": "configure", - "name": "adafruit_feather_esp32s3" + "name": "double_m33_express" }, { "type": "build", - "name": "adafruit_feather_esp32s3" + "name": "double_m33_express" } ] }, { - "name": "adafruit_feather_esp32_v2", + "name": "ea4088_quickstart", "steps": [ { "type": "configure", - "name": "adafruit_feather_esp32_v2" + "name": "ea4088_quickstart" }, { "type": "build", - "name": "adafruit_feather_esp32_v2" + "name": "ea4088_quickstart" } ] }, { - "name": "adafruit_magtag_29gray", + "name": "ea4357", "steps": [ { "type": "configure", - "name": "adafruit_magtag_29gray" + "name": "ea4357" }, { "type": "build", - "name": "adafruit_magtag_29gray" + "name": "ea4357" } ] }, { - "name": "adafruit_metro_esp32s2", + "name": "ek_tm4c123gxl", "steps": [ { "type": "configure", - "name": "adafruit_metro_esp32s2" + "name": "ek_tm4c123gxl" }, { "type": "build", - "name": "adafruit_metro_esp32s2" + "name": "ek_tm4c123gxl" } ] }, @@ -1971,236 +2153,210 @@ ] }, { - "name": "fomu", - "steps": [ - { - "type": "configure", - "name": "fomu" - }, - { - "type": "build", - "name": "fomu" - } - ] - }, - { - "name": "sipeed_longan_nano", - "steps": [ - { - "type": "configure", - "name": "sipeed_longan_nano" - }, - { - "type": "build", - "name": "sipeed_longan_nano" - } - ] - }, - { - "name": "metro_m7_1011", + "name": "feather_m0_express", "steps": [ { "type": "configure", - "name": "metro_m7_1011" + "name": "feather_m0_express" }, { "type": "build", - "name": "metro_m7_1011" + "name": "feather_m0_express" } ] }, { - "name": "metro_m7_1011_sd", + "name": "feather_m4_express", "steps": [ { "type": "configure", - "name": "metro_m7_1011_sd" + "name": "feather_m4_express" }, { "type": "build", - "name": "metro_m7_1011_sd" + "name": "feather_m4_express" } ] }, { - "name": "mimxrt1010_evk", + "name": "feather_nrf52840_express", "steps": [ { "type": "configure", - "name": "mimxrt1010_evk" + "name": "feather_nrf52840_express" }, { "type": "build", - "name": "mimxrt1010_evk" + "name": "feather_nrf52840_express" } ] }, { - "name": "mimxrt1015_evk", + "name": "feather_nrf52840_sense", "steps": [ { "type": "configure", - "name": "mimxrt1015_evk" + "name": "feather_nrf52840_sense" }, { "type": "build", - "name": "mimxrt1015_evk" + "name": "feather_nrf52840_sense" } ] }, { - "name": "mimxrt1020_evk", + "name": "feather_rp2040_max3421", "steps": [ { "type": "configure", - "name": "mimxrt1020_evk" + "name": "feather_rp2040_max3421" }, { "type": "build", - "name": "mimxrt1020_evk" + "name": "feather_rp2040_max3421" } ] }, { - "name": "mimxrt1024_evk", + "name": "feather_stm32f405", "steps": [ { "type": "configure", - "name": "mimxrt1024_evk" + "name": "feather_stm32f405" }, { "type": "build", - "name": "mimxrt1024_evk" + "name": "feather_stm32f405" } ] }, { - "name": "mimxrt1050_evkb", + "name": "fomu", "steps": [ { "type": "configure", - "name": "mimxrt1050_evkb" + "name": "fomu" }, { "type": "build", - "name": "mimxrt1050_evkb" + "name": "fomu" } ] }, { - "name": "mimxrt1060_evk", + "name": "frdm_k32l2a4s", "steps": [ { "type": "configure", - "name": "mimxrt1060_evk" + "name": "frdm_k32l2a4s" }, { "type": "build", - "name": "mimxrt1060_evk" + "name": "frdm_k32l2a4s" } ] }, { - "name": "mimxrt1064_evk", + "name": "frdm_k32l2b", "steps": [ { "type": "configure", - "name": "mimxrt1064_evk" + "name": "frdm_k32l2b" }, { "type": "build", - "name": "mimxrt1064_evk" + "name": "frdm_k32l2b" } ] }, { - "name": "mimxrt1170_evkb", + "name": "frdm_k64f", "steps": [ { "type": "configure", - "name": "mimxrt1170_evkb" + "name": "frdm_k64f" }, { "type": "build", - "name": "mimxrt1170_evkb" + "name": "frdm_k64f" } ] }, { - "name": "teensy_40", + "name": "frdm_kl25z", "steps": [ { "type": "configure", - "name": "teensy_40" + "name": "frdm_kl25z" }, { "type": "build", - "name": "teensy_40" + "name": "frdm_kl25z" } ] }, { - "name": "teensy_41", + "name": "frdm_mcxa153", "steps": [ { "type": "configure", - "name": "teensy_41" + "name": "frdm_mcxa153" }, { "type": "build", - "name": "teensy_41" + "name": "frdm_mcxa153" } ] }, { - "name": "frdm_k64f", + "name": "frdm_mcxn947", "steps": [ { "type": "configure", - "name": "frdm_k64f" + "name": "frdm_mcxn947" }, { "type": "build", - "name": "frdm_k64f" + "name": "frdm_mcxn947" } ] }, { - "name": "teensy_35", + "name": "itsybitsy_m0", "steps": [ { "type": "configure", - "name": "teensy_35" + "name": "itsybitsy_m0" }, { "type": "build", - "name": "teensy_35" + "name": "itsybitsy_m0" } ] }, { - "name": "frdm_k32l2a4s", + "name": "itsybitsy_m4", "steps": [ { "type": "configure", - "name": "frdm_k32l2a4s" + "name": "itsybitsy_m4" }, { "type": "build", - "name": "frdm_k32l2a4s" + "name": "itsybitsy_m4" } ] }, { - "name": "frdm_k32l2b", + "name": "itsybitsy_nrf52840", "steps": [ { "type": "configure", - "name": "frdm_k32l2b" + "name": "itsybitsy_nrf52840" }, { "type": "build", - "name": "frdm_k32l2b" + "name": "itsybitsy_nrf52840" } ] }, @@ -2217,19 +2373,6 @@ } ] }, - { - "name": "frdm_kl25z", - "steps": [ - { - "type": "configure", - "name": "frdm_kl25z" - }, - { - "type": "build", - "name": "frdm_kl25z" - } - ] - }, { "name": "lpcxpresso11u37", "steps": [ @@ -2295,19 +2438,6 @@ } ] }, - { - "name": "mbed1768", - "steps": [ - { - "type": "configure", - "name": "mbed1768" - }, - { - "type": "build", - "name": "mbed1768" - } - ] - }, { "name": "lpcxpresso18s37", "steps": [ @@ -2321,45 +2451,6 @@ } ] }, - { - "name": "mcb1800", - "steps": [ - { - "type": "configure", - "name": "mcb1800" - }, - { - "type": "build", - "name": "mcb1800" - } - ] - }, - { - "name": "ea4088_quickstart", - "steps": [ - { - "type": "configure", - "name": "ea4088_quickstart" - }, - { - "type": "build", - "name": "ea4088_quickstart" - } - ] - }, - { - "name": "ea4357", - "steps": [ - { - "type": "configure", - "name": "ea4357" - }, - { - "type": "build", - "name": "ea4357" - } - ] - }, { "name": "lpcxpresso43s67", "steps": [ @@ -2425,19 +2516,6 @@ } ] }, - { - "name": "double_m33_express", - "steps": [ - { - "type": "configure", - "name": "double_m33_express" - }, - { - "type": "build", - "name": "double_m33_express" - } - ] - }, { "name": "lpcxpresso55s28", "steps": [ @@ -2464,19 +2542,6 @@ } ] }, - { - "name": "mcu_link", - "steps": [ - { - "type": "configure", - "name": "mcu_link" - }, - { - "type": "build", - "name": "mcu_link" - } - ] - }, { "name": "max32650evkit", "steps": [ @@ -2525,748 +2590,709 @@ }, { "type": "build", - "name": "max32666evkit" - } - ] - }, - { - "name": "max32666fthr", - "steps": [ - { - "type": "configure", - "name": "max32666fthr" - }, - { - "type": "build", - "name": "max32666fthr" - } - ] - }, - { - "name": "apard32690", - "steps": [ - { - "type": "configure", - "name": "apard32690" - }, - { - "type": "build", - "name": "apard32690" - } - ] - }, - { - "name": "max32690evkit", - "steps": [ - { - "type": "configure", - "name": "max32690evkit" - }, - { - "type": "build", - "name": "max32690evkit" + "name": "max32666evkit" } ] }, { - "name": "max78002evkit", + "name": "max32666fthr", "steps": [ { "type": "configure", - "name": "max78002evkit" + "name": "max32666fthr" }, { "type": "build", - "name": "max78002evkit" + "name": "max32666fthr" } ] }, { - "name": "frdm_mcxa153", + "name": "max32690evkit", "steps": [ { "type": "configure", - "name": "frdm_mcxa153" + "name": "max32690evkit" }, { "type": "build", - "name": "frdm_mcxa153" + "name": "max32690evkit" } ] }, { - "name": "frdm_mcxn947", + "name": "max78002evkit", "steps": [ { "type": "configure", - "name": "frdm_mcxn947" + "name": "max78002evkit" }, { "type": "build", - "name": "frdm_mcxn947" + "name": "max78002evkit" } ] }, { - "name": "mcxn947brk", + "name": "mbed1768", "steps": [ { "type": "configure", - "name": "mcxn947brk" + "name": "mbed1768" }, { "type": "build", - "name": "mcxn947brk" + "name": "mbed1768" } ] }, { - "name": "mm32f327x_mb39", + "name": "mcb1800", "steps": [ { "type": "configure", - "name": "mm32f327x_mb39" + "name": "mcb1800" }, { "type": "build", - "name": "mm32f327x_mb39" + "name": "mcb1800" } ] }, { - "name": "mm32f327x_pitaya_lite", + "name": "mcu_link", "steps": [ { "type": "configure", - "name": "mm32f327x_pitaya_lite" + "name": "mcu_link" }, { "type": "build", - "name": "mm32f327x_pitaya_lite" + "name": "mcu_link" } ] }, { - "name": "msp_exp430f5529lp", + "name": "mcxn947brk", "steps": [ { "type": "configure", - "name": "msp_exp430f5529lp" + "name": "mcxn947brk" }, { "type": "build", - "name": "msp_exp430f5529lp" + "name": "mcxn947brk" } ] }, { - "name": "msp_exp432e401y", + "name": "metro_m0_express", "steps": [ { "type": "configure", - "name": "msp_exp432e401y" + "name": "metro_m0_express" }, { "type": "build", - "name": "msp_exp432e401y" + "name": "metro_m0_express" } ] }, { - "name": "adafruit_clue", + "name": "metro_m4_express", "steps": [ { "type": "configure", - "name": "adafruit_clue" + "name": "metro_m4_express" }, { "type": "build", - "name": "adafruit_clue" + "name": "metro_m4_express" } ] }, { - "name": "arduino_nano33_ble", + "name": "metro_m7_1011", "steps": [ { "type": "configure", - "name": "arduino_nano33_ble" + "name": "metro_m7_1011" }, { "type": "build", - "name": "arduino_nano33_ble" + "name": "metro_m7_1011" } ] }, { - "name": "circuitplayground_bluefruit", + "name": "metro_m7_1011_sd", "steps": [ { "type": "configure", - "name": "circuitplayground_bluefruit" + "name": "metro_m7_1011_sd" }, { "type": "build", - "name": "circuitplayground_bluefruit" + "name": "metro_m7_1011_sd" } ] }, { - "name": "feather_nrf52840_express", + "name": "mimxrt1010_evk", "steps": [ { "type": "configure", - "name": "feather_nrf52840_express" + "name": "mimxrt1010_evk" }, { "type": "build", - "name": "feather_nrf52840_express" + "name": "mimxrt1010_evk" } ] }, { - "name": "feather_nrf52840_sense", + "name": "mimxrt1015_evk", "steps": [ { "type": "configure", - "name": "feather_nrf52840_sense" + "name": "mimxrt1015_evk" }, { "type": "build", - "name": "feather_nrf52840_sense" + "name": "mimxrt1015_evk" } ] }, { - "name": "itsybitsy_nrf52840", + "name": "mimxrt1020_evk", "steps": [ { "type": "configure", - "name": "itsybitsy_nrf52840" + "name": "mimxrt1020_evk" }, { "type": "build", - "name": "itsybitsy_nrf52840" + "name": "mimxrt1020_evk" } ] }, { - "name": "pca10056", + "name": "mimxrt1024_evk", "steps": [ { "type": "configure", - "name": "pca10056" + "name": "mimxrt1024_evk" }, { "type": "build", - "name": "pca10056" + "name": "mimxrt1024_evk" } ] }, { - "name": "pca10059", + "name": "mimxrt1050_evkb", "steps": [ { "type": "configure", - "name": "pca10059" + "name": "mimxrt1050_evkb" }, { "type": "build", - "name": "pca10059" + "name": "mimxrt1050_evkb" } ] }, { - "name": "pca10095", + "name": "mimxrt1060_evk", "steps": [ { "type": "configure", - "name": "pca10095" + "name": "mimxrt1060_evk" }, { "type": "build", - "name": "pca10095" + "name": "mimxrt1060_evk" } ] }, { - "name": "pca10100", + "name": "mimxrt1064_evk", "steps": [ { "type": "configure", - "name": "pca10100" + "name": "mimxrt1064_evk" }, { "type": "build", - "name": "pca10100" + "name": "mimxrt1064_evk" } ] }, { - "name": "portenta_c33", + "name": "mimxrt1170_evkb", "steps": [ { "type": "configure", - "name": "portenta_c33" + "name": "mimxrt1170_evkb" }, { "type": "build", - "name": "portenta_c33" + "name": "mimxrt1170_evkb" } ] }, { - "name": "ra2a1_ek", + "name": "mm32f327x_mb39", "steps": [ { "type": "configure", - "name": "ra2a1_ek" + "name": "mm32f327x_mb39" }, { "type": "build", - "name": "ra2a1_ek" + "name": "mm32f327x_mb39" } ] }, { - "name": "ra4m1_ek", + "name": "mm32f327x_pitaya_lite", "steps": [ { "type": "configure", - "name": "ra4m1_ek" + "name": "mm32f327x_pitaya_lite" }, { "type": "build", - "name": "ra4m1_ek" + "name": "mm32f327x_pitaya_lite" } ] }, { - "name": "ra4m3_ek", + "name": "msp_exp430f5529lp", "steps": [ { "type": "configure", - "name": "ra4m3_ek" + "name": "msp_exp430f5529lp" }, { "type": "build", - "name": "ra4m3_ek" + "name": "msp_exp430f5529lp" } ] }, { - "name": "ra6m1_ek", + "name": "msp_exp432e401y", "steps": [ { "type": "configure", - "name": "ra6m1_ek" + "name": "msp_exp432e401y" }, { "type": "build", - "name": "ra6m1_ek" + "name": "msp_exp432e401y" } ] }, { - "name": "ra6m5_ek", + "name": "nanoch32v203", "steps": [ { "type": "configure", - "name": "ra6m5_ek" + "name": "nanoch32v203" }, { "type": "build", - "name": "ra6m5_ek" + "name": "nanoch32v203" } ] }, { - "name": "ra8m1_ek", + "name": "pca10056", "steps": [ { "type": "configure", - "name": "ra8m1_ek" + "name": "pca10056" }, { "type": "build", - "name": "ra8m1_ek" + "name": "pca10056" } ] }, { - "name": "uno_r4", + "name": "pca10059", "steps": [ { "type": "configure", - "name": "uno_r4" + "name": "pca10059" }, { "type": "build", - "name": "uno_r4" + "name": "pca10059" } ] }, { - "name": "feather_rp2040_max3421", + "name": "pca10095", "steps": [ { "type": "configure", - "name": "feather_rp2040_max3421" + "name": "pca10095" }, { "type": "build", - "name": "feather_rp2040_max3421" + "name": "pca10095" } ] }, { - "name": "pico_sdk", + "name": "pca10100", "steps": [ { "type": "configure", - "name": "pico_sdk" + "name": "pca10100" }, { "type": "build", - "name": "pico_sdk" + "name": "pca10100" } ] }, { - "name": "raspberry_pi_pico", + "name": "pico_sdk", "steps": [ { "type": "configure", - "name": "raspberry_pi_pico" + "name": "pico_sdk" }, { "type": "build", - "name": "raspberry_pi_pico" + "name": "pico_sdk" } ] }, { - "name": "raspberry_pi_pico2", + "name": "portenta_c33", "steps": [ { "type": "configure", - "name": "raspberry_pi_pico2" + "name": "portenta_c33" }, { "type": "build", - "name": "raspberry_pi_pico2" + "name": "portenta_c33" } ] }, { - "name": "cynthion_d11", + "name": "pybadge", "steps": [ { "type": "configure", - "name": "cynthion_d11" + "name": "pybadge" }, { "type": "build", - "name": "cynthion_d11" + "name": "pybadge" } ] }, { - "name": "samd11_xplained", + "name": "pyboardv11", "steps": [ { "type": "configure", - "name": "samd11_xplained" + "name": "pyboardv11" }, { "type": "build", - "name": "samd11_xplained" + "name": "pyboardv11" } ] }, { - "name": "atsamd21_xpro", + "name": "pyportal", "steps": [ { "type": "configure", - "name": "atsamd21_xpro" + "name": "pyportal" }, { "type": "build", - "name": "atsamd21_xpro" + "name": "pyportal" } ] }, { - "name": "circuitplayground_express", + "name": "qtpy", "steps": [ { "type": "configure", - "name": "circuitplayground_express" + "name": "qtpy" }, { "type": "build", - "name": "circuitplayground_express" + "name": "qtpy" } ] }, { - "name": "curiosity_nano", + "name": "ra2a1_ek", "steps": [ { "type": "configure", - "name": "curiosity_nano" + "name": "ra2a1_ek" }, { "type": "build", - "name": "curiosity_nano" + "name": "ra2a1_ek" } ] }, { - "name": "cynthion_d21", + "name": "ra4m1_ek", "steps": [ { "type": "configure", - "name": "cynthion_d21" + "name": "ra4m1_ek" }, { "type": "build", - "name": "cynthion_d21" + "name": "ra4m1_ek" } ] }, { - "name": "feather_m0_express", + "name": "ra4m3_ek", "steps": [ { "type": "configure", - "name": "feather_m0_express" + "name": "ra4m3_ek" }, { "type": "build", - "name": "feather_m0_express" + "name": "ra4m3_ek" } ] }, { - "name": "itsybitsy_m0", + "name": "ra6m1_ek", "steps": [ { "type": "configure", - "name": "itsybitsy_m0" + "name": "ra6m1_ek" }, { "type": "build", - "name": "itsybitsy_m0" + "name": "ra6m1_ek" } ] }, { - "name": "metro_m0_express", + "name": "ra6m5_ek", "steps": [ { "type": "configure", - "name": "metro_m0_express" + "name": "ra6m5_ek" }, { "type": "build", - "name": "metro_m0_express" + "name": "ra6m5_ek" } ] }, { - "name": "qtpy", + "name": "ra8m1_ek", "steps": [ { "type": "configure", - "name": "qtpy" + "name": "ra8m1_ek" }, { "type": "build", - "name": "qtpy" + "name": "ra8m1_ek" } ] }, { - "name": "seeeduino_xiao", + "name": "raspberry_pi_pico", "steps": [ { "type": "configure", - "name": "seeeduino_xiao" + "name": "raspberry_pi_pico" }, { "type": "build", - "name": "seeeduino_xiao" + "name": "raspberry_pi_pico" } ] }, { - "name": "sparkfun_samd21_mini_usb", + "name": "raspberry_pi_pico2", "steps": [ { "type": "configure", - "name": "sparkfun_samd21_mini_usb" + "name": "raspberry_pi_pico2" }, { "type": "build", - "name": "sparkfun_samd21_mini_usb" + "name": "raspberry_pi_pico2" } ] }, { - "name": "trinket_m0", + "name": "raspberrypi_cm4", "steps": [ { "type": "configure", - "name": "trinket_m0" + "name": "raspberrypi_cm4" }, { "type": "build", - "name": "trinket_m0" + "name": "raspberrypi_cm4" } ] }, { - "name": "d5035_01", + "name": "raspberrypi_zero", "steps": [ { "type": "configure", - "name": "d5035_01" + "name": "raspberrypi_zero" }, { "type": "build", - "name": "d5035_01" + "name": "raspberrypi_zero" } ] }, { - "name": "feather_m4_express", + "name": "raspberrypi_zero2", "steps": [ { "type": "configure", - "name": "feather_m4_express" + "name": "raspberrypi_zero2" }, { "type": "build", - "name": "feather_m4_express" + "name": "raspberrypi_zero2" } ] }, { - "name": "itsybitsy_m4", + "name": "samd11_xplained", "steps": [ { "type": "configure", - "name": "itsybitsy_m4" + "name": "samd11_xplained" }, { "type": "build", - "name": "itsybitsy_m4" + "name": "samd11_xplained" } ] }, { - "name": "metro_m4_express", + "name": "same54_xplained", "steps": [ { "type": "configure", - "name": "metro_m4_express" + "name": "same54_xplained" }, { "type": "build", - "name": "metro_m4_express" + "name": "same54_xplained" } ] }, { - "name": "pybadge", + "name": "samg55_xplained", "steps": [ { "type": "configure", - "name": "pybadge" + "name": "samg55_xplained" }, { "type": "build", - "name": "pybadge" + "name": "samg55_xplained" } ] }, { - "name": "pyportal", + "name": "saml22_feather", "steps": [ { "type": "configure", - "name": "pyportal" + "name": "saml22_feather" }, { "type": "build", - "name": "pyportal" + "name": "saml22_feather" } ] }, { - "name": "same54_xplained", + "name": "seeeduino_xiao", "steps": [ { "type": "configure", - "name": "same54_xplained" + "name": "seeeduino_xiao" }, { "type": "build", - "name": "same54_xplained" + "name": "seeeduino_xiao" } ] }, { - "name": "samg55_xplained", + "name": "sensorwatch_m0", "steps": [ { "type": "configure", - "name": "samg55_xplained" + "name": "sensorwatch_m0" }, { "type": "build", - "name": "samg55_xplained" + "name": "sensorwatch_m0" } ] }, { - "name": "atsaml21_xpro", + "name": "sipeed_longan_nano", "steps": [ { "type": "configure", - "name": "atsaml21_xpro" + "name": "sipeed_longan_nano" }, { "type": "build", - "name": "atsaml21_xpro" + "name": "sipeed_longan_nano" } ] }, { - "name": "saml22_feather", + "name": "sparkfun_samd21_mini_usb", "steps": [ { "type": "configure", - "name": "saml22_feather" + "name": "sparkfun_samd21_mini_usb" }, { "type": "build", - "name": "saml22_feather" + "name": "sparkfun_samd21_mini_usb" } ] }, { - "name": "sensorwatch_m0", + "name": "stlinkv3mini", "steps": [ { "type": "configure", - "name": "sensorwatch_m0" + "name": "stlinkv3mini" }, { "type": "build", - "name": "sensorwatch_m0" + "name": "stlinkv3mini" } ] }, @@ -3322,19 +3348,6 @@ } ] }, - { - "name": "stm32f103ze_iar", - "steps": [ - { - "type": "configure", - "name": "stm32f103ze_iar" - }, - { - "type": "build", - "name": "stm32f103ze_iar" - } - ] - }, { "name": "stm32f103_bluepill", "steps": [ @@ -3362,54 +3375,41 @@ ] }, { - "name": "stm32f207nucleo", - "steps": [ - { - "type": "configure", - "name": "stm32f207nucleo" - }, - { - "type": "build", - "name": "stm32f207nucleo" - } - ] - }, - { - "name": "stm32f303disco", + "name": "stm32f103ze_iar", "steps": [ { "type": "configure", - "name": "stm32f303disco" + "name": "stm32f103ze_iar" }, { "type": "build", - "name": "stm32f303disco" + "name": "stm32f103ze_iar" } ] }, { - "name": "feather_stm32f405", + "name": "stm32f207nucleo", "steps": [ { "type": "configure", - "name": "feather_stm32f405" + "name": "stm32f207nucleo" }, { "type": "build", - "name": "feather_stm32f405" + "name": "stm32f207nucleo" } ] }, { - "name": "pyboardv11", + "name": "stm32f303disco", "steps": [ { "type": "configure", - "name": "pyboardv11" + "name": "stm32f303disco" }, { "type": "build", - "name": "pyboardv11" + "name": "stm32f303disco" } ] }, @@ -3517,19 +3517,6 @@ } ] }, - { - "name": "stlinkv3mini", - "steps": [ - { - "type": "configure", - "name": "stlinkv3mini" - }, - { - "type": "build", - "name": "stlinkv3mini" - } - ] - }, { "name": "stm32f723disco", "steps": [ @@ -3608,19 +3595,6 @@ } ] }, - { - "name": "b_g474e_dpow1", - "steps": [ - { - "type": "configure", - "name": "b_g474e_dpow1" - }, - { - "type": "build", - "name": "b_g474e_dpow1" - } - ] - }, { "name": "stm32g474nucleo", "steps": [ @@ -3686,19 +3660,6 @@ } ] }, - { - "name": "daisyseed", - "steps": [ - { - "type": "configure", - "name": "daisyseed" - }, - { - "type": "build", - "name": "daisyseed" - } - ] - }, { "name": "stm32h723nucleo", "steps": [ @@ -3751,19 +3712,6 @@ } ] }, - { - "name": "stm32h750bdk", - "steps": [ - { - "type": "configure", - "name": "stm32h750bdk" - }, - { - "type": "build", - "name": "stm32h750bdk" - } - ] - }, { "name": "stm32h750_weact", "steps": [ @@ -3778,15 +3726,15 @@ ] }, { - "name": "waveshare_openh743i", + "name": "stm32h750bdk", "steps": [ { "type": "configure", - "name": "waveshare_openh743i" + "name": "stm32h750bdk" }, { "type": "build", - "name": "waveshare_openh743i" + "name": "stm32h750bdk" } ] }, @@ -3881,19 +3829,6 @@ } ] }, - { - "name": "b_u585i_iot2a", - "steps": [ - { - "type": "configure", - "name": "b_u585i_iot2a" - }, - { - "type": "build", - "name": "b_u585i_iot2a" - } - ] - }, { "name": "stm32u545nucleo", "steps": [ @@ -3960,15 +3895,80 @@ ] }, { - "name": "ek_tm4c123gxl", + "name": "teensy_35", "steps": [ { "type": "configure", - "name": "ek_tm4c123gxl" + "name": "teensy_35" }, { "type": "build", - "name": "ek_tm4c123gxl" + "name": "teensy_35" + } + ] + }, + { + "name": "teensy_40", + "steps": [ + { + "type": "configure", + "name": "teensy_40" + }, + { + "type": "build", + "name": "teensy_40" + } + ] + }, + { + "name": "teensy_41", + "steps": [ + { + "type": "configure", + "name": "teensy_41" + }, + { + "type": "build", + "name": "teensy_41" + } + ] + }, + { + "name": "trinket_m0", + "steps": [ + { + "type": "configure", + "name": "trinket_m0" + }, + { + "type": "build", + "name": "trinket_m0" + } + ] + }, + { + "name": "uno_r4", + "steps": [ + { + "type": "configure", + "name": "uno_r4" + }, + { + "type": "build", + "name": "uno_r4" + } + ] + }, + { + "name": "waveshare_openh743i", + "steps": [ + { + "type": "configure", + "name": "waveshare_openh743i" + }, + { + "type": "build", + "name": "waveshare_openh743i" } ] }, diff --git a/tools/gen_presets.py b/tools/gen_presets.py index 98b1a7d46..7542cfdf5 100755 --- a/tools/gen_presets.py +++ b/tools/gen_presets.py @@ -24,46 +24,57 @@ def main(): {"name": "default", "hidden": True, "description": r"Configure preset for the ${presetName} board", - "generator": "Ninja", + "generator": "Ninja Multi-Config", "binaryDir": r"${sourceDir}/build/${presetName}", "cacheVariables": { - "CMAKE_BUILD_TYPE": "RelWithDebInfo", + "CMAKE_DEFAULT_BUILD_TYPE": "RelWithDebInfo", "BOARD": r"${presetName}" - } - }] + }}] presets['configurePresets'].extend( - [{'name': board, 'inherits': 'default'} for board in board_list] + sorted( + [ + { + 'name': board, + 'inherits': 'default' + } + for board in board_list + ], key=lambda x: x['name'] + ) ) # Build presets # no inheritance since 'name' doesn't support macro expansion - presets['buildPresets'] = [ - { - 'name': board, - 'description': "Build preset for the " + board + " board", - 'configurePreset': board - } - for board in board_list - ] + presets['buildPresets'] = sorted( + [ + { + 'name': board, + 'description': "Build preset for the " + board + " board", + 'configurePreset': board + } + for board in board_list + ], key=lambda x: x['name'] + ) # Workflow presets - presets['workflowPresets'] = [ - { - "name": board, - "steps": [ - { - "type": "configure", - "name": board - }, - { - "type": "build", - "name": board - } - ] - } - for board in board_list - ] + presets['workflowPresets'] = sorted( + [ + { + "name": board, + "steps": [ + { + "type": "configure", + "name": board + }, + { + "type": "build", + "name": board + } + ] + } + for board in board_list + ], key=lambda x: x['name'] + ) with open("hw/bsp/BoardPresets.json", "w") as f: f.write('{}\n'.format(json.dumps(presets, indent=2))) @@ -87,5 +98,6 @@ def main(): print('Generating presets for the following examples:') print(example_list) + if __name__ == "__main__": main() -- cgit v1.3.1 From 3560ed3d986426b22837e86f2d1648174db02428 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 11 Feb 2025 21:55:28 +0700 Subject: remove board_mcu.h --- examples/build_system/make/make.mk | 2 + hw/bsp/board.c | 4 +- hw/bsp/board_mcu.h | 193 ------------------------------------- 3 files changed, 3 insertions(+), 196 deletions(-) delete mode 100644 hw/bsp/board_mcu.h (limited to 'hw') diff --git a/examples/build_system/make/make.mk b/examples/build_system/make/make.mk index 206516eaf..3101b66b9 100644 --- a/examples/build_system/make/make.mk +++ b/examples/build_system/make/make.mk @@ -169,6 +169,8 @@ ifeq ($(RTOS),freertos) $(TOP)/$(FREERTOS_SRC)/include \ $(TOP)/$(FREERTOS_PORTABLE_SRC) + CFLAGS += -DCFG_TUSB_OS=OPT_OS_FREERTOS + # Suppress FreeRTOSConfig.h warnings CFLAGS_GCC += -Wno-error=redundant-decls diff --git a/hw/bsp/board.c b/hw/bsp/board.c index 5bcdb7f15..0e0fa4ac6 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -64,9 +64,7 @@ int sys_read(int fhdl, char *buf, size_t count) { #endif #elif defined(LOGGER_SWO) -// Logging with SWO for ARM Cortex -#include "board_mcu.h" - +// Logging with SWO for ARM Cortex-M int sys_write (int fhdl, const char *buf, size_t count) { (void) fhdl; uint8_t const* buf8 = (uint8_t const*) buf; diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h deleted file mode 100644 index e720cd747..000000000 --- a/hw/bsp/board_mcu.h +++ /dev/null @@ -1,193 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2020, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - - -#ifndef BOARD_MCU_H_ -#define BOARD_MCU_H_ - -#include "tusb_option.h" - -//--------------------------------------------------------------------+ -// Low Level MCU header include. Example should be -// platform independent and mostly doesn't need to include this file. -// However there are still certain situation where this file is needed: -// - FreeRTOSConfig.h to set up correct clock and NVIC interrupts for ARM Cortex -// - SWO logging for Cortex M with ITM_SendChar() / ITM_ReceiveChar() -//--------------------------------------------------------------------+ - -// Include order follows OPT_MCU_ number -#if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX) || \ - TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC18XX) || \ - TU_CHECK_MCU(OPT_MCU_LPC40XX, OPT_MCU_LPC43XX) - #include "chip.h" - -#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX, OPT_MCU_MCXN9) - #include "fsl_device_registers.h" - -#elif TU_CHECK_MCU(OPT_MCU_KINETIS_KL, OPT_MCU_KINETIS_K32L, OPT_MCU_KINETIS_K) - #include "fsl_device_registers.h" - -#elif CFG_TUSB_MCU == OPT_MCU_NRF5X - #include "nrf.h" - -#elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \ - CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \ - CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21 - #include "sam.h" - -#elif CFG_TUSB_MCU == OPT_MCU_SAMG - #undef LITTLE_ENDIAN // hack to suppress "LITTLE_ENDIAN" redefined - #include "sam.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F0 - #include "stm32f0xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F1 - #include "stm32f1xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F2 - #include "stm32f2xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F3 - #include "stm32f3xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F4 - #include "stm32f4xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32F7 - #include "stm32f7xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32G4 - #include "stm32g4xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32H5 - #include "stm32h5xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32H7 - #include "stm32h7xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32L0 - #include "stm32l0xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32L1 - #include "stm32l1xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32L4 - #include "stm32l4xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32WB - #include "stm32wbxx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32U5 - #include "stm32u5xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32G0 - #include "stm32g0xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_STM32C0 - #include "stm32c0xx.h" - -#elif CFG_TUSB_MCU == OPT_MCU_CXD56 - // no header needed - -#elif CFG_TUSB_MCU == OPT_MCU_MSP430x5xx - #include "msp430.h" - -#elif CFG_TUSB_MCU == OPT_MCU_MSP432E4 - #include "msp.h" - -#elif CFG_TUSB_MCU == OPT_MCU_VALENTYUSB_EPTRI - // no header needed - -#elif CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX - #include "fsl_device_registers.h" - -#elif CFG_TUSB_MCU == OPT_MCU_NUC120 - #include "NUC100Series.h" - -#elif CFG_TUSB_MCU == OPT_MCU_NUC121 || CFG_TUSB_MCU == OPT_MCU_NUC126 - #include "NuMicro.h" - -#elif CFG_TUSB_MCU == OPT_MCU_NUC505 - #include "NUC505Series.h" - -#elif CFG_TUSB_MCU == OPT_MCU_ESP32S2 - // no header needed - -#elif CFG_TUSB_MCU == OPT_MCU_ESP32S3 - // no header needed - -#elif CFG_TUSB_MCU == OPT_MCU_DA1469X - #include "DA1469xAB.h" - -#elif CFG_TUSB_MCU == OPT_MCU_RP2040 - #include "pico.h" - -#elif CFG_TUSB_MCU == OPT_MCU_EFM32GG - #include "em_device.h" - -#elif CFG_TUSB_MCU == OPT_MCU_RX63X || CFG_TUSB_MCU == OPT_MCU_RX65X - // no header needed - -#elif CFG_TUSB_MCU == OPT_MCU_RAXXX - #include "bsp_api.h" - -#elif CFG_TUSB_MCU == OPT_MCU_GD32VF103 - #include "gd32vf103.h" - -#elif CFG_TUSB_MCU == OPT_MCU_MM32F327X - #include "mm32_device.h" - -#elif CFG_TUSB_MCU == OPT_MCU_XMC4000 - #include "xmc_device.h" - -#elif CFG_TUSB_MCU == OPT_MCU_TM4C123 - #include "TM4C123.h" - -#elif CFG_TUSB_MCU == OPT_MCU_CH32F20X - #include "ch32f20x.h" - -#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837) - // no header needed - -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 - #include "max32690.h" - -#elif CFG_TUSB_MCU == OPT_MCU_MAX32650 - #include "max32650.h" - -#elif CFG_TUSB_MCU == OPT_MCU_MAX32666 - #include "max32665.h" - -#elif CFG_TUSB_MCU == OPT_MCU_MAX78002 - #include "max78002.h" - -#else - #error "Missing MCU header" -#endif - - -#endif /* BOARD_MCU_H_ */ -- cgit v1.3.1 From 85247e50ddc17347fca1f6c9b9fedb1227eda25f Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 12 Feb 2025 11:34:32 +0700 Subject: clean up --- hw/bsp/rp2040/family.cmake | 30 +++++++++++++++--------------- src/class/midi/midi_device.c | 2 +- src/device/usbd.c | 13 ++++++------- src/host/usbh.c | 8 ++++++-- src/tusb_option.h | 6 +++--- 5 files changed, 31 insertions(+), 28 deletions(-) (limited to 'hw') diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index cf5295f22..1cbc0742c 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -100,21 +100,21 @@ target_sources(tinyusb_device_base INTERFACE ${TOP}/src/class/video/video_device.c ) - #------------------------------------ - # Base config for host mode; wrapped by SDK's tinyusb_host - #------------------------------------ - add_library(tinyusb_host_base INTERFACE) - target_sources(tinyusb_host_base INTERFACE - ${TOP}/src/portable/raspberrypi/rp2040/hcd_rp2040.c - ${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c - ${TOP}/src/host/usbh.c - ${TOP}/src/host/hub.c - ${TOP}/src/class/cdc/cdc_host.c - ${TOP}/src/class/hid/hid_host.c - ${TOP}/src/class/midi/midi_host.c - ${TOP}/src/class/msc/msc_host.c - ${TOP}/src/class/vendor/vendor_host.c - ) +#------------------------------------ +# Base config for host mode; wrapped by SDK's tinyusb_host +#------------------------------------ +add_library(tinyusb_host_base INTERFACE) +target_sources(tinyusb_host_base INTERFACE + ${TOP}/src/portable/raspberrypi/rp2040/hcd_rp2040.c + ${TOP}/src/portable/raspberrypi/rp2040/rp2040_usb.c + ${TOP}/src/host/usbh.c + ${TOP}/src/host/hub.c + ${TOP}/src/class/cdc/cdc_host.c + ${TOP}/src/class/hid/hid_host.c + ${TOP}/src/class/midi/midi_host.c + ${TOP}/src/class/msc/msc_host.c + ${TOP}/src/class/vendor/vendor_host.c + ) # Sometimes have to do host specific actions in mostly common functions target_compile_definitions(tinyusb_host_base INTERFACE diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c index 4ae8ea8fa..dd1883e37 100644 --- a/src/class/midi/midi_device.c +++ b/src/class/midi/midi_device.c @@ -440,7 +440,7 @@ uint16_t midid_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uint1 drv_len = tu_desc_len(desc_itf); p_desc = tu_desc_next(desc_itf); // Skip Class Specific descriptors - while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len ) { + while (TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len) { drv_len += tu_desc_len(p_desc); p_desc = tu_desc_next(p_desc); } diff --git a/src/device/usbd.c b/src/device/usbd.c index 20f803563..faf926855 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1032,14 +1032,13 @@ static bool process_set_config(uint8_t rhport, uint8_t cfg_num) #endif #if CFG_TUD_MIDI - if ( driver->open == midid_open ) - { - // If there is a class-compliant Audio Control Class, then 2 interfaces - // Otherwise, only one + if (driver->open == midid_open) { + // If there is a class-compliant Audio Control Class, then 2 interfaces. Otherwise, only one if (TUSB_CLASS_AUDIO == desc_itf->bInterfaceClass && - AUDIO_SUBCLASS_CONTROL == desc_itf->bInterfaceSubClass && - AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol) - assoc_itf_count = 2; + AUDIO_SUBCLASS_CONTROL == desc_itf->bInterfaceSubClass && + AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol) { + assoc_itf_count = 2; + } } #endif diff --git a/src/host/usbh.c b/src/host/usbh.c index 6f7a8b8bf..30a4f5f63 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -1488,7 +1488,9 @@ static void process_enumeration(tuh_xfer_t* xfer) { dev->i_product = desc_device->iProduct; dev->i_serial = desc_device->iSerialNumber; - if (tuh_desc_device_cb) tuh_desc_device_cb(daddr, (tusb_desc_device_t const*) _usbh_ctrl_buf); + if (tuh_desc_device_cb) { + tuh_desc_device_cb(daddr, (tusb_desc_device_t const*) _usbh_ctrl_buf); + } // Get 9-byte for total length uint8_t const config_idx = CONFIG_NUM - 1; @@ -1517,7 +1519,9 @@ static void process_enumeration(tuh_xfer_t* xfer) { } case ENUM_SET_CONFIG: - if (tuh_desc_config_cb) tuh_desc_config_cb(daddr, (const tusb_desc_configuration_t*) _usbh_ctrl_buf); + if (tuh_desc_config_cb) { + tuh_desc_config_cb(daddr, (const tusb_desc_configuration_t*) _usbh_ctrl_buf); + } TU_ASSERT(tuh_configuration_set(daddr, CONFIG_NUM, process_enumeration, ENUM_CONFIG_DRIVER),); break; diff --git a/src/tusb_option.h b/src/tusb_option.h index 84319939a..29fdcb0d6 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -657,9 +657,9 @@ //------------------------------------------------------------------ // Configuration Validation //------------------------------------------------------------------ -//#if CFG_TUD_ENDPOINT0_SIZE > 64 -// #error Control Endpoint Max Packet Size cannot be larger than 64 -//#endif +#if CFG_TUD_ENDPOINT0_SIZE > 64 + #error Control Endpoint Max Packet Size cannot be larger than 64 +#endif // To avoid GCC compiler warnings when -pedantic option is used (strict ISO C) typedef int make_iso_compilers_happy; -- cgit v1.3.1 From 86d371fb79ca8b1ee6794c33b6a74d4319d9c1a6 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 12 Feb 2025 13:58:01 +0700 Subject: more ci fix --- examples/host/device_info/src/tusb_config.h | 3 +- examples/host/midi_rx/src/main.c | 137 +++++++++++++--------------- examples/host/midi_rx/src/tusb_config.h | 77 ++++++++++------ hw/bsp/rp2040/family.c | 4 +- 4 files changed, 120 insertions(+), 101 deletions(-) (limited to 'hw') diff --git a/examples/host/device_info/src/tusb_config.h b/examples/host/device_info/src/tusb_config.h index 5190b5b1f..27dd07e25 100644 --- a/examples/host/device_info/src/tusb_config.h +++ b/examples/host/device_info/src/tusb_config.h @@ -109,8 +109,7 @@ // only hub class is enabled #define CFG_TUH_HUB 1 -// max device support (excluding hub device) -// 1 hub typically has 4 ports +// max device support (excluding hub device): 1 hub typically has 4 ports #define CFG_TUH_DEVICE_MAX (3*CFG_TUH_HUB + 1) #ifdef __cplusplus diff --git a/examples/host/midi_rx/src/main.c b/examples/host/midi_rx/src/main.c index 8b83977e2..a03fd588f 100644 --- a/examples/host/midi_rx/src/main.c +++ b/examples/host/midi_rx/src/main.c @@ -23,8 +23,8 @@ * */ -#include #include +#include #include #include "bsp/board_api.h" @@ -44,22 +44,25 @@ void led_blinking_task(void); void midi_host_rx_task(void); /*------------- MAIN -------------*/ -int main(void) -{ - board_init(); +int main(void) { + board_init(); - printf("TinyUSB Host MIDI Example\r\n"); + printf("TinyUSB Host MIDI Example\r\n"); - tusb_init(); + // init host stack on configured roothub port + tusb_rhport_init_t host_init = { + .role = TUSB_ROLE_HOST, + .speed = TUSB_SPEED_AUTO + }; + tusb_init(BOARD_TUH_RHPORT, &host_init); - while (1) - { - tuh_task(); - led_blinking_task(); - midi_host_rx_task(); - } + while (1) { + tuh_task(); + led_blinking_task(); + midi_host_rx_task(); + } - return 0; + return 0; } #endif @@ -67,36 +70,32 @@ int main(void) //--------------------------------------------------------------------+ // Blinking Task //--------------------------------------------------------------------+ -void led_blinking_task(void) -{ - const uint32_t interval_ms = 1000; - static uint32_t start_ms = 0; +void led_blinking_task(void) { + const uint32_t interval_ms = 1000; + static uint32_t start_ms = 0; - static bool led_state = false; + static bool led_state = false; - // Blink every interval ms - if ( board_millis() - start_ms < interval_ms) return; // not enough time - start_ms += interval_ms; + // Blink every interval ms + if (board_millis() - start_ms < interval_ms) return;// not enough time + start_ms += interval_ms; - board_led_write(led_state); - led_state = 1 - led_state; // toggle + board_led_write(led_state); + led_state = 1 - led_state;// toggle } //--------------------------------------------------------------------+ // MIDI host receive task //--------------------------------------------------------------------+ -void midi_host_rx_task(void) -{ - // device must be attached and have at least one endpoint ready to receive a message - if (!midi_dev_addr || !tuh_midi_configured(midi_dev_addr)) - { - return; - } - if (tuh_midih_get_num_rx_cables(midi_dev_addr) < 1) - { - return; - } - tuh_midi_read_poll(midi_dev_addr); +void midi_host_rx_task(void) { + // device must be attached and have at least one endpoint ready to receive a message + if (!midi_dev_addr || !tuh_midi_configured(midi_dev_addr)) { + return; + } + if (tuh_midih_get_num_rx_cables(midi_dev_addr) < 1) { + return; + } + tuh_midi_read_poll(midi_dev_addr); } //--------------------------------------------------------------------+ @@ -108,51 +107,45 @@ void midi_host_rx_task(void) // can be used to parse common/simple enough descriptor. // Note: if report descriptor length > CFG_TUH_ENUMERATION_BUFSIZE, it will be skipped // therefore report_desc = NULL, desc_len = 0 -void tuh_midi_mount_cb(uint8_t dev_addr, uint8_t in_ep, uint8_t out_ep, uint8_t num_cables_rx, uint16_t num_cables_tx) -{ - (void ) in_ep; - (void ) out_ep; - (void ) num_cables_rx; - (void ) num_cables_tx; +void tuh_midi_mount_cb(uint8_t dev_addr, uint8_t in_ep, uint8_t out_ep, uint8_t num_cables_rx, uint16_t num_cables_tx) { + (void) in_ep; + (void) out_ep; + (void) num_cables_rx; + (void) num_cables_tx; - TU_LOG1("MIDI device address = %u, IN endpoint %u has %u cables, OUT endpoint %u has %u cables\r\n", - dev_addr, in_ep & 0xf, num_cables_rx, out_ep & 0xf, num_cables_tx); + TU_LOG1("MIDI device address = %u, IN endpoint %u has %u cables, OUT endpoint %u has %u cables\r\n", + dev_addr, in_ep & 0xf, num_cables_rx, out_ep & 0xf, num_cables_tx); - midi_dev_addr = dev_addr; + midi_dev_addr = dev_addr; } // Invoked when device with hid interface is un-mounted -void tuh_midi_umount_cb(uint8_t dev_addr, uint8_t instance) -{ - (void ) dev_addr; - (void ) instance; +void tuh_midi_umount_cb(uint8_t dev_addr, uint8_t instance) { + (void) dev_addr; + (void) instance; - TU_LOG1("MIDI device address = %d, instance = %d is unmounted\r\n", dev_addr, instance); - midi_dev_addr = 0; + TU_LOG1("MIDI device address = %d, instance = %d is unmounted\r\n", dev_addr, instance); + midi_dev_addr = 0; } -void tuh_midi_rx_cb(uint8_t dev_addr, uint32_t num_packets) -{ - if (midi_dev_addr != dev_addr) - { - return; - } - - if(num_packets == 0) - { - return; - } - - uint8_t cable_num; - uint8_t buffer[48]; - uint32_t bytes_read = tuh_midi_stream_read(dev_addr, &cable_num, buffer, sizeof(buffer)); - (void ) bytes_read; - - TU_LOG1("Read bytes %lu cable %u", bytes_read, cable_num); - TU_LOG1_MEM(buffer, bytes_read, 2); +void tuh_midi_rx_cb(uint8_t dev_addr, uint32_t num_packets) { + if (midi_dev_addr != dev_addr) { + return; + } + + if (num_packets == 0) { + return; + } + + uint8_t cable_num; + uint8_t buffer[48]; + uint32_t bytes_read = tuh_midi_stream_read(dev_addr, &cable_num, buffer, sizeof(buffer)); + (void) bytes_read; + + TU_LOG1("Read bytes %lu cable %u", bytes_read, cable_num); + TU_LOG1_MEM(buffer, bytes_read, 2); } -void tuh_midi_tx_cb(uint8_t dev_addr) -{ - (void ) dev_addr; +void tuh_midi_tx_cb(uint8_t dev_addr) { + (void) dev_addr; } diff --git a/examples/host/midi_rx/src/tusb_config.h b/examples/host/midi_rx/src/tusb_config.h index 5cc354ea9..1afcbbd63 100644 --- a/examples/host/midi_rx/src/tusb_config.h +++ b/examples/host/midi_rx/src/tusb_config.h @@ -23,15 +23,15 @@ * */ -#ifndef _TUSB_CONFIG_H_ -#define _TUSB_CONFIG_H_ +#ifndef TUSB_CONFIG_H_ +#define TUSB_CONFIG_H_ #ifdef __cplusplus extern "C" { #endif //-------------------------------------------------------------------- -// COMMON CONFIGURATION +// Common Configuration //-------------------------------------------------------------------- // defined by compiler flags for flexibility @@ -39,18 +39,18 @@ extern "C" { #error CFG_TUSB_MCU must be defined #endif -#if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT10XX -#define CFG_TUSB_RHPORT0_MODE (OPT_MODE_HOST | OPT_MODE_HIGH_SPEED) -#else -#define CFG_TUSB_RHPORT0_MODE OPT_MODE_HOST +// Espressif IDF requires "freertos/" prefix in include path +#if TUSB_MCU_VENDOR_ESPRESSIF +#define CFG_TUSB_OS_INC_PATH freertos/ #endif #ifndef CFG_TUSB_OS -#define CFG_TUSB_OS OPT_OS_NONE +#define CFG_TUSB_OS OPT_OS_NONE #endif -// CFG_TUSB_DEBUG is defined by compiler in DEBUG build -// #define CFG_TUSB_DEBUG 0 +#ifndef CFG_TUSB_DEBUG +#define CFG_TUSB_DEBUG 0 +#endif /* USB DMA on some MCUs can only access a specific SRAM region with restriction on alignment. * Tinyusb use follows macros to declare transferring memory so that they can be put @@ -59,38 +59,63 @@ extern "C" { * - CFG_TUSB_MEM SECTION : __attribute__ (( section(".usb_ram") )) * - CFG_TUSB_MEM_ALIGN : __attribute__ ((aligned(4))) */ -#ifndef CFG_TUSB_MEM_SECTION -#define CFG_TUSB_MEM_SECTION +#ifndef CFG_TUH_MEM_SECTION +#define CFG_TUH_MEM_SECTION #endif -#ifndef CFG_TUSB_MEM_ALIGN -#define CFG_TUSB_MEM_ALIGN __attribute__ ((aligned(4))) +#ifndef CFG_TUH_MEM_ALIGN +#define CFG_TUH_MEM_ALIGN __attribute__ ((aligned(4))) #endif //-------------------------------------------------------------------- -// CONFIGURATION +// Host Configuration +//-------------------------------------------------------------------- + +// Enable Host stack +#define CFG_TUH_ENABLED 1 + +#if CFG_TUSB_MCU == OPT_MCU_RP2040 + // #define CFG_TUH_RPI_PIO_USB 1 // use pio-usb as host controller + // #define CFG_TUH_MAX3421 1 // use max3421 as host controller + + // host roothub port is 1 if using either pio-usb or max3421 + #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421) + #define BOARD_TUH_RHPORT 1 + #endif +#endif + +// Default is max speed that hardware controller could support with on-chip PHY +#define CFG_TUH_MAX_SPEED BOARD_TUH_MAX_SPEED + +//------------------------- Board Specific -------------------------- + +// RHPort number used for host can be defined by board.mk, default to port 0 +#ifndef BOARD_TUH_RHPORT +#define BOARD_TUH_RHPORT 0 +#endif + +// RHPort max operational speed can defined by board.mk +#ifndef BOARD_TUH_MAX_SPEED +#define BOARD_TUH_MAX_SPEED OPT_MODE_DEFAULT_SPEED +#endif + +//-------------------------------------------------------------------- +// Driver Configuration //-------------------------------------------------------------------- // Size of buffer to hold descriptors and other data used for enumeration #define CFG_TUH_ENUMERATION_BUFSIZE 256 #define CFG_TUH_HUB 1 -#define CFG_TUH_CDC 0 -#define CFG_TUH_HID 0 // typical keyboard + mouse device can have 3-4 HID interfaces #define CFG_TUH_MIDI 1 // there will be at most one MIDIStreaming Interface descriptor -#define CFG_TUH_MSC 0 -#define CFG_TUH_VENDOR 0 -// max device support (excluding hub device) -#define CFG_TUH_DEVICE_MAX (CFG_TUH_HUB ? 4 : 1) // hub typically has 4 ports -#define CFG_MIDI_HOST_DEVSTRINGS 1 +// max device support (excluding hub device): 1 hub typically has 4 ports +#define CFG_TUH_DEVICE_MAX (3*CFG_TUH_HUB + 1) -//------------- HID -------------// -#define CFG_TUH_HID_EPIN_BUFSIZE 64 -#define CFG_TUH_HID_EPOUT_BUFSIZE 64 +#define CFG_MIDI_HOST_DEVSTRINGS 1 #ifdef __cplusplus } #endif -#endif /* _TUSB_CONFIG_H_ */ +#endif diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c index 24aa0b616..689e264bd 100644 --- a/hw/bsp/rp2040/family.c +++ b/hw/bsp/rp2040/family.c @@ -266,7 +266,9 @@ int board_getchar(void) { #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 void max3421_int_handler(uint gpio, uint32_t event_mask) { - if (!(gpio == MAX3421_INTR_PIN && event_mask & GPIO_IRQ_EDGE_FALL)) return; + if (!(gpio == MAX3421_INTR_PIN && event_mask & GPIO_IRQ_EDGE_FALL)) { + return; + } tuh_int_handler(BOARD_TUH_RHPORT, true); } -- cgit v1.3.1 From aa860041b8cfad9b5740db93d013add03667f01c Mon Sep 17 00:00:00 2001 From: Devin Auclair Date: Fri, 14 Feb 2025 11:01:33 -0500 Subject: Add full/high speed compile flag for Microchip SAME70 examples Default is still high speed, but setting SPEED=high|full work as expected. `make BOARD=same70_xplained SPEED=full` Tested with examples/device/cdc_msc ```preformatted lsusb -v ... TinyUSB Device: Product ID: 0x4003 Vendor ID: 0xcafe Version: 1.00 Serial Number: 0123456789ABCDEF Speed: Up to 12 Mb/s <------ full speed here Manufacturer: TinyUSB Location ID: 0x03142130 / 12 Current Available (mA): 500 Current Required (mA): 100 Extra Operating Current (mA): 0 Media: Mass Storage: Capacity: 8 KB (8,192 bytes) Removable Media: Yes BSD Name: disk5 Logical Unit: 0 Partition Map Type: Unknown S.M.A.R.T. status: Verified USB Interface: 2 ``` --- hw/bsp/same70_xplained/board.mk | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'hw') diff --git a/hw/bsp/same70_xplained/board.mk b/hw/bsp/same70_xplained/board.mk index 3edc128a5..60702f14a 100644 --- a/hw/bsp/same70_xplained/board.mk +++ b/hw/bsp/same70_xplained/board.mk @@ -14,6 +14,14 @@ CFLAGS += \ # suppress following warnings from mcu driver CFLAGS += -Wno-error=unused-parameter -Wno-error=cast-align -Wno-error=redundant-decls +SPEED ?= high + +ifeq ($(SPEED), high) + CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED +else + CFLAGS += -DBOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED +endif + # SAM driver is flooded with -Wcast-qual which slow down complication significantly CFLAGS_SKIP += -Wcast-qual -- cgit v1.3.1 From 6572c1da0d6ad2f298ef97189ca4b288f710f49a Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 20 Feb 2025 15:47:29 +0700 Subject: add fruitjam bsp --- hw/bsp/family_support.cmake | 4 + hw/bsp/rp2040/board.h | 102 ------------------- .../adafruit_feather_rp2040_usb_host/board.h | 64 ++++++++++++ .../boards/adafruit_fruit_jam/adafruit_fruit_jam.h | 113 +++++++++++++++++++++ .../rp2040/boards/adafruit_fruit_jam/board.cmake | 4 + hw/bsp/rp2040/boards/adafruit_fruit_jam/board.h | 52 ++++++++++ .../rp2040/boards/feather_rp2040_max3421/board.h | 64 ++++++++++++ hw/bsp/rp2040/boards/raspberry_pi_pico/board.h | 69 +++++++++++++ .../rp2040/boards/raspberry_pi_pico2/board.cmake | 1 + hw/bsp/rp2040/boards/raspberry_pi_pico2/board.h | 69 +++++++++++++ hw/bsp/rp2040/family.c | 38 +++++-- hw/bsp/rp2040/family.cmake | 5 +- hw/bsp/rp2040/rp2350-openocd.cfg | 3 + 13 files changed, 478 insertions(+), 110 deletions(-) delete mode 100644 hw/bsp/rp2040/board.h create mode 100644 hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.h create mode 100644 hw/bsp/rp2040/boards/adafruit_fruit_jam/adafruit_fruit_jam.h create mode 100644 hw/bsp/rp2040/boards/adafruit_fruit_jam/board.cmake create mode 100644 hw/bsp/rp2040/boards/adafruit_fruit_jam/board.h create mode 100644 hw/bsp/rp2040/boards/feather_rp2040_max3421/board.h create mode 100644 hw/bsp/rp2040/boards/raspberry_pi_pico/board.h create mode 100644 hw/bsp/rp2040/boards/raspberry_pi_pico2/board.h create mode 100644 hw/bsp/rp2040/rp2350-openocd.cfg (limited to 'hw') diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 409fb9c75..562d4995b 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -476,6 +476,10 @@ function(family_flash_openocd TARGET) set(OPENOCD_OPTION2 "") endif () + if (DEFINED OPENOCD_SERIAL) + set(OPENOCD_OPTION "-c \"adapter serial ${OPENOCD_SERIAL}\" ${OPENOCD_OPTION}") + endif () + separate_arguments(OPTION_LIST UNIX_COMMAND ${OPENOCD_OPTION}) separate_arguments(OPTION_LIST2 UNIX_COMMAND ${OPENOCD_OPTION2}) diff --git a/hw/bsp/rp2040/board.h b/hw/bsp/rp2040/board.h deleted file mode 100644 index 5dbb1dd37..000000000 --- a/hw/bsp/rp2040/board.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2021, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -/* metadata: - name: Pico - url: https://www.raspberrypi.org/products/raspberry-pi-pico/ -*/ - -#ifndef BOARD_H_ -#define BOARD_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -// LED -#ifdef PICO_DEFAULT_LED_PIN -#define LED_PIN PICO_DEFAULT_LED_PIN -#define LED_STATE_ON (!(PICO_DEFAULT_LED_PIN_INVERTED)) -#endif - -// Button pin is BOOTSEL which is flash CS pin -#define BUTTON_BOOTSEL -#define BUTTON_STATE_ACTIVE 0 - -// UART -#if defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN) && \ - defined(PICO_DEFAULT_UART) && defined(LIB_PICO_STDIO_UART) -#define UART_DEV PICO_DEFAULT_UART -#define UART_TX_PIN PICO_DEFAULT_UART_TX_PIN -#define UART_RX_PIN PICO_DEFAULT_UART_RX_PIN -#endif - -//--------------------------------------------------------------------+ -// PIO_USB -// default to pin on Adafruit Feather rp2040 USB Host or Tester if defined -//--------------------------------------------------------------------+ - -// #define USE_ADAFRUIT_FEATHER_RP2040_USBHOST -#ifdef USE_ADAFRUIT_FEATHER_RP2040_USBHOST -#define PICO_DEFAULT_PIO_USB_DP_PIN 16 -#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 18 -#endif - -#ifndef PICO_DEFAULT_PIO_USB_DP_PIN -#define PICO_DEFAULT_PIO_USB_DP_PIN 20 -#endif - -// VBUS enable pin and its active state -#ifndef PICO_DEFAULT_PIO_USB_VBUSEN_PIN -#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 22 -#endif - -// VBUS enable state -#ifndef PICO_DEFAULT_PIO_USB_VBUSEN_STATE -#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1 -#endif - -//-------------------------------------------------------------------- -// USB Host MAX3421E -//-------------------------------------------------------------------- - -#ifdef PICO_DEFAULT_SPI -#define MAX3421_SPI PICO_DEFAULT_SPI // sdk v2 -#else -#define MAX3421_SPI PICO_DEFAULT_SPI_INSTANCE // sdk v1 -#endif - -#define MAX3421_SCK_PIN PICO_DEFAULT_SPI_SCK_PIN -#define MAX3421_MOSI_PIN PICO_DEFAULT_SPI_TX_PIN -#define MAX3421_MISO_PIN PICO_DEFAULT_SPI_RX_PIN -#define MAX3421_CS_PIN 10 -#define MAX3421_INTR_PIN 9 - -#ifdef __cplusplus - } -#endif - -#endif /* BOARD_H_ */ diff --git a/hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.h b/hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.h new file mode 100644 index 000000000..f36ca14c9 --- /dev/null +++ b/hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.h @@ -0,0 +1,64 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef TUSB_BOARD_H +#define TUSB_BOARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +// UART and LED are already defined in pico-sdk board + +//--------------------------------------------------------------------+ +// PIO_USB +//--------------------------------------------------------------------+ + +#define PICO_DEFAULT_PIO_USB_DP_PIN 16 +#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 18 +#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1 + +//-------------------------------------------------------------------- +// USB Host MAX3421E +//-------------------------------------------------------------------- + +#ifdef PICO_DEFAULT_SPI +#define MAX3421_SPI PICO_DEFAULT_SPI // sdk v2 +#else +#define MAX3421_SPI PICO_DEFAULT_SPI_INSTANCE // sdk v1 +#endif + +#define MAX3421_SCK_PIN PICO_DEFAULT_SPI_SCK_PIN +#define MAX3421_MOSI_PIN PICO_DEFAULT_SPI_TX_PIN +#define MAX3421_MISO_PIN PICO_DEFAULT_SPI_RX_PIN +#define MAX3421_CS_PIN 10 +#define MAX3421_INTR_PIN 9 + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/rp2040/boards/adafruit_fruit_jam/adafruit_fruit_jam.h b/hw/bsp/rp2040/boards/adafruit_fruit_jam/adafruit_fruit_jam.h new file mode 100644 index 000000000..2d4c689de --- /dev/null +++ b/hw/bsp/rp2040/boards/adafruit_fruit_jam/adafruit_fruit_jam.h @@ -0,0 +1,113 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ +#ifndef BOARDS_ADAFRUIT_FRUIT_JAM_H +#define BOARDS_ADAFRUIT_FRUIT_JAM_H + +// required for board that is not part of pico-sdk + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// pico_cmake_set PICO_PLATFORM=rp2350 + +// On some samples, the xosc can take longer to stabilize than is usual +#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER +#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64 +#endif + +// For board detection +#define ADAFRUIT_FRUIT_JAM + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 1 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 8 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 9 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 29 +#endif + +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 32 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 20 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 21 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 30 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 31 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 28 +#endif + +// --- FLASH --- + +// FruitJam use w25q128 but sdk does not have .s for it, use q080 instead +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +// pico_cmake_set_default PICO_RP2350_A2_SUPPORTED = 1 +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/hw/bsp/rp2040/boards/adafruit_fruit_jam/board.cmake b/hw/bsp/rp2040/boards/adafruit_fruit_jam/board.cmake new file mode 100644 index 000000000..4ab8a5477 --- /dev/null +++ b/hw/bsp/rp2040/boards/adafruit_fruit_jam/board.cmake @@ -0,0 +1,4 @@ +set(PICO_PLATFORM rp2350-arm-s) +set(PICO_BOARD adafruit_fruit_jam) +set(PICO_BOARD_HEADER_DIRS ${CMAKE_CURRENT_LIST_DIR}) +#set(OPENOCD_SERIAL E6614103E78E8324) diff --git a/hw/bsp/rp2040/boards/adafruit_fruit_jam/board.h b/hw/bsp/rp2040/boards/adafruit_fruit_jam/board.h new file mode 100644 index 000000000..f81da3b70 --- /dev/null +++ b/hw/bsp/rp2040/boards/adafruit_fruit_jam/board.h @@ -0,0 +1,52 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef TUSB_BOARD_H +#define TUSB_BOARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +// UART and LED are already defined in pico-sdk board + +//--------------------------------------------------------------------+ +// PIO_USB +//--------------------------------------------------------------------+ +// default to pico brain tester +#define PICO_DEFAULT_PIO_USB_DP_PIN 1 +#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 11 +#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1 + +//-------------------------------------------------------------------- +// USB Host MAX3421E +//-------------------------------------------------------------------- + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.h b/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.h new file mode 100644 index 000000000..f36ca14c9 --- /dev/null +++ b/hw/bsp/rp2040/boards/feather_rp2040_max3421/board.h @@ -0,0 +1,64 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef TUSB_BOARD_H +#define TUSB_BOARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +// UART and LED are already defined in pico-sdk board + +//--------------------------------------------------------------------+ +// PIO_USB +//--------------------------------------------------------------------+ + +#define PICO_DEFAULT_PIO_USB_DP_PIN 16 +#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 18 +#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1 + +//-------------------------------------------------------------------- +// USB Host MAX3421E +//-------------------------------------------------------------------- + +#ifdef PICO_DEFAULT_SPI +#define MAX3421_SPI PICO_DEFAULT_SPI // sdk v2 +#else +#define MAX3421_SPI PICO_DEFAULT_SPI_INSTANCE // sdk v1 +#endif + +#define MAX3421_SCK_PIN PICO_DEFAULT_SPI_SCK_PIN +#define MAX3421_MOSI_PIN PICO_DEFAULT_SPI_TX_PIN +#define MAX3421_MISO_PIN PICO_DEFAULT_SPI_RX_PIN +#define MAX3421_CS_PIN 10 +#define MAX3421_INTR_PIN 9 + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.h b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.h new file mode 100644 index 000000000..12c772b84 --- /dev/null +++ b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.h @@ -0,0 +1,69 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: Pico + url: https://www.raspberrypi.org/products/raspberry-pi-pico/ +*/ + +#ifndef TUSB_BOARD_H +#define TUSB_BOARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +// UART and LED are already defined in pico-sdk board + +//--------------------------------------------------------------------+ +// PIO_USB +//--------------------------------------------------------------------+ +// default to pico brain tester +#define PICO_DEFAULT_PIO_USB_DP_PIN 20 +#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 22 +#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1 + +//-------------------------------------------------------------------- +// USB Host MAX3421E +//-------------------------------------------------------------------- + +#ifdef PICO_DEFAULT_SPI +#define MAX3421_SPI PICO_DEFAULT_SPI // sdk v2 +#else +#define MAX3421_SPI PICO_DEFAULT_SPI_INSTANCE // sdk v1 +#endif + +#define MAX3421_SCK_PIN PICO_DEFAULT_SPI_SCK_PIN +#define MAX3421_MOSI_PIN PICO_DEFAULT_SPI_TX_PIN +#define MAX3421_MISO_PIN PICO_DEFAULT_SPI_RX_PIN +#define MAX3421_CS_PIN 10 +#define MAX3421_INTR_PIN 9 + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake index 3482e2674..0a7dd4d23 100644 --- a/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake +++ b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.cmake @@ -1,2 +1,3 @@ set(PICO_PLATFORM rp2350-arm-s) set(PICO_BOARD pico2) +#set(OPENOCD_SERIAL E6614103E77C5A24) diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.h b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.h new file mode 100644 index 000000000..139b58ceb --- /dev/null +++ b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.h @@ -0,0 +1,69 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: Pico2 + url: https://www.raspberrypi.org/products/raspberry-pi-pico/ +*/ + +#ifndef TUSB_BOARD_H +#define TUSB_BOARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +// UART and LED are already defined in pico-sdk board + +//--------------------------------------------------------------------+ +// PIO_USB +//--------------------------------------------------------------------+ +// default to pico brain tester +#define PICO_DEFAULT_PIO_USB_DP_PIN 20 +#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 22 +#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1 + +//-------------------------------------------------------------------- +// USB Host MAX3421E +//-------------------------------------------------------------------- + +#ifdef PICO_DEFAULT_SPI +#define MAX3421_SPI PICO_DEFAULT_SPI // sdk v2 +#else +#define MAX3421_SPI PICO_DEFAULT_SPI_INSTANCE // sdk v1 +#endif + +#define MAX3421_SCK_PIN PICO_DEFAULT_SPI_SCK_PIN +#define MAX3421_MOSI_PIN PICO_DEFAULT_SPI_TX_PIN +#define MAX3421_MISO_PIN PICO_DEFAULT_SPI_RX_PIN +#define MAX3421_CS_PIN 10 +#define MAX3421_INTR_PIN 9 + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c index 24aa0b616..0c97d6ed0 100644 --- a/hw/bsp/rp2040/family.c +++ b/hw/bsp/rp2040/family.c @@ -42,10 +42,6 @@ #include "bsp/board_api.h" #include "board.h" -#ifdef UART_DEV -static uart_inst_t *uart_inst; -#endif - #if (CFG_TUH_ENABLED && CFG_TUH_RPI_PIO_USB) || (CFG_TUD_ENABLED && CFG_TUD_RPI_PIO_USB) #include "pio_usb.h" #endif @@ -55,6 +51,36 @@ static uart_inst_t *uart_inst; static void max3421_init(void); #endif +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ +// LED +#if !defined(LED_PIN) && defined(PICO_DEFAULT_LED_PIN) +#define LED_PIN PICO_DEFAULT_LED_PIN +#define LED_STATE_ON (!(PICO_DEFAULT_LED_PIN_INVERTED)) +#endif + +// Button, if not defined use BOOTSEL button +#ifndef BUTTON_PIN +#define BUTTON_BOOTSEL +#define BUTTON_STATE_ACTIVE 0 +#endif + +// UART +#if !defined(UART_DEV) && defined(PICO_DEFAULT_UART) && defined(LIB_PICO_STDIO_UART) && \ + defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN) +#define UART_DEV PICO_DEFAULT_UART +#define UART_TX_PIN PICO_DEFAULT_UART_TX_PIN +#define UART_RX_PIN PICO_DEFAULT_UART_RX_PIN +#endif + +#ifdef UART_DEV +static uart_inst_t *uart_inst; +#endif + +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ #ifdef BUTTON_BOOTSEL // This example blinks the Picoboard LED when the BOOTSEL button is pressed. // @@ -79,7 +105,7 @@ bool __no_inline_not_in_flash_func(get_bootsel_button)(void) { IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS); // Note we can't call into any sleep functions in flash right now - for (volatile int i = 0; i < 1000; ++i); + for (volatile int i = 0; i < 1000; ++i) {} // The HI GPIO registers in SIO can observe and control the 6 QSPI pins. // Note the button pulls the pin *low* when pressed. @@ -133,7 +159,6 @@ void stdio_rtt_init(void) { //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ - void board_init(void) { #if (CFG_TUH_ENABLED && CFG_TUH_RPI_PIO_USB) || (CFG_TUD_ENABLED && CFG_TUD_RPI_PIO_USB) @@ -193,7 +218,6 @@ void board_init(void) //--------------------------------------------------------------------+ // Board porting API //--------------------------------------------------------------------+ - void board_led_write(bool state) { (void) state; diff --git a/hw/bsp/rp2040/family.cmake b/hw/bsp/rp2040/family.cmake index b2b01b1cf..384b06933 100644 --- a/hw/bsp/rp2040/family.cmake +++ b/hw/bsp/rp2040/family.cmake @@ -31,7 +31,9 @@ elseif (PICO_PLATFORM STREQUAL "rp2350-riscv") set(OPENOCD_TARGET rp2350-riscv) endif() -set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/${OPENOCD_TARGET}.cfg -c \"adapter speed 5000\"") +if (NOT OPENOCD_OPTION) + set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/${OPENOCD_TARGET}.cfg -c \"adapter speed 5000\"") +endif() if (NOT PICO_TINYUSB_PATH) set(PICO_TINYUSB_PATH ${TOP}) @@ -143,6 +145,7 @@ target_sources(tinyusb_bsp INTERFACE ) target_include_directories(tinyusb_bsp INTERFACE ${TOP}/hw + ${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD} ) target_link_libraries(tinyusb_bsp INTERFACE pico_unique_id diff --git a/hw/bsp/rp2040/rp2350-openocd.cfg b/hw/bsp/rp2040/rp2350-openocd.cfg new file mode 100644 index 000000000..52c71cd99 --- /dev/null +++ b/hw/bsp/rp2040/rp2350-openocd.cfg @@ -0,0 +1,3 @@ +source [find interface/cmsis-dap.cfg] +adapter speed 5000 +source [find target/rp2350.cfg] -- cgit v1.3.1 From cafc788508834b71248a91773a262542fc2cad37 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 20 Feb 2025 16:01:06 +0700 Subject: change pio-usb to wip fork for testing --- hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.cmake | 2 ++ tools/get_deps.py | 4 ++-- 2 files changed, 4 insertions(+), 2 deletions(-) create mode 100644 hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.cmake (limited to 'hw') diff --git a/hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.cmake b/hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.cmake new file mode 100644 index 000000000..41897f644 --- /dev/null +++ b/hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.cmake @@ -0,0 +1,2 @@ +set(PICO_PLATFORM rp2040) +set(PICO_BOARD adafruit_feather_rp2040_usb_host) diff --git a/tools/get_deps.py b/tools/get_deps.py index 3665904b3..b82abac4f 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -58,8 +58,8 @@ deps_optional = { 'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git', '144f1eb7ea8c06512e12f12b27383601c0272410', 'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'], - 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git', - '442af432568f25fb72c5784d9d67b8e85465cb28', + 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/hathach/Pico-PIO-USB.git', + '9c8df3083b62c0a678f3bd3d8a7e773932622d4b', 'rp2040'], 'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git', 'edcc97d684b6f716728a60d7a6fea049d9870bd6', -- cgit v1.3.1 From 61aab7a86aaaf5c254ba5d14a04ff44aec8623d3 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 20 Feb 2025 22:16:05 +0700 Subject: pio-usb now only need sysclk to be multiple of 12Mhz --- hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake | 1 + hw/bsp/rp2040/family.c | 6 +++++- 2 files changed, 6 insertions(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake index 804cdb50a..2d739291c 100644 --- a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake +++ b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.cmake @@ -1,2 +1,3 @@ set(PICO_PLATFORM rp2040) set(PICO_BOARD pico) +#set(OPENOCD_SERIAL E6614103E719612F) diff --git a/hw/bsp/rp2040/family.c b/hw/bsp/rp2040/family.c index 0c97d6ed0..a6e176308 100644 --- a/hw/bsp/rp2040/family.c +++ b/hw/bsp/rp2040/family.c @@ -162,8 +162,12 @@ void stdio_rtt_init(void) { void board_init(void) { #if (CFG_TUH_ENABLED && CFG_TUH_RPI_PIO_USB) || (CFG_TUD_ENABLED && CFG_TUD_RPI_PIO_USB) - // Set the system clock to a multiple of 120mhz for bitbanging USB with pico-usb + // Set the system clock to a multiple of 12mhz for bit-banging USB with pico-usb set_sys_clock_khz(120000, true); + // set_sys_clock_khz(180000, true); + // set_sys_clock_khz(192000, true); + // set_sys_clock_khz(240000, true); + // set_sys_clock_khz(264000, true); #ifdef PICO_DEFAULT_PIO_USB_VBUSEN_PIN gpio_init(PICO_DEFAULT_PIO_USB_VBUSEN_PIN); -- cgit v1.3.1 From 720697b6ae8208b446497cc0658f3590a3694d9d Mon Sep 17 00:00:00 2001 From: Tomas Rezucha Date: Thu, 27 Feb 2025 12:48:31 +0100 Subject: fix(esp): Remove deprecated include soc/usb_pins.h header will be deprecated in IDF v6.0 --- hw/bsp/espressif/boards/family.c | 1 - 1 file changed, 1 deletion(-) (limited to 'hw') diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index 2f9ecfe4d..7049c0415 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -162,7 +162,6 @@ int board_getchar(void) { #if ESP_IDF_VERSION >= ESP_IDF_VERSION_VAL(5, 3, 0) #include "esp_private/usb_phy.h" -#include "soc/usb_pins.h" static usb_phy_handle_t phy_hdl; -- cgit v1.3.1 From c1df796a7c463dad43e709a2df145d6e24cd96a4 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 28 Feb 2025 12:04:54 +0700 Subject: add missing board.h for BOARD=pico_sdk --- .../adafruit_feather_rp2040_usb_host/board.h | 5 +++ hw/bsp/rp2040/boards/adafruit_fruit_jam/board.h | 5 +++ hw/bsp/rp2040/boards/pico_sdk/board.h | 40 ++++++++++++++++++++++ hw/bsp/rp2040/boards/raspberry_pi_pico/board.h | 2 +- hw/bsp/rp2040/boards/raspberry_pi_pico2/board.h | 2 +- 5 files changed, 52 insertions(+), 2 deletions(-) create mode 100644 hw/bsp/rp2040/boards/pico_sdk/board.h (limited to 'hw') diff --git a/hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.h b/hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.h index f36ca14c9..d003ae828 100644 --- a/hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.h +++ b/hw/bsp/rp2040/boards/adafruit_feather_rp2040_usb_host/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Feather RP2040 with USB Type A Host + url: https://www.adafruit.com/product/5723 +*/ + #ifndef TUSB_BOARD_H #define TUSB_BOARD_H diff --git a/hw/bsp/rp2040/boards/adafruit_fruit_jam/board.h b/hw/bsp/rp2040/boards/adafruit_fruit_jam/board.h index f81da3b70..0f53fd96f 100644 --- a/hw/bsp/rp2040/boards/adafruit_fruit_jam/board.h +++ b/hw/bsp/rp2040/boards/adafruit_fruit_jam/board.h @@ -24,6 +24,11 @@ * This file is part of the TinyUSB stack. */ +/* metadata: + name: Adafruit Fruit Jam - Mini RP2350 + url: https://www.adafruit.com/product/6200 +*/ + #ifndef TUSB_BOARD_H #define TUSB_BOARD_H diff --git a/hw/bsp/rp2040/boards/pico_sdk/board.h b/hw/bsp/rp2040/boards/pico_sdk/board.h new file mode 100644 index 000000000..284edac7d --- /dev/null +++ b/hw/bsp/rp2040/boards/pico_sdk/board.h @@ -0,0 +1,40 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef TUSB_BOARD_H +#define TUSB_BOARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +// UART and LED are already defined in pico-sdk board + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.h b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.h index 12c772b84..88f8793f4 100644 --- a/hw/bsp/rp2040/boards/raspberry_pi_pico/board.h +++ b/hw/bsp/rp2040/boards/raspberry_pi_pico/board.h @@ -26,7 +26,7 @@ /* metadata: name: Pico - url: https://www.raspberrypi.org/products/raspberry-pi-pico/ + url: https://www.raspberrypi.com/products/raspberry-pi-pico/ */ #ifndef TUSB_BOARD_H diff --git a/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.h b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.h index 139b58ceb..b5ce8b7e1 100644 --- a/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.h +++ b/hw/bsp/rp2040/boards/raspberry_pi_pico2/board.h @@ -26,7 +26,7 @@ /* metadata: name: Pico2 - url: https://www.raspberrypi.org/products/raspberry-pi-pico/ + url: https://www.raspberrypi.com/products/raspberry-pi-pico-2/ */ #ifndef TUSB_BOARD_H -- cgit v1.3.1 From 7dbad0a23e69cde6173f09357419c4257a0ed09c Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 4 Mar 2025 22:38:17 +0700 Subject: add adafruit metro rp2350 --- .idea/cmake.xml | 8 +- .idea/vcs.xml | 1 + .../adafruit_metro_rp2350/adafruit_metro_rp2350.h | 113 +++++++++++++++++++++ .../boards/adafruit_metro_rp2350/board.cmake | 4 + hw/bsp/rp2040/boards/adafruit_metro_rp2350/board.h | 57 +++++++++++ 5 files changed, 180 insertions(+), 3 deletions(-) create mode 100644 hw/bsp/rp2040/boards/adafruit_metro_rp2350/adafruit_metro_rp2350.h create mode 100644 hw/bsp/rp2040/boards/adafruit_metro_rp2350/board.cmake create mode 100644 hw/bsp/rp2040/boards/adafruit_metro_rp2350/board.h (limited to 'hw') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index a792b1a05..7365e13a8 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -12,6 +12,8 @@ + + @@ -80,14 +82,14 @@ - + - - + + diff --git a/.idea/vcs.xml b/.idea/vcs.xml index 94a25f7f4..d44b5516f 100644 --- a/.idea/vcs.xml +++ b/.idea/vcs.xml @@ -2,5 +2,6 @@ + \ No newline at end of file diff --git a/hw/bsp/rp2040/boards/adafruit_metro_rp2350/adafruit_metro_rp2350.h b/hw/bsp/rp2040/boards/adafruit_metro_rp2350/adafruit_metro_rp2350.h new file mode 100644 index 000000000..9fb9658a5 --- /dev/null +++ b/hw/bsp/rp2040/boards/adafruit_metro_rp2350/adafruit_metro_rp2350.h @@ -0,0 +1,113 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ +#ifndef BOARDS_ADAFRUIT_METRO_RP2350_H +#define BOARDS_ADAFRUIT_METRO_RP2350_H + +// required for board that is not part of pico-sdk + +// ----------------------------------------------------- +// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLER SO +// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES +// ----------------------------------------------------- + +// pico_cmake_set PICO_PLATFORM=rp2350 + +// On some samples, the xosc can take longer to stabilize than is usual +#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER +#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 64 +#endif + +// For board detection +#define ADAFRUIT_METRO_RP2350 + +// --- RP2350 VARIANT --- +#define PICO_RP2350A 0 + +// --- UART --- +#ifndef PICO_DEFAULT_UART +#define PICO_DEFAULT_UART 0 +#endif +#ifndef PICO_DEFAULT_UART_TX_PIN +#define PICO_DEFAULT_UART_TX_PIN 0 +#endif +#ifndef PICO_DEFAULT_UART_RX_PIN +#define PICO_DEFAULT_UART_RX_PIN 1 +#endif + +// --- LED --- +#ifndef PICO_DEFAULT_LED_PIN +#define PICO_DEFAULT_LED_PIN 23 +#endif + +#ifndef PICO_DEFAULT_WS2812_PIN +#define PICO_DEFAULT_WS2812_PIN 25 +#endif + +// --- I2C --- +#ifndef PICO_DEFAULT_I2C +#define PICO_DEFAULT_I2C 0 +#endif +#ifndef PICO_DEFAULT_I2C_SDA_PIN +#define PICO_DEFAULT_I2C_SDA_PIN 20 +#endif +#ifndef PICO_DEFAULT_I2C_SCL_PIN +#define PICO_DEFAULT_I2C_SCL_PIN 21 +#endif + +// --- SPI --- +#ifndef PICO_DEFAULT_SPI +#define PICO_DEFAULT_SPI 1 +#endif +#ifndef PICO_DEFAULT_SPI_SCK_PIN +#define PICO_DEFAULT_SPI_SCK_PIN 30 +#endif +#ifndef PICO_DEFAULT_SPI_TX_PIN +#define PICO_DEFAULT_SPI_TX_PIN 31 +#endif +#ifndef PICO_DEFAULT_SPI_RX_PIN +#define PICO_DEFAULT_SPI_RX_PIN 28 +#endif + +// --- FLASH --- + +// FruitJam use w25q128 but sdk does not have .s for it, use q080 instead +#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1 + +#ifndef PICO_FLASH_SPI_CLKDIV +#define PICO_FLASH_SPI_CLKDIV 2 +#endif + +// pico_cmake_set_default PICO_FLASH_SIZE_BYTES = (8 * 1024 * 1024) +#ifndef PICO_FLASH_SIZE_BYTES +#define PICO_FLASH_SIZE_BYTES (8 * 1024 * 1024) +#endif + +// pico_cmake_set_default PICO_RP2350_A2_SUPPORTED = 1 +#ifndef PICO_RP2350_A2_SUPPORTED +#define PICO_RP2350_A2_SUPPORTED 1 +#endif + +#endif diff --git a/hw/bsp/rp2040/boards/adafruit_metro_rp2350/board.cmake b/hw/bsp/rp2040/boards/adafruit_metro_rp2350/board.cmake new file mode 100644 index 000000000..9a58821a5 --- /dev/null +++ b/hw/bsp/rp2040/boards/adafruit_metro_rp2350/board.cmake @@ -0,0 +1,4 @@ +set(PICO_PLATFORM rp2350-arm-s) +set(PICO_BOARD adafruit_metro_rp2350) +set(PICO_BOARD_HEADER_DIRS ${CMAKE_CURRENT_LIST_DIR}) +#set(OPENOCD_SERIAL E6614103E78E8324) diff --git a/hw/bsp/rp2040/boards/adafruit_metro_rp2350/board.h b/hw/bsp/rp2040/boards/adafruit_metro_rp2350/board.h new file mode 100644 index 000000000..0b8515d1f --- /dev/null +++ b/hw/bsp/rp2040/boards/adafruit_metro_rp2350/board.h @@ -0,0 +1,57 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +/* metadata: + name: Adafruit Metro RP2350 + url: https://www.adafruit.com/product/6003 +*/ + +#ifndef TUSB_BOARD_H +#define TUSB_BOARD_H + +#ifdef __cplusplus + extern "C" { +#endif + +// UART and LED are already defined in pico-sdk board + +//--------------------------------------------------------------------+ +// PIO_USB +//--------------------------------------------------------------------+ +// default to pico brain tester +#define PICO_DEFAULT_PIO_USB_DP_PIN 32 +#define PICO_DEFAULT_PIO_USB_VBUSEN_PIN 29 +#define PICO_DEFAULT_PIO_USB_VBUSEN_STATE 1 + +//-------------------------------------------------------------------- +// USB Host MAX3421E +//-------------------------------------------------------------------- + +#ifdef __cplusplus + } +#endif + +#endif -- cgit v1.3.1 From 683b1e9702f60a8093ada3b0fdd4a7a51a05a981 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 10 Mar 2025 11:20:47 +0700 Subject: fix(rp2040) set RTOS as cmake cache to fix pico-example build --- hw/bsp/family_support.cmake | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'hw') diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 562d4995b..e7161eba3 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -12,7 +12,7 @@ set(UF2CONV_PY ${TOP}/tools/uf2/utils/uf2conv.py) # RTOS #------------------------------------------------------------- if (NOT DEFINED RTOS) - set(RTOS noos) + set(RTOS noos CACHE STRING "RTOS") endif () #------------------------------------------------------------- -- cgit v1.3.1 From 73e810a7ba73a54c0bd074e86a18b6e2954057fa Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 26 Mar 2025 15:20:02 +0700 Subject: imxrt: disable BOARD_ConfigMPU() since it cause issue with imxrt1060/64. Update imxrt configtool forr some board to get uart pin init. --- hw/bsp/family_support.cmake | 4 - .../boards/mimxrt1015_evk/board/clock_config.c | 4 +- .../boards/mimxrt1015_evk/board/clock_config.h | 66 +++++++------- hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.c | 35 ++++++-- hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.h | 30 ++++--- .../imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex | 63 +++++++++---- .../boards/mimxrt1064_evk/board/clock_config.c | 4 +- .../boards/mimxrt1064_evk/board/clock_config.h | 100 ++++++++++----------- hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c | 13 +-- hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h | 1 + .../imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex | 36 ++++---- .../boards/mimxrt1170_evkb/board/clock_config.c | 4 +- .../imxrt/boards/mimxrt1170_evkb/board/pin_mux.c | 56 ++++++++---- .../imxrt/boards/mimxrt1170_evkb/board/pin_mux.h | 27 +++--- .../boards/mimxrt1170_evkb/mimxrt1170_evkb.mex | 73 ++++++++------- hw/bsp/imxrt/family.c | 4 +- hw/bsp/imxrt/family.cmake | 4 - 17 files changed, 297 insertions(+), 227 deletions(-) (limited to 'hw') diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index e7161eba3..3a6890690 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -270,10 +270,6 @@ function(family_add_tinyusb TARGET OPT_MCU) # Add TinyUSB sources, include and common define tinyusb_target_add(${TARGET}) - - # path to tusb_config.h - target_include_directories(${TARGET} PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/src) - target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_MCU=${OPT_MCU}) if (DEFINED LOG) target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_DEBUG=${LOG}) diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c index ae1aa7fb1..b9e4851bf 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.c @@ -15,11 +15,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v11.0 +product: Clocks v15.0 processor: MIMXRT1015xxxxx package_id: MIMXRT1015DAF5A mcu_data: ksdk2_0 -processor_version: 13.0.2 +processor_version: 24.12.10 board: MIMXRT1015-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h index 2acdb16a7..cccbe487a 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/clock_config.h @@ -36,39 +36,39 @@ void BOARD_InitBootClocks(void); #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */ /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 196363636UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, USB, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL /* Clock consumers of ENET_500M_REF_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 196363636UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC_ETC, AOI, ARM, BEE, CCM, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, EWM, FLEXIO1, FLEXRAM, FLEXSPI, GPC, GPIO1, GPIO2, GPIO3, GPIO5, IOMUXC, KPP, LPI2C1, LPI2C2, LPSPI1, LPSPI2, LPUART1, LPUART2, LPUART3, LPUART4, NVIC, OCOTP, PWM1, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TRNG, USB, WDOG1, WDOG2, XBARA, XBARB */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2 */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4 */ +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB */ /*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration. */ diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.c index 97224a332..76c1dae70 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.c +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.c @@ -6,11 +6,11 @@ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Pins v13.1 +product: Pins v17.0 processor: MIMXRT1015xxxxx package_id: MIMXRT1015DAF5A mcu_data: ksdk2_0 -processor_version: 13.0.2 +processor_version: 24.12.10 board: MIMXRT1015-EVK external_user_signals: {} pin_labels: @@ -32,6 +32,7 @@ power_domains: {NVCC_GPIO: '3.3'} * END ****************************************************************************************************************/ void BOARD_InitBootPins(void) { BOARD_InitPins(); + BOARD_InitDEBUG_UARTPins(); } /* @@ -40,8 +41,6 @@ BOARD_InitPins: - options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} - pin_list: - {pin_num: '1', peripheral: GPIO2, signal: 'gpio_io, 09', pin_signal: GPIO_EMC_09, direction: INPUT, pull_keeper_select: Pull, pull_up_down_config: Pull_Up_47K_Ohm} - - {pin_num: '68', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07, pull_up_down_config: Pull_Down_100K_Ohm} - - {pin_num: '72', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06} - {pin_num: '21', peripheral: GPIO3, signal: 'gpio_io, 21', pin_signal: GPIO_SD_B1_01, direction: OUTPUT} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** */ @@ -73,15 +72,11 @@ void BOARD_InitPins(void) { /* Initialize GPIO functionality on GPIO_SD_B1_01 (pin 21) */ GPIO_PinInit(GPIO3, 21U, &USER_LED_config); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U); - IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_GPIO3_IO21, 0U); - IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0x10B0U); IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_09_GPIO2_IO09, 0x70B0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitQSPIPins: @@ -113,6 +108,30 @@ void BOARD_InitQSPIPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPI_A_SS0_B, 0U); } +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '68', peripheral: LPUART1, signal: RX, pin_signal: GPIO_AD_B0_07, slew_rate: Slow} + - {pin_num: '72', peripheral: LPUART1, signal: TX, pin_signal: GPIO_AD_B0_06, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); + + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_06_LPUART1_TX, 0x10B0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_07_LPUART1_RX, 0x10B0U); +} /*********************************************************************************************************************** * EOF **********************************************************************************************************************/ diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.h index c9cbe3b72..2f3bf2c4c 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.h +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/board/pin_mux.h @@ -37,7 +37,7 @@ extern "C" { */ void BOARD_InitBootPins(void); -/* GPIO_EMC_09 (number 1), USER_BUTTON */ +/* GPIO_EMC_09 (number 1), USER_BUTTON/SW4 */ /* Routed pin properties */ #define BOARD_INITPINS_USER_BUTTON_PERIPHERAL GPIO2 /*!< Peripheral name */ #define BOARD_INITPINS_USER_BUTTON_SIGNAL gpio_io /*!< Signal name */ @@ -51,16 +51,6 @@ void BOARD_InitBootPins(void); #define BOARD_INITPINS_USER_BUTTON_PIN 9U /*!< PORT pin number */ #define BOARD_INITPINS_USER_BUTTON_PIN_MASK (1U << 9U) /*!< PORT pin mask */ -/* GPIO_AD_B0_07 (number 68), LPUART1_RXD */ -/* Routed pin properties */ -#define BOARD_INITPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ -#define BOARD_INITPINS_UART1_RXD_SIGNAL RX /*!< Signal name */ - -/* GPIO_AD_B0_06 (number 72), LPUART1_TXD */ -/* Routed pin properties */ -#define BOARD_INITPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ -#define BOARD_INITPINS_UART1_TXD_SIGNAL TX /*!< Signal name */ - /* GPIO_SD_B1_01 (number 21), GPIO SD_B1_01 */ /* Routed pin properties */ #define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO3 /*!< Peripheral name */ @@ -69,6 +59,7 @@ void BOARD_InitBootPins(void); /* Symbols to be used with GPIO driver */ #define BOARD_INITPINS_USER_LED_GPIO GPIO3 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ #define BOARD_INITPINS_USER_LED_GPIO_PIN 21U /*!< GPIO pin number */ #define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 21U) /*!< GPIO pin mask */ #define BOARD_INITPINS_USER_LED_PORT GPIO3 /*!< PORT peripheral base pointer */ @@ -119,6 +110,23 @@ void BOARD_InitPins(void); */ void BOARD_InitQSPIPins(void); +/* GPIO_AD_B0_07 (number 68), LPUART1_RXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_RXD_SIGNAL RX /*!< Signal name */ + +/* GPIO_AD_B0_06 (number 72), LPUART1_TXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_UART1_TXD_SIGNAL TX /*!< Signal name */ + + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); + #if defined(__cplusplus) } #endif diff --git a/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex b/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex index 88265d32e..917bed375 100644 --- a/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex +++ b/hw/bsp/imxrt/boards/mimxrt1015_evk/mimxrt1015_evk.mex @@ -1,5 +1,5 @@ - + MIMXRT1015xxxxx MIMXRT1015DAF5A @@ -13,19 +13,18 @@ true - false false true false - + - 13.0.2 + 24.12.10 @@ -45,12 +44,7 @@ true - - - true - - - + true @@ -79,12 +73,6 @@ - - - - - - @@ -100,7 +88,7 @@ true - + true @@ -125,15 +113,52 @@ + + Configures pin routing and optionally pin electrical features. + + true + core0 + true + + + + + true + + + + + true + + + + + true + + + + + + + + + + + + + + + + - + - 13.0.2 + 24.12.10 diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c index 778ab02f2..be684faee 100644 --- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.c @@ -15,11 +15,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v11.0 +product: Clocks v15.0 processor: MIMXRT1064xxxxA package_id: MIMXRT1064DVL6A mcu_data: ksdk2_0 -processor_version: 13.0.2 +processor_version: 24.12.10 board: MIMXRT1064-EVK * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h index 7ce24b6f4..2fa713c0d 100644 --- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/clock_config.h @@ -36,56 +36,56 @@ void BOARD_InitBootClocks(void); #define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */ /* Clock outputs (values are in Hz): */ -#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL -#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL -#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL -#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL -#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL -#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL -#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL -#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL -#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL -#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL -#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL -#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL -#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL -#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL -#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL -#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL -#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL -#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL -#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL -#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL -#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL -#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL -#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL -#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL -#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL -#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL -#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL -#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL -#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL +#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL /* Clock consumers of AHB_CLK_ROOT output : AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4, ARM, FLEXIO3, FLEXSPI, FLEXSPI2, GPIO6, GPIO7, GPIO8, GPIO9 */ +#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL /* Clock consumers of CAN_CLK_ROOT output : CAN1, CAN2, CAN3 */ +#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL /* Clock consumers of CKIL_SYNC_CLK_ROOT output : CSU, EWM, GPT1, GPT2, KPP, PIT, RTWDOG, SNVS, SPDIF, TEMPMON, TSC, USB1, USB2, WDOG1, WDOG2 */ +#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL /* Clock consumers of CLKO1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL /* Clock consumers of CLKO2_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL /* Clock consumers of CLK_1M output : EWM, RTWDOG */ +#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL /* Clock consumers of CLK_24M output : GPT1, GPT2 */ +#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL /* Clock consumers of CSI_CLK_ROOT output : CSI */ +#define BOARD_BOOTCLOCKRUN_ENET2_125M_CLK 1200000UL /* Clock consumers of ENET2_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET2_REF_CLK 0UL /* Clock consumers of ENET2_REF_CLK output : ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET2_TX_CLK 0UL /* Clock consumers of ENET2_TX_CLK output : ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL /* Clock consumers of ENET_125M_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL /* Clock consumers of ENET_25M_REF_CLK output : ENET, ENET2 */ +#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL /* Clock consumers of ENET_REF_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL /* Clock consumers of ENET_TX_CLK output : ENET */ +#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO1_CLK_ROOT output : FLEXIO1 */ +#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL /* Clock consumers of FLEXIO2_CLK_ROOT output : FLEXIO2, FLEXIO3 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI2_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI2_CLK_ROOT output : FLEXSPI2 */ +#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 130909090UL /* Clock consumers of FLEXSPI_CLK_ROOT output : FLEXSPI */ +#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT1_ipg_clk_highfreq output : GPT1 */ +#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL /* Clock consumers of GPT2_ipg_clk_highfreq output : GPT2 */ +#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL /* Clock consumers of IPG_CLK_ROOT output : ADC1, ADC2, ADC_ETC, AOI1, AOI2, ARM, BEE, CAN1, CAN2, CAN3, CCM, CMP1, CMP2, CMP3, CMP4, CSI, CSU, DCDC, DCP, DMA0, DMAMUX, ENC1, ENC2, ENC3, ENC4, ENET, ENET2, EWM, FLEXIO1, FLEXIO2, FLEXIO3, FLEXRAM, FLEXSPI, FLEXSPI2, GPC, GPIO1, GPIO10, GPIO2, GPIO3, GPIO4, GPIO5, IOMUXC, KPP, LCDIF, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, NVIC, OCOTP, PMU, PWM1, PWM2, PWM3, PWM4, PXP, ROMC, RTWDOG, SAI1, SAI2, SAI3, SNVS, SPDIF, SRC, TEMPMON, TMR1, TMR2, TMR3, TMR4, TRNG, TSC, USB1, USB2, USDHC1, USDHC2, WDOG1, WDOG2, XBARA1, XBARB2, XBARB3 */ +#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL /* Clock consumers of LCDIF_CLK_ROOT output : LCDIF */ +#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL /* Clock consumers of LPI2C_CLK_ROOT output : LPI2C1, LPI2C2, LPI2C3, LPI2C4 */ +#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL /* Clock consumers of LPSPI_CLK_ROOT output : LPSPI1, LPSPI2, LPSPI3, LPSPI4 */ +#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL /* Clock consumers of LVDS1_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL /* Clock consumers of MQS_MCLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL /* Clock consumers of PERCLK_CLK_ROOT output : GPT1, GPT2, PIT */ +#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 480000000UL /* Clock consumers of PLL7_MAIN_CLK output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL /* Clock consumers of SAI1_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL /* Clock consumers of SAI1_MCLK1 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL /* Clock consumers of SAI1_MCLK2 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL /* Clock consumers of SAI1_MCLK3 output : SAI1 */ +#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL /* Clock consumers of SAI2_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL /* Clock consumers of SAI2_MCLK1 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL /* Clock consumers of SAI2_MCLK2 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL /* Clock consumers of SAI2_MCLK3 output : SAI2 */ +#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL /* Clock consumers of SAI3_CLK_ROOT output : N/A */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL /* Clock consumers of SAI3_MCLK1 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL /* Clock consumers of SAI3_MCLK2 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL /* Clock consumers of SAI3_MCLK3 output : SAI3 */ +#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL /* Clock consumers of SEMC_CLK_ROOT output : SEMC */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL /* Clock consumers of SPDIF0_CLK_ROOT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL /* Clock consumers of SPDIF0_EXTCLK_OUT output : SPDIF */ +#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL /* Clock consumers of TRACE_CLK_ROOT output : ARM */ +#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL /* Clock consumers of UART_CLK_ROOT output : LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8 */ +#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 480000000UL /* Clock consumers of USBPHY1_CLK output : TEMPMON, USB1 */ +#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 480000000UL /* Clock consumers of USBPHY2_CLK output : USB2 */ +#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL /* Clock consumers of USDHC1_CLK_ROOT output : USDHC1 */ +#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL /* Clock consumers of USDHC2_CLK_ROOT output : USDHC2 */ /*! @brief Arm PLL set for BOARD_BootClockRUN configuration. */ diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c index 8e975dc72..60c4bab37 100644 --- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.c @@ -6,11 +6,11 @@ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Pins v13.1 +product: Pins v17.0 processor: MIMXRT1064xxxxA package_id: MIMXRT1064DVL6A mcu_data: ksdk2_0 -processor_version: 13.0.2 +processor_version: 24.12.10 board: MIMXRT1064-EVK pin_labels: - {pin_num: F14, pin_signal: GPIO_AD_B0_09, label: 'JTAG_TDI/J21[5]/ENET_RST/J22[5]', identifier: USER_LED} @@ -81,7 +81,6 @@ void BOARD_InitPins(void) { IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0x50A0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitDEBUG_UARTPins: @@ -109,7 +108,6 @@ void BOARD_InitDEBUG_UARTPins(void) { IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_LPUART1_RX, 0x10B0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitSDRAMPins: @@ -209,7 +207,6 @@ void BOARD_InitSDRAMPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_39_SEMC_DQS, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitCSIPins: @@ -267,7 +264,6 @@ void BOARD_InitCSIPins(void) { IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA, 0xD8B0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitLCDPins: @@ -360,7 +356,6 @@ void BOARD_InitLCDPins(void) { IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_15_GPIO2_IO31, 0x10B0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitCANPins: @@ -384,7 +379,6 @@ void BOARD_InitCANPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitENETPins: @@ -424,7 +418,6 @@ void BOARD_InitENETPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitUSDHCPins: @@ -458,7 +451,6 @@ void BOARD_InitUSDHCPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3, 0U); } - /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* BOARD_InitQSPIPins: @@ -491,7 +483,6 @@ void BOARD_InitQSPIPins(void) { IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02, 0U); IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03, 0U); } - /*********************************************************************************************************************** * EOF **********************************************************************************************************************/ diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h index bf494b6f6..be1461f16 100644 --- a/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/board/pin_mux.h @@ -47,6 +47,7 @@ void BOARD_InitBootPins(void); /* Symbols to be used with GPIO driver */ #define BOARD_INITPINS_USER_LED_GPIO GPIO1 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ #define BOARD_INITPINS_USER_LED_GPIO_PIN 9U /*!< GPIO pin number */ #define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 9U) /*!< GPIO pin mask */ #define BOARD_INITPINS_USER_LED_PORT GPIO1 /*!< PORT peripheral base pointer */ diff --git a/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex b/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex index 3f0948101..58247fa5b 100644 --- a/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex +++ b/hw/bsp/imxrt/boards/mimxrt1064_evk/mimxrt1064_evk.mex @@ -1,5 +1,5 @@ - + MIMXRT1064xxxxA MIMXRT1064DVL6A @@ -13,19 +13,18 @@ true - false false true false - + - 13.0.2 + 24.12.10 @@ -41,7 +40,7 @@ true - + true @@ -84,7 +83,7 @@ true - + true @@ -137,7 +136,7 @@ true - + true @@ -204,12 +203,12 @@ true - + true - + true @@ -277,7 +276,7 @@ true - + true @@ -450,7 +449,7 @@ true - + true @@ -479,7 +478,7 @@ true - + true @@ -516,7 +515,7 @@ true - + true @@ -550,7 +549,7 @@ true - + true @@ -578,13 +577,13 @@ - + - 13.0.2 + 24.12.10 @@ -751,10 +750,7 @@ - - - - + 13.0.2 diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c index 66f1f983a..4f06299de 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/clock_config.c @@ -11,11 +11,11 @@ /* TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Clocks v14.0 +product: Clocks v15.0 processor: MIMXRT1176xxxxx package_id: MIMXRT1176DVMAA mcu_data: ksdk2_0 -processor_version: 16.3.0 +processor_version: 24.12.10 board: MIMXRT1170-EVKB * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/ diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c index 2c83fb55e..5e8cb91c1 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.c @@ -6,11 +6,11 @@ /* * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* !!GlobalInfo -product: Pins v16.0 +product: Pins v17.0 processor: MIMXRT1176xxxxx package_id: MIMXRT1176DVMAA mcu_data: ksdk2_0 -processor_version: 16.3.0 +processor_version: 24.12.10 board: MIMXRT1170-EVKB external_user_signals: {} pin_labels: @@ -31,6 +31,7 @@ pin_labels: * END ****************************************************************************************************************/ void BOARD_InitBootPins(void) { BOARD_InitPins(); + BOARD_InitDEBUG_UARTPins(); } /* @@ -38,10 +39,6 @@ void BOARD_InitBootPins(void) { BOARD_InitPins: - options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} - pin_list: - - {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, - open_drain: Disable, drive_strength: High, slew_rate: Slow} - - {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, software_input_on: Disable, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper, - open_drain: Disable, drive_strength: High, slew_rate: Slow} - {pin_num: M13, peripheral: GPIO9, signal: 'gpio_io, 03', pin_signal: GPIO_AD_04, identifier: USER_LED, direction: OUTPUT, pull_up_down_config: Pull_Down, pull_keeper_select: Keeper} - {pin_num: T8, peripheral: GPIO13, signal: 'gpio_io, 00', pin_signal: WAKEUP, direction: INPUT, pull_up_down_config: Pull_Up} * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** @@ -77,12 +74,6 @@ void BOARD_InitPins(void) { IOMUXC_SetPinMux( IOMUXC_GPIO_AD_04_GPIO9_IO03, /* GPIO_AD_04 is configured as GPIO9_IO03 */ 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ - IOMUXC_SetPinMux( - IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */ - 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinMux( IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG is configured as GPIO13_IO00 */ 0U); /* Software Input On Field: Input Path is determined by functionality */ @@ -95,6 +86,40 @@ void BOARD_InitPins(void) { Open Drain Field: Disabled Domain write protection: Both cores are allowed Domain write protection lock: Neither of DWP bits is locked */ + IOMUXC_SetPinConfig( + IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG PAD functional properties : */ + 0x0EU); /* Pull / Keep Select Field: Pull Enable + Pull Up / Down Config. Field: Weak pull up + Open Drain SNVS Field: Disabled + Domain write protection: Both cores are allowed + Domain write protection lock: Neither of DWP bits is locked */ +} + +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitDEBUG_UARTPins: +- options: {callFromInitBoot: 'true', coreID: cm7, enableClock: 'true'} +- pin_list: + - {pin_num: L13, peripheral: LPUART1, signal: TXD, pin_signal: GPIO_AD_24, pull_keeper_select: Keeper, slew_rate: Slow} + - {pin_num: M15, peripheral: LPUART1, signal: RXD, pin_signal: GPIO_AD_25, pull_keeper_select: Keeper, slew_rate: Slow} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitDEBUG_UARTPins, assigned for the Cortex-M7F core. + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitDEBUG_UARTPins(void) { + CLOCK_EnableClock(kCLOCK_Iomuxc); /* LPCG on: LPCG is ON. */ + + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 is configured as LPUART1_TXD */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ + IOMUXC_SetPinMux( + IOMUXC_GPIO_AD_25_LPUART1_RXD, /* GPIO_AD_25 is configured as LPUART1_RXD */ + 0U); /* Software Input On Field: Input Path is determined by functionality */ IOMUXC_SetPinConfig( IOMUXC_GPIO_AD_24_LPUART1_TXD, /* GPIO_AD_24 PAD functional properties : */ 0x02U); /* Slew Rate Field: Slow Slew Rate @@ -113,13 +138,6 @@ void BOARD_InitPins(void) { Open Drain Field: Disabled Domain write protection: Both cores are allowed Domain write protection lock: Neither of DWP bits is locked */ - IOMUXC_SetPinConfig( - IOMUXC_WAKEUP_DIG_GPIO13_IO00, /* WAKEUP_DIG PAD functional properties : */ - 0x0EU); /* Pull / Keep Select Field: Pull Enable - Pull Up / Down Config. Field: Weak pull up - Open Drain SNVS Field: Disabled - Domain write protection: Both cores are allowed - Domain write protection lock: Neither of DWP bits is locked */ } /*********************************************************************************************************************** * EOF diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h index a5b621476..0e0368ef6 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/board/pin_mux.h @@ -25,16 +25,6 @@ extern "C" { */ void BOARD_InitBootPins(void); -/* GPIO_AD_25 (coord M15), LPUART1_RXD */ -/* Routed pin properties */ -#define BOARD_INITPINS_LPUART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ -#define BOARD_INITPINS_LPUART1_RXD_SIGNAL RXD /*!< Signal name */ - -/* GPIO_AD_24 (coord L13), LPUART1_TXD */ -/* Routed pin properties */ -#define BOARD_INITPINS_LPUART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ -#define BOARD_INITPINS_LPUART1_TXD_SIGNAL TXD /*!< Signal name */ - /* GPIO_AD_04 (coord M13), SIM1_PD/J44[C8]/USER_LED_CTL1/J9[8]/J25[7] */ /* Routed pin properties */ #define BOARD_INITPINS_USER_LED_PERIPHERAL GPIO9 /*!< Peripheral name */ @@ -43,6 +33,7 @@ void BOARD_InitBootPins(void); /* Symbols to be used with GPIO driver */ #define BOARD_INITPINS_USER_LED_GPIO GPIO9 /*!< GPIO peripheral base pointer */ +#define BOARD_INITPINS_USER_LED_INIT_GPIO_VALUE 0U /*!< GPIO output initial state */ #define BOARD_INITPINS_USER_LED_GPIO_PIN 3U /*!< GPIO pin number */ #define BOARD_INITPINS_USER_LED_GPIO_PIN_MASK (1U << 3U) /*!< GPIO pin mask */ @@ -63,6 +54,22 @@ void BOARD_InitBootPins(void); */ void BOARD_InitPins(void); /* Function assigned for the Cortex-M7F */ +/* GPIO_AD_24 (coord L13), LPUART1_TXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_LPUART1_TXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_LPUART1_TXD_SIGNAL TXD /*!< Signal name */ + +/* GPIO_AD_25 (coord M15), LPUART1_RXD */ +/* Routed pin properties */ +#define BOARD_INITDEBUG_UARTPINS_LPUART1_RXD_PERIPHERAL LPUART1 /*!< Peripheral name */ +#define BOARD_INITDEBUG_UARTPINS_LPUART1_RXD_SIGNAL RXD /*!< Signal name */ + +/*! + * @brief Configures pin routing and optionally pin electrical features. + * + */ +void BOARD_InitDEBUG_UARTPins(void); /* Function assigned for the Cortex-M7F */ + #if defined(__cplusplus) } #endif diff --git a/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex b/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex index a4c8917f7..de6b12394 100644 --- a/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex +++ b/hw/bsp/imxrt/boards/mimxrt1170_evkb/mimxrt1170_evkb.mex @@ -1,5 +1,5 @@ - + MIMXRT1176xxxxx MIMXRT1176DVMAA @@ -13,19 +13,18 @@ true - false false true false - + - 16.3.0 + 24.12.10 @@ -43,11 +42,6 @@ true - - - true - - true @@ -65,51 +59,70 @@ - + - + + - - - - + - - - - - - + + - + + + + Configures pin routing and optionally pin electrical features. + + true + cm7 + true + + + + + true + + + + + true + + + + + true + + + + + - - - + - + - - + + - + - 16.3.0 + 24.12.10 diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index ad529a227..eaaf83c03 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -109,8 +109,8 @@ static void init_usb_phy(uint8_t usb_id) { } void board_init(void) { - BOARD_ConfigMPU(); - BOARD_InitPins(); + // BOARD_ConfigMPU(); + BOARD_InitBootPins(); BOARD_BootClockRUN(); SystemCoreClockUpdate(); diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index f08ccb3e5..6224b63a4 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -123,8 +123,6 @@ function(family_configure_example TARGET RTOS) # Board target add_board_target(board_${BOARD}) - #---------- Port Specific ---------- - # These files are built for each example since it depends on example's tusb_config.h target_sources(${TARGET} PUBLIC # BSP ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c @@ -146,8 +144,6 @@ function(family_configure_example TARGET RTOS) ) target_link_libraries(${TARGET} PUBLIC board_${BOARD}) - - # Flashing family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) -- cgit v1.3.1 From 1615120bca3c482b7ba3b2d5620393354acf9c81 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 26 Mar 2025 15:32:19 +0700 Subject: added mimxrt1064_evk to hil test pool --- hw/bsp/imxrt/family.c | 2 ++ 1 file changed, 2 insertions(+) (limited to 'hw') diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index eaaf83c03..7b89cc76d 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -258,6 +258,7 @@ void _exit(int __status) { //-------------------------------------------------------------------- // MPU configuration //-------------------------------------------------------------------- +#if 0 // TODO move to per board specific #if __CORTEX_M == 7 static void BOARD_ConfigMPU(void) { #if defined(__CC_ARM) || defined(__ARMCC_VERSION) @@ -636,3 +637,4 @@ void BOARD_ConfigMPU(void) { LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK; } #endif +#endif -- cgit v1.3.1 From 901ce2ad93b39c08e8e6b7e5b3f4dbd0b9df879e Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 26 Mar 2025 21:13:01 +0700 Subject: hcd/ehci: hcd_edpt_open() return false if ep is already opened. implement hcd_edpt_close() --- hw/bsp/imxrt/family.c | 4 +- src/device/usbd.c | 9 +- src/host/usbh.c | 2 +- src/portable/ehci/ehci.c | 259 ++++++++++++++++++++------------------ src/portable/ehci/ehci.h | 314 +++++++++++++++++++++++------------------------ test/hil/hil_test.py | 3 +- 6 files changed, 301 insertions(+), 290 deletions(-) (limited to 'hw') diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index 7b89cc76d..7e4734a66 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -61,7 +61,7 @@ - Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) */ -static void BOARD_ConfigMPU(void); +// static void BOARD_ConfigMPU(void); // needed by fsl_flexspi_nor_boot TU_ATTR_USED const uint8_t dcd_data[] = {0x00}; @@ -456,7 +456,7 @@ static void BOARD_ConfigMPU(void) { #elif __CORTEX_M == 4 -void BOARD_ConfigMPU(void) { +static void BOARD_ConfigMPU(void) { #if defined(__CC_ARM) || defined(__ARMCC_VERSION) extern uint32_t Image$$RW_m_ncache$$Base[]; /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */ diff --git a/src/device/usbd.c b/src/device/usbd.c index fb5cec49d..9c381d5e0 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -561,8 +561,7 @@ static void usbd_reset(uint8_t rhport) { } bool tud_task_event_ready(void) { - // Skip if stack is not initialized - if (!tud_inited()) return false; + TU_VERIFY(tud_inited()); // Skip if stack is not initialized return !osal_queue_empty(_usbd_q); } @@ -684,7 +683,9 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) { case USBD_EVENT_FUNC_CALL: TU_LOG_USBD("\r\n"); - if (event.func_call.func) event.func_call.func(event.func_call.param); + if (event.func_call.func) { + event.func_call.func(event.func_call.param); + } break; case DCD_EVENT_SOF: @@ -701,7 +702,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) { #if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO // return if there is no more events, for application to run other background - if (osal_queue_empty(_usbd_q)) return; + if (osal_queue_empty(_usbd_q)) { return; } #endif } } diff --git a/src/host/usbh.c b/src/host/usbh.c index 5925a7be0..e60db53da 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -520,7 +520,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { // Loop until there is no more events in the queue while (1) { hcd_event_t event; - if (!osal_queue_receive(_usbh_q, &event, timeout_ms)) return; + if (!osal_queue_receive(_usbh_q, &event, timeout_ms)) { return; } switch (event.event_id) { case HCD_EVENT_DEVICE_ATTACH: diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 01bbf62bf..292a352fb 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -62,8 +62,7 @@ #define QHD_MAX (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX + CFG_TUH_HUB) #define QTD_MAX QHD_MAX -typedef struct -{ +typedef struct { ehci_link_t period_framelist[FRAMELIST_SIZE]; // TODO only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist) @@ -139,6 +138,12 @@ static ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr); static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc); static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd); static void qhd_remove_qtd(ehci_qhd_t *qhd); +TU_ATTR_ALWAYS_INLINE static inline bool qhd_is_periodic(ehci_qhd_t const *qhd) { + return qhd->int_smask != 0; +} +TU_ATTR_ALWAYS_INLINE static inline uint8_t qhd_ep_addr(ehci_qhd_t const *qhd) { + return tu_edpt_addr(qhd->ep_number, qhd->pid); +} TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_control(uint8_t dev_addr); TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_find_free (void); @@ -146,9 +151,10 @@ static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes) TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_get_period_head(uint8_t rhport, uint32_t interval_ms); TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* list_get_async_head(uint8_t rhport); -TU_ATTR_ALWAYS_INLINE static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type); TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_next (ehci_link_t const *p_link); -static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr); +TU_ATTR_ALWAYS_INLINE static inline void list_insert (ehci_link_t *current, ehci_link_t *entry, uint8_t type); +TU_ATTR_ALWAYS_INLINE static inline void list_remove(ehci_link_t* head, ehci_link_t* prev, ehci_qhd_t* qhd); +static void list_remove_qhd_by_addr(ehci_link_t *list_head, uint8_t dev_addr, uint8_t ep_addr); static void ehci_disable_schedule(ehci_registers_t* regs, bool is_period) { // maybe have a timeout for status @@ -175,15 +181,12 @@ static void ehci_enable_schedule(ehci_registers_t* regs, bool is_period) { //--------------------------------------------------------------------+ // HCD API //--------------------------------------------------------------------+ - -uint32_t hcd_frame_number(uint8_t rhport) -{ +uint32_t hcd_frame_number(uint8_t rhport) { (void) rhport; return (ehci_data.uframe_number + ehci_data.regs->frame_index) >> 3; } -void hcd_port_reset(uint8_t rhport) -{ +void hcd_port_reset(uint8_t rhport) { (void) rhport; ehci_registers_t* regs = ehci_data.regs; @@ -204,8 +207,7 @@ void hcd_port_reset(uint8_t rhport) regs->portsc = portsc; } -void hcd_port_reset_end(uint8_t rhport) -{ +void hcd_port_reset_end(uint8_t rhport) { (void) rhport; ehci_registers_t* regs = ehci_data.regs; @@ -221,32 +223,29 @@ void hcd_port_reset_end(uint8_t rhport) regs->portsc = portsc; } -bool hcd_port_connect_status(uint8_t rhport) -{ +bool hcd_port_connect_status(uint8_t rhport) { (void) rhport; return ehci_data.regs->portsc_bm.current_connect_status; } -tusb_speed_t hcd_port_speed_get(uint8_t rhport) -{ +tusb_speed_t hcd_port_speed_get(uint8_t rhport) { (void) rhport; return (tusb_speed_t) ehci_data.regs->portsc_bm.nxp_port_speed; // NXP specific port speed } // Close all opened endpoint belong to this device -void hcd_device_close(uint8_t rhport, uint8_t daddr) -{ +void hcd_device_close(uint8_t rhport, uint8_t daddr) { // skip dev0 if (daddr == 0) { return; } - // Remove from async list - list_remove_qhd_by_daddr((ehci_link_t *) list_get_async_head(rhport), daddr); + // Remove from async list all endpoints of this device + list_remove_qhd_by_addr((ehci_link_t *) list_get_async_head(rhport), daddr, TUSB_INDEX_INVALID_8); - // Remove from all interval period list - for(uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) { - list_remove_qhd_by_daddr((ehci_link_t *) &ehci_data.period_head_arr[i], daddr); + // Remove from all interval period list of this device + for (uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) { + list_remove_qhd_by_addr((ehci_link_t *) &ehci_data.period_head_arr[i], daddr, TUSB_INDEX_INVALID_8); } // Async doorbell (EHCI 4.8.2 for operational details) @@ -358,12 +357,10 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg) } #if 0 -static void ehci_stop(uint8_t rhport) -{ +static void ehci_stop(uint8_t rhport) { (void) rhport; ehci_registers_t* regs = ehci_data.regs; - regs->command_bm.run_stop = 0; // USB Spec: controller has to stop within 16 uframe = 2 frames @@ -375,41 +372,44 @@ static void ehci_stop(uint8_t rhport) // Endpoint API //--------------------------------------------------------------------+ -bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) -{ - (void) rhport; - +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { // TODO not support ISO yet TU_ASSERT (ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS); //------------- Prepare Queue Head -------------// - ehci_qhd_t *p_qhd = (ep_desc->bEndpointAddress == 0) ? qhd_control(dev_addr) : qhd_find_free(); + ehci_qhd_t *p_qhd; + if (ep_desc->bEndpointAddress == 0) { + p_qhd = qhd_control(dev_addr); + } else { + TU_VERIFY(NULL == qhd_get_from_addr(dev_addr, ep_desc->bEndpointAddress)); // ep not opened yet + p_qhd = qhd_find_free(); + } TU_ASSERT(p_qhd); - qhd_init(p_qhd, dev_addr, ep_desc); - // control of dev0 is always present as async head - if ( dev_addr == 0 ) return true; + // control of dev0 always exists as async head + if (dev_addr == 0) { + return true; + } // Insert to list ehci_link_t * list_head = NULL; - - switch (ep_desc->bmAttributes.xfer) - { + switch (ep_desc->bmAttributes.xfer) { case TUSB_XFER_CONTROL: case TUSB_XFER_BULK: - list_head = (ehci_link_t*) list_get_async_head(rhport); - break; + list_head = (ehci_link_t *) list_get_async_head(rhport); + break; case TUSB_XFER_INTERRUPT: list_head = list_get_period_head(rhport, p_qhd->interval_ms); - break; + break; case TUSB_XFER_ISOCHRONOUS: // TODO iso is not supported - break; + break; - default: break; + default: + break; } TU_ASSERT(list_head); @@ -421,8 +421,23 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const return true; } -bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) -{ +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + ehci_qhd_t* qhd = qhd_get_from_addr(daddr, ep_addr); + TU_VERIFY(qhd != NULL); + + ehci_link_t * list_head; + if (qhd_is_periodic(qhd)) { + // interrupt endpoint + list_head = list_get_period_head(rhport, qhd->interval_ms);; + } else { + list_head = (ehci_link_t *) list_get_async_head(rhport); + } + + list_remove_qhd_by_addr(list_head, daddr, ep_addr); + return true; +} + +bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { (void) rhport; ehci_qhd_t* qhd = &ehci_data.control[dev_addr].qhd; @@ -444,14 +459,14 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet return true; } -bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) -{ +bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { (void) rhport; uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); ehci_qhd_t* qhd = qhd_get_from_addr(dev_addr, ep_addr); + TU_VERIFY(qhd != NULL); ehci_qtd_t* qtd; if (epnum == 0) { @@ -540,8 +555,7 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { // This isr mean it is safe to modify previously removed queue head from async list. // In tinyusb, queue head is only removed when device is unplugged. TU_ATTR_ALWAYS_INLINE static inline -void async_advance_isr(uint8_t rhport) -{ +void async_advance_isr(uint8_t rhport) { (void) rhport; ehci_qhd_t *qhd_pool = ehci_data.qhd_pool; @@ -612,8 +626,7 @@ void qhd_xfer_complete_isr(ehci_qhd_t * qhd) { } TU_ATTR_ALWAYS_INLINE static inline -void proccess_async_xfer_isr(ehci_qhd_t * const list_head) -{ +void proccess_async_xfer_isr(ehci_qhd_t * const list_head) { ehci_qhd_t *qhd = list_head; do { @@ -623,8 +636,7 @@ void proccess_async_xfer_isr(ehci_qhd_t * const list_head) } TU_ATTR_ALWAYS_INLINE static inline -void process_period_xfer_isr(uint8_t rhport, uint32_t interval_ms) -{ +void process_period_xfer_isr(uint8_t rhport, uint32_t interval_ms) { uint32_t const period_1ms_addr = (uint32_t) list_get_period_head(rhport, 1u); ehci_link_t next_link = *list_get_period_head(rhport, interval_ms); @@ -726,51 +738,55 @@ TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_next(ehci_link_t const *p_ return (ehci_link_t*) tu_align32(p_link->address); } -TU_ATTR_ALWAYS_INLINE static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type) -{ - new->address = current->address; - current->address = ((uint32_t) new) | (new_type << 1); +TU_ATTR_ALWAYS_INLINE static inline void list_insert(ehci_link_t *current, ehci_link_t *entry, uint8_t type) { + entry->address = current->address; + current->address = ((uint32_t) entry) | (type << 1); +} + +// Remove a queue head from the list. +// Per EHCI 4.8.2 the removed qhd's next is linked to list head (which always reachable by Host Controller) +// TODO support iTD/siTD +TU_ATTR_ALWAYS_INLINE static inline void list_remove(ehci_link_t* head, ehci_link_t* prev, ehci_qhd_t* qhd) { + // TODO deactivate all TD, wait for QHD to inactive before removal + prev->address = qhd->next.address; + + // link the removed qhd's next to list head + qhd->next.address = ((uint32_t) head) | (EHCI_QTYPE_QHD << 1); + + if (qhd_is_periodic(qhd)) { + // period list queue element is guarantee to be free in the next frame (1 ms) + qhd->used = 0; + } else { + // async list use async advance handshake. Mark as removing, will completely re-usable when async advance isr occurs + qhd->removing = 1; + } + + hcd_dcache_clean(qhd, sizeof(ehci_qhd_t)); + hcd_dcache_clean(prev, sizeof(ehci_qhd_t)); } -// Remove all queue head belong to this device address -static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr) { - ehci_link_t* prev = list_head; +// Remove queue head belong to this device address +static void list_remove_qhd_by_addr(ehci_link_t *list_head, uint8_t dev_addr, uint8_t ep_addr) { + ehci_link_t *prev = list_head; while (prev && !prev->terminate) { - ehci_qhd_t* qhd = (ehci_qhd_t*) (uintptr_t) list_next(prev); + ehci_qhd_t *qhd = (ehci_qhd_t *) (uintptr_t) list_next(prev); // done if loop back to head - if ( (uintptr_t) qhd == (uintptr_t) list_head) { + if ((uintptr_t) qhd == (uintptr_t) list_head) { break; } - if ( qhd->dev_addr == dev_addr ) { - // TODO deactivate all TD, wait for QHD to inactive before removal - prev->address = qhd->next.address; - - // EHCI 4.8.2 link the removed qhd's next to async head (which always reachable by Host Controller) - qhd->next.address = ((uint32_t) list_head) | (EHCI_QTYPE_QHD << 1); - - if ( qhd->int_smask ) - { - // period list queue element is guarantee to be free in the next frame (1 ms) - qhd->used = 0; - }else - { - // async list use async advance handshake - // mark as removing, will completely re-usable when async advance isr occurs - qhd->removing = 1; - } - - hcd_dcache_clean(qhd, sizeof(ehci_qhd_t)); - hcd_dcache_clean(prev, sizeof(ehci_qhd_t)); - }else { + // ep_addr is 0xff means all endpoints of this device address + if (qhd->dev_addr == dev_addr && + (ep_addr == TUSB_INDEX_INVALID_8 || qhd_ep_addr(qhd) == ep_addr)) { + list_remove(list_head, prev, qhd); + } else { prev = list_next(prev); } } } - //--------------------------------------------------------------------+ // Queue Header helper //--------------------------------------------------------------------+ @@ -782,8 +798,10 @@ TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_control(uint8_t dev_addr) { // Find a free queue head TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t *qhd_find_free(void) { - for ( uint32_t i = 0; i < QHD_MAX; i++ ) { - if ( !ehci_data.qhd_pool[i].used ) return &ehci_data.qhd_pool[i]; + for (uint32_t i = 0; i < QHD_MAX; i++) { + if (!ehci_data.qhd_pool[i].used) { + return &ehci_data.qhd_pool[i]; + } } return NULL; } @@ -800,10 +818,9 @@ static ehci_qhd_t *qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) { } ehci_qhd_t *qhd_pool = ehci_data.qhd_pool; - - for ( uint32_t i = 0; i < QHD_MAX; i++ ) { - if ( (qhd_pool[i].dev_addr == dev_addr) && - ep_addr == tu_edpt_addr(qhd_pool[i].ep_number, qhd_pool[i].pid) ) { + for (uint32_t i = 0; i < QHD_MAX; i++) { + if ((qhd_pool[i].dev_addr == dev_addr) && + ep_addr == qhd_ep_addr(&qhd_pool[i])) { return &qhd_pool[i]; } } @@ -812,8 +829,7 @@ static ehci_qhd_t *qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) { } // Init queue head with endpoint descriptor -static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) -{ +static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { // address 0 is used as async head, which always on the list --> cannot be cleared (ehci halted otherwise) if (dev_addr != 0) { tu_memclr(p_qhd, sizeof(ehci_qhd_t)); @@ -830,39 +846,43 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c p_qhd->ep_number = tu_edpt_number(ep_desc->bEndpointAddress); p_qhd->ep_speed = devtree_info.speed; p_qhd->data_toggle_control= (xfer_type == TUSB_XFER_CONTROL) ? 1 : 0; - p_qhd->head_list_flag = (dev_addr == 0) ? 1 : 0; // addr0's endpoint is the static asyn list head + p_qhd->head_list_flag = (dev_addr == 0) ? 1 : 0; // addr0's endpoint is the static async list head p_qhd->max_packet_size = tu_edpt_packet_size(ep_desc); p_qhd->fl_ctrl_ep_flag = ((xfer_type == TUSB_XFER_CONTROL) && (p_qhd->ep_speed != TUSB_SPEED_HIGH)) ? 1 : 0; p_qhd->nak_reload = 0; - // Bulk/Control -> smask = cmask = 0 - // TODO Isochronous - if (TUSB_XFER_INTERRUPT == xfer_type) - { - if (TUSB_SPEED_HIGH == p_qhd->ep_speed) - { - TU_ASSERT( interval <= 16, ); - if ( interval < 4) // sub millisecond interval - { - p_qhd->interval_ms = 0; - p_qhd->int_smask = (interval == 1) ? TU_BIN8(11111111) : - (interval == 2) ? TU_BIN8(10101010) : TU_BIN8(01000100); - }else - { - p_qhd->interval_ms = (uint8_t) tu_min16( 1 << (interval-4), 255 ); - p_qhd->int_smask = TU_BIT(interval % 8); + switch (xfer_type) { + case TUSB_XFER_CONTROL: + case TUSB_XFER_BULK: + p_qhd->int_smask = p_qhd->fl_int_cmask = 0; + break; + + case TUSB_XFER_INTERRUPT: + if (TUSB_SPEED_HIGH == p_qhd->ep_speed) { + TU_ASSERT(interval <= 16, ); + if (interval < 4) { + // sub millisecond interval + p_qhd->interval_ms = 0; + p_qhd->int_smask = (interval == 1) ? TU_BIN8(11111111) : + (interval == 2) ? TU_BIN8(10101010): TU_BIN8(01000100); + } else { + p_qhd->interval_ms = (uint8_t) tu_min16(1 << (interval - 4), 255); + p_qhd->int_smask = TU_BIT(interval % 8); + } + } else { + TU_ASSERT(0 != interval, ); + // Full/Low: 4.12.2.1 (EHCI) case 1 schedule start split at 1 us & complete split at 2,3,4 uframes + p_qhd->int_smask = 0x01; + p_qhd->fl_int_cmask = TU_BIN8(11100); + p_qhd->interval_ms = interval; } - }else - { - TU_ASSERT( 0 != interval, ); - // Full/Low: 4.12.2.1 (EHCI) case 1 schedule start split at 1 us & complete split at 2,3,4 uframes - p_qhd->int_smask = 0x01; - p_qhd->fl_int_cmask = TU_BIN8(11100); - p_qhd->interval_ms = interval; - } - }else - { - p_qhd->int_smask = p_qhd->fl_int_cmask = 0; + break; + + case TUSB_XFER_ISOCHRONOUS: + // TODO not support ISO yet + break; + + default: break; } p_qhd->fl_hub_addr = devtree_info.hub_addr; @@ -880,8 +900,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c p_qhd->qtd_overlay.next.terminate = 1; p_qhd->qtd_overlay.alternate.terminate = 1; - if (TUSB_XFER_BULK == xfer_type && p_qhd->ep_speed == TUSB_SPEED_HIGH && p_qhd->pid == EHCI_PID_OUT) - { + if (TUSB_XFER_BULK == xfer_type && p_qhd->ep_speed == TUSB_SPEED_HIGH && p_qhd->pid == EHCI_PID_OUT) { p_qhd->qtd_overlay.ping_err = 1; // do PING for Highspeed Bulk OUT, EHCI section 4.11 } } diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h index 457adc1d3..87659701b 100644 --- a/src/portable/ehci/ehci.h +++ b/src/portable/ehci/ehci.h @@ -49,15 +49,14 @@ // TODO merge OHCI with EHCI enum { - EHCI_MAX_ITD = 4, + EHCI_MAX_ITD = 4, EHCI_MAX_SITD = 16 }; //--------------------------------------------------------------------+ // EHCI Data Structure //--------------------------------------------------------------------+ -enum -{ +enum { EHCI_QTYPE_ITD = 0 , EHCI_QTYPE_QHD , EHCI_QTYPE_SITD , @@ -65,8 +64,7 @@ enum }; /// EHCI PID -enum -{ +enum { EHCI_PID_OUT = 0 , EHCI_PID_IN , EHCI_PID_SETUP @@ -74,187 +72,182 @@ enum /// Link pointer typedef union { - uint32_t address; - struct { - uint32_t terminate : 1; - uint32_t type : 2; - }; -}ehci_link_t; + uint32_t address; + struct { + uint32_t terminate : 1; + uint32_t type : 2; + }; +} ehci_link_t; TU_VERIFY_STATIC( sizeof(ehci_link_t) == 4, "size is not correct" ); /// Queue Element Transfer Descriptor /// Qtd is used to declare overlay in ehci_qhd_t -> cannot be declared with TU_ATTR_ALIGNED(32) -typedef struct -{ - // Word 0: Next QTD Pointer - ehci_link_t next; - - // Word 1: Alternate Next QTD Pointer (not used) - union{ - ehci_link_t alternate; - struct { - uint32_t : 5; - uint32_t used : 1; - uint32_t : 10; - uint32_t expected_bytes : 16; - }; - }; - - // Word 2: qTQ Token - volatile uint32_t ping_err : 1 ; ///< For Highspeed: 0 Out, 1 Ping. Full/Slow used as error indicator - volatile uint32_t non_hs_split_state : 1 ; ///< Used by HC to track the state of split transaction - volatile uint32_t non_hs_missed_uframe : 1 ; ///< HC misses a complete split transaction - volatile uint32_t xact_err : 1 ; ///< Error (Timeout, CRC, Bad PID ... ) - volatile uint32_t babble_err : 1 ; ///< Babble detected, also set Halted bit to 1 - volatile uint32_t buffer_err : 1 ; ///< Data overrun/underrun error - volatile uint32_t halted : 1 ; ///< Serious error or STALL received - volatile uint32_t active : 1 ; ///< Start transfer, clear by HC when complete - - uint32_t pid : 2 ; ///< 0: OUT, 1: IN, 2 Setup - volatile uint32_t err_count : 2 ; ///< Error Counter of consecutive errors - volatile uint32_t current_page : 3 ; ///< Index into the qTD buffer pointer list - uint32_t int_on_complete : 1 ; ///< Interrupt on complete - volatile uint32_t total_bytes : 15 ; ///< Transfer bytes, decreased during transaction - volatile uint32_t data_toggle : 1 ; ///< Data Toggle bit - - - /// Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page - uint32_t buffer[5]; +typedef struct { + // Word 0 Next QTD Pointer + ehci_link_t next; + + // Word 1 Alternate Next QTD Pointer (not used) + union { + ehci_link_t alternate; + struct { + uint32_t : 5; + uint32_t used : 1; + uint32_t : 10; + uint32_t expected_bytes : 16; + }; + }; + + // Word 2 qTQ Token + volatile uint32_t ping_err : 1; // For Highspeed: 0 Out, 1 Ping. Full/Slow used as error indicator + volatile uint32_t non_hs_split_state : 1; // Used by HC to track the state of split transaction + volatile uint32_t non_hs_missed_uframe : 1; // HC misses a complete split transaction + volatile uint32_t xact_err : 1; // Error (Timeout, CRC, Bad PID ... ) + volatile uint32_t babble_err : 1; // Babble detected, also set Halted bit to 1 + volatile uint32_t buffer_err : 1; // Data overrun/underrun error + volatile uint32_t halted : 1; // Serious error or STALL received + volatile uint32_t active : 1; // Start transfer, clear by HC when complete + + uint32_t pid : 2; // 0: OUT, 1: IN, 2 Setup + volatile uint32_t err_count : 2; // Error Counter of consecutive errors + volatile uint32_t current_page : 3; // Index into the qTD buffer pointer list + uint32_t int_on_complete : 1; // Interrupt on complete + volatile uint32_t total_bytes : 15; // Transfer bytes, decreased during transaction + volatile uint32_t data_toggle : 1; // Data Toggle bit + + // Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. + // The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page + uint32_t buffer[5]; } ehci_qtd_t; TU_VERIFY_STATIC( sizeof(ehci_qtd_t) == 32, "size is not correct" ); /// Queue Head -typedef struct TU_ATTR_ALIGNED(32) -{ - // Word 0: Next QHD - ehci_link_t next; - - // Word 1: Endpoint Characteristics - uint32_t dev_addr : 7 ; ///< device address - uint32_t fl_inactive_next_xact : 1 ; ///< Only valid for Periodic with Full/Slow speed - uint32_t ep_number : 4 ; ///< EP number - uint32_t ep_speed : 2 ; ///< 0: Full, 1: Low, 2: High - uint32_t data_toggle_control : 1 ; ///< 0: use DT in qHD, 1: use DT in qTD - uint32_t head_list_flag : 1 ; ///< Head of the queue - uint32_t max_packet_size : 11 ; ///< Max packet size - uint32_t fl_ctrl_ep_flag : 1 ; ///< 1 if is Full/Low speed control endpoint - uint32_t nak_reload : 4 ; ///< Used by HC - - // Word 2: Endpoint Capabilities - uint32_t int_smask : 8 ; ///< Interrupt Schedule Mask - uint32_t fl_int_cmask : 8 ; ///< Split Completion Mask for Full/Slow speed - uint32_t fl_hub_addr : 7 ; ///< Hub Address for Full/Slow speed - uint32_t fl_hub_port : 7 ; ///< Hub Port for Full/Slow speed - uint32_t mult : 2 ; ///< Transaction per micro frame - - // Word 3: Current qTD Pointer - volatile uint32_t qtd_addr; - - // Word 4-11: Transfer Overlay - volatile ehci_qtd_t qtd_overlay; - - //--------------------------------------------------------------------+ +typedef struct TU_ATTR_ALIGNED(32) { + // Word 0 Next QHD + ehci_link_t next; + + // Word 1 Endpoint Characteristics + uint32_t dev_addr : 7; // device address + uint32_t fl_inactive_next_xact : 1; // Only valid for Periodic with Full/Slow speed + uint32_t ep_number : 4; // EP number + uint32_t ep_speed : 2; // Full (0), Low (1), High (2) + uint32_t data_toggle_control : 1; // 0 use DT in qHD, 1 use DT in qTD + uint32_t head_list_flag : 1; // Head of the queue + uint32_t max_packet_size : 11; // Max packet size + uint32_t fl_ctrl_ep_flag : 1; // 1 if is Full/Low speed control endpoint + uint32_t nak_reload : 4; // Used by HC + + // Word 2 Endpoint Capabilities + uint32_t int_smask : 8; // Interrupt Schedule Mask + uint32_t fl_int_cmask : 8; // Split Completion Mask for Full/Slow speed + uint32_t fl_hub_addr : 7; // Hub Address for Full/Slow speed + uint32_t fl_hub_port : 7; // Hub Port for Full/Slow speed + uint32_t mult : 2; // Transaction per micro frame + + // Word 3 Current qTD Pointer + volatile uint32_t qtd_addr; + + // Word 4-11 Transfer Overlay + volatile ehci_qtd_t qtd_overlay; + + //--------------------------------------------------------------------+ /// Due to the fact QHD is 32 bytes aligned but occupies only 48 bytes - /// thus there are 16 bytes padding free that we can make use of. + /// thus there are 16 bytes padding free that we can make use of. //--------------------------------------------------------------------+ - uint8_t used; - uint8_t removing; // removed from asyn list, waiting for async advance - uint8_t pid; - uint8_t interval_ms; // polling interval in frames (or millisecond) + uint8_t used; + uint8_t removing;// removed from asyn list, waiting for async advance + uint8_t pid; + uint8_t interval_ms;// polling interval in frames (or millisecond) - uint8_t TU_RESERVED[4]; + uint8_t TU_RESERVED[4]; // Attached TD management, note usbh will only queue 1 TD per QHD. // buffer for dcache invalidate since td's buffer is modified by HC and finding initial buffer address is not trivial uint32_t attached_buffer; - ehci_qtd_t * volatile attached_qtd; + ehci_qtd_t *volatile attached_qtd; } ehci_qhd_t; - TU_VERIFY_STATIC( sizeof(ehci_qhd_t) == 64, "size is not correct" ); /// Highspeed Isochronous Transfer Descriptor (section 3.3) typedef struct TU_ATTR_ALIGNED(32) { - // Word 0: Next Link Pointer - ehci_link_t next; - - // Word 1-8: iTD Transaction Status and Control List - struct { - // iTD Control - volatile uint32_t offset : 12 ; ///< This field is a value that is an offset, expressed in bytes, from the beginning of a buffer. - volatile uint32_t page_select : 3 ; ///< These bits are set by software to indicate which of the buffer page pointers the offset field in this slot should be concatenated to produce the starting memory address for this transaction. The valid range of values for this field is 0 to 6 - uint32_t int_on_complete : 1 ; ///< If this bit is set to a one, it specifies that when this transaction completes, the Host Controller should issue an interrupt at the next interrupt threshold - volatile uint32_t length : 12 ; ///< For an OUT, this field is the number of data bytes the host controller will send during the transaction. The host controller is not required to update this field to reflect the actual number of bytes transferred during the transfer - ///< For an IN, the initial value of the field is the number of bytes the host expects the endpoint to deliver. During the status update, the host controller writes back the number of bytes successfully received. The value in this register is the actual byte count - // iTD Status - volatile uint32_t error : 1 ; ///< Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit may only be set for isochronous IN transactions. - volatile uint32_t babble_err : 1 ; ///< Set to a 1 by the Host Controller during status update when a babble is detected during the transaction - volatile uint32_t buffer_err : 1 ; ///< Set to a 1 by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (underrun). - volatile uint32_t active : 1 ; ///< Set to 1 by software to enable the execution of an isochronous transaction by the Host Controller - } xact[8]; - - // Word 9-15 Buffer Page Pointer List (Plus) - uint32_t BufferPointer[7]; - -// // FIXME: Store meta data into buffer pointer reserved for saving memory -// /*---------- HCD Area ----------*/ -// uint32_t used; -// uint32_t IhdIdx; -// uint32_t reserved[6]; + // Word 0: Next Link Pointer + ehci_link_t next; + + // Word 1-8: iTD Transaction Status and Control List + struct { + // iTD Control + volatile uint32_t offset : 12; // offset in bytes, from the beginning of a buffer. + volatile uint32_t page_select : 3; // buffer page pointers the offset field in this slot should be concatenated to produce the starting memory address for this transaction. The valid range of values for this field is 0 to 6 + uint32_t int_on_complete : 1; // If this bit is set to a one, it specifies that when this transaction completes, the Host Controller should issue an interrupt at the next interrupt threshold + volatile uint32_t length : 12; // For an OUT, this field is the number of data bytes the host controller will send during the transaction. The host controller is not required to update this field to reflect the actual number of bytes transferred during the transfer + // For an IN, the initial value of the field is the number of bytes the host expects the endpoint to deliver. During the status update, the host controller writes back the number of bytes successfully received. The value in this register is the actual byte count + // iTD Status + volatile uint32_t error : 1; // Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit may only be set for isochronous IN transactions. + volatile uint32_t babble_err : 1; // Set to a 1 by the Host Controller during status update when a babble is detected during the transaction + volatile uint32_t buffer_err : 1; // Set to a 1 by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (underrun). + volatile uint32_t active : 1; // Set to 1 by software to enable the execution of an isochronous transaction by the Host Controller + } xact[8]; + + // Word 9-15 Buffer Page Pointer List (Plus) + uint32_t BufferPointer[7]; + + // FIXME: Store meta data into buffer pointer reserved for saving memory + //---------- HCD Area ---------- + // uint32_t used; + // uint32_t IhdIdx; + // uint32_t reserved[6]; } ehci_itd_t; - TU_VERIFY_STATIC( sizeof(ehci_itd_t) == 64, "size is not correct" ); /// Split (Full-Speed) Isochronous Transfer Descriptor -typedef struct TU_ATTR_ALIGNED(32) -{ +typedef struct TU_ATTR_ALIGNED(32) { // Word 0: Next Link Pointer - ehci_link_t next; - - // Word 1: siTD Endpoint Characteristics - uint32_t dev_addr : 7; ///< This field selects the specific device serving as the data source or sink. - uint32_t : 1; ///< reserved - uint32_t ep_number : 4; ///< This 4-bit field selects the particular endpoint number on the device serving as the data source or sink. - uint32_t : 4; ///< This field is reserved and should be set to zero. - uint32_t hub_addr : 7; ///< This field holds the device address of the transaction translators’ hub. - uint32_t : 1; ///< reserved - uint32_t port_number : 7; ///< This field is the port number of the recipient transaction translator. - uint32_t direction : 1; ///< 0 = OUT; 1 = IN. This field encodes whether the full-speed transaction should be an IN or OUT. - - // Word 2: Micro-frame Schedule Control - uint8_t int_smask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute complete-split transactions - uint8_t fl_int_cmask; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute start-split transactions. - uint16_t reserved ; ///< reserved - - // Word 3: siTD Transfer Status and Control - // Status [7:0] TODO identical to qTD Token'status --> refactor later - volatile uint32_t : 1 ; // reserved - volatile uint32_t split_state : 1 ; - volatile uint32_t missed_uframe : 1 ; - volatile uint32_t xact_err : 1 ; - volatile uint32_t babble_err : 1 ; - volatile uint32_t buffer_err : 1 ; - volatile uint32_t error : 1 ; - volatile uint32_t active : 1 ; - // Micro-frame Schedule Control - volatile uint32_t cmask_progress : 8 ; ///< This field is used by the host controller to record which split-completes have been executed. See Section 4.12.3.3.2 for behavioral requirements. - volatile uint32_t total_bytes : 10 ; ///< This field is initialized by software to the total number of bytes expected in this transfer. Maximum value is 1023 - volatile uint32_t : 4 ; ///< reserved - volatile uint32_t page_select : 1 ; ///< Used to indicate which data page pointer should be concatenated with the CurrentOffsetfield to construct a data buffer pointer - uint32_t int_on_complete : 1 ; ///< Do not interrupt when transaction is complete. 1 = Do interrupt when transaction is complete - uint32_t : 0 ; // padding to the end of current storage unit - - /// Word 4-5: Buffer Pointer List - uint32_t buffer[2]; // buffer[1] TP: Transaction Position - T-Count: Transaction Count - - /*---------- Word 6 ----------*/ - ehci_link_t back; - - /// SITD is 32-byte aligned but occupies only 28 --> 4 bytes for storing extra data - uint8_t used; - uint8_t ihd_idx; - uint8_t reserved2[2]; + ehci_link_t next; + + // Word 1: siTD Endpoint Characteristics + uint32_t dev_addr : 7; ///< This field selects the specific device serving as the data source or sink. + uint32_t : 1; ///< reserved + uint32_t ep_number : 4; ///< This 4-bit field selects the particular endpoint number on the device serving as the data source or sink. + uint32_t : 4; ///< This field is reserved and should be set to zero. + uint32_t hub_addr : 7; ///< This field holds the device address of the transaction translators’ hub. + uint32_t : 1; ///< reserved + uint32_t port_number : 7; ///< This field is the port number of the recipient transaction translator. + uint32_t direction : 1; ///< 0 = OUT; 1 = IN. This field encodes whether the full-speed transaction should be an IN or OUT. + + // Word 2: Micro-frame Schedule Control + uint8_t int_smask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute complete-split transactions + uint8_t fl_int_cmask; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute start-split transactions. + uint16_t reserved ; ///< reserved + + // Word 3: siTD Transfer Status and Control + // Status [7:0] TODO identical to qTD Token'status --> refactor later + volatile uint32_t : 1 ; // reserved + volatile uint32_t split_state : 1 ; + volatile uint32_t missed_uframe : 1 ; + volatile uint32_t xact_err : 1 ; + volatile uint32_t babble_err : 1 ; + volatile uint32_t buffer_err : 1 ; + volatile uint32_t error : 1 ; + volatile uint32_t active : 1 ; + // Micro-frame Schedule Control + volatile uint32_t cmask_progress : 8 ; ///< This field is used by the host controller to record which split-completes have been executed. See Section 4.12.3.3.2 for behavioral requirements. + volatile uint32_t total_bytes : 10 ; ///< This field is initialized by software to the total number of bytes expected in this transfer. Maximum value is 1023 + volatile uint32_t : 4 ; ///< reserved + volatile uint32_t page_select : 1 ; ///< Used to indicate which data page pointer should be concatenated with the CurrentOffsetfield to construct a data buffer pointer + uint32_t int_on_complete : 1 ; ///< Do not interrupt when transaction is complete. 1 = Do interrupt when transaction is complete + uint32_t : 0 ; // padding to the end of current storage unit + + /// Word 4-5: Buffer Pointer List + uint32_t buffer[2]; // buffer[1] TP: Transaction Position - T-Count: Transaction Count + + /*---------- Word 6 ----------*/ + ehci_link_t back; + + /// SITD is 32-byte aligned but occupies only 28 --> 4 bytes for storing extra data + uint8_t used; + uint8_t ihd_idx; + uint8_t reserved2[2]; } ehci_sitd_t; TU_VERIFY_STATIC( sizeof(ehci_sitd_t) == 32, "size is not correct" ); @@ -315,8 +308,7 @@ enum { EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE }; -typedef volatile struct -{ +typedef volatile struct { union { uint32_t command; // 0x00 diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py index 662bb3a1f..8b89de66c 100755 --- a/test/hil/hil_test.py +++ b/test/hil/hil_test.py @@ -340,8 +340,8 @@ def test_host_device_info(board): ser.close() if len(data) == 0: assert False, 'No data from device' - lines = data.decode('utf-8', errors='ignore').splitlines() + enum_dev_sn = [] for l in lines: vid_pid_sn = re.search(r'ID ([0-9a-fA-F]+):([0-9a-fA-F]+) SN (\w+)', l) @@ -353,7 +353,6 @@ def test_host_device_info(board): failed_msg = f'Expected {declared_devs}, Enumerated {enum_dev_sn}' print('\n'.join(lines)) assert False, failed_msg - return 0 -- cgit v1.3.1 From 1f2f92d97aea21345d0391caac05432ad06f4136 Mon Sep 17 00:00:00 2001 From: Radomir Dopieralski Date: Fri, 7 Mar 2025 12:20:33 +0100 Subject: Allow different port and mode for LED on ch32v boards While there is a define for the port, the clock enable is hardcoded for GPIOA, so setting a different port than GPIOA doesn't work. This fixes it by adding a define for enabling the port clock. It also adds a define for the pin mode, because not all boards have the LED connected in a way that open drain works with it. --- hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h | 2 ++ hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h | 2 ++ hw/bsp/ch32v20x/boards/nanoch32v203/board.h | 2 ++ hw/bsp/ch32v20x/family.c | 4 ++-- 4 files changed, 8 insertions(+), 2 deletions(-) (limited to 'hw') diff --git a/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h index 256958088..56f49205c 100644 --- a/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h +++ b/hw/bsp/ch32v20x/boards/ch32v203c_r0_1v0/board.h @@ -13,6 +13,8 @@ extern "C" { #define LED_PORT GPIOA #define LED_PIN GPIO_Pin_0 #define LED_STATE_ON 0 +#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE) +#define LED_MODE GPIO_Mode_Out_OD #define UART_DEV USART1 #define UART_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE) diff --git a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h index 827226d80..4a040e0df 100644 --- a/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h +++ b/hw/bsp/ch32v20x/boards/ch32v203g_r0_1v0/board.h @@ -13,6 +13,8 @@ extern "C" { #define LED_PORT GPIOA #define LED_PIN GPIO_Pin_0 #define LED_STATE_ON 0 +#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE) +#define LED_MODE GPIO_Mode_Out_OD #define UART_DEV USART2 #define UART_CLOCK_EN() RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE) diff --git a/hw/bsp/ch32v20x/boards/nanoch32v203/board.h b/hw/bsp/ch32v20x/boards/nanoch32v203/board.h index f02fceced..63237861c 100644 --- a/hw/bsp/ch32v20x/boards/nanoch32v203/board.h +++ b/hw/bsp/ch32v20x/boards/nanoch32v203/board.h @@ -13,6 +13,8 @@ extern "C" { #define LED_PORT GPIOA #define LED_PIN GPIO_Pin_15 #define LED_STATE_ON 0 +#define LED_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE) +#define LED_MODE GPIO_Mode_Out_OD #define UART_DEV USART1 #define UART_CLOCK_EN() RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE) diff --git a/hw/bsp/ch32v20x/family.c b/hw/bsp/ch32v20x/family.c index 5f52d9447..21ed94b0a 100644 --- a/hw/bsp/ch32v20x/family.c +++ b/hw/bsp/ch32v20x/family.c @@ -96,11 +96,11 @@ void board_init(void) { SysTick_Config(SystemCoreClock / 1000); #endif - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + LED_CLOCK_EN(); GPIO_InitTypeDef GPIO_InitStructure = { .GPIO_Pin = LED_PIN, - .GPIO_Mode = GPIO_Mode_Out_OD, + .GPIO_Mode = LED_MODE, .GPIO_Speed = GPIO_Speed_10MHz, }; GPIO_Init(LED_PORT, &GPIO_InitStructure); -- cgit v1.3.1