From 017c95037f3173455fa09efae6093d56fd3f3d1a Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 26 Apr 2020 14:51:44 +0700 Subject: add usbd edpt open - RTT mode is blocking to prevent log lost - Improve logging message --- src/common/tusb_common.h | 12 ++++++++++-- src/common/tusb_verify.h | 6 +++--- 2 files changed, 13 insertions(+), 5 deletions(-) (limited to 'src/common') diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 2d80f8210..fcb22cde1 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -219,17 +219,25 @@ void tu_print_mem(void const *buf, uint16_t count, uint8_t indent); #define tu_printf printf #endif +static inline +void tu_print_var(uint8_t const* buf, uint32_t bufsize) +{ + for(uint32_t i=0; i 1 #define TU_LOG2 TU_LOG1 #define TU_LOG2_MEM TU_LOG1_MEM + #define TU_LOG2_VAR TU_LOG1_VAR #define TU_LOG2_LOCATION() TU_LOG1_LOCATION() #define TU_LOG2_INT TU_LOG1_INT #define TU_LOG2_HEX TU_LOG1_HEX diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h index fee291df6..406f5e6ee 100644 --- a/src/common/tusb_verify.h +++ b/src/common/tusb_verify.h @@ -90,13 +90,13 @@ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */ \ } while(0) -#else -#if defined(__riscv) + +#elif defined(__riscv) #define TU_BREAKPOINT() do { __asm("ebreak\n"); } while(0) + #else #define TU_BREAKPOINT() do {} while (0) #endif -#endif /*------------------------------------------------------------------*/ /* Macro Generator -- cgit v1.3.1