From 5b68cc91ad5059c595536016c19a914af6928296 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 1 Nov 2019 17:50:40 +0700 Subject: adding TEST_FAIL() for TU_ASSERT() --- src/common/tusb_verify.h | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) (limited to 'src/common') diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h index e59481352..5ae3afc95 100644 --- a/src/common/tusb_verify.h +++ b/src/common/tusb_verify.h @@ -73,13 +73,21 @@ //--------------------------------------------------------------------+ // TU_VERIFY Helper //--------------------------------------------------------------------+ + +// Running unit tests +#ifdef _UNITY_TEST_ + #define _TEST_FAILED() TEST_FAIL(); +#else + #define _TEST_FAILED() +#endif + #if CFG_TUSB_DEBUG #include - #define _MESS_ERR(_err) printf("%s: %d: failed, error = %s\n", __func__, __LINE__, tusb_strerr[_err]) - #define _MESS_FAILED() printf("%s: %d: failed\n", __func__, __LINE__) + #define _MESS_ERR(_err) printf("%s %d: failed, error = %s\n", __func__, __LINE__, tusb_strerr[_err]) + #define _MESS_FAILED() do { printf("%s %d: assert failed\n", __func__, __LINE__); _TEST_FAILED() } while(0) #else #define _MESS_ERR(_err) - #define _MESS_FAILED() + #define _MESS_FAILED() _TEST_FAILED() #endif // Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7 -- cgit v1.3.1 From 838173efc34ab3c55e925176a378a47f9ba65e7e Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 1 Nov 2019 18:27:15 +0700 Subject: remove TEST_FAIL() from TU_ASSERT, since it prevents we testing how stack response with failed assert --- src/common/tusb_verify.h | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) (limited to 'src/common') diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h index 5ae3afc95..41364d055 100644 --- a/src/common/tusb_verify.h +++ b/src/common/tusb_verify.h @@ -74,20 +74,13 @@ // TU_VERIFY Helper //--------------------------------------------------------------------+ -// Running unit tests -#ifdef _UNITY_TEST_ - #define _TEST_FAILED() TEST_FAIL(); -#else - #define _TEST_FAILED() -#endif - #if CFG_TUSB_DEBUG #include #define _MESS_ERR(_err) printf("%s %d: failed, error = %s\n", __func__, __LINE__, tusb_strerr[_err]) - #define _MESS_FAILED() do { printf("%s %d: assert failed\n", __func__, __LINE__); _TEST_FAILED() } while(0) + #define _MESS_FAILED() printf("%s %d: assert failed\n", __func__, __LINE__) #else #define _MESS_ERR(_err) - #define _MESS_FAILED() _TEST_FAILED() + #define _MESS_FAILED() #endif // Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7 -- cgit v1.3.1 From 359189ea2d791ab895dc29cbfa4e3eba14caf65f Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Mon, 14 Oct 2019 11:58:17 +0800 Subject: tusb_verify: add riscv assert support This simply executes an "ebreak" instruction. Signed-off-by: Sean Cross --- src/common/tusb_verify.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/common') diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h index e59481352..2b63ab946 100644 --- a/src/common/tusb_verify.h +++ b/src/common/tusb_verify.h @@ -89,9 +89,13 @@ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \ if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */ \ } while(0) +#else +#if defined(__riscv) + #define TU_BREAKPOINT() do { __asm("ebreak\n"); } while(0) #else #define TU_BREAKPOINT() #endif +#endif /*------------------------------------------------------------------*/ /* Macro Generator -- cgit v1.3.1