From 8ab1e4fbd01f9ec0f01cbfee26e72c73f8eeea44 Mon Sep 17 00:00:00 2001 From: dp111 <19616418+dp111@users.noreply.github.com> Date: Tue, 3 Sep 2024 19:38:34 +0100 Subject: make function prototypes match ( found by cppcheck) --- src/device/usbd_control.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/device/usbd_control.c') diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index 35cce1f7e..b1fd357aa 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -137,7 +137,7 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const* request, voi void usbd_control_reset(void); void usbd_control_set_request(tusb_control_request_t const* request); void usbd_control_set_complete_callback(usbd_control_xfer_cb_t fp); -bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes); +bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); void usbd_control_reset(void) { tu_varclr(&_ctrl_xfer); -- cgit v1.3.1 From fa523a5682d8dc91cc1c7a63475623743e37ac83 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 21 Nov 2024 10:15:30 +0700 Subject: make sure usb buffer occupies whole cache line when DCACHE is enabled for msc,cdc,hid HIL enable device DMA for p4 --- .../boards/espressif_p4_function_ev/board.h | 4 +- src/class/cdc/cdc_device.c | 10 +- src/class/hid/hid_device.c | 15 ++- src/class/msc/msc_device.c | 125 +++++++++------------ src/common/tusb_common.h | 3 + src/common/tusb_compiler.h | 5 +- src/device/usbd_control.c | 29 ++--- src/portable/synopsys/dwc2/dcd_dwc2.c | 8 +- src/tusb_option.h | 6 +- test/hil/tinyusb.json | 3 + 10 files changed, 105 insertions(+), 103 deletions(-) (limited to 'src/device/usbd_control.c') diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h index 0022f0d2d..c4f73c72e 100644 --- a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h +++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h @@ -8,7 +8,7 @@ * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: + * furnished to do so, subject to the following conditions:aaaaa * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. @@ -33,7 +33,7 @@ // #define NEOPIXEL_PIN 48 -#define BUTTON_PIN 0 +#define BUTTON_PIN 35 #define BUTTON_STATE_ACTIVE 0 // For CI hardware test, to test both device and host on the same HS port with help of diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index ebc408f5a..3e856383e 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -69,8 +69,14 @@ typedef struct { OSAL_MUTEX_DEF(tx_ff_mutex); // Endpoint Transfer buffer - CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE]; - CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE]; + union { + CFG_TUD_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; + union { + CFG_TUD_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; } cdcd_interface_t; #define ITF_MEM_RESET_SIZE offsetof(cdcd_interface_t, wanted_char) diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c index ef6c7f3af..257af86e0 100644 --- a/src/class/hid/hid_device.c +++ b/src/class/hid/hid_device.c @@ -53,9 +53,18 @@ typedef struct { // Note: HID descriptor may be not available from application after enumeration tusb_hid_descriptor_hid_t const *hid_descriptor; - uint8_t ctrl_buf[CFG_TUD_HID_EP_BUFSIZE]; - CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_HID_EP_BUFSIZE]; - CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_HID_EP_BUFSIZE]; + union { + CFG_TUD_MEM_ALIGN uint8_t ctrl_buf[CFG_TUD_HID_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; + union { + CFG_TUD_MEM_ALIGN uint8_t epin_buf[CFG_TUD_HID_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; + union { + CFG_TUD_MEM_ALIGN uint8_t epout_buf[CFG_TUD_HID_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; } hidd_interface_t; CFG_TUD_MEM_SECTION tu_static hidd_interface_t _hidd_itf[CFG_TUD_HID]; diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 447560b4d..af035bcf3 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -44,8 +44,7 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ -enum -{ +enum { MSC_STAGE_CMD = 0, MSC_STAGE_DATA, MSC_STAGE_STATUS, @@ -53,11 +52,19 @@ enum MSC_STAGE_NEED_RESET, }; -typedef struct -{ - // TODO optimize alignment - CFG_TUSB_MEM_ALIGN msc_cbw_t cbw; - CFG_TUSB_MEM_ALIGN msc_csw_t csw; +typedef struct { + union { + CFG_TUD_MEM_ALIGN msc_cbw_t cbw; + TUD_DCACHE_PADDING; + }; + union { + CFG_TUD_MEM_ALIGN msc_csw_t csw; + TUD_DCACHE_PADDING; + }; + union { + CFG_TUD_MEM_ALIGN uint8_t ep_buf[CFG_TUD_MSC_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; uint8_t itf_num; uint8_t ep_in; @@ -74,8 +81,7 @@ typedef struct uint8_t add_sense_qualifier; }mscd_interface_t; -CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static mscd_interface_t _mscd_itf; -CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE]; +CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN static mscd_interface_t _mscd_itf; //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION @@ -86,13 +92,11 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc); static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc); static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint32_t xferred_bytes); -TU_ATTR_ALWAYS_INLINE static inline bool is_data_in(uint8_t dir) -{ +TU_ATTR_ALWAYS_INLINE static inline bool is_data_in(uint8_t dir) { return tu_bit_test(dir, 7); } -static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc) -{ +static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc) { // Data residue is always = host expect - actual transferred p_msc->csw.data_residue = p_msc->cbw.total_bytes - p_msc->xferred_len; @@ -100,14 +104,12 @@ static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc) return usbd_edpt_xfer(rhport, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)); } -static inline bool prepare_cbw(uint8_t rhport, mscd_interface_t* p_msc) -{ +static inline bool prepare_cbw(uint8_t rhport, mscd_interface_t* p_msc) { p_msc->stage = MSC_STAGE_CMD; return usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)); } -static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status) -{ +static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status) { msc_cbw_t const * p_cbw = &p_msc->cbw; msc_csw_t * p_csw = &p_msc->csw; @@ -116,24 +118,21 @@ static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status p_msc->stage = MSC_STAGE_STATUS; // failed but sense key is not set: default to Illegal Request - if ( p_msc->sense_key == 0 ) tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); + if (p_msc->sense_key == 0) { + tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); + } // If there is data stage and not yet complete, stall it - if ( p_cbw->total_bytes && p_csw->data_residue ) - { - if ( is_data_in(p_cbw->dir) ) - { + if (p_cbw->total_bytes && p_csw->data_residue) { + if (is_data_in(p_cbw->dir)) { usbd_edpt_stall(rhport, p_msc->ep_in); - } - else - { + } else { usbd_edpt_stall(rhport, p_msc->ep_out); } } } -static inline uint32_t rdwr10_get_lba(uint8_t const command[]) -{ +static inline uint32_t rdwr10_get_lba(uint8_t const command[]) { // use offsetof to avoid pointer to the odd/unaligned address uint32_t const lba = tu_unaligned_read32(command + offsetof(scsi_write10_t, lba)); @@ -141,14 +140,12 @@ static inline uint32_t rdwr10_get_lba(uint8_t const command[]) return tu_ntohl(lba); } -static inline uint16_t rdwr10_get_blockcount(msc_cbw_t const* cbw) -{ +static inline uint16_t rdwr10_get_blockcount(msc_cbw_t const* cbw) { uint16_t const block_count = tu_unaligned_read16(cbw->command + offsetof(scsi_write10_t, block_count)); return tu_ntohs(block_count); } -static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) -{ +static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) { // first extract block count in the command uint16_t const block_count = rdwr10_get_blockcount(cbw); @@ -158,40 +155,28 @@ static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) return (uint16_t) (cbw->total_bytes / block_count); } -uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) -{ +uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) { uint8_t status = MSC_CSW_STATUS_PASSED; uint16_t const block_count = rdwr10_get_blockcount(cbw); - if ( cbw->total_bytes == 0 ) - { - if ( block_count ) - { + if (cbw->total_bytes == 0) { + if (block_count) { TU_LOG_DRV(" SCSI case 2 (Hn < Di) or case 3 (Hn < Do) \r\n"); status = MSC_CSW_STATUS_PHASE_ERROR; - }else - { + } else { // no data transfer, only exist in complaint test suite } - }else - { - if ( SCSI_CMD_READ_10 == cbw->command[0] && !is_data_in(cbw->dir) ) - { + } else { + if (SCSI_CMD_READ_10 == cbw->command[0] && !is_data_in(cbw->dir)) { TU_LOG_DRV(" SCSI case 10 (Ho <> Di)\r\n"); status = MSC_CSW_STATUS_PHASE_ERROR; - } - else if ( SCSI_CMD_WRITE_10 == cbw->command[0] && is_data_in(cbw->dir) ) - { + } else if (SCSI_CMD_WRITE_10 == cbw->command[0] && is_data_in(cbw->dir)) { TU_LOG_DRV(" SCSI case 8 (Hi <> Do)\r\n"); status = MSC_CSW_STATUS_PHASE_ERROR; - } - else if ( 0 == block_count ) - { + } else if (0 == block_count) { TU_LOG_DRV(" SCSI case 4 Hi > Dn (READ10) or case 9 Ho > Dn (WRITE10) \r\n"); - status = MSC_CSW_STATUS_FAILED; - } - else if ( cbw->total_bytes / block_count == 0 ) - { + status = MSC_CSW_STATUS_FAILED; + } else if (cbw->total_bytes / block_count == 0) { TU_LOG_DRV(" Computed block size = 0. SCSI case 7 Hi < Di (READ10) or case 13 Ho < Do (WRIT10)\r\n"); status = MSC_CSW_STATUS_PHASE_ERROR; } @@ -205,8 +190,7 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG >= CFG_TUD_MSC_LOG_LEVEL -TU_ATTR_UNUSED tu_static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = -{ +TU_ATTR_UNUSED tu_static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = { { .key = SCSI_CMD_TEST_UNIT_READY , .data = "Test Unit Ready" }, { .key = SCSI_CMD_INQUIRY , .data = "Inquiry" }, { .key = SCSI_CMD_MODE_SELECT_6 , .data = "Mode_Select 6" }, @@ -220,8 +204,7 @@ TU_ATTR_UNUSED tu_static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = { .key = SCSI_CMD_WRITE_10 , .data = "Write10" } }; -TU_ATTR_UNUSED tu_static tu_lookup_table_t const _msc_scsi_cmd_table = -{ +TU_ATTR_UNUSED tu_static tu_lookup_table_t const _msc_scsi_cmd_table = { .count = TU_ARRAY_SIZE(_msc_scsi_cmd_lookup), .items = _msc_scsi_cmd_lookup }; @@ -462,7 +445,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // 2. IN & Zero: Process if is built-in, else Invoke app callback. Skip DATA if zero length if ( (p_cbw->total_bytes > 0 ) && !is_data_in(p_cbw->dir) ) { - if (p_cbw->total_bytes > sizeof(_mscd_buf)) + if (p_cbw->total_bytes > CFG_TUD_MSC_EP_BUFSIZE) { TU_LOG_DRV(" SCSI reject non READ10/WRITE10 with large data\r\n"); fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); @@ -470,17 +453,17 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t { // Didn't check for case 9 (Ho > Dn), which requires examining scsi command first // but it is OK to just receive data then responded with failed status - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, (uint16_t) p_msc->total_len) ); + TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, p_msc->ep_buf, (uint16_t) p_msc->total_len) ); } }else { // First process if it is a built-in commands - int32_t resplen = proc_builtin_scsi(p_cbw->lun, p_cbw->command, _mscd_buf, sizeof(_mscd_buf)); + int32_t resplen = proc_builtin_scsi(p_cbw->lun, p_cbw->command, p_msc->ep_buf, CFG_TUD_MSC_EP_BUFSIZE); // Invoke user callback if not built-in if ( (resplen < 0) && (p_msc->sense_key == 0) ) { - resplen = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, (uint16_t) p_msc->total_len); + resplen = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, p_msc->ep_buf, (uint16_t) p_msc->total_len); } if ( resplen < 0 ) @@ -513,7 +496,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t { // cannot return more than host expect p_msc->total_len = tu_min32((uint32_t) resplen, p_cbw->total_bytes); - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_buf, (uint16_t) p_msc->total_len) ); + TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, p_msc->ep_buf, (uint16_t) p_msc->total_len) ); } } } @@ -522,7 +505,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t case MSC_STAGE_DATA: TU_LOG_DRV(" SCSI Data [Lun%u]\r\n", p_cbw->lun); - //TU_LOG_MEM(MSC_DEBUG, _mscd_buf, xferred_bytes, 2); + //TU_LOG_MEM(MSC_DEBUG, p_msc->ep_buf, xferred_bytes, 2); if (SCSI_CMD_READ_10 == p_cbw->command[0]) { @@ -548,7 +531,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // OUT transfer, invoke callback if needed if ( !is_data_in(p_cbw->dir) ) { - int32_t cb_result = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, (uint16_t) p_msc->total_len); + int32_t cb_result = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, p_msc->ep_buf, (uint16_t) p_msc->total_len); if ( cb_result < 0 ) { @@ -861,11 +844,11 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz); // remaining bytes capped at class buffer - int32_t nbytes = (int32_t) tu_min32(sizeof(_mscd_buf), p_cbw->total_bytes-p_msc->xferred_len); + int32_t nbytes = (int32_t) tu_min32(CFG_TUD_MSC_EP_BUFSIZE, p_cbw->total_bytes-p_msc->xferred_len); // Application can consume smaller bytes uint32_t const offset = p_msc->xferred_len % block_sz; - nbytes = tud_msc_read10_cb(p_cbw->lun, lba, offset, _mscd_buf, (uint32_t) nbytes); + nbytes = tud_msc_read10_cb(p_cbw->lun, lba, offset, p_msc->ep_buf, (uint32_t) nbytes); if ( nbytes < 0 ) { @@ -884,7 +867,7 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) } else { - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_buf, (uint16_t) nbytes), ); + TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, p_msc->ep_buf, (uint16_t) nbytes), ); } } @@ -908,10 +891,10 @@ static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc) } // remaining bytes capped at class buffer - uint16_t nbytes = (uint16_t) tu_min32(sizeof(_mscd_buf), p_cbw->total_bytes-p_msc->xferred_len); + uint16_t nbytes = (uint16_t) tu_min32(CFG_TUD_MSC_EP_BUFSIZE, p_cbw->total_bytes-p_msc->xferred_len); // Write10 callback will be called later when usb transfer complete - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, nbytes), ); + TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, p_msc->ep_buf, nbytes), ); } // process new data arrived from WRITE10 @@ -927,7 +910,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 // Invoke callback to consume new data uint32_t const offset = p_msc->xferred_len % block_sz; - int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, offset, _mscd_buf, xferred_bytes); + int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, offset, p_msc->ep_buf, xferred_bytes); if ( nbytes < 0 ) { @@ -950,7 +933,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 if ( nbytes > 0 ) { p_msc->xferred_len += (uint16_t) nbytes; - memmove(_mscd_buf, _mscd_buf+nbytes, left_over); + memmove(p_msc->ep_buf, p_msc->ep_buf+nbytes, left_over); } // simulate an transfer complete with adjusted parameters --> callback will be invoked with adjusted parameter diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 59cc0fb48..416bad296 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -58,6 +58,9 @@ // Generate a mask with bit from high (31) to low (0) set, e.g TU_GENMASK(3, 0) = 0b1111 #define TU_GENMASK(h, l) ( (UINT32_MAX << (l)) & (UINT32_MAX >> (31 - (h))) ) +// DCache padding for variable to occupy full cache line +#define TUD_DCACHE_PADDING uint8_t TU_XSTRCAT(dcache_padding_, _TU_COUNTER_)[CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1] + //--------------------------------------------------------------------+ // Includes //--------------------------------------------------------------------+ diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h index 646c22b29..9b33a6f61 100644 --- a/src/common/tusb_compiler.h +++ b/src/common/tusb_compiler.h @@ -136,7 +136,7 @@ #define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name))) #define TU_ATTR_PACKED __attribute__ ((packed)) #define TU_ATTR_WEAK __attribute__ ((weak)) - // #define TU_ATTR_WEAK_ALIAS(f) __attribute__ ((weak, alias(#f)) + // #define TU_ATTR_WEAK_ALIAS(f) __attribute__ ((weak, alias(#f))) #ifndef TU_ATTR_ALWAYS_INLINE // allow to override for debug #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline)) #endif @@ -189,6 +189,7 @@ #define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name))) #define TU_ATTR_PACKED __attribute__ ((packed)) #define TU_ATTR_WEAK __attribute__ ((weak)) + // #define TU_ATTR_WEAK_ALIAS(f) __attribute__ ((weak, alias(#f))) #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline)) #define TU_ATTR_DEPRECATED(mess) __attribute__ ((deprecated(mess))) // warn if function with this attribute is used #define TU_ATTR_UNUSED __attribute__ ((unused)) // Function/Variable is meant to be possibly unused @@ -216,6 +217,7 @@ #define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name))) #define TU_ATTR_PACKED __attribute__ ((packed)) #define TU_ATTR_WEAK __attribute__ ((weak)) + // #define TU_ATTR_WEAK_ALIAS(f) __attribute__ ((weak, alias(#f))) #ifndef TU_ATTR_ALWAYS_INLINE // allow to override for debug #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline)) #endif @@ -244,6 +246,7 @@ #define TU_ATTR_SECTION(sec_name) #define TU_ATTR_PACKED #define TU_ATTR_WEAK + // #define TU_ATTR_WEAK_ALIAS(f) #define TU_ATTR_ALWAYS_INLINE #define TU_ATTR_DEPRECATED(mess) #define TU_ATTR_UNUSED diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index b1fd357aa..59c66eb1e 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -54,6 +54,10 @@ enum { }; typedef struct { + union { + CFG_TUD_MEM_ALIGN uint8_t ep_buf[CFG_TUD_ENDPOINT0_SIZE]; + TUD_DCACHE_PADDING; + }; tusb_control_request_t request; uint8_t* buffer; uint16_t data_len; @@ -61,17 +65,14 @@ typedef struct { usbd_control_xfer_cb_t complete_cb; } usbd_control_xfer_t; -tu_static usbd_control_xfer_t _ctrl_xfer; - -CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN -tu_static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE]; +CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN static usbd_control_xfer_t _ctrl_xfer; //--------------------------------------------------------------------+ // Application API //--------------------------------------------------------------------+ // Queue ZLP status transaction -static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t const* request) { +static inline bool status_stage_xact(uint8_t rhport, tusb_control_request_t const* request) { // Opposite to endpoint in Data Phase uint8_t const ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN; return usbd_edpt_xfer(rhport, ep_addr, NULL, 0); @@ -84,13 +85,13 @@ bool tud_control_status(uint8_t rhport, tusb_control_request_t const* request) { _ctrl_xfer.total_xferred = 0; _ctrl_xfer.data_len = 0; - return _status_stage_xact(rhport, request); + return status_stage_xact(rhport, request); } // Queue a transaction in Data Stage // Each transaction has up to Endpoint0's max packet size. // This function can also transfer an zero-length packet -static bool _data_stage_xact(uint8_t rhport) { +static bool data_stage_xact(uint8_t rhport) { uint16_t const xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred, CFG_TUD_ENDPOINT0_SIZE); @@ -99,11 +100,11 @@ static bool _data_stage_xact(uint8_t rhport) { if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN) { ep_addr = EDPT_CTRL_IN; if (xact_len) { - TU_VERIFY(0 == tu_memcpy_s(_usbd_ctrl_buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len)); + TU_VERIFY(0 == tu_memcpy_s(_ctrl_xfer.ep_buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len)); } } - return usbd_edpt_xfer(rhport, ep_addr, xact_len ? _usbd_ctrl_buf : NULL, xact_len); + return usbd_edpt_xfer(rhport, ep_addr, xact_len ? _ctrl_xfer.ep_buf : NULL, xact_len); } // Transmit data to/from the control endpoint. @@ -122,10 +123,10 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const* request, voi // TU_LOG2(" Control total data length is %u bytes\r\n", _ctrl_xfer.data_len); // Data stage - TU_ASSERT(_data_stage_xact(rhport)); + TU_ASSERT(data_stage_xact(rhport)); } else { // Status stage - TU_ASSERT(_status_stage_xact(rhport, request)); + TU_ASSERT(status_stage_xact(rhport, request)); } return true; @@ -179,7 +180,7 @@ bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT) { TU_VERIFY(_ctrl_xfer.buffer); - memcpy(_ctrl_xfer.buffer, _usbd_ctrl_buf, xferred_bytes); + memcpy(_ctrl_xfer.buffer, _ctrl_xfer.ep_buf, xferred_bytes); TU_LOG_MEM(CFG_TUD_LOG_LEVEL, _usbd_ctrl_buf, xferred_bytes, 2); } @@ -205,7 +206,7 @@ bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, if (is_ok) { // Send status - TU_ASSERT(_status_stage_xact(rhport, &_ctrl_xfer.request)); + TU_ASSERT(status_stage_xact(rhport, &_ctrl_xfer.request)); } else { // Stall both IN and OUT control endpoint dcd_edpt_stall(rhport, EDPT_CTRL_OUT); @@ -213,7 +214,7 @@ bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, } } else { // More data to transfer - TU_ASSERT(_data_stage_xact(rhport)); + TU_ASSERT(data_stage_xact(rhport)); } return true; diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 363c77761..f2eb80e12 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -58,11 +58,9 @@ static xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir]) typedef struct { - CFG_TUD_MEM_ALIGN union { - uint32_t setup_packet[2]; -#if CFG_TUD_MEM_DCACHE_ENABLE - uint8_t setup_packet_cache_padding[CFG_TUD_MEM_DCACHE_LINE_SIZE]; -#endif + union { + CFG_TUD_MEM_ALIGN uint32_t setup_packet[2]; + TUD_DCACHE_PADDING; }; // EP0 transfers are limited to 1 packet - larger sizes has to be split diff --git a/src/tusb_option.h b/src/tusb_option.h index 500d74903..1c8e8aff4 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -252,11 +252,7 @@ #define CFG_TUD_DWC2_SLAVE_ENABLE 1 #endif -// DWC2 controller: use DMA for data transfer -// For processors with data cache enabled, USB endpoint buffer region -// (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable. -// For example, on Cortex-M7 the MPU region can be configured as normal -// non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0. +// Enable DWC2 DMA for device #ifndef CFG_TUD_DWC2_DMA_ENABLE #define CFG_TUD_DWC2_DMA_ENABLE 0 #endif diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json index b6c9b540a..8b4ef6d3a 100644 --- a/test/hil/tinyusb.json +++ b/test/hil/tinyusb.json @@ -3,6 +3,9 @@ { "name": "espressif_p4_function_ev", "uid": "6055F9F98715", + "build" : { + "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE"] + }, "tests": { "only": ["device/cdc_msc_freertos", "device/hid_composite_freertos", "host/device_info"], "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002427"}] -- cgit v1.3.1 From 85e54b0fc3b53e3a690698bc5cf85581e6eaa69d Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 21 Nov 2024 19:18:52 +0700 Subject: use TUD_EPBUF_DEF to declare buffer memory for midi --- src/class/midi/midi_device.c | 151 ++++++++++++++++------------------ src/common/tusb_common.h | 5 +- src/common/tusb_types.h | 10 +++ src/device/usbd_control.c | 40 ++++----- src/portable/synopsys/dwc2/dcd_dwc2.c | 31 ++++--- 5 files changed, 115 insertions(+), 122 deletions(-) (limited to 'src/device/usbd_control.c') diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c index 7e30e5ea4..5be4cb993 100644 --- a/src/class/midi/midi_device.c +++ b/src/class/midi/midi_device.c @@ -68,40 +68,36 @@ typedef struct { osal_mutex_def_t rx_ff_mutex; osal_mutex_def_t tx_ff_mutex; #endif - - // Endpoint Transfer buffer - union { - CFG_TUD_MEM_ALIGN uint8_t epout_buf[CFG_TUD_MIDI_EP_BUFSIZE]; - TUD_DCACHE_PADDING; - }; - union { - CFG_TUD_MEM_ALIGN uint8_t epin_buf[CFG_TUD_MIDI_EP_BUFSIZE]; - TUD_DCACHE_PADDING; - }; } midid_interface_t; #define ITF_MEM_RESET_SIZE offsetof(midid_interface_t, rx_ff) +// Endpoint Transfer buffer +CFG_TUD_MEM_SECTION static struct { + TUD_EPBUF_DEF(epin, CFG_TUD_MIDI_EP_BUFSIZE); + TUD_EPBUF_DEF(epout, CFG_TUD_MIDI_EP_BUFSIZE); +} _midid_epbuf[CFG_TUD_MIDI]; + //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUD_MEM_SECTION midid_interface_t _midid_itf[CFG_TUD_MIDI]; +static midid_interface_t _midid_itf[CFG_TUD_MIDI]; bool tud_midi_n_mounted (uint8_t itf) { midid_interface_t* midi = &_midid_itf[itf]; return midi->ep_in && midi->ep_out; } -static void _prep_out_transaction (midid_interface_t* p_midi) -{ - uint8_t const rhport = 0; +static void _prep_out_transaction(uint8_t idx) { + const uint8_t rhport = 0; + midid_interface_t* p_midi = &_midid_itf[idx]; uint16_t available = tu_fifo_remaining(&p_midi->rx_ff); // Prepare for incoming data but only allow what we can store in the ring buffer. // TODO Actually we can still carry out the transfer, keeping count of received bytes // and slowly move it to the FIFO when read(). // This pre-check reduces endpoint claiming - TU_VERIFY(available >= sizeof(p_midi->epout_buf), ); + TU_VERIFY(available >= sizeof(_midid_epbuf[idx].epout), ); // claim endpoint TU_VERIFY(usbd_edpt_claim(rhport, p_midi->ep_out), ); @@ -109,8 +105,8 @@ static void _prep_out_transaction (midid_interface_t* p_midi) // fifo can be changed before endpoint is claimed available = tu_fifo_remaining(&p_midi->rx_ff); - if ( available >= sizeof(p_midi->epout_buf) ) { - usbd_edpt_xfer(rhport, p_midi->ep_out, p_midi->epout_buf, sizeof(p_midi->epout_buf)); + if ( available >= CFG_TUD_MIDI_EP_BUFSIZE ) { + usbd_edpt_xfer(rhport, p_midi->ep_out, _midid_epbuf[idx].epout, CFG_TUD_MIDI_EP_BUFSIZE); }else { // Release endpoint since we don't make any transfer @@ -126,7 +122,7 @@ uint32_t tud_midi_n_available(uint8_t itf, uint8_t cable_num) (void) cable_num; midid_interface_t* midi = &_midid_itf[itf]; - midid_stream_t const* stream = &midi->stream_read; + const midid_stream_t* stream = &midi->stream_read; // when using with packet API stream total & index are both zero return tu_fifo_count(&midi->rx_ff) + (uint8_t) (stream->total - stream->index); @@ -207,8 +203,8 @@ bool tud_midi_n_packet_read (uint8_t itf, uint8_t packet[4]) midid_interface_t* midi = &_midid_itf[itf]; TU_VERIFY(midi->ep_out); - uint32_t const num_read = tu_fifo_read_n(&midi->rx_ff, packet, 4); - _prep_out_transaction(midi); + const uint32_t num_read = tu_fifo_read_n(&midi->rx_ff, packet, 4); + _prep_out_transaction(itf); return (num_read == 4); } @@ -216,31 +212,31 @@ bool tud_midi_n_packet_read (uint8_t itf, uint8_t packet[4]) // WRITE API //--------------------------------------------------------------------+ -static uint32_t write_flush(midid_interface_t* midi) -{ - // No data to send - if ( !tu_fifo_count(&midi->tx_ff) ) return 0; +static uint32_t write_flush(uint8_t idx) { + midid_interface_t* midi = &_midid_itf[idx]; - uint8_t const rhport = 0; + if (!tu_fifo_count(&midi->tx_ff)) { + return 0; // No data to send + } + + const uint8_t rhport = 0; // skip if previous transfer not complete TU_VERIFY( usbd_edpt_claim(rhport, midi->ep_in), 0 ); - uint16_t count = tu_fifo_read_n(&midi->tx_ff, midi->epin_buf, CFG_TUD_MIDI_EP_BUFSIZE); + uint16_t count = tu_fifo_read_n(&midi->tx_ff, _midid_epbuf[idx].epin, CFG_TUD_MIDI_EP_BUFSIZE); - if (count) - { - TU_ASSERT( usbd_edpt_xfer(rhport, midi->ep_in, midi->epin_buf, count), 0 ); + if (count) { + TU_ASSERT( usbd_edpt_xfer(rhport, midi->ep_in, _midid_epbuf[idx].epin, count), 0 ); return count; - }else - { + }else { // Release endpoint since we don't make any transfer usbd_edpt_release(rhport, midi->ep_in); return 0; } } -uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize) +uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, const uint8_t* buffer, uint32_t bufsize) { midid_interface_t* midi = &_midid_itf[itf]; TU_VERIFY(midi->ep_in, 0); @@ -250,14 +246,13 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const* uint32_t i = 0; while ( (i < bufsize) && (tu_fifo_remaining(&midi->tx_ff) >= 4) ) { - uint8_t const data = buffer[i]; + const uint8_t data = buffer[i]; i++; if ( stream->index == 0 ) { //------------- New event packet -------------// - - uint8_t const msg = data >> 4; + const uint8_t msg = data >> 4; stream->index = 2; stream->buffer[1] = data; @@ -342,9 +337,11 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const* if ( stream->index == stream->total ) { // zeroes unused bytes - for(uint8_t idx = stream->total; idx < 4; idx++) stream->buffer[idx] = 0; + for (uint8_t idx = stream->total; idx < 4; idx++) { + stream->buffer[idx] = 0; + } - uint16_t const count = tu_fifo_write_n(&midi->tx_ff, stream->buffer, 4); + const uint16_t count = tu_fifo_write_n(&midi->tx_ff, stream->buffer, 4); // complete current event packet, reset stream stream->index = stream->total = 0; @@ -354,20 +351,21 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const* } } - write_flush(midi); + write_flush(itf); return i; } -bool tud_midi_n_packet_write (uint8_t itf, uint8_t const packet[4]) -{ +bool tud_midi_n_packet_write (uint8_t itf, const uint8_t packet[4]) { midid_interface_t* midi = &_midid_itf[itf]; TU_VERIFY(midi->ep_in); - if (tu_fifo_remaining(&midi->tx_ff) < 4) return false; + if (tu_fifo_remaining(&midi->tx_ff) < 4) { + return false; + } tu_fifo_write_n(&midi->tx_ff, packet, 4); - write_flush(midi); + write_flush(itf); return true; } @@ -431,7 +429,7 @@ void midid_reset(uint8_t rhport) } } -uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint16_t max_len) +uint16_t midid_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uint16_t max_len) { // 1st Interface is Audio Control v1 TU_VERIFY(TUSB_CLASS_AUDIO == desc_itf->bInterfaceClass && @@ -439,7 +437,7 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol, 0); uint16_t drv_len = tu_desc_len(desc_itf); - uint8_t const * p_desc = tu_desc_next(desc_itf); + const uint8_t* p_desc = tu_desc_next(desc_itf); // Skip Class Specific descriptors while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len ) @@ -450,7 +448,7 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint // 2nd Interface is MIDI Streaming TU_VERIFY(TUSB_DESC_INTERFACE == tu_desc_type(p_desc), 0); - tusb_desc_interface_t const * desc_midi = (tusb_desc_interface_t const *) p_desc; + const tusb_desc_interface_t* desc_midi = (const tusb_desc_interface_t*) p_desc; TU_VERIFY(TUSB_CLASS_AUDIO == desc_midi->bInterfaceClass && AUDIO_SUBCLASS_MIDI_STREAMING == desc_midi->bInterfaceSubClass && @@ -458,11 +456,10 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint // Find available interface midid_interface_t * p_midi = NULL; - for(uint8_t i=0; ibEndpointAddress; + TU_ASSERT(usbd_edpt_open(rhport, (const tusb_desc_endpoint_t*) p_desc), 0); + uint8_t ep_addr = ((const tusb_desc_endpoint_t*) p_desc)->bEndpointAddress; if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) { @@ -503,7 +500,7 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint } // Prepare for incoming data - _prep_out_transaction(p_midi); + _prep_out_transaction(idx); return drv_len; } @@ -511,14 +508,9 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint // Invoked when a control transfer occurred on an interface of this class // Driver response accordingly to the request and the transfer stage (setup/data/ack) // return false to stall control endpoint (e.g unsupported request) -bool midid_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) -{ - (void) rhport; - (void) stage; - (void) request; - - // driver doesn't support any request yet - return false; +bool midid_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control_request_t* request) { + (void) rhport; (void) stage; (void) request; + return false; // driver doesn't support any request yet } bool midid_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) @@ -526,40 +518,37 @@ bool midid_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32 (void) result; (void) rhport; - uint8_t itf; + uint8_t idx; midid_interface_t* p_midi; // Identify which interface to use - for (itf = 0; itf < CFG_TUD_MIDI; itf++) - { - p_midi = &_midid_itf[itf]; - if ( ( ep_addr == p_midi->ep_out ) || ( ep_addr == p_midi->ep_in ) ) break; + for (idx = 0; idx < CFG_TUD_MIDI; idx++) { + p_midi = &_midid_itf[idx]; + if ((ep_addr == p_midi->ep_out) || (ep_addr == p_midi->ep_in)) { + break; + } } - TU_ASSERT(itf < CFG_TUD_MIDI); + TU_ASSERT(idx < CFG_TUD_MIDI); // receive new data - if ( ep_addr == p_midi->ep_out ) - { - tu_fifo_write_n(&p_midi->rx_ff, p_midi->epout_buf, (uint16_t) xferred_bytes); + if (ep_addr == p_midi->ep_out) { + tu_fifo_write_n(&p_midi->rx_ff, _midid_epbuf[idx].epout, (uint16_t)xferred_bytes); // invoke receive callback if available - if (tud_midi_rx_cb) tud_midi_rx_cb(itf); + if (tud_midi_rx_cb) { + tud_midi_rx_cb(idx); + } // prepare for next // TODO for now ep_out is not used by public API therefore there is no race condition, // and does not need to claim like ep_in - _prep_out_transaction(p_midi); - } - else if ( ep_addr == p_midi->ep_in ) - { - if (0 == write_flush(p_midi)) - { + _prep_out_transaction(idx); + } else if (ep_addr == p_midi->ep_in) { + if (0 == write_flush(idx)) { // If there is no data left, a ZLP should be sent if // xferred_bytes is multiple of EP size and not zero - if ( !tu_fifo_count(&p_midi->tx_ff) && xferred_bytes && (0 == (xferred_bytes % CFG_TUD_MIDI_EP_BUFSIZE)) ) - { - if ( usbd_edpt_claim(rhport, p_midi->ep_in) ) - { + if (!tu_fifo_count(&p_midi->tx_ff) && xferred_bytes && (0 == (xferred_bytes % CFG_TUD_MIDI_EP_BUFSIZE))) { + if (usbd_edpt_claim(rhport, p_midi->ep_in)) { usbd_edpt_xfer(rhport, p_midi->ep_in, NULL, 0); } } diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 416bad296..d05032d00 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -58,9 +58,6 @@ // Generate a mask with bit from high (31) to low (0) set, e.g TU_GENMASK(3, 0) = 0b1111 #define TU_GENMASK(h, l) ( (UINT32_MAX << (l)) & (UINT32_MAX >> (31 - (h))) ) -// DCache padding for variable to occupy full cache line -#define TUD_DCACHE_PADDING uint8_t TU_XSTRCAT(dcache_padding_, _TU_COUNTER_)[CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1] - //--------------------------------------------------------------------+ // Includes //--------------------------------------------------------------------+ @@ -179,7 +176,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool tu_is_aligned32(uint32_t value) { retur TU_ATTR_ALWAYS_INLINE static inline bool tu_is_aligned64(uint64_t value) { return (value & 0x3FUL) == 0; } //------------- Mathematics -------------// -TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_div_ceil(uint32_t v, uint32_t d) { return (v + d -1)/d; } +TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_div_ceil(uint32_t v, uint32_t d) { return TU_DIV_CEIL(v, d); } // log2 of a value is its MSB's position // TODO use clz TODO remove diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index d045a3c8f..d0a5c866f 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -35,6 +35,16 @@ extern "C" { #endif +// DCache padding for variable to occupy full cache line +#define TUD_DCACHE_PADDING uint8_t TU_XSTRCAT(dcache_padding_, _TU_COUNTER_)[CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1] + +#define TUD_EPBUF_DEF(_name, _size) \ + union { \ + CFG_TUD_MEM_ALIGN uint8_t _name[_size]; \ + uint8_t _name##_dcache_padding[CFG_TUD_MEM_DCACHE_ENABLE ? (TU_DIV_CEIL(_size, CFG_TUD_MEM_DCACHE_LINE_SIZE) * CFG_TUD_MEM_DCACHE_LINE_SIZE) : 1]; \ + }; + + /*------------------------------------------------------------------*/ /* CONSTANTS *------------------------------------------------------------------*/ diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index 59c66eb1e..80a2a2cc1 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -35,7 +35,7 @@ //--------------------------------------------------------------------+ // Callback weak stubs (called if application does not provide) //--------------------------------------------------------------------+ -TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const* request) { +TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, const tusb_control_request_t* request) { (void) rhport; (void) request; } @@ -54,10 +54,6 @@ enum { }; typedef struct { - union { - CFG_TUD_MEM_ALIGN uint8_t ep_buf[CFG_TUD_ENDPOINT0_SIZE]; - TUD_DCACHE_PADDING; - }; tusb_control_request_t request; uint8_t* buffer; uint16_t data_len; @@ -65,21 +61,25 @@ typedef struct { usbd_control_xfer_cb_t complete_cb; } usbd_control_xfer_t; -CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN static usbd_control_xfer_t _ctrl_xfer; +static usbd_control_xfer_t _ctrl_xfer; + +CFG_TUD_MEM_SECTION static struct { + TUD_EPBUF_DEF(buf, CFG_TUD_ENDPOINT0_SIZE); +} _ctrl_epbuf; //--------------------------------------------------------------------+ // Application API //--------------------------------------------------------------------+ // Queue ZLP status transaction -static inline bool status_stage_xact(uint8_t rhport, tusb_control_request_t const* request) { +static inline bool status_stage_xact(uint8_t rhport, const tusb_control_request_t* request) { // Opposite to endpoint in Data Phase - uint8_t const ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN; + const uint8_t ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN; return usbd_edpt_xfer(rhport, ep_addr, NULL, 0); } // Status phase -bool tud_control_status(uint8_t rhport, tusb_control_request_t const* request) { +bool tud_control_status(uint8_t rhport, const tusb_control_request_t* request) { _ctrl_xfer.request = (*request); _ctrl_xfer.buffer = NULL; _ctrl_xfer.total_xferred = 0; @@ -92,24 +92,22 @@ bool tud_control_status(uint8_t rhport, tusb_control_request_t const* request) { // Each transaction has up to Endpoint0's max packet size. // This function can also transfer an zero-length packet static bool data_stage_xact(uint8_t rhport) { - uint16_t const xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred, - CFG_TUD_ENDPOINT0_SIZE); - + const uint16_t xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred, CFG_TUD_ENDPOINT0_SIZE); uint8_t ep_addr = EDPT_CTRL_OUT; if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN) { ep_addr = EDPT_CTRL_IN; if (xact_len) { - TU_VERIFY(0 == tu_memcpy_s(_ctrl_xfer.ep_buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len)); + TU_VERIFY(0 == tu_memcpy_s(_ctrl_epbuf.buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len)); } } - return usbd_edpt_xfer(rhport, ep_addr, xact_len ? _ctrl_xfer.ep_buf : NULL, xact_len); + return usbd_edpt_xfer(rhport, ep_addr, xact_len ? _ctrl_epbuf.buf : NULL, xact_len); } // Transmit data to/from the control endpoint. // If the request's wLength is zero, a status packet is sent instead. -bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const* request, void* buffer, uint16_t len) { +bool tud_control_xfer(uint8_t rhport, const tusb_control_request_t* request, void* buffer, uint16_t len) { _ctrl_xfer.request = (*request); _ctrl_xfer.buffer = (uint8_t*) buffer; _ctrl_xfer.total_xferred = 0U; @@ -119,13 +117,8 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const* request, voi if (_ctrl_xfer.data_len > 0U) { TU_ASSERT(buffer); } - -// TU_LOG2(" Control total data length is %u bytes\r\n", _ctrl_xfer.data_len); - - // Data stage TU_ASSERT(data_stage_xact(rhport)); } else { - // Status stage TU_ASSERT(status_stage_xact(rhport, request)); } @@ -136,7 +129,7 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const* request, voi // USBD API //--------------------------------------------------------------------+ void usbd_control_reset(void); -void usbd_control_set_request(tusb_control_request_t const* request); +void usbd_control_set_request(const tusb_control_request_t* request); void usbd_control_set_complete_callback(usbd_control_xfer_cb_t fp); bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); @@ -150,7 +143,7 @@ void usbd_control_set_complete_callback(usbd_control_xfer_cb_t fp) { } // for dcd_set_address where DCD is responsible for status response -void usbd_control_set_request(tusb_control_request_t const* request) { +void usbd_control_set_request(const tusb_control_request_t* request) { _ctrl_xfer.request = (*request); _ctrl_xfer.buffer = NULL; _ctrl_xfer.total_xferred = 0; @@ -180,7 +173,7 @@ bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT) { TU_VERIFY(_ctrl_xfer.buffer); - memcpy(_ctrl_xfer.buffer, _ctrl_xfer.ep_buf, xferred_bytes); + memcpy(_ctrl_xfer.buffer, _ctrl_epbuf.buf, xferred_bytes); TU_LOG_MEM(CFG_TUD_LOG_LEVEL, _usbd_ctrl_buf, xferred_bytes, 2); } @@ -205,7 +198,6 @@ bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, } if (is_ok) { - // Send status TU_ASSERT(status_stage_xact(rhport, &_ctrl_xfer.request)); } else { // Stall both IN and OUT control endpoint diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index f2eb80e12..6c7b94778 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -31,6 +31,10 @@ #if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2) +#if !CFG_TUD_DWC2_SLAVE_ENABLE && !CFG_TUH_DWC2_DMA_ENABLE +#error DWC2 require either CFG_TUD_DWC2_SLAVE_ENABLE or CFG_TUH_DWC2_DMA_ENABLE to be enabled +#endif + // Debug level for DWC2 #define DWC2_DEBUG 2 @@ -58,11 +62,6 @@ static xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir]) typedef struct { - union { - CFG_TUD_MEM_ALIGN uint32_t setup_packet[2]; - TUD_DCACHE_PADDING; - }; - // EP0 transfers are limited to 1 packet - larger sizes has to be split uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type uint16_t dfifo_top; // top free location in DFIFO in words @@ -74,7 +73,11 @@ typedef struct { bool sof_en; } dcd_data_t; -CFG_TUD_MEM_SECTION static dcd_data_t _dcd_data; +static dcd_data_t _dcd_data; + +CFG_TUD_MEM_SECTION static struct { + TUD_EPBUF_DEF(setup_packet, 8); +} _dcd_usbbuf; //-------------------------------------------------------------------- // DMA @@ -116,7 +119,7 @@ static void dma_setup_prepare(uint8_t rhport) { // Receive only 1 packet dwc2->epout[0].doeptsiz = (1 << DOEPTSIZ_STUPCNT_Pos) | (1 << DOEPTSIZ_PKTCNT_Pos) | (8 << DOEPTSIZ_XFRSIZ_Pos); - dwc2->epout[0].doepdma = (uintptr_t) _dcd_data.setup_packet; + dwc2->epout[0].doepdma = (uintptr_t) _dcd_usbbuf.setup_packet; dwc2->epout[0].doepctl |= DOEPCTL_EPENA | DOEPCTL_USBAEP; } @@ -751,12 +754,14 @@ static void handle_rxflvl_irq(uint8_t rhport) { // Global OUT NAK: do nothing break; - case GRXSTS_PKTSTS_SETUP_RX: + case GRXSTS_PKTSTS_SETUP_RX: { // Setup packet received + uint32_t* setup = (uint32_t*)(uintptr_t) _dcd_usbbuf.setup_packet; // We can receive up to three setup packets in succession, but only the last one is valid. - _dcd_data.setup_packet[0] = (*rx_fifo); - _dcd_data.setup_packet[1] = (*rx_fifo); + setup[0] = (*rx_fifo); + setup[1] = (*rx_fifo); break; + } case GRXSTS_PKTSTS_SETUP_DONE: // Setup packet done: @@ -802,7 +807,7 @@ static void handle_rxflvl_irq(uint8_t rhport) { static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) { if (doepint_bm.setup_phase_done) { - dcd_event_setup_received(rhport, (uint8_t*) _dcd_data.setup_packet, true); + dcd_event_setup_received(rhport, _dcd_usbbuf.setup_packet, true); return; } @@ -878,8 +883,8 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi if (doepint_bm.setup_phase_done) { dma_setup_prepare(rhport); - dcd_dcache_invalidate(_dcd_data.setup_packet, 8); - dcd_event_setup_received(rhport, (uint8_t*) _dcd_data.setup_packet, true); + dcd_dcache_invalidate(_dcd_usbbuf.setup_packet, 8); + dcd_event_setup_received(rhport, _dcd_usbbuf.setup_packet, true); return; } -- cgit v1.3.1 From ecc65a86c871972766f460e8f2ce0f436ae2391b Mon Sep 17 00:00:00 2001 From: Roman Leonov Date: Thu, 28 Nov 2024 11:57:38 +0100 Subject: refactor(usbd_control): Updated the buffer name for deeper debug --- src/device/usbd_control.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/device/usbd_control.c') diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index 80a2a2cc1..d964a75d0 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -174,7 +174,7 @@ bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT) { TU_VERIFY(_ctrl_xfer.buffer); memcpy(_ctrl_xfer.buffer, _ctrl_epbuf.buf, xferred_bytes); - TU_LOG_MEM(CFG_TUD_LOG_LEVEL, _usbd_ctrl_buf, xferred_bytes, 2); + TU_LOG_MEM(CFG_TUD_LOG_LEVEL, _ctrl_xfer.buffer, xferred_bytes, 2); } _ctrl_xfer.total_xferred += (uint16_t) xferred_bytes; -- cgit v1.3.1 From ad0ac6780daf57e8aa8c27fb86b421bf0a9d20b4 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 13 Dec 2024 17:28:50 +0700 Subject: change OPT_MCU_RAXXX, fix missing prototype warnings. --- .idea/cmake.xml | 5 +++-- src/device/usbd_control.c | 4 ---- src/device/usbd_pvt.h | 5 +++++ src/tusb_option.h | 2 +- 4 files changed, 9 insertions(+), 7 deletions(-) (limited to 'src/device/usbd_control.c') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 9399a121a..e4c189251 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -121,8 +121,9 @@ - - + + + diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index d964a75d0..c9700fd9d 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -44,10 +44,6 @@ TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, const tusb_control_r // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ -#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL -extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback); -#endif - enum { EDPT_CTRL_OUT = 0x00, EDPT_CTRL_IN = 0x80 diff --git a/src/device/usbd_pvt.h b/src/device/usbd_pvt.h index 90f37db3e..190d6fd7f 100644 --- a/src/device/usbd_pvt.h +++ b/src/device/usbd_pvt.h @@ -127,6 +127,11 @@ void usbd_sof_enable(uint8_t rhport, sof_consumer_t consumer, bool en); bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const* p_desc, uint8_t ep_count, uint8_t xfer_type, uint8_t* ep_out, uint8_t* ep_in); void usbd_defer_func(osal_task_func_t func, void *param, bool in_isr); + +#if CFG_TUSB_DEBUG >= CFG_TUD_LOG_LEVEL +void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback); +#endif + #ifdef __cplusplus } #endif diff --git a/src/tusb_option.h b/src/tusb_option.h index dca1e4109..8b1a6af01 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -152,7 +152,7 @@ #define OPT_MCU_RX63X 1400 ///< Renesas RX63N/631 #define OPT_MCU_RX65X 1401 ///< Renesas RX65N/RX651 #define OPT_MCU_RX72N 1402 ///< Renesas RX72N -#define OPT_MCU_RAXXX 1403 ///< Renesas RAxxx families +#define OPT_MCU_RAXXX 1420 ///< Renesas RA generic // Mind Motion #define OPT_MCU_MM32F327X 1500 ///< Mind Motion MM32F327 -- cgit v1.3.1