From cde722385c579fc388fcf78ddb57fad22a643ba5 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 5 Apr 2024 22:19:45 +0200 Subject: dwc2: add dma support. --- src/portable/synopsys/dwc2/dcd_dwc2.c | 154 +++++++++++++++++++++++++++------- 1 file changed, 124 insertions(+), 30 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 692096fc8..2e679d1f3 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -67,6 +67,11 @@ // Debug level for DWC2 #define DWC2_DEBUG 2 +// DMA switch +#ifndef DWC2_ENABLE_DMA +#define DWC2_ENABLE_DMA 1 +#endif + #ifndef dcache_clean #define dcache_clean(_addr, _size) #endif @@ -186,6 +191,32 @@ static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { return true; } +static bool dma_supported(uint8_t rhport) +{ + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + // Internal DMA only + return (dwc2->ghwcfg2_bm.arch == 2) && DWC2_ENABLE_DMA; +} + +static void dma_stpkt_rx(uint8_t rhport) +{ + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + + if (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a) { + if(dwc2->epout[0].doepctl & DOEPCTL_EPENA) + return; + } + + // Receive only 1 packet + dwc2->epout[0].doeptsiz = 0; + dwc2->epout[0].doeptsiz |= (1 << DOEPTSIZ_STUPCNT_Pos); + dwc2->epout[0].doeptsiz |= 8; + dwc2->epout[0].doeptsiz |= (1 << DOEPTSIZ_PKTCNT_Pos); + dwc2->epout[0].doepdma = (uintptr_t)_setup_packet; + + dwc2->epout[0].doepctl |= DOEPCTL_EPENA | DOEPCTL_USBAEP; +} + static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); @@ -351,6 +382,11 @@ static void bus_reset(uint8_t rhport) { // Setup the control endpoint 0 _allocated_fifo_words_tx = 16; + // DMA needs extra space for processing, needs size confirmation + if(dma_supported(rhport)) { + _allocated_fifo_words_tx += 72; + } + // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) dwc2->dieptxf0 = (16 << DIEPTXF0_TX0FD_Pos) | (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx); @@ -361,6 +397,10 @@ static void bus_reset(uint8_t rhport) { dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); + if(dma_supported(rhport)) { + dma_stpkt_rx(rhport); + } + dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT; } @@ -369,11 +409,11 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c (void) rhport; dwc2_regs_t* dwc2 = DWC2_REG(rhport); + xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir); // EP0 is limited to one packet each xfer // We use multiple transaction of xfer->max_size length to get a whole transfer done if (epnum == 0) { - xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir); total_bytes = tu_min16(ep0_pending[dir], xfer->max_size); ep0_pending[dir] -= total_bytes; } @@ -386,17 +426,31 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); - epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; + if(dma_supported(rhport)) { + epin[epnum].diepdma = (uintptr_t)xfer->buffer; - // For ISO endpoint set correct odd/even bit for next frame. - if ((epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { - // Take odd/even bit from frame counter. - uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); - epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); - } - // Enable fifo empty interrupt only if there are something to put in the fifo. - if (total_bytes != 0) { - dwc2->diepempmsk |= (1 << epnum); + // For ISO endpoint set correct odd/even bit for next frame. + if ((epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { + // Take odd/even bit from frame counter. + uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); + epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); + } + + epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; + } else { + + epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; + + // For ISO endpoint set correct odd/even bit for next frame. + if ((epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { + // Take odd/even bit from frame counter. + uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); + epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); + } + // Enable fifo empty interrupt only if there are something to put in the fifo. + if (total_bytes != 0) { + dwc2->diepempmsk |= (1 << epnum); + } } } else { dwc2_epout_t* epout = dwc2->epout; @@ -406,13 +460,18 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c epout[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) | ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk); - epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK; if ((epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && XFER_CTL_BASE(epnum, dir)->interval == 1) { // Take odd/even bit from frame counter. uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); } + + if(dma_supported(rhport)) { + epout[epnum].doepdma = (uintptr_t)xfer->buffer; + } + + epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK; } } @@ -619,6 +678,11 @@ void dcd_init(uint8_t rhport) { // Enable global interrupt dwc2->gahbcfg |= GAHBCFG_GINT; + if (dma_supported(rhport)) { + dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2; + dwc2->gintmsk &=~GINTMSK_RXFLVLM; + } + // make sure we are in device mode // TU_ASSERT(!(dwc2->gintsts & GINTSTS_CMOD), ); @@ -728,6 +792,11 @@ void dcd_edpt_close_all(uint8_t rhport) { // reset allocated fifo IN _allocated_fifo_words_tx = 16; + // DMA needs extra space for processing, needs size confirmation + if(dma_supported(rhport)) { + _allocated_fifo_words_tx += 72; + } + fifo_flush_tx(dwc2, 0x10); // all tx fifo fifo_flush_rx(dwc2); } @@ -809,6 +878,9 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { edpt_disable(rhport, ep_addr, true); + if((tu_edpt_number(ep_addr) == 0) && dma_supported(rhport)) { + dma_stpkt_rx(rhport); + } } void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { @@ -991,32 +1063,51 @@ static void handle_epout_irq(uint8_t rhport) { uint32_t const doepint = epout->doepint; - // SETUP packet Setup Phase done. - if (doepint & DOEPINT_STUP) { - uint32_t clear_flag = DOEPINT_STUP; - - // STPKTRX is only available for version from 3_00a - if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) { - clear_flag |= DOEPINT_STPKTRX; - } - - epout->doepint = clear_flag; - dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); - } - // OUT XFER complete if (epout->doepint & DOEPINT_XFRC) { epout->doepint = DOEPINT_XFRC; xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); - // EP0 can only handle one packet - if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) { - // Schedule another packet to be received. - edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + if (doepint & DOEPINT_STUP) { + // STPKTRX is only available for version from 3_00a + if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) { + epout->doepint = DOEPINT_STPKTRX; + } + } else if (doepint & DOEPINT_OTEPSPR) { + epout->doepint = DOEPINT_OTEPSPR; } else { - dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); + // EP0 can only handle one packet + if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) { + // Schedule another packet to be received. + edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + } else { + if(dma_supported(rhport)) { + // Fix packet length + uint16_t remain = (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; + xfer->total_len -= remain; + // this is ZLP, so prepare EP0 for next setup + if(n == 0 && xfer->total_len == 0) { + dma_stpkt_rx(rhport); + } + } + + dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); + } + } + } + + // SETUP packet Setup Phase done. + if (doepint & DOEPINT_STUP) { + epout->doepint = DOEPINT_STUP; + if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) { + epout->doepint = DOEPINT_STPKTRX; + } + if(dma_supported(rhport) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) { + dma_stpkt_rx(rhport); } + + dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); } } } @@ -1042,6 +1133,9 @@ static void handle_epin_irq(uint8_t rhport) { // Schedule another packet to be transmitted. edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); } else { + if((n == 0) && dma_supported(rhport)) { + dma_stpkt_rx(rhport); + } dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); } } -- cgit v1.3.1 From 394dc0686a5c26bd3375ce9aba12b82fa18ba42f Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Thu, 25 Apr 2024 22:09:59 +0200 Subject: Check IN ep count limit. --- src/portable/synopsys/dwc2/dcd_dwc2.c | 13 +++++++++++++ src/portable/synopsys/dwc2/dwc2_esp32.h | 5 +++-- src/portable/synopsys/dwc2/dwc2_type.h | 1 + 3 files changed, 17 insertions(+), 2 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 2e679d1f3..cdf6c2a68 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -103,6 +103,9 @@ static uint16_t ep0_pending[2]; // Index determines direction as t // TX FIFO RAM allocation so far in words - RX FIFO size is readily available from dwc2->grxfsiz static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs) +// Number of IN endpoints active +static uint8_t _allocated_ep_in_count; + // SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by static bool _sof_en; @@ -170,6 +173,12 @@ static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { dwc2->grxfsiz = sz; } } else { + // Check IN endpoints concurrently active limit + if(_dwc2_controller->ep_in_count) { + TU_ASSERT(_allocated_ep_in_count < _dwc2_controller->ep_in_count); + _allocated_ep_in_count++; + } + // Note if The TXFELVL is configured as half empty. In order // to be able to write a packet at that point, the fifo must be twice the max_size. if ((dwc2->gahbcfg & GAHBCFG_TXFELVL) == 0) { @@ -303,6 +312,8 @@ static void bus_reset(uint8_t rhport) { _sof_en = false; + _allocated_ep_in_count = 1; + // clear device address dwc2->dcfg &= ~DCFG_DAD_Msk; @@ -770,6 +781,8 @@ void dcd_edpt_close_all(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const ep_count = _dwc2_controller[rhport].ep_count; + _allocated_ep_in_count = 1; + // Disable non-control interrupt dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index c50dd66b8..fc12d7551 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -37,11 +37,12 @@ //#include "soc/usb_periph.h" #define DWC2_REG_BASE 0x60080000UL -#define DWC2_EP_MAX 6 // USB_OUT_EP_NUM. TODO ESP32Sx only has 5 tx fifo (5 endpoint IN) +#define DWC2_EP_MAX 7 +#define DWC2_EP_IN_MAX 5 static const dwc2_controller_t _dwc2_controller[] = { - { .reg_base = DWC2_REG_BASE, .irqnum = 0, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 1024 } + { .reg_base = DWC2_REG_BASE, .irqnum = 0, .ep_count = DWC2_EP_MAX, .ep_in_count = DWC2_EP_IN_MAX, .ep_fifo_size = 1024 } }; static intr_handle_t usb_ih; diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index c15771237..5db453561 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -29,6 +29,7 @@ typedef struct uintptr_t reg_base; uint32_t irqnum; uint8_t ep_count; + uint8_t ep_in_count; uint32_t ep_fifo_size; }dwc2_controller_t; -- cgit v1.3.1 From 298f7f2d818d117785af9f79da79fbdb85120cd2 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Thu, 25 Apr 2024 22:11:49 +0200 Subject: Fix DMA FIFO reservation. --- src/portable/synopsys/dwc2/dcd_dwc2.c | 16 +++++++++------- src/portable/synopsys/dwc2/dwc2_bcm.h | 2 +- src/portable/synopsys/dwc2/dwc2_type.h | 6 +++--- 3 files changed, 13 insertions(+), 11 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index cdf6c2a68..1057ee925 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -393,9 +393,10 @@ static void bus_reset(uint8_t rhport) { // Setup the control endpoint 0 _allocated_fifo_words_tx = 16; - // DMA needs extra space for processing, needs size confirmation + // DMA needs extra space for processing if(dma_supported(rhport)) { - _allocated_fifo_words_tx += 72; + uint16_t reserved = _dwc2_controller[rhport].ep_fifo_size / 4- dwc2->ghwcfg3_bm.total_fifo_size; + _allocated_fifo_words_tx += reserved; } // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) @@ -805,13 +806,14 @@ void dcd_edpt_close_all(uint8_t rhport) { // reset allocated fifo IN _allocated_fifo_words_tx = 16; - // DMA needs extra space for processing, needs size confirmation - if(dma_supported(rhport)) { - _allocated_fifo_words_tx += 72; - } - fifo_flush_tx(dwc2, 0x10); // all tx fifo fifo_flush_rx(dwc2); + + // DMA needs extra space for processing + if(dma_supported(rhport)) { + uint16_t reserved = _dwc2_controller[rhport].ep_fifo_size / 4- dwc2->ghwcfg3_bm.total_fifo_size; + _allocated_fifo_words_tx += reserved; + } } bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { diff --git a/src/portable/synopsys/dwc2/dwc2_bcm.h b/src/portable/synopsys/dwc2/dwc2_bcm.h index 732d96ae0..e5824606a 100644 --- a/src/portable/synopsys/dwc2/dwc2_bcm.h +++ b/src/portable/synopsys/dwc2/dwc2_bcm.h @@ -39,7 +39,7 @@ static const dwc2_controller_t _dwc2_controller[] = { - { .reg_base = USB_OTG_GLOBAL_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 4096 } + { .reg_base = USB_OTG_GLOBAL_BASE, .irqnum = USB_IRQn, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 16384 } }; #define dcache_clean(_addr, _size) data_clean(_addr, _size) diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 5db453561..08c9b8b1b 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -214,15 +214,15 @@ union { volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep) union { volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2 - dwc2_ghwcfg2_t ghwcfg2_bm; + volatile dwc2_ghwcfg2_t ghwcfg2_bm; }; union { volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3 - dwc2_ghwcfg3_t ghwcfg3_bm; + volatile dwc2_ghwcfg3_t ghwcfg3_bm; }; union { volatile uint32_t ghwcfg4; // 050 User Hardware Configuration4 - dwc2_ghwcfg4_t ghwcfg4_bm; + volatile dwc2_ghwcfg4_t ghwcfg4_bm; }; volatile uint32_t glpmcfg; // 054 Core LPM Configuration volatile uint32_t gpwrdn; // 058 Power Down -- cgit v1.3.1 From 87655682822690de87ade34ceca7c21ca65dd000 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Thu, 25 Apr 2024 22:39:19 +0200 Subject: Change DMA condition. --- src/class/audio/audio_device.c | 4 ++- src/portable/synopsys/dwc2/dcd_dwc2.c | 47 ++++++++++++++--------------------- 2 files changed, 21 insertions(+), 30 deletions(-) (limited to 'src/portable') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 9ba38a20c..b7af0259a 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -65,8 +65,10 @@ //--------------------------------------------------------------------+ // Use ring buffer if it's available, some MCUs need extra RAM requirements +// For DWC2 enable ring buffer will disable DMA (if available) #ifndef TUD_AUDIO_PREFER_RING_BUFFER - #if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX + #if CFG_TUSB_MCU == OPT_MCU_LPC43XX || CFG_TUSB_MCU == OPT_MCU_LPC18XX || CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX || \ + defined(TUP_USBIP_DWC2) #define TUD_AUDIO_PREFER_RING_BUFFER 0 #else #define TUD_AUDIO_PREFER_RING_BUFFER 1 diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 1057ee925..c4b1956ce 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -67,23 +67,6 @@ // Debug level for DWC2 #define DWC2_DEBUG 2 -// DMA switch -#ifndef DWC2_ENABLE_DMA -#define DWC2_ENABLE_DMA 1 -#endif - -#ifndef dcache_clean -#define dcache_clean(_addr, _size) -#endif - -#ifndef dcache_invalidate -#define dcache_invalidate(_addr, _size) -#endif - -#ifndef dcache_clean_invalidate -#define dcache_clean_invalidate(_addr, _size) -#endif - static TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2]; typedef struct { @@ -200,11 +183,17 @@ static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { return true; } -static bool dma_supported(uint8_t rhport) +static inline bool dma_enabled(uint8_t rhport) { + // DMA doesn't support fifo transfer +#ifdef TUD_AUDIO_PREFER_RING_BUFFER +#if TUD_AUDIO_PREFER_RING_BUFFER + return false; +#endif +#endif dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Internal DMA only - return (dwc2->ghwcfg2_bm.arch == 2) && DWC2_ENABLE_DMA; + return (dwc2->ghwcfg2_bm.arch == 2); } static void dma_stpkt_rx(uint8_t rhport) @@ -394,7 +383,7 @@ static void bus_reset(uint8_t rhport) { _allocated_fifo_words_tx = 16; // DMA needs extra space for processing - if(dma_supported(rhport)) { + if(dma_enabled(rhport)) { uint16_t reserved = _dwc2_controller[rhport].ep_fifo_size / 4- dwc2->ghwcfg3_bm.total_fifo_size; _allocated_fifo_words_tx += reserved; } @@ -409,7 +398,7 @@ static void bus_reset(uint8_t rhport) { dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); - if(dma_supported(rhport)) { + if(dma_enabled(rhport)) { dma_stpkt_rx(rhport); } @@ -438,7 +427,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); - if(dma_supported(rhport)) { + if(dma_enabled(rhport)) { epin[epnum].diepdma = (uintptr_t)xfer->buffer; // For ISO endpoint set correct odd/even bit for next frame. @@ -479,7 +468,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); } - if(dma_supported(rhport)) { + if(dma_enabled(rhport)) { epout[epnum].doepdma = (uintptr_t)xfer->buffer; } @@ -690,7 +679,7 @@ void dcd_init(uint8_t rhport) { // Enable global interrupt dwc2->gahbcfg |= GAHBCFG_GINT; - if (dma_supported(rhport)) { + if (dma_enabled(rhport)) { dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2; dwc2->gintmsk &=~GINTMSK_RXFLVLM; } @@ -810,7 +799,7 @@ void dcd_edpt_close_all(uint8_t rhport) { fifo_flush_rx(dwc2); // DMA needs extra space for processing - if(dma_supported(rhport)) { + if(dma_enabled(rhport)) { uint16_t reserved = _dwc2_controller[rhport].ep_fifo_size / 4- dwc2->ghwcfg3_bm.total_fifo_size; _allocated_fifo_words_tx += reserved; } @@ -893,7 +882,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { edpt_disable(rhport, ep_addr, true); - if((tu_edpt_number(ep_addr) == 0) && dma_supported(rhport)) { + if((tu_edpt_number(ep_addr) == 0) && dma_enabled(rhport)) { dma_stpkt_rx(rhport); } } @@ -1097,7 +1086,7 @@ static void handle_epout_irq(uint8_t rhport) { // Schedule another packet to be received. edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); } else { - if(dma_supported(rhport)) { + if(dma_enabled(rhport)) { // Fix packet length uint16_t remain = (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; xfer->total_len -= remain; @@ -1118,7 +1107,7 @@ static void handle_epout_irq(uint8_t rhport) { if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) { epout->doepint = DOEPINT_STPKTRX; } - if(dma_supported(rhport) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) { + if(dma_enabled(rhport) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) { dma_stpkt_rx(rhport); } @@ -1148,7 +1137,7 @@ static void handle_epin_irq(uint8_t rhport) { // Schedule another packet to be transmitted. edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); } else { - if((n == 0) && dma_supported(rhport)) { + if((n == 0) && dma_enabled(rhport)) { dma_stpkt_rx(rhport); } dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); -- cgit v1.3.1 From 02ec4866105eca3f95e7392e538caf97ebb902b4 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sun, 5 May 2024 22:01:09 +0200 Subject: Fix spurious EP0 completion. --- src/portable/synopsys/dwc2/dcd_dwc2.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index c4b1956ce..8c3a6ec61 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -1081,22 +1081,26 @@ static void handle_epout_irq(uint8_t rhport) { } else if (doepint & DOEPINT_OTEPSPR) { epout->doepint = DOEPINT_OTEPSPR; } else { - // EP0 can only handle one packet - if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) { - // Schedule another packet to be received. - edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) { + epout->doepint = DOEPINT_STPKTRX; } else { - if(dma_enabled(rhport)) { - // Fix packet length - uint16_t remain = (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; - xfer->total_len -= remain; - // this is ZLP, so prepare EP0 for next setup - if(n == 0 && xfer->total_len == 0) { - dma_stpkt_rx(rhport); + // EP0 can only handle one packet + if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) { + // Schedule another packet to be received. + edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + } else { + if(dma_enabled(rhport)) { + // Fix packet length + uint16_t remain = (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; + xfer->total_len -= remain; + // this is ZLP, so prepare EP0 for next setup + if(n == 0 && xfer->total_len == 0) { + dma_stpkt_rx(rhport); + } } - } - dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); + dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); + } } } } -- cgit v1.3.1 From 6d4e2f6c16e239889195fcfbd81b4d27b6ff1979 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Thu, 27 Jun 2024 22:02:18 +0200 Subject: Fix GenID 3.10 issue on STM32L4. --- src/portable/synopsys/dwc2/dcd_dwc2.c | 66 ++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 32 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index ffcb52f40..2871927be 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -1032,21 +1032,7 @@ static void handle_rxflvl_irq(uint8_t rhport) { // XFRC complete is additionally generated when // - setup packet is received // - complete the data stage of control write is complete - if ((epnum == 0) && (bcnt == 0) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) { - uint32_t doepint = epout->doepint; - - if (doepint & (DOEPINT_STPKTRX | DOEPINT_OTEPSPR)) { - // skip this "no-data" transfer complete event - // Note: STPKTRX will be clear later by setup received handler - uint32_t clear_flags = DOEPINT_XFRC; - - if (doepint & DOEPINT_OTEPSPR) clear_flags |= DOEPINT_OTEPSPR; - - epout->doepint = clear_flags; - - // TU_LOG(DWC2_DEBUG, " FIX extra transfer complete on setup/data compete\r\n"); - } - } + // It will be handled in handle_epout_irq() break; default: // Invalid @@ -1073,23 +1059,23 @@ static void handle_epout_irq(uint8_t rhport) { xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); - if (doepint & DOEPINT_STUP) { - // STPKTRX is only available for version from 3_00a - if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) { - epout->doepint = DOEPINT_STPKTRX; - } - } else if (doepint & DOEPINT_OTEPSPR) { - epout->doepint = DOEPINT_OTEPSPR; - } else { - if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) { - epout->doepint = DOEPINT_STPKTRX; + if(dma_enabled(rhport)) { + if (doepint & DOEPINT_STUP) { + // STPKTRX is only available for version from 3_00a + if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { + epout->doepint = DOEPINT_STPKTRX; + } + } else if (doepint & DOEPINT_OTEPSPR) { + epout->doepint = DOEPINT_OTEPSPR; } else { - // EP0 can only handle one packet - if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) { - // Schedule another packet to be received. - edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { + epout->doepint = DOEPINT_STPKTRX; } else { - if(dma_enabled(rhport)) { + // EP0 can only handle one packet + if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) { + // Schedule another packet to be received. + edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + } else { // Fix packet length uint16_t remain = (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; xfer->total_len -= remain; @@ -1097,8 +1083,24 @@ static void handle_epout_irq(uint8_t rhport) { if(n == 0 && xfer->total_len == 0) { dma_stpkt_rx(rhport); } + + dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); } + } + } + } else { + if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid == DWC2_CORE_REV_3_10a)) { + epout->doepint = DOEPINT_STPKTRX; + } else { + if ((doepint & DOEPINT_OTEPSPR) && (dwc2->gsnpsid == DWC2_CORE_REV_3_10a)) { + epout->doepint = DOEPINT_OTEPSPR; + } + // EP0 can only handle one packet + if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) { + // Schedule another packet to be received. + edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + } else { dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); } } @@ -1108,10 +1110,10 @@ static void handle_epout_irq(uint8_t rhport) { // SETUP packet Setup Phase done. if (doepint & DOEPINT_STUP) { epout->doepint = DOEPINT_STUP; - if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) { + if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { epout->doepint = DOEPINT_STPKTRX; } - if(dma_enabled(rhport) && (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a)) { + if(dma_enabled(rhport) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { dma_stpkt_rx(rhport); } -- cgit v1.3.1 From 0f288326cc80dba192d08b74116aa0be91a81a6f Mon Sep 17 00:00:00 2001 From: Brent Kowal Date: Fri, 28 Jun 2024 16:55:27 -0400 Subject: Initial Commit for MAX32 Support Initial commit for the port of TUSB to MAX32xxx parts, staring with MAX32690 - Added dcd_max32.c (based on dcd_musb.c) for interfacing with the peripheral - Added MAX32690 part family support - Added max32690evkit board support - Updated examples for unique EP number requirement - Updated get_deps.py to fetch the MSDK Known Issues / Additional Testing Required - msc_dual_lun only shown 1 volume on Windows - USBTMC does not have a valid Windowsdriver - DFU does not have a valid Windows driver - WebUSB is "Device not Recognized" - Need to test build scripts with IAR and Clang --- examples/device/cdc_msc/src/usb_descriptors.c | 10 + .../device/cdc_msc_freertos/src/usb_descriptors.c | 10 + examples/device/cdc_uac2/src/usb_descriptors.c | 10 + .../dynamic_configuration/src/usb_descriptors.c | 13 + examples/device/midi_test/src/usb_descriptors.c | 4 + examples/device/msc_dual_lun/src/usb_descriptors.c | 6 + .../device/net_lwip_webserver/src/tusb_config.h | 2 + .../net_lwip_webserver/src/usb_descriptors.c | 7 + examples/device/uac2_headset/src/usb_descriptors.c | 7 + .../device/webusb_serial/src/usb_descriptors.c | 7 + hw/bsp/board_mcu.h | 3 + hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h | 149 ++++ hw/bsp/max32690/boards/max32690evkit/board.cmake | 1 + hw/bsp/max32690/boards/max32690evkit/board.h | 56 ++ hw/bsp/max32690/boards/max32690evkit/board.mk | 1 + hw/bsp/max32690/family.c | 159 ++++ hw/bsp/max32690/family.cmake | 152 ++++ hw/bsp/max32690/family.mk | 106 +++ hw/bsp/max32690/max32690.ld | 162 ++++ src/common/tusb_mcu.h | 8 + src/portable/analog/max32/dcd_max32.c | 841 +++++++++++++++++++++ src/tusb_option.h | 3 + tools/get_deps.py | 3 + 23 files changed, 1720 insertions(+) create mode 100644 hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/max32690/boards/max32690evkit/board.cmake create mode 100644 hw/bsp/max32690/boards/max32690evkit/board.h create mode 100644 hw/bsp/max32690/boards/max32690evkit/board.mk create mode 100644 hw/bsp/max32690/family.c create mode 100644 hw/bsp/max32690/family.cmake create mode 100644 hw/bsp/max32690/family.mk create mode 100644 hw/bsp/max32690/max32690.ld create mode 100644 src/portable/analog/max32/dcd_max32.c (limited to 'src/portable') diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c index 2afa24903..1ca614f4e 100644 --- a/examples/device/cdc_msc/src/usb_descriptors.c +++ b/examples/device/cdc_msc/src/usb_descriptors.c @@ -125,6 +125,16 @@ enum { #define EPNUM_MSC_OUT 0x04 #define EPNUM_MSC_IN 0x85 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // MAX32 doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_CDC_NOTIF 0x81 + #define EPNUM_CDC_OUT 0x02 + #define EPNUM_CDC_IN 0x83 + + #define EPNUM_MSC_OUT 0x04 + #define EPNUM_MSC_IN 0x85 + #else #define EPNUM_CDC_NOTIF 0x81 #define EPNUM_CDC_OUT 0x02 diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_freertos/src/usb_descriptors.c index 9c29701c7..f563e80d3 100644 --- a/examples/device/cdc_msc_freertos/src/usb_descriptors.c +++ b/examples/device/cdc_msc_freertos/src/usb_descriptors.c @@ -106,6 +106,16 @@ enum #define EPNUM_MSC_OUT 0x04 #define EPNUM_MSC_IN 0x85 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // MAX32 doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_CDC_NOTIF 0x81 + #define EPNUM_CDC_OUT 0x02 + #define EPNUM_CDC_IN 0x83 + + #define EPNUM_MSC_OUT 0x04 + #define EPNUM_MSC_IN 0x85 + #else #define EPNUM_CDC_NOTIF 0x81 #define EPNUM_CDC_OUT 0x02 diff --git a/examples/device/cdc_uac2/src/usb_descriptors.c b/examples/device/cdc_uac2/src/usb_descriptors.c index 72a695622..43e8cf3d7 100644 --- a/examples/device/cdc_uac2/src/usb_descriptors.c +++ b/examples/device/cdc_uac2/src/usb_descriptors.c @@ -117,6 +117,16 @@ uint8_t const * tud_descriptor_device_cb(void) #define EPNUM_CDC_OUT 0x04 #define EPNUM_CDC_IN 0x85 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // MAX32 doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_AUDIO_IN 0x01 + #define EPNUM_AUDIO_OUT 0x02 + + #define EPNUM_CDC_NOTIF 0x83 + #define EPNUM_CDC_OUT 0x04 + #define EPNUM_CDC_IN 0x85 + #else #define EPNUM_AUDIO_IN 0x01 #define EPNUM_AUDIO_OUT 0x01 diff --git a/examples/device/dynamic_configuration/src/usb_descriptors.c b/examples/device/dynamic_configuration/src/usb_descriptors.c index 7f35b4b22..eebdd4f69 100644 --- a/examples/device/dynamic_configuration/src/usb_descriptors.c +++ b/examples/device/dynamic_configuration/src/usb_descriptors.c @@ -158,6 +158,19 @@ enum #define EPNUM_1_MSC_OUT 0x01 #define EPNUM_1_MSC_IN 0x82 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // FT9XX doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_0_CDC_NOTIF 0x81 + #define EPNUM_0_CDC_OUT 0x02 + #define EPNUM_0_CDC_IN 0x83 + + #define EPNUM_0_MIDI_OUT 0x04 + #define EPNUM_0_MIDI_IN 0x85 + + #define EPNUM_1_MSC_OUT 0x01 + #define EPNUM_1_MSC_IN 0x82 + #else #define EPNUM_0_CDC_NOTIF 0x81 #define EPNUM_0_CDC_OUT 0x02 diff --git a/examples/device/midi_test/src/usb_descriptors.c b/examples/device/midi_test/src/usb_descriptors.c index 9781d3d6f..797b50ab2 100644 --- a/examples/device/midi_test/src/usb_descriptors.c +++ b/examples/device/midi_test/src/usb_descriptors.c @@ -90,6 +90,10 @@ enum // On Bridgetek FT9xx endpoint numbers must be unique... #define EPNUM_MIDI_OUT 0x02 #define EPNUM_MIDI_IN 0x03 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // On MAX32 endpoint numbers must be unique... + #define EPNUM_MIDI_OUT 0x02 + #define EPNUM_MIDI_IN 0x03 #else #define EPNUM_MIDI_OUT 0x01 #define EPNUM_MIDI_IN 0x01 diff --git a/examples/device/msc_dual_lun/src/usb_descriptors.c b/examples/device/msc_dual_lun/src/usb_descriptors.c index c0610945f..e32466228 100644 --- a/examples/device/msc_dual_lun/src/usb_descriptors.c +++ b/examples/device/msc_dual_lun/src/usb_descriptors.c @@ -97,6 +97,12 @@ enum #define EPNUM_MSC_OUT 0x01 #define EPNUM_MSC_IN 0x82 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // MAX32 doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_MSC_OUT 0x01 + #define EPNUM_MSC_IN 0x82 + #else #define EPNUM_MSC_OUT 0x01 #define EPNUM_MSC_IN 0x81 diff --git a/examples/device/net_lwip_webserver/src/tusb_config.h b/examples/device/net_lwip_webserver/src/tusb_config.h index d3e094517..2f641f33e 100644 --- a/examples/device/net_lwip_webserver/src/tusb_config.h +++ b/examples/device/net_lwip_webserver/src/tusb_config.h @@ -91,6 +91,8 @@ extern "C" { #define USE_ECM 1 #elif TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F1) #define USE_ECM 1 +#elif TU_CHECK_MCU(OPT_MCU_MAX32690) + #define USE_ECM 1 #else #define USE_ECM 0 #define INCLUDE_IPERF diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c index da628c8be..ba30b869e 100644 --- a/examples/device/net_lwip_webserver/src/usb_descriptors.c +++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c @@ -120,6 +120,13 @@ uint8_t const * tud_descriptor_device_cb(void) #define EPNUM_NET_OUT 0x02 #define EPNUM_NET_IN 0x83 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // MAX32 doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_NET_NOTIF 0x81 + #define EPNUM_NET_OUT 0x02 + #define EPNUM_NET_IN 0x83 + #else #define EPNUM_NET_NOTIF 0x81 #define EPNUM_NET_OUT 0x02 diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c index ff4dc2acc..bfc8a4ab5 100644 --- a/examples/device/uac2_headset/src/usb_descriptors.c +++ b/examples/device/uac2_headset/src/usb_descriptors.c @@ -104,6 +104,13 @@ uint8_t const * tud_descriptor_device_cb(void) #define EPNUM_AUDIO_OUT 0x02 #define EPNUM_AUDIO_INT 0x03 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // MAX32 doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_AUDIO_IN 0x01 + #define EPNUM_AUDIO_OUT 0x02 + #define EPNUM_AUDIO_INT 0x03 + #else #define EPNUM_AUDIO_IN 0x01 #define EPNUM_AUDIO_OUT 0x01 diff --git a/examples/device/webusb_serial/src/usb_descriptors.c b/examples/device/webusb_serial/src/usb_descriptors.c index b01fae8e3..bcfbe590e 100644 --- a/examples/device/webusb_serial/src/usb_descriptors.c +++ b/examples/device/webusb_serial/src/usb_descriptors.c @@ -105,6 +105,13 @@ enum #define EPNUM_CDC_OUT 3 #define EPNUM_VENDOR_IN 4 #define EPNUM_VENDOR_OUT 5 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + // MAX32 doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_CDC_IN 2 + #define EPNUM_CDC_OUT 3 + #define EPNUM_VENDOR_IN 4 + #define EPNUM_VENDOR_OUT 5 #else #define EPNUM_CDC_IN 2 #define EPNUM_CDC_OUT 2 diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index 013eb1c83..436164c35 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -170,6 +170,9 @@ #elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837) // no header needed +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 + #include "max32690.h" + #else #error "Missing MCU header" #endif diff --git a/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..e5a76af85 --- /dev/null +++ b/hw/bsp/max32690/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,149 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "mxc_device.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS __NVIC_PRIO_BITS + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN; + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_USB); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) { + #if LED_STATE_ON + state = !state; + #endif + if(state) { + MXC_GPIO_OutClr(LED_PORT, LED_PIN); + } else { + MXC_GPIO_OutSet(LED_PORT, LED_PIN); + } +} + +uint32_t board_button_read(void) { + uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0; + return BUTTON_STATE_ACTIVE == state; +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN]; //USN Buffer + /* All other 2nd parameter is optional checkum buffer */ + MXC_SYS_GetUSN(hw_id, NULL); + + size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); + memcpy(id, hw_id, act_len); + return act_len; +} + +int board_uart_read(uint8_t *buf, int len) { + int uart_val; + int act_len = 0; + + while( act_len < len ) { + if((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { + break; + } else { + *buf++ = (uint8_t)uart_val; + act_len++; + } + } + return act_len; +} + +int board_uart_write(void const *buf, int len) { + int act_len = 0; + const uint8_t* ch_ptr = (const uint8_t*)buf; + while(act_len < len){ + MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++); + act_len++; + } + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) { + system_ticks++; +} + +uint32_t board_millis(void) { + return system_ticks; +} +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake new file mode 100644 index 000000000..e1d797f58 --- /dev/null +++ b/hw/bsp/max32690/family.cmake @@ -0,0 +1,152 @@ +include_guard() + +set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers) +set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS) +set(CMSIS_5 ${TOP}/lib/CMSIS_5) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# Get the linker file from current location (family) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max32690.ld) +set(LD_FILE_Clang ${LD_FILE_GNU}) + +# toolchain set up +set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) +set(JLINK_DEVICE max32690) + +set(FAMILY_MCUS MAX32690 CACHE INTERNAL "") + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + TARGET=MAX32690 + TARGET_REV=0x4131 + MXC_ASSERT_ENABLE + MAX32690 + FLASH_ORIGIN=0x10000000 + FLASH_SIZE=0x340000 + SRAM_ORIGIN=0x20000000 + SRAM_SIZE=0x100000 + IAR_PRAGMAS=0 + CFG_TUSB_MCU=OPT_MCU_MAX32690 + BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + ) +endfunction() + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/GCC/startup_max32690.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/IAR/startup_max32690.s) + + set(PERIPH_SRC ${MAX32_PERIPH}/Source) + add_library(${BOARD_TARGET} STATIC + ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/heap.c + ${MAX32_CMSIS}/Device/Maxim/MAX32690/Source/system_max32690.c + ${PERIPH_SRC}/SYS/mxc_assert.c + ${PERIPH_SRC}/SYS/mxc_delay.c + ${PERIPH_SRC}/SYS/mxc_lock.c + ${PERIPH_SRC}/SYS/nvic_table.c + ${PERIPH_SRC}/SYS/pins_me18.c + ${PERIPH_SRC}/SYS/sys_me18.c + ${PERIPH_SRC}/CTB/ctb_me18.c + ${PERIPH_SRC}/CTB/ctb_reva.c + ${PERIPH_SRC}/CTB/ctb_common.c + ${PERIPH_SRC}/FLC/flc_common.c + ${PERIPH_SRC}/FLC/flc_me18.c + ${PERIPH_SRC}/FLC/flc_reva.c + ${PERIPH_SRC}/GPIO/gpio_common.c + ${PERIPH_SRC}/GPIO/gpio_me18.c + ${PERIPH_SRC}/GPIO/gpio_reva.c + ${PERIPH_SRC}/ICC/icc_me18.c + ${PERIPH_SRC}/ICC/icc_reva.c + ${PERIPH_SRC}/UART/uart_common.c + ${PERIPH_SRC}/UART/uart_me18.c + ${PERIPH_SRC}/UART/uart_revb.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMSIS_5}/CMSIS/Core/Include + ${MAX32_CMSIS}/Include + ${MAX32_CMSIS}/Device/Maxim/MAX32690/Include + ${MAX32_PERIPH}/Include/MAX32690 + ${PERIPH_SRC}/SYS + ${PERIPH_SRC}/GPIO + ${PERIPH_SRC}/CTB + ${PERIPH_SRC}/ICC + ${PERIPH_SRC}/FLC + ${PERIPH_SRC}/UART + ) + + target_compile_options(${TARGET} PRIVATE + -Wno-error=strict-prototypes + ) + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_MAX32690 ${RTOS}) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/analog/max32/dcd_max32.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_compile_options(${TARGET}-tinyusb PRIVATE + -Wno-error=strict-prototypes + ) + + # Link dependencies + target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + + # Flashing + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/max32690/family.mk b/hw/bsp/max32690/family.mk new file mode 100644 index 000000000..08d5e8671 --- /dev/null +++ b/hw/bsp/max32690/family.mk @@ -0,0 +1,106 @@ +DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32 + +# Important locations in the hw support for MCU +MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS +MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers + +# Add any board specific make rules +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 +PORT ?= 0 + +# GCC +SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/GCC/startup_max32690.s +LD_FILE = $(FAMILY_PATH)/max32690.ld + +# IAR +SRC_S_IAR += $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/IAR/startup_max32690.s + +# -------------- +# Compiler Flags +# -------------- +# Flags for the MAX32690 SDK +CFLAGS += -DTARGET=MAX32690 \ + -DTARGET_REV=0x4131 \ + -DMXC_ASSERT_ENABLE \ + -DMAX32690 \ + -DFLASH_ORIGIN=0x10000000 \ + -DFLASH_SIZE=0x340000 \ + -DSRAM_ORIGIN=0x20000000 \ + -DSRAM_SIZE=0x100000 \ + -DIAR_PRAGMAS=0 + +# Flags for TUSB features +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_MAX32690 \ + -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + +# mcu driver cause following warnings +CFLAGS += -Wno-error=unused-parameter \ + -Wno-error=strict-prototypes \ + -Wno-error=old-style-declaration \ + -Wno-error=sign-compare \ + -Wno-error=cast-qual \ + -Wno-lto-type-mismatch + +LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs + +# For flash-jlink target +JLINK_DEVICE = max32690 + +# flash target using Jlik +flash: flash-jlink + +# Optional flash option when running within an installed MSDK to use OpenOCD +# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. +# If the MSDK is installed, flash-msdk can be run to utilize the the modified +# openocd with the algorithms +MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) +flash-msdk: + $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ + -f interface/cmsis-dap.cfg -f target/max32690.cfg \ + -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" + +# ----------------- +# Sources & Include +# ----------------- +PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source +SRC_C += \ + src/portable/analog/max32/dcd_max32.c \ + $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/heap.c \ + $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/system_max32690.c \ + $(PERIPH_SRC)/SYS/mxc_assert.c \ + $(PERIPH_SRC)/SYS/mxc_delay.c \ + $(PERIPH_SRC)/SYS/mxc_lock.c \ + $(PERIPH_SRC)/SYS/nvic_table.c \ + $(PERIPH_SRC)/SYS/pins_me18.c \ + $(PERIPH_SRC)/SYS/sys_me18.c \ + $(PERIPH_SRC)/CTB/ctb_me18.c \ + $(PERIPH_SRC)/CTB/ctb_reva.c \ + $(PERIPH_SRC)/CTB/ctb_common.c \ + $(PERIPH_SRC)/FLC/flc_common.c \ + $(PERIPH_SRC)/FLC/flc_me18.c \ + $(PERIPH_SRC)/FLC/flc_reva.c \ + $(PERIPH_SRC)/GPIO/gpio_common.c \ + $(PERIPH_SRC)/GPIO/gpio_me18.c \ + $(PERIPH_SRC)/GPIO/gpio_reva.c \ + $(PERIPH_SRC)/ICC/icc_me18.c \ + $(PERIPH_SRC)/ICC/icc_reva.c \ + $(PERIPH_SRC)/UART/uart_common.c \ + $(PERIPH_SRC)/UART/uart_me18.c \ + $(PERIPH_SRC)/UART/uart_revb.c \ + + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(MAX32_CMSIS)/Include \ + $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32690/Include \ + $(TOP)/$(MAX32_PERIPH)/Include/MAX32690 \ + $(PERIPH_SRC)/SYS \ + $(PERIPH_SRC)/GPIO \ + $(PERIPH_SRC)/CTB \ + $(PERIPH_SRC)/ICC \ + $(PERIPH_SRC)/FLC \ + $(PERIPH_SRC)/UART diff --git a/hw/bsp/max32690/max32690.ld b/hw/bsp/max32690/max32690.ld new file mode 100644 index 000000000..35886fe3a --- /dev/null +++ b/hw/bsp/max32690/max32690.ld @@ -0,0 +1,162 @@ +MEMORY { + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00020000 /* 128kB ROM */ + FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00340000 + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00100000 + + /* + * Note that CS0/CS1 address mappings may be reversed using MXC_HPC->mbr0 and ->mbr1 + * The following mappings are selected for simplicity + */ + HPB_CS0 (rwx) : ORIGIN = 0x60000000, LENGTH = 0x10000000 /* External Hyperbus/Xccelabus chip select 0 */ + HPB_CS1 (rwx) : ORIGIN = 0x70000000, LENGTH = 0x10000000 /* External Hyperbus/Xccelabus chip select 1 */ +} + +SECTIONS { + .rom : + { + KEEP(*(.rom_vector)) + *(.rom_handlers*) + } > ROM + + .text : + { + _text = .; + KEEP(*(.isr_vector)) + EXCLUDE_FILE (*riscv.o) *(.text*) /* program code, exclude RISCV code */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + /* These sections allow code to be compiled/linked for HPB addresses, but reside in + * flash until copied by code to the external HPB flash device + */ + .hpb_cs0_section : + { + __hpb_cs0_start = ABSOLUTE(.); + KEEP(*(.hpb_cs0_section*)) + } > HPB_CS0 AT>FLASH + + __load_start_hpb_cs0 = LOADADDR(.hpb_cs0_section); + __load_length_hpb_cs0 = SIZEOF(.hpb_cs0_section); + + .hpb_cs1_section : + { + __hpb_cs1_start = ABSOLUTE(.); + KEEP(*(.hpb_cs1_section*)) + } > HPB_CS1 AT>FLASH + + __load_start_hpb_cs1 = LOADADDR(.hpb_cs1_section); + __load_length_hpb_cs1 = SIZEOF(.hpb_cs1_section); + + /* Binary import */ + .bin_storage : + { + FILL(0xFF) + _bin_start_ = .; + KEEP(*(.bin_storage_img)) + _bin_end_ = .; + . = ALIGN(4); + } > FLASH + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + *(vtable) + *(.data*) /*read-write initialized data: initialized global variable*/ + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + /* Run the flash programming functions from SRAM */ + *(.flashprog) + + _edata = ALIGN(., 4); + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") +} diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index c66996c4f..a68e160bd 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -452,6 +452,14 @@ #define TUP_RHPORT_HIGHSPEED CFG_TUD_WCH_USBIP_USBHS #define TUP_DCD_ENDPOINT_MAX (CFG_TUD_WCH_USBIP_USBHS ? 16 : 8) +//--------------------------------------------------------------------+ +// Analog Devices +//--------------------------------------------------------------------+ +#elif TU_CHECK_MCU(OPT_MCU_MAX32690) + #define TUP_DCD_ENDPOINT_MAX 12 + #define TUP_RHPORT_HIGHSPEED 1 + + #endif //--------------------------------------------------------------------+ diff --git a/src/portable/analog/max32/dcd_max32.c b/src/portable/analog/max32/dcd_max32.c new file mode 100644 index 000000000..150d476fa --- /dev/null +++ b/src/portable/analog/max32/dcd_max32.c @@ -0,0 +1,841 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Koji KITAYAMA + * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUD_ENABLED && TU_CHECK_MCU(OPT_MCU_MAX32690) + +#if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) +/* GCC warns that an address may be unaligned, even though + * the target CPU has the capability for unaligned memory access. */ +_Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); +#endif + +#include "device/dcd.h" + +#include "mxc_delay.h" +#include "mxc_device.h" +#include "mxc_sys.h" +#include "nvic_table.h" +#include "usbhs_regs.h" + +#define USBHS_M31_CLOCK_RECOVERY + +/*------------------------------------------------------------------ + * MACRO TYPEDEF CONSTANT ENUM DECLARATION + *------------------------------------------------------------------*/ +#define REQUEST_TYPE_INVALID (0xFFu) + + +typedef union { + uint8_t u8; + uint16_t u16; + uint32_t u32; +} hw_fifo_t; + +typedef struct TU_ATTR_PACKED +{ + void *buf; /* the start address of a transfer data buffer */ + uint16_t length; /* the number of bytes in the buffer */ + uint16_t remaining; /* the number of bytes remaining in the buffer */ +} pipe_state_t; + +typedef struct +{ + tusb_control_request_t setup_packet; + uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */ + int8_t status_out; + pipe_state_t pipe0; + pipe_state_t pipe[2][TUP_DCD_ENDPOINT_MAX - 1]; /* pipe[direction][endpoint number - 1] */ + uint16_t pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */ +} dcd_data_t; + +/*------------------------------------------------------------------ + * INTERNAL OBJECT & FUNCTION DECLARATION + *------------------------------------------------------------------*/ +static dcd_data_t _dcd; + + +static volatile void* edpt_get_fifo_ptr(unsigned epnum) +{ + volatile uint32_t *ptr; + + ptr = &MXC_USBHS->fifo0; + ptr += epnum; /* Pointer math: multiplies ep by sizeof(uint32_t) */ + + return (volatile void *)ptr; +} + +static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) +{ + volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; + uintptr_t addr = (uintptr_t)buf; + while (len >= 4) { + reg->u32 = *(uint32_t const *)addr; + addr += 4; + len -= 4; + } + if (len >= 2) { + reg->u16 = *(uint16_t const *)addr; + addr += 2; + len -= 2; + } + if (len) { + reg->u8 = *(uint8_t const *)addr; + } +} + +static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) +{ + volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; + uintptr_t addr = (uintptr_t)buf; + while (len >= 4) { + *(uint32_t *)addr = reg->u32; + addr += 4; + len -= 4; + } + if (len >= 2) { + *(uint16_t *)addr = reg->u16; + addr += 2; + len -= 2; + } + if (len) { + *(uint8_t *)addr = reg->u8; + } +} + +static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) +{ + static const struct { + void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info); + void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n); + void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len); + } ops[] = { + /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet}, + /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, + }; + tu_fifo_buffer_info_t info; + ops[dir].tu_fifo_get_info(f, &info); + unsigned total_len = len; + len = TU_MIN(total_len, info.len_lin); + ops[dir].pipe_read_write(info.ptr_lin, fifo, len); + unsigned rem = total_len - len; + if (rem) { + len = TU_MIN(rem, info.len_wrap); + ops[dir].pipe_read_write(info.ptr_wrap, fifo, len); + rem -= len; + } + ops[dir].tu_fifo_advance(f, total_len - rem); +} + +static void process_setup_packet(uint8_t rhport) +{ + uint32_t *p = (void*)&_dcd.setup_packet; + p[0] = MXC_USBHS->fifo0; + p[1] = MXC_USBHS->fifo0; + + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; + _dcd.pipe0.remaining = 0; + dcd_event_setup_received(rhport, (const uint8_t*)(uintptr_t)&_dcd.setup_packet, true); + + const unsigned len = _dcd.setup_packet.wLength; + _dcd.remaining_ctrl = len; + const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType); + /* Clear RX FIFO and reverse the transaction direction */ + if (len && dir_in) { + MXC_USBHS->index = 0; + MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY; + } +} + +static bool handle_xfer_in(uint_fast8_t ep_addr) +{ + unsigned epnum = tu_edpt_number(ep_addr); + unsigned epnum_minus1 = epnum - 1; + pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; + const unsigned rem = pipe->remaining; + + //This function should not be for ep0 + TU_ASSERT(epnum); + + if (!rem) { + pipe->buf = NULL; + return true; + } + + MXC_USBHS->index = epnum; + const unsigned mps = MXC_USBHS->inmaxp; + const unsigned len = TU_MIN(mps, rem); + void *buf = pipe->buf; + volatile void* fifo_ptr = edpt_get_fifo_ptr(epnum); + // TU_LOG1(" %p mps %d len %d rem %d\r\n", buf, mps, len, rem); + if (len) { + if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) { + pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_IN); + } else { + pipe_write_packet(buf,fifo_ptr, len); + pipe->buf = buf + len; + } + pipe->remaining = rem - len; + } + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_INPKTRDY; //TODO: Verify a | isnt needed + + return false; +} + +static bool handle_xfer_out(uint_fast8_t ep_addr) +{ + unsigned epnum = tu_edpt_number(ep_addr); + unsigned epnum_minus1 = epnum - 1; + pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; + + //This function should not be for ep0 + TU_ASSERT(epnum); + + MXC_USBHS->index = epnum; + + TU_ASSERT(MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY); + + const unsigned mps = MXC_USBHS->outmaxp; + const unsigned rem = pipe->remaining; + const unsigned vld = MXC_USBHS->outcount; + const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); + void *buf = pipe->buf; + volatile void* fifo_ptr = edpt_get_fifo_ptr(epnum); + if (len) { + if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) { + pipe_read_write_packet_ff(buf,fifo_ptr, len, TUSB_DIR_OUT); + } else { + pipe_read_packet(buf, fifo_ptr, len); + pipe->buf = buf + len; + } + pipe->remaining = rem - len; + } + if ((len < mps) || (rem == len)) { + pipe->buf = NULL; + return NULL != buf; + } + MXC_USBHS->outcsrl = 0; /* Clear RXRDY bit */ //TODO: Verify just setting to 0 is ok + return false; +} + +static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) +{ + (void)rhport; + + unsigned epnum = tu_edpt_number(ep_addr); + unsigned epnum_minus1 = epnum - 1; + unsigned dir_in = tu_edpt_dir(ep_addr); + + pipe_state_t *pipe = &_dcd.pipe[dir_in][epnum_minus1]; + pipe->buf = buffer; + pipe->length = total_bytes; + pipe->remaining = total_bytes; + + if (dir_in) { + handle_xfer_in(ep_addr); + } else { + MXC_USBHS->index = epnum; + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY){ + MXC_USBHS->outcsrl = 0; //TODO: Verify just setting to 0 is ok + } + } + return true; +} + +static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) +{ + (void)rhport; + TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */ + + const unsigned req = _dcd.setup_packet.bmRequestType; + TU_ASSERT(req != REQUEST_TYPE_INVALID || total_bytes == 0); + + if (req == REQUEST_TYPE_INVALID || _dcd.status_out) { + /* STATUS OUT stage. + * MUSB controller automatically handles STATUS OUT packets without + * software helps. We do not have to do anything. And STATUS stage + * may have already finished and received the next setup packet + * without calling this function, so we have no choice but to + * invoke the callback function of status packet here. */ + _dcd.status_out = 0; + if (req == REQUEST_TYPE_INVALID) { + dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false); + } else { + /* The next setup packet has already been received, it aborts + * invoking callback function to avoid confusing TUSB stack. */ + TU_LOG1("Drop CONTROL_STAGE_ACK\r\n"); + } + return true; + } + const unsigned dir_in = tu_edpt_dir(ep_addr); + MXC_USBHS->index = 0; + if (tu_edpt_dir(req) == dir_in) { /* DATA stage */ + TU_ASSERT(total_bytes <= _dcd.remaining_ctrl); + const unsigned rem = _dcd.remaining_ctrl; + const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes); + volatile void* fifo_ptr = edpt_get_fifo_ptr(0); + if (dir_in) { + pipe_write_packet(buffer, fifo_ptr, len); + + _dcd.pipe0.buf = buffer + len; + _dcd.pipe0.length = len; + _dcd.pipe0.remaining = 0; + + _dcd.remaining_ctrl = rem - len; + if ((len < 64) || (rem == len)) { + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */ + _dcd.status_out = 1; + /* Flush TX FIFO and reverse the transaction direction. */ + MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_INPKTRDY | MXC_F_USBHS_CSR0_DATA_END; + } else { + MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_INPKTRDY; /* Flush TX FIFO to return ACK. */ + } + } else { + _dcd.pipe0.buf = buffer; + _dcd.pipe0.length = len; + _dcd.pipe0.remaining = len; + MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY; /* Clear RX FIFO to return ACK. */ + } + } else if (dir_in) { + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; + _dcd.pipe0.remaining = 0; + /* Clear RX FIFO and reverse the transaction direction */ + MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY | MXC_F_USBHS_CSR0_DATA_END; + } + return true; +} + +static void process_ep0(uint8_t rhport) +{ + MXC_USBHS->index = 0; + uint_fast8_t csrl = MXC_USBHS->csr0; + + if (csrl & MXC_F_USBHS_CSR0_SENT_STALL) { + /* Returned STALL packet to HOST. */ + MXC_USBHS->csr0 = 0; /* Clear STALL */ + return; + } + + unsigned req = _dcd.setup_packet.bmRequestType; + if (csrl & MXC_F_USBHS_CSR0_SETUP_END) { + TU_LOG1(" ABORT by the next packets\r\n"); + MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_SETUP_END; + if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) { + /* DATA stage was aborted by receiving STATUS or SETUP packet. */ + _dcd.pipe0.buf = NULL; + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; + dcd_event_xfer_complete(rhport, + req & TUSB_DIR_IN_MASK, + _dcd.pipe0.length - _dcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + } + req = REQUEST_TYPE_INVALID; + if (!(csrl & MXC_F_USBHS_CSR0_OUTPKTRDY)) return; /* Received SETUP packet */ + } + + if (csrl & MXC_F_USBHS_CSR0_OUTPKTRDY) { + /* Received SETUP or DATA OUT packet */ + if (req == REQUEST_TYPE_INVALID) { + /* SETUP */ + TU_ASSERT(sizeof(tusb_control_request_t) == MXC_USBHS->count0,); + process_setup_packet(rhport); + return; + } + if (_dcd.pipe0.buf) { + /* DATA OUT */ + const unsigned vld = MXC_USBHS->count0; + const unsigned rem = _dcd.pipe0.remaining; + const unsigned len = TU_MIN(TU_MIN(rem, 64), vld); + volatile void* fifo_ptr = edpt_get_fifo_ptr(0); + pipe_read_packet(_dcd.pipe0.buf, fifo_ptr, len); + + _dcd.pipe0.remaining = rem - len; + _dcd.remaining_ctrl -= len; + + _dcd.pipe0.buf = NULL; + dcd_event_xfer_complete(rhport, + tu_edpt_addr(0, TUSB_DIR_OUT), + _dcd.pipe0.length - _dcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + } + return; + } + + /* When CSRL0 is zero, it means that completion of sending a any length packet + * or receiving a zero length packet. */ + if (req != REQUEST_TYPE_INVALID && !tu_edpt_dir(req)) { + /* STATUS IN */ + if (*(const uint16_t*)(uintptr_t)&_dcd.setup_packet == 0x0500) { + /* The address must be changed on completion of the control transfer. */ + MXC_USBHS->faddr = (uint8_t)_dcd.setup_packet.wValue; + } + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; + dcd_event_xfer_complete(rhport, + tu_edpt_addr(0, TUSB_DIR_IN), + _dcd.pipe0.length - _dcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + return; + } + if (_dcd.pipe0.buf) { + /* DATA IN */ + _dcd.pipe0.buf = NULL; + dcd_event_xfer_complete(rhport, + tu_edpt_addr(0, TUSB_DIR_IN), + _dcd.pipe0.length - _dcd.pipe0.remaining, + XFER_RESULT_SUCCESS, true); + } +} + +static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) +{ + bool completed; + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned epnum = tu_edpt_number(ep_addr); + + MXC_USBHS->index = epnum; + + if (dir_in) { + if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_SENTSTALL) { + MXC_USBHS->incsrl &= ~(MXC_F_USBHS_INCSRL_SENTSTALL | MXC_F_USBHS_INCSRL_UNDERRUN); + return; + } + completed = handle_xfer_in(ep_addr); + } else { + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_SENTSTALL) { + MXC_USBHS->outcsrl &= ~(MXC_F_USBHS_OUTCSRL_SENTSTALL | MXC_F_USBHS_OUTCSRL_OVERRUN); + return; + } + completed = handle_xfer_out(ep_addr); + } + + if (completed) { + pipe_state_t *pipe = &_dcd.pipe[dir_in][tu_edpt_number(ep_addr) - 1]; + dcd_event_xfer_complete(rhport, ep_addr, + pipe->length - pipe->remaining, + XFER_RESULT_SUCCESS, true); + } +} + +static void process_bus_reset(uint8_t rhport) +{ + (void)rhport; + TU_LOG0("------Bus Reset\r\n"); + /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), + * a control transfer state is SETUP or STATUS stage. */ + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; + _dcd.status_out = 0; + /* When pipe0.buf has not NULL, DATA stage works in progress. */ + _dcd.pipe0.buf = NULL; + + MXC_USBHS->intrinen = 1; /* Enable only EP0 */ + MXC_USBHS->introuten = 0; + + + /* Clear FIFO settings */ + for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { + MXC_USBHS->index = i; + if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { + /* Per musbhsfc_pg, only flush FIFO if IN packet loaded */ + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_FLUSHFIFO; + } + + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { + /* Per musbhsfc_pg, only flush FIFO if OUT packet is ready */ + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_FLUSHFIFO; + } + } + dcd_event_bus_reset(0, (MXC_USBHS->power & MXC_F_USBHS_POWER_HS_MODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); +} + +/*------------------------------------------------------------------ + * Device API + *------------------------------------------------------------------*/ + +void dcd_init(uint8_t rhport) +{ + (void)rhport; + MXC_USBHS->intrusben |= MXC_F_USBHS_INTRUSBEN_SUSPEND_INT_EN; + + //Interrupt for VBUS disconnect + MXC_USBHS->mxm_int_en |= MXC_F_USBHS_MXM_INT_EN_NOVBUS; + + NVIC_ClearPendingIRQ(USB_IRQn); + dcd_edpt_close_all(rhport); + + //Unsuspend the MAC + MXC_USBHS->mxm_suspend = 0; + + /* Configure PHY */ + MXC_USBHS->m31_phy_xcfgi_31_0 = (0x1 << 3) | (0x1 << 11); + MXC_USBHS->m31_phy_xcfgi_63_32 = 0; + MXC_USBHS->m31_phy_xcfgi_95_64 = 0x1 << (72-64); + MXC_USBHS->m31_phy_xcfgi_127_96 = 0; + + +#ifdef USBHS_M31_CLOCK_RECOVERY + MXC_USBHS->m31_phy_noncry_rstb = 1; + MXC_USBHS->m31_phy_noncry_en = 1; + MXC_USBHS->m31_phy_outclksel = 0; + MXC_USBHS->m31_phy_coreclkin = 0; + MXC_USBHS->m31_phy_xtlsel = 2; /* Select 25 MHz clock */ +#else + /* Use this option to feed the PHY a 30 MHz clock, which is them used as a PLL reference */ + /* As it depends on the system core clock, this should probably be done at the SYS level */ + MXC_USBHS->m31_phy_noncry_rstb = 0; + MXC_USBHS->m31_phy_noncry_en = 0; + MXC_USBHS->m31_phy_outclksel = 1; + MXC_USBHS->m31_phy_coreclkin = 1; + MXC_USBHS->m31_phy_xtlsel = 3; /* Select 30 MHz clock */ +#endif + MXC_USBHS->m31_phy_pll_en = 1; + MXC_USBHS->m31_phy_oscouten = 1; + + /* Reset PHY */ + MXC_USBHS->m31_phy_ponrst = 0; + MXC_USBHS->m31_phy_ponrst = 1; + + dcd_connect(rhport); +} + +void dcd_int_enable(uint8_t rhport) +{ + (void)rhport; + NVIC_EnableIRQ(USB_IRQn); +} + +void dcd_int_disable(uint8_t rhport) +{ + (void)rhport; + NVIC_DisableIRQ(USB_IRQn); +} + +// Receive Set Address request, mcu port must also include status IN response +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) +{ + (void)rhport; + (void)dev_addr; + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; + _dcd.pipe0.remaining = 0; + /* Clear RX FIFO to return ACK. */ + MXC_USBHS->index = 0; + MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY | MXC_F_USBHS_CSR0_DATA_END; +} + +// Wake up host +void dcd_remote_wakeup(uint8_t rhport) +{ + (void)rhport; + MXC_USBHS->power |= MXC_F_USBHS_POWER_RESUME; + +#if CFG_TUSB_OS != OPT_OS_NONE + osal_task_delay(10); +#else + MXC_Delay(MXC_DELAY_MSEC(10)); +#endif + + MXC_USBHS->power &= ~MXC_F_USBHS_POWER_RESUME; +} + +// Connect by enabling internal pull-up resistor on D+/D- +void dcd_connect(uint8_t rhport) +{ + (void)rhport; + MXC_USBHS->power |= TUD_OPT_HIGH_SPEED ? MXC_F_USBHS_POWER_HS_ENABLE : 0; + MXC_USBHS->power |= MXC_F_USBHS_POWER_SOFTCONN; +} + +// Disconnect by disabling internal pull-up resistor on D+/D- +void dcd_disconnect(uint8_t rhport) +{ + (void)rhport; + MXC_USBHS->power &= ~MXC_F_USBHS_POWER_SOFTCONN; +} + +void dcd_sof_enable(uint8_t rhport, bool en) +{ + (void) rhport; + (void) en; + + // TODO implement later +} + +//--------------------------------------------------------------------+ +// Endpoint API +//--------------------------------------------------------------------+ + +// Configure endpoint's registers according to descriptor +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) +{ + (void) rhport; + + const unsigned ep_addr = ep_desc->bEndpointAddress; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned xfer = ep_desc->bmAttributes.xfer; + const unsigned mps = tu_edpt_packet_size(ep_desc); + + TU_ASSERT(epn < TUP_DCD_ENDPOINT_MAX); + + pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1]; + pipe->buf = NULL; + pipe->length = 0; + pipe->remaining = 0; + + MXC_USBHS->index = epn; + + if (dir_in) { + MXC_USBHS->inmaxp = mps; + MXC_USBHS->incsru = (MXC_F_USBHS_INCSRU_DPKTBUFDIS | MXC_F_USBHS_INCSRU_MODE) | ((xfer == TUSB_XFER_ISOCHRONOUS) ? MXC_F_USBHS_INCSRU_ISO : 0); + if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO; + } else { + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; + } + MXC_USBHS->intrinen |= TU_BIT(epn); + } else { + MXC_USBHS->outmaxp = mps; + MXC_USBHS->outcsru = (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS) | ((xfer == TUSB_XFER_ISOCHRONOUS) ? MXC_F_USBHS_OUTCSRU_ISO : 0); + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO; + } else { + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG; + } + MXC_USBHS->introuten |= TU_BIT(epn); + } + + return true; +} + +void dcd_edpt_close_all(uint8_t rhport) +{ + (void) rhport; + + MXC_SYS_Crit_Enter(); + MXC_USBHS->intrinen = 1; /* Enable only EP0 */ + MXC_USBHS->introuten = 0; + + for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { + MXC_USBHS->index = i; + MXC_USBHS->inmaxp = 0; + MXC_USBHS->incsru = MXC_F_USBHS_INCSRU_DPKTBUFDIS; + + if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO; + } else { + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; + } + + MXC_USBHS->outmaxp = 0; + MXC_USBHS->outcsru = MXC_F_USBHS_OUTCSRU_DPKTBUFDIS; + + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO; + } else { + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG; + } + } + MXC_SYS_Crit_Exit(); +} + +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + unsigned const epn = tu_edpt_number(ep_addr); + unsigned const dir_in = tu_edpt_dir(ep_addr); + + MXC_SYS_Crit_Enter(); + MXC_USBHS->index = epn; + if (dir_in) { + MXC_USBHS->intrinen &= ~TU_BIT(epn); + MXC_USBHS->inmaxp = 0; + MXC_USBHS->incsru = MXC_F_USBHS_INCSRU_DPKTBUFDIS; + if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO; + } else { + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; + } + } else { + MXC_USBHS->introuten &= ~TU_BIT(epn); + MXC_USBHS->outmaxp = 0; + MXC_USBHS->outcsru = MXC_F_USBHS_OUTCSRU_DPKTBUFDIS; + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO; + } else { + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG; + } + } + MXC_SYS_Crit_Exit(); +} + +// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) +{ + (void)rhport; + bool ret; + unsigned const epnum = tu_edpt_number(ep_addr); + MXC_SYS_Crit_Enter(); + if (epnum) { + _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] &= ~TU_BIT(epnum - 1); + ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes); + } else + ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes); + MXC_SYS_Crit_Exit(); + return ret; +} + +// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c +bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) +{ + (void)rhport; + bool ret; + unsigned const epnum = tu_edpt_number(ep_addr); + TU_ASSERT(epnum); + MXC_SYS_Crit_Enter(); + _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] |= TU_BIT(epnum - 1); + ret = edpt_n_xfer(rhport, ep_addr, (uint8_t*)ff, total_bytes); + MXC_SYS_Crit_Exit(); + return ret; +} + +// Stall endpoint +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + unsigned const epn = tu_edpt_number(ep_addr); + MXC_SYS_Crit_Enter(); + MXC_USBHS->index = epn; + if (0 == epn) { + if (!ep_addr) { /* Ignore EP80 */ + _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; + _dcd.pipe0.buf = NULL; + MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SEND_STALL; + } + } else { + if (tu_edpt_dir(ep_addr)) { /* IN */ + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_SENDSTALL; + } else { /* OUT */ + TU_ASSERT(!(MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY),); + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_SENDSTALL; + } + } + MXC_SYS_Crit_Exit(); +} + +// clear stall, data toggle is also reset to DATA0 +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) +{ + (void)rhport; + unsigned const epn = tu_edpt_number(ep_addr); + MXC_SYS_Crit_Enter(); + MXC_USBHS->index = epn; + if (tu_edpt_dir(ep_addr)) { /* IN */ + /* IN endpoint */ + if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { + /* Per musbhsfc_pg, only flush FIFO if IN packet loaded */ + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO; + } else { + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; + } + } else { /* OUT */ + /* Otherwise, must be OUT endpoint */ + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { + /* Per musbhsfc_pg, only flush FIFO if OUT packet is ready */ + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO; + } else { + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG; + } + } + MXC_SYS_Crit_Exit(); +} + +/*------------------------------------------------------------------- + * ISR + *-------------------------------------------------------------------*/ +void dcd_int_handler(uint8_t rhport) +{ + uint_fast8_t is, txis, rxis; + uint32_t mxm_int, mxm_int_en, mxm_is; + uint32_t saved_index; + + /* Save current index register */ + saved_index = MXC_USBHS->index; + + is = MXC_USBHS->intrusb; /* read and clear interrupt status */ + txis = MXC_USBHS->intrin; /* read and clear interrupt status */ + rxis = MXC_USBHS->introut; /* read and clear interrupt status */ + + /* These USB interrupt flags are W1C. */ + /* Order of volatile accesses must be separated for IAR */ + mxm_int = MXC_USBHS->mxm_int; + mxm_int_en = MXC_USBHS->mxm_int_en; + mxm_is = mxm_int & mxm_int_en; + MXC_USBHS->mxm_int = mxm_is; + + is &= MXC_USBHS->intrusben; /* Clear disabled interrupts */ + + if (mxm_is & MXC_F_USBHS_MXM_INT_NOVBUS) { + dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); + } + if (is & MXC_F_USBHS_INTRUSB_SOF_INT) { + dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); + } + if (is & MXC_F_USBHS_INTRUSB_RESET_INT) { + process_bus_reset(rhport); + } + if (is & MXC_F_USBHS_INTRUSB_RESUME_INT) { + dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); + } + if (is & MXC_F_USBHS_INTRUSB_SUSPEND_INT) { + dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); + } + + txis &= MXC_USBHS->intrinen; /* Clear disabled interrupts */ + if (txis & MXC_F_USBHS_INTRIN_EP0_IN_INT) { + process_ep0(rhport); + txis &= ~TU_BIT(0); + } + while (txis) { + unsigned const num = __builtin_ctz(txis); + process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN)); + txis &= ~TU_BIT(num); + } + rxis &= MXC_USBHS->introuten; /* Clear disabled interrupts */ + while (rxis) { + unsigned const num = __builtin_ctz(rxis); + process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT)); + rxis &= ~TU_BIT(num); + } + + /* Restore register index before exiting ISR */ + MXC_USBHS->index = saved_index; +} + +#endif diff --git a/src/tusb_option.h b/src/tusb_option.h index db8b94580..18f78b49c 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -188,6 +188,9 @@ #define OPT_MCU_MCXN9 2300 ///< NXP MCX N9 Series #define OPT_MCU_MCXA15 2301 ///< NXP MCX A15 Series +// Analog Devices +#define OPT_MCU_MAX32690 2400 ///< ADI MAX32690 + // Check if configured MCU is one of listed // Apply _TU_CHECK_MCU with || as separator to list of input #define _TU_CHECK_MCU(_m) (CFG_TUSB_MCU == _m) diff --git a/tools/get_deps.py b/tools/get_deps.py index 50cc5c893..e05cc4d76 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -24,6 +24,9 @@ deps_optional = { 'hw/mcu/allwinner': ['https://github.com/hathach/allwinner_driver.git', '8e5e89e8e132c0fd90e72d5422e5d3d68232b756', 'fc100s'], + 'hw/mcu/analog/max32' : ['https://github.com/analogdevicesinc/msdk.git', + 'b20b398d3e5e2007594e54a74ba3d2a2e50ddd75', + 'max32690'], 'hw/mcu/bridgetek/ft9xx/ft90x-sdk': ['https://github.com/BRTSG-FOSS/ft90x-sdk.git', '91060164afe239fcb394122e8bf9eb24d3194eb1', 'brtmm90x'], -- cgit v1.3.1 From 0b82af61f3ca7f6b708399c49519fb109ab33abb Mon Sep 17 00:00:00 2001 From: Brent Kowal Date: Mon, 1 Jul 2024 16:31:17 -0400 Subject: AD-APARD32690-SL Support and Cleanup - Added BSP for AD-APARD32690-SL board (apard32690) - Ran clang-formatting on previously committed code - Removed LOG messages from dcd_max32.c --- hw/bsp/max32690/boards/apard32690/board.cmake | 1 + hw/bsp/max32690/boards/apard32690/board.h | 56 +++++ hw/bsp/max32690/boards/apard32690/board.mk | 1 + hw/bsp/max32690/boards/max32690evkit/board.h | 22 +- hw/bsp/max32690/family.c | 32 +-- src/portable/analog/max32/dcd_max32.c | 339 ++++++++++++-------------- 6 files changed, 239 insertions(+), 212 deletions(-) create mode 100644 hw/bsp/max32690/boards/apard32690/board.cmake create mode 100644 hw/bsp/max32690/boards/apard32690/board.h create mode 100644 hw/bsp/max32690/boards/apard32690/board.mk (limited to 'src/portable') diff --git a/hw/bsp/max32690/boards/apard32690/board.cmake b/hw/bsp/max32690/boards/apard32690/board.cmake new file mode 100644 index 000000000..9dc6962eb --- /dev/null +++ b/hw/bsp/max32690/boards/apard32690/board.cmake @@ -0,0 +1 @@ +# Nothing to be done at the board level diff --git a/hw/bsp/max32690/boards/apard32690/board.h b/hw/bsp/max32690/boards/apard32690/board.h new file mode 100644 index 000000000..f94097ca9 --- /dev/null +++ b/hw/bsp/max32690/boards/apard32690/board.h @@ -0,0 +1,56 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#include "gpio.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// LED +#define LED_PORT MXC_GPIO2 +#define LED_PIN MXC_GPIO_PIN_1 +#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH +#define LED_STATE_ON 1 + +// Button +#define BUTTON_PORT MXC_GPIO1 +#define BUTTON_PIN MXC_GPIO_PIN_27 +#define BUTTON_PULL MXC_GPIO_PAD_NONE +#define BUTTON_STATE_ACTIVE 1 + +// UART Enable for UART on ARM SWD Connector +#define UART_NUM 0 + +#ifdef __cplusplus +} +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/max32690/boards/apard32690/board.mk b/hw/bsp/max32690/boards/apard32690/board.mk new file mode 100644 index 000000000..a813a5327 --- /dev/null +++ b/hw/bsp/max32690/boards/apard32690/board.mk @@ -0,0 +1 @@ +# No specific build requirements for the board. diff --git a/hw/bsp/max32690/boards/max32690evkit/board.h b/hw/bsp/max32690/boards/max32690evkit/board.h index f5a904702..05d60f220 100644 --- a/hw/bsp/max32690/boards/max32690evkit/board.h +++ b/hw/bsp/max32690/boards/max32690evkit/board.h @@ -31,26 +31,26 @@ #include "mxc_sys.h" #ifdef __cplusplus - extern "C" { +extern "C" { #endif // LED -#define LED_PORT MXC_GPIO0 -#define LED_PIN MXC_GPIO_PIN_14 -#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH -#define LED_STATE_ON 0 +#define LED_PORT MXC_GPIO0 +#define LED_PIN MXC_GPIO_PIN_14 +#define LED_VDDIO MXC_GPIO_VSSEL_VDDIOH +#define LED_STATE_ON 0 // Button -#define BUTTON_PORT MXC_GPIO4 -#define BUTTON_PIN MXC_GPIO_PIN_0 -#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP -#define BUTTON_STATE_ACTIVE 0 +#define BUTTON_PORT MXC_GPIO4 +#define BUTTON_PIN MXC_GPIO_PIN_0 +#define BUTTON_PULL MXC_GPIO_PAD_PULL_UP +#define BUTTON_STATE_ACTIVE 0 // UART Enable for EvKit's Integrated FTDI Adapter. Pin Mux handled by the HAL -#define UART_NUM 2 +#define UART_NUM 2 #ifdef __cplusplus - } +} #endif #endif /* BOARD_H_ */ diff --git a/hw/bsp/max32690/family.c b/hw/bsp/max32690/family.c index f443bc575..acd6e2593 100644 --- a/hw/bsp/max32690/family.c +++ b/hw/bsp/max32690/family.c @@ -24,12 +24,12 @@ * This file is part of the TinyUSB stack. */ -#include "bsp/board_api.h" #include "board.h" -#include "mxc_device.h" +#include "bsp/board_api.h" +#include "gpio.h" #include "mcr_regs.h" +#include "mxc_device.h" #include "uart.h" -#include "gpio.h" //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler @@ -49,7 +49,7 @@ void board_init(void) { SysTick_Config(SystemCoreClock / 1000); #elif CFG_TUSB_OS == OPT_OS_FREERTOS // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) - NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY ); + NVIC_SetPriority(USB_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); #endif mxc_gpio_cfg_t gpioConfig; @@ -87,10 +87,10 @@ void board_init(void) { //--------------------------------------------------------------------+ void board_led_write(bool state) { - #if LED_STATE_ON - state = !state; - #endif - if(state) { +#if LED_STATE_ON + state = !state; +#endif + if (state) { MXC_GPIO_OutClr(LED_PORT, LED_PIN); } else { MXC_GPIO_OutSet(LED_PORT, LED_PIN); @@ -103,9 +103,9 @@ uint32_t board_button_read(void) { } size_t board_get_unique_id(uint8_t id[], size_t max_len) { - uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN]; //USN Buffer - /* All other 2nd parameter is optional checkum buffer */ - MXC_SYS_GetUSN(hw_id, NULL); + uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer + /* All other 2nd parameter is optional checkum buffer */ + MXC_SYS_GetUSN(hw_id, NULL); size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); memcpy(id, hw_id, act_len); @@ -116,11 +116,11 @@ int board_uart_read(uint8_t *buf, int len) { int uart_val; int act_len = 0; - while( act_len < len ) { - if((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { + while (act_len < len) { + if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { break; } else { - *buf++ = (uint8_t)uart_val; + *buf++ = (uint8_t) uart_val; act_len++; } } @@ -129,8 +129,8 @@ int board_uart_read(uint8_t *buf, int len) { int board_uart_write(void const *buf, int len) { int act_len = 0; - const uint8_t* ch_ptr = (const uint8_t*)buf; - while(act_len < len){ + const uint8_t *ch_ptr = (const uint8_t *) buf; + while (act_len < len) { MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++); act_len++; } diff --git a/src/portable/analog/max32/dcd_max32.c b/src/portable/analog/max32/dcd_max32.c index 150d476fa..b3370ddd1 100644 --- a/src/portable/analog/max32/dcd_max32.c +++ b/src/portable/analog/max32/dcd_max32.c @@ -29,49 +29,48 @@ #if CFG_TUD_ENABLED && TU_CHECK_MCU(OPT_MCU_MAX32690) -#if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) + #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) /* GCC warns that an address may be unaligned, even though * the target CPU has the capability for unaligned memory access. */ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); -#endif + #endif -#include "device/dcd.h" + #include "device/dcd.h" -#include "mxc_delay.h" -#include "mxc_device.h" -#include "mxc_sys.h" -#include "nvic_table.h" -#include "usbhs_regs.h" + #include "mxc_delay.h" + #include "mxc_device.h" + #include "mxc_sys.h" + #include "nvic_table.h" + #include "usbhs_regs.h" -#define USBHS_M31_CLOCK_RECOVERY + #define USBHS_M31_CLOCK_RECOVERY -/*------------------------------------------------------------------ + /*------------------------------------------------------------------ * MACRO TYPEDEF CONSTANT ENUM DECLARATION *------------------------------------------------------------------*/ -#define REQUEST_TYPE_INVALID (0xFFu) + #define REQUEST_TYPE_INVALID (0xFFu) typedef union { - uint8_t u8; - uint16_t u16; - uint32_t u32; + uint8_t u8; + uint16_t u16; + uint32_t u32; } hw_fifo_t; -typedef struct TU_ATTR_PACKED -{ - void *buf; /* the start address of a transfer data buffer */ - uint16_t length; /* the number of bytes in the buffer */ - uint16_t remaining; /* the number of bytes remaining in the buffer */ +typedef struct TU_ATTR_PACKED { + void *buf; /* the start address of a transfer data buffer */ + uint16_t length; /* the number of bytes in the buffer */ + uint16_t remaining; /* the number of bytes remaining in the buffer */ } pipe_state_t; typedef struct { tusb_control_request_t setup_packet; - uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */ - int8_t status_out; + uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */ + int8_t status_out; pipe_state_t pipe0; - pipe_state_t pipe[2][TUP_DCD_ENDPOINT_MAX - 1]; /* pipe[direction][endpoint number - 1] */ - uint16_t pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */ + pipe_state_t pipe[2][TUP_DCD_ENDPOINT_MAX - 1]; /* pipe[direction][endpoint number - 1] */ + uint16_t pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */ } dcd_data_t; /*------------------------------------------------------------------ @@ -80,63 +79,59 @@ typedef struct static dcd_data_t _dcd; -static volatile void* edpt_get_fifo_ptr(unsigned epnum) -{ - volatile uint32_t *ptr; +static volatile void *edpt_get_fifo_ptr(unsigned epnum) { + volatile uint32_t *ptr; - ptr = &MXC_USBHS->fifo0; - ptr += epnum; /* Pointer math: multiplies ep by sizeof(uint32_t) */ + ptr = &MXC_USBHS->fifo0; + ptr += epnum; /* Pointer math: multiplies ep by sizeof(uint32_t) */ - return (volatile void *)ptr; + return (volatile void *) ptr; } -static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) -{ - volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; - uintptr_t addr = (uintptr_t)buf; +static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { + volatile hw_fifo_t *reg = (volatile hw_fifo_t *) fifo; + uintptr_t addr = (uintptr_t) buf; while (len >= 4) { - reg->u32 = *(uint32_t const *)addr; + reg->u32 = *(uint32_t const *) addr; addr += 4; - len -= 4; + len -= 4; } if (len >= 2) { - reg->u16 = *(uint16_t const *)addr; + reg->u16 = *(uint16_t const *) addr; addr += 2; - len -= 2; + len -= 2; } if (len) { - reg->u8 = *(uint8_t const *)addr; + reg->u8 = *(uint8_t const *) addr; } } -static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) -{ - volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; - uintptr_t addr = (uintptr_t)buf; +static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) { + volatile hw_fifo_t *reg = (volatile hw_fifo_t *) fifo; + uintptr_t addr = (uintptr_t) buf; while (len >= 4) { - *(uint32_t *)addr = reg->u32; + *(uint32_t *) addr = reg->u32; addr += 4; - len -= 4; + len -= 4; } if (len >= 2) { - *(uint16_t *)addr = reg->u16; + *(uint16_t *) addr = reg->u16; addr += 2; - len -= 2; + len -= 2; } if (len) { - *(uint8_t *)addr = reg->u8; + *(uint8_t *) addr = reg->u8; } } -static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) -{ +static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) { static const struct { void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info); void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n); void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len); } ops[] = { - /* OUT */ {tu_fifo_get_write_info,tu_fifo_advance_write_pointer,pipe_read_packet}, - /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, + /* OUT */ {tu_fifo_get_write_info, tu_fifo_advance_write_pointer, pipe_read_packet}, + /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, }; tu_fifo_buffer_info_t info; ops[dir].tu_fifo_get_info(f, &info); @@ -152,19 +147,18 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne ops[dir].tu_fifo_advance(f, total_len - rem); } -static void process_setup_packet(uint8_t rhport) -{ - uint32_t *p = (void*)&_dcd.setup_packet; - p[0] = MXC_USBHS->fifo0; - p[1] = MXC_USBHS->fifo0; +static void process_setup_packet(uint8_t rhport) { + uint32_t *p = (void *) &_dcd.setup_packet; + p[0] = MXC_USBHS->fifo0; + p[1] = MXC_USBHS->fifo0; - _dcd.pipe0.buf = NULL; - _dcd.pipe0.length = 0; + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; - dcd_event_setup_received(rhport, (const uint8_t*)(uintptr_t)&_dcd.setup_packet, true); + dcd_event_setup_received(rhport, (const uint8_t *) (uintptr_t) &_dcd.setup_packet, true); - const unsigned len = _dcd.setup_packet.wLength; - _dcd.remaining_ctrl = len; + const unsigned len = _dcd.setup_packet.wLength; + _dcd.remaining_ctrl = len; const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType); /* Clear RX FIFO and reverse the transaction direction */ if (len && dir_in) { @@ -173,12 +167,11 @@ static void process_setup_packet(uint8_t rhport) } } -static bool handle_xfer_in(uint_fast8_t ep_addr) -{ +static bool handle_xfer_in(uint_fast8_t ep_addr) { unsigned epnum = tu_edpt_number(ep_addr); unsigned epnum_minus1 = epnum - 1; - pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; - const unsigned rem = pipe->remaining; + pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; + const unsigned rem = pipe->remaining; //This function should not be for ep0 TU_ASSERT(epnum); @@ -191,28 +184,26 @@ static bool handle_xfer_in(uint_fast8_t ep_addr) MXC_USBHS->index = epnum; const unsigned mps = MXC_USBHS->inmaxp; const unsigned len = TU_MIN(mps, rem); - void *buf = pipe->buf; - volatile void* fifo_ptr = edpt_get_fifo_ptr(epnum); - // TU_LOG1(" %p mps %d len %d rem %d\r\n", buf, mps, len, rem); + void *buf = pipe->buf; + volatile void *fifo_ptr = edpt_get_fifo_ptr(epnum); if (len) { if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) { pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_IN); } else { - pipe_write_packet(buf,fifo_ptr, len); - pipe->buf = buf + len; + pipe_write_packet(buf, fifo_ptr, len); + pipe->buf = buf + len; } pipe->remaining = rem - len; } - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_INPKTRDY; //TODO: Verify a | isnt needed + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_INPKTRDY;//TODO: Verify a | isnt needed return false; } -static bool handle_xfer_out(uint_fast8_t ep_addr) -{ +static bool handle_xfer_out(uint_fast8_t ep_addr) { unsigned epnum = tu_edpt_number(ep_addr); unsigned epnum_minus1 = epnum - 1; - pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; + pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; //This function should not be for ep0 TU_ASSERT(epnum); @@ -225,14 +216,14 @@ static bool handle_xfer_out(uint_fast8_t ep_addr) const unsigned rem = pipe->remaining; const unsigned vld = MXC_USBHS->outcount; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); - void *buf = pipe->buf; - volatile void* fifo_ptr = edpt_get_fifo_ptr(epnum); + void *buf = pipe->buf; + volatile void *fifo_ptr = edpt_get_fifo_ptr(epnum); if (len) { if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) { - pipe_read_write_packet_ff(buf,fifo_ptr, len, TUSB_DIR_OUT); + pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_OUT); } else { pipe_read_packet(buf, fifo_ptr, len); - pipe->buf = buf + len; + pipe->buf = buf + len; } pipe->remaining = rem - len; } @@ -240,37 +231,35 @@ static bool handle_xfer_out(uint_fast8_t ep_addr) pipe->buf = NULL; return NULL != buf; } - MXC_USBHS->outcsrl = 0; /* Clear RXRDY bit */ //TODO: Verify just setting to 0 is ok + MXC_USBHS->outcsrl = 0; /* Clear RXRDY bit *///TODO: Verify just setting to 0 is ok return false; } -static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) -{ - (void)rhport; +static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { + (void) rhport; - unsigned epnum = tu_edpt_number(ep_addr); + unsigned epnum = tu_edpt_number(ep_addr); unsigned epnum_minus1 = epnum - 1; - unsigned dir_in = tu_edpt_dir(ep_addr); + unsigned dir_in = tu_edpt_dir(ep_addr); pipe_state_t *pipe = &_dcd.pipe[dir_in][epnum_minus1]; - pipe->buf = buffer; - pipe->length = total_bytes; - pipe->remaining = total_bytes; + pipe->buf = buffer; + pipe->length = total_bytes; + pipe->remaining = total_bytes; if (dir_in) { handle_xfer_in(ep_addr); } else { MXC_USBHS->index = epnum; - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY){ - MXC_USBHS->outcsrl = 0; //TODO: Verify just setting to 0 is ok + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { + MXC_USBHS->outcsrl = 0;//TODO: Verify just setting to 0 is ok } } return true; } -static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) -{ - (void)rhport; +static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { + (void) rhport; TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */ const unsigned req = _dcd.setup_packet.bmRequestType; @@ -299,15 +288,15 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ TU_ASSERT(total_bytes <= _dcd.remaining_ctrl); const unsigned rem = _dcd.remaining_ctrl; const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes); - volatile void* fifo_ptr = edpt_get_fifo_ptr(0); + volatile void *fifo_ptr = edpt_get_fifo_ptr(0); if (dir_in) { pipe_write_packet(buffer, fifo_ptr, len); - _dcd.pipe0.buf = buffer + len; - _dcd.pipe0.length = len; + _dcd.pipe0.buf = buffer + len; + _dcd.pipe0.length = len; _dcd.pipe0.remaining = 0; - _dcd.remaining_ctrl = rem - len; + _dcd.remaining_ctrl = rem - len; if ((len < 64) || (rem == len)) { _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */ _dcd.status_out = 1; @@ -317,14 +306,14 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_INPKTRDY; /* Flush TX FIFO to return ACK. */ } } else { - _dcd.pipe0.buf = buffer; - _dcd.pipe0.length = len; + _dcd.pipe0.buf = buffer; + _dcd.pipe0.length = len; _dcd.pipe0.remaining = len; MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY; /* Clear RX FIFO to return ACK. */ } } else if (dir_in) { _dcd.pipe0.buf = NULL; - _dcd.pipe0.length = 0; + _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; /* Clear RX FIFO and reverse the transaction direction */ MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY | MXC_F_USBHS_CSR0_DATA_END; @@ -332,8 +321,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ return true; } -static void process_ep0(uint8_t rhport) -{ +static void process_ep0(uint8_t rhport) { MXC_USBHS->index = 0; uint_fast8_t csrl = MXC_USBHS->csr0; @@ -364,7 +352,7 @@ static void process_ep0(uint8_t rhport) /* Received SETUP or DATA OUT packet */ if (req == REQUEST_TYPE_INVALID) { /* SETUP */ - TU_ASSERT(sizeof(tusb_control_request_t) == MXC_USBHS->count0,); + TU_ASSERT(sizeof(tusb_control_request_t) == MXC_USBHS->count0, ); process_setup_packet(rhport); return; } @@ -373,7 +361,7 @@ static void process_ep0(uint8_t rhport) const unsigned vld = MXC_USBHS->count0; const unsigned rem = _dcd.pipe0.remaining; const unsigned len = TU_MIN(TU_MIN(rem, 64), vld); - volatile void* fifo_ptr = edpt_get_fifo_ptr(0); + volatile void *fifo_ptr = edpt_get_fifo_ptr(0); pipe_read_packet(_dcd.pipe0.buf, fifo_ptr, len); _dcd.pipe0.remaining = rem - len; @@ -392,9 +380,9 @@ static void process_ep0(uint8_t rhport) * or receiving a zero length packet. */ if (req != REQUEST_TYPE_INVALID && !tu_edpt_dir(req)) { /* STATUS IN */ - if (*(const uint16_t*)(uintptr_t)&_dcd.setup_packet == 0x0500) { + if (*(const uint16_t *) (uintptr_t) &_dcd.setup_packet == 0x0500) { /* The address must be changed on completion of the control transfer. */ - MXC_USBHS->faddr = (uint8_t)_dcd.setup_packet.wValue; + MXC_USBHS->faddr = (uint8_t) _dcd.setup_packet.wValue; } _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; dcd_event_xfer_complete(rhport, @@ -413,11 +401,10 @@ static void process_ep0(uint8_t rhport) } } -static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) -{ +static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) { bool completed; - const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned epnum = tu_edpt_number(ep_addr); + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned epnum = tu_edpt_number(ep_addr); MXC_USBHS->index = epnum; @@ -443,10 +430,8 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) } } -static void process_bus_reset(uint8_t rhport) -{ - (void)rhport; - TU_LOG0("------Bus Reset\r\n"); +static void process_bus_reset(uint8_t rhport) { + (void) rhport; /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), * a control transfer state is SETUP or STATUS stage. */ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; @@ -462,14 +447,14 @@ static void process_bus_reset(uint8_t rhport) for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { MXC_USBHS->index = i; if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { - /* Per musbhsfc_pg, only flush FIFO if IN packet loaded */ - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_FLUSHFIFO; - } + /* Per musbhsfc_pg, only flush FIFO if IN packet loaded */ + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_FLUSHFIFO; + } - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { - /* Per musbhsfc_pg, only flush FIFO if OUT packet is ready */ - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_FLUSHFIFO; - } + if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { + /* Per musbhsfc_pg, only flush FIFO if OUT packet is ready */ + MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_FLUSHFIFO; + } } dcd_event_bus_reset(0, (MXC_USBHS->power & MXC_F_USBHS_POWER_HS_MODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); } @@ -478,9 +463,8 @@ static void process_bus_reset(uint8_t rhport) * Device API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport) -{ - (void)rhport; +void dcd_init(uint8_t rhport) { + (void) rhport; MXC_USBHS->intrusben |= MXC_F_USBHS_INTRUSBEN_SUSPEND_INT_EN; //Interrupt for VBUS disconnect @@ -495,17 +479,17 @@ void dcd_init(uint8_t rhport) /* Configure PHY */ MXC_USBHS->m31_phy_xcfgi_31_0 = (0x1 << 3) | (0x1 << 11); MXC_USBHS->m31_phy_xcfgi_63_32 = 0; - MXC_USBHS->m31_phy_xcfgi_95_64 = 0x1 << (72-64); + MXC_USBHS->m31_phy_xcfgi_95_64 = 0x1 << (72 - 64); MXC_USBHS->m31_phy_xcfgi_127_96 = 0; -#ifdef USBHS_M31_CLOCK_RECOVERY + #ifdef USBHS_M31_CLOCK_RECOVERY MXC_USBHS->m31_phy_noncry_rstb = 1; MXC_USBHS->m31_phy_noncry_en = 1; MXC_USBHS->m31_phy_outclksel = 0; MXC_USBHS->m31_phy_coreclkin = 0; MXC_USBHS->m31_phy_xtlsel = 2; /* Select 25 MHz clock */ -#else + #else /* Use this option to feed the PHY a 30 MHz clock, which is them used as a PLL reference */ /* As it depends on the system core clock, this should probably be done at the SYS level */ MXC_USBHS->m31_phy_noncry_rstb = 0; @@ -513,7 +497,7 @@ void dcd_init(uint8_t rhport) MXC_USBHS->m31_phy_outclksel = 1; MXC_USBHS->m31_phy_coreclkin = 1; MXC_USBHS->m31_phy_xtlsel = 3; /* Select 30 MHz clock */ -#endif + #endif MXC_USBHS->m31_phy_pll_en = 1; MXC_USBHS->m31_phy_oscouten = 1; @@ -524,25 +508,22 @@ void dcd_init(uint8_t rhport) dcd_connect(rhport); } -void dcd_int_enable(uint8_t rhport) -{ - (void)rhport; +void dcd_int_enable(uint8_t rhport) { + (void) rhport; NVIC_EnableIRQ(USB_IRQn); } -void dcd_int_disable(uint8_t rhport) -{ - (void)rhport; +void dcd_int_disable(uint8_t rhport) { + (void) rhport; NVIC_DisableIRQ(USB_IRQn); } // Receive Set Address request, mcu port must also include status IN response -void dcd_set_address(uint8_t rhport, uint8_t dev_addr) -{ - (void)rhport; - (void)dev_addr; - _dcd.pipe0.buf = NULL; - _dcd.pipe0.length = 0; +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { + (void) rhport; + (void) dev_addr; + _dcd.pipe0.buf = NULL; + _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; /* Clear RX FIFO to return ACK. */ MXC_USBHS->index = 0; @@ -550,37 +531,33 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) } // Wake up host -void dcd_remote_wakeup(uint8_t rhport) -{ - (void)rhport; +void dcd_remote_wakeup(uint8_t rhport) { + (void) rhport; MXC_USBHS->power |= MXC_F_USBHS_POWER_RESUME; -#if CFG_TUSB_OS != OPT_OS_NONE + #if CFG_TUSB_OS != OPT_OS_NONE osal_task_delay(10); -#else + #else MXC_Delay(MXC_DELAY_MSEC(10)); -#endif + #endif MXC_USBHS->power &= ~MXC_F_USBHS_POWER_RESUME; } // Connect by enabling internal pull-up resistor on D+/D- -void dcd_connect(uint8_t rhport) -{ - (void)rhport; +void dcd_connect(uint8_t rhport) { + (void) rhport; MXC_USBHS->power |= TUD_OPT_HIGH_SPEED ? MXC_F_USBHS_POWER_HS_ENABLE : 0; MXC_USBHS->power |= MXC_F_USBHS_POWER_SOFTCONN; } // Disconnect by disabling internal pull-up resistor on D+/D- -void dcd_disconnect(uint8_t rhport) -{ - (void)rhport; +void dcd_disconnect(uint8_t rhport) { + (void) rhport; MXC_USBHS->power &= ~MXC_F_USBHS_POWER_SOFTCONN; } -void dcd_sof_enable(uint8_t rhport, bool en) -{ +void dcd_sof_enable(uint8_t rhport, bool en) { (void) rhport; (void) en; @@ -592,21 +569,20 @@ void dcd_sof_enable(uint8_t rhport, bool en) //--------------------------------------------------------------------+ // Configure endpoint's registers according to descriptor -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) -{ +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) { (void) rhport; const unsigned ep_addr = ep_desc->bEndpointAddress; - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned xfer = ep_desc->bmAttributes.xfer; - const unsigned mps = tu_edpt_packet_size(ep_desc); + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned xfer = ep_desc->bmAttributes.xfer; + const unsigned mps = tu_edpt_packet_size(ep_desc); TU_ASSERT(epn < TUP_DCD_ENDPOINT_MAX); pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1]; - pipe->buf = NULL; - pipe->length = 0; + pipe->buf = NULL; + pipe->length = 0; pipe->remaining = 0; MXC_USBHS->index = epn; @@ -634,8 +610,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) return true; } -void dcd_edpt_close_all(uint8_t rhport) -{ +void dcd_edpt_close_all(uint8_t rhport) { (void) rhport; MXC_SYS_Crit_Enter(); @@ -665,10 +640,9 @@ void dcd_edpt_close_all(uint8_t rhport) MXC_SYS_Crit_Exit(); } -void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) -{ - (void)rhport; - unsigned const epn = tu_edpt_number(ep_addr); +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { + (void) rhport; + unsigned const epn = tu_edpt_number(ep_addr); unsigned const dir_in = tu_edpt_dir(ep_addr); MXC_SYS_Crit_Enter(); @@ -683,7 +657,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; } } else { - MXC_USBHS->introuten &= ~TU_BIT(epn); + MXC_USBHS->introuten &= ~TU_BIT(epn); MXC_USBHS->outmaxp = 0; MXC_USBHS->outcsru = MXC_F_USBHS_OUTCSRU_DPKTBUFDIS; if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { @@ -696,9 +670,8 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) } // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) -{ - (void)rhport; +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { + (void) rhport; bool ret; unsigned const epnum = tu_edpt_number(ep_addr); MXC_SYS_Crit_Enter(); @@ -712,23 +685,21 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t } // Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c -bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) -{ - (void)rhport; +bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes) { + (void) rhport; bool ret; unsigned const epnum = tu_edpt_number(ep_addr); TU_ASSERT(epnum); MXC_SYS_Crit_Enter(); _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] |= TU_BIT(epnum - 1); - ret = edpt_n_xfer(rhport, ep_addr, (uint8_t*)ff, total_bytes); + ret = edpt_n_xfer(rhport, ep_addr, (uint8_t *) ff, total_bytes); MXC_SYS_Crit_Exit(); return ret; } // Stall endpoint -void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) -{ - (void)rhport; +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { + (void) rhport; unsigned const epn = tu_edpt_number(ep_addr); MXC_SYS_Crit_Enter(); MXC_USBHS->index = epn; @@ -742,7 +713,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) if (tu_edpt_dir(ep_addr)) { /* IN */ MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_SENDSTALL; } else { /* OUT */ - TU_ASSERT(!(MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY),); + TU_ASSERT(!(MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY), ); MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_SENDSTALL; } } @@ -750,9 +721,8 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) } // clear stall, data toggle is also reset to DATA0 -void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) -{ - (void)rhport; +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { + (void) rhport; unsigned const epn = tu_edpt_number(ep_addr); MXC_SYS_Crit_Enter(); MXC_USBHS->index = epn; @@ -779,8 +749,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) /*------------------------------------------------------------------- * ISR *-------------------------------------------------------------------*/ -void dcd_int_handler(uint8_t rhport) -{ +void dcd_int_handler(uint8_t rhport) { uint_fast8_t is, txis, rxis; uint32_t mxm_int, mxm_int_en, mxm_is; uint32_t saved_index; @@ -788,7 +757,7 @@ void dcd_int_handler(uint8_t rhport) /* Save current index register */ saved_index = MXC_USBHS->index; - is = MXC_USBHS->intrusb; /* read and clear interrupt status */ + is = MXC_USBHS->intrusb; /* read and clear interrupt status */ txis = MXC_USBHS->intrin; /* read and clear interrupt status */ rxis = MXC_USBHS->introut; /* read and clear interrupt status */ -- cgit v1.3.1 From 2353c4ffbaa50072d89008df7a06a7732c824018 Mon Sep 17 00:00:00 2001 From: Brent Kowal Date: Mon, 1 Jul 2024 17:31:38 -0400 Subject: Add MAX78002 Support -Added support for MAX78002, MAX78002EVKIT -Added provisions for remaining MAX32 USB parts --- examples/device/cdc_msc/src/usb_descriptors.c | 3 +- .../device/cdc_msc_freertos/src/usb_descriptors.c | 3 +- examples/device/cdc_uac2/src/usb_descriptors.c | 3 +- .../dynamic_configuration/src/usb_descriptors.c | 3 +- examples/device/midi_test/src/usb_descriptors.c | 3 +- examples/device/msc_dual_lun/src/usb_descriptors.c | 3 +- .../device/net_lwip_webserver/src/tusb_config.h | 2 +- .../net_lwip_webserver/src/usb_descriptors.c | 3 +- examples/device/uac2_headset/src/usb_descriptors.c | 3 +- .../device/webusb_serial/src/usb_descriptors.c | 3 +- hw/bsp/board_mcu.h | 9 ++ hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h | 149 +++++++++++++++++ hw/bsp/max78002/boards/max78002evkit/board.cmake | 1 + hw/bsp/max78002/boards/max78002evkit/board.h | 58 +++++++ hw/bsp/max78002/boards/max78002evkit/board.mk | 1 + hw/bsp/max78002/family.c | 158 ++++++++++++++++++ hw/bsp/max78002/family.cmake | 152 +++++++++++++++++ hw/bsp/max78002/family.mk | 104 ++++++++++++ hw/bsp/max78002/max78002.ld | 180 +++++++++++++++++++++ src/common/tusb_mcu.h | 3 +- src/portable/analog/max32/dcd_max32.c | 3 +- src/tusb_option.h | 3 + tools/get_deps.py | 2 +- 23 files changed, 839 insertions(+), 13 deletions(-) create mode 100644 hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h create mode 100644 hw/bsp/max78002/boards/max78002evkit/board.cmake create mode 100644 hw/bsp/max78002/boards/max78002evkit/board.h create mode 100644 hw/bsp/max78002/boards/max78002evkit/board.mk create mode 100644 hw/bsp/max78002/family.c create mode 100644 hw/bsp/max78002/family.cmake create mode 100644 hw/bsp/max78002/family.mk create mode 100644 hw/bsp/max78002/max78002.ld (limited to 'src/portable') diff --git a/examples/device/cdc_msc/src/usb_descriptors.c b/examples/device/cdc_msc/src/usb_descriptors.c index 1ca614f4e..fac7cce8f 100644 --- a/examples/device/cdc_msc/src/usb_descriptors.c +++ b/examples/device/cdc_msc/src/usb_descriptors.c @@ -125,7 +125,8 @@ enum { #define EPNUM_MSC_OUT 0x04 #define EPNUM_MSC_IN 0x85 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // MAX32 doesn't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_CDC_NOTIF 0x81 diff --git a/examples/device/cdc_msc_freertos/src/usb_descriptors.c b/examples/device/cdc_msc_freertos/src/usb_descriptors.c index f563e80d3..917b73e10 100644 --- a/examples/device/cdc_msc_freertos/src/usb_descriptors.c +++ b/examples/device/cdc_msc_freertos/src/usb_descriptors.c @@ -106,7 +106,8 @@ enum #define EPNUM_MSC_OUT 0x04 #define EPNUM_MSC_IN 0x85 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // MAX32 doesn't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_CDC_NOTIF 0x81 diff --git a/examples/device/cdc_uac2/src/usb_descriptors.c b/examples/device/cdc_uac2/src/usb_descriptors.c index 43e8cf3d7..ab1a2ee83 100644 --- a/examples/device/cdc_uac2/src/usb_descriptors.c +++ b/examples/device/cdc_uac2/src/usb_descriptors.c @@ -117,7 +117,8 @@ uint8_t const * tud_descriptor_device_cb(void) #define EPNUM_CDC_OUT 0x04 #define EPNUM_CDC_IN 0x85 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // MAX32 doesn't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_AUDIO_IN 0x01 diff --git a/examples/device/dynamic_configuration/src/usb_descriptors.c b/examples/device/dynamic_configuration/src/usb_descriptors.c index eebdd4f69..20f237155 100644 --- a/examples/device/dynamic_configuration/src/usb_descriptors.c +++ b/examples/device/dynamic_configuration/src/usb_descriptors.c @@ -158,7 +158,8 @@ enum #define EPNUM_1_MSC_OUT 0x01 #define EPNUM_1_MSC_IN 0x82 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // FT9XX doesn't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_0_CDC_NOTIF 0x81 diff --git a/examples/device/midi_test/src/usb_descriptors.c b/examples/device/midi_test/src/usb_descriptors.c index 797b50ab2..41e6e1818 100644 --- a/examples/device/midi_test/src/usb_descriptors.c +++ b/examples/device/midi_test/src/usb_descriptors.c @@ -90,7 +90,8 @@ enum // On Bridgetek FT9xx endpoint numbers must be unique... #define EPNUM_MIDI_OUT 0x02 #define EPNUM_MIDI_IN 0x03 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // On MAX32 endpoint numbers must be unique... #define EPNUM_MIDI_OUT 0x02 #define EPNUM_MIDI_IN 0x03 diff --git a/examples/device/msc_dual_lun/src/usb_descriptors.c b/examples/device/msc_dual_lun/src/usb_descriptors.c index e32466228..c55bab0d8 100644 --- a/examples/device/msc_dual_lun/src/usb_descriptors.c +++ b/examples/device/msc_dual_lun/src/usb_descriptors.c @@ -97,7 +97,8 @@ enum #define EPNUM_MSC_OUT 0x01 #define EPNUM_MSC_IN 0x82 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // MAX32 doesn't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_MSC_OUT 0x01 diff --git a/examples/device/net_lwip_webserver/src/tusb_config.h b/examples/device/net_lwip_webserver/src/tusb_config.h index 2f641f33e..22082fc81 100644 --- a/examples/device/net_lwip_webserver/src/tusb_config.h +++ b/examples/device/net_lwip_webserver/src/tusb_config.h @@ -91,7 +91,7 @@ extern "C" { #define USE_ECM 1 #elif TU_CHECK_MCU(OPT_MCU_STM32F0, OPT_MCU_STM32F1) #define USE_ECM 1 -#elif TU_CHECK_MCU(OPT_MCU_MAX32690) +#elif TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX78002) #define USE_ECM 1 #else #define USE_ECM 0 diff --git a/examples/device/net_lwip_webserver/src/usb_descriptors.c b/examples/device/net_lwip_webserver/src/usb_descriptors.c index ba30b869e..012e1bcd8 100644 --- a/examples/device/net_lwip_webserver/src/usb_descriptors.c +++ b/examples/device/net_lwip_webserver/src/usb_descriptors.c @@ -120,7 +120,8 @@ uint8_t const * tud_descriptor_device_cb(void) #define EPNUM_NET_OUT 0x02 #define EPNUM_NET_IN 0x83 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // MAX32 doesn't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_NET_NOTIF 0x81 diff --git a/examples/device/uac2_headset/src/usb_descriptors.c b/examples/device/uac2_headset/src/usb_descriptors.c index bfc8a4ab5..a042ad206 100644 --- a/examples/device/uac2_headset/src/usb_descriptors.c +++ b/examples/device/uac2_headset/src/usb_descriptors.c @@ -104,7 +104,8 @@ uint8_t const * tud_descriptor_device_cb(void) #define EPNUM_AUDIO_OUT 0x02 #define EPNUM_AUDIO_INT 0x03 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // MAX32 doesn't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_AUDIO_IN 0x01 diff --git a/examples/device/webusb_serial/src/usb_descriptors.c b/examples/device/webusb_serial/src/usb_descriptors.c index bcfbe590e..ae1051af6 100644 --- a/examples/device/webusb_serial/src/usb_descriptors.c +++ b/examples/device/webusb_serial/src/usb_descriptors.c @@ -105,7 +105,8 @@ enum #define EPNUM_CDC_OUT 3 #define EPNUM_VENDOR_IN 4 #define EPNUM_VENDOR_OUT 5 -#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 // MAX32 doesn't support a same endpoint number with different direction IN and OUT // e.g EP1 OUT & EP1 IN cannot exist together #define EPNUM_CDC_IN 2 diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index 436164c35..d3a33cf36 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -173,6 +173,15 @@ #elif CFG_TUSB_MCU == OPT_MCU_MAX32690 #include "max32690.h" +#elif CFG_TUSB_MCU == OPT_MCU_MAX32650 + #include "max32650.h" + +#elif CFG_TUSB_MCU == OPT_MCU_MAX32666 + #include "max32665.h" + +#elif CFG_TUSB_MCU == OPT_MCU_MAX78002 + #include "max78002.h" + #else #error "Missing MCU header" #endif diff --git a/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h b/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h new file mode 100644 index 000000000..e5a76af85 --- /dev/null +++ b/hw/bsp/max78002/FreeRTOSConfig/FreeRTOSConfig.h @@ -0,0 +1,149 @@ +/* + * FreeRTOS Kernel V10.0.0 + * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. If you wish to use our Amazon + * FreeRTOS name, please do so in a fair use way that does not cause confusion. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * http://www.FreeRTOS.org + * http://aws.amazon.com/freertos + * + * 1 tab == 4 spaces! + */ + + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +// skip if included from IAR assembler +#ifndef __IASMARM__ + #include "mxc_device.h" +#endif + +/* Cortex M23/M33 port configuration. */ +#define configENABLE_MPU 0 +#define configENABLE_FPU 1 +#define configENABLE_TRUSTZONE 0 +#define configMINIMAL_SECURE_STACK_SIZE (1024) + +#define configUSE_PREEMPTION 1 +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 +#define configCPU_CLOCK_HZ SystemCoreClock +#define configTICK_RATE_HZ ( 1000 ) +#define configMAX_PRIORITIES ( 5 ) +#define configMINIMAL_STACK_SIZE ( 128 ) +#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 ) +#define configMAX_TASK_NAME_LEN 16 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configQUEUE_REGISTRY_SIZE 4 +#define configUSE_QUEUE_SETS 0 +#define configUSE_TIME_SLICING 0 +#define configUSE_NEWLIB_REENTRANT 0 +#define configENABLE_BACKWARD_COMPATIBILITY 1 +#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0 + +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 0 + +/* Hook function related definitions. */ +#define configUSE_IDLE_HOOK 0 +#define configUSE_TICK_HOOK 0 +#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configCHECK_HANDLER_INSTALLATION 0 + +/* Run time and task stats gathering related definitions. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define configRECORD_STACK_HIGH_ADDRESS 1 +#define configUSE_TRACE_FACILITY 1 // legacy trace +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES 2 + +/* Software timer related definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2) +#define configTIMER_QUEUE_LENGTH 32 +#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE + +/* Optional functions - most linkers will remove unused functions anyway. */ +#define INCLUDE_vTaskPrioritySet 0 +#define INCLUDE_uxTaskPriorityGet 0 +#define INCLUDE_vTaskDelete 0 +#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY +#define INCLUDE_xResumeFromISR 0 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTaskGetSchedulerState 0 +#define INCLUDE_xTaskGetCurrentTaskHandle 1 +#define INCLUDE_uxTaskGetStackHighWaterMark 0 +#define INCLUDE_xTaskGetIdleTaskHandle 0 +#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0 +#define INCLUDE_pcTaskGetTaskName 0 +#define INCLUDE_eTaskGetState 0 +#define INCLUDE_xEventGroupSetBitFromISR 0 +#define INCLUDE_xTimerPendFunctionCall 0 + +/* FreeRTOS hooks to NVIC vectors */ +#define xPortPendSVHandler PendSV_Handler +#define xPortSysTickHandler SysTick_Handler +#define vPortSVCHandler SVC_Handler + +//--------------------------------------------------------------------+ +// Interrupt nesting behavior configuration. +//--------------------------------------------------------------------+ + +// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header +#define configPRIO_BITS __NVIC_PRIO_BITS + +/* The lowest interrupt priority that can be used in a call to a "set priority" function. */ +#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<vssel |= UART_VDDIO_BITS; //Set necessary bits to 3.3V + + //USB + MXC_MCR->ldoctrl |= MXC_F_MCR_LDOCTRL_0P9EN; + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_USB); +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) { +#if LED_STATE_ON + state = !state; +#endif + if (state) { + MXC_GPIO_OutClr(LED_PORT, LED_PIN); + } else { + MXC_GPIO_OutSet(LED_PORT, LED_PIN); + } +} + +uint32_t board_button_read(void) { + uint32_t state = MXC_GPIO_InGet(BUTTON_PORT, BUTTON_PIN) ? 1 : 0; + return BUTTON_STATE_ACTIVE == state; +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer + /* All other 2nd parameter is optional checkum buffer */ + MXC_SYS_GetUSN(hw_id, NULL); + + size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); + memcpy(id, hw_id, act_len); + return act_len; +} + +int board_uart_read(uint8_t *buf, int len) { + int uart_val; + int act_len = 0; + + while (act_len < len) { + if ((uart_val = MXC_UART_ReadCharacterRaw(ConsoleUart)) == E_UNDERFLOW) { + break; + } else { + *buf++ = (uint8_t) uart_val; + act_len++; + } + } + return act_len; +} + +int board_uart_write(void const *buf, int len) { + int act_len = 0; + const uint8_t *ch_ptr = (const uint8_t *) buf; + while (act_len < len) { + MXC_UART_WriteCharacter(ConsoleUart, *ch_ptr++); + act_len++; + } + return len; +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) { + system_ticks++; +} + +uint32_t board_millis(void) { + return system_ticks; +} +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { +} diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake new file mode 100644 index 000000000..43b172b9f --- /dev/null +++ b/hw/bsp/max78002/family.cmake @@ -0,0 +1,152 @@ +include_guard() + +set(MAX32_PERIPH ${TOP}/hw/mcu/analog/max32/Libraries/PeriphDrivers) +set(MAX32_CMSIS ${TOP}/hw/mcu/analog/max32/Libraries/CMSIS) +set(CMSIS_5 ${TOP}/lib/CMSIS_5) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# Get the linker file from current location (family) +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/max78002.ld) +set(LD_FILE_Clang ${LD_FILE_GNU}) + +# toolchain set up +set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) +set(JLINK_DEVICE max78000) + +set(FAMILY_MCUS MAX78002 CACHE INTERNAL "") + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + TARGET=MAX78002 + TARGET_REV=0x4131 + MXC_ASSERT_ENABLE + MAX78002 + IAR_PRAGMAS=0 + CFG_TUSB_MCU=OPT_MCU_MAX78002 + BOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + ) +endfunction() + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + #set(STARTUP_FILE_IAR ?) + + set(PERIPH_SRC ${MAX32_PERIPH}/Source) + add_library(${BOARD_TARGET} STATIC + ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/heap.c + ${MAX32_CMSIS}/Device/Maxim/MAX78002/Source/system_max78002.c + ${PERIPH_SRC}/SYS/mxc_assert.c + ${PERIPH_SRC}/SYS/mxc_delay.c + ${PERIPH_SRC}/SYS/mxc_lock.c + ${PERIPH_SRC}/SYS/nvic_table.c + ${PERIPH_SRC}/SYS/pins_ai87.c + ${PERIPH_SRC}/SYS/sys_ai87.c + ${PERIPH_SRC}/AES/aes_ai87.c + ${PERIPH_SRC}/AES/aes_revb.c + ${PERIPH_SRC}/FLC/flc_common.c + ${PERIPH_SRC}/FLC/flc_ai87.c + ${PERIPH_SRC}/FLC/flc_reva.c + ${PERIPH_SRC}/GPIO/gpio_common.c + ${PERIPH_SRC}/GPIO/gpio_ai87.c + ${PERIPH_SRC}/GPIO/gpio_reva.c + ${PERIPH_SRC}/ICC/icc_ai87.c + ${PERIPH_SRC}/ICC/icc_reva.c + ${PERIPH_SRC}/TRNG/trng_ai87.c + ${PERIPH_SRC}/TRNG/trng_revb.c + ${PERIPH_SRC}/UART/uart_common.c + ${PERIPH_SRC}/UART/uart_ai87.c + ${PERIPH_SRC}/UART/uart_revb.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMSIS_5}/CMSIS/Core/Include + ${MAX32_CMSIS}/Include + ${MAX32_CMSIS}/Device/Maxim/MAX78002/Include + ${MAX32_PERIPH}/Include/MAX78002 + ${PERIPH_SRC}/SYS + ${PERIPH_SRC}/GPIO + ${PERIPH_SRC}/AES + ${PERIPH_SRC}/TRNG + ${PERIPH_SRC}/ICC + ${PERIPH_SRC}/FLC + ${PERIPH_SRC}/UART + ) + + target_compile_options(${TARGET} PRIVATE + -Wno-error=strict-prototypes + -Wno-error=redundant-decls + ) + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_MAX78002 ${RTOS}) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/analog/max32/dcd_max32.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + target_compile_options(${TARGET}-tinyusb PRIVATE + -Wno-error=strict-prototypes + -Wno-error=redundant-decls + ) + + # Link dependencies + target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + + # Flashing + family_flash_jlink(${TARGET}) +endfunction() diff --git a/hw/bsp/max78002/family.mk b/hw/bsp/max78002/family.mk new file mode 100644 index 000000000..825920596 --- /dev/null +++ b/hw/bsp/max78002/family.mk @@ -0,0 +1,104 @@ +DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/analog/max32 + +# Important locations in the hw support for MCU +MAX32_CMSIS = hw/mcu/analog/max32/Libraries/CMSIS +MAX32_PERIPH = hw/mcu/analog/max32/Libraries/PeriphDrivers + +# Add any board specific make rules +include $(TOP)/$(BOARD_PATH)/board.mk + +CPU_CORE ?= cortex-m4 +PORT ?= 0 + +# GCC +SRC_S_GCC += $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/GCC/startup_max78002.S +LD_FILE = $(FAMILY_PATH)/max78002.ld + +# IAR +#SRC_S_IAR += + +# -------------- +# Compiler Flags +# -------------- +# Flags for the MAX78002 SDK +CFLAGS += -DTARGET=MAX78002 \ + -DTARGET_REV=0x4131 \ + -DMXC_ASSERT_ENABLE \ + -DMAX78002 \ + -DIAR_PRAGMAS=0 + +# Flags for TUSB features +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_MAX78002 \ + -DBOARD_TUD_MAX_SPEED=OPT_MODE_HIGH_SPEED + +# mcu driver cause following warnings +CFLAGS += -Wno-error=redundant-decls \ + -Wno-error=strict-prototypes \ + -Wno-error=unused-parameter \ + -Wno-error=enum-conversion \ + -Wno-error=sign-compare \ + -Wno-error=cast-qual + +LDFLAGS_GCC += -nostartfiles --specs=nosys.specs --specs=nano.specs + +# For flash-jlink target +JLINK_DEVICE = max78000 + +# flash target using Jlik +flash: flash-jlink + +# Optional flash option when running within an installed MSDK to use OpenOCD +# Mainline OpenOCD does not yet have the MAX32's flash algorithm integrated. +# If the MSDK is installed, flash-msdk can be run to utilize the the modified +# openocd with the algorithms +MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) +flash-msdk: + $(MAXIM_PATH)/Tools/OpenOCD/openocd -s $(MAXIM_PATH)/Tools/OpenOCD/scripts \ + -f interface/cmsis-dap.cfg -f target/max78002.cfg \ + -c "program $(BUILD)/$(PROJECT).elf verify; init; reset; exit" + +# ----------------- +# Sources & Include +# ----------------- +PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source +SRC_C += \ + src/portable/analog/max32/dcd_max32.c \ + $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/heap.c \ + $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/system_max78002.c \ + $(PERIPH_SRC)/SYS/mxc_assert.c \ + $(PERIPH_SRC)/SYS/mxc_delay.c \ + $(PERIPH_SRC)/SYS/mxc_lock.c \ + $(PERIPH_SRC)/SYS/nvic_table.c \ + $(PERIPH_SRC)/SYS/pins_ai87.c \ + $(PERIPH_SRC)/SYS/sys_ai87.c \ + $(PERIPH_SRC)/AES/aes_ai87.c \ + $(PERIPH_SRC)/AES/aes_revb.c \ + $(PERIPH_SRC)/FLC/flc_common.c \ + $(PERIPH_SRC)/FLC/flc_ai87.c \ + $(PERIPH_SRC)/FLC/flc_reva.c \ + $(PERIPH_SRC)/GPIO/gpio_common.c \ + $(PERIPH_SRC)/GPIO/gpio_ai87.c \ + $(PERIPH_SRC)/GPIO/gpio_reva.c \ + $(PERIPH_SRC)/ICC/icc_ai87.c \ + $(PERIPH_SRC)/ICC/icc_reva.c \ + $(PERIPH_SRC)/TRNG/trng_ai87.c \ + $(PERIPH_SRC)/TRNG/trng_revb.c \ + $(PERIPH_SRC)/UART/uart_common.c \ + $(PERIPH_SRC)/UART/uart_ai87.c \ + $(PERIPH_SRC)/UART/uart_revb.c \ + + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(MAX32_CMSIS)/Include \ + $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX78002/Include \ + $(TOP)/$(MAX32_PERIPH)/Include/MAX78002 \ + $(PERIPH_SRC)/SYS \ + $(PERIPH_SRC)/GPIO \ + $(PERIPH_SRC)/AES \ + $(PERIPH_SRC)/ICC \ + $(PERIPH_SRC)/FLC \ + $(PERIPH_SRC)/TRNG \ + $(PERIPH_SRC)/UART diff --git a/hw/bsp/max78002/max78002.ld b/hw/bsp/max78002/max78002.ld new file mode 100644 index 000000000..5f9ed9356 --- /dev/null +++ b/hw/bsp/max78002/max78002.ld @@ -0,0 +1,180 @@ +MEMORY { + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64 kB ROM */ + FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00280000 /* 2.5 MB Flash */ + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00060000 /* 384 kB SRAM */ + /*CSI2 (rwx) : ORIGIN = 0x2001F000, LENGTH = 0x00001000 4096 B CSI2 Buffer */ +} + +SECTIONS { + .rom : + { + KEEP(*(.rom_vector)) + *(.rom_handlers*) + } > ROM + + .text : + { + _text = .; + KEEP(*(.isr_vector)) + EXCLUDE_FILE (*riscv.o) *(.text*) /* Program code (exclude RISCV code) */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + /* Binary import */ + .bin_storage : + { + FILL(0xFF) + _bin_start_ = .; + KEEP(*(.bin_storage_img)) + _bin_end_ = .; + . = ALIGN(4); + } > FLASH + + .rom_code : + { + . = ALIGN(16); + _sran_code = .; + *(.rom_code_section) + _esran_code = .; + } > ROM + + .flash_code : + { + . = ALIGN(16); + _sran_code = .; + *(.flash_code_section) + _esran_code = .; + } > FLASH + + .sram_code : + { + . = ALIGN(16); + _sran_code = .; + *(.sram_code_section) + _esran_code = .; + } > SRAM + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + _csi = . + 0x20000; + *(vtable) + *(.data*) /*read-write initialized data: initialized global variable*/ + + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + .shared : + { + . = ALIGN(4); + _shared = .; + *(.mailbox*) + . = ALIGN(4); + *(.shared*) /*read-write zero initialized data: uninitialzed global variable*/ + _eshared = ALIGN(., 4); + } > SRAM + __shared_data = LOADADDR(.shared); + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") + + /* Section used by RISCV loader projects. See RISCV_LOAD documentation in the build system. */ + .riscv_flash : + { + /* Align address to mod 256 with a small offset. This is required to match the flash page size.*/ + . = ALIGN(256); /* ALIGN operatator is used here. Note that (. & 0x1FFFFF00) was used in the past, but a strange bug was seen on Windows where the & did not behave as expected.*/ + . += 0x100; + _riscv_boot = .; + KEEP(*riscv.o (.text*)) + } > FLASH +} diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index a68e160bd..07cdf3ff0 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -455,7 +455,8 @@ //--------------------------------------------------------------------+ // Analog Devices //--------------------------------------------------------------------+ -#elif TU_CHECK_MCU(OPT_MCU_MAX32690) +#elif TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32666, \ + OPT_MCU_MAX32650, OPT_MCU_MAX78002) #define TUP_DCD_ENDPOINT_MAX 12 #define TUP_RHPORT_HIGHSPEED 1 diff --git a/src/portable/analog/max32/dcd_max32.c b/src/portable/analog/max32/dcd_max32.c index b3370ddd1..7226003de 100644 --- a/src/portable/analog/max32/dcd_max32.c +++ b/src/portable/analog/max32/dcd_max32.c @@ -27,7 +27,8 @@ #include "tusb_option.h" -#if CFG_TUD_ENABLED && TU_CHECK_MCU(OPT_MCU_MAX32690) +#if CFG_TUD_ENABLED && \ + TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX78002) #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) /* GCC warns that an address may be unaligned, even though diff --git a/src/tusb_option.h b/src/tusb_option.h index 18f78b49c..1290d605c 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -190,6 +190,9 @@ // Analog Devices #define OPT_MCU_MAX32690 2400 ///< ADI MAX32690 +#define OPT_MCU_MAX32666 2401 ///< ADI MAX32666/5 +#define OPT_MCU_MAX32650 2402 ///< ADI MAX32650/1/2 +#define OPT_MCU_MAX78002 2403 ///< ADI MAX78002 // Check if configured MCU is one of listed // Apply _TU_CHECK_MCU with || as separator to list of input diff --git a/tools/get_deps.py b/tools/get_deps.py index e05cc4d76..fe548f4ab 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -26,7 +26,7 @@ deps_optional = { 'fc100s'], 'hw/mcu/analog/max32' : ['https://github.com/analogdevicesinc/msdk.git', 'b20b398d3e5e2007594e54a74ba3d2a2e50ddd75', - 'max32690'], + 'max32690 max32650 max32666 max78002'], 'hw/mcu/bridgetek/ft9xx/ft90x-sdk': ['https://github.com/BRTSG-FOSS/ft90x-sdk.git', '91060164afe239fcb394122e8bf9eb24d3194eb1', 'brtmm90x'], -- cgit v1.3.1 From 13f5f20c981cc54baa8438e275524db03fb79e94 Mon Sep 17 00:00:00 2001 From: Brent Kowal Date: Thu, 11 Jul 2024 12:13:30 -0400 Subject: Pre-commit fixes. Resolve codespell and EOF errors found in the pre-commit CI task. --- hw/bsp/max32650/README.md | 2 +- hw/bsp/max32650/boards/max32650evkit/max32650.ld | 2 +- hw/bsp/max32650/boards/max32650fthr/max32650.ld | 2 +- hw/bsp/max32650/boards/max32651evkit/max32651.ld | 2 +- hw/bsp/max32650/family.mk | 2 +- hw/bsp/max32666/family.c | 2 +- hw/bsp/max32666/max32666.ld | 2 +- hw/bsp/max32690/family.c | 2 +- hw/bsp/max32690/max32690.ld | 2 +- hw/bsp/max78002/family.c | 2 +- hw/bsp/max78002/max78002.ld | 4 ++-- src/portable/analog/max32/dcd_max32.c | 2 +- 12 files changed, 13 insertions(+), 13 deletions(-) (limited to 'src/portable') diff --git a/hw/bsp/max32650/README.md b/hw/bsp/max32650/README.md index cb8069bba..ca66a1ac4 100644 --- a/hw/bsp/max32650/README.md +++ b/hw/bsp/max32650/README.md @@ -43,4 +43,4 @@ MAX32651EVKIT. To flash the signed image, the MSDK's OpenOCD variant must be used. To flash the MAX32651EVKIT please install the bundled MSDK, and utilize the `flash-msdk` -and `-msdk` rule and target. \ No newline at end of file +and `-msdk` rule and target. diff --git a/hw/bsp/max32650/boards/max32650evkit/max32650.ld b/hw/bsp/max32650/boards/max32650evkit/max32650.ld index 3a1e5100d..0e56a91ec 100644 --- a/hw/bsp/max32650/boards/max32650evkit/max32650.ld +++ b/hw/bsp/max32650/boards/max32650evkit/max32650.ld @@ -85,7 +85,7 @@ SECTIONS { { . = ALIGN(4); _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ *(COMMON) _ebss = ALIGN(., 4); } > SRAM diff --git a/hw/bsp/max32650/boards/max32650fthr/max32650.ld b/hw/bsp/max32650/boards/max32650fthr/max32650.ld index 3a1e5100d..0e56a91ec 100644 --- a/hw/bsp/max32650/boards/max32650fthr/max32650.ld +++ b/hw/bsp/max32650/boards/max32650fthr/max32650.ld @@ -85,7 +85,7 @@ SECTIONS { { . = ALIGN(4); _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ *(COMMON) _ebss = ALIGN(., 4); } > SRAM diff --git a/hw/bsp/max32650/boards/max32651evkit/max32651.ld b/hw/bsp/max32650/boards/max32651evkit/max32651.ld index a873463d4..3921d10f2 100644 --- a/hw/bsp/max32650/boards/max32651evkit/max32651.ld +++ b/hw/bsp/max32650/boards/max32651evkit/max32651.ld @@ -98,7 +98,7 @@ SECTIONS { { . = ALIGN(4); _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ *(COMMON) _ebss = ALIGN(., 4); } > SRAM diff --git a/hw/bsp/max32650/family.mk b/hw/bsp/max32650/family.mk index 577d96717..0718523c3 100644 --- a/hw/bsp/max32650/family.mk +++ b/hw/bsp/max32650/family.mk @@ -121,7 +121,7 @@ SIGN_EXE := sign_app.exe endif endif -# Rule to sign the build. This will in-place modifiy the existing .elf file +# Rule to sign the build. This will in-place modify the existing .elf file # an populate the .sig section with the signature value sign-build: $(BUILD)/$(PROJECT).elf $(OBJCOPY) $(BUILD)/$(PROJECT).elf -R .sig -O binary $(BUILD)/$(PROJECT).bin diff --git a/hw/bsp/max32666/family.c b/hw/bsp/max32666/family.c index 98e1248d7..1398e09ff 100644 --- a/hw/bsp/max32666/family.c +++ b/hw/bsp/max32666/family.c @@ -106,7 +106,7 @@ uint32_t board_button_read(void) { size_t board_get_unique_id(uint8_t id[], size_t max_len) { uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer - /* All other 2nd parameter is optional checkum buffer */ + /* All other 2nd parameter is optional checksum buffer */ MXC_SYS_GetUSN(hw_id, NULL); size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); diff --git a/hw/bsp/max32666/max32666.ld b/hw/bsp/max32666/max32666.ld index dcf61a3d0..06c124247 100644 --- a/hw/bsp/max32666/max32666.ld +++ b/hw/bsp/max32666/max32666.ld @@ -101,7 +101,7 @@ SECTIONS { { . = ALIGN(4); _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ *(COMMON) _ebss = ALIGN(., 4); } > SRAM diff --git a/hw/bsp/max32690/family.c b/hw/bsp/max32690/family.c index acd6e2593..f4998bdbe 100644 --- a/hw/bsp/max32690/family.c +++ b/hw/bsp/max32690/family.c @@ -104,7 +104,7 @@ uint32_t board_button_read(void) { size_t board_get_unique_id(uint8_t id[], size_t max_len) { uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer - /* All other 2nd parameter is optional checkum buffer */ + /* All other 2nd parameter is optional checksum buffer */ MXC_SYS_GetUSN(hw_id, NULL); size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); diff --git a/hw/bsp/max32690/max32690.ld b/hw/bsp/max32690/max32690.ld index 3d857b4e8..64b906a54 100644 --- a/hw/bsp/max32690/max32690.ld +++ b/hw/bsp/max32690/max32690.ld @@ -130,7 +130,7 @@ SECTIONS { { . = ALIGN(4); _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ *(COMMON) _ebss = ALIGN(., 4); } > SRAM diff --git a/hw/bsp/max78002/family.c b/hw/bsp/max78002/family.c index c105f056b..7758083a2 100644 --- a/hw/bsp/max78002/family.c +++ b/hw/bsp/max78002/family.c @@ -103,7 +103,7 @@ uint32_t board_button_read(void) { size_t board_get_unique_id(uint8_t id[], size_t max_len) { uint8_t hw_id[MXC_SYS_USN_CHECKSUM_LEN];//USN Buffer - /* All other 2nd parameter is optional checkum buffer */ + /* All other 2nd parameter is optional checksum buffer */ MXC_SYS_GetUSN(hw_id, NULL); size_t act_len = TU_MIN(max_len, MXC_SYS_USN_LEN); diff --git a/hw/bsp/max78002/max78002.ld b/hw/bsp/max78002/max78002.ld index 60f99e28f..e5c4866ee 100644 --- a/hw/bsp/max78002/max78002.ld +++ b/hw/bsp/max78002/max78002.ld @@ -127,7 +127,7 @@ SECTIONS { { . = ALIGN(4); _bss = .; - *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(.bss*) /*read-write zero initialized data: uninitialized global variable*/ *(COMMON) _ebss = ALIGN(., 4); } > SRAM @@ -138,7 +138,7 @@ SECTIONS { _shared = .; *(.mailbox*) . = ALIGN(4); - *(.shared*) /*read-write zero initialized data: uninitialzed global variable*/ + *(.shared*) /*read-write zero initialized data: uninitialized global variable*/ _eshared = ALIGN(., 4); } > SRAM __shared_data = LOADADDR(.shared); diff --git a/src/portable/analog/max32/dcd_max32.c b/src/portable/analog/max32/dcd_max32.c index 7226003de..df616120a 100644 --- a/src/portable/analog/max32/dcd_max32.c +++ b/src/portable/analog/max32/dcd_max32.c @@ -196,7 +196,7 @@ static bool handle_xfer_in(uint_fast8_t ep_addr) { } pipe->remaining = rem - len; } - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_INPKTRDY;//TODO: Verify a | isnt needed + MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_INPKTRDY;//TODO: Verify a | isn't needed return false; } -- cgit v1.3.1 From 5122d6d109f8c4b31b6cbe29c685fad30a8961fe Mon Sep 17 00:00:00 2001 From: Brent Kowal Date: Thu, 25 Jul 2024 09:08:37 -0400 Subject: Combined DCD MUSB implementations Combined the new MAX32 MUSB implementation with the existing (TI) implementation to provide generic code base for working the MUSB DCD peripheral. - Added abstraction calls for FIFO setup, EP registers, Ctrl registers and interrupt setup. - Combined TM4C and MSP432E into a single header file. - Created musb_max32.h, and removed the MAX32 specific C implementation. - Updated MAX32 build system to use dcd_musb.c. - Added MAX32 conditions for cdc_dual_ports example descriptors missed during first testing. --- .../device/cdc_dual_ports/src/usb_descriptors.c | 12 + hw/bsp/max32650/family.cmake | 2 +- hw/bsp/max32650/family.mk | 2 +- hw/bsp/max32666/family.cmake | 2 +- hw/bsp/max32666/family.mk | 2 +- hw/bsp/max32690/family.cmake | 2 +- hw/bsp/max32690/family.mk | 2 +- hw/bsp/max78002/family.cmake | 2 +- hw/bsp/max78002/family.mk | 2 +- src/portable/analog/max32/dcd_max32.c | 811 --------------------- src/portable/mentor/musb/dcd_musb.c | 436 ++++------- src/portable/mentor/musb/hcd_musb.c | 12 +- src/portable/mentor/musb/musb_max32.h | 221 ++++++ src/portable/mentor/musb/musb_msp432e.h | 40 - src/portable/mentor/musb/musb_ti.h | 285 ++++++++ src/portable/mentor/musb/musb_tm4c.h | 45 -- src/portable/mentor/musb/musb_type.h | 33 + 17 files changed, 711 insertions(+), 1200 deletions(-) delete mode 100644 src/portable/analog/max32/dcd_max32.c create mode 100644 src/portable/mentor/musb/musb_max32.h delete mode 100644 src/portable/mentor/musb/musb_msp432e.h create mode 100644 src/portable/mentor/musb/musb_ti.h delete mode 100644 src/portable/mentor/musb/musb_tm4c.h (limited to 'src/portable') diff --git a/examples/device/cdc_dual_ports/src/usb_descriptors.c b/examples/device/cdc_dual_ports/src/usb_descriptors.c index de2505c07..808d78411 100644 --- a/examples/device/cdc_dual_ports/src/usb_descriptors.c +++ b/examples/device/cdc_dual_ports/src/usb_descriptors.c @@ -120,6 +120,18 @@ enum #define EPNUM_CDC_1_OUT 0x05 #define EPNUM_CDC_1_IN 0x86 +#elif CFG_TUSB_MCU == OPT_MCU_MAX32690 || CFG_TUSB_MCU == OPT_MCU_MAX32650 || \ + CFG_TUSB_MCU == OPT_MCU_MAX32666 || CFG_TUSB_MCU == OPT_MCU_MAX78002 + // MAX32 doesn't support a same endpoint number with different direction IN and OUT + // e.g EP1 OUT & EP1 IN cannot exist together + #define EPNUM_CDC_0_NOTIF 0x81 + #define EPNUM_CDC_0_OUT 0x02 + #define EPNUM_CDC_0_IN 0x83 + + #define EPNUM_CDC_1_NOTIF 0x84 + #define EPNUM_CDC_1_OUT 0x05 + #define EPNUM_CDC_1_IN 0x86 + #else #define EPNUM_CDC_0_NOTIF 0x81 #define EPNUM_CDC_0_OUT 0x02 diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake index 129d99af8..92b68a1cd 100644 --- a/hw/bsp/max32650/family.cmake +++ b/hw/bsp/max32650/family.cmake @@ -132,7 +132,7 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MAX32650 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/analog/max32/dcd_max32.c + ${TOP}/src/portable/mentor/musb/dcd_musb.c ) target_compile_options(${TARGET} PRIVATE -Wno-error=strict-prototypes diff --git a/hw/bsp/max32650/family.mk b/hw/bsp/max32650/family.mk index 0718523c3..359261216 100644 --- a/hw/bsp/max32650/family.mk +++ b/hw/bsp/max32650/family.mk @@ -62,7 +62,7 @@ flash: $(DEFAULT_FLASH) # ----------------- PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source SRC_C += \ - src/portable/analog/max32/dcd_max32.c \ + src/portable/mentor/musb/dcd_musb.c \ $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/heap.c \ $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/system_max32650.c \ $(MAX32_CMSIS)/Device/Maxim/MAX32650/Source/header_MAX32650.c \ diff --git a/hw/bsp/max32666/family.cmake b/hw/bsp/max32666/family.cmake index ef2a2bb63..eb9d2175f 100644 --- a/hw/bsp/max32666/family.cmake +++ b/hw/bsp/max32666/family.cmake @@ -127,7 +127,7 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MAX32666 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/analog/max32/dcd_max32.c + ${TOP}/src/portable/mentor/musb/dcd_musb.c ) target_compile_options(${TARGET} PRIVATE -Wno-error=strict-prototypes diff --git a/hw/bsp/max32666/family.mk b/hw/bsp/max32666/family.mk index 31f81f014..720d994ef 100644 --- a/hw/bsp/max32666/family.mk +++ b/hw/bsp/max32666/family.mk @@ -57,7 +57,7 @@ flash-msdk: $(BUILD)/$(PROJECT).elf # ----------------- PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source SRC_C += \ - src/portable/analog/max32/dcd_max32.c \ + src/portable/mentor/musb/dcd_musb.c \ $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/heap.c \ $(MAX32_CMSIS)/Device/Maxim/MAX32665/Source/system_max32665.c \ $(PERIPH_SRC)/SYS/mxc_assert.c \ diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake index d7a562956..2a9422dbe 100644 --- a/hw/bsp/max32690/family.cmake +++ b/hw/bsp/max32690/family.cmake @@ -132,7 +132,7 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MAX32690 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/analog/max32/dcd_max32.c + ${TOP}/src/portable/mentor/musb/dcd_musb.c ) target_compile_options(${TARGET} PRIVATE -Wno-error=strict-prototypes diff --git a/hw/bsp/max32690/family.mk b/hw/bsp/max32690/family.mk index 9360a07c6..c533cf4a4 100644 --- a/hw/bsp/max32690/family.mk +++ b/hw/bsp/max32690/family.mk @@ -64,7 +64,7 @@ flash-msdk: $(BUILD)/$(PROJECT).elf # ----------------- PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source SRC_C += \ - src/portable/analog/max32/dcd_max32.c \ + src/portable/mentor/musb/dcd_musb.c \ $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/heap.c \ $(MAX32_CMSIS)/Device/Maxim/MAX32690/Source/system_max32690.c \ $(PERIPH_SRC)/SYS/mxc_assert.c \ diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake index 83fd3007f..090f1da43 100644 --- a/hw/bsp/max78002/family.cmake +++ b/hw/bsp/max78002/family.cmake @@ -137,7 +137,7 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_MAX78002 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/analog/max32/dcd_max32.c + ${TOP}/src/portable/mentor/musb/dcd_musb.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) target_compile_options(${TARGET}-tinyusb PRIVATE diff --git a/hw/bsp/max78002/family.mk b/hw/bsp/max78002/family.mk index 8df8517da..5297815de 100644 --- a/hw/bsp/max78002/family.mk +++ b/hw/bsp/max78002/family.mk @@ -60,7 +60,7 @@ flash-msdk: $(BUILD)/$(PROJECT).elf # ----------------- PERIPH_SRC = $(TOP)/$(MAX32_PERIPH)/Source SRC_C += \ - src/portable/analog/max32/dcd_max32.c \ + src/portable/mentor/musb/dcd_musb.c \ $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/heap.c \ $(MAX32_CMSIS)/Device/Maxim/MAX78002/Source/system_max78002.c \ $(PERIPH_SRC)/SYS/mxc_assert.c \ diff --git a/src/portable/analog/max32/dcd_max32.c b/src/portable/analog/max32/dcd_max32.c deleted file mode 100644 index df616120a..000000000 --- a/src/portable/analog/max32/dcd_max32.c +++ /dev/null @@ -1,811 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2021 Koji KITAYAMA - * Copyright (c) 2024 Brent Kowal (Analog Devices, Inc) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" - -#if CFG_TUD_ENABLED && \ - TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX78002) - - #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) -/* GCC warns that an address may be unaligned, even though - * the target CPU has the capability for unaligned memory access. */ -_Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); - #endif - - #include "device/dcd.h" - - #include "mxc_delay.h" - #include "mxc_device.h" - #include "mxc_sys.h" - #include "nvic_table.h" - #include "usbhs_regs.h" - - #define USBHS_M31_CLOCK_RECOVERY - - /*------------------------------------------------------------------ - * MACRO TYPEDEF CONSTANT ENUM DECLARATION - *------------------------------------------------------------------*/ - #define REQUEST_TYPE_INVALID (0xFFu) - - -typedef union { - uint8_t u8; - uint16_t u16; - uint32_t u32; -} hw_fifo_t; - -typedef struct TU_ATTR_PACKED { - void *buf; /* the start address of a transfer data buffer */ - uint16_t length; /* the number of bytes in the buffer */ - uint16_t remaining; /* the number of bytes remaining in the buffer */ -} pipe_state_t; - -typedef struct -{ - tusb_control_request_t setup_packet; - uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */ - int8_t status_out; - pipe_state_t pipe0; - pipe_state_t pipe[2][TUP_DCD_ENDPOINT_MAX - 1]; /* pipe[direction][endpoint number - 1] */ - uint16_t pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */ -} dcd_data_t; - -/*------------------------------------------------------------------ - * INTERNAL OBJECT & FUNCTION DECLARATION - *------------------------------------------------------------------*/ -static dcd_data_t _dcd; - - -static volatile void *edpt_get_fifo_ptr(unsigned epnum) { - volatile uint32_t *ptr; - - ptr = &MXC_USBHS->fifo0; - ptr += epnum; /* Pointer math: multiplies ep by sizeof(uint32_t) */ - - return (volatile void *) ptr; -} - -static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { - volatile hw_fifo_t *reg = (volatile hw_fifo_t *) fifo; - uintptr_t addr = (uintptr_t) buf; - while (len >= 4) { - reg->u32 = *(uint32_t const *) addr; - addr += 4; - len -= 4; - } - if (len >= 2) { - reg->u16 = *(uint16_t const *) addr; - addr += 2; - len -= 2; - } - if (len) { - reg->u8 = *(uint8_t const *) addr; - } -} - -static void pipe_read_packet(void *buf, volatile void *fifo, unsigned len) { - volatile hw_fifo_t *reg = (volatile hw_fifo_t *) fifo; - uintptr_t addr = (uintptr_t) buf; - while (len >= 4) { - *(uint32_t *) addr = reg->u32; - addr += 4; - len -= 4; - } - if (len >= 2) { - *(uint16_t *) addr = reg->u16; - addr += 2; - len -= 2; - } - if (len) { - *(uint8_t *) addr = reg->u8; - } -} - -static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigned len, unsigned dir) { - static const struct { - void (*tu_fifo_get_info)(tu_fifo_t *f, tu_fifo_buffer_info_t *info); - void (*tu_fifo_advance)(tu_fifo_t *f, uint16_t n); - void (*pipe_read_write)(void *buf, volatile void *fifo, unsigned len); - } ops[] = { - /* OUT */ {tu_fifo_get_write_info, tu_fifo_advance_write_pointer, pipe_read_packet}, - /* IN */ {tu_fifo_get_read_info, tu_fifo_advance_read_pointer, pipe_write_packet}, - }; - tu_fifo_buffer_info_t info; - ops[dir].tu_fifo_get_info(f, &info); - unsigned total_len = len; - len = TU_MIN(total_len, info.len_lin); - ops[dir].pipe_read_write(info.ptr_lin, fifo, len); - unsigned rem = total_len - len; - if (rem) { - len = TU_MIN(rem, info.len_wrap); - ops[dir].pipe_read_write(info.ptr_wrap, fifo, len); - rem -= len; - } - ops[dir].tu_fifo_advance(f, total_len - rem); -} - -static void process_setup_packet(uint8_t rhport) { - uint32_t *p = (void *) &_dcd.setup_packet; - p[0] = MXC_USBHS->fifo0; - p[1] = MXC_USBHS->fifo0; - - _dcd.pipe0.buf = NULL; - _dcd.pipe0.length = 0; - _dcd.pipe0.remaining = 0; - dcd_event_setup_received(rhport, (const uint8_t *) (uintptr_t) &_dcd.setup_packet, true); - - const unsigned len = _dcd.setup_packet.wLength; - _dcd.remaining_ctrl = len; - const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType); - /* Clear RX FIFO and reverse the transaction direction */ - if (len && dir_in) { - MXC_USBHS->index = 0; - MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY; - } -} - -static bool handle_xfer_in(uint_fast8_t ep_addr) { - unsigned epnum = tu_edpt_number(ep_addr); - unsigned epnum_minus1 = epnum - 1; - pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; - const unsigned rem = pipe->remaining; - - //This function should not be for ep0 - TU_ASSERT(epnum); - - if (!rem) { - pipe->buf = NULL; - return true; - } - - MXC_USBHS->index = epnum; - const unsigned mps = MXC_USBHS->inmaxp; - const unsigned len = TU_MIN(mps, rem); - void *buf = pipe->buf; - volatile void *fifo_ptr = edpt_get_fifo_ptr(epnum); - if (len) { - if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) { - pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_IN); - } else { - pipe_write_packet(buf, fifo_ptr, len); - pipe->buf = buf + len; - } - pipe->remaining = rem - len; - } - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_INPKTRDY;//TODO: Verify a | isn't needed - - return false; -} - -static bool handle_xfer_out(uint_fast8_t ep_addr) { - unsigned epnum = tu_edpt_number(ep_addr); - unsigned epnum_minus1 = epnum - 1; - pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; - - //This function should not be for ep0 - TU_ASSERT(epnum); - - MXC_USBHS->index = epnum; - - TU_ASSERT(MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY); - - const unsigned mps = MXC_USBHS->outmaxp; - const unsigned rem = pipe->remaining; - const unsigned vld = MXC_USBHS->outcount; - const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); - void *buf = pipe->buf; - volatile void *fifo_ptr = edpt_get_fifo_ptr(epnum); - if (len) { - if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) { - pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_OUT); - } else { - pipe_read_packet(buf, fifo_ptr, len); - pipe->buf = buf + len; - } - pipe->remaining = rem - len; - } - if ((len < mps) || (rem == len)) { - pipe->buf = NULL; - return NULL != buf; - } - MXC_USBHS->outcsrl = 0; /* Clear RXRDY bit *///TODO: Verify just setting to 0 is ok - return false; -} - -static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - (void) rhport; - - unsigned epnum = tu_edpt_number(ep_addr); - unsigned epnum_minus1 = epnum - 1; - unsigned dir_in = tu_edpt_dir(ep_addr); - - pipe_state_t *pipe = &_dcd.pipe[dir_in][epnum_minus1]; - pipe->buf = buffer; - pipe->length = total_bytes; - pipe->remaining = total_bytes; - - if (dir_in) { - handle_xfer_in(ep_addr); - } else { - MXC_USBHS->index = epnum; - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { - MXC_USBHS->outcsrl = 0;//TODO: Verify just setting to 0 is ok - } - } - return true; -} - -static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - (void) rhport; - TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */ - - const unsigned req = _dcd.setup_packet.bmRequestType; - TU_ASSERT(req != REQUEST_TYPE_INVALID || total_bytes == 0); - - if (req == REQUEST_TYPE_INVALID || _dcd.status_out) { - /* STATUS OUT stage. - * MUSB controller automatically handles STATUS OUT packets without - * software helps. We do not have to do anything. And STATUS stage - * may have already finished and received the next setup packet - * without calling this function, so we have no choice but to - * invoke the callback function of status packet here. */ - _dcd.status_out = 0; - if (req == REQUEST_TYPE_INVALID) { - dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false); - } else { - /* The next setup packet has already been received, it aborts - * invoking callback function to avoid confusing TUSB stack. */ - TU_LOG1("Drop CONTROL_STAGE_ACK\r\n"); - } - return true; - } - const unsigned dir_in = tu_edpt_dir(ep_addr); - MXC_USBHS->index = 0; - if (tu_edpt_dir(req) == dir_in) { /* DATA stage */ - TU_ASSERT(total_bytes <= _dcd.remaining_ctrl); - const unsigned rem = _dcd.remaining_ctrl; - const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes); - volatile void *fifo_ptr = edpt_get_fifo_ptr(0); - if (dir_in) { - pipe_write_packet(buffer, fifo_ptr, len); - - _dcd.pipe0.buf = buffer + len; - _dcd.pipe0.length = len; - _dcd.pipe0.remaining = 0; - - _dcd.remaining_ctrl = rem - len; - if ((len < 64) || (rem == len)) { - _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */ - _dcd.status_out = 1; - /* Flush TX FIFO and reverse the transaction direction. */ - MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_INPKTRDY | MXC_F_USBHS_CSR0_DATA_END; - } else { - MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_INPKTRDY; /* Flush TX FIFO to return ACK. */ - } - } else { - _dcd.pipe0.buf = buffer; - _dcd.pipe0.length = len; - _dcd.pipe0.remaining = len; - MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY; /* Clear RX FIFO to return ACK. */ - } - } else if (dir_in) { - _dcd.pipe0.buf = NULL; - _dcd.pipe0.length = 0; - _dcd.pipe0.remaining = 0; - /* Clear RX FIFO and reverse the transaction direction */ - MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY | MXC_F_USBHS_CSR0_DATA_END; - } - return true; -} - -static void process_ep0(uint8_t rhport) { - MXC_USBHS->index = 0; - uint_fast8_t csrl = MXC_USBHS->csr0; - - if (csrl & MXC_F_USBHS_CSR0_SENT_STALL) { - /* Returned STALL packet to HOST. */ - MXC_USBHS->csr0 = 0; /* Clear STALL */ - return; - } - - unsigned req = _dcd.setup_packet.bmRequestType; - if (csrl & MXC_F_USBHS_CSR0_SETUP_END) { - TU_LOG1(" ABORT by the next packets\r\n"); - MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_SETUP_END; - if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) { - /* DATA stage was aborted by receiving STATUS or SETUP packet. */ - _dcd.pipe0.buf = NULL; - _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; - dcd_event_xfer_complete(rhport, - req & TUSB_DIR_IN_MASK, - _dcd.pipe0.length - _dcd.pipe0.remaining, - XFER_RESULT_SUCCESS, true); - } - req = REQUEST_TYPE_INVALID; - if (!(csrl & MXC_F_USBHS_CSR0_OUTPKTRDY)) return; /* Received SETUP packet */ - } - - if (csrl & MXC_F_USBHS_CSR0_OUTPKTRDY) { - /* Received SETUP or DATA OUT packet */ - if (req == REQUEST_TYPE_INVALID) { - /* SETUP */ - TU_ASSERT(sizeof(tusb_control_request_t) == MXC_USBHS->count0, ); - process_setup_packet(rhport); - return; - } - if (_dcd.pipe0.buf) { - /* DATA OUT */ - const unsigned vld = MXC_USBHS->count0; - const unsigned rem = _dcd.pipe0.remaining; - const unsigned len = TU_MIN(TU_MIN(rem, 64), vld); - volatile void *fifo_ptr = edpt_get_fifo_ptr(0); - pipe_read_packet(_dcd.pipe0.buf, fifo_ptr, len); - - _dcd.pipe0.remaining = rem - len; - _dcd.remaining_ctrl -= len; - - _dcd.pipe0.buf = NULL; - dcd_event_xfer_complete(rhport, - tu_edpt_addr(0, TUSB_DIR_OUT), - _dcd.pipe0.length - _dcd.pipe0.remaining, - XFER_RESULT_SUCCESS, true); - } - return; - } - - /* When CSRL0 is zero, it means that completion of sending a any length packet - * or receiving a zero length packet. */ - if (req != REQUEST_TYPE_INVALID && !tu_edpt_dir(req)) { - /* STATUS IN */ - if (*(const uint16_t *) (uintptr_t) &_dcd.setup_packet == 0x0500) { - /* The address must be changed on completion of the control transfer. */ - MXC_USBHS->faddr = (uint8_t) _dcd.setup_packet.wValue; - } - _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; - dcd_event_xfer_complete(rhport, - tu_edpt_addr(0, TUSB_DIR_IN), - _dcd.pipe0.length - _dcd.pipe0.remaining, - XFER_RESULT_SUCCESS, true); - return; - } - if (_dcd.pipe0.buf) { - /* DATA IN */ - _dcd.pipe0.buf = NULL; - dcd_event_xfer_complete(rhport, - tu_edpt_addr(0, TUSB_DIR_IN), - _dcd.pipe0.length - _dcd.pipe0.remaining, - XFER_RESULT_SUCCESS, true); - } -} - -static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) { - bool completed; - const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned epnum = tu_edpt_number(ep_addr); - - MXC_USBHS->index = epnum; - - if (dir_in) { - if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_SENTSTALL) { - MXC_USBHS->incsrl &= ~(MXC_F_USBHS_INCSRL_SENTSTALL | MXC_F_USBHS_INCSRL_UNDERRUN); - return; - } - completed = handle_xfer_in(ep_addr); - } else { - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_SENTSTALL) { - MXC_USBHS->outcsrl &= ~(MXC_F_USBHS_OUTCSRL_SENTSTALL | MXC_F_USBHS_OUTCSRL_OVERRUN); - return; - } - completed = handle_xfer_out(ep_addr); - } - - if (completed) { - pipe_state_t *pipe = &_dcd.pipe[dir_in][tu_edpt_number(ep_addr) - 1]; - dcd_event_xfer_complete(rhport, ep_addr, - pipe->length - pipe->remaining, - XFER_RESULT_SUCCESS, true); - } -} - -static void process_bus_reset(uint8_t rhport) { - (void) rhport; - /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), - * a control transfer state is SETUP or STATUS stage. */ - _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; - _dcd.status_out = 0; - /* When pipe0.buf has not NULL, DATA stage works in progress. */ - _dcd.pipe0.buf = NULL; - - MXC_USBHS->intrinen = 1; /* Enable only EP0 */ - MXC_USBHS->introuten = 0; - - - /* Clear FIFO settings */ - for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { - MXC_USBHS->index = i; - if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { - /* Per musbhsfc_pg, only flush FIFO if IN packet loaded */ - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_FLUSHFIFO; - } - - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { - /* Per musbhsfc_pg, only flush FIFO if OUT packet is ready */ - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_FLUSHFIFO; - } - } - dcd_event_bus_reset(0, (MXC_USBHS->power & MXC_F_USBHS_POWER_HS_MODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); -} - -/*------------------------------------------------------------------ - * Device API - *------------------------------------------------------------------*/ - -void dcd_init(uint8_t rhport) { - (void) rhport; - MXC_USBHS->intrusben |= MXC_F_USBHS_INTRUSBEN_SUSPEND_INT_EN; - - //Interrupt for VBUS disconnect - MXC_USBHS->mxm_int_en |= MXC_F_USBHS_MXM_INT_EN_NOVBUS; - - NVIC_ClearPendingIRQ(USB_IRQn); - dcd_edpt_close_all(rhport); - - //Unsuspend the MAC - MXC_USBHS->mxm_suspend = 0; - - /* Configure PHY */ - MXC_USBHS->m31_phy_xcfgi_31_0 = (0x1 << 3) | (0x1 << 11); - MXC_USBHS->m31_phy_xcfgi_63_32 = 0; - MXC_USBHS->m31_phy_xcfgi_95_64 = 0x1 << (72 - 64); - MXC_USBHS->m31_phy_xcfgi_127_96 = 0; - - - #ifdef USBHS_M31_CLOCK_RECOVERY - MXC_USBHS->m31_phy_noncry_rstb = 1; - MXC_USBHS->m31_phy_noncry_en = 1; - MXC_USBHS->m31_phy_outclksel = 0; - MXC_USBHS->m31_phy_coreclkin = 0; - MXC_USBHS->m31_phy_xtlsel = 2; /* Select 25 MHz clock */ - #else - /* Use this option to feed the PHY a 30 MHz clock, which is them used as a PLL reference */ - /* As it depends on the system core clock, this should probably be done at the SYS level */ - MXC_USBHS->m31_phy_noncry_rstb = 0; - MXC_USBHS->m31_phy_noncry_en = 0; - MXC_USBHS->m31_phy_outclksel = 1; - MXC_USBHS->m31_phy_coreclkin = 1; - MXC_USBHS->m31_phy_xtlsel = 3; /* Select 30 MHz clock */ - #endif - MXC_USBHS->m31_phy_pll_en = 1; - MXC_USBHS->m31_phy_oscouten = 1; - - /* Reset PHY */ - MXC_USBHS->m31_phy_ponrst = 0; - MXC_USBHS->m31_phy_ponrst = 1; - - dcd_connect(rhport); -} - -void dcd_int_enable(uint8_t rhport) { - (void) rhport; - NVIC_EnableIRQ(USB_IRQn); -} - -void dcd_int_disable(uint8_t rhport) { - (void) rhport; - NVIC_DisableIRQ(USB_IRQn); -} - -// Receive Set Address request, mcu port must also include status IN response -void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { - (void) rhport; - (void) dev_addr; - _dcd.pipe0.buf = NULL; - _dcd.pipe0.length = 0; - _dcd.pipe0.remaining = 0; - /* Clear RX FIFO to return ACK. */ - MXC_USBHS->index = 0; - MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SERV_OUTPKTRDY | MXC_F_USBHS_CSR0_DATA_END; -} - -// Wake up host -void dcd_remote_wakeup(uint8_t rhport) { - (void) rhport; - MXC_USBHS->power |= MXC_F_USBHS_POWER_RESUME; - - #if CFG_TUSB_OS != OPT_OS_NONE - osal_task_delay(10); - #else - MXC_Delay(MXC_DELAY_MSEC(10)); - #endif - - MXC_USBHS->power &= ~MXC_F_USBHS_POWER_RESUME; -} - -// Connect by enabling internal pull-up resistor on D+/D- -void dcd_connect(uint8_t rhport) { - (void) rhport; - MXC_USBHS->power |= TUD_OPT_HIGH_SPEED ? MXC_F_USBHS_POWER_HS_ENABLE : 0; - MXC_USBHS->power |= MXC_F_USBHS_POWER_SOFTCONN; -} - -// Disconnect by disabling internal pull-up resistor on D+/D- -void dcd_disconnect(uint8_t rhport) { - (void) rhport; - MXC_USBHS->power &= ~MXC_F_USBHS_POWER_SOFTCONN; -} - -void dcd_sof_enable(uint8_t rhport, bool en) { - (void) rhport; - (void) en; - - // TODO implement later -} - -//--------------------------------------------------------------------+ -// Endpoint API -//--------------------------------------------------------------------+ - -// Configure endpoint's registers according to descriptor -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc) { - (void) rhport; - - const unsigned ep_addr = ep_desc->bEndpointAddress; - const unsigned epn = tu_edpt_number(ep_addr); - const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned xfer = ep_desc->bmAttributes.xfer; - const unsigned mps = tu_edpt_packet_size(ep_desc); - - TU_ASSERT(epn < TUP_DCD_ENDPOINT_MAX); - - pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1]; - pipe->buf = NULL; - pipe->length = 0; - pipe->remaining = 0; - - MXC_USBHS->index = epn; - - if (dir_in) { - MXC_USBHS->inmaxp = mps; - MXC_USBHS->incsru = (MXC_F_USBHS_INCSRU_DPKTBUFDIS | MXC_F_USBHS_INCSRU_MODE) | ((xfer == TUSB_XFER_ISOCHRONOUS) ? MXC_F_USBHS_INCSRU_ISO : 0); - if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO; - } else { - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; - } - MXC_USBHS->intrinen |= TU_BIT(epn); - } else { - MXC_USBHS->outmaxp = mps; - MXC_USBHS->outcsru = (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS) | ((xfer == TUSB_XFER_ISOCHRONOUS) ? MXC_F_USBHS_OUTCSRU_ISO : 0); - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO; - } else { - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG; - } - MXC_USBHS->introuten |= TU_BIT(epn); - } - - return true; -} - -void dcd_edpt_close_all(uint8_t rhport) { - (void) rhport; - - MXC_SYS_Crit_Enter(); - MXC_USBHS->intrinen = 1; /* Enable only EP0 */ - MXC_USBHS->introuten = 0; - - for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { - MXC_USBHS->index = i; - MXC_USBHS->inmaxp = 0; - MXC_USBHS->incsru = MXC_F_USBHS_INCSRU_DPKTBUFDIS; - - if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO; - } else { - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; - } - - MXC_USBHS->outmaxp = 0; - MXC_USBHS->outcsru = MXC_F_USBHS_OUTCSRU_DPKTBUFDIS; - - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO; - } else { - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG; - } - } - MXC_SYS_Crit_Exit(); -} - -void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { - (void) rhport; - unsigned const epn = tu_edpt_number(ep_addr); - unsigned const dir_in = tu_edpt_dir(ep_addr); - - MXC_SYS_Crit_Enter(); - MXC_USBHS->index = epn; - if (dir_in) { - MXC_USBHS->intrinen &= ~TU_BIT(epn); - MXC_USBHS->inmaxp = 0; - MXC_USBHS->incsru = MXC_F_USBHS_INCSRU_DPKTBUFDIS; - if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO; - } else { - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; - } - } else { - MXC_USBHS->introuten &= ~TU_BIT(epn); - MXC_USBHS->outmaxp = 0; - MXC_USBHS->outcsru = MXC_F_USBHS_OUTCSRU_DPKTBUFDIS; - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO; - } else { - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG; - } - } - MXC_SYS_Crit_Exit(); -} - -// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - (void) rhport; - bool ret; - unsigned const epnum = tu_edpt_number(ep_addr); - MXC_SYS_Crit_Enter(); - if (epnum) { - _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] &= ~TU_BIT(epnum - 1); - ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes); - } else - ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes); - MXC_SYS_Crit_Exit(); - return ret; -} - -// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c -bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t *ff, uint16_t total_bytes) { - (void) rhport; - bool ret; - unsigned const epnum = tu_edpt_number(ep_addr); - TU_ASSERT(epnum); - MXC_SYS_Crit_Enter(); - _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] |= TU_BIT(epnum - 1); - ret = edpt_n_xfer(rhport, ep_addr, (uint8_t *) ff, total_bytes); - MXC_SYS_Crit_Exit(); - return ret; -} - -// Stall endpoint -void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - (void) rhport; - unsigned const epn = tu_edpt_number(ep_addr); - MXC_SYS_Crit_Enter(); - MXC_USBHS->index = epn; - if (0 == epn) { - if (!ep_addr) { /* Ignore EP80 */ - _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; - _dcd.pipe0.buf = NULL; - MXC_USBHS->csr0 = MXC_F_USBHS_CSR0_SEND_STALL; - } - } else { - if (tu_edpt_dir(ep_addr)) { /* IN */ - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_SENDSTALL; - } else { /* OUT */ - TU_ASSERT(!(MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY), ); - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_SENDSTALL; - } - } - MXC_SYS_Crit_Exit(); -} - -// clear stall, data toggle is also reset to DATA0 -void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - (void) rhport; - unsigned const epn = tu_edpt_number(ep_addr); - MXC_SYS_Crit_Enter(); - MXC_USBHS->index = epn; - if (tu_edpt_dir(ep_addr)) { /* IN */ - /* IN endpoint */ - if (MXC_USBHS->incsrl & MXC_F_USBHS_INCSRL_INPKTRDY) { - /* Per musbhsfc_pg, only flush FIFO if IN packet loaded */ - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG | MXC_F_USBHS_INCSRL_FLUSHFIFO; - } else { - MXC_USBHS->incsrl = MXC_F_USBHS_INCSRL_CLRDATATOG; - } - } else { /* OUT */ - /* Otherwise, must be OUT endpoint */ - if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) { - /* Per musbhsfc_pg, only flush FIFO if OUT packet is ready */ - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG | MXC_F_USBHS_OUTCSRL_FLUSHFIFO; - } else { - MXC_USBHS->outcsrl = MXC_F_USBHS_OUTCSRL_CLRDATATOG; - } - } - MXC_SYS_Crit_Exit(); -} - -/*------------------------------------------------------------------- - * ISR - *-------------------------------------------------------------------*/ -void dcd_int_handler(uint8_t rhport) { - uint_fast8_t is, txis, rxis; - uint32_t mxm_int, mxm_int_en, mxm_is; - uint32_t saved_index; - - /* Save current index register */ - saved_index = MXC_USBHS->index; - - is = MXC_USBHS->intrusb; /* read and clear interrupt status */ - txis = MXC_USBHS->intrin; /* read and clear interrupt status */ - rxis = MXC_USBHS->introut; /* read and clear interrupt status */ - - /* These USB interrupt flags are W1C. */ - /* Order of volatile accesses must be separated for IAR */ - mxm_int = MXC_USBHS->mxm_int; - mxm_int_en = MXC_USBHS->mxm_int_en; - mxm_is = mxm_int & mxm_int_en; - MXC_USBHS->mxm_int = mxm_is; - - is &= MXC_USBHS->intrusben; /* Clear disabled interrupts */ - - if (mxm_is & MXC_F_USBHS_MXM_INT_NOVBUS) { - dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); - } - if (is & MXC_F_USBHS_INTRUSB_SOF_INT) { - dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); - } - if (is & MXC_F_USBHS_INTRUSB_RESET_INT) { - process_bus_reset(rhport); - } - if (is & MXC_F_USBHS_INTRUSB_RESUME_INT) { - dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); - } - if (is & MXC_F_USBHS_INTRUSB_SUSPEND_INT) { - dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); - } - - txis &= MXC_USBHS->intrinen; /* Clear disabled interrupts */ - if (txis & MXC_F_USBHS_INTRIN_EP0_IN_INT) { - process_ep0(rhport); - txis &= ~TU_BIT(0); - } - while (txis) { - unsigned const num = __builtin_ctz(txis); - process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN)); - txis &= ~TU_BIT(num); - } - rxis &= MXC_USBHS->introuten; /* Clear disabled interrupts */ - while (rxis) { - unsigned const num = __builtin_ctz(rxis); - process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT)); - rxis &= ~TU_BIT(num); - } - - /* Restore register index before exiting ISR */ - MXC_USBHS->index = saved_index; -} - -#endif diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index a817c5d6e..ee36656fd 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -2,6 +2,7 @@ * The MIT License (MIT) * * Copyright (c) 2021 Koji KITAYAMA + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -26,8 +27,7 @@ #include "tusb_option.h" -#if CFG_TUD_ENABLED && \ - TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) +#if CFG_TUD_ENABLED #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) /* GCC warns that an address may be unaligned, even though @@ -35,43 +35,30 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); #endif +#include "musb_type.h" #include "device/dcd.h" -#if TU_CHECK_MCU(OPT_MCU_MSP432E4) - #include "musb_msp432e.h" - -#elif TU_CHECK_MCU(OPT_MCU_TM4C123, OPT_MCU_TM4C129) - #include "musb_tm4c.h" - - // HACK generalize later - #include "musb_type.h" - #define FIFO0_WORD FIFO0 - #define FIFO1_WORD FIFO1 - +// Following symbols must be defined by port header +// - musb_dcd_int_enable/disable/clear/get_enable +// - musb_dcd_int_handler_enter/exit +// - musb_dcd_epn_regs: Get memory mapped struct of end point registers +// - musb_dcd_ep0_regs: Get memory mapped struct of EP0 registers +// - musb_dcd_ctl_regs: Get memory mapped struct of control registers +// - musb_dcd_ep_get_fifo_ptr: Gets the address of the provided EP's FIFO +// - musb_dcd_setup_fifo/reset_fifo: Configuration of the EP's FIFO +#if TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) + #include "musb_ti.h" +#elif TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX78002) + #include "musb_max32.h" #else - #error "Unsupported MCUs" + #error "Unsupported MCU" #endif /*------------------------------------------------------------------ * MACRO TYPEDEF CONSTANT ENUM DECLARATION *------------------------------------------------------------------*/ -#define REQUEST_TYPE_INVALID (0xFFu) -typedef struct { - uint_fast16_t beg; /* offset of including first element */ - uint_fast16_t end; /* offset of excluding the last element */ -} free_block_t; - -typedef struct TU_ATTR_PACKED { - uint16_t TXMAXP; - uint8_t TXCSRL; - uint8_t TXCSRH; - uint16_t RXMAXP; - uint8_t RXCSRL; - uint8_t RXCSRH; - uint16_t RXCOUNT; - uint16_t RESERVED[3]; -} hw_endpoint_t; +#define REQUEST_TYPE_INVALID (0xFFu) typedef union { uint8_t u8; @@ -92,7 +79,7 @@ typedef struct uint16_t remaining_ctrl; /* The number of bytes remaining in data stage of control transfer. */ int8_t status_out; pipe_state_t pipe0; - pipe_state_t pipe[2][7]; /* pipe[direction][endpoint number - 1] */ + pipe_state_t pipe[2][TUP_DCD_ENDPOINT_MAX-1]; /* pipe[direction][endpoint number - 1] */ uint16_t pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */ } dcd_data_t; @@ -102,126 +89,6 @@ typedef struct static dcd_data_t _dcd; -static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr) -{ - free_block_t *cur = beg; - for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ; - return cur; -} - -static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size) -{ - free_block_t *p = find_containing_block(blks, blks + num, addr); - TU_ASSERT(p != blks + num, -2); - if (p->beg == addr) { - /* Shrink block */ - p->beg = addr + size; - if (p->beg != p->end) return 0; - /* remove block */ - free_block_t *end = blks + num; - while (p + 1 < end) { - *p = *(p + 1); - ++p; - } - return -1; - } else { - /* Split into 2 blocks */ - free_block_t tmp = { - .beg = addr + size, - .end = p->end - }; - p->end = addr; - if (p->beg == p->end) { - if (tmp.beg != tmp.end) { - *p = tmp; - return 0; - } - /* remove block */ - free_block_t *end = blks + num; - while (p + 1 < end) { - *p = *(p + 1); - ++p; - } - return -1; - } - if (tmp.beg == tmp.end) return 0; - blks[num] = tmp; - return 1; - } -} - -static inline unsigned free_block_size(free_block_t const *blk) -{ - return blk->end - blk->beg; -} - -#if 0 -static inline void print_block_list(free_block_t const *blk, unsigned num) -{ - TU_LOG1("*************\r\n"); - for (unsigned i = 0; i < num; ++i) { - TU_LOG1(" Blk%u %u %u\r\n", i, blk->beg, blk->end); - ++blk; - } -} -#else -#define print_block_list(a,b) -#endif - -static unsigned find_free_memory(uint_fast16_t size_in_log2_minus3) -{ - free_block_t free_blocks[2 * (TUP_DCD_ENDPOINT_MAX - 1)]; - unsigned num_blocks = 1; - - /* Initialize free memory block list */ - free_blocks[0].beg = 64 / 8; - free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */ - for (int i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { - uint_fast16_t addr; - int num; - USB0->EPIDX = i; - addr = USB0->TXFIFOADD; - if (addr) { - unsigned sz = USB0->TXFIFOSZ; - unsigned sft = (sz & USB_TXFIFOSZ_SIZE_M) + ((sz & USB_TXFIFOSZ_DPB) ? 1: 0); - num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); - TU_ASSERT(-2 < num, 0); - num_blocks += num; - print_block_list(free_blocks, num_blocks); - } - addr = USB0->RXFIFOADD; - if (addr) { - unsigned sz = USB0->RXFIFOSZ; - unsigned sft = (sz & USB_RXFIFOSZ_SIZE_M) + ((sz & USB_RXFIFOSZ_DPB) ? 1: 0); - num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); - TU_ASSERT(-2 < num, 0); - num_blocks += num; - print_block_list(free_blocks, num_blocks); - } - } - print_block_list(free_blocks, num_blocks); - - /* Find the best fit memory block */ - uint_fast16_t size_in_8byte_unit = 1 << size_in_log2_minus3; - free_block_t const *min = NULL; - uint_fast16_t min_sz = 0xFFFFu; - free_block_t const *end = &free_blocks[num_blocks]; - for (free_block_t const *cur = &free_blocks[0]; cur < end; ++cur) { - uint_fast16_t sz = free_block_size(cur); - if (sz < size_in_8byte_unit) continue; - if (size_in_8byte_unit == sz) return cur->beg; - if (sz < min_sz) min = cur; - } - TU_ASSERT(min, 0); - return min->beg; -} - -static inline volatile hw_endpoint_t* edpt_regs(unsigned epnum_minus1) -{ - volatile hw_endpoint_t *regs = (volatile hw_endpoint_t*)((uintptr_t)&USB0->TXMAXP1); - return regs + epnum_minus1; -} - static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; @@ -287,8 +154,10 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne static void process_setup_packet(uint8_t rhport) { uint32_t *p = (void*)&_dcd.setup_packet; - p[0] = USB0->FIFO0_WORD; - p[1] = USB0->FIFO0_WORD; + volatile uint32_t *fifo_ptr = musb_dcd_ep_get_fifo_ptr(rhport, 0); + volatile musb_dcd_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); + p[0] = *fifo_ptr; + p[1] = *fifo_ptr; _dcd.pipe0.buf = NULL; _dcd.pipe0.length = 0; @@ -299,12 +168,13 @@ static void process_setup_packet(uint8_t rhport) _dcd.remaining_ctrl = len; const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType); /* Clear RX FIFO and reverse the transaction direction */ - if (len && dir_in) USB0->CSRL0 = USB_CSRL0_RXRDYC; + if (len && dir_in) ep0_regs->CSRL0 = USB_CSRL0_RXRDYC; } -static bool handle_xfer_in(uint_fast8_t ep_addr) +static bool handle_xfer_in(uint8_t rhport, uint_fast8_t ep_addr) { - unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1; + unsigned epnum = tu_edpt_number(ep_addr); + unsigned epnum_minus1 = epnum - 1; pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; const unsigned rem = pipe->remaining; @@ -313,30 +183,32 @@ static bool handle_xfer_in(uint_fast8_t ep_addr) return true; } - volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1); + volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epnum); const unsigned mps = regs->TXMAXP; const unsigned len = TU_MIN(mps, rem); void *buf = pipe->buf; + volatile void *fifo_ptr = musb_dcd_ep_get_fifo_ptr(rhport, epnum); // TU_LOG1(" %p mps %d len %d rem %d\r\n", buf, mps, len, rem); if (len) { if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) { - pipe_read_write_packet_ff(buf, &USB0->FIFO1_WORD + epnum_minus1, len, TUSB_DIR_IN); + pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_IN); } else { - pipe_write_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len); + pipe_write_packet(buf, fifo_ptr, len); pipe->buf = buf + len; } pipe->remaining = rem - len; } regs->TXCSRL = USB_TXCSRL1_TXRDY; - // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum_minus1 + 1, regs->TXCSRL, rem - len); + // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum, regs->TXCSRL, rem - len); return false; } -static bool handle_xfer_out(uint_fast8_t ep_addr) +static bool handle_xfer_out(uint8_t rhport, uint_fast8_t ep_addr) { - unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1; + unsigned epnum = tu_edpt_number(ep_addr); + unsigned epnum_minus1 = epnum - 1; pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; - volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1); + volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epnum); // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, regs->RXCSRL); TU_ASSERT(regs->RXCSRL & USB_RXCSRL1_RXRDY); @@ -346,11 +218,12 @@ static bool handle_xfer_out(uint_fast8_t ep_addr) const unsigned vld = regs->RXCOUNT; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; + volatile void *fifo_ptr = musb_dcd_ep_get_fifo_ptr(rhport, epnum); if (len) { if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) { - pipe_read_write_packet_ff(buf, &USB0->FIFO1_WORD + epnum_minus1, len, TUSB_DIR_OUT); + pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_OUT); } else { - pipe_read_packet(buf, &USB0->FIFO1_WORD + epnum_minus1, len); + pipe_read_packet(buf, fifo_ptr, len); pipe->buf = buf + len; } pipe->remaining = rem - len; @@ -365,9 +238,8 @@ static bool handle_xfer_out(uint_fast8_t ep_addr) static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - (void)rhport; - - unsigned epnum_minus1 = tu_edpt_number(ep_addr) - 1; + unsigned epnum = tu_edpt_number(ep_addr); + unsigned epnum_minus1 = epnum - 1; unsigned dir_in = tu_edpt_dir(ep_addr); pipe_state_t *pipe = &_dcd.pipe[dir_in][epnum_minus1]; @@ -376,9 +248,9 @@ static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16 pipe->remaining = total_bytes; if (dir_in) { - handle_xfer_in(ep_addr); + handle_xfer_in(rhport, ep_addr); } else { - volatile hw_endpoint_t *regs = edpt_regs(epnum_minus1); + volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epnum); if (regs->RXCSRL & USB_RXCSRL1_RXRDY) regs->RXCSRL = 0; } return true; @@ -388,7 +260,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ { (void)rhport; TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */ - + volatile musb_dcd_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); const unsigned req = _dcd.setup_packet.bmRequestType; TU_ASSERT(req != REQUEST_TYPE_INVALID || total_bytes == 0); @@ -399,7 +271,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ * may have already finished and received the next setup packet * without calling this function, so we have no choice but to * invoke the callback function of status packet here. */ - // TU_LOG1(" STATUS OUT USB0->CSRL0 = %x\r\n", USB0->CSRL0); + // TU_LOG1(" STATUS OUT ep0_regs->CSRL0 = %x\r\n", ep0_regs->CSRL0); _dcd.status_out = 0; if (req == REQUEST_TYPE_INVALID) { dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false); @@ -415,8 +287,9 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ TU_ASSERT(total_bytes <= _dcd.remaining_ctrl); const unsigned rem = _dcd.remaining_ctrl; const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes); + volatile void *fifo_ptr = musb_dcd_ep_get_fifo_ptr(rhport, 0); if (dir_in) { - pipe_write_packet(buffer, &USB0->FIFO0_WORD, len); + pipe_write_packet(buffer, fifo_ptr, len); _dcd.pipe0.buf = buffer + len; _dcd.pipe0.length = len; @@ -427,45 +300,46 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */ _dcd.status_out = 1; /* Flush TX FIFO and reverse the transaction direction. */ - USB0->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND; + ep0_regs->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND; } else { - USB0->CSRL0 = USB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */ + ep0_regs->CSRL0 = USB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */ } - // TU_LOG1(" IN USB0->CSRL0 = %x\r\n", USB0->CSRL0); + // TU_LOG1(" IN ep0_regs->CSRL0 = %x\r\n", ep0_regs->CSRL0); } else { - // TU_LOG1(" OUT USB0->CSRL0 = %x\r\n", USB0->CSRL0); + // TU_LOG1(" OUT ep0_regs->CSRL0 = %x\r\n", ep0_regs->CSRL0); _dcd.pipe0.buf = buffer; _dcd.pipe0.length = len; _dcd.pipe0.remaining = len; - USB0->CSRL0 = USB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */ + ep0_regs->CSRL0 = USB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */ } } else if (dir_in) { - // TU_LOG1(" STATUS IN USB0->CSRL0 = %x\r\n", USB0->CSRL0); + // TU_LOG1(" STATUS IN ep0_regs->CSRL0 = %x\r\n", ep0_regs->CSRL0); _dcd.pipe0.buf = NULL; _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; /* Clear RX FIFO and reverse the transaction direction */ - USB0->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; + ep0_regs->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; } return true; } static void process_ep0(uint8_t rhport) { - uint_fast8_t csrl = USB0->CSRL0; + volatile musb_dcd_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); + uint_fast8_t csrl = ep0_regs->CSRL0; - // TU_LOG1(" EP0 USB0->CSRL0 = %x\r\n", csrl); + // TU_LOG1(" EP0 ep0_regs->CSRL0 = %x\r\n", csrl); if (csrl & USB_CSRL0_STALLED) { /* Returned STALL packet to HOST. */ - USB0->CSRL0 = 0; /* Clear STALL */ + ep0_regs->CSRL0 = 0; /* Clear STALL */ return; } unsigned req = _dcd.setup_packet.bmRequestType; if (csrl & USB_CSRL0_SETEND) { TU_LOG1(" ABORT by the next packets\r\n"); - USB0->CSRL0 = USB_CSRL0_SETENDC; + ep0_regs->CSRL0 = USB_CSRL0_SETENDC; if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) { /* DATA stage was aborted by receiving STATUS or SETUP packet. */ _dcd.pipe0.buf = NULL; @@ -483,16 +357,17 @@ static void process_ep0(uint8_t rhport) /* Received SETUP or DATA OUT packet */ if (req == REQUEST_TYPE_INVALID) { /* SETUP */ - TU_ASSERT(sizeof(tusb_control_request_t) == USB0->COUNT0,); + TU_ASSERT(sizeof(tusb_control_request_t) == ep0_regs->COUNT0,); process_setup_packet(rhport); return; } if (_dcd.pipe0.buf) { /* DATA OUT */ - const unsigned vld = USB0->COUNT0; + const unsigned vld = ep0_regs->COUNT0; const unsigned rem = _dcd.pipe0.remaining; const unsigned len = TU_MIN(TU_MIN(rem, 64), vld); - pipe_read_packet(_dcd.pipe0.buf, &USB0->FIFO0_WORD, len); + volatile void *fifo_ptr = musb_dcd_ep_get_fifo_ptr(rhport, 0); + pipe_read_packet(_dcd.pipe0.buf, fifo_ptr, len); _dcd.pipe0.remaining = rem - len; _dcd.remaining_ctrl -= len; @@ -506,13 +381,15 @@ static void process_ep0(uint8_t rhport) return; } + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + /* When CSRL0 is zero, it means that completion of sending a any length packet * or receiving a zero length packet. */ if (req != REQUEST_TYPE_INVALID && !tu_edpt_dir(req)) { /* STATUS IN */ if (*(const uint16_t*)(uintptr_t)&_dcd.setup_packet == 0x0500) { /* The address must be changed on completion of the control transfer. */ - USB0->FADDR = (uint8_t)_dcd.setup_packet.wValue; + ctrl_regs->FADDR = (uint8_t)_dcd.setup_packet.wValue; } _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; dcd_event_xfer_complete(rhport, @@ -535,27 +412,28 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) { bool completed; const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned epn_minus1 = tu_edpt_number(ep_addr) - 1; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned epn_minus1 = epn - 1; - volatile hw_endpoint_t *regs = edpt_regs(epn_minus1); + volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); if (dir_in) { - // TU_LOG1(" TXCSRL%d = %x\r\n", epn_minus1 + 1, regs->TXCSRL); + // TU_LOG1(" TXCSRL%d = %x\r\n", epn, regs->TXCSRL); if (regs->TXCSRL & USB_TXCSRL1_STALLED) { regs->TXCSRL &= ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_UNDRN); return; } - completed = handle_xfer_in(ep_addr); + completed = handle_xfer_in(rhport, ep_addr); } else { - // TU_LOG1(" RXCSRL%d = %x\r\n", epn_minus1 + 1, regs->RXCSRL); + // TU_LOG1(" RXCSRL%d = %x\r\n", epn, regs->RXCSRL); if (regs->RXCSRL & USB_RXCSRL1_STALLED) { regs->RXCSRL &= ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_OVER); return; } - completed = handle_xfer_out(ep_addr); + completed = handle_xfer_out(rhport, ep_addr); } if (completed) { - pipe_state_t *pipe = &_dcd.pipe[dir_in][tu_edpt_number(ep_addr) - 1]; + pipe_state_t *pipe = &_dcd.pipe[dir_in][epn_minus1]; dcd_event_xfer_complete(rhport, ep_addr, pipe->length - pipe->remaining, XFER_RESULT_SUCCESS, true); @@ -564,6 +442,7 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) static void process_bus_reset(uint8_t rhport) { + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), * a control transfer state is SETUP or STATUS stage. */ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; @@ -571,18 +450,15 @@ static void process_bus_reset(uint8_t rhport) /* When pipe0.buf has not NULL, DATA stage works in progress. */ _dcd.pipe0.buf = NULL; - USB0->TXIE = 1; /* Enable only EP0 */ - USB0->RXIE = 0; + ctrl_regs->TXIE = 1; /* Enable only EP0 */ + ctrl_regs->RXIE = 0; /* Clear FIFO settings */ for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { - USB0->EPIDX = i; - USB0->TXFIFOSZ = 0; - USB0->TXFIFOADD = 0; - USB0->RXFIFOSZ = 0; - USB0->RXFIFOADD = 0; + musb_dcd_reset_fifo(rhport, i, 0); + musb_dcd_reset_fifo(rhport, i, 1); } - dcd_event_bus_reset(rhport, TUSB_SPEED_FULL, true); + dcd_event_bus_reset(rhport, (ctrl_regs->POWER & USB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); } /*------------------------------------------------------------------ @@ -591,61 +467,60 @@ static void process_bus_reset(uint8_t rhport) void dcd_init(uint8_t rhport) { - (void)rhport; - USB0->IE |= USB_IE_SUSPND; - NVIC_ClearPendingIRQ(USB0_IRQn); - + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + ctrl_regs->IE |= USB_IE_SUSPND; + musb_dcd_int_clear(rhport); + musb_dcd_phy_init(rhport); dcd_connect(rhport); } void dcd_int_enable(uint8_t rhport) { - (void)rhport; - NVIC_EnableIRQ(USB0_IRQn); + musb_dcd_int_enable(rhport); } void dcd_int_disable(uint8_t rhport) { - (void)rhport; - NVIC_DisableIRQ(USB0_IRQn); + musb_dcd_int_disable(rhport); } // Receive Set Address request, mcu port must also include status IN response void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { - (void)rhport; (void)dev_addr; + volatile musb_dcd_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); _dcd.pipe0.buf = NULL; _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; /* Clear RX FIFO to return ACK. */ - USB0->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; + ep0_regs->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; } // Wake up host void dcd_remote_wakeup(uint8_t rhport) { - (void)rhport; - USB0->POWER |= USB_POWER_RESUME; + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + ctrl_regs->POWER |= USB_POWER_RESUME; unsigned cnt = SystemCoreClock / 1000; while (cnt--) __NOP(); - USB0->POWER &= ~USB_POWER_RESUME; + ctrl_regs->POWER &= ~USB_POWER_RESUME; } // Connect by enabling internal pull-up resistor on D+/D- void dcd_connect(uint8_t rhport) { - (void)rhport; - USB0->POWER |= USB_POWER_SOFTCONN; + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + ctrl_regs->POWER |= TUD_OPT_HIGH_SPEED ? USB_POWER_HSENAB : 0; + ctrl_regs->POWER |= USB_POWER_SOFTCONN; } // Disconnect by disabling internal pull-up resistor on D+/D- void dcd_disconnect(uint8_t rhport) { - (void)rhport; - USB0->POWER &= ~USB_POWER_SOFTCONN; + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + ctrl_regs->POWER &= ~USB_POWER_SOFTCONN; } void dcd_sof_enable(uint8_t rhport, bool en) @@ -663,8 +538,6 @@ void dcd_sof_enable(uint8_t rhport, bool en) // Configure endpoint's registers according to descriptor bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { - (void) rhport; - const unsigned ep_addr = ep_desc->bEndpointAddress; const unsigned epn = tu_edpt_number(ep_addr); const unsigned dir_in = tu_edpt_dir(ep_addr); @@ -678,7 +551,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) pipe->length = 0; pipe->remaining = 0; - volatile hw_endpoint_t *regs = edpt_regs(epn - 1); + volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); if (dir_in) { regs->TXMAXP = mps; regs->TXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_TXCSRH1_ISO : 0; @@ -686,7 +560,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; else regs->TXCSRL = USB_TXCSRL1_CLRDT; - USB0->TXIE |= TU_BIT(epn); + ctrl_regs->TXIE |= TU_BIT(epn); } else { regs->RXMAXP = mps; regs->RXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0; @@ -694,36 +568,25 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; else regs->RXCSRL = USB_RXCSRL1_CLRDT; - USB0->RXIE |= TU_BIT(epn); + ctrl_regs->RXIE |= TU_BIT(epn); } /* Setup FIFO */ - int size_in_log2_minus3 = 28 - TU_MIN(28, __CLZ((uint32_t)mps)); - if ((8u << size_in_log2_minus3) < mps) ++size_in_log2_minus3; - unsigned addr = find_free_memory(size_in_log2_minus3); - TU_ASSERT(addr); - - USB0->EPIDX = epn; - if (dir_in) { - USB0->TXFIFOADD = addr; - USB0->TXFIFOSZ = size_in_log2_minus3; - } else { - USB0->RXFIFOADD = addr; - USB0->RXFIFOSZ = size_in_log2_minus3; - } + musb_dcd_setup_fifo(rhport, epn, dir_in, mps); return true; } void dcd_edpt_close_all(uint8_t rhport) { - (void) rhport; - volatile hw_endpoint_t *regs = (volatile hw_endpoint_t *)(uintptr_t)&USB0->TXMAXP1; - unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); - NVIC_DisableIRQ(USB0_IRQn); - USB0->TXIE = 1; /* Enable only EP0 */ - USB0->RXIE = 0; + volatile musb_dcd_epn_regs_t *regs; + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + unsigned const ie = musb_dcd_get_int_enable(rhport); + musb_dcd_int_disable(rhport); + ctrl_regs->TXIE = 1; /* Enable only EP0 */ + ctrl_regs->RXIE = 0; for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { + regs = musb_dcd_epn_regs(rhport, i); regs->TXMAXP = 0; regs->TXCSRH = 0; if (regs->TXCSRL & USB_TXCSRL1_TXRDY) @@ -738,50 +601,41 @@ void dcd_edpt_close_all(uint8_t rhport) else regs->RXCSRL = USB_RXCSRL1_CLRDT; - USB0->EPIDX = i; - USB0->TXFIFOSZ = 0; - USB0->TXFIFOADD = 0; - USB0->RXFIFOSZ = 0; - USB0->RXFIFOADD = 0; + musb_dcd_reset_fifo(rhport, i, 0); + musb_dcd_reset_fifo(rhport, i, 1); + } - if (ie) NVIC_EnableIRQ(USB0_IRQn); + if (ie) musb_dcd_int_enable(rhport); } void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; unsigned const epn = tu_edpt_number(ep_addr); unsigned const dir_in = tu_edpt_dir(ep_addr); - hw_endpoint_t volatile *regs = edpt_regs(epn - 1); - unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); - NVIC_DisableIRQ(USB0_IRQn); + volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); + volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + unsigned const ie = musb_dcd_get_int_enable(rhport); + musb_dcd_int_disable(rhport); if (dir_in) { - USB0->TXIE &= ~TU_BIT(epn); + ctrl_regs->TXIE &= ~TU_BIT(epn); regs->TXMAXP = 0; regs->TXCSRH = 0; if (regs->TXCSRL & USB_TXCSRL1_TXRDY) regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; else regs->TXCSRL = USB_TXCSRL1_CLRDT; - - USB0->EPIDX = epn; - USB0->TXFIFOSZ = 0; - USB0->TXFIFOADD = 0; } else { - USB0->RXIE &= ~TU_BIT(epn); + ctrl_regs->RXIE &= ~TU_BIT(epn); regs->RXMAXP = 0; regs->RXCSRH = 0; if (regs->RXCSRL & USB_RXCSRL1_RXRDY) regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; else regs->RXCSRL = USB_RXCSRL1_CLRDT; - - USB0->EPIDX = epn; - USB0->RXFIFOSZ = 0; - USB0->RXFIFOADD = 0; } - if (ie) NVIC_EnableIRQ(USB0_IRQn); + musb_dcd_reset_fifo(rhport, epn, dir_in); + if (ie) musb_dcd_int_enable(rhport); } // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack @@ -791,14 +645,14 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t bool ret; // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes); unsigned const epnum = tu_edpt_number(ep_addr); - unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); - NVIC_DisableIRQ(USB0_IRQn); + unsigned const ie = musb_dcd_get_int_enable(rhport); + musb_dcd_int_disable(rhport); if (epnum) { _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] &= ~TU_BIT(epnum - 1); ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes); } else ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes); - if (ie) NVIC_EnableIRQ(USB0_IRQn); + if (ie) musb_dcd_int_enable(rhport); return ret; } @@ -810,29 +664,29 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_ // TU_LOG1("X %x %d\r\n", ep_addr, total_bytes); unsigned const epnum = tu_edpt_number(ep_addr); TU_ASSERT(epnum); - unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); - NVIC_DisableIRQ(USB0_IRQn); + unsigned const ie = musb_dcd_get_int_enable(rhport); + musb_dcd_int_disable(rhport); _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] |= TU_BIT(epnum - 1); ret = edpt_n_xfer(rhport, ep_addr, (uint8_t*)ff, total_bytes); - if (ie) NVIC_EnableIRQ(USB0_IRQn); + if (ie) musb_dcd_int_enable(rhport); return ret; } // Stall endpoint void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; unsigned const epn = tu_edpt_number(ep_addr); - unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); - NVIC_DisableIRQ(USB0_IRQn); + unsigned const ie = musb_dcd_get_int_enable(rhport); + musb_dcd_int_disable(rhport); if (0 == epn) { + volatile musb_dcd_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); if (!ep_addr) { /* Ignore EP80 */ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; _dcd.pipe0.buf = NULL; - USB0->CSRL0 = USB_CSRL0_STALL; + ep0_regs->CSRL0 = USB_CSRL0_STALL; } } else { - volatile hw_endpoint_t *regs = edpt_regs(epn - 1); + volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); if (tu_edpt_dir(ep_addr)) { /* IN */ regs->TXCSRL = USB_TXCSRL1_STALL; } else { /* OUT */ @@ -840,7 +694,7 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) regs->RXCSRL = USB_RXCSRL1_STALL; } } - if (ie) NVIC_EnableIRQ(USB0_IRQn); + if (ie) musb_dcd_int_enable(rhport); } // clear stall, data toggle is also reset to DATA0 @@ -848,15 +702,15 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { (void)rhport; unsigned const epn = tu_edpt_number(ep_addr); - hw_endpoint_t volatile *regs = edpt_regs(epn - 1); - unsigned const ie = NVIC_GetEnableIRQ(USB0_IRQn); - NVIC_DisableIRQ(USB0_IRQn); + musb_dcd_epn_regs_t volatile *regs = musb_dcd_epn_regs(rhport, epn); + unsigned const ie = musb_dcd_get_int_enable(rhport); + musb_dcd_int_disable(rhport); if (tu_edpt_dir(ep_addr)) { /* IN */ regs->TXCSRL = USB_TXCSRL1_CLRDT; } else { /* OUT */ regs->RXCSRL = USB_RXCSRL1_CLRDT; } - if (ie) NVIC_EnableIRQ(USB0_IRQn); + if (ie) musb_dcd_int_enable(rhport); } /*------------------------------------------------------------------- @@ -865,13 +719,18 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) void dcd_int_handler(uint8_t rhport) { uint_fast8_t is, txis, rxis; + volatile musb_dcd_ctl_regs_t *ctrl_regs; + + //Part specific ISR setup/entry + musb_dcd_int_handler_enter(rhport); - is = USB0->IS; /* read and clear interrupt status */ - txis = USB0->TXIS; /* read and clear interrupt status */ - rxis = USB0->RXIS; /* read and clear interrupt status */ + ctrl_regs = musb_dcd_ctl_regs(rhport); + is = ctrl_regs->IS; /* read and clear interrupt status */ + txis = ctrl_regs->TXIS; /* read and clear interrupt status */ + rxis = ctrl_regs->RXIS; /* read and clear interrupt status */ // TU_LOG1("D%2x T%2x R%2x\r\n", is, txis, rxis); - is &= USB0->IE; /* Clear disabled interrupts */ + is &= ctrl_regs->IE; /* Clear disabled interrupts */ if (is & USB_IS_DISCON) { } if (is & USB_IS_SOF) { @@ -887,7 +746,7 @@ void dcd_int_handler(uint8_t rhport) dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); } - txis &= USB0->TXIE; /* Clear disabled interrupts */ + txis &= ctrl_regs->TXIE; /* Clear disabled interrupts */ if (txis & USB_TXIE_EP0) { process_ep0(rhport); txis &= ~TU_BIT(0); @@ -897,12 +756,15 @@ void dcd_int_handler(uint8_t rhport) process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN)); txis &= ~TU_BIT(num); } - rxis &= USB0->RXIE; /* Clear disabled interrupts */ + rxis &= ctrl_regs->RXIE; /* Clear disabled interrupts */ while (rxis) { unsigned const num = __builtin_ctz(rxis); process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT)); rxis &= ~TU_BIT(num); } + + //Part specific ISR exit + musb_dcd_int_handler_exit(rhport); } #endif diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c index 5312c2812..8fc225676 100644 --- a/src/portable/mentor/musb/hcd_musb.c +++ b/src/portable/mentor/musb/hcd_musb.c @@ -37,16 +37,10 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); #include "host/hcd.h" -#if TU_CHECK_MCU(OPT_MCU_MSP432E4) - #include "musb_msp432e.h" - -#elif TU_CHECK_MCU(OPT_MCU_TM4C123, OPT_MCU_TM4C129) - #include "musb_tm4c.h" - - // HACK generalize later - #include "musb_type.h" - #define FIFO0_WORD FIFO0 +#include "musb_type.h" +#if TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) + #include "musb_ti.h" #else #error "Unsupported MCUs" #endif diff --git a/src/portable/mentor/musb/musb_max32.h b/src/portable/mentor/musb/musb_max32.h new file mode 100644 index 000000000..297a695f8 --- /dev/null +++ b/src/portable/mentor/musb/musb_max32.h @@ -0,0 +1,221 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_MUSB_MAX32_H_ +#define _TUSB_MUSB_MAX32_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#if TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX78002) + #include "mxc_device.h" + #include "usbhs_regs.h" +#else + #error "Unsupported MCUs" +#endif + + +#if CFG_TUD_ENABLED +#define USBHS_M31_CLOCK_RECOVERY + +// Mapping of peripheral instances to port. Currently just 1. +static mxc_usbhs_regs_t* const musb_periph_inst[] = { + MXC_USBHS +}; + +// Mapping of IRQ numbers to port. Currently just 1. +static const IRQn_Type musb_irqs[] = { + USB_IRQn +}; + +TU_ATTR_ALWAYS_INLINE +static inline void musb_dcd_int_enable(uint8_t rhport) +{ + NVIC_EnableIRQ(musb_irqs[rhport]); +} + +TU_ATTR_ALWAYS_INLINE +static inline void musb_dcd_int_disable(uint8_t rhport) +{ + NVIC_DisableIRQ(musb_irqs[rhport]); +} + +TU_ATTR_ALWAYS_INLINE +static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) +{ + return NVIC_GetEnableIRQ(musb_irqs[rhport]); +} + +TU_ATTR_ALWAYS_INLINE +static inline void musb_dcd_int_clear(uint8_t rhport) +{ + NVIC_ClearPendingIRQ(musb_irqs[rhport]); +} + +//Used to save and restore user's register map when interrupt occurs +static volatile unsigned isr_saved_index = 0; + +static inline void musb_dcd_int_handler_enter(uint8_t rhport) +{ + uint32_t mxm_int, mxm_int_en, mxm_is; + + //save current register index + isr_saved_index = musb_periph_inst[rhport]->index; + + //Handle PHY specific events + mxm_int = musb_periph_inst[rhport]->mxm_int; + mxm_int_en = musb_periph_inst[rhport]->mxm_int_en; + mxm_is = mxm_int & mxm_int_en; + musb_periph_inst[rhport]->mxm_int = mxm_is; + + if (mxm_is & MXC_F_USBHS_MXM_INT_NOVBUS) { + dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); + } +} + +static inline void musb_dcd_int_handler_exit(uint8_t rhport) +{ + //restore register index + musb_periph_inst[rhport]->index = isr_saved_index; +} + +static inline void musb_dcd_phy_init(uint8_t rhport) +{ + //Interrupt for VBUS disconnect + musb_periph_inst[rhport]->mxm_int_en |= MXC_F_USBHS_MXM_INT_EN_NOVBUS; + + musb_dcd_int_clear(rhport); + + //Unsuspend the MAC + musb_periph_inst[rhport]->mxm_suspend = 0; + + // Configure PHY + musb_periph_inst[rhport]->m31_phy_xcfgi_31_0 = (0x1 << 3) | (0x1 << 11); + musb_periph_inst[rhport]->m31_phy_xcfgi_63_32 = 0; + musb_periph_inst[rhport]->m31_phy_xcfgi_95_64 = 0x1 << (72 - 64); + musb_periph_inst[rhport]->m31_phy_xcfgi_127_96 = 0; + + + #ifdef USBHS_M31_CLOCK_RECOVERY + musb_periph_inst[rhport]->m31_phy_noncry_rstb = 1; + musb_periph_inst[rhport]->m31_phy_noncry_en = 1; + musb_periph_inst[rhport]->m31_phy_outclksel = 0; + musb_periph_inst[rhport]->m31_phy_coreclkin = 0; + musb_periph_inst[rhport]->m31_phy_xtlsel = 2; /* Select 25 MHz clock */ + #else + musb_periph_inst[rhport]->m31_phy_noncry_rstb = 0; + musb_periph_inst[rhport]->m31_phy_noncry_en = 0; + musb_periph_inst[rhport]->m31_phy_outclksel = 1; + musb_periph_inst[rhport]->m31_phy_coreclkin = 1; + musb_periph_inst[rhport]->m31_phy_xtlsel = 3; /* Select 30 MHz clock */ + #endif + musb_periph_inst[rhport]->m31_phy_pll_en = 1; + musb_periph_inst[rhport]->m31_phy_oscouten = 1; + + /* Reset PHY */ + musb_periph_inst[rhport]->m31_phy_ponrst = 0; + musb_periph_inst[rhport]->m31_phy_ponrst = 1; +} + +static inline volatile musb_dcd_ctl_regs_t* musb_dcd_ctl_regs(uint8_t rhport) +{ + volatile musb_dcd_ctl_regs_t *regs = (volatile musb_dcd_ctl_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->faddr)); + return regs; +} + +static inline volatile musb_dcd_epn_regs_t* musb_dcd_epn_regs(uint8_t rhport, unsigned epnum) +{ + //Need to set index to map EP registers + musb_periph_inst[rhport]->index = epnum; + volatile musb_dcd_epn_regs_t *regs = (volatile musb_dcd_epn_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->inmaxp)); + return regs; +} + +static inline volatile musb_dcd_ep0_regs_t* musb_dcd_ep0_regs(uint8_t rhport) +{ + //Need to set index to map EP0 registers + musb_periph_inst[rhport]->index = 0; + volatile musb_dcd_ep0_regs_t *regs = (volatile musb_dcd_ep0_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->csr0)); + return regs; +} + +static volatile void *musb_dcd_ep_get_fifo_ptr(uint8_t rhport, unsigned epnum) +{ + volatile uint32_t *ptr; + + ptr = &(musb_periph_inst[rhport]->fifo0); + ptr += epnum; + + return (volatile void *) ptr; +} + + +static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) +{ + (void)mps; + + //Most likely the caller has already grabbed the right register block. But + //as a precaution save and restore the register bank anyways + unsigned saved_index = musb_periph_inst[rhport]->index; + + musb_periph_inst[rhport]->index = epnum; + + //Disable double buffering + if(dir_in) { + musb_periph_inst[rhport]->incsru |= (MXC_F_USBHS_INCSRU_DPKTBUFDIS | MXC_F_USBHS_INCSRU_MODE); + } else { + musb_periph_inst[rhport]->outcsru |= (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS); + } + + musb_periph_inst[rhport]->index = saved_index; +} + +static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in) +{ + //Most likely the caller has already grabbed the right register block. But + //as a precaution save and restore the register bank anyways + unsigned saved_index = musb_periph_inst[rhport]->index; + + musb_periph_inst[rhport]->index = epnum; + + //Disable double buffering + if(dir_in) { + musb_periph_inst[rhport]->incsru |= (MXC_F_USBHS_INCSRU_DPKTBUFDIS); + } else { + musb_periph_inst[rhport]->outcsru |= (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS); + } + + musb_periph_inst[rhport]->index = saved_index; +} + +#endif // CFG_TUD_ENABLED + +#ifdef __cplusplus + } +#endif + +#endif // _TUSB_MUSB_MAX32_H_ diff --git a/src/portable/mentor/musb/musb_msp432e.h b/src/portable/mentor/musb/musb_msp432e.h deleted file mode 100644 index fce21de88..000000000 --- a/src/portable/mentor/musb/musb_msp432e.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2021, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifndef _TUSB_MUSB_MSP432E_H_ -#define _TUSB_MUSB_MSP432E_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -#include "msp.h" - -#ifdef __cplusplus - } -#endif - -#endif diff --git a/src/portable/mentor/musb/musb_ti.h b/src/portable/mentor/musb/musb_ti.h new file mode 100644 index 000000000..dbf82f391 --- /dev/null +++ b/src/portable/mentor/musb/musb_ti.h @@ -0,0 +1,285 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024, Brent Kowal (Analog Devices, Inc) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef _TUSB_MUSB_TI_H_ +#define _TUSB_MUSB_TI_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#if CFG_TUSB_MCU == OPT_MCU_TM4C123 + #include "TM4C123.h" + #define FIFO0_WORD FIFO0 + #define FIFO1_WORD FIFO1 +//#elif CFG_TUSB_MCU == OPT_MCU_TM4C129 +#elif CFG_TUSB_MCU == OPT_MCU_MSP432E4 + #include "msp.h" +#else + #error "Unsupported MCUs" +#endif + + +// Header supports both device and host modes. Only include whats necessary +#if CFG_TUD_ENABLED + +// Mapping of peripheral instances to port. Currently just 1. +static USB0_Type* const musb_periph_inst[] = { + USB0 +}; + +// Mapping of IRQ numbers to port. Currently just 1. +static const IRQn_Type musb_irqs[] = { + USB0_IRQn +}; + +static inline void musb_dcd_phy_init(uint8_t rhport){ + (void)rhport; + //Nothing to do for this part +} + +TU_ATTR_ALWAYS_INLINE +static inline void musb_dcd_int_enable(uint8_t rhport) +{ + NVIC_EnableIRQ(musb_irqs[rhport]); +} + +TU_ATTR_ALWAYS_INLINE +static inline void musb_dcd_int_disable(uint8_t rhport) +{ + NVIC_DisableIRQ(musb_irqs[rhport]); +} + +TU_ATTR_ALWAYS_INLINE +static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) +{ + return NVIC_GetEnableIRQ(musb_irqs[rhport]); +} + +TU_ATTR_ALWAYS_INLINE +static inline void musb_dcd_int_clear(uint8_t rhport) +{ + NVIC_ClearPendingIRQ(musb_irqs[rhport]); +} + +static inline void musb_dcd_int_handler_enter(uint8_t rhport){ + (void)rhport; + //Nothing to do for this part +} + +static inline void musb_dcd_int_handler_exit(uint8_t rhport){ + (void)rhport; + //Nothing to do for this part +} + +static inline volatile musb_dcd_ctl_regs_t* musb_dcd_ctl_regs(uint8_t rhport) +{ + volatile musb_dcd_ctl_regs_t *regs = (volatile musb_dcd_ctl_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->FADDR)); + return regs; +} + +static inline volatile musb_dcd_epn_regs_t* musb_dcd_epn_regs(uint8_t rhport, unsigned epnum) +{ + uintptr_t baseptr = (uintptr_t)&(musb_periph_inst[rhport]->TXMAXP1); + + //On the TI parts, the epn registers are 16-bytes apart. The core regs defined + //by musb_dcd_epn_regs and 6 reserved/other use bytes + volatile musb_dcd_epn_regs_t *regs = (volatile musb_dcd_epn_regs_t*)(baseptr + ((epnum - 1)*16)); + return regs; +} + +static inline volatile musb_dcd_ep0_regs_t* musb_dcd_ep0_regs(uint8_t rhport) +{ + volatile musb_dcd_ep0_regs_t *regs = (volatile musb_dcd_ep0_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->CSRL0)); + return regs; +} + +static volatile void *musb_dcd_ep_get_fifo_ptr(uint8_t rhport, unsigned epnum) +{ + if(epnum){ + return (volatile void *)(&(musb_periph_inst[rhport]->FIFO1_WORD) + (epnum - 1)); + } else { + return (volatile void *)&(musb_periph_inst[rhport]->FIFO0_WORD); + } +} + + +typedef struct { + uint_fast16_t beg; /* offset of including first element */ + uint_fast16_t end; /* offset of excluding the last element */ +} free_block_t; + +static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr) +{ + free_block_t *cur = beg; + for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ; + return cur; +} + +static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size) +{ + free_block_t *p = find_containing_block(blks, blks + num, addr); + TU_ASSERT(p != blks + num, -2); + if (p->beg == addr) { + /* Shrink block */ + p->beg = addr + size; + if (p->beg != p->end) return 0; + /* remove block */ + free_block_t *end = blks + num; + while (p + 1 < end) { + *p = *(p + 1); + ++p; + } + return -1; + } else { + /* Split into 2 blocks */ + free_block_t tmp = { + .beg = addr + size, + .end = p->end + }; + p->end = addr; + if (p->beg == p->end) { + if (tmp.beg != tmp.end) { + *p = tmp; + return 0; + } + /* remove block */ + free_block_t *end = blks + num; + while (p + 1 < end) { + *p = *(p + 1); + ++p; + } + return -1; + } + if (tmp.beg == tmp.end) return 0; + blks[num] = tmp; + return 1; + } +} + +static inline unsigned free_block_size(free_block_t const *blk) +{ + return blk->end - blk->beg; +} + +#if 0 +static inline void print_block_list(free_block_t const *blk, unsigned num) +{ + TU_LOG1("*************\r\n"); + for (unsigned i = 0; i < num; ++i) { + TU_LOG1(" Blk%u %u %u\r\n", i, blk->beg, blk->end); + ++blk; + } +} +#else +#define print_block_list(a,b) +#endif + +static unsigned find_free_memory(uint8_t rhport, uint_fast16_t size_in_log2_minus3) +{ + free_block_t free_blocks[2 * (TUP_DCD_ENDPOINT_MAX - 1)]; + unsigned num_blocks = 1; + + /* Initialize free memory block list */ + free_blocks[0].beg = 64 / 8; + free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */ + for (int i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { + uint_fast16_t addr; + int num; + musb_periph_inst[rhport]->EPIDX = i; + addr = musb_periph_inst[rhport]->TXFIFOADD; + if (addr) { + unsigned sz = musb_periph_inst[rhport]->TXFIFOSZ; + unsigned sft = (sz & USB_TXFIFOSZ_SIZE_M) + ((sz & USB_TXFIFOSZ_DPB) ? 1: 0); + num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); + TU_ASSERT(-2 < num, 0); + num_blocks += num; + print_block_list(free_blocks, num_blocks); + } + addr = musb_periph_inst[rhport]->RXFIFOADD; + if (addr) { + unsigned sz = musb_periph_inst[rhport]->RXFIFOSZ; + unsigned sft = (sz & USB_RXFIFOSZ_SIZE_M) + ((sz & USB_RXFIFOSZ_DPB) ? 1: 0); + num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); + TU_ASSERT(-2 < num, 0); + num_blocks += num; + print_block_list(free_blocks, num_blocks); + } + } + print_block_list(free_blocks, num_blocks); + + /* Find the best fit memory block */ + uint_fast16_t size_in_8byte_unit = 1 << size_in_log2_minus3; + free_block_t const *min = NULL; + uint_fast16_t min_sz = 0xFFFFu; + free_block_t const *end = &free_blocks[num_blocks]; + for (free_block_t const *cur = &free_blocks[0]; cur < end; ++cur) { + uint_fast16_t sz = free_block_size(cur); + if (sz < size_in_8byte_unit) continue; + if (size_in_8byte_unit == sz) return cur->beg; + if (sz < min_sz) min = cur; + } + TU_ASSERT(min, 0); + return min->beg; +} + + +static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) +{ + int size_in_log2_minus3 = 28 - TU_MIN(28, __CLZ((uint32_t)mps)); + if ((8u << size_in_log2_minus3) < mps) ++size_in_log2_minus3; + unsigned addr = find_free_memory(rhport, size_in_log2_minus3); + TU_ASSERT(addr,); + + musb_periph_inst[rhport]->EPIDX = epnum; + if (dir_in) { + musb_periph_inst[rhport]->TXFIFOADD = addr; + musb_periph_inst[rhport]->TXFIFOSZ = size_in_log2_minus3; + } else { + musb_periph_inst[rhport]->RXFIFOADD = addr; + musb_periph_inst[rhport]->RXFIFOSZ = size_in_log2_minus3; + } +} + +static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in) +{ + musb_periph_inst[rhport]->EPIDX = epnum; + if (dir_in) { + musb_periph_inst[rhport]->TXFIFOADD = 0; + musb_periph_inst[rhport]->TXFIFOSZ = 0; + } else { + musb_periph_inst[rhport]->RXFIFOADD = 0; + musb_periph_inst[rhport]->RXFIFOSZ = 0; + } +} + +#endif // CFG_TUD_ENABLED + +#ifdef __cplusplus + } +#endif + +#endif // _TUSB_MUSB_TI_H_ diff --git a/src/portable/mentor/musb/musb_tm4c.h b/src/portable/mentor/musb/musb_tm4c.h deleted file mode 100644 index 65a1751b0..000000000 --- a/src/portable/mentor/musb/musb_tm4c.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2021, Ha Thach (tinyusb.org) - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#ifndef _TUSB_MUSB_TM4C_H_ -#define _TUSB_MUSB_TM4C_H_ - -#ifdef __cplusplus - extern "C" { -#endif - -#if CFG_TUSB_MCU == OPT_MCU_TM4C123 - #include "TM4C123.h" -//#elif CFG_TUSB_MCU == OPT_MCU_TM4C129 -#else - #error "Unsupported MCUs" -#endif - -#ifdef __cplusplus - } -#endif - -#endif diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h index 8f83305a5..e8af8f19b 100644 --- a/src/portable/mentor/musb/musb_type.h +++ b/src/portable/mentor/musb/musb_type.h @@ -35,10 +35,43 @@ #ifndef _TUSB_MUSB_TYPE_H_ #define _TUSB_MUSB_TYPE_H_ +#include "stdint.h" + #ifdef __cplusplus extern "C" { #endif +// Endpoint register mapping. Non-zero end points. +typedef struct TU_ATTR_PACKED { + uint16_t TXMAXP; + uint8_t TXCSRL; + uint8_t TXCSRH; + uint16_t RXMAXP; + uint8_t RXCSRL; + uint8_t RXCSRH; + uint16_t RXCOUNT; +} musb_dcd_epn_regs_t; + +// Endpoint 0 register mapping. +typedef struct TU_ATTR_PACKED { + uint8_t CSRL0; + uint8_t CSRH0; + uint32_t RESERVED; + uint8_t COUNT0; +} musb_dcd_ep0_regs_t; + +// Control register mapping +typedef struct TU_ATTR_PACKED { + uint8_t FADDR; + uint8_t POWER; + uint16_t TXIS; + uint16_t RXIS; + uint16_t TXIE; + uint16_t RXIE; + uint8_t IS; + uint8_t IE; +} musb_dcd_ctl_regs_t; + //***************************************************************************** // // The following are defines for the bit fields in the USB_O_FADDR register. -- cgit v1.3.1 From f6b96f7ea9f0d0c4872e1e290bf59f65c68a7bf3 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 14 Aug 2024 22:56:59 +0700 Subject: fix spelling, add max32 to ci with arm-gcc build --- .github/workflows/ci_set_matrix.py | 1 + src/portable/mentor/musb/musb_ti.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'src/portable') diff --git a/.github/workflows/ci_set_matrix.py b/.github/workflows/ci_set_matrix.py index a56bd4214..c9698c934 100644 --- a/.github/workflows/ci_set_matrix.py +++ b/.github/workflows/ci_set_matrix.py @@ -22,6 +22,7 @@ family_list = { "lpc11 lpc13 lpc15": ["arm-gcc", "arm-clang"], "lpc17 lpc18 lpc40 lpc43": ["arm-gcc", "arm-clang"], "lpc51 lpc54 lpc55": ["arm-gcc", "arm-clang"], + "max32650 max32666 max32690 max78002": ["arm-gcc"], "mcx": ["arm-gcc"], "mm32": ["arm-gcc"], "msp430": ["msp430-gcc"], diff --git a/src/portable/mentor/musb/musb_ti.h b/src/portable/mentor/musb/musb_ti.h index dbf82f391..4c9f00278 100644 --- a/src/portable/mentor/musb/musb_ti.h +++ b/src/portable/mentor/musb/musb_ti.h @@ -43,7 +43,7 @@ #endif -// Header supports both device and host modes. Only include whats necessary +// Header supports both device and host modes. Only include what's necessary #if CFG_TUD_ENABLED // Mapping of peripheral instances to port. Currently just 1. -- cgit v1.3.1 From 0be427bae95ef0fe94cb6f0b405eb5c3bbae160a Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 14 Aug 2024 23:59:35 +0700 Subject: use max32 cmsis, fix NVIC_GetEnableIRQ() not defined when using with CMISIS < 5 --- hw/bsp/max32650/family.c | 16 ++++++++++++++-- hw/bsp/max32650/family.cmake | 1 - hw/bsp/max32650/family.mk | 3 +-- hw/bsp/max32666/family.c | 15 +++++++++++++-- hw/bsp/max32666/family.cmake | 1 - hw/bsp/max32666/family.mk | 1 - hw/bsp/max32690/family.c | 16 ++++++++++++++-- hw/bsp/max32690/family.cmake | 1 - hw/bsp/max32690/family.mk | 1 - hw/bsp/max78002/family.c | 15 +++++++++++++-- hw/bsp/max78002/family.cmake | 1 - hw/bsp/max78002/family.mk | 1 - src/portable/mentor/musb/musb_max32.h | 33 ++++++++++++++------------------- tools/get_deps.py | 2 +- 14 files changed, 70 insertions(+), 37 deletions(-) (limited to 'src/portable') diff --git a/hw/bsp/max32650/family.c b/hw/bsp/max32650/family.c index 16b5233b9..89a5db160 100644 --- a/hw/bsp/max32650/family.c +++ b/hw/bsp/max32650/family.c @@ -24,12 +24,24 @@ * This file is part of the TinyUSB stack. */ -#include "board.h" -#include "bsp/board_api.h" +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() +#endif + #include "gpio.h" +#include "mxc_sys.h" #include "mxc_device.h" #include "uart.h" +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "board.h" +#include "bsp/board_api.h" + + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ diff --git a/hw/bsp/max32650/family.cmake b/hw/bsp/max32650/family.cmake index 92b68a1cd..8c4f286a2 100644 --- a/hw/bsp/max32650/family.cmake +++ b/hw/bsp/max32650/family.cmake @@ -74,7 +74,6 @@ function(add_board_target BOARD_TARGET) ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMSIS_5}/CMSIS/Core/Include ${MAX32_CMSIS}/Include ${MAX32_CMSIS}/Device/Maxim/MAX32650/Include ${MAX32_PERIPH}/Include/MAX32650 diff --git a/hw/bsp/max32650/family.mk b/hw/bsp/max32650/family.mk index 359261216..d2fc293e4 100644 --- a/hw/bsp/max32650/family.mk +++ b/hw/bsp/max32650/family.mk @@ -82,14 +82,13 @@ SRC_C += \ $(PERIPH_SRC)/ICC/icc_reva.c \ $(PERIPH_SRC)/ICC/icc_common.c \ $(PERIPH_SRC)/TPU/tpu_me10.c \ - $(PERIPH_SRC)/TPU/tpu_reva.c \ + $(PERIPH_SRC)/TPU/tpu_reva.c \ $(PERIPH_SRC)/UART/uart_common.c \ $(PERIPH_SRC)/UART/uart_me10.c \ $(PERIPH_SRC)/UART/uart_reva.c \ INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(MAX32_CMSIS)/Include \ $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32650/Include \ $(TOP)/$(MAX32_PERIPH)/Include/MAX32650 \ diff --git a/hw/bsp/max32666/family.c b/hw/bsp/max32666/family.c index 1398e09ff..8ee4b6762 100644 --- a/hw/bsp/max32666/family.c +++ b/hw/bsp/max32666/family.c @@ -24,13 +24,24 @@ * This file is part of the TinyUSB stack. */ -#include "board.h" -#include "bsp/board_api.h" +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() +#endif + #include "gpio.h" +#include "mxc_sys.h" #include "mcr_regs.h" #include "mxc_device.h" #include "uart.h" +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "board.h" +#include "bsp/board_api.h" + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ diff --git a/hw/bsp/max32666/family.cmake b/hw/bsp/max32666/family.cmake index eb9d2175f..4a3f1a428 100644 --- a/hw/bsp/max32666/family.cmake +++ b/hw/bsp/max32666/family.cmake @@ -70,7 +70,6 @@ function(add_board_target BOARD_TARGET) ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMSIS_5}/CMSIS/Core/Include ${MAX32_CMSIS}/Include ${MAX32_CMSIS}/Device/Maxim/MAX32665/Include ${MAX32_PERIPH}/Include/MAX32665 diff --git a/hw/bsp/max32666/family.mk b/hw/bsp/max32666/family.mk index 720d994ef..b4f7d1e57 100644 --- a/hw/bsp/max32666/family.mk +++ b/hw/bsp/max32666/family.mk @@ -82,7 +82,6 @@ SRC_C += \ INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(MAX32_CMSIS)/Include \ $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32665/Include \ $(TOP)/$(MAX32_PERIPH)/Include/MAX32665 \ diff --git a/hw/bsp/max32690/family.c b/hw/bsp/max32690/family.c index f4998bdbe..2418168d4 100644 --- a/hw/bsp/max32690/family.c +++ b/hw/bsp/max32690/family.c @@ -24,13 +24,25 @@ * This file is part of the TinyUSB stack. */ -#include "board.h" -#include "bsp/board_api.h" +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() +#endif + #include "gpio.h" +#include "mxc_sys.h" #include "mcr_regs.h" #include "mxc_device.h" #include "uart.h" +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "board.h" +#include "bsp/board_api.h" + + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake index 2a9422dbe..58647e432 100644 --- a/hw/bsp/max32690/family.cmake +++ b/hw/bsp/max32690/family.cmake @@ -75,7 +75,6 @@ function(add_board_target BOARD_TARGET) ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMSIS_5}/CMSIS/Core/Include ${MAX32_CMSIS}/Include ${MAX32_CMSIS}/Device/Maxim/MAX32690/Include ${MAX32_PERIPH}/Include/MAX32690 diff --git a/hw/bsp/max32690/family.mk b/hw/bsp/max32690/family.mk index c533cf4a4..d4df8ef2f 100644 --- a/hw/bsp/max32690/family.mk +++ b/hw/bsp/max32690/family.mk @@ -90,7 +90,6 @@ SRC_C += \ INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(MAX32_CMSIS)/Include \ $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX32690/Include \ $(TOP)/$(MAX32_PERIPH)/Include/MAX32690 \ diff --git a/hw/bsp/max78002/family.c b/hw/bsp/max78002/family.c index 7758083a2..8d51f141c 100644 --- a/hw/bsp/max78002/family.c +++ b/hw/bsp/max78002/family.c @@ -24,13 +24,24 @@ * This file is part of the TinyUSB stack. */ -#include "board.h" -#include "bsp/board_api.h" +#ifdef __GNUC__ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wstrict-prototypes" // _mxc_crit_get_state() +#endif + #include "gpio.h" +#include "mxc_sys.h" #include "mcr_regs.h" #include "mxc_device.h" #include "uart.h" +#ifdef __GNUC__ +#pragma GCC diagnostic pop +#endif + +#include "board.h" +#include "bsp/board_api.h" + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ diff --git a/hw/bsp/max78002/family.cmake b/hw/bsp/max78002/family.cmake index 090f1da43..446930bd8 100644 --- a/hw/bsp/max78002/family.cmake +++ b/hw/bsp/max78002/family.cmake @@ -72,7 +72,6 @@ function(add_board_target BOARD_TARGET) ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${CMSIS_5}/CMSIS/Core/Include ${MAX32_CMSIS}/Include ${MAX32_CMSIS}/Device/Maxim/MAX78002/Include ${MAX32_PERIPH}/Include/MAX78002 diff --git a/hw/bsp/max78002/family.mk b/hw/bsp/max78002/family.mk index 5297815de..997816261 100644 --- a/hw/bsp/max78002/family.mk +++ b/hw/bsp/max78002/family.mk @@ -87,7 +87,6 @@ SRC_C += \ INC += \ $(TOP)/$(BOARD_PATH) \ - $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ $(TOP)/$(MAX32_CMSIS)/Include \ $(TOP)/$(MAX32_CMSIS)/Device/Maxim/MAX78002/Include \ $(TOP)/$(MAX32_PERIPH)/Include/MAX78002 \ diff --git a/src/portable/mentor/musb/musb_max32.h b/src/portable/mentor/musb/musb_max32.h index 297a695f8..bc6ce76dd 100644 --- a/src/portable/mentor/musb/musb_max32.h +++ b/src/portable/mentor/musb/musb_max32.h @@ -31,13 +31,8 @@ extern "C" { #endif -#if TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX78002) - #include "mxc_device.h" - #include "usbhs_regs.h" -#else - #error "Unsupported MCUs" -#endif - +#include "mxc_device.h" +#include "usbhs_regs.h" #if CFG_TUD_ENABLED #define USBHS_M31_CLOCK_RECOVERY @@ -48,39 +43,39 @@ static mxc_usbhs_regs_t* const musb_periph_inst[] = { }; // Mapping of IRQ numbers to port. Currently just 1. -static const IRQn_Type musb_irqs[] = { +static const IRQn_Type musb_irqs[] = { USB_IRQn }; TU_ATTR_ALWAYS_INLINE -static inline void musb_dcd_int_enable(uint8_t rhport) -{ +static inline void musb_dcd_int_enable(uint8_t rhport) { NVIC_EnableIRQ(musb_irqs[rhport]); } TU_ATTR_ALWAYS_INLINE -static inline void musb_dcd_int_disable(uint8_t rhport) -{ +static inline void musb_dcd_int_disable(uint8_t rhport) { NVIC_DisableIRQ(musb_irqs[rhport]); } TU_ATTR_ALWAYS_INLINE -static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) -{ +static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) { + #ifdef NVIC_GetEnableIRQ // only defined in CMSIS 5 return NVIC_GetEnableIRQ(musb_irqs[rhport]); + #else + uint32_t IRQn = (uint32_t) musb_irqs[rhport]; + return ((NVIC->ISER[IRQn >> 5UL] & (1UL << (IRQn & 0x1FUL))) != 0UL) ? 1UL : 0UL; + #endif } TU_ATTR_ALWAYS_INLINE -static inline void musb_dcd_int_clear(uint8_t rhport) -{ - NVIC_ClearPendingIRQ(musb_irqs[rhport]); +static inline void musb_dcd_int_clear(uint8_t rhport) { + NVIC_ClearPendingIRQ(musb_irqs[rhport]); } //Used to save and restore user's register map when interrupt occurs static volatile unsigned isr_saved_index = 0; -static inline void musb_dcd_int_handler_enter(uint8_t rhport) -{ +static inline void musb_dcd_int_handler_enter(uint8_t rhport) { uint32_t mxm_int, mxm_int_en, mxm_is; //save current register index diff --git a/tools/get_deps.py b/tools/get_deps.py index 51d6304ae..f141d3d41 100644 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -26,7 +26,7 @@ deps_optional = { 'fc100s'], 'hw/mcu/analog/max32' : ['https://github.com/analogdevicesinc/msdk.git', 'b20b398d3e5e2007594e54a74ba3d2a2e50ddd75', - 'max32690 max32650 max32666 max78002'], + 'max32650 max32666 max32690 max78002'], 'hw/mcu/bridgetek/ft9xx/ft90x-sdk': ['https://github.com/BRTSG-FOSS/ft90x-sdk.git', '91060164afe239fcb394122e8bf9eb24d3194eb1', 'brtmm90x'], -- cgit v1.3.1 From a9df933e0d35c1c198343464d49e69eff20dde4a Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 15 Aug 2024 15:24:04 +0700 Subject: add TUP_USBIP_MUSB macro, minor rename --- src/common/tusb_mcu.h | 6 ++--- src/portable/mentor/musb/dcd_musb.c | 50 +++++++++++++++++------------------ src/portable/mentor/musb/musb_max32.h | 18 ++++++------- src/portable/mentor/musb/musb_ti.h | 18 ++++++------- src/portable/mentor/musb/musb_type.h | 6 ++--- 5 files changed, 49 insertions(+), 49 deletions(-) (limited to 'src/portable') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 259b9e002..7ec3c5842 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -308,6 +308,7 @@ #define TUP_DCD_ENDPOINT_MAX 8 #elif TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) + #define TUP_USBIP_MUSB #define TUP_DCD_ENDPOINT_MAX 8 //--------------------------------------------------------------------+ @@ -471,12 +472,11 @@ //--------------------------------------------------------------------+ // Analog Devices //--------------------------------------------------------------------+ -#elif TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32666, \ - OPT_MCU_MAX32650, OPT_MCU_MAX78002) +#elif TU_CHECK_MCU(OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX32690, OPT_MCU_MAX78002) + #define TUP_USBIP_MUSB #define TUP_DCD_ENDPOINT_MAX 12 #define TUP_RHPORT_HIGHSPEED 1 - #endif //--------------------------------------------------------------------+ diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index ee36656fd..80dfb9235 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -27,7 +27,7 @@ #include "tusb_option.h" -#if CFG_TUD_ENABLED +#if CFG_TUD_ENABLED && defined(TUP_USBIP_MUSB) #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) /* GCC warns that an address may be unaligned, even though @@ -155,7 +155,7 @@ static void process_setup_packet(uint8_t rhport) { uint32_t *p = (void*)&_dcd.setup_packet; volatile uint32_t *fifo_ptr = musb_dcd_ep_get_fifo_ptr(rhport, 0); - volatile musb_dcd_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); + volatile musb_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); p[0] = *fifo_ptr; p[1] = *fifo_ptr; @@ -183,7 +183,7 @@ static bool handle_xfer_in(uint8_t rhport, uint_fast8_t ep_addr) return true; } - volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epnum); + volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epnum); const unsigned mps = regs->TXMAXP; const unsigned len = TU_MIN(mps, rem); void *buf = pipe->buf; @@ -208,7 +208,7 @@ static bool handle_xfer_out(uint8_t rhport, uint_fast8_t ep_addr) unsigned epnum = tu_edpt_number(ep_addr); unsigned epnum_minus1 = epnum - 1; pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; - volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epnum); + volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epnum); // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, regs->RXCSRL); TU_ASSERT(regs->RXCSRL & USB_RXCSRL1_RXRDY); @@ -250,7 +250,7 @@ static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16 if (dir_in) { handle_xfer_in(rhport, ep_addr); } else { - volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epnum); + volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epnum); if (regs->RXCSRL & USB_RXCSRL1_RXRDY) regs->RXCSRL = 0; } return true; @@ -260,7 +260,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ { (void)rhport; TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */ - volatile musb_dcd_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); + volatile musb_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); const unsigned req = _dcd.setup_packet.bmRequestType; TU_ASSERT(req != REQUEST_TYPE_INVALID || total_bytes == 0); @@ -325,7 +325,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ static void process_ep0(uint8_t rhport) { - volatile musb_dcd_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); + volatile musb_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); uint_fast8_t csrl = ep0_regs->CSRL0; // TU_LOG1(" EP0 ep0_regs->CSRL0 = %x\r\n", csrl); @@ -381,7 +381,7 @@ static void process_ep0(uint8_t rhport) return; } - volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); /* When CSRL0 is zero, it means that completion of sending a any length packet * or receiving a zero length packet. */ @@ -415,7 +415,7 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) const unsigned epn = tu_edpt_number(ep_addr); const unsigned epn_minus1 = epn - 1; - volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); + volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); if (dir_in) { // TU_LOG1(" TXCSRL%d = %x\r\n", epn, regs->TXCSRL); if (regs->TXCSRL & USB_TXCSRL1_STALLED) { @@ -442,7 +442,7 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) static void process_bus_reset(uint8_t rhport) { - volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), * a control transfer state is SETUP or STATUS stage. */ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; @@ -467,7 +467,7 @@ static void process_bus_reset(uint8_t rhport) void dcd_init(uint8_t rhport) { - volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); ctrl_regs->IE |= USB_IE_SUSPND; musb_dcd_int_clear(rhport); musb_dcd_phy_init(rhport); @@ -488,7 +488,7 @@ void dcd_int_disable(uint8_t rhport) void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { (void)dev_addr; - volatile musb_dcd_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); + volatile musb_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); _dcd.pipe0.buf = NULL; _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; @@ -499,7 +499,7 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) // Wake up host void dcd_remote_wakeup(uint8_t rhport) { - volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); ctrl_regs->POWER |= USB_POWER_RESUME; unsigned cnt = SystemCoreClock / 1000; @@ -511,7 +511,7 @@ void dcd_remote_wakeup(uint8_t rhport) // Connect by enabling internal pull-up resistor on D+/D- void dcd_connect(uint8_t rhport) { - volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); ctrl_regs->POWER |= TUD_OPT_HIGH_SPEED ? USB_POWER_HSENAB : 0; ctrl_regs->POWER |= USB_POWER_SOFTCONN; } @@ -519,7 +519,7 @@ void dcd_connect(uint8_t rhport) // Disconnect by disabling internal pull-up resistor on D+/D- void dcd_disconnect(uint8_t rhport) { - volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); ctrl_regs->POWER &= ~USB_POWER_SOFTCONN; } @@ -551,8 +551,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) pipe->length = 0; pipe->remaining = 0; - volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); - volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); + volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); if (dir_in) { regs->TXMAXP = mps; regs->TXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_TXCSRH1_ISO : 0; @@ -579,8 +579,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) void dcd_edpt_close_all(uint8_t rhport) { - volatile musb_dcd_epn_regs_t *regs; - volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + volatile musb_epn_regs_t *regs; + volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); ctrl_regs->TXIE = 1; /* Enable only EP0 */ @@ -613,8 +613,8 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) unsigned const epn = tu_edpt_number(ep_addr); unsigned const dir_in = tu_edpt_dir(ep_addr); - volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); - volatile musb_dcd_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); + volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); if (dir_in) { @@ -679,14 +679,14 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); if (0 == epn) { - volatile musb_dcd_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); + volatile musb_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); if (!ep_addr) { /* Ignore EP80 */ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; _dcd.pipe0.buf = NULL; ep0_regs->CSRL0 = USB_CSRL0_STALL; } } else { - volatile musb_dcd_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); + volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); if (tu_edpt_dir(ep_addr)) { /* IN */ regs->TXCSRL = USB_TXCSRL1_STALL; } else { /* OUT */ @@ -702,7 +702,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { (void)rhport; unsigned const epn = tu_edpt_number(ep_addr); - musb_dcd_epn_regs_t volatile *regs = musb_dcd_epn_regs(rhport, epn); + musb_epn_regs_t volatile *regs = musb_dcd_epn_regs(rhport, epn); unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); if (tu_edpt_dir(ep_addr)) { /* IN */ @@ -719,7 +719,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) void dcd_int_handler(uint8_t rhport) { uint_fast8_t is, txis, rxis; - volatile musb_dcd_ctl_regs_t *ctrl_regs; + volatile musb_ctl_regs_t *ctrl_regs; //Part specific ISR setup/entry musb_dcd_int_handler_enter(rhport); diff --git a/src/portable/mentor/musb/musb_max32.h b/src/portable/mentor/musb/musb_max32.h index bc6ce76dd..0712aeda4 100644 --- a/src/portable/mentor/musb/musb_max32.h +++ b/src/portable/mentor/musb/musb_max32.h @@ -24,8 +24,8 @@ * This file is part of the TinyUSB stack. */ -#ifndef _TUSB_MUSB_MAX32_H_ -#define _TUSB_MUSB_MAX32_H_ +#ifndef TUSB_MUSB_MAX32_H_ +#define TUSB_MUSB_MAX32_H_ #ifdef __cplusplus extern "C" { @@ -136,25 +136,25 @@ static inline void musb_dcd_phy_init(uint8_t rhport) musb_periph_inst[rhport]->m31_phy_ponrst = 1; } -static inline volatile musb_dcd_ctl_regs_t* musb_dcd_ctl_regs(uint8_t rhport) +static inline volatile musb_ctl_regs_t* musb_dcd_ctl_regs(uint8_t rhport) { - volatile musb_dcd_ctl_regs_t *regs = (volatile musb_dcd_ctl_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->faddr)); + volatile musb_ctl_regs_t *regs = (volatile musb_ctl_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->faddr)); return regs; } -static inline volatile musb_dcd_epn_regs_t* musb_dcd_epn_regs(uint8_t rhport, unsigned epnum) +static inline volatile musb_epn_regs_t* musb_dcd_epn_regs(uint8_t rhport, unsigned epnum) { //Need to set index to map EP registers musb_periph_inst[rhport]->index = epnum; - volatile musb_dcd_epn_regs_t *regs = (volatile musb_dcd_epn_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->inmaxp)); + volatile musb_epn_regs_t *regs = (volatile musb_epn_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->inmaxp)); return regs; } -static inline volatile musb_dcd_ep0_regs_t* musb_dcd_ep0_regs(uint8_t rhport) +static inline volatile musb_ep0_regs_t* musb_dcd_ep0_regs(uint8_t rhport) { //Need to set index to map EP0 registers musb_periph_inst[rhport]->index = 0; - volatile musb_dcd_ep0_regs_t *regs = (volatile musb_dcd_ep0_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->csr0)); + volatile musb_ep0_regs_t *regs = (volatile musb_ep0_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->csr0)); return regs; } @@ -213,4 +213,4 @@ static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned } #endif -#endif // _TUSB_MUSB_MAX32_H_ +#endif // TUSB_MUSB_MAX32_H_ diff --git a/src/portable/mentor/musb/musb_ti.h b/src/portable/mentor/musb/musb_ti.h index 4c9f00278..ec0a267b1 100644 --- a/src/portable/mentor/musb/musb_ti.h +++ b/src/portable/mentor/musb/musb_ti.h @@ -24,8 +24,8 @@ * This file is part of the TinyUSB stack. */ -#ifndef _TUSB_MUSB_TI_H_ -#define _TUSB_MUSB_TI_H_ +#ifndef TUSB_MUSB_TI_H_ +#define TUSB_MUSB_TI_H_ #ifdef __cplusplus extern "C" { @@ -95,25 +95,25 @@ static inline void musb_dcd_int_handler_exit(uint8_t rhport){ //Nothing to do for this part } -static inline volatile musb_dcd_ctl_regs_t* musb_dcd_ctl_regs(uint8_t rhport) +static inline volatile musb_ctl_regs_t* musb_dcd_ctl_regs(uint8_t rhport) { - volatile musb_dcd_ctl_regs_t *regs = (volatile musb_dcd_ctl_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->FADDR)); + volatile musb_ctl_regs_t *regs = (volatile musb_ctl_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->FADDR)); return regs; } -static inline volatile musb_dcd_epn_regs_t* musb_dcd_epn_regs(uint8_t rhport, unsigned epnum) +static inline volatile musb_epn_regs_t* musb_dcd_epn_regs(uint8_t rhport, unsigned epnum) { uintptr_t baseptr = (uintptr_t)&(musb_periph_inst[rhport]->TXMAXP1); //On the TI parts, the epn registers are 16-bytes apart. The core regs defined //by musb_dcd_epn_regs and 6 reserved/other use bytes - volatile musb_dcd_epn_regs_t *regs = (volatile musb_dcd_epn_regs_t*)(baseptr + ((epnum - 1)*16)); + volatile musb_epn_regs_t *regs = (volatile musb_epn_regs_t*)(baseptr + ((epnum - 1) * 16)); return regs; } -static inline volatile musb_dcd_ep0_regs_t* musb_dcd_ep0_regs(uint8_t rhport) +static inline volatile musb_ep0_regs_t* musb_dcd_ep0_regs(uint8_t rhport) { - volatile musb_dcd_ep0_regs_t *regs = (volatile musb_dcd_ep0_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->CSRL0)); + volatile musb_ep0_regs_t *regs = (volatile musb_ep0_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->CSRL0)); return regs; } @@ -282,4 +282,4 @@ static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned } #endif -#endif // _TUSB_MUSB_TI_H_ +#endif // TUSB_MUSB_TI_H_ diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h index e8af8f19b..d21dcd6da 100644 --- a/src/portable/mentor/musb/musb_type.h +++ b/src/portable/mentor/musb/musb_type.h @@ -50,7 +50,7 @@ typedef struct TU_ATTR_PACKED { uint8_t RXCSRL; uint8_t RXCSRH; uint16_t RXCOUNT; -} musb_dcd_epn_regs_t; +} musb_epn_regs_t; // Endpoint 0 register mapping. typedef struct TU_ATTR_PACKED { @@ -58,7 +58,7 @@ typedef struct TU_ATTR_PACKED { uint8_t CSRH0; uint32_t RESERVED; uint8_t COUNT0; -} musb_dcd_ep0_regs_t; +} musb_ep0_regs_t; // Control register mapping typedef struct TU_ATTR_PACKED { @@ -70,7 +70,7 @@ typedef struct TU_ATTR_PACKED { uint16_t RXIE; uint8_t IS; uint8_t IE; -} musb_dcd_ctl_regs_t; +} musb_ctl_regs_t; //***************************************************************************** // -- cgit v1.3.1 From e339702a2a7977e4e62c2f3fea9aca55f71190ee Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 15 Aug 2024 16:41:20 +0700 Subject: adding universal register structs for musb --- src/portable/mentor/musb/dcd_musb.c | 99 +++++++++++---------- src/portable/mentor/musb/musb_max32.h | 47 ++++------ src/portable/mentor/musb/musb_ti.h | 8 +- src/portable/mentor/musb/musb_type.h | 156 +++++++++++++++++++++++++++++++--- 4 files changed, 216 insertions(+), 94 deletions(-) (limited to 'src/portable') diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 80dfb9235..78fc3d616 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -54,6 +54,8 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); #error "Unsupported MCU" #endif +#define MUSB_REGS(rhport) ((musb_regs_t*) MUSB_BASES[rhport]) + /*------------------------------------------------------------------ * MACRO TYPEDEF CONSTANT ENUM DECLARATION *------------------------------------------------------------------*/ @@ -381,7 +383,7 @@ static void process_ep0(uint8_t rhport) return; } - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + musb_regs_t* musb_regs = MUSB_REGS(rhport); /* When CSRL0 is zero, it means that completion of sending a any length packet * or receiving a zero length packet. */ @@ -389,7 +391,7 @@ static void process_ep0(uint8_t rhport) /* STATUS IN */ if (*(const uint16_t*)(uintptr_t)&_dcd.setup_packet == 0x0500) { /* The address must be changed on completion of the control transfer. */ - ctrl_regs->FADDR = (uint8_t)_dcd.setup_packet.wValue; + musb_regs->faddr = (uint8_t)_dcd.setup_packet.wValue; } _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; dcd_event_xfer_complete(rhport, @@ -442,7 +444,7 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) static void process_bus_reset(uint8_t rhport) { - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + musb_regs_t* musb_regs = MUSB_REGS(rhport); /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), * a control transfer state is SETUP or STATUS stage. */ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; @@ -450,15 +452,15 @@ static void process_bus_reset(uint8_t rhport) /* When pipe0.buf has not NULL, DATA stage works in progress. */ _dcd.pipe0.buf = NULL; - ctrl_regs->TXIE = 1; /* Enable only EP0 */ - ctrl_regs->RXIE = 0; + musb_regs->intr_txen = 1; /* Enable only EP0 */ + musb_regs->intr_rxen = 0; /* Clear FIFO settings */ for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { musb_dcd_reset_fifo(rhport, i, 0); musb_dcd_reset_fifo(rhport, i, 1); } - dcd_event_bus_reset(rhport, (ctrl_regs->POWER & USB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); + dcd_event_bus_reset(rhport, (musb_regs->power & USB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); } /*------------------------------------------------------------------ @@ -467,8 +469,8 @@ static void process_bus_reset(uint8_t rhport) void dcd_init(uint8_t rhport) { - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); - ctrl_regs->IE |= USB_IE_SUSPND; + musb_regs_t* musb_regs = MUSB_REGS(rhport); + musb_regs->intrusben |= USB_IE_SUSPND; musb_dcd_int_clear(rhport); musb_dcd_phy_init(rhport); dcd_connect(rhport); @@ -497,30 +499,29 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) } // Wake up host -void dcd_remote_wakeup(uint8_t rhport) -{ - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); - ctrl_regs->POWER |= USB_POWER_RESUME; +void dcd_remote_wakeup(uint8_t rhport) { + musb_regs_t* musb_regs = MUSB_REGS(rhport); + musb_regs->power |= USB_POWER_RESUME; unsigned cnt = SystemCoreClock / 1000; while (cnt--) __NOP(); - ctrl_regs->POWER &= ~USB_POWER_RESUME; + musb_regs->power &= ~USB_POWER_RESUME; } // Connect by enabling internal pull-up resistor on D+/D- void dcd_connect(uint8_t rhport) { - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); - ctrl_regs->POWER |= TUD_OPT_HIGH_SPEED ? USB_POWER_HSENAB : 0; - ctrl_regs->POWER |= USB_POWER_SOFTCONN; + musb_regs_t* musb_regs = MUSB_REGS(rhport); + musb_regs->power |= TUD_OPT_HIGH_SPEED ? USB_POWER_HSENAB : 0; + musb_regs->power |= USB_POWER_SOFTCONN; } // Disconnect by disabling internal pull-up resistor on D+/D- void dcd_disconnect(uint8_t rhport) { - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); - ctrl_regs->POWER &= ~USB_POWER_SOFTCONN; + musb_regs_t* musb_regs = MUSB_REGS(rhport); + musb_regs->power &= ~USB_POWER_SOFTCONN; } void dcd_sof_enable(uint8_t rhport, bool en) @@ -552,23 +553,25 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) pipe->remaining = 0; volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + musb_regs_t* musb_regs = MUSB_REGS(rhport); if (dir_in) { regs->TXMAXP = mps; regs->TXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_TXCSRH1_ISO : 0; - if (regs->TXCSRL & USB_TXCSRL1_TXRDY) + if (regs->TXCSRL & USB_TXCSRL1_TXRDY) { regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; - else + } else { regs->TXCSRL = USB_TXCSRL1_CLRDT; - ctrl_regs->TXIE |= TU_BIT(epn); + } + musb_regs->intr_txen |= TU_BIT(epn); } else { regs->RXMAXP = mps; regs->RXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0; - if (regs->RXCSRL & USB_RXCSRL1_RXRDY) + if (regs->RXCSRL & USB_RXCSRL1_RXRDY) { regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; - else + } else { regs->RXCSRL = USB_RXCSRL1_CLRDT; - ctrl_regs->RXIE |= TU_BIT(epn); + } + musb_regs->intr_rxen |= TU_BIT(epn); } /* Setup FIFO */ @@ -580,11 +583,11 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) void dcd_edpt_close_all(uint8_t rhport) { volatile musb_epn_regs_t *regs; - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + musb_regs_t* musb_regs = MUSB_REGS(rhport); unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); - ctrl_regs->TXIE = 1; /* Enable only EP0 */ - ctrl_regs->RXIE = 0; + musb_regs->intr_txen = 1; /* Enable only EP0 */ + musb_regs->intr_rxen = 0; for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { regs = musb_dcd_epn_regs(rhport, i); regs->TXMAXP = 0; @@ -596,10 +599,11 @@ void dcd_edpt_close_all(uint8_t rhport) regs->RXMAXP = 0; regs->RXCSRH = 0; - if (regs->RXCSRL & USB_RXCSRL1_RXRDY) + if (regs->RXCSRL & USB_RXCSRL1_RXRDY) { regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; - else + } else { regs->RXCSRL = USB_RXCSRL1_CLRDT; + } musb_dcd_reset_fifo(rhport, i, 0); musb_dcd_reset_fifo(rhport, i, 1); @@ -614,25 +618,27 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) unsigned const dir_in = tu_edpt_dir(ep_addr); volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); - volatile musb_ctl_regs_t *ctrl_regs = musb_dcd_ctl_regs(rhport); + musb_regs_t* musb_regs = MUSB_REGS(rhport); unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); if (dir_in) { - ctrl_regs->TXIE &= ~TU_BIT(epn); + musb_regs->intr_txen &= ~TU_BIT(epn); regs->TXMAXP = 0; regs->TXCSRH = 0; - if (regs->TXCSRL & USB_TXCSRL1_TXRDY) + if (regs->TXCSRL & USB_TXCSRL1_TXRDY) { regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; - else + } else { regs->TXCSRL = USB_TXCSRL1_CLRDT; + } } else { - ctrl_regs->RXIE &= ~TU_BIT(epn); + musb_regs->intr_rxen &= ~TU_BIT(epn); regs->RXMAXP = 0; regs->RXCSRH = 0; - if (regs->RXCSRL & USB_RXCSRL1_RXRDY) + if (regs->RXCSRL & USB_RXCSRL1_RXRDY) { regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; - else + } else { regs->RXCSRL = USB_RXCSRL1_CLRDT; + } } musb_dcd_reset_fifo(rhport, epn, dir_in); if (ie) musb_dcd_int_enable(rhport); @@ -650,8 +656,9 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t if (epnum) { _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] &= ~TU_BIT(epnum - 1); ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes); - } else + } else { ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes); + } if (ie) musb_dcd_int_enable(rhport); return ret; } @@ -719,18 +726,18 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) void dcd_int_handler(uint8_t rhport) { uint_fast8_t is, txis, rxis; - volatile musb_ctl_regs_t *ctrl_regs; //Part specific ISR setup/entry musb_dcd_int_handler_enter(rhport); - ctrl_regs = musb_dcd_ctl_regs(rhport); - is = ctrl_regs->IS; /* read and clear interrupt status */ - txis = ctrl_regs->TXIS; /* read and clear interrupt status */ - rxis = ctrl_regs->RXIS; /* read and clear interrupt status */ + musb_regs_t* musb_regs = MUSB_REGS(rhport); + + is = musb_regs->intrusb; /* read and clear interrupt status */ + txis = musb_regs->intr_tx; /* read and clear interrupt status */ + rxis = musb_regs->intr_rx; /* read and clear interrupt status */ // TU_LOG1("D%2x T%2x R%2x\r\n", is, txis, rxis); - is &= ctrl_regs->IE; /* Clear disabled interrupts */ + is &= musb_regs->intrusben; /* Clear disabled interrupts */ if (is & USB_IS_DISCON) { } if (is & USB_IS_SOF) { @@ -746,7 +753,7 @@ void dcd_int_handler(uint8_t rhport) dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); } - txis &= ctrl_regs->TXIE; /* Clear disabled interrupts */ + txis &= musb_regs->intr_txen; /* Clear disabled interrupts */ if (txis & USB_TXIE_EP0) { process_ep0(rhport); txis &= ~TU_BIT(0); @@ -756,7 +763,7 @@ void dcd_int_handler(uint8_t rhport) process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN)); txis &= ~TU_BIT(num); } - rxis &= ctrl_regs->RXIE; /* Clear disabled interrupts */ + rxis &= musb_regs->intr_rxen; /* Clear disabled interrupts */ while (rxis) { unsigned const num = __builtin_ctz(rxis); process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT)); diff --git a/src/portable/mentor/musb/musb_max32.h b/src/portable/mentor/musb/musb_max32.h index 0712aeda4..9c048513c 100644 --- a/src/portable/mentor/musb/musb_max32.h +++ b/src/portable/mentor/musb/musb_max32.h @@ -28,12 +28,14 @@ #define TUSB_MUSB_MAX32_H_ #ifdef __cplusplus - extern "C" { +extern "C" { #endif #include "mxc_device.h" #include "usbhs_regs.h" +const uintptr_t MUSB_BASES[] = { MXC_BASE_USBHS }; + #if CFG_TUD_ENABLED #define USBHS_M31_CLOCK_RECOVERY @@ -92,14 +94,12 @@ static inline void musb_dcd_int_handler_enter(uint8_t rhport) { } } -static inline void musb_dcd_int_handler_exit(uint8_t rhport) -{ +static inline void musb_dcd_int_handler_exit(uint8_t rhport) { //restore register index musb_periph_inst[rhport]->index = isr_saved_index; } -static inline void musb_dcd_phy_init(uint8_t rhport) -{ +static inline void musb_dcd_phy_init(uint8_t rhport) { //Interrupt for VBUS disconnect musb_periph_inst[rhport]->mxm_int_en |= MXC_F_USBHS_MXM_INT_EN_NOVBUS; @@ -136,42 +136,32 @@ static inline void musb_dcd_phy_init(uint8_t rhport) musb_periph_inst[rhport]->m31_phy_ponrst = 1; } -static inline volatile musb_ctl_regs_t* musb_dcd_ctl_regs(uint8_t rhport) -{ - volatile musb_ctl_regs_t *regs = (volatile musb_ctl_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->faddr)); - return regs; -} - -static inline volatile musb_epn_regs_t* musb_dcd_epn_regs(uint8_t rhport, unsigned epnum) -{ +static inline volatile musb_epn_regs_t* musb_dcd_epn_regs(uint8_t rhport, unsigned epnum) { //Need to set index to map EP registers musb_periph_inst[rhport]->index = epnum; - volatile musb_epn_regs_t *regs = (volatile musb_epn_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->inmaxp)); + volatile musb_epn_regs_t* regs = (volatile musb_epn_regs_t*) ((uintptr_t) &(musb_periph_inst[rhport]->inmaxp)); return regs; } -static inline volatile musb_ep0_regs_t* musb_dcd_ep0_regs(uint8_t rhport) -{ +static inline volatile musb_ep0_regs_t* musb_dcd_ep0_regs(uint8_t rhport) { //Need to set index to map EP0 registers musb_periph_inst[rhport]->index = 0; - volatile musb_ep0_regs_t *regs = (volatile musb_ep0_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->csr0)); + volatile musb_ep0_regs_t* regs = (volatile musb_ep0_regs_t*) ((uintptr_t) &(musb_periph_inst[rhport]->csr0)); return regs; } -static volatile void *musb_dcd_ep_get_fifo_ptr(uint8_t rhport, unsigned epnum) -{ - volatile uint32_t *ptr; +static volatile void* musb_dcd_ep_get_fifo_ptr(uint8_t rhport, unsigned epnum) { + volatile uint32_t* ptr; ptr = &(musb_periph_inst[rhport]->fifo0); ptr += epnum; - return (volatile void *) ptr; + return (volatile void*) ptr; } -static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) -{ - (void)mps; +static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) { + (void) mps; //Most likely the caller has already grabbed the right register block. But //as a precaution save and restore the register bank anyways @@ -180,7 +170,7 @@ static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned musb_periph_inst[rhport]->index = epnum; //Disable double buffering - if(dir_in) { + if (dir_in) { musb_periph_inst[rhport]->incsru |= (MXC_F_USBHS_INCSRU_DPKTBUFDIS | MXC_F_USBHS_INCSRU_MODE); } else { musb_periph_inst[rhport]->outcsru |= (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS); @@ -189,8 +179,7 @@ static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned musb_periph_inst[rhport]->index = saved_index; } -static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in) -{ +static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in) { //Most likely the caller has already grabbed the right register block. But //as a precaution save and restore the register bank anyways unsigned saved_index = musb_periph_inst[rhport]->index; @@ -198,7 +187,7 @@ static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned musb_periph_inst[rhport]->index = epnum; //Disable double buffering - if(dir_in) { + if (dir_in) { musb_periph_inst[rhport]->incsru |= (MXC_F_USBHS_INCSRU_DPKTBUFDIS); } else { musb_periph_inst[rhport]->outcsru |= (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS); @@ -210,7 +199,7 @@ static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned #endif // CFG_TUD_ENABLED #ifdef __cplusplus - } +} #endif #endif // TUSB_MUSB_MAX32_H_ diff --git a/src/portable/mentor/musb/musb_ti.h b/src/portable/mentor/musb/musb_ti.h index ec0a267b1..df77303a0 100644 --- a/src/portable/mentor/musb/musb_ti.h +++ b/src/portable/mentor/musb/musb_ti.h @@ -42,6 +42,8 @@ #error "Unsupported MCUs" #endif +const uintptr_t MUSB_BASES[] = { USB0_BASE }; + // Header supports both device and host modes. Only include what's necessary #if CFG_TUD_ENABLED @@ -95,12 +97,6 @@ static inline void musb_dcd_int_handler_exit(uint8_t rhport){ //Nothing to do for this part } -static inline volatile musb_ctl_regs_t* musb_dcd_ctl_regs(uint8_t rhport) -{ - volatile musb_ctl_regs_t *regs = (volatile musb_ctl_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->FADDR)); - return regs; -} - static inline volatile musb_epn_regs_t* musb_dcd_epn_regs(uint8_t rhport, unsigned epnum) { uintptr_t baseptr = (uintptr_t)&(musb_periph_inst[rhport]->TXMAXP1); diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h index d21dcd6da..9986a30e0 100644 --- a/src/portable/mentor/musb/musb_type.h +++ b/src/portable/mentor/musb/musb_type.h @@ -32,8 +32,8 @@ * *******************************************************************************/ -#ifndef _TUSB_MUSB_TYPE_H_ -#define _TUSB_MUSB_TYPE_H_ +#ifndef TUSB_MUSB_TYPE_H_ +#define TUSB_MUSB_TYPE_H_ #include "stdint.h" @@ -41,6 +41,22 @@ extern "C" { #endif +#ifndef __IO + #define __IO volatile +#endif + +#ifndef __I + #define __I volatile const +#endif + +#ifndef __O + #define __O volatile +#endif + +#ifndef __R + #define __R volatile const +#endif + // Endpoint register mapping. Non-zero end points. typedef struct TU_ATTR_PACKED { uint16_t TXMAXP; @@ -60,17 +76,131 @@ typedef struct TU_ATTR_PACKED { uint8_t COUNT0; } musb_ep0_regs_t; -// Control register mapping -typedef struct TU_ATTR_PACKED { - uint8_t FADDR; - uint8_t POWER; - uint16_t TXIS; - uint16_t RXIS; - uint16_t TXIE; - uint16_t RXIE; - uint8_t IS; - uint8_t IE; -} musb_ctl_regs_t; +typedef struct { + //------------- Common -------------// + __IO uint8_t faddr; // 0x00: FADDR + __IO uint8_t power; // 0x01: POWER + + __IO uint16_t intr_tx; // 0x02: INTR_TX + __IO uint16_t intr_rx; // 0x04: INTR_RX + + __IO uint16_t intr_txen; // 0x06: INTR_TXEN + __IO uint16_t intr_rxen; // 0x08: INTR_RXEN + + __IO uint8_t intrusb; // 0x0A: INTRUSB + __IO uint8_t intrusben; // 0x0B: INTRUSBEN + + __IO uint16_t frame; // 0x0C: FRAME + __IO uint8_t index; // 0x0E: INDEX + __IO uint8_t testmode; // 0x0F: TESTMODE + __IO uint16_t inmaxp; // 0x10: INMAXP + union { + __IO uint8_t csr0; // 0x12: CSR0 + __IO uint8_t incsrl; // 0x12: INCSRL + }; + __IO uint8_t incsru; // 0x13: INCSRU + __IO uint16_t outmaxp; // 0x14: OUTMAXP + __IO uint8_t outcsrl; // 0x16: OUTCSRL + __IO uint8_t outcsru; // 0x17: OUTCSRU + union { + __IO uint16_t count0; // 0x18: COUNT0 + __IO uint16_t outcount; // 0x18: OUTCOUNT + }; + __R uint16_t rsv_0x1a_0x1f[3]; + __IO uint32_t fifo0; // 0x20: FIFO0 + __IO uint32_t fifo1; // 0x24: FIFO1 + __IO uint32_t fifo2; // 0x28: FIFO2 + __IO uint32_t fifo3; // 0x2c: FIFO3 + __IO uint32_t fifo4; // 0x30: FIFO4 + __IO uint32_t fifo5; // 0x34: FIFO5 + __IO uint32_t fifo6; // 0x38: FIFO6 + __IO uint32_t fifo7; // 0x3c: FIFO7 + __IO uint32_t fifo8; // 0x40: FIFO8 + __IO uint32_t fifo9; // 0x44: FIFO9 + __IO uint32_t fifo10; // 0x48: FIFO10 + __IO uint32_t fifo11; // 0x4c: FIFO11 + __IO uint32_t fifo12; // 0x50: FIFO12 + __IO uint32_t fifo13; // 0x54: FIFO13 + __IO uint32_t fifo14; // 0x58: FIFO14 + __IO uint32_t fifo15; // 0x5c: FIFO15 + __IO uint8_t devctl; // 0x60: DEVCTL + __IO uint8_t misc; // 0x61: MISC + + //------------- Dynammic FIFO -------------// + __IO uint8_t txfifo_sz; // 0x62: TXFIFO_SZ + __IO uint8_t rxfifo_sz; // 0x63: RXFIFO_SZ + __IO uint16_t txfifo_addr; // 0x64: TXFIFO_ADDR + __IO uint16_t rxfifo_addr; // 0x66: RXFIFO_ADDR + + //------------- Additional Control/Status -------------// + union { + __O uint32_t vcontrol; // 0x68: VCONTROL + __IO uint32_t vstatus; // 0x68: VSTATUS + }; + __IO uint16_t hwvers; // 0x6c: HWVERS + __R uint16_t rsv_0x6e_0x77[5]; + + //------------- Additional Configuration -------------// + __IO uint8_t epinfo; // 0x78: EPINFO + __IO uint8_t raminfo; // 0x79: RAMINFO + __IO uint8_t softreset; // 0x7A: SOFTRESET (Analog), Link info + __IO uint8_t vplen; // 0x7B: VPLEN + __IO uint8_t hs_eof1; // 0x7C: HS_EOF1 + __IO uint8_t fs_eof1; // 0x7D: FS_EOF1 + __IO uint8_t ls_eof1; // 0x7E: LS_EOF1 + __IO uint8_t soft_rst; // 0x7F: SOFT_RST + + //------------- Extended -------------// + __IO uint16_t ctuch; // 0x80: CTUCH + __IO uint16_t cthsrtn; // 0x82: CTHSRTN + __R uint32_t rsv_0x84_0x3ff[223]; + + //------------- Analog PHY -------------// + __IO uint32_t mxm_usb_reg_00; // 0x400: MXM_USB_REG_00 + __IO uint32_t m31_phy_utmi_reset; // 0x404: M31_PHY_UTMI_RESET + __IO uint32_t m31_phy_utmi_vcontrol; // 0x408: M31_PHY_UTMI_VCONTROL + __IO uint32_t m31_phy_clk_en; // 0x40C: M31_PHY_CLK_EN + __IO uint32_t m31_phy_ponrst; // 0x410: M31_PHY_PONRST + __IO uint32_t m31_phy_noncry_rstb; // 0x414: M31_PHY_NONCRY_RSTB + __IO uint32_t m31_phy_noncry_en; // 0x418: M31_PHY_NONCRY_EN + __R uint32_t rsv_0x41c; + __IO uint32_t m31_phy_u2_compliance_en; // 0x420: M31_PHY_U2_COMPLIANCE_EN + __IO uint32_t m31_phy_u2_compliance_dac_adj; // 0x424: M31_PHY_U2_COMPLIANCE_DAC_ADJ + __IO uint32_t m31_phy_u2_compliance_dac_adj_en; // 0x428: M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN + __IO uint32_t m31_phy_clk_rdy; // 0x42C: M31_PHY_CLK_RDY + __IO uint32_t m31_phy_pll_en; // 0x430: M31_PHY_PLL_EN + __IO uint32_t m31_phy_bist_ok; // 0x434: M31_PHY_BIST_OK + __IO uint32_t m31_phy_data_oe; // 0x438: M31_PHY_DATA_OE + __IO uint32_t m31_phy_oscouten; // 0x43C: M31_PHY_OSCOUTEN + __IO uint32_t m31_phy_lpm_alive; // 0x440: M31_PHY_LPM_ALIVE + __IO uint32_t m31_phy_hs_bist_mode; // 0x444: M31_PHY_HS_BIST_MODE + __IO uint32_t m31_phy_coreclkin; // 0x448: M31_PHY_CORECLKIN + __IO uint32_t m31_phy_xtlsel; // 0x44C: M31_PHY_XTLSEL + __IO uint32_t m31_phy_ls_en; // 0x450: M31_PHY_LS_EN + __IO uint32_t m31_phy_debug_sel; // 0x454: M31_PHY_DEBUG_SEL + __IO uint32_t m31_phy_debug_out; // 0x458: M31_PHY_DEBUG_OUT + __IO uint32_t m31_phy_outclksel; // 0x45C: M31_PHY_OUTCLKSEL + __IO uint32_t m31_phy_xcfgi_31_0; // 0x460: M31_PHY_XCFGI_31_0 + __IO uint32_t m31_phy_xcfgi_63_32; // 0x464: M31_PHY_XCFGI_63_32 + __IO uint32_t m31_phy_xcfgi_95_64; // 0x468: M31_PHY_XCFGI_95_64 + __IO uint32_t m31_phy_xcfgi_127_96; // 0x46C: M31_PHY_XCFGI_127_96 + __IO uint32_t m31_phy_xcfgi_137_128; // 0x470: M31_PHY_XCFGI_137_128 + __IO uint32_t m31_phy_xcfg_hs_coarse_tune_num; // 0x474: M31_PHY_XCFG_HS_COARSE_TUNE_NUM + __IO uint32_t m31_phy_xcfg_hs_fine_tune_num; // 0x478: M31_PHY_XCFG_HS_FINE_TUNE_NUM + __IO uint32_t m31_phy_xcfg_fs_coarse_tune_num; // 0x47C: M31_PHY_XCFG_FS_COARSE_TUNE_NUM + __IO uint32_t m31_phy_xcfg_fs_fine_tune_num; // 0x480: M31_PHY_XCFG_FS_FINE_TUNE_NUM + __IO uint32_t m31_phy_xcfg_lock_range_max; // 0x484: M31_PHY_XCFG_LOCK_RANGE_MAX + __IO uint32_t m31_phy_xcfgi_lock_range_min; // 0x488: M31_PHY_XCFGI_LOCK_RANGE_MIN + __IO uint32_t m31_phy_xcfg_ob_rsel; // 0x48C: M31_PHY_XCFG_OB_RSEL + __IO uint32_t m31_phy_xcfg_oc_rsel; // 0x490: M31_PHY_XCFG_OC_RSEL + __IO uint32_t m31_phy_xcfgo; // 0x494: M31_PHY_XCFGO + __IO uint32_t mxm_int; // 0x498: MXM_INT + __IO uint32_t mxm_int_en; // 0x49C: MXM_INT_EN + __IO uint32_t mxm_suspend; // 0x4A0: MXM_SUSPEND + __IO uint32_t mxm_reg_a4; // 0x4A4: MXM_REG_A4 +} musb_regs_t; + +TU_VERIFY_STATIC(sizeof(musb_regs_t) == 0x4A8, "size is not correct"); //***************************************************************************** // -- cgit v1.3.1 From 7d8d364332189f840cbd0265f2834c1b343c5e52 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 15 Aug 2024 16:52:50 +0700 Subject: update musb fifo usage --- src/portable/mentor/musb/dcd_musb.c | 20 +++++++++++--------- src/portable/mentor/musb/musb_max32.h | 10 ---------- src/portable/mentor/musb/musb_ti.h | 10 ---------- src/portable/mentor/musb/musb_type.h | 17 +---------------- 4 files changed, 12 insertions(+), 45 deletions(-) (limited to 'src/portable') diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 78fc3d616..114720a6a 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -153,10 +153,10 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne ops[dir].tu_fifo_advance(f, total_len - rem); } -static void process_setup_packet(uint8_t rhport) -{ +static void process_setup_packet(uint8_t rhport) { + musb_regs_t* musb_regs = MUSB_REGS(rhport); uint32_t *p = (void*)&_dcd.setup_packet; - volatile uint32_t *fifo_ptr = musb_dcd_ep_get_fifo_ptr(rhport, 0); + volatile uint32_t *fifo_ptr = &musb_regs->fifo[0]; volatile musb_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); p[0] = *fifo_ptr; p[1] = *fifo_ptr; @@ -185,11 +185,12 @@ static bool handle_xfer_in(uint8_t rhport, uint_fast8_t ep_addr) return true; } + musb_regs_t* musb_regs = MUSB_REGS(rhport); volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epnum); const unsigned mps = regs->TXMAXP; const unsigned len = TU_MIN(mps, rem); void *buf = pipe->buf; - volatile void *fifo_ptr = musb_dcd_ep_get_fifo_ptr(rhport, epnum); + volatile void *fifo_ptr = &musb_regs->fifo[epnum]; // TU_LOG1(" %p mps %d len %d rem %d\r\n", buf, mps, len, rem); if (len) { if (_dcd.pipe_buf_is_fifo[TUSB_DIR_IN] & TU_BIT(epnum_minus1)) { @@ -210,6 +211,7 @@ static bool handle_xfer_out(uint8_t rhport, uint_fast8_t ep_addr) unsigned epnum = tu_edpt_number(ep_addr); unsigned epnum_minus1 = epnum - 1; pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; + musb_regs_t* musb_regs = MUSB_REGS(rhport); volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epnum); // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, regs->RXCSRL); @@ -220,7 +222,7 @@ static bool handle_xfer_out(uint8_t rhport, uint_fast8_t ep_addr) const unsigned vld = regs->RXCOUNT; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; - volatile void *fifo_ptr = musb_dcd_ep_get_fifo_ptr(rhport, epnum); + volatile void *fifo_ptr = &musb_regs->fifo[epnum]; if (len) { if (_dcd.pipe_buf_is_fifo[TUSB_DIR_OUT] & TU_BIT(epnum_minus1)) { pipe_read_write_packet_ff(buf, fifo_ptr, len, TUSB_DIR_OUT); @@ -262,6 +264,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ { (void)rhport; TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */ + musb_regs_t* musb_regs = MUSB_REGS(rhport); volatile musb_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); const unsigned req = _dcd.setup_packet.bmRequestType; TU_ASSERT(req != REQUEST_TYPE_INVALID || total_bytes == 0); @@ -289,7 +292,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ TU_ASSERT(total_bytes <= _dcd.remaining_ctrl); const unsigned rem = _dcd.remaining_ctrl; const unsigned len = TU_MIN(TU_MIN(rem, 64), total_bytes); - volatile void *fifo_ptr = musb_dcd_ep_get_fifo_ptr(rhport, 0); + volatile void *fifo_ptr = &musb_regs->fifo[0]; if (dir_in) { pipe_write_packet(buffer, fifo_ptr, len); @@ -327,6 +330,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ static void process_ep0(uint8_t rhport) { + musb_regs_t* musb_regs = MUSB_REGS(rhport); volatile musb_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); uint_fast8_t csrl = ep0_regs->CSRL0; @@ -368,7 +372,7 @@ static void process_ep0(uint8_t rhport) const unsigned vld = ep0_regs->COUNT0; const unsigned rem = _dcd.pipe0.remaining; const unsigned len = TU_MIN(TU_MIN(rem, 64), vld); - volatile void *fifo_ptr = musb_dcd_ep_get_fifo_ptr(rhport, 0); + volatile void *fifo_ptr = &musb_regs->fifo[0]; pipe_read_packet(_dcd.pipe0.buf, fifo_ptr, len); _dcd.pipe0.remaining = rem - len; @@ -383,8 +387,6 @@ static void process_ep0(uint8_t rhport) return; } - musb_regs_t* musb_regs = MUSB_REGS(rhport); - /* When CSRL0 is zero, it means that completion of sending a any length packet * or receiving a zero length packet. */ if (req != REQUEST_TYPE_INVALID && !tu_edpt_dir(req)) { diff --git a/src/portable/mentor/musb/musb_max32.h b/src/portable/mentor/musb/musb_max32.h index 9c048513c..0a97f529a 100644 --- a/src/portable/mentor/musb/musb_max32.h +++ b/src/portable/mentor/musb/musb_max32.h @@ -150,16 +150,6 @@ static inline volatile musb_ep0_regs_t* musb_dcd_ep0_regs(uint8_t rhport) { return regs; } -static volatile void* musb_dcd_ep_get_fifo_ptr(uint8_t rhport, unsigned epnum) { - volatile uint32_t* ptr; - - ptr = &(musb_periph_inst[rhport]->fifo0); - ptr += epnum; - - return (volatile void*) ptr; -} - - static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) { (void) mps; diff --git a/src/portable/mentor/musb/musb_ti.h b/src/portable/mentor/musb/musb_ti.h index df77303a0..499e01e63 100644 --- a/src/portable/mentor/musb/musb_ti.h +++ b/src/portable/mentor/musb/musb_ti.h @@ -113,16 +113,6 @@ static inline volatile musb_ep0_regs_t* musb_dcd_ep0_regs(uint8_t rhport) return regs; } -static volatile void *musb_dcd_ep_get_fifo_ptr(uint8_t rhport, unsigned epnum) -{ - if(epnum){ - return (volatile void *)(&(musb_periph_inst[rhport]->FIFO1_WORD) + (epnum - 1)); - } else { - return (volatile void *)&(musb_periph_inst[rhport]->FIFO0_WORD); - } -} - - typedef struct { uint_fast16_t beg; /* offset of including first element */ uint_fast16_t end; /* offset of excluding the last element */ diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h index 9986a30e0..c31e0c984 100644 --- a/src/portable/mentor/musb/musb_type.h +++ b/src/portable/mentor/musb/musb_type.h @@ -107,22 +107,7 @@ typedef struct { __IO uint16_t outcount; // 0x18: OUTCOUNT }; __R uint16_t rsv_0x1a_0x1f[3]; - __IO uint32_t fifo0; // 0x20: FIFO0 - __IO uint32_t fifo1; // 0x24: FIFO1 - __IO uint32_t fifo2; // 0x28: FIFO2 - __IO uint32_t fifo3; // 0x2c: FIFO3 - __IO uint32_t fifo4; // 0x30: FIFO4 - __IO uint32_t fifo5; // 0x34: FIFO5 - __IO uint32_t fifo6; // 0x38: FIFO6 - __IO uint32_t fifo7; // 0x3c: FIFO7 - __IO uint32_t fifo8; // 0x40: FIFO8 - __IO uint32_t fifo9; // 0x44: FIFO9 - __IO uint32_t fifo10; // 0x48: FIFO10 - __IO uint32_t fifo11; // 0x4c: FIFO11 - __IO uint32_t fifo12; // 0x50: FIFO12 - __IO uint32_t fifo13; // 0x54: FIFO13 - __IO uint32_t fifo14; // 0x58: FIFO14 - __IO uint32_t fifo15; // 0x5c: FIFO15 + __IO uint32_t fifo[16]; // 0x20-0x5C: FIFO 0-15 __IO uint8_t devctl; // 0x60: DEVCTL __IO uint8_t misc; // 0x61: MISC -- cgit v1.3.1 From 6152adb17fd0e8d76c60f589d84eee0fec323fa5 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 15 Aug 2024 19:05:28 +0700 Subject: use musb_ep_csr_t for indexed CSR, also use indexed csr for TI access as well. Merge ep0 and epn together --- src/portable/mentor/musb/dcd_musb.c | 181 +++++++++++++++++----------------- src/portable/mentor/musb/musb_max32.h | 14 --- src/portable/mentor/musb/musb_ti.h | 16 --- src/portable/mentor/musb/musb_type.h | 104 +++++++++++++------ 4 files changed, 163 insertions(+), 152 deletions(-) (limited to 'src/portable') diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 114720a6a..48f6e9d97 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -41,10 +41,6 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); // Following symbols must be defined by port header // - musb_dcd_int_enable/disable/clear/get_enable // - musb_dcd_int_handler_enter/exit -// - musb_dcd_epn_regs: Get memory mapped struct of end point registers -// - musb_dcd_ep0_regs: Get memory mapped struct of EP0 registers -// - musb_dcd_ctl_regs: Get memory mapped struct of control registers -// - musb_dcd_ep_get_fifo_ptr: Gets the address of the provided EP's FIFO // - musb_dcd_setup_fifo/reset_fifo: Configuration of the EP's FIFO #if TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) #include "musb_ti.h" @@ -157,7 +153,7 @@ static void process_setup_packet(uint8_t rhport) { musb_regs_t* musb_regs = MUSB_REGS(rhport); uint32_t *p = (void*)&_dcd.setup_packet; volatile uint32_t *fifo_ptr = &musb_regs->fifo[0]; - volatile musb_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); + p[0] = *fifo_ptr; p[1] = *fifo_ptr; @@ -170,7 +166,10 @@ static void process_setup_packet(uint8_t rhport) { _dcd.remaining_ctrl = len; const unsigned dir_in = tu_edpt_dir(_dcd.setup_packet.bmRequestType); /* Clear RX FIFO and reverse the transaction direction */ - if (len && dir_in) ep0_regs->CSRL0 = USB_CSRL0_RXRDYC; + if (len && dir_in) { + musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, 0); + ep_csr->csr0l = USB_CSRL0_RXRDYC; + } } static bool handle_xfer_in(uint8_t rhport, uint_fast8_t ep_addr) @@ -186,8 +185,8 @@ static bool handle_xfer_in(uint8_t rhport, uint_fast8_t ep_addr) } musb_regs_t* musb_regs = MUSB_REGS(rhport); - volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epnum); - const unsigned mps = regs->TXMAXP; + musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epnum); + const unsigned mps = ep_csr->tx_maxp; const unsigned len = TU_MIN(mps, rem); void *buf = pipe->buf; volatile void *fifo_ptr = &musb_regs->fifo[epnum]; @@ -201,8 +200,8 @@ static bool handle_xfer_in(uint8_t rhport, uint_fast8_t ep_addr) } pipe->remaining = rem - len; } - regs->TXCSRL = USB_TXCSRL1_TXRDY; - // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum, regs->TXCSRL, rem - len); + ep_csr->tx_csrl = USB_TXCSRL1_TXRDY; + // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum, ep_csr->tx_csrl, rem - len); return false; } @@ -212,14 +211,14 @@ static bool handle_xfer_out(uint8_t rhport, uint_fast8_t ep_addr) unsigned epnum_minus1 = epnum - 1; pipe_state_t *pipe = &_dcd.pipe[tu_edpt_dir(ep_addr)][epnum_minus1]; musb_regs_t* musb_regs = MUSB_REGS(rhport); - volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epnum); - // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, regs->RXCSRL); + musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epnum); + // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, ep_csr->rx_csrl); - TU_ASSERT(regs->RXCSRL & USB_RXCSRL1_RXRDY); + TU_ASSERT(ep_csr->rx_csrl & USB_RXCSRL1_RXRDY); - const unsigned mps = regs->RXMAXP; + const unsigned mps = ep_csr->rx_maxp; const unsigned rem = pipe->remaining; - const unsigned vld = regs->RXCOUNT; + const unsigned vld = ep_csr->rx_count; const unsigned len = TU_MIN(TU_MIN(rem, mps), vld); void *buf = pipe->buf; volatile void *fifo_ptr = &musb_regs->fifo[epnum]; @@ -236,7 +235,7 @@ static bool handle_xfer_out(uint8_t rhport, uint_fast8_t ep_addr) pipe->buf = NULL; return NULL != buf; } - regs->RXCSRL = 0; /* Clear RXRDY bit */ + ep_csr->rx_csrl = 0; /* Clear RXRDY bit */ return false; } @@ -254,8 +253,9 @@ static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16 if (dir_in) { handle_xfer_in(rhport, ep_addr); } else { - volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epnum); - if (regs->RXCSRL & USB_RXCSRL1_RXRDY) regs->RXCSRL = 0; + musb_regs_t* musb_regs = MUSB_REGS(rhport); + musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epnum); + if (ep_csr->rx_csrl & USB_RXCSRL1_RXRDY) ep_csr->rx_csrl = 0; } return true; } @@ -265,7 +265,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ (void)rhport; TU_ASSERT(total_bytes <= 64); /* Current implementation supports for only up to 64 bytes. */ musb_regs_t* musb_regs = MUSB_REGS(rhport); - volatile musb_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); + musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, 0); const unsigned req = _dcd.setup_packet.bmRequestType; TU_ASSERT(req != REQUEST_TYPE_INVALID || total_bytes == 0); @@ -276,7 +276,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ * may have already finished and received the next setup packet * without calling this function, so we have no choice but to * invoke the callback function of status packet here. */ - // TU_LOG1(" STATUS OUT ep0_regs->CSRL0 = %x\r\n", ep0_regs->CSRL0); + // TU_LOG1(" STATUS OUT ep_csr->csr0l = %x\r\n", ep_csr->csr0l); _dcd.status_out = 0; if (req == REQUEST_TYPE_INVALID) { dcd_event_xfer_complete(rhport, ep_addr, total_bytes, XFER_RESULT_SUCCESS, false); @@ -305,25 +305,25 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */ _dcd.status_out = 1; /* Flush TX FIFO and reverse the transaction direction. */ - ep0_regs->CSRL0 = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND; + ep_csr->csr0l = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND; } else { - ep0_regs->CSRL0 = USB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */ + ep_csr->csr0l = USB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */ } - // TU_LOG1(" IN ep0_regs->CSRL0 = %x\r\n", ep0_regs->CSRL0); + // TU_LOG1(" IN ep_csr->csr0l = %x\r\n", ep_csr->csr0l); } else { - // TU_LOG1(" OUT ep0_regs->CSRL0 = %x\r\n", ep0_regs->CSRL0); + // TU_LOG1(" OUT ep_csr->csr0l = %x\r\n", ep_csr->csr0l); _dcd.pipe0.buf = buffer; _dcd.pipe0.length = len; _dcd.pipe0.remaining = len; - ep0_regs->CSRL0 = USB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */ + ep_csr->csr0l = USB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */ } } else if (dir_in) { - // TU_LOG1(" STATUS IN ep0_regs->CSRL0 = %x\r\n", ep0_regs->CSRL0); + // TU_LOG1(" STATUS IN ep_csr->csr0l = %x\r\n", ep_csr->csr0l); _dcd.pipe0.buf = NULL; _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; /* Clear RX FIFO and reverse the transaction direction */ - ep0_regs->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; + ep_csr->csr0l = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; } return true; } @@ -331,21 +331,21 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ static void process_ep0(uint8_t rhport) { musb_regs_t* musb_regs = MUSB_REGS(rhport); - volatile musb_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); - uint_fast8_t csrl = ep0_regs->CSRL0; + musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, 0); + uint_fast8_t csrl = ep_csr->csr0l; - // TU_LOG1(" EP0 ep0_regs->CSRL0 = %x\r\n", csrl); + // TU_LOG1(" EP0 ep_csr->csr0l = %x\r\n", csrl); if (csrl & USB_CSRL0_STALLED) { /* Returned STALL packet to HOST. */ - ep0_regs->CSRL0 = 0; /* Clear STALL */ + ep_csr->csr0l = 0; /* Clear STALL */ return; } unsigned req = _dcd.setup_packet.bmRequestType; if (csrl & USB_CSRL0_SETEND) { TU_LOG1(" ABORT by the next packets\r\n"); - ep0_regs->CSRL0 = USB_CSRL0_SETENDC; + ep_csr->csr0l = USB_CSRL0_SETENDC; if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) { /* DATA stage was aborted by receiving STATUS or SETUP packet. */ _dcd.pipe0.buf = NULL; @@ -363,13 +363,13 @@ static void process_ep0(uint8_t rhport) /* Received SETUP or DATA OUT packet */ if (req == REQUEST_TYPE_INVALID) { /* SETUP */ - TU_ASSERT(sizeof(tusb_control_request_t) == ep0_regs->COUNT0,); + TU_ASSERT(sizeof(tusb_control_request_t) == ep_csr->rx_count,); process_setup_packet(rhport); return; } if (_dcd.pipe0.buf) { /* DATA OUT */ - const unsigned vld = ep0_regs->COUNT0; + const unsigned vld = ep_csr->rx_count; const unsigned rem = _dcd.pipe0.remaining; const unsigned len = TU_MIN(TU_MIN(rem, 64), vld); volatile void *fifo_ptr = &musb_regs->fifo[0]; @@ -415,22 +415,23 @@ static void process_ep0(uint8_t rhport) static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) { bool completed; - const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned dir_in = tu_edpt_dir(ep_addr); const unsigned epn = tu_edpt_number(ep_addr); const unsigned epn_minus1 = epn - 1; - volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); + musb_regs_t* musb_regs = MUSB_REGS(rhport); + musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn); if (dir_in) { - // TU_LOG1(" TXCSRL%d = %x\r\n", epn, regs->TXCSRL); - if (regs->TXCSRL & USB_TXCSRL1_STALLED) { - regs->TXCSRL &= ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_UNDRN); + // TU_LOG1(" TX CSRL%d = %x\r\n", epn, ep_csr->tx_csrl); + if (ep_csr->tx_csrl & USB_TXCSRL1_STALLED) { + ep_csr->tx_csrl &= ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_UNDRN); return; } completed = handle_xfer_in(rhport, ep_addr); } else { - // TU_LOG1(" RXCSRL%d = %x\r\n", epn, regs->RXCSRL); - if (regs->RXCSRL & USB_RXCSRL1_STALLED) { - regs->RXCSRL &= ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_OVER); + // TU_LOG1(" RX CSRL%d = %x\r\n", epn, ep_csr->rx_csrl); + if (ep_csr->rx_csrl & USB_RXCSRL1_STALLED) { + ep_csr->rx_csrl &= ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_OVER); return; } completed = handle_xfer_out(rhport, ep_addr); @@ -492,12 +493,14 @@ void dcd_int_disable(uint8_t rhport) void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { (void)dev_addr; - volatile musb_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); + musb_regs_t* musb_regs = MUSB_REGS(rhport); + musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, 0); + _dcd.pipe0.buf = NULL; _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; /* Clear RX FIFO to return ACK. */ - ep0_regs->CSRL0 = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; + ep_csr->csr0l = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; } // Wake up host @@ -554,24 +557,24 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) pipe->length = 0; pipe->remaining = 0; - volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); musb_regs_t* musb_regs = MUSB_REGS(rhport); + musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn); if (dir_in) { - regs->TXMAXP = mps; - regs->TXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_TXCSRH1_ISO : 0; - if (regs->TXCSRL & USB_TXCSRL1_TXRDY) { - regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; + ep_csr->tx_maxp = mps; + ep_csr->tx_csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_TXCSRH1_ISO : 0; + if (ep_csr->tx_csrl & USB_TXCSRL1_TXRDY) { + ep_csr->tx_csrl = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; } else { - regs->TXCSRL = USB_TXCSRL1_CLRDT; + ep_csr->tx_csrl = USB_TXCSRL1_CLRDT; } musb_regs->intr_txen |= TU_BIT(epn); } else { - regs->RXMAXP = mps; - regs->RXCSRH = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0; - if (regs->RXCSRL & USB_RXCSRL1_RXRDY) { - regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; + ep_csr->rx_maxp = mps; + ep_csr->rx_csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0; + if (ep_csr->rx_csrl & USB_RXCSRL1_RXRDY) { + ep_csr->rx_csrl = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; } else { - regs->RXCSRL = USB_RXCSRL1_CLRDT; + ep_csr->rx_csrl = USB_RXCSRL1_CLRDT; } musb_regs->intr_rxen |= TU_BIT(epn); } @@ -584,27 +587,26 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) void dcd_edpt_close_all(uint8_t rhport) { - volatile musb_epn_regs_t *regs; musb_regs_t* musb_regs = MUSB_REGS(rhport); unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); musb_regs->intr_txen = 1; /* Enable only EP0 */ musb_regs->intr_rxen = 0; for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { - regs = musb_dcd_epn_regs(rhport, i); - regs->TXMAXP = 0; - regs->TXCSRH = 0; - if (regs->TXCSRL & USB_TXCSRL1_TXRDY) - regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; + musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, i); + ep_csr->tx_maxp = 0; + ep_csr->tx_csrh = 0; + if (ep_csr->tx_csrl & USB_TXCSRL1_TXRDY) + ep_csr->tx_csrl = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; else - regs->TXCSRL = USB_TXCSRL1_CLRDT; + ep_csr->tx_csrl = USB_TXCSRL1_CLRDT; - regs->RXMAXP = 0; - regs->RXCSRH = 0; - if (regs->RXCSRL & USB_RXCSRL1_RXRDY) { - regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; + ep_csr->rx_maxp = 0; + ep_csr->rx_csrh = 0; + if (ep_csr->rx_csrl & USB_RXCSRL1_RXRDY) { + ep_csr->rx_csrl = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; } else { - regs->RXCSRL = USB_RXCSRL1_CLRDT; + ep_csr->rx_csrl = USB_RXCSRL1_CLRDT; } musb_dcd_reset_fifo(rhport, i, 0); @@ -618,28 +620,27 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { unsigned const epn = tu_edpt_number(ep_addr); unsigned const dir_in = tu_edpt_dir(ep_addr); - - volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); musb_regs_t* musb_regs = MUSB_REGS(rhport); + musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn); unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); if (dir_in) { musb_regs->intr_txen &= ~TU_BIT(epn); - regs->TXMAXP = 0; - regs->TXCSRH = 0; - if (regs->TXCSRL & USB_TXCSRL1_TXRDY) { - regs->TXCSRL = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; + ep_csr->tx_maxp = 0; + ep_csr->tx_csrh = 0; + if (ep_csr->tx_csrl & USB_TXCSRL1_TXRDY) { + ep_csr->tx_csrl = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; } else { - regs->TXCSRL = USB_TXCSRL1_CLRDT; + ep_csr->tx_csrl = USB_TXCSRL1_CLRDT; } } else { musb_regs->intr_rxen &= ~TU_BIT(epn); - regs->RXMAXP = 0; - regs->RXCSRH = 0; - if (regs->RXCSRL & USB_RXCSRL1_RXRDY) { - regs->RXCSRL = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; + ep_csr->rx_maxp = 0; + ep_csr->rx_csrh = 0; + if (ep_csr->rx_csrl & USB_RXCSRL1_RXRDY) { + ep_csr->rx_csrl = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; } else { - regs->RXCSRL = USB_RXCSRL1_CLRDT; + ep_csr->rx_csrl = USB_RXCSRL1_CLRDT; } } musb_dcd_reset_fifo(rhport, epn, dir_in); @@ -682,25 +683,24 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_ } // Stall endpoint -void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) -{ +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { unsigned const epn = tu_edpt_number(ep_addr); unsigned const ie = musb_dcd_get_int_enable(rhport); + musb_regs_t* musb_regs = MUSB_REGS(rhport); + musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn); musb_dcd_int_disable(rhport); if (0 == epn) { - volatile musb_ep0_regs_t* ep0_regs = musb_dcd_ep0_regs(rhport); if (!ep_addr) { /* Ignore EP80 */ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; _dcd.pipe0.buf = NULL; - ep0_regs->CSRL0 = USB_CSRL0_STALL; + ep_csr->csr0l = USB_CSRL0_STALL; } } else { - volatile musb_epn_regs_t *regs = musb_dcd_epn_regs(rhport, epn); if (tu_edpt_dir(ep_addr)) { /* IN */ - regs->TXCSRL = USB_TXCSRL1_STALL; + ep_csr->tx_csrl = USB_TXCSRL1_STALL; } else { /* OUT */ - TU_ASSERT(!(regs->RXCSRL & USB_RXCSRL1_RXRDY),); - regs->RXCSRL = USB_RXCSRL1_STALL; + TU_ASSERT(!(ep_csr->rx_csrl & USB_RXCSRL1_RXRDY),); + ep_csr->rx_csrl = USB_RXCSRL1_STALL; } } if (ie) musb_dcd_int_enable(rhport); @@ -711,13 +711,14 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { (void)rhport; unsigned const epn = tu_edpt_number(ep_addr); - musb_epn_regs_t volatile *regs = musb_dcd_epn_regs(rhport, epn); + musb_regs_t* musb_regs = MUSB_REGS(rhport); + musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn); unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); if (tu_edpt_dir(ep_addr)) { /* IN */ - regs->TXCSRL = USB_TXCSRL1_CLRDT; + ep_csr->tx_csrl = USB_TXCSRL1_CLRDT; } else { /* OUT */ - regs->RXCSRL = USB_RXCSRL1_CLRDT; + ep_csr->rx_csrl = USB_RXCSRL1_CLRDT; } if (ie) musb_dcd_int_enable(rhport); } diff --git a/src/portable/mentor/musb/musb_max32.h b/src/portable/mentor/musb/musb_max32.h index 0a97f529a..43f56de3c 100644 --- a/src/portable/mentor/musb/musb_max32.h +++ b/src/portable/mentor/musb/musb_max32.h @@ -136,20 +136,6 @@ static inline void musb_dcd_phy_init(uint8_t rhport) { musb_periph_inst[rhport]->m31_phy_ponrst = 1; } -static inline volatile musb_epn_regs_t* musb_dcd_epn_regs(uint8_t rhport, unsigned epnum) { - //Need to set index to map EP registers - musb_periph_inst[rhport]->index = epnum; - volatile musb_epn_regs_t* regs = (volatile musb_epn_regs_t*) ((uintptr_t) &(musb_periph_inst[rhport]->inmaxp)); - return regs; -} - -static inline volatile musb_ep0_regs_t* musb_dcd_ep0_regs(uint8_t rhport) { - //Need to set index to map EP0 registers - musb_periph_inst[rhport]->index = 0; - volatile musb_ep0_regs_t* regs = (volatile musb_ep0_regs_t*) ((uintptr_t) &(musb_periph_inst[rhport]->csr0)); - return regs; -} - static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) { (void) mps; diff --git a/src/portable/mentor/musb/musb_ti.h b/src/portable/mentor/musb/musb_ti.h index 499e01e63..d1a0aa4f9 100644 --- a/src/portable/mentor/musb/musb_ti.h +++ b/src/portable/mentor/musb/musb_ti.h @@ -97,22 +97,6 @@ static inline void musb_dcd_int_handler_exit(uint8_t rhport){ //Nothing to do for this part } -static inline volatile musb_epn_regs_t* musb_dcd_epn_regs(uint8_t rhport, unsigned epnum) -{ - uintptr_t baseptr = (uintptr_t)&(musb_periph_inst[rhport]->TXMAXP1); - - //On the TI parts, the epn registers are 16-bytes apart. The core regs defined - //by musb_dcd_epn_regs and 6 reserved/other use bytes - volatile musb_epn_regs_t *regs = (volatile musb_epn_regs_t*)(baseptr + ((epnum - 1) * 16)); - return regs; -} - -static inline volatile musb_ep0_regs_t* musb_dcd_ep0_regs(uint8_t rhport) -{ - volatile musb_ep0_regs_t *regs = (volatile musb_ep0_regs_t*)((uintptr_t)&(musb_periph_inst[rhport]->CSRL0)); - return regs; -} - typedef struct { uint_fast16_t beg; /* offset of including first element */ uint_fast16_t end; /* offset of excluding the last element */ diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h index c31e0c984..670bc2ca1 100644 --- a/src/portable/mentor/musb/musb_type.h +++ b/src/portable/mentor/musb/musb_type.h @@ -1,3 +1,29 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + /****************************************************************************** * * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ @@ -57,24 +83,29 @@ #define __R volatile const #endif -// Endpoint register mapping. Non-zero end points. -typedef struct TU_ATTR_PACKED { - uint16_t TXMAXP; - uint8_t TXCSRL; - uint8_t TXCSRH; - uint16_t RXMAXP; - uint8_t RXCSRL; - uint8_t RXCSRH; - uint16_t RXCOUNT; -} musb_epn_regs_t; - -// Endpoint 0 register mapping. typedef struct TU_ATTR_PACKED { - uint8_t CSRL0; - uint8_t CSRH0; - uint32_t RESERVED; - uint8_t COUNT0; -} musb_ep0_regs_t; + __IO uint16_t tx_maxp; // 0x00: TXMAXP + union { + __IO uint8_t csr0l; // 0x02: CSR0 + __IO uint8_t tx_csrl; // 0x02: TX CSRL + }; + union { + __IO uint8_t csr0h; // 0x03: CSR0H + __IO uint8_t tx_csrh; // 0x03: TX CSRH + }; + __IO uint16_t rx_maxp; // 0x04: RX MAXP + __IO uint8_t rx_csrl; // 0x06: RX CSRL + __IO uint8_t rx_csrh; // 0x07: RX CSRH + __IO uint16_t rx_count; // 0x08: RX COUNT + __IO uint8_t tx_type; // 0x0A: TX TYPE + __IO uint8_t tx_interval; // 0x0B: TX INTERVAL + __IO uint8_t rx_type; // 0x0C: RX TYPE + __IO uint8_t rx_interval; // 0x0D: RX INTERVAL + __IO uint8_t reserved_0x0e; // 0x0E: Reserved + __IO uint8_t fifo_size; // 0x0F: FIFO_SIZE +} musb_ep_csr_t; + +TU_VERIFY_STATIC(sizeof(musb_ep_csr_t) == 16, "size is not correct"); typedef struct { //------------- Common -------------// @@ -93,21 +124,14 @@ typedef struct { __IO uint16_t frame; // 0x0C: FRAME __IO uint8_t index; // 0x0E: INDEX __IO uint8_t testmode; // 0x0F: TESTMODE - __IO uint16_t inmaxp; // 0x10: INMAXP - union { - __IO uint8_t csr0; // 0x12: CSR0 - __IO uint8_t incsrl; // 0x12: INCSRL - }; - __IO uint8_t incsru; // 0x13: INCSRU - __IO uint16_t outmaxp; // 0x14: OUTMAXP - __IO uint8_t outcsrl; // 0x16: OUTCSRL - __IO uint8_t outcsru; // 0x17: OUTCSRU - union { - __IO uint16_t count0; // 0x18: COUNT0 - __IO uint16_t outcount; // 0x18: OUTCOUNT - }; - __R uint16_t rsv_0x1a_0x1f[3]; + + //------------- Indexed CSR -------------// + musb_ep_csr_t indexed_csr; // 0x10-0x1F: Indexed CSR 0-15 + + //------------- FIFOs -------------// __IO uint32_t fifo[16]; // 0x20-0x5C: FIFO 0-15 + + // Common (2) __IO uint8_t devctl; // 0x60: DEVCTL __IO uint8_t misc; // 0x61: MISC @@ -138,7 +162,13 @@ typedef struct { //------------- Extended -------------// __IO uint16_t ctuch; // 0x80: CTUCH __IO uint16_t cthsrtn; // 0x82: CTHSRTN - __R uint32_t rsv_0x84_0x3ff[223]; + __R uint32_t rsv_0x84_0xff[31]; // 0x84-0xFF: Reserved + + //------------- Absolute CSR (used index to remap to Indexed above) -------------// + // TI tm4c can access this directly, but should use indexed_csr for portability + musb_ep_csr_t ep_csr[16]; // 0x100-0x1FF: EP0-15 CSR + + __R uint32_t rsv_0x200_0x3ff[128]; // 0x200-0x3FF: Reserved //------------- Analog PHY -------------// __IO uint32_t mxm_usb_reg_00; // 0x400: MXM_USB_REG_00 @@ -187,6 +217,16 @@ typedef struct { TU_VERIFY_STATIC(sizeof(musb_regs_t) == 0x4A8, "size is not correct"); +//--------------------------------------------------------------------+ +// Helper +//--------------------------------------------------------------------+ + +TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_regs, unsigned epnum) { + musb_regs->index = epnum; + return &musb_regs->indexed_csr; +} + + //***************************************************************************** // // The following are defines for the bit fields in the USB_O_FADDR register. -- cgit v1.3.1 From 33e3ea36450a30d76113e5e356ddf5f99cdda2c5 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 15 Aug 2024 23:46:33 +0700 Subject: remove analog PHY from musb_regs_t hil: remove ch32v203 since not reliable enough --- src/portable/mentor/musb/musb_type.h | 138 ++++++++++++----------------------- test/hil/rpi.json | 14 ++-- 2 files changed, 55 insertions(+), 97 deletions(-) (limited to 'src/portable') diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h index 670bc2ca1..57ab2aefa 100644 --- a/src/portable/mentor/musb/musb_type.h +++ b/src/portable/mentor/musb/musb_type.h @@ -97,136 +97,94 @@ typedef struct TU_ATTR_PACKED { __IO uint8_t rx_csrl; // 0x06: RX CSRL __IO uint8_t rx_csrh; // 0x07: RX CSRH __IO uint16_t rx_count; // 0x08: RX COUNT - __IO uint8_t tx_type; // 0x0A: TX TYPE + union { + __IO uint8_t type0; // 0x0A: TYPE0 (host only) + __IO uint8_t tx_type; // 0x0A: TX TYPE + }; __IO uint8_t tx_interval; // 0x0B: TX INTERVAL __IO uint8_t rx_type; // 0x0C: RX TYPE __IO uint8_t rx_interval; // 0x0D: RX INTERVAL __IO uint8_t reserved_0x0e; // 0x0E: Reserved - __IO uint8_t fifo_size; // 0x0F: FIFO_SIZE + union { + __IO uint8_t config_data; // 0x0F: CONFIG DATA + __IO uint8_t fifo_size; // 0x0F: FIFO_SIZE + }; } musb_ep_csr_t; TU_VERIFY_STATIC(sizeof(musb_ep_csr_t) == 16, "size is not correct"); typedef struct { //------------- Common -------------// - __IO uint8_t faddr; // 0x00: FADDR - __IO uint8_t power; // 0x01: POWER + __IO uint8_t faddr; // 0x00: FADDR + __IO uint8_t power; // 0x01: POWER - __IO uint16_t intr_tx; // 0x02: INTR_TX - __IO uint16_t intr_rx; // 0x04: INTR_RX + __IO uint16_t intr_tx; // 0x02: INTR_TX + __IO uint16_t intr_rx; // 0x04: INTR_RX - __IO uint16_t intr_txen; // 0x06: INTR_TXEN - __IO uint16_t intr_rxen; // 0x08: INTR_RXEN + __IO uint16_t intr_txen; // 0x06: INTR_TXEN + __IO uint16_t intr_rxen; // 0x08: INTR_RXEN - __IO uint8_t intrusb; // 0x0A: INTRUSB - __IO uint8_t intrusben; // 0x0B: INTRUSBEN + __IO uint8_t intrusb; // 0x0A: INTRUSB + __IO uint8_t intrusben; // 0x0B: INTRUSBEN - __IO uint16_t frame; // 0x0C: FRAME - __IO uint8_t index; // 0x0E: INDEX - __IO uint8_t testmode; // 0x0F: TESTMODE + __IO uint16_t frame; // 0x0C: FRAME + __IO uint8_t index; // 0x0E: INDEX + __IO uint8_t testmode; // 0x0F: TESTMODE - //------------- Indexed CSR -------------// - musb_ep_csr_t indexed_csr; // 0x10-0x1F: Indexed CSR 0-15 + //------------- CSR (indexed) -------------// + musb_ep_csr_t indexed_csr; // 0x10-0x1F: Indexed CSR 0-15 //------------- FIFOs -------------// - __IO uint32_t fifo[16]; // 0x20-0x5C: FIFO 0-15 + __IO uint32_t fifo[16]; // 0x20-0x5C: FIFO 0-15 // Common (2) - __IO uint8_t devctl; // 0x60: DEVCTL - __IO uint8_t misc; // 0x61: MISC + __IO uint8_t devctl; // 0x60: DEVCTL + __IO uint8_t misc; // 0x61: MISC - //------------- Dynammic FIFO -------------// - __IO uint8_t txfifo_sz; // 0x62: TXFIFO_SZ - __IO uint8_t rxfifo_sz; // 0x63: RXFIFO_SZ - __IO uint16_t txfifo_addr; // 0x64: TXFIFO_ADDR - __IO uint16_t rxfifo_addr; // 0x66: RXFIFO_ADDR + //------------- Dynammic FIFO (indexed) -------------// + __IO uint8_t txfifo_sz; // 0x62: TXFIFO_SZ + __IO uint8_t rxfifo_sz; // 0x63: RXFIFO_SZ + __IO uint16_t txfifo_addr; // 0x64: TXFIFO_ADDR + __IO uint16_t rxfifo_addr; // 0x66: RXFIFO_ADDR //------------- Additional Control/Status -------------// union { - __O uint32_t vcontrol; // 0x68: VCONTROL - __IO uint32_t vstatus; // 0x68: VSTATUS + __O uint32_t vcontrol; // 0x68: VCONTROL + __IO uint32_t vstatus; // 0x68: VSTATUS }; - __IO uint16_t hwvers; // 0x6c: HWVERS - __R uint16_t rsv_0x6e_0x77[5]; - - //------------- Additional Configuration -------------// - __IO uint8_t epinfo; // 0x78: EPINFO - __IO uint8_t raminfo; // 0x79: RAMINFO - __IO uint8_t softreset; // 0x7A: SOFTRESET (Analog), Link info - __IO uint8_t vplen; // 0x7B: VPLEN - __IO uint8_t hs_eof1; // 0x7C: HS_EOF1 - __IO uint8_t fs_eof1; // 0x7D: FS_EOF1 - __IO uint8_t ls_eof1; // 0x7E: LS_EOF1 - __IO uint8_t soft_rst; // 0x7F: SOFT_RST + __IO uint16_t hwvers; // 0x6c: HWVERS + __R uint16_t rsv_0x6e_0x77[5]; // 0x6E-0x77: Reserved + + //------------- Additional Configuration -------------// + __IO uint8_t epinfo; // 0x78: EPINFO + __IO uint8_t raminfo; // 0x79: RAMINFO + __IO uint8_t softreset; // 0x7A: SOFTRESET (Analog), Link info + __IO uint8_t vplen; // 0x7B: VPLEN + __IO uint8_t hs_eof1; // 0x7C: HS_EOF1 + __IO uint8_t fs_eof1; // 0x7D: FS_EOF1 + __IO uint8_t ls_eof1; // 0x7E: LS_EOF1 + __IO uint8_t soft_rst; // 0x7F: SOFT_RST //------------- Extended -------------// - __IO uint16_t ctuch; // 0x80: CTUCH - __IO uint16_t cthsrtn; // 0x82: CTHSRTN - __R uint32_t rsv_0x84_0xff[31]; // 0x84-0xFF: Reserved + __IO uint16_t ctuch; // 0x80: CTUCH + __IO uint16_t cthsrtn; // 0x82: CTHSRTN + __R uint32_t rsv_0x84_0xff[31]; // 0x84-0xFF: Reserved //------------- Absolute CSR (used index to remap to Indexed above) -------------// // TI tm4c can access this directly, but should use indexed_csr for portability - musb_ep_csr_t ep_csr[16]; // 0x100-0x1FF: EP0-15 CSR - - __R uint32_t rsv_0x200_0x3ff[128]; // 0x200-0x3FF: Reserved - - //------------- Analog PHY -------------// - __IO uint32_t mxm_usb_reg_00; // 0x400: MXM_USB_REG_00 - __IO uint32_t m31_phy_utmi_reset; // 0x404: M31_PHY_UTMI_RESET - __IO uint32_t m31_phy_utmi_vcontrol; // 0x408: M31_PHY_UTMI_VCONTROL - __IO uint32_t m31_phy_clk_en; // 0x40C: M31_PHY_CLK_EN - __IO uint32_t m31_phy_ponrst; // 0x410: M31_PHY_PONRST - __IO uint32_t m31_phy_noncry_rstb; // 0x414: M31_PHY_NONCRY_RSTB - __IO uint32_t m31_phy_noncry_en; // 0x418: M31_PHY_NONCRY_EN - __R uint32_t rsv_0x41c; - __IO uint32_t m31_phy_u2_compliance_en; // 0x420: M31_PHY_U2_COMPLIANCE_EN - __IO uint32_t m31_phy_u2_compliance_dac_adj; // 0x424: M31_PHY_U2_COMPLIANCE_DAC_ADJ - __IO uint32_t m31_phy_u2_compliance_dac_adj_en; // 0x428: M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN - __IO uint32_t m31_phy_clk_rdy; // 0x42C: M31_PHY_CLK_RDY - __IO uint32_t m31_phy_pll_en; // 0x430: M31_PHY_PLL_EN - __IO uint32_t m31_phy_bist_ok; // 0x434: M31_PHY_BIST_OK - __IO uint32_t m31_phy_data_oe; // 0x438: M31_PHY_DATA_OE - __IO uint32_t m31_phy_oscouten; // 0x43C: M31_PHY_OSCOUTEN - __IO uint32_t m31_phy_lpm_alive; // 0x440: M31_PHY_LPM_ALIVE - __IO uint32_t m31_phy_hs_bist_mode; // 0x444: M31_PHY_HS_BIST_MODE - __IO uint32_t m31_phy_coreclkin; // 0x448: M31_PHY_CORECLKIN - __IO uint32_t m31_phy_xtlsel; // 0x44C: M31_PHY_XTLSEL - __IO uint32_t m31_phy_ls_en; // 0x450: M31_PHY_LS_EN - __IO uint32_t m31_phy_debug_sel; // 0x454: M31_PHY_DEBUG_SEL - __IO uint32_t m31_phy_debug_out; // 0x458: M31_PHY_DEBUG_OUT - __IO uint32_t m31_phy_outclksel; // 0x45C: M31_PHY_OUTCLKSEL - __IO uint32_t m31_phy_xcfgi_31_0; // 0x460: M31_PHY_XCFGI_31_0 - __IO uint32_t m31_phy_xcfgi_63_32; // 0x464: M31_PHY_XCFGI_63_32 - __IO uint32_t m31_phy_xcfgi_95_64; // 0x468: M31_PHY_XCFGI_95_64 - __IO uint32_t m31_phy_xcfgi_127_96; // 0x46C: M31_PHY_XCFGI_127_96 - __IO uint32_t m31_phy_xcfgi_137_128; // 0x470: M31_PHY_XCFGI_137_128 - __IO uint32_t m31_phy_xcfg_hs_coarse_tune_num; // 0x474: M31_PHY_XCFG_HS_COARSE_TUNE_NUM - __IO uint32_t m31_phy_xcfg_hs_fine_tune_num; // 0x478: M31_PHY_XCFG_HS_FINE_TUNE_NUM - __IO uint32_t m31_phy_xcfg_fs_coarse_tune_num; // 0x47C: M31_PHY_XCFG_FS_COARSE_TUNE_NUM - __IO uint32_t m31_phy_xcfg_fs_fine_tune_num; // 0x480: M31_PHY_XCFG_FS_FINE_TUNE_NUM - __IO uint32_t m31_phy_xcfg_lock_range_max; // 0x484: M31_PHY_XCFG_LOCK_RANGE_MAX - __IO uint32_t m31_phy_xcfgi_lock_range_min; // 0x488: M31_PHY_XCFGI_LOCK_RANGE_MIN - __IO uint32_t m31_phy_xcfg_ob_rsel; // 0x48C: M31_PHY_XCFG_OB_RSEL - __IO uint32_t m31_phy_xcfg_oc_rsel; // 0x490: M31_PHY_XCFG_OC_RSEL - __IO uint32_t m31_phy_xcfgo; // 0x494: M31_PHY_XCFGO - __IO uint32_t mxm_int; // 0x498: MXM_INT - __IO uint32_t mxm_int_en; // 0x49C: MXM_INT_EN - __IO uint32_t mxm_suspend; // 0x4A0: MXM_SUSPEND - __IO uint32_t mxm_reg_a4; // 0x4A4: MXM_REG_A4 + musb_ep_csr_t ep_csr[16]; // 0x100-0x1FF: EP0-15 CSR } musb_regs_t; -TU_VERIFY_STATIC(sizeof(musb_regs_t) == 0x4A8, "size is not correct"); +TU_VERIFY_STATIC(sizeof(musb_regs_t) == 0x200, "size is not correct"); //--------------------------------------------------------------------+ // Helper //--------------------------------------------------------------------+ - TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_regs, unsigned epnum) { musb_regs->index = epnum; return &musb_regs->indexed_csr; } - //***************************************************************************** // // The following are defines for the bit fields in the USB_O_FADDR register. diff --git a/test/hil/rpi.json b/test/hil/rpi.json index 688ea3822..b7d36c543 100644 --- a/test/hil/rpi.json +++ b/test/hil/rpi.json @@ -50,13 +50,6 @@ "flasher": "openocd", "flasher_sn": "066FFF495087534867063844", "flasher_args": "-f interface/stlink.cfg -f target/stm32g0x.cfg" - }, - { - "name": "nanoch32v203", - "uid": "CDAB277B0FBC03E339E339E3", - "flasher": "openocd_wch", - "flasher_sn": "EBCA8F0670AF", - "flasher_args": "" } ], "boards-skip": [ @@ -68,6 +61,13 @@ "flasher_args": "-device MIMXRT1011xxx5A", "comment": "not running reliably in bulk with other boards, probably power, flashing etc .." }, + { + "name": "nanoch32v203", + "uid": "CDAB277B0FBC03E339E339E3", + "flasher": "openocd_wch", + "flasher_sn": "EBCA8F0670AF", + "flasher_args": "" + }, { "name": "espressif_s3_devkitm", "uid": "84F703C084E4", -- cgit v1.3.1 From eaf9cc1beb6f5e34683debe531c7fa4d012c47b2 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 17 Aug 2024 13:31:31 +0700 Subject: more refactor to simplify musb driver --- src/common/tusb_mcu.h | 2 + src/portable/mentor/musb/dcd_musb.c | 176 +-- src/portable/mentor/musb/musb_max32.h | 66 +- src/portable/mentor/musb/musb_ti.h | 47 +- src/portable/mentor/musb/musb_type.h | 2387 +++++++++++++-------------------- 5 files changed, 1090 insertions(+), 1588 deletions(-) (limited to 'src/portable') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 7ec3c5842..0180fc466 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -309,6 +309,7 @@ #elif TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) #define TUP_USBIP_MUSB + #define TUP_USBIP_MUSB_TI #define TUP_DCD_ENDPOINT_MAX 8 //--------------------------------------------------------------------+ @@ -474,6 +475,7 @@ //--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX32690, OPT_MCU_MAX78002) #define TUP_USBIP_MUSB + #define TUP_USBIP_MUSB_ADI #define TUP_DCD_ENDPOINT_MAX 12 #define TUP_RHPORT_HIGHSPEED 1 diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 48f6e9d97..36690c952 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -41,10 +41,10 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); // Following symbols must be defined by port header // - musb_dcd_int_enable/disable/clear/get_enable // - musb_dcd_int_handler_enter/exit -// - musb_dcd_setup_fifo/reset_fifo: Configuration of the EP's FIFO -#if TU_CHECK_MCU(OPT_MCU_MSP432E4, OPT_MCU_TM4C123, OPT_MCU_TM4C129) +// - musb_dcd_setup_fifo: Configuration of the EP's FIFO +#if defined(TUP_USBIP_MUSB_TI) #include "musb_ti.h" -#elif TU_CHECK_MCU(OPT_MCU_MAX32690, OPT_MCU_MAX32650, OPT_MCU_MAX32666, OPT_MCU_MAX78002) +#elif defined(TUP_USBIP_MUSB_ADI) #include "musb_max32.h" #else #error "Unsupported MCU" @@ -52,6 +52,8 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); #define MUSB_REGS(rhport) ((musb_regs_t*) MUSB_BASES[rhport]) +#define MUSB_DEBUG 2 + /*------------------------------------------------------------------ * MACRO TYPEDEF CONSTANT ENUM DECLARATION *------------------------------------------------------------------*/ @@ -86,6 +88,18 @@ typedef struct *------------------------------------------------------------------*/ static dcd_data_t _dcd; +TU_ATTR_ALWAYS_INLINE static inline void fifo_reset(musb_regs_t* musb, unsigned epnum, unsigned dir_in) { + musb->index = epnum; + const uint8_t is_rx = 1 - dir_in; + +#if MUSB_CFG_DYNAMIC_FIFO + musb->fifo_size[is_rx] = 0; + musb->fifo_addr[is_rx] = 0; +#elif defined(TUP_USBIP_MUSB_ADI) + // Analog have custom double buffered in csrh register, disable it + musb->indexed_csr.maxp_csr[is_rx].csrh |= MUSB_CSRH_DISABLE_DOUBLE_PACKET(is_rx); +#endif +} static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { @@ -363,13 +377,13 @@ static void process_ep0(uint8_t rhport) /* Received SETUP or DATA OUT packet */ if (req == REQUEST_TYPE_INVALID) { /* SETUP */ - TU_ASSERT(sizeof(tusb_control_request_t) == ep_csr->rx_count,); + TU_ASSERT(sizeof(tusb_control_request_t) == ep_csr->count0,); process_setup_packet(rhport); return; } if (_dcd.pipe0.buf) { /* DATA OUT */ - const unsigned vld = ep_csr->rx_count; + const unsigned vld = ep_csr->count0; const unsigned rem = _dcd.pipe0.remaining; const unsigned len = TU_MIN(TU_MIN(rem, 64), vld); volatile void *fifo_ptr = &musb_regs->fifo[0]; @@ -445,47 +459,70 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) } } -static void process_bus_reset(uint8_t rhport) -{ - musb_regs_t* musb_regs = MUSB_REGS(rhport); - /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), - * a control transfer state is SETUP or STATUS stage. */ +// Upon BUS RESET is detected, hardware havs already done: +// faddr = 0, index = 0, flushes all ep fifos, clears all ep csr, enabled all ep interrupts +static void process_bus_reset(uint8_t rhport) { + musb_regs_t* musb = MUSB_REGS(rhport); + /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), a control transfer state is SETUP or STATUS stage. */ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; _dcd.status_out = 0; /* When pipe0.buf has not NULL, DATA stage works in progress. */ _dcd.pipe0.buf = NULL; - musb_regs->intr_txen = 1; /* Enable only EP0 */ - musb_regs->intr_rxen = 0; + musb->intr_txen = 1; /* Enable only EP0 */ + musb->intr_rxen = 0; /* Clear FIFO settings */ for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { - musb_dcd_reset_fifo(rhport, i, 0); - musb_dcd_reset_fifo(rhport, i, 1); + fifo_reset(musb, i, 0); + fifo_reset(musb, i, 1); } - dcd_event_bus_reset(rhport, (musb_regs->power & USB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); + dcd_event_bus_reset(rhport, (musb->power & USB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); } /*------------------------------------------------------------------ * Device API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport) -{ +#if CFG_TUSB_DEBUG >= MUSB_DEBUG +void print_musb_info(musb_regs_t* musb_regs) { + // print version, epinfo, raminfo, config_data0, fifo_size + TU_LOG1("musb version = %u.%u\r\n", musb_regs->hwvers_bit.major, musb_regs->hwvers_bit.minor); + TU_LOG1("Number of endpoints: %u TX, %u RX\r\n", musb_regs->epinfo_bit.tx_ep_num, musb_regs->epinfo_bit.rx_ep_num); + TU_LOG1("RAM Info: %u DMA Channel, %u RAM address width\r\n", musb_regs->raminfo_bit.dma_channel, musb_regs->raminfo_bit.ram_bits); + + musb_regs->index = 0; + TU_LOG1("config_data0 = 0x%x\r\n", musb_regs->indexed_csr.config_data0); + +#if MUSB_CFG_DYNAMIC_FIFO + TU_LOG1("Dynamic FIFO configuration\r\n"); +#else + for (uint8_t i=1; i <= musb_regs->epinfo_bit.tx_ep_num; i++) { + musb_regs->index = i; + TU_LOG1("FIFO %u Size: TX %u RX %u\r\n", i, musb_regs->indexed_csr.fifo_size_bit.tx, musb_regs->indexed_csr.fifo_size_bit.rx); + } +#endif +} +#endif + +void dcd_init(uint8_t rhport) { musb_regs_t* musb_regs = MUSB_REGS(rhport); - musb_regs->intrusben |= USB_IE_SUSPND; + +#if CFG_TUSB_DEBUG >= MUSB_DEBUG + print_musb_info(musb_regs); +#endif + + musb_regs->intr_usben |= USB_IE_SUSPND; musb_dcd_int_clear(rhport); musb_dcd_phy_init(rhport); dcd_connect(rhport); } -void dcd_int_enable(uint8_t rhport) -{ +void dcd_int_enable(uint8_t rhport) { musb_dcd_int_enable(rhport); } -void dcd_int_disable(uint8_t rhport) -{ +void dcd_int_disable(uint8_t rhport) { musb_dcd_int_disable(rhport); } @@ -559,25 +596,17 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) musb_regs_t* musb_regs = MUSB_REGS(rhport); musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn); - if (dir_in) { - ep_csr->tx_maxp = mps; - ep_csr->tx_csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_TXCSRH1_ISO : 0; - if (ep_csr->tx_csrl & USB_TXCSRL1_TXRDY) { - ep_csr->tx_csrl = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; - } else { - ep_csr->tx_csrl = USB_TXCSRL1_CLRDT; - } - musb_regs->intr_txen |= TU_BIT(epn); - } else { - ep_csr->rx_maxp = mps; - ep_csr->rx_csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0; - if (ep_csr->rx_csrl & USB_RXCSRL1_RXRDY) { - ep_csr->rx_csrl = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; - } else { - ep_csr->rx_csrl = USB_RXCSRL1_CLRDT; - } - musb_regs->intr_rxen |= TU_BIT(epn); + + const uint8_t is_rx = 1 - dir_in; + ep_csr->maxp_csr[is_rx].maxp = mps; + ep_csr->maxp_csr[is_rx].csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0; + + uint8_t csrl = MUSB_CSRL_CLEAR_DATA_TOGGLE(is_rx); + if (ep_csr->maxp_csr[is_rx].csrl & MUSB_CSRL_PACKET_READY(is_rx)) { + csrl |= MUSB_CSRL_FLUSH_FIFO(is_rx); } + ep_csr->maxp_csr[is_rx].csrl = csrl; + musb_regs->intren_ep[is_rx] |= TU_BIT(epn); /* Setup FIFO */ musb_dcd_setup_fifo(rhport, epn, dir_in, mps); @@ -587,13 +616,13 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) void dcd_edpt_close_all(uint8_t rhport) { - musb_regs_t* musb_regs = MUSB_REGS(rhport); + musb_regs_t* musb = MUSB_REGS(rhport); unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); - musb_regs->intr_txen = 1; /* Enable only EP0 */ - musb_regs->intr_rxen = 0; + musb->intr_txen = 1; /* Enable only EP0 */ + musb->intr_rxen = 0; for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { - musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, i); + musb_ep_csr_t* ep_csr = get_ep_csr(musb, i); ep_csr->tx_maxp = 0; ep_csr->tx_csrh = 0; if (ep_csr->tx_csrl & USB_TXCSRL1_TXRDY) @@ -609,8 +638,8 @@ void dcd_edpt_close_all(uint8_t rhport) ep_csr->rx_csrl = USB_RXCSRL1_CLRDT; } - musb_dcd_reset_fifo(rhport, i, 0); - musb_dcd_reset_fifo(rhport, i, 1); + fifo_reset(musb, i, 0); + fifo_reset(musb, i, 1); } if (ie) musb_dcd_int_enable(rhport); @@ -620,12 +649,12 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { unsigned const epn = tu_edpt_number(ep_addr); unsigned const dir_in = tu_edpt_dir(ep_addr); - musb_regs_t* musb_regs = MUSB_REGS(rhport); - musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn); + musb_regs_t* musb = MUSB_REGS(rhport); + musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn); unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); if (dir_in) { - musb_regs->intr_txen &= ~TU_BIT(epn); + musb->intr_txen &= ~TU_BIT(epn); ep_csr->tx_maxp = 0; ep_csr->tx_csrh = 0; if (ep_csr->tx_csrl & USB_TXCSRL1_TXRDY) { @@ -634,7 +663,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) ep_csr->tx_csrl = USB_TXCSRL1_CLRDT; } } else { - musb_regs->intr_rxen &= ~TU_BIT(epn); + musb->intr_rxen &= ~TU_BIT(epn); ep_csr->rx_maxp = 0; ep_csr->rx_csrh = 0; if (ep_csr->rx_csrl & USB_RXCSRL1_RXRDY) { @@ -643,7 +672,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) ep_csr->rx_csrl = USB_RXCSRL1_CLRDT; } } - musb_dcd_reset_fifo(rhport, epn, dir_in); + fifo_reset(musb, epn, dir_in); if (ie) musb_dcd_int_enable(rhport); } @@ -726,51 +755,48 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) /*------------------------------------------------------------------- * ISR *-------------------------------------------------------------------*/ -void dcd_int_handler(uint8_t rhport) -{ - uint_fast8_t is, txis, rxis; - +void dcd_int_handler(uint8_t rhport) { //Part specific ISR setup/entry musb_dcd_int_handler_enter(rhport); musb_regs_t* musb_regs = MUSB_REGS(rhport); - - is = musb_regs->intrusb; /* read and clear interrupt status */ - txis = musb_regs->intr_tx; /* read and clear interrupt status */ - rxis = musb_regs->intr_rx; /* read and clear interrupt status */ + uint_fast8_t intr_usb = musb_regs->intr_usb; // a read will clear this interrupt status + uint_fast8_t intr_tx = musb_regs->intr_tx; // a read will clear this interrupt status + uint_fast8_t intr_rx = musb_regs->intr_rx; // a read will clear this interrupt status // TU_LOG1("D%2x T%2x R%2x\r\n", is, txis, rxis); - is &= musb_regs->intrusben; /* Clear disabled interrupts */ - if (is & USB_IS_DISCON) { + intr_usb &= musb_regs->intr_usben; /* Clear disabled interrupts */ + if (intr_usb & USB_IS_DISCON) { } - if (is & USB_IS_SOF) { + if (intr_usb & USB_IS_SOF) { dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); } - if (is & USB_IS_RESET) { + if (intr_usb & USB_IS_RESET) { process_bus_reset(rhport); } - if (is & USB_IS_RESUME) { + if (intr_usb & USB_IS_RESUME) { dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); } - if (is & USB_IS_SUSPEND) { + if (intr_usb & USB_IS_SUSPEND) { dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); } - txis &= musb_regs->intr_txen; /* Clear disabled interrupts */ - if (txis & USB_TXIE_EP0) { + intr_tx &= musb_regs->intr_txen; /* Clear disabled interrupts */ + if (intr_tx & TU_BIT(0)) { process_ep0(rhport); - txis &= ~TU_BIT(0); + intr_tx &= ~TU_BIT(0); } - while (txis) { - unsigned const num = __builtin_ctz(txis); + while (intr_tx) { + unsigned const num = __builtin_ctz(intr_tx); process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_IN)); - txis &= ~TU_BIT(num); + intr_tx &= ~TU_BIT(num); } - rxis &= musb_regs->intr_rxen; /* Clear disabled interrupts */ - while (rxis) { - unsigned const num = __builtin_ctz(rxis); + + intr_rx &= musb_regs->intr_rxen; /* Clear disabled interrupts */ + while (intr_rx) { + unsigned const num = __builtin_ctz(intr_rx); process_edpt_n(rhport, tu_edpt_addr(num, TUSB_DIR_OUT)); - rxis &= ~TU_BIT(num); + intr_rx &= ~TU_BIT(num); } //Part specific ISR exit diff --git a/src/portable/mentor/musb/musb_max32.h b/src/portable/mentor/musb/musb_max32.h index 43f56de3c..73f63ee2e 100644 --- a/src/portable/mentor/musb/musb_max32.h +++ b/src/portable/mentor/musb/musb_max32.h @@ -34,6 +34,8 @@ extern "C" { #include "mxc_device.h" #include "usbhs_regs.h" +#define MUSB_CFG_DYNAMIC_FIFO 0 + const uintptr_t MUSB_BASES[] = { MXC_BASE_USBHS }; #if CFG_TUD_ENABLED @@ -100,40 +102,43 @@ static inline void musb_dcd_int_handler_exit(uint8_t rhport) { } static inline void musb_dcd_phy_init(uint8_t rhport) { - //Interrupt for VBUS disconnect - musb_periph_inst[rhport]->mxm_int_en |= MXC_F_USBHS_MXM_INT_EN_NOVBUS; + (void) rhport; + mxc_usbhs_regs_t* hs_phy = MXC_USBHS; + + // Interrupt for VBUS disconnect + hs_phy->mxm_int_en |= MXC_F_USBHS_MXM_INT_EN_NOVBUS; musb_dcd_int_clear(rhport); - //Unsuspend the MAC - musb_periph_inst[rhport]->mxm_suspend = 0; + // Unsuspend the MAC + hs_phy->mxm_suspend = 0; // Configure PHY - musb_periph_inst[rhport]->m31_phy_xcfgi_31_0 = (0x1 << 3) | (0x1 << 11); - musb_periph_inst[rhport]->m31_phy_xcfgi_63_32 = 0; - musb_periph_inst[rhport]->m31_phy_xcfgi_95_64 = 0x1 << (72 - 64); - musb_periph_inst[rhport]->m31_phy_xcfgi_127_96 = 0; + hs_phy->m31_phy_xcfgi_31_0 = (0x1 << 3) | (0x1 << 11); + hs_phy->m31_phy_xcfgi_63_32 = 0; + hs_phy->m31_phy_xcfgi_95_64 = 0x1 << (72 - 64); + hs_phy->m31_phy_xcfgi_127_96 = 0; #ifdef USBHS_M31_CLOCK_RECOVERY - musb_periph_inst[rhport]->m31_phy_noncry_rstb = 1; - musb_periph_inst[rhport]->m31_phy_noncry_en = 1; - musb_periph_inst[rhport]->m31_phy_outclksel = 0; - musb_periph_inst[rhport]->m31_phy_coreclkin = 0; - musb_periph_inst[rhport]->m31_phy_xtlsel = 2; /* Select 25 MHz clock */ + hs_phy->m31_phy_noncry_rstb = 1; + hs_phy->m31_phy_noncry_en = 1; + hs_phy->m31_phy_outclksel = 0; + hs_phy->m31_phy_coreclkin = 0; + hs_phy->m31_phy_xtlsel = 2; /* Select 25 MHz clock */ #else - musb_periph_inst[rhport]->m31_phy_noncry_rstb = 0; - musb_periph_inst[rhport]->m31_phy_noncry_en = 0; - musb_periph_inst[rhport]->m31_phy_outclksel = 1; - musb_periph_inst[rhport]->m31_phy_coreclkin = 1; - musb_periph_inst[rhport]->m31_phy_xtlsel = 3; /* Select 30 MHz clock */ + hs_phy->m31_phy_noncry_rstb = 0; + hs_phy->m31_phy_noncry_en = 0; + hs_phy->m31_phy_outclksel = 1; + hs_phy->m31_phy_coreclkin = 1; + hs_phy->m31_phy_xtlsel = 3; /* Select 30 MHz clock */ #endif - musb_periph_inst[rhport]->m31_phy_pll_en = 1; - musb_periph_inst[rhport]->m31_phy_oscouten = 1; + hs_phy->m31_phy_pll_en = 1; + hs_phy->m31_phy_oscouten = 1; /* Reset PHY */ - musb_periph_inst[rhport]->m31_phy_ponrst = 0; - musb_periph_inst[rhport]->m31_phy_ponrst = 1; + hs_phy->m31_phy_ponrst = 0; + hs_phy->m31_phy_ponrst = 1; } static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) { @@ -155,23 +160,6 @@ static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned musb_periph_inst[rhport]->index = saved_index; } -static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in) { - //Most likely the caller has already grabbed the right register block. But - //as a precaution save and restore the register bank anyways - unsigned saved_index = musb_periph_inst[rhport]->index; - - musb_periph_inst[rhport]->index = epnum; - - //Disable double buffering - if (dir_in) { - musb_periph_inst[rhport]->incsru |= (MXC_F_USBHS_INCSRU_DPKTBUFDIS); - } else { - musb_periph_inst[rhport]->outcsru |= (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS); - } - - musb_periph_inst[rhport]->index = saved_index; -} - #endif // CFG_TUD_ENABLED #ifdef __cplusplus diff --git a/src/portable/mentor/musb/musb_ti.h b/src/portable/mentor/musb/musb_ti.h index d1a0aa4f9..e43b3d3c0 100644 --- a/src/portable/mentor/musb/musb_ti.h +++ b/src/portable/mentor/musb/musb_ti.h @@ -42,8 +42,10 @@ #error "Unsupported MCUs" #endif -const uintptr_t MUSB_BASES[] = { USB0_BASE }; +#define MUSB_CFG_DYNAMIC_FIFO 1 +#define MUSB_CFG_DYNAMIC_FIFO_SIZE 4096 +const uintptr_t MUSB_BASES[] = { USB0_BASE }; // Header supports both device and host modes. Only include what's necessary #if CFG_TUD_ENABLED @@ -63,36 +65,28 @@ static inline void musb_dcd_phy_init(uint8_t rhport){ //Nothing to do for this part } -TU_ATTR_ALWAYS_INLINE -static inline void musb_dcd_int_enable(uint8_t rhport) -{ +TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_enable(uint8_t rhport) { NVIC_EnableIRQ(musb_irqs[rhport]); } -TU_ATTR_ALWAYS_INLINE -static inline void musb_dcd_int_disable(uint8_t rhport) -{ +TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_disable(uint8_t rhport) { NVIC_DisableIRQ(musb_irqs[rhport]); } -TU_ATTR_ALWAYS_INLINE -static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) -{ +TU_ATTR_ALWAYS_INLINE static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) { return NVIC_GetEnableIRQ(musb_irqs[rhport]); } -TU_ATTR_ALWAYS_INLINE -static inline void musb_dcd_int_clear(uint8_t rhport) -{ - NVIC_ClearPendingIRQ(musb_irqs[rhport]); +TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_clear(uint8_t rhport) { + NVIC_ClearPendingIRQ(musb_irqs[rhport]); } -static inline void musb_dcd_int_handler_enter(uint8_t rhport){ +static inline void musb_dcd_int_handler_enter(uint8_t rhport) { (void)rhport; //Nothing to do for this part } -static inline void musb_dcd_int_handler_exit(uint8_t rhport){ +static inline void musb_dcd_int_handler_exit(uint8_t rhport) { (void)rhport; //Nothing to do for this part } @@ -102,15 +96,13 @@ typedef struct { uint_fast16_t end; /* offset of excluding the last element */ } free_block_t; -static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr) -{ +static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr) { free_block_t *cur = beg; for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ; return cur; } -static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size) -{ +static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size) { free_block_t *p = find_containing_block(blks, blks + num, addr); TU_ASSERT(p != blks + num, -2); if (p->beg == addr) { @@ -150,8 +142,7 @@ static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_ } } -static inline unsigned free_block_size(free_block_t const *blk) -{ +static inline unsigned free_block_size(free_block_t const *blk) { return blk->end - blk->beg; } @@ -234,18 +225,6 @@ static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned } } -static inline void musb_dcd_reset_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in) -{ - musb_periph_inst[rhport]->EPIDX = epnum; - if (dir_in) { - musb_periph_inst[rhport]->TXFIFOADD = 0; - musb_periph_inst[rhport]->TXFIFOSZ = 0; - } else { - musb_periph_inst[rhport]->RXFIFOADD = 0; - musb_periph_inst[rhport]->RXFIFOSZ = 0; - } -} - #endif // CFG_TUD_ENABLED #ifdef __cplusplus diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h index 57ab2aefa..ee0187270 100644 --- a/src/portable/mentor/musb/musb_type.h +++ b/src/portable/mentor/musb/musb_type.h @@ -83,20 +83,37 @@ #define __R volatile const #endif +// 0: TX (device IN, host OUT) +// 1: RX (device OUT, host IN) typedef struct TU_ATTR_PACKED { - __IO uint16_t tx_maxp; // 0x00: TXMAXP union { - __IO uint8_t csr0l; // 0x02: CSR0 - __IO uint8_t tx_csrl; // 0x02: TX CSRL + struct { + __IO uint16_t tx_maxp; // 0x00: TXMAXP + union { + __IO uint8_t csr0l; // 0x02: CSR0 + __IO uint8_t tx_csrl; // 0x02: TX CSRL + }; + union { + __IO uint8_t csr0h; // 0x03: CSR0H + __IO uint8_t tx_csrh; // 0x03: TX CSRH + }; + + __IO uint16_t rx_maxp; // 0x04: RX MAXP + __IO uint8_t rx_csrl; // 0x06: RX CSRL + __IO uint8_t rx_csrh; // 0x07: RX CSRH + }; + + struct { + __IO uint16_t maxp; // 0x00: MAXP + __IO uint8_t csrl; // 0x02: CSRL + __IO uint8_t csrh; // 0x03: CSRH + }maxp_csr[2]; }; + union { - __IO uint8_t csr0h; // 0x03: CSR0H - __IO uint8_t tx_csrh; // 0x03: TX CSRH + __IO uint16_t count0; // 0x08: COUNT0 + __IO uint16_t rx_count; // 0x08: RX COUNT }; - __IO uint16_t rx_maxp; // 0x04: RX MAXP - __IO uint8_t rx_csrl; // 0x06: RX CSRL - __IO uint8_t rx_csrh; // 0x07: RX CSRH - __IO uint16_t rx_count; // 0x08: RX COUNT union { __IO uint8_t type0; // 0x0A: TYPE0 (host only) __IO uint8_t tx_type; // 0x0A: TX TYPE @@ -106,32 +123,71 @@ typedef struct TU_ATTR_PACKED { __IO uint8_t rx_interval; // 0x0D: RX INTERVAL __IO uint8_t reserved_0x0e; // 0x0E: Reserved union { - __IO uint8_t config_data; // 0x0F: CONFIG DATA + __IO uint8_t config_data0; // 0x0F: CONFIG DATA + struct { + __IO uint8_t utmi_data_width : 1; // [0] UTMI Data Width + __IO uint8_t softconn_en : 1; // [1] Soft Connect Enable + __IO uint8_t dynamic_fifo : 1; // [2] Dynamic FIFO Sizing + __IO uint8_t hb_tx_en : 1; // [3] High Bandwidth TX ISO Enable + __IO uint8_t hb_rx_en : 1; // [4] High Bandwidth RX ISO Enable + __IO uint8_t big_endian : 1; // [5] Big Endian + __IO uint8_t mp_tx_en : 1; // [6] Auto splitting BULK TX Enable + __IO uint8_t mp_rx_en : 1; // [7] Auto amalgamation BULK RX Enable + } config_data0_bit; + __IO uint8_t fifo_size; // 0x0F: FIFO_SIZE + struct { + __IO uint8_t tx : 4; // [3:0] TX FIFO Size + __IO uint8_t rx : 4; // [7:4] RX FIFO Size + }fifo_size_bit; }; } musb_ep_csr_t; TU_VERIFY_STATIC(sizeof(musb_ep_csr_t) == 16, "size is not correct"); -typedef struct { +typedef struct TU_ATTR_PACKED { //------------- Common -------------// __IO uint8_t faddr; // 0x00: FADDR - __IO uint8_t power; // 0x01: POWER + union { + __IO uint8_t power; // 0x01: POWER + struct { + __IO uint8_t suspend_mode_en : 1; // [0] SUSPEND Mode Enable + __IO uint8_t suspend_mode : 1; // [1] SUSPEND Mode + __IO uint8_t resume_mode : 1; // [2] RESUME + __IO uint8_t reset : 1; // [3] RESET + __IO uint8_t highspeed_mode : 1; // [4] High Speed Mode + __IO uint8_t highspeed_en : 1; // [5] High Speed Enable + __IO uint8_t soft_conn : 1; // [6] Soft Connect/Disconnect + __IO uint8_t iso_update : 1; // [7] Isochronous Update + } power_bit; + }; + + union { + struct { + __IO uint16_t intr_tx; // 0x02: INTR_TX + __IO uint16_t intr_rx; // 0x04: INTR_RX + }; + + __IO uint16_t intr_ep[2]; // 0x02-0x05: INTR_EP0-1 + }; - __IO uint16_t intr_tx; // 0x02: INTR_TX - __IO uint16_t intr_rx; // 0x04: INTR_RX + union { + struct { + __IO uint16_t intr_txen; // 0x06: INTR_TXEN + __IO uint16_t intr_rxen; // 0x08: INTR_RXEN + }; - __IO uint16_t intr_txen; // 0x06: INTR_TXEN - __IO uint16_t intr_rxen; // 0x08: INTR_RXEN + __IO uint16_t intren_ep[2]; // 0x06-0x09: INTREN_EP0-1 + }; - __IO uint8_t intrusb; // 0x0A: INTRUSB - __IO uint8_t intrusben; // 0x0B: INTRUSBEN + __IO uint8_t intr_usb; // 0x0A: INTRUSB + __IO uint8_t intr_usben; // 0x0B: INTRUSBEN __IO uint16_t frame; // 0x0C: FRAME __IO uint8_t index; // 0x0E: INDEX __IO uint8_t testmode; // 0x0F: TESTMODE - //------------- CSR (indexed) -------------// + //------------- Endpoint CSR (indexed) -------------// musb_ep_csr_t indexed_csr; // 0x10-0x1F: Indexed CSR 0-15 //------------- FIFOs -------------// @@ -142,35 +198,68 @@ typedef struct { __IO uint8_t misc; // 0x61: MISC //------------- Dynammic FIFO (indexed) -------------// - __IO uint8_t txfifo_sz; // 0x62: TXFIFO_SZ - __IO uint8_t rxfifo_sz; // 0x63: RXFIFO_SZ - __IO uint16_t txfifo_addr; // 0x64: TXFIFO_ADDR - __IO uint16_t rxfifo_addr; // 0x66: RXFIFO_ADDR + union { + struct { + __IO uint8_t txfifo_sz; // 0x62: TXFIFO_SZ + __IO uint8_t rxfifo_sz; // 0x63: RXFIFO_SZ + }; + __IO uint8_t fifo_size[2]; + }; + + union { + struct { + __IO uint16_t txfifo_addr; // 0x64: TXFIFO_ADDR + __IO uint16_t rxfifo_addr; // 0x66: RXFIFO_ADDR + }; + __IO uint16_t fifo_addr[2]; + }; - //------------- Additional Control/Status -------------// + //------------- Additional Control and Configuration -------------// + union { + __O uint32_t vcontrol; // 0x68: PHY VCONTROL + __IO uint32_t vstatus; // 0x68: PHY VSTATUS + }; union { - __O uint32_t vcontrol; // 0x68: VCONTROL - __IO uint32_t vstatus; // 0x68: VSTATUS + __IO uint16_t hwvers; // 0x6C: HWVERS + struct { + __IO uint16_t minor : 10; // [9:0] Minor + __IO uint16_t major : 5; // [14:10] Major + __IO uint16_t rc : 1; // [15] Release Candidate + } hwvers_bit; }; - __IO uint16_t hwvers; // 0x6c: HWVERS __R uint16_t rsv_0x6e_0x77[5]; // 0x6E-0x77: Reserved //------------- Additional Configuration -------------// - __IO uint8_t epinfo; // 0x78: EPINFO - __IO uint8_t raminfo; // 0x79: RAMINFO - __IO uint8_t softreset; // 0x7A: SOFTRESET (Analog), Link info + union { + __IO uint8_t epinfo; // 0x78: EPINFO + struct { + __IO uint8_t tx_ep_num : 4; // [3:0] TX Endpoints + __IO uint8_t rx_ep_num : 4; // [7:4] RX Endpoints + } epinfo_bit; + }; + union { + __IO uint8_t raminfo; // 0x79: RAMINFO + struct { + __IO uint8_t ram_bits : 4; // [3:0] RAM Address Bus Width + __IO uint8_t dma_channel : 4; // [7:4] DMA Channels + }raminfo_bit; + }; + union { + __IO uint8_t link_info; // 0x7A: LINK_INFO + __IO uint8_t adi_softreset; // 0x7A: AnalogDevice SOFTRESET + }; __IO uint8_t vplen; // 0x7B: VPLEN __IO uint8_t hs_eof1; // 0x7C: HS_EOF1 __IO uint8_t fs_eof1; // 0x7D: FS_EOF1 __IO uint8_t ls_eof1; // 0x7E: LS_EOF1 __IO uint8_t soft_rst; // 0x7F: SOFT_RST - //------------- Extended -------------// + //------------- Target Endpoints (multipoint option) -------------// __IO uint16_t ctuch; // 0x80: CTUCH __IO uint16_t cthsrtn; // 0x82: CTHSRTN __R uint32_t rsv_0x84_0xff[31]; // 0x84-0xFF: Reserved - //------------- Absolute CSR (used index to remap to Indexed above) -------------// + //------------- Non-Indexed Endpoint CSRs -------------// // TI tm4c can access this directly, but should use indexed_csr for portability musb_ep_csr_t ep_csr[16]; // 0x100-0x1FF: EP0-15 CSR } musb_regs_t; @@ -185,267 +274,151 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ return &musb_regs->indexed_csr; } -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FADDR register. -// -//***************************************************************************** -#define USB_FADDR_M 0x0000007F // Function Address -#define USB_FADDR_S 0 +//--------------------------------------------------------------------+ +// Register Bit Field +//--------------------------------------------------------------------+ -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_POWER register. -// -//***************************************************************************** -#define USB_POWER_ISOUP 0x00000080 // Isochronous Update -#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect -#define USB_POWER_HSENAB 0x00000020 // High Speed Enable -#define USB_POWER_HSMODE 0x00000010 // High Speed Enable -#define USB_POWER_RESET 0x00000008 // RESET Signaling -#define USB_POWER_RESUME 0x00000004 // RESUME Signaling -#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode -#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY +// 0x01: Power +#define USB_POWER_ISOUP 0x0080 // Isochronous Update +#define USB_POWER_SOFTCONN 0x0040 // Soft Connect/Disconnect +#define USB_POWER_HSENAB 0x0020 // High Speed Enable +#define USB_POWER_HSMODE 0x0010 // High Speed Enable +#define USB_POWER_RESET 0x0008 // RESET Signaling +#define USB_POWER_RESUME 0x0004 // RESUME Signaling +#define USB_POWER_SUSPEND 0x0002 // SUSPEND Mode +#define USB_POWER_PWRDNPHY 0x0001 // Power Down PHY -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXIS register. -// -//***************************************************************************** -#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt -#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt -#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt -#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt -#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt -#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt -#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt -#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt +// Interrupt TX/RX Status and Enable: each bit is for an endpoint -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXIS register. -// -//***************************************************************************** -#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt -#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt -#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt -#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt -#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt -#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt -#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt +// 0x6c: HWVERS +#define MUSB_HWVERS_RC_SHIFT 15 +#define MUSB_HWVERS_RC_MASK 0x8000 +#define MUSB_HWVERS_MAJOR_SHIFT 10 +#define MUSB_HWVERS_MAJOR_MASK 0x7C00 +#define MUSB_HWVERS_MINOR_SHIFT 0 +#define MUSB_HWVERS_MINOR_MASK 0x03FF -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXIE register. -// -//***************************************************************************** -#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable -#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable -#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable -#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable -#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable -#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable -#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable -#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt - // Enable +// 0x12, 0x16: TX/RX CSRL +#define MUSB_CSRL_PACKET_READY(_rx) (1u << 0) +#define MUSB_CSRL_FLUSH_FIFO(_rx) (1u << ((_rx) ? 4 : 3)) +#define MUSB_CSRL_SEND_STALL(_rx) (1u << ((_rx) ? 5 : 4)) +#define MUSB_CSRL_SENT_STALL(_rx) (1u << ((_rx) ? 6 : 5)) +#define MUSB_CSRL_CLEAR_DATA_TOGGLE(_rx) (1u << ((_rx) ? 7 : 6)) + +// 0x13, 0x17: TX/RX CSRH +#define MUSB_CSRH_DISABLE_DOUBLE_PACKET(_rx) (1u << 1) -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXIE register. -// -//***************************************************************************** -#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable -#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable -#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable -#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable -#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable -#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable -#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable //***************************************************************************** // // The following are defines for the bit fields in the USB_O_IS register. // //***************************************************************************** -#define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only) -#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only) -#define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only) -#define USB_IS_CONN 0x00000010 // Session Connect -#define USB_IS_SOF 0x00000008 // Start of Frame -#define USB_IS_BABBLE 0x00000004 // Babble Detected -#define USB_IS_RESET 0x00000004 // RESET Signaling Detected -#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected -#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected +#define USB_IS_VBUSERR 0x0080 // VBUS Error (OTG only) +#define USB_IS_SESREQ 0x0040 // SESSION REQUEST (OTG only) +#define USB_IS_DISCON 0x0020 // Session Disconnect (OTG only) +#define USB_IS_CONN 0x0010 // Session Connect +#define USB_IS_SOF 0x0008 // Start of Frame +#define USB_IS_BABBLE 0x0004 // Babble Detected +#define USB_IS_RESET 0x0004 // RESET Signaling Detected +#define USB_IS_RESUME 0x0002 // RESUME Signaling Detected +#define USB_IS_SUSPEND 0x0001 // SUSPEND Signaling Detected //***************************************************************************** // // The following are defines for the bit fields in the USB_O_IE register. // //***************************************************************************** -#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG - // only) -#define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG - // only) -#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt -#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt -#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt -#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt -#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt -#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt -#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt +#define USB_IE_VBUSERR 0x0080 // Enable VBUS Error Interrupt (OTG only) +#define USB_IE_SESREQ 0x0040 // Enable Session Request (OTG only) +#define USB_IE_DISCON 0x0020 // Enable Disconnect Interrupt +#define USB_IE_CONN 0x0010 // Enable Connect Interrupt +#define USB_IE_SOF 0x0008 // Enable Start-of-Frame Interrupt +#define USB_IE_BABBLE 0x0004 // Enable Babble Interrupt +#define USB_IE_RESET 0x0004 // Enable RESET Interrupt +#define USB_IE_RESUME 0x0002 // Enable RESUME Interrupt +#define USB_IE_SUSPND 0x0001 // Enable SUSPEND Interrupt //***************************************************************************** // // The following are defines for the bit fields in the USB_O_FRAME register. // //***************************************************************************** -#define USB_FRAME_M 0x000007FF // Frame Number +#define USB_FRAME_M 0x07FF // Frame Number #define USB_FRAME_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPIDX register. -// -//***************************************************************************** -#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index -#define USB_EPIDX_EPIDX_S 0 - //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TEST register. // //***************************************************************************** -#define USB_TEST_FORCEH 0x00000080 // Force Host Mode -#define USB_TEST_FIFOACC 0x00000040 // FIFO Access -#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode -#define USB_TEST_FORCEHS 0x00000010 // Force High-Speed Mode -#define USB_TEST_TESTPKT 0x00000008 // Test Packet Mode Enable -#define USB_TEST_TESTK 0x00000004 // Test_K Mode Enable -#define USB_TEST_TESTJ 0x00000002 // Test_J Mode Enable -#define USB_TEST_TESTSE0NAK 0x00000001 // Test_SE0_NAK Test Mode Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO0 register. -// -//***************************************************************************** -#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO0_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO1 register. -// -//***************************************************************************** -#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO1_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO2 register. -// -//***************************************************************************** -#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO2_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO3 register. -// -//***************************************************************************** -#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO3_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO4 register. -// -//***************************************************************************** -#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO4_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO5 register. -// -//***************************************************************************** -#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO5_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO6 register. -// -//***************************************************************************** -#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO6_EPDATA_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_FIFO7 register. -// -//***************************************************************************** -#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data -#define USB_FIFO7_EPDATA_S 0 +#define USB_TEST_FORCEH 0x0080 // Force Host Mode +#define USB_TEST_FIFOACC 0x0040 // FIFO Access +#define USB_TEST_FORCEFS 0x0020 // Force Full-Speed Mode +#define USB_TEST_FORCEHS 0x0010 // Force High-Speed Mode +#define USB_TEST_TESTPKT 0x0008 // Test Packet Mode Enable +#define USB_TEST_TESTK 0x0004 // Test_K Mode Enable +#define USB_TEST_TESTJ 0x0002 // Test_J Mode Enable +#define USB_TEST_TESTSE0NAK 0x0001 // Test_SE0_NAK Test Mode Enable //***************************************************************************** // // The following are defines for the bit fields in the USB_O_DEVCTL register. // //***************************************************************************** -#define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only) -#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected -#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected -#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only) -#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd -#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid -#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid -#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid -#define USB_DEVCTL_HOST 0x00000004 // Host Mode -#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only) -#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only) +#define USB_DEVCTL_DEV 0x0080 // Device Mode (OTG only) +#define USB_DEVCTL_FSDEV 0x0040 // Full-Speed Device Detected +#define USB_DEVCTL_LSDEV 0x0020 // Low-Speed Device Detected +#define USB_DEVCTL_VBUS_M 0x0018 // VBUS Level (OTG only) +#define USB_DEVCTL_VBUS_NONE 0x0000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x0008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x0010 // Above AValid, below VBUSValid +#define USB_DEVCTL_VBUS_VALID 0x0018 // Above VBUSValid +#define USB_DEVCTL_HOST 0x0004 // Host Mode +#define USB_DEVCTL_HOSTREQ 0x0002 // Host Request (OTG only) +#define USB_DEVCTL_SESSION 0x0001 // Session Start/End (OTG only) //***************************************************************************** // // The following are defines for the bit fields in the USB_O_CCONF register. // //***************************************************************************** -#define USB_CCONF_TXEDMA 0x00000002 // TX Early DMA Enable -#define USB_CCONF_RXEDMA 0x00000001 // TX Early DMA Enable +#define USB_CCONF_TXEDMA 0x0002 // TX Early DMA Enable +#define USB_CCONF_RXEDMA 0x0001 // TX Early DMA Enable //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXFIFOSZ register. // //***************************************************************************** -#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support -#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size -#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 -#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 -#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 -#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 -#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 -#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 -#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 -#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 -#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 +#define USB_TXFIFOSZ_DPB 0x0010 // Double Packet Buffer Support +#define USB_TXFIFOSZ_SIZE_M 0x000F // Max Packet Size +#define USB_TXFIFOSZ_SIZE_8 0x0000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x0001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x0002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x0003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x0004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x0005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x0006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x0007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x0008 // 2048 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXFIFOSZ register. // //***************************************************************************** -#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support -#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size -#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 -#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 -#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 -#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 -#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 -#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 -#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 -#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 -#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 +#define USB_RXFIFOSZ_DPB 0x0010 // Double Packet Buffer Support +#define USB_RXFIFOSZ_SIZE_M 0x000F // Max Packet Size +#define USB_RXFIFOSZ_SIZE_8 0x0000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x0001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x0002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x0003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x0004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x0005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x0006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x0007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x0008 // 2048 //***************************************************************************** // @@ -453,7 +426,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_TXFIFOADD_ADDR_M 0x01FF // Transmit/Receive Start Address #define USB_TXFIFOADD_ADDR_S 0 //***************************************************************************** @@ -462,7 +435,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_RXFIFOADD_ADDR_M 0x01FF // Transmit/Receive Start Address #define USB_RXFIFOADD_ADDR_S 0 //***************************************************************************** @@ -471,10 +444,8 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_ULPIVBUSCTL_USEEXTVBUSIND \ - 0x00000002 // Use External VBUS Indicator -#define USB_ULPIVBUSCTL_USEEXTVBUS \ - 0x00000001 // Use External VBUS +#define USB_ULPIVBUSCTL_USEEXTVBUSIND 0x0002 // Use External VBUS Indicator +#define USB_ULPIVBUSCTL_USEEXTVBUS 0x0001 // Use External VBUS //***************************************************************************** // @@ -482,18 +453,15 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_ULPIREGDATA_REGDATA_M \ - 0x000000FF // Register Data -#define USB_ULPIREGDATA_REGDATA_S \ - 0 - +#define USB_ULPIREGDATA_REGDATA_M 0x00FF // Register Data +#define USB_ULPIREGDATA_REGDATA_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_ULPIREGADDR // register. // //***************************************************************************** -#define USB_ULPIREGADDR_ADDR_M 0x000000FF // Register Address +#define USB_ULPIREGADDR_ADDR_M 0x00FF // Register Address #define USB_ULPIREGADDR_ADDR_S 0 //***************************************************************************** @@ -502,17 +470,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_ULPIREGCTL_RDWR 0x00000004 // Read/Write Control -#define USB_ULPIREGCTL_REGCMPLT 0x00000002 // Register Access Complete -#define USB_ULPIREGCTL_REGACC 0x00000001 // Initiate Register Access +#define USB_ULPIREGCTL_RDWR 0x0004 // Read/Write Control +#define USB_ULPIREGCTL_REGCMPLT 0x0002 // Register Access Complete +#define USB_ULPIREGCTL_REGACC 0x0001 // Initiate Register Access //***************************************************************************** // // The following are defines for the bit fields in the USB_O_EPINFO register. // //***************************************************************************** -#define USB_EPINFO_RXEP_M 0x000000F0 // RX Endpoints -#define USB_EPINFO_TXEP_M 0x0000000F // TX Endpoints +#define USB_EPINFO_RXEP_M 0x00F0 // RX Endpoints +#define USB_EPINFO_TXEP_M 0x000F // TX Endpoints #define USB_EPINFO_RXEP_S 4 #define USB_EPINFO_TXEP_S 0 @@ -521,8 +489,8 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RAMINFO register. // //***************************************************************************** -#define USB_RAMINFO_DMACHAN_M 0x000000F0 // DMA Channels -#define USB_RAMINFO_RAMBITS_M 0x0000000F // RAM Address Bus Width +#define USB_RAMINFO_DMACHAN_M 0x00F0 // DMA Channels +#define USB_RAMINFO_RAMBITS_M 0x000F // RAM Address Bus Width #define USB_RAMINFO_DMACHAN_S 4 #define USB_RAMINFO_RAMBITS_S 0 @@ -531,8 +499,8 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_CONTIM register. // //***************************************************************************** -#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait -#define USB_CONTIM_WTID_M 0x0000000F // Wait ID +#define USB_CONTIM_WTCON_M 0x00F0 // Connect Wait +#define USB_CONTIM_WTID_M 0x000F // Wait ID #define USB_CONTIM_WTCON_S 4 #define USB_CONTIM_WTID_S 0 @@ -541,7 +509,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_VPLEN register. // //***************************************************************************** -#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length +#define USB_VPLEN_VPLEN_M 0x00FF // VBUS Pulse Length #define USB_VPLEN_VPLEN_S 0 //***************************************************************************** @@ -549,7 +517,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_HSEOF register. // //***************************************************************************** -#define USB_HSEOF_HSEOFG_M 0x000000FF // HIgh-Speed End-of-Frame Gap +#define USB_HSEOF_HSEOFG_M 0x00FF // HIgh-Speed End-of-Frame Gap #define USB_HSEOF_HSEOFG_S 0 //***************************************************************************** @@ -557,7 +525,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_FSEOF register. // //***************************************************************************** -#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap +#define USB_FSEOF_FSEOFG_M 0x00FF // Full-Speed End-of-Frame Gap #define USB_FSEOF_FSEOFG_S 0 //***************************************************************************** @@ -565,449 +533,44 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_LSEOF register. // //***************************************************************************** -#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap +#define USB_LSEOF_LSEOFG_M 0x00FF // Low-Speed End-of-Frame Gap #define USB_LSEOF_LSEOFG_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR0_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR0 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR0_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT0 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT0_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR1 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT1 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT1_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR1 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR1_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT1 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT1_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR2 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT2 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT2_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR2 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR2_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT2 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT2_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR3 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT3 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT3_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR3 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR3_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT3 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT3_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR4 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT4 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT4_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR4 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR4_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT4 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT4_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR5 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT5 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT5_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR5 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR5_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT5 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT5_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR6 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT6 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT6_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR6 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR6_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT6 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT6_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 -// register. -// -//***************************************************************************** -#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address -#define USB_TXFUNCADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBADDR7 -// register. -// -//***************************************************************************** -#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address -#define USB_TXHUBADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXHUBPORT7 -// register. -// -//***************************************************************************** -#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port -#define USB_TXHUBPORT7_PORT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 -// register. -// -//***************************************************************************** -#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address -#define USB_RXFUNCADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBADDR7 -// register. -// -//***************************************************************************** -#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address -#define USB_RXHUBADDR7_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXHUBPORT7 -// register. -// -//***************************************************************************** -#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port -#define USB_RXHUBPORT7_PORT_S 0 - //***************************************************************************** // // The following are defines for the bit fields in the USB_O_CSRL0 register. // //***************************************************************************** -#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout -#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear -#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet -#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear -#define USB_CSRL0_REQPKT 0x00000020 // Request Packet -#define USB_CSRL0_STALL 0x00000020 // Send Stall -#define USB_CSRL0_SETEND 0x00000010 // Setup End -#define USB_CSRL0_ERROR 0x00000010 // Error -#define USB_CSRL0_DATAEND 0x00000008 // Data End -#define USB_CSRL0_SETUP 0x00000008 // Setup Packet -#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled -#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready -#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready +#define USB_CSRL0_NAKTO 0x0080 // NAK Timeout +#define USB_CSRL0_SETENDC 0x0080 // Setup End Clear +#define USB_CSRL0_STATUS 0x0040 // STATUS Packet +#define USB_CSRL0_RXRDYC 0x0040 // RXRDY Clear +#define USB_CSRL0_REQPKT 0x0020 // Request Packet +#define USB_CSRL0_STALL 0x0020 // Send Stall +#define USB_CSRL0_SETEND 0x0010 // Setup End +#define USB_CSRL0_ERROR 0x0010 // Error +#define USB_CSRL0_DATAEND 0x0008 // Data End +#define USB_CSRL0_SETUP 0x0008 // Setup Packet +#define USB_CSRL0_STALLED 0x0004 // Endpoint Stalled +#define USB_CSRL0_TXRDY 0x0002 // Transmit Packet Ready +#define USB_CSRL0_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_CSRH0 register. // //***************************************************************************** -#define USB_CSRH0_DISPING 0x00000008 // PING Disable -#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_CSRH0_DT 0x00000002 // Data Toggle -#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO +#define USB_CSRH0_DISPING 0x0008 // PING Disable +#define USB_CSRH0_DTWE 0x0004 // Data Toggle Write Enable +#define USB_CSRH0_DT 0x0002 // Data Toggle +#define USB_CSRH0_FLUSH 0x0001 // Flush FIFO //***************************************************************************** // // The following are defines for the bit fields in the USB_O_COUNT0 register. // //***************************************************************************** -#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count +#define USB_COUNT0_COUNT_M 0x007F // FIFO Count #define USB_COUNT0_COUNT_S 0 //***************************************************************************** @@ -1015,17 +578,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TYPE0 register. // //***************************************************************************** -#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed -#define USB_TYPE0_SPEED_HIGH 0x00000040 // High -#define USB_TYPE0_SPEED_FULL 0x00000080 // Full -#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low +#define USB_TYPE0_SPEED_M 0x00C0 // Operating Speed +#define USB_TYPE0_SPEED_HIGH 0x0040 // High +#define USB_TYPE0_SPEED_FULL 0x0080 // Full +#define USB_TYPE0_SPEED_LOW 0x00C0 // Low //***************************************************************************** // // The following are defines for the bit fields in the USB_O_NAKLMT register. // //***************************************************************************** -#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit +#define USB_NAKLMT_NAKLMT_M 0x001F // EP0 NAK Limit #define USB_NAKLMT_NAKLMT_S 0 //***************************************************************************** @@ -1033,7 +596,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXMAXP1 register. // //***************************************************************************** -#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP1_MAXLOAD_M 0x07FF // Maximum Payload #define USB_TXMAXP1_MAXLOAD_S 0 //***************************************************************************** @@ -1041,37 +604,37 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXCSRL1 register. // //***************************************************************************** -#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL1_STALL 0x00000010 // Send STALL -#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL1_ERROR 0x00000004 // Error -#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready +#define USB_TXCSRL1_NAKTO 0x0080 // NAK Timeout +#define USB_TXCSRL1_CLRDT 0x0040 // Clear Data Toggle +#define USB_TXCSRL1_STALLED 0x0020 // Endpoint Stalled +#define USB_TXCSRL1_STALL 0x0010 // Send STALL +#define USB_TXCSRL1_SETUP 0x0010 // Setup Packet +#define USB_TXCSRL1_FLUSH 0x0008 // Flush FIFO +#define USB_TXCSRL1_ERROR 0x0004 // Error +#define USB_TXCSRL1_UNDRN 0x0004 // Underrun +#define USB_TXCSRL1_FIFONE 0x0002 // FIFO Not Empty +#define USB_TXCSRL1_TXRDY 0x0001 // Transmit Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXCSRH1 register. // //***************************************************************************** -#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH1_MODE 0x00000020 // Mode -#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH1_DT 0x00000001 // Data Toggle +#define USB_TXCSRH1_AUTOSET 0x0080 // Auto Set +#define USB_TXCSRH1_ISO 0x0040 // Isochronous Transfers +#define USB_TXCSRH1_MODE 0x0020 // Mode +#define USB_TXCSRH1_DMAEN 0x0010 // DMA Request Enable +#define USB_TXCSRH1_FDT 0x0008 // Force Data Toggle +#define USB_TXCSRH1_DMAMOD 0x0004 // DMA Request Mode +#define USB_TXCSRH1_DTWE 0x0002 // Data Toggle Write Enable +#define USB_TXCSRH1_DT 0x0001 // Data Toggle //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXMAXP1 register. // //***************************************************************************** -#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP1_MAXLOAD_M 0x07FF // Maximum Payload #define USB_RXMAXP1_MAXLOAD_S 0 //***************************************************************************** @@ -1079,33 +642,33 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCSRL1 register. // //***************************************************************************** -#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL1_STALL 0x00000020 // Send STALL -#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL1_OVER 0x00000004 // Overrun -#define USB_RXCSRL1_ERROR 0x00000004 // Error -#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready +#define USB_RXCSRL1_CLRDT 0x0080 // Clear Data Toggle +#define USB_RXCSRL1_STALLED 0x0040 // Endpoint Stalled +#define USB_RXCSRL1_STALL 0x0020 // Send STALL +#define USB_RXCSRL1_REQPKT 0x0020 // Request Packet +#define USB_RXCSRL1_FLUSH 0x0010 // Flush FIFO +#define USB_RXCSRL1_DATAERR 0x0008 // Data Error +#define USB_RXCSRL1_NAKTO 0x0008 // NAK Timeout +#define USB_RXCSRL1_OVER 0x0004 // Overrun +#define USB_RXCSRL1_ERROR 0x0004 // Error +#define USB_RXCSRL1_FULL 0x0002 // FIFO Full +#define USB_RXCSRL1_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXCSRH1 register. // //***************************************************************************** -#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH1_DT 0x00000002 // Data Toggle -#define USB_RXCSRH1_INCOMPRX 0x00000001 // Incomplete RX Transmission +#define USB_RXCSRH1_AUTOCL 0x0080 // Auto Clear +#define USB_RXCSRH1_AUTORQ 0x0040 // Auto Request +#define USB_RXCSRH1_ISO 0x0040 // Isochronous Transfers +#define USB_RXCSRH1_DMAEN 0x0020 // DMA Request Enable +#define USB_RXCSRH1_DISNYET 0x0010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x0010 // PID Error +#define USB_RXCSRH1_DMAMOD 0x0008 // DMA Request Mode +#define USB_RXCSRH1_DTWE 0x0004 // Data Toggle Write Enable +#define USB_RXCSRH1_DT 0x0002 // Data Toggle +#define USB_RXCSRH1_INCOMPRX 0x0001 // Incomplete RX Transmission // Status //***************************************************************************** @@ -1113,7 +676,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCOUNT1 register. // //***************************************************************************** -#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT1_COUNT_M 0x1FFF // Receive Packet Count #define USB_RXCOUNT1_COUNT_S 0 //***************************************************************************** @@ -1121,17 +684,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXTYPE1 register. // //***************************************************************************** -#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE1_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE1_SPEED_M 0x00C0 // Operating Speed +#define USB_TXTYPE1_SPEED_DFLT 0x0000 // Default +#define USB_TXTYPE1_SPEED_HIGH 0x0040 // High +#define USB_TXTYPE1_SPEED_FULL 0x0080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x00C0 // Low +#define USB_TXTYPE1_PROTO_M 0x0030 // Protocol +#define USB_TXTYPE1_PROTO_CTRL 0x0000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x0010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x0020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x0030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x000F // Target Endpoint Number #define USB_TXTYPE1_TEP_S 0 //***************************************************************************** @@ -1140,31 +703,27 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXINTERVAL1_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL1_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL1_TXPOLL_S \ - 0 -#define USB_TXINTERVAL1_NAKLMT_S \ - 0 +#define USB_TXINTERVAL1_NAKLMT_M 0x00FF // NAK Limit +#define USB_TXINTERVAL1_TXPOLL_M 0x00FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S 0 +#define USB_TXINTERVAL1_NAKLMT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXTYPE1 register. // //***************************************************************************** -#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE1_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE1_SPEED_M 0x00C0 // Operating Speed +#define USB_RXTYPE1_SPEED_DFLT 0x0000 // Default +#define USB_RXTYPE1_SPEED_HIGH 0x0040 // High +#define USB_RXTYPE1_SPEED_FULL 0x0080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x00C0 // Low +#define USB_RXTYPE1_PROTO_M 0x0030 // Protocol +#define USB_RXTYPE1_PROTO_CTRL 0x0000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x0010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x0020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x0030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x000F // Target Endpoint Number #define USB_RXTYPE1_TEP_S 0 //***************************************************************************** @@ -1173,21 +732,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXINTERVAL1_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL1_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL1_TXPOLL_S \ - 0 -#define USB_RXINTERVAL1_NAKLMT_S \ - 0 +#define USB_RXINTERVAL1_TXPOLL_M 0x00FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M 0x00FF // NAK Limit +#define USB_RXINTERVAL1_TXPOLL_S 0 +#define USB_RXINTERVAL1_NAKLMT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXMAXP2 register. // //***************************************************************************** -#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP2_MAXLOAD_M 0x07FF // Maximum Payload #define USB_TXMAXP2_MAXLOAD_S 0 //***************************************************************************** @@ -1195,37 +750,37 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXCSRL2 register. // //***************************************************************************** -#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL2_STALL 0x00000010 // Send STALL -#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL2_ERROR 0x00000004 // Error -#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready +#define USB_TXCSRL2_NAKTO 0x0080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x0040 // Clear Data Toggle +#define USB_TXCSRL2_STALLED 0x0020 // Endpoint Stalled +#define USB_TXCSRL2_SETUP 0x0010 // Setup Packet +#define USB_TXCSRL2_STALL 0x0010 // Send STALL +#define USB_TXCSRL2_FLUSH 0x0008 // Flush FIFO +#define USB_TXCSRL2_ERROR 0x0004 // Error +#define USB_TXCSRL2_UNDRN 0x0004 // Underrun +#define USB_TXCSRL2_FIFONE 0x0002 // FIFO Not Empty +#define USB_TXCSRL2_TXRDY 0x0001 // Transmit Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXCSRH2 register. // //***************************************************************************** -#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH2_MODE 0x00000020 // Mode -#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH2_DT 0x00000001 // Data Toggle +#define USB_TXCSRH2_AUTOSET 0x0080 // Auto Set +#define USB_TXCSRH2_ISO 0x0040 // Isochronous Transfers +#define USB_TXCSRH2_MODE 0x0020 // Mode +#define USB_TXCSRH2_DMAEN 0x0010 // DMA Request Enable +#define USB_TXCSRH2_FDT 0x0008 // Force Data Toggle +#define USB_TXCSRH2_DMAMOD 0x0004 // DMA Request Mode +#define USB_TXCSRH2_DTWE 0x0002 // Data Toggle Write Enable +#define USB_TXCSRH2_DT 0x0001 // Data Toggle //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXMAXP2 register. // //***************************************************************************** -#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP2_MAXLOAD_M 0x07FF // Maximum Payload #define USB_RXMAXP2_MAXLOAD_S 0 //***************************************************************************** @@ -1233,33 +788,33 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCSRL2 register. // //***************************************************************************** -#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL2_STALL 0x00000020 // Send STALL -#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL2_ERROR 0x00000004 // Error -#define USB_RXCSRL2_OVER 0x00000004 // Overrun -#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready +#define USB_RXCSRL2_CLRDT 0x0080 // Clear Data Toggle +#define USB_RXCSRL2_STALLED 0x0040 // Endpoint Stalled +#define USB_RXCSRL2_REQPKT 0x0020 // Request Packet +#define USB_RXCSRL2_STALL 0x0020 // Send STALL +#define USB_RXCSRL2_FLUSH 0x0010 // Flush FIFO +#define USB_RXCSRL2_DATAERR 0x0008 // Data Error +#define USB_RXCSRL2_NAKTO 0x0008 // NAK Timeout +#define USB_RXCSRL2_ERROR 0x0004 // Error +#define USB_RXCSRL2_OVER 0x0004 // Overrun +#define USB_RXCSRL2_FULL 0x0002 // FIFO Full +#define USB_RXCSRL2_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXCSRH2 register. // //***************************************************************************** -#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH2_DT 0x00000002 // Data Toggle -#define USB_RXCSRH2_INCOMPRX 0x00000001 // Incomplete RX Transmission +#define USB_RXCSRH2_AUTOCL 0x0080 // Auto Clear +#define USB_RXCSRH2_AUTORQ 0x0040 // Auto Request +#define USB_RXCSRH2_ISO 0x0040 // Isochronous Transfers +#define USB_RXCSRH2_DMAEN 0x0020 // DMA Request Enable +#define USB_RXCSRH2_DISNYET 0x0010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x0010 // PID Error +#define USB_RXCSRH2_DMAMOD 0x0008 // DMA Request Mode +#define USB_RXCSRH2_DTWE 0x0004 // Data Toggle Write Enable +#define USB_RXCSRH2_DT 0x0002 // Data Toggle +#define USB_RXCSRH2_INCOMPRX 0x0001 // Incomplete RX Transmission // Status //***************************************************************************** @@ -1267,7 +822,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCOUNT2 register. // //***************************************************************************** -#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT2_COUNT_M 0x1FFF // Receive Packet Count #define USB_RXCOUNT2_COUNT_S 0 //***************************************************************************** @@ -1275,17 +830,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXTYPE2 register. // //***************************************************************************** -#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE2_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE2_SPEED_M 0x00C0 // Operating Speed +#define USB_TXTYPE2_SPEED_DFLT 0x0000 // Default +#define USB_TXTYPE2_SPEED_HIGH 0x0040 // High +#define USB_TXTYPE2_SPEED_FULL 0x0080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x00C0 // Low +#define USB_TXTYPE2_PROTO_M 0x0030 // Protocol +#define USB_TXTYPE2_PROTO_CTRL 0x0000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x0010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x0020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x0030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x000F // Target Endpoint Number #define USB_TXTYPE2_TEP_S 0 //***************************************************************************** @@ -1294,31 +849,27 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXINTERVAL2_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL2_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL2_NAKLMT_S \ - 0 -#define USB_TXINTERVAL2_TXPOLL_S \ - 0 +#define USB_TXINTERVAL2_TXPOLL_M 0x00FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M 0x00FF // NAK Limit +#define USB_TXINTERVAL2_NAKLMT_S 0 +#define USB_TXINTERVAL2_TXPOLL_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXTYPE2 register. // //***************************************************************************** -#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE2_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE2_SPEED_M 0x00C0 // Operating Speed +#define USB_RXTYPE2_SPEED_DFLT 0x0000 // Default +#define USB_RXTYPE2_SPEED_HIGH 0x0040 // High +#define USB_RXTYPE2_SPEED_FULL 0x0080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x00C0 // Low +#define USB_RXTYPE2_PROTO_M 0x0030 // Protocol +#define USB_RXTYPE2_PROTO_CTRL 0x0000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x0010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x0020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x0030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x000F // Target Endpoint Number #define USB_RXTYPE2_TEP_S 0 //***************************************************************************** @@ -1327,21 +878,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXINTERVAL2_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL2_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL2_TXPOLL_S \ - 0 -#define USB_RXINTERVAL2_NAKLMT_S \ - 0 +#define USB_RXINTERVAL2_TXPOLL_M 0x00FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M 0x00FF // NAK Limit +#define USB_RXINTERVAL2_TXPOLL_S 0 +#define USB_RXINTERVAL2_NAKLMT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXMAXP3 register. // //***************************************************************************** -#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP3_MAXLOAD_M 0x07FF // Maximum Payload #define USB_TXMAXP3_MAXLOAD_S 0 //***************************************************************************** @@ -1349,37 +896,37 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXCSRL3 register. // //***************************************************************************** -#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL3_STALL 0x00000010 // Send STALL -#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL3_ERROR 0x00000004 // Error -#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready +#define USB_TXCSRL3_NAKTO 0x0080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x0040 // Clear Data Toggle +#define USB_TXCSRL3_STALLED 0x0020 // Endpoint Stalled +#define USB_TXCSRL3_SETUP 0x0010 // Setup Packet +#define USB_TXCSRL3_STALL 0x0010 // Send STALL +#define USB_TXCSRL3_FLUSH 0x0008 // Flush FIFO +#define USB_TXCSRL3_ERROR 0x0004 // Error +#define USB_TXCSRL3_UNDRN 0x0004 // Underrun +#define USB_TXCSRL3_FIFONE 0x0002 // FIFO Not Empty +#define USB_TXCSRL3_TXRDY 0x0001 // Transmit Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXCSRH3 register. // //***************************************************************************** -#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH3_MODE 0x00000020 // Mode -#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH3_DT 0x00000001 // Data Toggle +#define USB_TXCSRH3_AUTOSET 0x0080 // Auto Set +#define USB_TXCSRH3_ISO 0x0040 // Isochronous Transfers +#define USB_TXCSRH3_MODE 0x0020 // Mode +#define USB_TXCSRH3_DMAEN 0x0010 // DMA Request Enable +#define USB_TXCSRH3_FDT 0x0008 // Force Data Toggle +#define USB_TXCSRH3_DMAMOD 0x0004 // DMA Request Mode +#define USB_TXCSRH3_DTWE 0x0002 // Data Toggle Write Enable +#define USB_TXCSRH3_DT 0x0001 // Data Toggle //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXMAXP3 register. // //***************************************************************************** -#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP3_MAXLOAD_M 0x07FF // Maximum Payload #define USB_RXMAXP3_MAXLOAD_S 0 //***************************************************************************** @@ -1387,33 +934,33 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCSRL3 register. // //***************************************************************************** -#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL3_STALL 0x00000020 // Send STALL -#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL3_ERROR 0x00000004 // Error -#define USB_RXCSRL3_OVER 0x00000004 // Overrun -#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready +#define USB_RXCSRL3_CLRDT 0x0080 // Clear Data Toggle +#define USB_RXCSRL3_STALLED 0x0040 // Endpoint Stalled +#define USB_RXCSRL3_STALL 0x0020 // Send STALL +#define USB_RXCSRL3_REQPKT 0x0020 // Request Packet +#define USB_RXCSRL3_FLUSH 0x0010 // Flush FIFO +#define USB_RXCSRL3_DATAERR 0x0008 // Data Error +#define USB_RXCSRL3_NAKTO 0x0008 // NAK Timeout +#define USB_RXCSRL3_ERROR 0x0004 // Error +#define USB_RXCSRL3_OVER 0x0004 // Overrun +#define USB_RXCSRL3_FULL 0x0002 // FIFO Full +#define USB_RXCSRL3_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXCSRH3 register. // //***************************************************************************** -#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH3_DT 0x00000002 // Data Toggle -#define USB_RXCSRH3_INCOMPRX 0x00000001 // Incomplete RX Transmission +#define USB_RXCSRH3_AUTOCL 0x0080 // Auto Clear +#define USB_RXCSRH3_AUTORQ 0x0040 // Auto Request +#define USB_RXCSRH3_ISO 0x0040 // Isochronous Transfers +#define USB_RXCSRH3_DMAEN 0x0020 // DMA Request Enable +#define USB_RXCSRH3_DISNYET 0x0010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x0010 // PID Error +#define USB_RXCSRH3_DMAMOD 0x0008 // DMA Request Mode +#define USB_RXCSRH3_DTWE 0x0004 // Data Toggle Write Enable +#define USB_RXCSRH3_DT 0x0002 // Data Toggle +#define USB_RXCSRH3_INCOMPRX 0x0001 // Incomplete RX Transmission // Status //***************************************************************************** @@ -1421,7 +968,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCOUNT3 register. // //***************************************************************************** -#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT3_COUNT_M 0x1FFF // Receive Packet Count #define USB_RXCOUNT3_COUNT_S 0 //***************************************************************************** @@ -1429,17 +976,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXTYPE3 register. // //***************************************************************************** -#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE3_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE3_SPEED_M 0x00C0 // Operating Speed +#define USB_TXTYPE3_SPEED_DFLT 0x0000 // Default +#define USB_TXTYPE3_SPEED_HIGH 0x0040 // High +#define USB_TXTYPE3_SPEED_FULL 0x0080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x00C0 // Low +#define USB_TXTYPE3_PROTO_M 0x0030 // Protocol +#define USB_TXTYPE3_PROTO_CTRL 0x0000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x0010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x0020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x0030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x000F // Target Endpoint Number #define USB_TXTYPE3_TEP_S 0 //***************************************************************************** @@ -1448,31 +995,27 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXINTERVAL3_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL3_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL3_TXPOLL_S \ - 0 -#define USB_TXINTERVAL3_NAKLMT_S \ - 0 +#define USB_TXINTERVAL3_TXPOLL_M 0x00FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M 0x00FF // NAK Limit +#define USB_TXINTERVAL3_TXPOLL_S 0 +#define USB_TXINTERVAL3_NAKLMT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXTYPE3 register. // //***************************************************************************** -#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE3_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE3_SPEED_M 0x00C0 // Operating Speed +#define USB_RXTYPE3_SPEED_DFLT 0x0000 // Default +#define USB_RXTYPE3_SPEED_HIGH 0x0040 // High +#define USB_RXTYPE3_SPEED_FULL 0x0080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x00C0 // Low +#define USB_RXTYPE3_PROTO_M 0x0030 // Protocol +#define USB_RXTYPE3_PROTO_CTRL 0x0000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x0010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x0020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x0030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x000F // Target Endpoint Number #define USB_RXTYPE3_TEP_S 0 //***************************************************************************** @@ -1481,21 +1024,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXINTERVAL3_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL3_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL3_TXPOLL_S \ - 0 -#define USB_RXINTERVAL3_NAKLMT_S \ - 0 +#define USB_RXINTERVAL3_TXPOLL_M 0x00FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M 0x00FF // NAK Limit +#define USB_RXINTERVAL3_TXPOLL_S 0 +#define USB_RXINTERVAL3_NAKLMT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXMAXP4 register. // //***************************************************************************** -#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP4_MAXLOAD_M 0x07FF // Maximum Payload #define USB_TXMAXP4_MAXLOAD_S 0 //***************************************************************************** @@ -1503,37 +1042,37 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXCSRL4 register. // //***************************************************************************** -#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL4_STALL 0x00000010 // Send STALL -#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL4_ERROR 0x00000004 // Error -#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready +#define USB_TXCSRL4_NAKTO 0x0080 // NAK Timeout +#define USB_TXCSRL4_CLRDT 0x0040 // Clear Data Toggle +#define USB_TXCSRL4_STALLED 0x0020 // Endpoint Stalled +#define USB_TXCSRL4_SETUP 0x0010 // Setup Packet +#define USB_TXCSRL4_STALL 0x0010 // Send STALL +#define USB_TXCSRL4_FLUSH 0x0008 // Flush FIFO +#define USB_TXCSRL4_ERROR 0x0004 // Error +#define USB_TXCSRL4_UNDRN 0x0004 // Underrun +#define USB_TXCSRL4_FIFONE 0x0002 // FIFO Not Empty +#define USB_TXCSRL4_TXRDY 0x0001 // Transmit Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXCSRH4 register. // //***************************************************************************** -#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH4_MODE 0x00000020 // Mode -#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH4_DT 0x00000001 // Data Toggle +#define USB_TXCSRH4_AUTOSET 0x0080 // Auto Set +#define USB_TXCSRH4_ISO 0x0040 // Isochronous Transfers +#define USB_TXCSRH4_MODE 0x0020 // Mode +#define USB_TXCSRH4_DMAEN 0x0010 // DMA Request Enable +#define USB_TXCSRH4_FDT 0x0008 // Force Data Toggle +#define USB_TXCSRH4_DMAMOD 0x0004 // DMA Request Mode +#define USB_TXCSRH4_DTWE 0x0002 // Data Toggle Write Enable +#define USB_TXCSRH4_DT 0x0001 // Data Toggle //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXMAXP4 register. // //***************************************************************************** -#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP4_MAXLOAD_M 0x07FF // Maximum Payload #define USB_RXMAXP4_MAXLOAD_S 0 //***************************************************************************** @@ -1541,33 +1080,33 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCSRL4 register. // //***************************************************************************** -#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL4_STALL 0x00000020 // Send STALL -#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL4_OVER 0x00000004 // Overrun -#define USB_RXCSRL4_ERROR 0x00000004 // Error -#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready +#define USB_RXCSRL4_CLRDT 0x0080 // Clear Data Toggle +#define USB_RXCSRL4_STALLED 0x0040 // Endpoint Stalled +#define USB_RXCSRL4_STALL 0x0020 // Send STALL +#define USB_RXCSRL4_REQPKT 0x0020 // Request Packet +#define USB_RXCSRL4_FLUSH 0x0010 // Flush FIFO +#define USB_RXCSRL4_NAKTO 0x0008 // NAK Timeout +#define USB_RXCSRL4_DATAERR 0x0008 // Data Error +#define USB_RXCSRL4_OVER 0x0004 // Overrun +#define USB_RXCSRL4_ERROR 0x0004 // Error +#define USB_RXCSRL4_FULL 0x0002 // FIFO Full +#define USB_RXCSRL4_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXCSRH4 register. // //***************************************************************************** -#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH4_DT 0x00000002 // Data Toggle -#define USB_RXCSRH4_INCOMPRX 0x00000001 // Incomplete RX Transmission +#define USB_RXCSRH4_AUTOCL 0x0080 // Auto Clear +#define USB_RXCSRH4_AUTORQ 0x0040 // Auto Request +#define USB_RXCSRH4_ISO 0x0040 // Isochronous Transfers +#define USB_RXCSRH4_DMAEN 0x0020 // DMA Request Enable +#define USB_RXCSRH4_DISNYET 0x0010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x0010 // PID Error +#define USB_RXCSRH4_DMAMOD 0x0008 // DMA Request Mode +#define USB_RXCSRH4_DTWE 0x0004 // Data Toggle Write Enable +#define USB_RXCSRH4_DT 0x0002 // Data Toggle +#define USB_RXCSRH4_INCOMPRX 0x0001 // Incomplete RX Transmission // Status //***************************************************************************** @@ -1575,7 +1114,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCOUNT4 register. // //***************************************************************************** -#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT4_COUNT_M 0x1FFF // Receive Packet Count #define USB_RXCOUNT4_COUNT_S 0 //***************************************************************************** @@ -1583,17 +1122,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXTYPE4 register. // //***************************************************************************** -#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE4_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE4_SPEED_M 0x00C0 // Operating Speed +#define USB_TXTYPE4_SPEED_DFLT 0x0000 // Default +#define USB_TXTYPE4_SPEED_HIGH 0x0040 // High +#define USB_TXTYPE4_SPEED_FULL 0x0080 // Full +#define USB_TXTYPE4_SPEED_LOW 0x00C0 // Low +#define USB_TXTYPE4_PROTO_M 0x0030 // Protocol +#define USB_TXTYPE4_PROTO_CTRL 0x0000 // Control +#define USB_TXTYPE4_PROTO_ISOC 0x0010 // Isochronous +#define USB_TXTYPE4_PROTO_BULK 0x0020 // Bulk +#define USB_TXTYPE4_PROTO_INT 0x0030 // Interrupt +#define USB_TXTYPE4_TEP_M 0x000F // Target Endpoint Number #define USB_TXTYPE4_TEP_S 0 //***************************************************************************** @@ -1602,31 +1141,27 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXINTERVAL4_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL4_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL4_NAKLMT_S \ - 0 -#define USB_TXINTERVAL4_TXPOLL_S \ - 0 +#define USB_TXINTERVAL4_TXPOLL_M 0x00FF // TX Polling +#define USB_TXINTERVAL4_NAKLMT_M 0x00FF // NAK Limit +#define USB_TXINTERVAL4_NAKLMT_S 0 +#define USB_TXINTERVAL4_TXPOLL_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXTYPE4 register. // //***************************************************************************** -#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE4_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE4_SPEED_M 0x00C0 // Operating Speed +#define USB_RXTYPE4_SPEED_DFLT 0x0000 // Default +#define USB_RXTYPE4_SPEED_HIGH 0x0040 // High +#define USB_RXTYPE4_SPEED_FULL 0x0080 // Full +#define USB_RXTYPE4_SPEED_LOW 0x00C0 // Low +#define USB_RXTYPE4_PROTO_M 0x0030 // Protocol +#define USB_RXTYPE4_PROTO_CTRL 0x0000 // Control +#define USB_RXTYPE4_PROTO_ISOC 0x0010 // Isochronous +#define USB_RXTYPE4_PROTO_BULK 0x0020 // Bulk +#define USB_RXTYPE4_PROTO_INT 0x0030 // Interrupt +#define USB_RXTYPE4_TEP_M 0x000F // Target Endpoint Number #define USB_RXTYPE4_TEP_S 0 //***************************************************************************** @@ -1635,21 +1170,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXINTERVAL4_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL4_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL4_NAKLMT_S \ - 0 -#define USB_RXINTERVAL4_TXPOLL_S \ - 0 +#define USB_RXINTERVAL4_TXPOLL_M 0x00FF // RX Polling +#define USB_RXINTERVAL4_NAKLMT_M 0x00FF // NAK Limit +#define USB_RXINTERVAL4_NAKLMT_S 0 +#define USB_RXINTERVAL4_TXPOLL_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXMAXP5 register. // //***************************************************************************** -#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP5_MAXLOAD_M 0x07FF // Maximum Payload #define USB_TXMAXP5_MAXLOAD_S 0 //***************************************************************************** @@ -1657,37 +1188,37 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXCSRL5 register. // //***************************************************************************** -#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL5_STALL 0x00000010 // Send STALL -#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL5_ERROR 0x00000004 // Error -#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready +#define USB_TXCSRL5_NAKTO 0x0080 // NAK Timeout +#define USB_TXCSRL5_CLRDT 0x0040 // Clear Data Toggle +#define USB_TXCSRL5_STALLED 0x0020 // Endpoint Stalled +#define USB_TXCSRL5_SETUP 0x0010 // Setup Packet +#define USB_TXCSRL5_STALL 0x0010 // Send STALL +#define USB_TXCSRL5_FLUSH 0x0008 // Flush FIFO +#define USB_TXCSRL5_ERROR 0x0004 // Error +#define USB_TXCSRL5_UNDRN 0x0004 // Underrun +#define USB_TXCSRL5_FIFONE 0x0002 // FIFO Not Empty +#define USB_TXCSRL5_TXRDY 0x0001 // Transmit Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXCSRH5 register. // //***************************************************************************** -#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH5_MODE 0x00000020 // Mode -#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH5_DT 0x00000001 // Data Toggle +#define USB_TXCSRH5_AUTOSET 0x0080 // Auto Set +#define USB_TXCSRH5_ISO 0x0040 // Isochronous Transfers +#define USB_TXCSRH5_MODE 0x0020 // Mode +#define USB_TXCSRH5_DMAEN 0x0010 // DMA Request Enable +#define USB_TXCSRH5_FDT 0x0008 // Force Data Toggle +#define USB_TXCSRH5_DMAMOD 0x0004 // DMA Request Mode +#define USB_TXCSRH5_DTWE 0x0002 // Data Toggle Write Enable +#define USB_TXCSRH5_DT 0x0001 // Data Toggle //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXMAXP5 register. // //***************************************************************************** -#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP5_MAXLOAD_M 0x07FF // Maximum Payload #define USB_RXMAXP5_MAXLOAD_S 0 //***************************************************************************** @@ -1695,33 +1226,33 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCSRL5 register. // //***************************************************************************** -#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL5_STALL 0x00000020 // Send STALL -#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL5_ERROR 0x00000004 // Error -#define USB_RXCSRL5_OVER 0x00000004 // Overrun -#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready +#define USB_RXCSRL5_CLRDT 0x0080 // Clear Data Toggle +#define USB_RXCSRL5_STALLED 0x0040 // Endpoint Stalled +#define USB_RXCSRL5_STALL 0x0020 // Send STALL +#define USB_RXCSRL5_REQPKT 0x0020 // Request Packet +#define USB_RXCSRL5_FLUSH 0x0010 // Flush FIFO +#define USB_RXCSRL5_NAKTO 0x0008 // NAK Timeout +#define USB_RXCSRL5_DATAERR 0x0008 // Data Error +#define USB_RXCSRL5_ERROR 0x0004 // Error +#define USB_RXCSRL5_OVER 0x0004 // Overrun +#define USB_RXCSRL5_FULL 0x0002 // FIFO Full +#define USB_RXCSRL5_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXCSRH5 register. // //***************************************************************************** -#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH5_DT 0x00000002 // Data Toggle -#define USB_RXCSRH5_INCOMPRX 0x00000001 // Incomplete RX Transmission +#define USB_RXCSRH5_AUTOCL 0x0080 // Auto Clear +#define USB_RXCSRH5_AUTORQ 0x0040 // Auto Request +#define USB_RXCSRH5_ISO 0x0040 // Isochronous Transfers +#define USB_RXCSRH5_DMAEN 0x0020 // DMA Request Enable +#define USB_RXCSRH5_DISNYET 0x0010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x0010 // PID Error +#define USB_RXCSRH5_DMAMOD 0x0008 // DMA Request Mode +#define USB_RXCSRH5_DTWE 0x0004 // Data Toggle Write Enable +#define USB_RXCSRH5_DT 0x0002 // Data Toggle +#define USB_RXCSRH5_INCOMPRX 0x0001 // Incomplete RX Transmission // Status //***************************************************************************** @@ -1729,7 +1260,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCOUNT5 register. // //***************************************************************************** -#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT5_COUNT_M 0x1FFF // Receive Packet Count #define USB_RXCOUNT5_COUNT_S 0 //***************************************************************************** @@ -1737,17 +1268,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXTYPE5 register. // //***************************************************************************** -#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE5_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE5_SPEED_M 0x00C0 // Operating Speed +#define USB_TXTYPE5_SPEED_DFLT 0x0000 // Default +#define USB_TXTYPE5_SPEED_HIGH 0x0040 // High +#define USB_TXTYPE5_SPEED_FULL 0x0080 // Full +#define USB_TXTYPE5_SPEED_LOW 0x00C0 // Low +#define USB_TXTYPE5_PROTO_M 0x0030 // Protocol +#define USB_TXTYPE5_PROTO_CTRL 0x0000 // Control +#define USB_TXTYPE5_PROTO_ISOC 0x0010 // Isochronous +#define USB_TXTYPE5_PROTO_BULK 0x0020 // Bulk +#define USB_TXTYPE5_PROTO_INT 0x0030 // Interrupt +#define USB_TXTYPE5_TEP_M 0x000F // Target Endpoint Number #define USB_TXTYPE5_TEP_S 0 //***************************************************************************** @@ -1756,31 +1287,27 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXINTERVAL5_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL5_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL5_NAKLMT_S \ - 0 -#define USB_TXINTERVAL5_TXPOLL_S \ - 0 +#define USB_TXINTERVAL5_TXPOLL_M 0x00FF // TX Polling +#define USB_TXINTERVAL5_NAKLMT_M 0x00FF // NAK Limit +#define USB_TXINTERVAL5_NAKLMT_S 0 +#define USB_TXINTERVAL5_TXPOLL_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXTYPE5 register. // //***************************************************************************** -#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE5_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE5_SPEED_M 0x00C0 // Operating Speed +#define USB_RXTYPE5_SPEED_DFLT 0x0000 // Default +#define USB_RXTYPE5_SPEED_HIGH 0x0040 // High +#define USB_RXTYPE5_SPEED_FULL 0x0080 // Full +#define USB_RXTYPE5_SPEED_LOW 0x00C0 // Low +#define USB_RXTYPE5_PROTO_M 0x0030 // Protocol +#define USB_RXTYPE5_PROTO_CTRL 0x0000 // Control +#define USB_RXTYPE5_PROTO_ISOC 0x0010 // Isochronous +#define USB_RXTYPE5_PROTO_BULK 0x0020 // Bulk +#define USB_RXTYPE5_PROTO_INT 0x0030 // Interrupt +#define USB_RXTYPE5_TEP_M 0x000F // Target Endpoint Number #define USB_RXTYPE5_TEP_S 0 //***************************************************************************** @@ -1789,21 +1316,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXINTERVAL5_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL5_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL5_TXPOLL_S \ - 0 -#define USB_RXINTERVAL5_NAKLMT_S \ - 0 +#define USB_RXINTERVAL5_TXPOLL_M 0x00FF // RX Polling +#define USB_RXINTERVAL5_NAKLMT_M 0x00FF // NAK Limit +#define USB_RXINTERVAL5_TXPOLL_S 0 +#define USB_RXINTERVAL5_NAKLMT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXMAXP6 register. // //***************************************************************************** -#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP6_MAXLOAD_M 0x07FF // Maximum Payload #define USB_TXMAXP6_MAXLOAD_S 0 //***************************************************************************** @@ -1811,37 +1334,37 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXCSRL6 register. // //***************************************************************************** -#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL6_STALL 0x00000010 // Send STALL -#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL6_ERROR 0x00000004 // Error -#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready +#define USB_TXCSRL6_NAKTO 0x0080 // NAK Timeout +#define USB_TXCSRL6_CLRDT 0x0040 // Clear Data Toggle +#define USB_TXCSRL6_STALLED 0x0020 // Endpoint Stalled +#define USB_TXCSRL6_STALL 0x0010 // Send STALL +#define USB_TXCSRL6_SETUP 0x0010 // Setup Packet +#define USB_TXCSRL6_FLUSH 0x0008 // Flush FIFO +#define USB_TXCSRL6_ERROR 0x0004 // Error +#define USB_TXCSRL6_UNDRN 0x0004 // Underrun +#define USB_TXCSRL6_FIFONE 0x0002 // FIFO Not Empty +#define USB_TXCSRL6_TXRDY 0x0001 // Transmit Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXCSRH6 register. // //***************************************************************************** -#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH6_MODE 0x00000020 // Mode -#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH6_DT 0x00000001 // Data Toggle +#define USB_TXCSRH6_AUTOSET 0x0080 // Auto Set +#define USB_TXCSRH6_ISO 0x0040 // Isochronous Transfers +#define USB_TXCSRH6_MODE 0x0020 // Mode +#define USB_TXCSRH6_DMAEN 0x0010 // DMA Request Enable +#define USB_TXCSRH6_FDT 0x0008 // Force Data Toggle +#define USB_TXCSRH6_DMAMOD 0x0004 // DMA Request Mode +#define USB_TXCSRH6_DTWE 0x0002 // Data Toggle Write Enable +#define USB_TXCSRH6_DT 0x0001 // Data Toggle //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXMAXP6 register. // //***************************************************************************** -#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP6_MAXLOAD_M 0x07FF // Maximum Payload #define USB_RXMAXP6_MAXLOAD_S 0 //***************************************************************************** @@ -1849,33 +1372,33 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCSRL6 register. // //***************************************************************************** -#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL6_STALL 0x00000020 // Send STALL -#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL6_ERROR 0x00000004 // Error -#define USB_RXCSRL6_OVER 0x00000004 // Overrun -#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready +#define USB_RXCSRL6_CLRDT 0x0080 // Clear Data Toggle +#define USB_RXCSRL6_STALLED 0x0040 // Endpoint Stalled +#define USB_RXCSRL6_REQPKT 0x0020 // Request Packet +#define USB_RXCSRL6_STALL 0x0020 // Send STALL +#define USB_RXCSRL6_FLUSH 0x0010 // Flush FIFO +#define USB_RXCSRL6_NAKTO 0x0008 // NAK Timeout +#define USB_RXCSRL6_DATAERR 0x0008 // Data Error +#define USB_RXCSRL6_ERROR 0x0004 // Error +#define USB_RXCSRL6_OVER 0x0004 // Overrun +#define USB_RXCSRL6_FULL 0x0002 // FIFO Full +#define USB_RXCSRL6_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXCSRH6 register. // //***************************************************************************** -#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH6_DT 0x00000002 // Data Toggle -#define USB_RXCSRH6_INCOMPRX 0x00000001 // Incomplete RX Transmission +#define USB_RXCSRH6_AUTOCL 0x0080 // Auto Clear +#define USB_RXCSRH6_AUTORQ 0x0040 // Auto Request +#define USB_RXCSRH6_ISO 0x0040 // Isochronous Transfers +#define USB_RXCSRH6_DMAEN 0x0020 // DMA Request Enable +#define USB_RXCSRH6_DISNYET 0x0010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x0010 // PID Error +#define USB_RXCSRH6_DMAMOD 0x0008 // DMA Request Mode +#define USB_RXCSRH6_DTWE 0x0004 // Data Toggle Write Enable +#define USB_RXCSRH6_DT 0x0002 // Data Toggle +#define USB_RXCSRH6_INCOMPRX 0x0001 // Incomplete RX Transmission // Status //***************************************************************************** @@ -1883,7 +1406,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCOUNT6 register. // //***************************************************************************** -#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT6_COUNT_M 0x1FFF // Receive Packet Count #define USB_RXCOUNT6_COUNT_S 0 //***************************************************************************** @@ -1891,17 +1414,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXTYPE6 register. // //***************************************************************************** -#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE6_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE6_SPEED_M 0x00C0 // Operating Speed +#define USB_TXTYPE6_SPEED_DFLT 0x0000 // Default +#define USB_TXTYPE6_SPEED_HIGH 0x0040 // High +#define USB_TXTYPE6_SPEED_FULL 0x0080 // Full +#define USB_TXTYPE6_SPEED_LOW 0x00C0 // Low +#define USB_TXTYPE6_PROTO_M 0x0030 // Protocol +#define USB_TXTYPE6_PROTO_CTRL 0x0000 // Control +#define USB_TXTYPE6_PROTO_ISOC 0x0010 // Isochronous +#define USB_TXTYPE6_PROTO_BULK 0x0020 // Bulk +#define USB_TXTYPE6_PROTO_INT 0x0030 // Interrupt +#define USB_TXTYPE6_TEP_M 0x000F // Target Endpoint Number #define USB_TXTYPE6_TEP_S 0 //***************************************************************************** @@ -1910,31 +1433,27 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXINTERVAL6_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL6_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL6_TXPOLL_S \ - 0 -#define USB_TXINTERVAL6_NAKLMT_S \ - 0 +#define USB_TXINTERVAL6_TXPOLL_M 0x00FF // TX Polling +#define USB_TXINTERVAL6_NAKLMT_M 0x00FF // NAK Limit +#define USB_TXINTERVAL6_TXPOLL_S 0 +#define USB_TXINTERVAL6_NAKLMT_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXTYPE6 register. // //***************************************************************************** -#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE6_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE6_SPEED_M 0x00C0 // Operating Speed +#define USB_RXTYPE6_SPEED_DFLT 0x0000 // Default +#define USB_RXTYPE6_SPEED_HIGH 0x0040 // High +#define USB_RXTYPE6_SPEED_FULL 0x0080 // Full +#define USB_RXTYPE6_SPEED_LOW 0x00C0 // Low +#define USB_RXTYPE6_PROTO_M 0x0030 // Protocol +#define USB_RXTYPE6_PROTO_CTRL 0x0000 // Control +#define USB_RXTYPE6_PROTO_ISOC 0x0010 // Isochronous +#define USB_RXTYPE6_PROTO_BULK 0x0020 // Bulk +#define USB_RXTYPE6_PROTO_INT 0x0030 // Interrupt +#define USB_RXTYPE6_TEP_M 0x000F // Target Endpoint Number #define USB_RXTYPE6_TEP_S 0 //***************************************************************************** @@ -1943,21 +1462,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXINTERVAL6_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL6_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL6_NAKLMT_S \ - 0 -#define USB_RXINTERVAL6_TXPOLL_S \ - 0 +#define USB_RXINTERVAL6_TXPOLL_M 0x00FF // RX Polling +#define USB_RXINTERVAL6_NAKLMT_M 0x00FF // NAK Limit +#define USB_RXINTERVAL6_NAKLMT_S 0 +#define USB_RXINTERVAL6_TXPOLL_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXMAXP7 register. // //***************************************************************************** -#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP7_MAXLOAD_M 0x07FF // Maximum Payload #define USB_TXMAXP7_MAXLOAD_S 0 //***************************************************************************** @@ -1965,37 +1480,37 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXCSRL7 register. // //***************************************************************************** -#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout -#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle -#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled -#define USB_TXCSRL7_STALL 0x00000010 // Send STALL -#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet -#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO -#define USB_TXCSRL7_ERROR 0x00000004 // Error -#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun -#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty -#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready +#define USB_TXCSRL7_NAKTO 0x0080 // NAK Timeout +#define USB_TXCSRL7_CLRDT 0x0040 // Clear Data Toggle +#define USB_TXCSRL7_STALLED 0x0020 // Endpoint Stalled +#define USB_TXCSRL7_STALL 0x0010 // Send STALL +#define USB_TXCSRL7_SETUP 0x0010 // Setup Packet +#define USB_TXCSRL7_FLUSH 0x0008 // Flush FIFO +#define USB_TXCSRL7_ERROR 0x0004 // Error +#define USB_TXCSRL7_UNDRN 0x0004 // Underrun +#define USB_TXCSRL7_FIFONE 0x0002 // FIFO Not Empty +#define USB_TXCSRL7_TXRDY 0x0001 // Transmit Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXCSRH7 register. // //***************************************************************************** -#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set -#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers -#define USB_TXCSRH7_MODE 0x00000020 // Mode -#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable -#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle -#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode -#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable -#define USB_TXCSRH7_DT 0x00000001 // Data Toggle +#define USB_TXCSRH7_AUTOSET 0x0080 // Auto Set +#define USB_TXCSRH7_ISO 0x0040 // Isochronous Transfers +#define USB_TXCSRH7_MODE 0x0020 // Mode +#define USB_TXCSRH7_DMAEN 0x0010 // DMA Request Enable +#define USB_TXCSRH7_FDT 0x0008 // Force Data Toggle +#define USB_TXCSRH7_DMAMOD 0x0004 // DMA Request Mode +#define USB_TXCSRH7_DTWE 0x0002 // Data Toggle Write Enable +#define USB_TXCSRH7_DT 0x0001 // Data Toggle //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXMAXP7 register. // //***************************************************************************** -#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP7_MAXLOAD_M 0x07FF // Maximum Payload #define USB_RXMAXP7_MAXLOAD_S 0 //***************************************************************************** @@ -2003,33 +1518,33 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCSRL7 register. // //***************************************************************************** -#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle -#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled -#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet -#define USB_RXCSRL7_STALL 0x00000020 // Send STALL -#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO -#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error -#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout -#define USB_RXCSRL7_ERROR 0x00000004 // Error -#define USB_RXCSRL7_OVER 0x00000004 // Overrun -#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full -#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready +#define USB_RXCSRL7_CLRDT 0x0080 // Clear Data Toggle +#define USB_RXCSRL7_STALLED 0x0040 // Endpoint Stalled +#define USB_RXCSRL7_REQPKT 0x0020 // Request Packet +#define USB_RXCSRL7_STALL 0x0020 // Send STALL +#define USB_RXCSRL7_FLUSH 0x0010 // Flush FIFO +#define USB_RXCSRL7_DATAERR 0x0008 // Data Error +#define USB_RXCSRL7_NAKTO 0x0008 // NAK Timeout +#define USB_RXCSRL7_ERROR 0x0004 // Error +#define USB_RXCSRL7_OVER 0x0004 // Overrun +#define USB_RXCSRL7_FULL 0x0002 // FIFO Full +#define USB_RXCSRL7_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXCSRH7 register. // //***************************************************************************** -#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear -#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers -#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request -#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable -#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error -#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET -#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode -#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable -#define USB_RXCSRH7_DT 0x00000002 // Data Toggle -#define USB_RXCSRH7_INCOMPRX 0x00000001 // Incomplete RX Transmission +#define USB_RXCSRH7_AUTOCL 0x0080 // Auto Clear +#define USB_RXCSRH7_ISO 0x0040 // Isochronous Transfers +#define USB_RXCSRH7_AUTORQ 0x0040 // Auto Request +#define USB_RXCSRH7_DMAEN 0x0020 // DMA Request Enable +#define USB_RXCSRH7_PIDERR 0x0010 // PID Error +#define USB_RXCSRH7_DISNYET 0x0010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x0008 // DMA Request Mode +#define USB_RXCSRH7_DTWE 0x0004 // Data Toggle Write Enable +#define USB_RXCSRH7_DT 0x0002 // Data Toggle +#define USB_RXCSRH7_INCOMPRX 0x0001 // Incomplete RX Transmission // Status //***************************************************************************** @@ -2037,7 +1552,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_RXCOUNT7 register. // //***************************************************************************** -#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT7_COUNT_M 0x1FFF // Receive Packet Count #define USB_RXCOUNT7_COUNT_S 0 //***************************************************************************** @@ -2045,17 +1560,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_TXTYPE7 register. // //***************************************************************************** -#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed -#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default -#define USB_TXTYPE7_SPEED_HIGH 0x00000040 // High -#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full -#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low -#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol -#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control -#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous -#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk -#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt -#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE7_SPEED_M 0x00C0 // Operating Speed +#define USB_TXTYPE7_SPEED_DFLT 0x0000 // Default +#define USB_TXTYPE7_SPEED_HIGH 0x0040 // High +#define USB_TXTYPE7_SPEED_FULL 0x0080 // Full +#define USB_TXTYPE7_SPEED_LOW 0x00C0 // Low +#define USB_TXTYPE7_PROTO_M 0x0030 // Protocol +#define USB_TXTYPE7_PROTO_CTRL 0x0000 // Control +#define USB_TXTYPE7_PROTO_ISOC 0x0010 // Isochronous +#define USB_TXTYPE7_PROTO_BULK 0x0020 // Bulk +#define USB_TXTYPE7_PROTO_INT 0x0030 // Interrupt +#define USB_TXTYPE7_TEP_M 0x000F // Target Endpoint Number #define USB_TXTYPE7_TEP_S 0 //***************************************************************************** @@ -2064,31 +1579,27 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXINTERVAL7_TXPOLL_M \ - 0x000000FF // TX Polling -#define USB_TXINTERVAL7_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_TXINTERVAL7_NAKLMT_S \ - 0 -#define USB_TXINTERVAL7_TXPOLL_S \ - 0 +#define USB_TXINTERVAL7_TXPOLL_M 0x00FF // TX Polling +#define USB_TXINTERVAL7_NAKLMT_M 0x00FF // NAK Limit +#define USB_TXINTERVAL7_NAKLMT_S 0 +#define USB_TXINTERVAL7_TXPOLL_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXTYPE7 register. // //***************************************************************************** -#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed -#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default -#define USB_RXTYPE7_SPEED_HIGH 0x00000040 // High -#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full -#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low -#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol -#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control -#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous -#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk -#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt -#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE7_SPEED_M 0x00C0 // Operating Speed +#define USB_RXTYPE7_SPEED_DFLT 0x0000 // Default +#define USB_RXTYPE7_SPEED_HIGH 0x0040 // High +#define USB_RXTYPE7_SPEED_FULL 0x0080 // Full +#define USB_RXTYPE7_SPEED_LOW 0x00C0 // Low +#define USB_RXTYPE7_PROTO_M 0x0030 // Protocol +#define USB_RXTYPE7_PROTO_CTRL 0x0000 // Control +#define USB_RXTYPE7_PROTO_ISOC 0x0010 // Isochronous +#define USB_RXTYPE7_PROTO_BULK 0x0020 // Bulk +#define USB_RXTYPE7_PROTO_INT 0x0030 // Interrupt +#define USB_RXTYPE7_TEP_M 0x000F // Target Endpoint Number #define USB_RXTYPE7_TEP_S 0 //***************************************************************************** @@ -2097,47 +1608,43 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXINTERVAL7_TXPOLL_M \ - 0x000000FF // RX Polling -#define USB_RXINTERVAL7_NAKLMT_M \ - 0x000000FF // NAK Limit -#define USB_RXINTERVAL7_NAKLMT_S \ - 0 -#define USB_RXINTERVAL7_TXPOLL_S \ - 0 +#define USB_RXINTERVAL7_TXPOLL_M 0x00FF // RX Polling +#define USB_RXINTERVAL7_NAKLMT_M 0x00FF // NAK Limit +#define USB_RXINTERVAL7_NAKLMT_S 0 +#define USB_RXINTERVAL7_TXPOLL_S 0 //***************************************************************************** // // The following are defines for the bit fields in the USB_O_DMAINTR register. // //***************************************************************************** -#define USB_DMAINTR_CH7 0x00000080 // Channel 7 DMA Interrupt -#define USB_DMAINTR_CH6 0x00000040 // Channel 6 DMA Interrupt -#define USB_DMAINTR_CH5 0x00000020 // Channel 5 DMA Interrupt -#define USB_DMAINTR_CH4 0x00000010 // Channel 4 DMA Interrupt -#define USB_DMAINTR_CH3 0x00000008 // Channel 3 DMA Interrupt -#define USB_DMAINTR_CH2 0x00000004 // Channel 2 DMA Interrupt -#define USB_DMAINTR_CH1 0x00000002 // Channel 1 DMA Interrupt -#define USB_DMAINTR_CH0 0x00000001 // Channel 0 DMA Interrupt +#define USB_DMAINTR_CH7 0x0080 // Channel 7 DMA Interrupt +#define USB_DMAINTR_CH6 0x0040 // Channel 6 DMA Interrupt +#define USB_DMAINTR_CH5 0x0020 // Channel 5 DMA Interrupt +#define USB_DMAINTR_CH4 0x0010 // Channel 4 DMA Interrupt +#define USB_DMAINTR_CH3 0x0008 // Channel 3 DMA Interrupt +#define USB_DMAINTR_CH2 0x0004 // Channel 2 DMA Interrupt +#define USB_DMAINTR_CH1 0x0002 // Channel 1 DMA Interrupt +#define USB_DMAINTR_CH0 0x0001 // Channel 0 DMA Interrupt //***************************************************************************** // // The following are defines for the bit fields in the USB_O_DMACTL0 register. // //***************************************************************************** -#define USB_DMACTL0_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL0_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL0_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL0_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified +#define USB_DMACTL0_BRSTM_M 0x0600 // Burst Mode +#define USB_DMACTL0_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define USB_DMACTL0_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define USB_DMACTL0_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified // length -#define USB_DMACTL0_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or +#define USB_DMACTL0_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or // unspecified length -#define USB_DMACTL0_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL0_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL0_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL0_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL0_DIR 0x00000002 // DMA Direction -#define USB_DMACTL0_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL0_ERR 0x0100 // Bus Error Bit +#define USB_DMACTL0_EP_M 0x00F0 // Endpoint number +#define USB_DMACTL0_IE 0x0008 // DMA Interrupt Enable +#define USB_DMACTL0_MODE 0x0004 // DMA Transfer Mode +#define USB_DMACTL0_DIR 0x0002 // DMA Direction +#define USB_DMACTL0_ENABLE 0x0001 // DMA Transfer Enable #define USB_DMACTL0_EP_S 4 //***************************************************************************** @@ -2162,19 +1669,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_DMACTL1 register. // //***************************************************************************** -#define USB_DMACTL1_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL1_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL1_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL1_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified +#define USB_DMACTL1_BRSTM_M 0x0600 // Burst Mode +#define USB_DMACTL1_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define USB_DMACTL1_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define USB_DMACTL1_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified // length -#define USB_DMACTL1_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or +#define USB_DMACTL1_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or // unspecified length -#define USB_DMACTL1_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL1_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL1_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL1_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL1_DIR 0x00000002 // DMA Direction -#define USB_DMACTL1_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL1_ERR 0x0100 // Bus Error Bit +#define USB_DMACTL1_EP_M 0x00F0 // Endpoint number +#define USB_DMACTL1_IE 0x0008 // DMA Interrupt Enable +#define USB_DMACTL1_MODE 0x0004 // DMA Transfer Mode +#define USB_DMACTL1_DIR 0x0002 // DMA Direction +#define USB_DMACTL1_ENABLE 0x0001 // DMA Transfer Enable #define USB_DMACTL1_EP_S 4 //***************************************************************************** @@ -2199,19 +1706,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_DMACTL2 register. // //***************************************************************************** -#define USB_DMACTL2_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL2_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL2_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL2_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified +#define USB_DMACTL2_BRSTM_M 0x0600 // Burst Mode +#define USB_DMACTL2_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define USB_DMACTL2_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define USB_DMACTL2_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified // length -#define USB_DMACTL2_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or +#define USB_DMACTL2_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or // unspecified length -#define USB_DMACTL2_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL2_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL2_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL2_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL2_DIR 0x00000002 // DMA Direction -#define USB_DMACTL2_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL2_ERR 0x0100 // Bus Error Bit +#define USB_DMACTL2_EP_M 0x00F0 // Endpoint number +#define USB_DMACTL2_IE 0x0008 // DMA Interrupt Enable +#define USB_DMACTL2_MODE 0x0004 // DMA Transfer Mode +#define USB_DMACTL2_DIR 0x0002 // DMA Direction +#define USB_DMACTL2_ENABLE 0x0001 // DMA Transfer Enable #define USB_DMACTL2_EP_S 4 //***************************************************************************** @@ -2236,19 +1743,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_DMACTL3 register. // //***************************************************************************** -#define USB_DMACTL3_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL3_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL3_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL3_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified +#define USB_DMACTL3_BRSTM_M 0x0600 // Burst Mode +#define USB_DMACTL3_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define USB_DMACTL3_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define USB_DMACTL3_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified // length -#define USB_DMACTL3_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or +#define USB_DMACTL3_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or // unspecified length -#define USB_DMACTL3_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL3_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL3_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL3_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL3_DIR 0x00000002 // DMA Direction -#define USB_DMACTL3_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL3_ERR 0x0100 // Bus Error Bit +#define USB_DMACTL3_EP_M 0x00F0 // Endpoint number +#define USB_DMACTL3_IE 0x0008 // DMA Interrupt Enable +#define USB_DMACTL3_MODE 0x0004 // DMA Transfer Mode +#define USB_DMACTL3_DIR 0x0002 // DMA Direction +#define USB_DMACTL3_ENABLE 0x0001 // DMA Transfer Enable #define USB_DMACTL3_EP_S 4 //***************************************************************************** @@ -2273,19 +1780,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_DMACTL4 register. // //***************************************************************************** -#define USB_DMACTL4_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL4_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL4_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL4_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified +#define USB_DMACTL4_BRSTM_M 0x0600 // Burst Mode +#define USB_DMACTL4_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define USB_DMACTL4_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define USB_DMACTL4_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified // length -#define USB_DMACTL4_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or +#define USB_DMACTL4_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or // unspecified length -#define USB_DMACTL4_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL4_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL4_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL4_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL4_DIR 0x00000002 // DMA Direction -#define USB_DMACTL4_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL4_ERR 0x0100 // Bus Error Bit +#define USB_DMACTL4_EP_M 0x00F0 // Endpoint number +#define USB_DMACTL4_IE 0x0008 // DMA Interrupt Enable +#define USB_DMACTL4_MODE 0x0004 // DMA Transfer Mode +#define USB_DMACTL4_DIR 0x0002 // DMA Direction +#define USB_DMACTL4_ENABLE 0x0001 // DMA Transfer Enable #define USB_DMACTL4_EP_S 4 //***************************************************************************** @@ -2310,19 +1817,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_DMACTL5 register. // //***************************************************************************** -#define USB_DMACTL5_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL5_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL5_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL5_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified +#define USB_DMACTL5_BRSTM_M 0x0600 // Burst Mode +#define USB_DMACTL5_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define USB_DMACTL5_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define USB_DMACTL5_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified // length -#define USB_DMACTL5_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or +#define USB_DMACTL5_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or // unspecified length -#define USB_DMACTL5_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL5_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL5_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL5_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL5_DIR 0x00000002 // DMA Direction -#define USB_DMACTL5_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL5_ERR 0x0100 // Bus Error Bit +#define USB_DMACTL5_EP_M 0x00F0 // Endpoint number +#define USB_DMACTL5_IE 0x0008 // DMA Interrupt Enable +#define USB_DMACTL5_MODE 0x0004 // DMA Transfer Mode +#define USB_DMACTL5_DIR 0x0002 // DMA Direction +#define USB_DMACTL5_ENABLE 0x0001 // DMA Transfer Enable #define USB_DMACTL5_EP_S 4 //***************************************************************************** @@ -2347,19 +1854,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_DMACTL6 register. // //***************************************************************************** -#define USB_DMACTL6_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL6_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL6_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL6_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified +#define USB_DMACTL6_BRSTM_M 0x0600 // Burst Mode +#define USB_DMACTL6_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define USB_DMACTL6_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define USB_DMACTL6_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified // length -#define USB_DMACTL6_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or +#define USB_DMACTL6_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or // unspecified length -#define USB_DMACTL6_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL6_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL6_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL6_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL6_DIR 0x00000002 // DMA Direction -#define USB_DMACTL6_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL6_ERR 0x0100 // Bus Error Bit +#define USB_DMACTL6_EP_M 0x00F0 // Endpoint number +#define USB_DMACTL6_IE 0x0008 // DMA Interrupt Enable +#define USB_DMACTL6_MODE 0x0004 // DMA Transfer Mode +#define USB_DMACTL6_DIR 0x0002 // DMA Direction +#define USB_DMACTL6_ENABLE 0x0001 // DMA Transfer Enable #define USB_DMACTL6_EP_S 4 //***************************************************************************** @@ -2384,19 +1891,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_DMACTL7 register. // //***************************************************************************** -#define USB_DMACTL7_BRSTM_M 0x00000600 // Burst Mode -#define USB_DMACTL7_BRSTM_ANY 0x00000000 // Bursts of unspecified length -#define USB_DMACTL7_BRSTM_INC4 0x00000200 // INCR4 or unspecified length -#define USB_DMACTL7_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified +#define USB_DMACTL7_BRSTM_M 0x0600 // Burst Mode +#define USB_DMACTL7_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define USB_DMACTL7_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define USB_DMACTL7_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified // length -#define USB_DMACTL7_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or +#define USB_DMACTL7_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or // unspecified length -#define USB_DMACTL7_ERR 0x00000100 // Bus Error Bit -#define USB_DMACTL7_EP_M 0x000000F0 // Endpoint number -#define USB_DMACTL7_IE 0x00000008 // DMA Interrupt Enable -#define USB_DMACTL7_MODE 0x00000004 // DMA Transfer Mode -#define USB_DMACTL7_DIR 0x00000002 // DMA Direction -#define USB_DMACTL7_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL7_ERR 0x0100 // Bus Error Bit +#define USB_DMACTL7_EP_M 0x00F0 // Endpoint number +#define USB_DMACTL7_IE 0x0008 // DMA Interrupt Enable +#define USB_DMACTL7_MODE 0x0004 // DMA Transfer Mode +#define USB_DMACTL7_DIR 0x0002 // DMA Direction +#define USB_DMACTL7_ENABLE 0x0001 // DMA Transfer Enable #define USB_DMACTL7_EP_S 4 //***************************************************************************** @@ -2422,7 +1929,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT1_M 0xFFFF // Block Transfer Packet Count #define USB_RQPKTCOUNT1_S 0 //***************************************************************************** @@ -2431,7 +1938,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT2_M 0xFFFF // Block Transfer Packet Count #define USB_RQPKTCOUNT2_S 0 //***************************************************************************** @@ -2440,7 +1947,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT3_M 0xFFFF // Block Transfer Packet Count #define USB_RQPKTCOUNT3_S 0 //***************************************************************************** @@ -2449,7 +1956,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT4_COUNT_M 0xFFFF // Block Transfer Packet Count #define USB_RQPKTCOUNT4_COUNT_S 0 //***************************************************************************** @@ -2458,7 +1965,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT5_COUNT_M 0xFFFF // Block Transfer Packet Count #define USB_RQPKTCOUNT5_COUNT_S 0 //***************************************************************************** @@ -2467,7 +1974,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT6_COUNT_M 0xFFFF // Block Transfer Packet Count #define USB_RQPKTCOUNT6_COUNT_S 0 //***************************************************************************** @@ -2476,7 +1983,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT7_COUNT_M 0xFFFF // Block Transfer Packet Count #define USB_RQPKTCOUNT7_COUNT_S 0 //***************************************************************************** @@ -2485,19 +1992,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer +#define USB_RXDPKTBUFDIS_EP7 0x0080 // EP7 RX Double-Packet Buffer // Disable -#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer +#define USB_RXDPKTBUFDIS_EP6 0x0040 // EP6 RX Double-Packet Buffer // Disable -#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer +#define USB_RXDPKTBUFDIS_EP5 0x0020 // EP5 RX Double-Packet Buffer // Disable -#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer +#define USB_RXDPKTBUFDIS_EP4 0x0010 // EP4 RX Double-Packet Buffer // Disable -#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer +#define USB_RXDPKTBUFDIS_EP3 0x0008 // EP3 RX Double-Packet Buffer // Disable -#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer +#define USB_RXDPKTBUFDIS_EP2 0x0004 // EP2 RX Double-Packet Buffer // Disable -#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer +#define USB_RXDPKTBUFDIS_EP1 0x0002 // EP1 RX Double-Packet Buffer // Disable //***************************************************************************** @@ -2506,19 +2013,19 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // register. // //***************************************************************************** -#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer +#define USB_TXDPKTBUFDIS_EP7 0x0080 // EP7 TX Double-Packet Buffer // Disable -#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer +#define USB_TXDPKTBUFDIS_EP6 0x0040 // EP6 TX Double-Packet Buffer // Disable -#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer +#define USB_TXDPKTBUFDIS_EP5 0x0020 // EP5 TX Double-Packet Buffer // Disable -#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer +#define USB_TXDPKTBUFDIS_EP4 0x0010 // EP4 TX Double-Packet Buffer // Disable -#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer +#define USB_TXDPKTBUFDIS_EP3 0x0008 // EP3 TX Double-Packet Buffer // Disable -#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer +#define USB_TXDPKTBUFDIS_EP2 0x0004 // EP2 TX Double-Packet Buffer // Disable -#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer +#define USB_TXDPKTBUFDIS_EP1 0x0002 // EP1 TX Double-Packet Buffer // Disable //***************************************************************************** @@ -2526,7 +2033,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_CTO register. // //***************************************************************************** -#define USB_CTO_CCTV_M 0x0000FFFF // Configurable Chirp Timeout Value +#define USB_CTO_CCTV_M 0xFFFF // Configurable Chirp Timeout Value #define USB_CTO_CCTV_S 0 //***************************************************************************** @@ -2534,7 +2041,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_HHSRTN register. // //***************************************************************************** -#define USB_HHSRTN_HHSRTN_M 0x0000FFFF // HIgh Speed to UTM Operating +#define USB_HHSRTN_HHSRTN_M 0xFFFF // HIgh Speed to UTM Operating // Delay #define USB_HHSRTN_HHSRTN_S 0 @@ -2543,7 +2050,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_HSBT register. // //***************************************************************************** -#define USB_HSBT_HSBT_M 0x0000000F // High Speed Timeout Adder +#define USB_HSBT_HSBT_M 0x000F // High Speed Timeout Adder #define USB_HSBT_HSBT_S 0 //***************************************************************************** @@ -2551,11 +2058,11 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_LPMATTR register. // //***************************************************************************** -#define USB_LPMATTR_ENDPT_M 0x0000F000 // Endpoint -#define USB_LPMATTR_RMTWAK 0x00000100 // Remote Wake -#define USB_LPMATTR_HIRD_M 0x000000F0 // Host Initiated Resume Duration -#define USB_LPMATTR_LS_M 0x0000000F // Link State -#define USB_LPMATTR_LS_L1 0x00000001 // Sleep State (L1) +#define USB_LPMATTR_ENDPT_M 0xF000 // Endpoint +#define USB_LPMATTR_RMTWAK 0x0100 // Remote Wake +#define USB_LPMATTR_HIRD_M 0x00F0 // Host Initiated Resume Duration +#define USB_LPMATTR_LS_M 0x000F // Link State +#define USB_LPMATTR_LS_L1 0x0001 // Sleep State (L1) #define USB_LPMATTR_ENDPT_S 12 #define USB_LPMATTR_HIRD_S 4 @@ -2564,56 +2071,56 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_LPMCNTRL register. // //***************************************************************************** -#define USB_LPMCNTRL_NAK 0x00000010 // LPM NAK -#define USB_LPMCNTRL_EN_M 0x0000000C // LPM Enable -#define USB_LPMCNTRL_EN_NONE 0x00000000 // LPM and Extended transactions +#define USB_LPMCNTRL_NAK 0x0010 // LPM NAK +#define USB_LPMCNTRL_EN_M 0x000C // LPM Enable +#define USB_LPMCNTRL_EN_NONE 0x0000 // LPM and Extended transactions // are not supported. In this case, // the USB does not respond to LPM // transactions and LPM // transactions cause a timeout -#define USB_LPMCNTRL_EN_EXT 0x00000004 // LPM is not supported but +#define USB_LPMCNTRL_EN_EXT 0x0004 // LPM is not supported but // extended transactions are // supported. In this case, the USB // does respond to an LPM // transaction with a STALL -#define USB_LPMCNTRL_EN_LPMEXT 0x0000000C // The USB supports LPM extended +#define USB_LPMCNTRL_EN_LPMEXT 0x000C // The USB supports LPM extended // transactions. In this case, the // USB responds with a NYET or an // ACK as determined by the value // of TXLPM and other conditions -#define USB_LPMCNTRL_RES 0x00000002 // LPM Resume -#define USB_LPMCNTRL_TXLPM 0x00000001 // Transmit LPM Transaction Enable +#define USB_LPMCNTRL_RES 0x0002 // LPM Resume +#define USB_LPMCNTRL_TXLPM 0x0001 // Transmit LPM Transaction Enable //***************************************************************************** // // The following are defines for the bit fields in the USB_O_LPMIM register. // //***************************************************************************** -#define USB_LPMIM_ERR 0x00000020 // LPM Error Interrupt Mask -#define USB_LPMIM_RES 0x00000010 // LPM Resume Interrupt Mask -#define USB_LPMIM_NC 0x00000008 // LPM NC Interrupt Mask -#define USB_LPMIM_ACK 0x00000004 // LPM ACK Interrupt Mask -#define USB_LPMIM_NY 0x00000002 // LPM NY Interrupt Mask -#define USB_LPMIM_STALL 0x00000001 // LPM STALL Interrupt Mask +#define USB_LPMIM_ERR 0x0020 // LPM Error Interrupt Mask +#define USB_LPMIM_RES 0x0010 // LPM Resume Interrupt Mask +#define USB_LPMIM_NC 0x0008 // LPM NC Interrupt Mask +#define USB_LPMIM_ACK 0x0004 // LPM ACK Interrupt Mask +#define USB_LPMIM_NY 0x0002 // LPM NY Interrupt Mask +#define USB_LPMIM_STALL 0x0001 // LPM STALL Interrupt Mask //***************************************************************************** // // The following are defines for the bit fields in the USB_O_LPMRIS register. // //***************************************************************************** -#define USB_LPMRIS_ERR 0x00000020 // LPM Interrupt Status -#define USB_LPMRIS_RES 0x00000010 // LPM Resume Interrupt Status -#define USB_LPMRIS_NC 0x00000008 // LPM NC Interrupt Status -#define USB_LPMRIS_ACK 0x00000004 // LPM ACK Interrupt Status -#define USB_LPMRIS_NY 0x00000002 // LPM NY Interrupt Status -#define USB_LPMRIS_LPMST 0x00000001 // LPM STALL Interrupt Status +#define USB_LPMRIS_ERR 0x0020 // LPM Interrupt Status +#define USB_LPMRIS_RES 0x0010 // LPM Resume Interrupt Status +#define USB_LPMRIS_NC 0x0008 // LPM NC Interrupt Status +#define USB_LPMRIS_ACK 0x0004 // LPM ACK Interrupt Status +#define USB_LPMRIS_NY 0x0002 // LPM NY Interrupt Status +#define USB_LPMRIS_LPMST 0x0001 // LPM STALL Interrupt Status //***************************************************************************** // // The following are defines for the bit fields in the USB_O_LPMFADDR register. // //***************************************************************************** -#define USB_LPMFADDR_ADDR_M 0x0000007F // LPM Function Address +#define USB_LPMFADDR_ADDR_M 0x007F // LPM Function Address #define USB_LPMFADDR_ADDR_S 0 //***************************************************************************** @@ -2621,22 +2128,22 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_EPC register. // //***************************************************************************** -#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action -#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged -#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate -#define USB_EPC_PFLTACT_LOW 0x00000200 // Low -#define USB_EPC_PFLTACT_HIGH 0x00000300 // High -#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable -#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense -#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable -#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable -#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable +#define USB_EPC_PFLTACT_M 0x0300 // Power Fault Action +#define USB_EPC_PFLTACT_UNCHG 0x0000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x0100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x0200 // Low +#define USB_EPC_PFLTACT_HIGH 0x0300 // High +#define USB_EPC_PFLTAEN 0x0040 // Power Fault Action Enable +#define USB_EPC_PFLTSEN_HIGH 0x0020 // Power Fault Sense +#define USB_EPC_PFLTEN 0x0010 // Power Fault Input Enable +#define USB_EPC_EPENDE 0x0004 // EPEN Drive Enable +#define USB_EPC_EPEN_M 0x0003 // External Power Supply Enable // Configuration -#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low -#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High -#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low +#define USB_EPC_EPEN_LOW 0x0000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x0001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x0002 // Power Enable High if VBUS Low // (OTG only) -#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High +#define USB_EPC_EPEN_VBHIGH 0x0003 // Power Enable High if VBUS High // (OTG only) //***************************************************************************** @@ -2644,21 +2151,21 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_EPCRIS register. // //***************************************************************************** -#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status +#define USB_EPCRIS_PF 0x0001 // USB Power Fault Interrupt Status //***************************************************************************** // // The following are defines for the bit fields in the USB_O_EPCIM register. // //***************************************************************************** -#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask +#define USB_EPCIM_PF 0x0001 // USB Power Fault Interrupt Mask //***************************************************************************** // // The following are defines for the bit fields in the USB_O_EPCISC register. // //***************************************************************************** -#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status +#define USB_EPCISC_PF 0x0001 // USB Power Fault Interrupt Status // and Clear //***************************************************************************** @@ -2666,21 +2173,21 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_DRRIS register. // //***************************************************************************** -#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status +#define USB_DRRIS_RESUME 0x0001 // RESUME Interrupt Status //***************************************************************************** // // The following are defines for the bit fields in the USB_O_DRIM register. // //***************************************************************************** -#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask +#define USB_DRIM_RESUME 0x0001 // RESUME Interrupt Mask //***************************************************************************** // // The following are defines for the bit fields in the USB_O_DRISC register. // //***************************************************************************** -#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and +#define USB_DRISC_RESUME 0x0001 // RESUME Interrupt Status and // Clear //***************************************************************************** @@ -2688,14 +2195,14 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_GPCS register. // //***************************************************************************** -#define USB_GPCS_DEVMOD_M 0x00000007 // Device Mode -#define USB_GPCS_DEVMOD_OTG 0x00000000 // Use USB0VBUS and USB0ID pin -#define USB_GPCS_DEVMOD_HOST 0x00000002 // Force USB0VBUS and USB0ID low -#define USB_GPCS_DEVMOD_DEV 0x00000003 // Force USB0VBUS and USB0ID high +#define USB_GPCS_DEVMOD_M 0x0007 // Device Mode +#define USB_GPCS_DEVMOD_OTG 0x0000 // Use USB0VBUS and USB0ID pin +#define USB_GPCS_DEVMOD_HOST 0x0002 // Force USB0VBUS and USB0ID low +#define USB_GPCS_DEVMOD_DEV 0x0003 // Force USB0VBUS and USB0ID high #define USB_GPCS_DEVMOD_HOSTVBUS \ - 0x00000004 // Use USB0VBUS and force USB0ID + 0x0004 // Use USB0VBUS and force USB0ID // low -#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005 // Use USB0VBUS and force USB0ID +#define USB_GPCS_DEVMOD_DEVVBUS 0x0005 // Use USB0VBUS and force USB0ID // high //***************************************************************************** @@ -2703,28 +2210,28 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_VDC register. // //***************************************************************************** -#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable +#define USB_VDC_VBDEN 0x0001 // VBUS Droop Enable //***************************************************************************** // // The following are defines for the bit fields in the USB_O_VDCRIS register. // //***************************************************************************** -#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status +#define USB_VDCRIS_VD 0x0001 // VBUS Droop Raw Interrupt Status //***************************************************************************** // // The following are defines for the bit fields in the USB_O_VDCIM register. // //***************************************************************************** -#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask +#define USB_VDCIM_VD 0x0001 // VBUS Droop Interrupt Mask //***************************************************************************** // // The following are defines for the bit fields in the USB_O_VDCISC register. // //***************************************************************************** -#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and +#define USB_VDCISC_VD 0x0001 // VBUS Droop Interrupt Status and // Clear //***************************************************************************** @@ -2732,17 +2239,17 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_PP register. // //***************************************************************************** -#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count -#define USB_PP_USB_M 0x000000C0 // USB Capability -#define USB_PP_USB_DEVICE 0x00000040 // DEVICE -#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST -#define USB_PP_USB_OTG 0x000000C0 // OTG -#define USB_PP_ULPI 0x00000020 // ULPI Present -#define USB_PP_PHY 0x00000010 // PHY Present -#define USB_PP_TYPE_M 0x0000000F // Controller Type -#define USB_PP_TYPE_0 0x00000000 // The first-generation USB +#define USB_PP_ECNT_M 0xFF00 // Endpoint Count +#define USB_PP_USB_M 0x00C0 // USB Capability +#define USB_PP_USB_DEVICE 0x0040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x0080 // HOST +#define USB_PP_USB_OTG 0x00C0 // OTG +#define USB_PP_ULPI 0x0020 // ULPI Present +#define USB_PP_PHY 0x0010 // PHY Present +#define USB_PP_TYPE_M 0x000F // Controller Type +#define USB_PP_TYPE_0 0x0000 // The first-generation USB // controller -#define USB_PP_TYPE_1 0x00000001 // The second-generation USB +#define USB_PP_TYPE_1 0x0001 // The second-generation USB // controller revision #define USB_PP_ECNT_S 8 @@ -2758,9 +2265,9 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // The following are defines for the bit fields in the USB_O_CC register. // //***************************************************************************** -#define USB_CC_CLKEN 0x00000200 // USB Clock Enable -#define USB_CC_CSD 0x00000100 // Clock Source/Direction -#define USB_CC_CLKDIV_M 0x0000000F // PLL Clock Divisor +#define USB_CC_CLKEN 0x0200 // USB Clock Enable +#define USB_CC_CSD 0x0100 // Clock Source/Direction +#define USB_CC_CLKDIV_M 0x000F // PLL Clock Divisor #define USB_CC_CLKDIV_S 0 #ifdef __cplusplus -- cgit v1.3.1 From e9109f36ba873062812b37f2c40fc88bbf48af67 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 17 Aug 2024 16:34:24 +0700 Subject: refactor fifo configure/setup for dynamic and static fifo --- src/portable/mentor/musb/dcd_musb.c | 86 +++++++++++++++++++++++++++++++---- src/portable/mentor/musb/musb_max32.h | 39 ++++++++-------- src/portable/mentor/musb/musb_ti.h | 3 ++ src/portable/mentor/musb/musb_type.h | 3 +- 4 files changed, 101 insertions(+), 30 deletions(-) (limited to 'src/portable') diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 36690c952..e9d907828 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -41,7 +41,6 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); // Following symbols must be defined by port header // - musb_dcd_int_enable/disable/clear/get_enable // - musb_dcd_int_handler_enter/exit -// - musb_dcd_setup_fifo: Configuration of the EP's FIFO #if defined(TUP_USBIP_MUSB_TI) #include "musb_ti.h" #elif defined(TUP_USBIP_MUSB_ADI) @@ -88,19 +87,78 @@ typedef struct *------------------------------------------------------------------*/ static dcd_data_t _dcd; +#if MUSB_CFG_DYNAMIC_FIFO + +// musb is configured to use dynamic FIFO sizing. +// FF Size is encodded: 1 << (fifo_size[3:0] + 3) = 8 << fifo_size[3:0] +// FF Address is 8*ff_addr[12:0] +// First 64 bytes are reserved for EP0 +static uint32_t alloced_fifo_bytes; + TU_ATTR_ALWAYS_INLINE static inline void fifo_reset(musb_regs_t* musb, unsigned epnum, unsigned dir_in) { - musb->index = epnum; const uint8_t is_rx = 1 - dir_in; - -#if MUSB_CFG_DYNAMIC_FIFO + musb->index = epnum; musb->fifo_size[is_rx] = 0; musb->fifo_addr[is_rx] = 0; -#elif defined(TUP_USBIP_MUSB_ADI) +} + +TU_ATTR_ALWAYS_INLINE static inline bool fifo_configure(musb_regs_t* musb, unsigned epnum, unsigned dir_in, unsigned mps) { + // ffsize is log2(mps) - 3 (round up) + uint8_t ffsize = 28 - tu_min8(28, __builtin_clz(mps)); + // round up to the next power of 2 + if ((8u << ffsize) < mps) { + ++ffsize; + mps = 8 << ffsize; + } + + TU_ASSERT(alloced_fifo_bytes + mps <= MUSB_CFG_DYNAMIC_FIFO_SIZE); + const uint8_t is_rx = 1 - dir_in; + musb->index = epnum; + musb->fifo_addr[is_rx] = alloced_fifo_bytes / 8; + musb->fifo_size[is_rx] = ffsize; + + alloced_fifo_bytes += mps; + + return true; +} + +#else +TU_ATTR_ALWAYS_INLINE static inline void fifo_reset(musb_regs_t* musb, unsigned epnum, unsigned dir_in) { + const uint8_t is_rx = 1 - dir_in; + musb->index = epnum; + + #if defined(TUP_USBIP_MUSB_ADI) // Analog have custom double buffered in csrh register, disable it musb->indexed_csr.maxp_csr[is_rx].csrh |= MUSB_CSRH_DISABLE_DOUBLE_PACKET(is_rx); + #else + // disable double bufeffered in extended register + #endif +} + +TU_ATTR_ALWAYS_INLINE static inline bool fifo_configure(musb_regs_t* musb, unsigned epnum, unsigned dir_in, unsigned mps) { + (void) mps; + const uint8_t is_rx = 1 - dir_in; + musb->index = epnum; + + uint8_t csrh = 0; + +#if defined(TUP_USBIP_MUSB_ADI) + csrh = MUSB_CSRH_DISABLE_DOUBLE_PACKET(is_rx); #endif + +#if MUSB_CFG_SHARED_FIFO + if (dir_in) { + csrh |= MUSB_CSRH_TX_MODE; + } +#endif + + musb->indexed_csr.maxp_csr[is_rx].csrh |= csrh; + + return true; } +#endif + static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; @@ -463,6 +521,11 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) // faddr = 0, index = 0, flushes all ep fifos, clears all ep csr, enabled all ep interrupts static void process_bus_reset(uint8_t rhport) { musb_regs_t* musb = MUSB_REGS(rhport); + +#if MUSB_CFG_DYNAMIC_FIFO + alloced_fifo_bytes = CFG_TUD_ENDPOINT0_SIZE; +#endif + /* When bmRequestType is REQUEST_TYPE_INVALID(0xFF), a control transfer state is SETUP or STATUS stage. */ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; _dcd.status_out = 0; @@ -594,8 +657,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) pipe->length = 0; pipe->remaining = 0; - musb_regs_t* musb_regs = MUSB_REGS(rhport); - musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn); + musb_regs_t* musb = MUSB_REGS(rhport); + musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn); const uint8_t is_rx = 1 - dir_in; ep_csr->maxp_csr[is_rx].maxp = mps; @@ -606,10 +669,10 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) csrl |= MUSB_CSRL_FLUSH_FIFO(is_rx); } ep_csr->maxp_csr[is_rx].csrl = csrl; - musb_regs->intren_ep[is_rx] |= TU_BIT(epn); + musb->intren_ep[is_rx] |= TU_BIT(epn); /* Setup FIFO */ - musb_dcd_setup_fifo(rhport, epn, dir_in, mps); + fifo_configure(musb, epn, dir_in, mps); return true; } @@ -619,6 +682,7 @@ void dcd_edpt_close_all(uint8_t rhport) musb_regs_t* musb = MUSB_REGS(rhport); unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); + musb->intr_txen = 1; /* Enable only EP0 */ musb->intr_rxen = 0; for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { @@ -640,13 +704,15 @@ void dcd_edpt_close_all(uint8_t rhport) fifo_reset(musb, i, 0); fifo_reset(musb, i, 1); - } + alloced_fifo_bytes = CFG_TUD_ENDPOINT0_SIZE; + if (ie) musb_dcd_int_enable(rhport); } void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { + // FIXME: we should implement iso_alloc() and iso_activate() unsigned const epn = tu_edpt_number(ep_addr); unsigned const dir_in = tu_edpt_dir(ep_addr); musb_regs_t* musb = MUSB_REGS(rhport); diff --git a/src/portable/mentor/musb/musb_max32.h b/src/portable/mentor/musb/musb_max32.h index 73f63ee2e..1320239c9 100644 --- a/src/portable/mentor/musb/musb_max32.h +++ b/src/portable/mentor/musb/musb_max32.h @@ -34,7 +34,8 @@ extern "C" { #include "mxc_device.h" #include "usbhs_regs.h" -#define MUSB_CFG_DYNAMIC_FIFO 0 +#define MUSB_CFG_SHARED_FIFO 1 // shared FIFO for TX and RX endpoints +#define MUSB_CFG_DYNAMIC_FIFO 0 // dynamic EP FIFO sizing const uintptr_t MUSB_BASES[] = { MXC_BASE_USBHS }; @@ -141,24 +142,24 @@ static inline void musb_dcd_phy_init(uint8_t rhport) { hs_phy->m31_phy_ponrst = 1; } -static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) { - (void) mps; - - //Most likely the caller has already grabbed the right register block. But - //as a precaution save and restore the register bank anyways - unsigned saved_index = musb_periph_inst[rhport]->index; - - musb_periph_inst[rhport]->index = epnum; - - //Disable double buffering - if (dir_in) { - musb_periph_inst[rhport]->incsru |= (MXC_F_USBHS_INCSRU_DPKTBUFDIS | MXC_F_USBHS_INCSRU_MODE); - } else { - musb_periph_inst[rhport]->outcsru |= (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS); - } - - musb_periph_inst[rhport]->index = saved_index; -} +// static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) { +// (void) mps; +// +// //Most likely the caller has already grabbed the right register block. But +// //as a precaution save and restore the register bank anyways +// unsigned saved_index = musb_periph_inst[rhport]->index; +// +// musb_periph_inst[rhport]->index = epnum; +// +// //Disable double buffering +// if (dir_in) { +// musb_periph_inst[rhport]->incsru |= (MXC_F_USBHS_INCSRU_DPKTBUFDIS | MXC_F_USBHS_INCSRU_MODE); +// } else { +// musb_periph_inst[rhport]->outcsru |= (MXC_F_USBHS_OUTCSRU_DPKTBUFDIS); +// } +// +// musb_periph_inst[rhport]->index = saved_index; +// } #endif // CFG_TUD_ENABLED diff --git a/src/portable/mentor/musb/musb_ti.h b/src/portable/mentor/musb/musb_ti.h index e43b3d3c0..7c15b61ad 100644 --- a/src/portable/mentor/musb/musb_ti.h +++ b/src/portable/mentor/musb/musb_ti.h @@ -42,6 +42,7 @@ #error "Unsupported MCUs" #endif +#define MUSB_CFG_SHARED_FIFO 0 #define MUSB_CFG_DYNAMIC_FIFO 1 #define MUSB_CFG_DYNAMIC_FIFO_SIZE 4096 @@ -91,6 +92,7 @@ static inline void musb_dcd_int_handler_exit(uint8_t rhport) { //Nothing to do for this part } +#if 0 typedef struct { uint_fast16_t beg; /* offset of including first element */ uint_fast16_t end; /* offset of excluding the last element */ @@ -224,6 +226,7 @@ static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned musb_periph_inst[rhport]->RXFIFOSZ = size_in_log2_minus3; } } +#endif #endif // CFG_TUD_ENABLED diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h index ee0187270..08f26edbd 100644 --- a/src/portable/mentor/musb/musb_type.h +++ b/src/portable/mentor/musb/musb_type.h @@ -261,7 +261,7 @@ typedef struct TU_ATTR_PACKED { //------------- Non-Indexed Endpoint CSRs -------------// // TI tm4c can access this directly, but should use indexed_csr for portability - musb_ep_csr_t ep_csr[16]; // 0x100-0x1FF: EP0-15 CSR + musb_ep_csr_t abs_csr[16]; // 0x100-0x1FF: EP0-15 CSR } musb_regs_t; TU_VERIFY_STATIC(sizeof(musb_regs_t) == 0x200, "size is not correct"); @@ -307,6 +307,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // 0x13, 0x17: TX/RX CSRH #define MUSB_CSRH_DISABLE_DOUBLE_PACKET(_rx) (1u << 1) +#define MUSB_CSRH_TX_MODE (1u << 5) // 1 = TX, 0 = RX. only relevant for SHARED FIFO //***************************************************************************** -- cgit v1.3.1 From 993473312b390b722d8693c23310b306997f8c2b Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 17 Aug 2024 17:09:38 +0700 Subject: minor update --- src/portable/mentor/musb/dcd_musb.c | 31 ++++++++++++++++++------------- src/portable/mentor/musb/musb_max32.h | 24 ++++-------------------- src/portable/mentor/musb/musb_ti.h | 5 ----- 3 files changed, 22 insertions(+), 38 deletions(-) (limited to 'src/portable') diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index e9d907828..3dcb9cdf1 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -29,6 +29,9 @@ #if CFG_TUD_ENABLED && defined(TUP_USBIP_MUSB) +#define MUSB_DEBUG 2 +#define MUSB_REGS(rhport) ((musb_regs_t*) MUSB_BASES[rhport]) + #if __GNUC__ > 8 && defined(__ARM_FEATURE_UNALIGNED) /* GCC warns that an address may be unaligned, even though * the target CPU has the capability for unaligned memory access. */ @@ -49,10 +52,6 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); #error "Unsupported MCU" #endif -#define MUSB_REGS(rhport) ((musb_regs_t*) MUSB_BASES[rhport]) - -#define MUSB_DEBUG 2 - /*------------------------------------------------------------------ * MACRO TYPEDEF CONSTANT ENUM DECLARATION *------------------------------------------------------------------*/ @@ -60,9 +59,9 @@ _Pragma("GCC diagnostic ignored \"-Waddress-of-packed-member\""); #define REQUEST_TYPE_INVALID (0xFFu) typedef union { - uint8_t u8; - uint16_t u16; - uint32_t u32; + volatile uint8_t u8; + volatile uint16_t u16; + volatile uint32_t u32; } hw_fifo_t; typedef struct TU_ATTR_PACKED @@ -223,11 +222,12 @@ static void pipe_read_write_packet_ff(tu_fifo_t *f, volatile void *fifo, unsigne static void process_setup_packet(uint8_t rhport) { musb_regs_t* musb_regs = MUSB_REGS(rhport); + + // Read setup packet uint32_t *p = (void*)&_dcd.setup_packet; volatile uint32_t *fifo_ptr = &musb_regs->fifo[0]; - - p[0] = *fifo_ptr; - p[1] = *fifo_ptr; + p[0] = *fifo_ptr; + p[1] = *fifo_ptr; _dcd.pipe0.buf = NULL; _dcd.pipe0.length = 0; @@ -407,6 +407,7 @@ static void process_ep0(uint8_t rhport) uint_fast8_t csrl = ep_csr->csr0l; // TU_LOG1(" EP0 ep_csr->csr0l = %x\r\n", csrl); + // 21.1.5: endpoint 0 service routine as peripheral if (csrl & USB_CSRL0_STALLED) { /* Returned STALL packet to HOST. */ @@ -705,7 +706,10 @@ void dcd_edpt_close_all(uint8_t rhport) fifo_reset(musb, i, 0); fifo_reset(musb, i, 1); } + +#if MUSB_CFG_DYNAMIC_FIFO alloced_fifo_bytes = CFG_TUD_ENDPOINT0_SIZE; +#endif if (ie) musb_dcd_int_enable(rhport); } @@ -822,10 +826,12 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) * ISR *-------------------------------------------------------------------*/ void dcd_int_handler(uint8_t rhport) { + musb_regs_t* musb_regs = MUSB_REGS(rhport); + const uint8_t saved_index = musb_regs->index; // save endpoint index + //Part specific ISR setup/entry musb_dcd_int_handler_enter(rhport); - musb_regs_t* musb_regs = MUSB_REGS(rhport); uint_fast8_t intr_usb = musb_regs->intr_usb; // a read will clear this interrupt status uint_fast8_t intr_tx = musb_regs->intr_tx; // a read will clear this interrupt status uint_fast8_t intr_rx = musb_regs->intr_rx; // a read will clear this interrupt status @@ -865,8 +871,7 @@ void dcd_int_handler(uint8_t rhport) { intr_rx &= ~TU_BIT(num); } - //Part specific ISR exit - musb_dcd_int_handler_exit(rhport); + musb_regs->index = saved_index; // restore endpoint index } #endif diff --git a/src/portable/mentor/musb/musb_max32.h b/src/portable/mentor/musb/musb_max32.h index 1320239c9..38e80f680 100644 --- a/src/portable/mentor/musb/musb_max32.h +++ b/src/portable/mentor/musb/musb_max32.h @@ -42,11 +42,6 @@ const uintptr_t MUSB_BASES[] = { MXC_BASE_USBHS }; #if CFG_TUD_ENABLED #define USBHS_M31_CLOCK_RECOVERY -// Mapping of peripheral instances to port. Currently just 1. -static mxc_usbhs_regs_t* const musb_periph_inst[] = { - MXC_USBHS -}; - // Mapping of IRQ numbers to port. Currently just 1. static const IRQn_Type musb_irqs[] = { USB_IRQn @@ -77,31 +72,21 @@ static inline void musb_dcd_int_clear(uint8_t rhport) { NVIC_ClearPendingIRQ(musb_irqs[rhport]); } -//Used to save and restore user's register map when interrupt occurs -static volatile unsigned isr_saved_index = 0; - static inline void musb_dcd_int_handler_enter(uint8_t rhport) { + mxc_usbhs_regs_t* hs_phy = MXC_USBHS; uint32_t mxm_int, mxm_int_en, mxm_is; - //save current register index - isr_saved_index = musb_periph_inst[rhport]->index; - //Handle PHY specific events - mxm_int = musb_periph_inst[rhport]->mxm_int; - mxm_int_en = musb_periph_inst[rhport]->mxm_int_en; + mxm_int = hs_phy->mxm_int; + mxm_int_en = hs_phy->mxm_int_en; mxm_is = mxm_int & mxm_int_en; - musb_periph_inst[rhport]->mxm_int = mxm_is; + hs_phy->mxm_int = mxm_is; if (mxm_is & MXC_F_USBHS_MXM_INT_NOVBUS) { dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); } } -static inline void musb_dcd_int_handler_exit(uint8_t rhport) { - //restore register index - musb_periph_inst[rhport]->index = isr_saved_index; -} - static inline void musb_dcd_phy_init(uint8_t rhport) { (void) rhport; mxc_usbhs_regs_t* hs_phy = MXC_USBHS; @@ -120,7 +105,6 @@ static inline void musb_dcd_phy_init(uint8_t rhport) { hs_phy->m31_phy_xcfgi_95_64 = 0x1 << (72 - 64); hs_phy->m31_phy_xcfgi_127_96 = 0; - #ifdef USBHS_M31_CLOCK_RECOVERY hs_phy->m31_phy_noncry_rstb = 1; hs_phy->m31_phy_noncry_en = 1; diff --git a/src/portable/mentor/musb/musb_ti.h b/src/portable/mentor/musb/musb_ti.h index 7c15b61ad..680bebde7 100644 --- a/src/portable/mentor/musb/musb_ti.h +++ b/src/portable/mentor/musb/musb_ti.h @@ -87,11 +87,6 @@ static inline void musb_dcd_int_handler_enter(uint8_t rhport) { //Nothing to do for this part } -static inline void musb_dcd_int_handler_exit(uint8_t rhport) { - (void)rhport; - //Nothing to do for this part -} - #if 0 typedef struct { uint_fast16_t beg; /* offset of including first element */ -- cgit v1.3.1 From 123830c1f00813d86d0405dc7a5624ccb1220a31 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 17 Aug 2024 19:06:19 +0700 Subject: remove unused register def --- src/portable/mentor/musb/musb_type.h | 1594 ++-------------------------------- 1 file changed, 59 insertions(+), 1535 deletions(-) (limited to 'src/portable') diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h index 08f26edbd..619eb0108 100644 --- a/src/portable/mentor/musb/musb_type.h +++ b/src/portable/mentor/musb/musb_type.h @@ -262,9 +262,37 @@ typedef struct TU_ATTR_PACKED { //------------- Non-Indexed Endpoint CSRs -------------// // TI tm4c can access this directly, but should use indexed_csr for portability musb_ep_csr_t abs_csr[16]; // 0x100-0x1FF: EP0-15 CSR + + //------------- DMA -------------// + __IO uint8_t dma_intr; // 0x200: DMA_INTR + __R uint8_t rsv_0x201_0x203[3]; // 0x201-0x203: Reserved + struct { + __IO uint16_t cntl; // 0x204: DMA_CNTL + __IO uint16_t rsv_0x206; // 0x206: Reserved + __IO uint32_t addr; // 0x208: DMA_ADDR + __IO uint32_t count; // 0x20C: DMA_COUNT + __IO uint32_t rsv_0x210; // 0x210: Reserved + }dma[8]; + __R uint32_t rsv_0x284_0x2FF[31]; // 0x284-0x2FF: Reserved + + //------------- Extended -------------// + __R uint32_t rsv_0x300; // 0x300: Reserved + struct { + __IO uint16_t count; // 0x304: REQ_PACKET_COUNT + __R uint16_t rsv_0x306; // 0x306: Reserved + }req_packet[15]; + + __IO uint16_t rx_doulbe_packet_disable; // 0x340: RX_DOUBLE_PACKET_DISABLE + __IO uint16_t tx_double_packet_disable; // 0x342: TX_DOUBLE_PACKET_DISABLE + + __IO uint16_t chirp_timeout; // 0x344: CHIRP_TIMEOUT + __IO uint16_t hs_to_utm; // 0x346: HS_TO_UTM delay + __IO uint16_t hs_timeout_adder; // 0x348: HS_TIMEOUT_ADDER + + __R uint8_t rsv_34A_34f[6]; // 0x34A-0x34F: Reserved } musb_regs_t; -TU_VERIFY_STATIC(sizeof(musb_regs_t) == 0x200, "size is not correct"); +TU_VERIFY_STATIC(sizeof(musb_regs_t) == 0x350, "size is not correct"); //--------------------------------------------------------------------+ // Helper @@ -566,14 +594,6 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ #define USB_CSRH0_DT 0x0002 // Data Toggle #define USB_CSRH0_FLUSH 0x0001 // Flush FIFO -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_COUNT0 register. -// -//***************************************************************************** -#define USB_COUNT0_COUNT_M 0x007F // FIFO Count -#define USB_COUNT0_COUNT_S 0 - //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TYPE0 register. @@ -592,14 +612,6 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ #define USB_NAKLMT_NAKLMT_M 0x001F // EP0 NAK Limit #define USB_NAKLMT_NAKLMT_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP1 register. -// -//***************************************************************************** -#define USB_TXMAXP1_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_TXMAXP1_MAXLOAD_S 0 - //***************************************************************************** // // The following are defines for the bit fields in the USB_O_TXCSRL1 register. @@ -630,14 +642,6 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ #define USB_TXCSRH1_DTWE 0x0002 // Data Toggle Write Enable #define USB_TXCSRH1_DT 0x0001 // Data Toggle -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP1 register. -// -//***************************************************************************** -#define USB_RXMAXP1_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_RXMAXP1_MAXLOAD_S 0 - //***************************************************************************** // // The following are defines for the bit fields in the USB_O_RXCSRL1 register. @@ -669,16 +673,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ #define USB_RXCSRH1_DMAMOD 0x0008 // DMA Request Mode #define USB_RXCSRH1_DTWE 0x0004 // Data Toggle Write Enable #define USB_RXCSRH1_DT 0x0002 // Data Toggle -#define USB_RXCSRH1_INCOMPRX 0x0001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. -// -//***************************************************************************** -#define USB_RXCOUNT1_COUNT_M 0x1FFF // Receive Packet Count -#define USB_RXCOUNT1_COUNT_S 0 +#define USB_RXCSRH1_INCOMPRX 0x0001 // Incomplete RX Transmission Status //***************************************************************************** // @@ -740,1537 +735,66 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_TXMAXP2 register. -// -//***************************************************************************** -#define USB_TXMAXP2_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_TXMAXP2_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL2 register. -// -//***************************************************************************** -#define USB_TXCSRL2_NAKTO 0x0080 // NAK Timeout -#define USB_TXCSRL2_CLRDT 0x0040 // Clear Data Toggle -#define USB_TXCSRL2_STALLED 0x0020 // Endpoint Stalled -#define USB_TXCSRL2_SETUP 0x0010 // Setup Packet -#define USB_TXCSRL2_STALL 0x0010 // Send STALL -#define USB_TXCSRL2_FLUSH 0x0008 // Flush FIFO -#define USB_TXCSRL2_ERROR 0x0004 // Error -#define USB_TXCSRL2_UNDRN 0x0004 // Underrun -#define USB_TXCSRL2_FIFONE 0x0002 // FIFO Not Empty -#define USB_TXCSRL2_TXRDY 0x0001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH2 register. -// -//***************************************************************************** -#define USB_TXCSRH2_AUTOSET 0x0080 // Auto Set -#define USB_TXCSRH2_ISO 0x0040 // Isochronous Transfers -#define USB_TXCSRH2_MODE 0x0020 // Mode -#define USB_TXCSRH2_DMAEN 0x0010 // DMA Request Enable -#define USB_TXCSRH2_FDT 0x0008 // Force Data Toggle -#define USB_TXCSRH2_DMAMOD 0x0004 // DMA Request Mode -#define USB_TXCSRH2_DTWE 0x0002 // Data Toggle Write Enable -#define USB_TXCSRH2_DT 0x0001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP2 register. -// -//***************************************************************************** -#define USB_RXMAXP2_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_RXMAXP2_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL2 register. -// -//***************************************************************************** -#define USB_RXCSRL2_CLRDT 0x0080 // Clear Data Toggle -#define USB_RXCSRL2_STALLED 0x0040 // Endpoint Stalled -#define USB_RXCSRL2_REQPKT 0x0020 // Request Packet -#define USB_RXCSRL2_STALL 0x0020 // Send STALL -#define USB_RXCSRL2_FLUSH 0x0010 // Flush FIFO -#define USB_RXCSRL2_DATAERR 0x0008 // Data Error -#define USB_RXCSRL2_NAKTO 0x0008 // NAK Timeout -#define USB_RXCSRL2_ERROR 0x0004 // Error -#define USB_RXCSRL2_OVER 0x0004 // Overrun -#define USB_RXCSRL2_FULL 0x0002 // FIFO Full -#define USB_RXCSRL2_RXRDY 0x0001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH2 register. -// -//***************************************************************************** -#define USB_RXCSRH2_AUTOCL 0x0080 // Auto Clear -#define USB_RXCSRH2_AUTORQ 0x0040 // Auto Request -#define USB_RXCSRH2_ISO 0x0040 // Isochronous Transfers -#define USB_RXCSRH2_DMAEN 0x0020 // DMA Request Enable -#define USB_RXCSRH2_DISNYET 0x0010 // Disable NYET -#define USB_RXCSRH2_PIDERR 0x0010 // PID Error -#define USB_RXCSRH2_DMAMOD 0x0008 // DMA Request Mode -#define USB_RXCSRH2_DTWE 0x0004 // Data Toggle Write Enable -#define USB_RXCSRH2_DT 0x0002 // Data Toggle -#define USB_RXCSRH2_INCOMPRX 0x0001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. -// -//***************************************************************************** -#define USB_RXCOUNT2_COUNT_M 0x1FFF // Receive Packet Count -#define USB_RXCOUNT2_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE2 register. -// -//***************************************************************************** -#define USB_TXTYPE2_SPEED_M 0x00C0 // Operating Speed -#define USB_TXTYPE2_SPEED_DFLT 0x0000 // Default -#define USB_TXTYPE2_SPEED_HIGH 0x0040 // High -#define USB_TXTYPE2_SPEED_FULL 0x0080 // Full -#define USB_TXTYPE2_SPEED_LOW 0x00C0 // Low -#define USB_TXTYPE2_PROTO_M 0x0030 // Protocol -#define USB_TXTYPE2_PROTO_CTRL 0x0000 // Control -#define USB_TXTYPE2_PROTO_ISOC 0x0010 // Isochronous -#define USB_TXTYPE2_PROTO_BULK 0x0020 // Bulk -#define USB_TXTYPE2_PROTO_INT 0x0030 // Interrupt -#define USB_TXTYPE2_TEP_M 0x000F // Target Endpoint Number -#define USB_TXTYPE2_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL2 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL2_TXPOLL_M 0x00FF // TX Polling -#define USB_TXINTERVAL2_NAKLMT_M 0x00FF // NAK Limit -#define USB_TXINTERVAL2_NAKLMT_S 0 -#define USB_TXINTERVAL2_TXPOLL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE2 register. -// -//***************************************************************************** -#define USB_RXTYPE2_SPEED_M 0x00C0 // Operating Speed -#define USB_RXTYPE2_SPEED_DFLT 0x0000 // Default -#define USB_RXTYPE2_SPEED_HIGH 0x0040 // High -#define USB_RXTYPE2_SPEED_FULL 0x0080 // Full -#define USB_RXTYPE2_SPEED_LOW 0x00C0 // Low -#define USB_RXTYPE2_PROTO_M 0x0030 // Protocol -#define USB_RXTYPE2_PROTO_CTRL 0x0000 // Control -#define USB_RXTYPE2_PROTO_ISOC 0x0010 // Isochronous -#define USB_RXTYPE2_PROTO_BULK 0x0020 // Bulk -#define USB_RXTYPE2_PROTO_INT 0x0030 // Interrupt -#define USB_RXTYPE2_TEP_M 0x000F // Target Endpoint Number -#define USB_RXTYPE2_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL2 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL2_TXPOLL_M 0x00FF // RX Polling -#define USB_RXINTERVAL2_NAKLMT_M 0x00FF // NAK Limit -#define USB_RXINTERVAL2_TXPOLL_S 0 -#define USB_RXINTERVAL2_NAKLMT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP3 register. -// -//***************************************************************************** -#define USB_TXMAXP3_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_TXMAXP3_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL3 register. -// -//***************************************************************************** -#define USB_TXCSRL3_NAKTO 0x0080 // NAK Timeout -#define USB_TXCSRL3_CLRDT 0x0040 // Clear Data Toggle -#define USB_TXCSRL3_STALLED 0x0020 // Endpoint Stalled -#define USB_TXCSRL3_SETUP 0x0010 // Setup Packet -#define USB_TXCSRL3_STALL 0x0010 // Send STALL -#define USB_TXCSRL3_FLUSH 0x0008 // Flush FIFO -#define USB_TXCSRL3_ERROR 0x0004 // Error -#define USB_TXCSRL3_UNDRN 0x0004 // Underrun -#define USB_TXCSRL3_FIFONE 0x0002 // FIFO Not Empty -#define USB_TXCSRL3_TXRDY 0x0001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH3 register. -// -//***************************************************************************** -#define USB_TXCSRH3_AUTOSET 0x0080 // Auto Set -#define USB_TXCSRH3_ISO 0x0040 // Isochronous Transfers -#define USB_TXCSRH3_MODE 0x0020 // Mode -#define USB_TXCSRH3_DMAEN 0x0010 // DMA Request Enable -#define USB_TXCSRH3_FDT 0x0008 // Force Data Toggle -#define USB_TXCSRH3_DMAMOD 0x0004 // DMA Request Mode -#define USB_TXCSRH3_DTWE 0x0002 // Data Toggle Write Enable -#define USB_TXCSRH3_DT 0x0001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP3 register. -// -//***************************************************************************** -#define USB_RXMAXP3_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_RXMAXP3_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL3 register. -// -//***************************************************************************** -#define USB_RXCSRL3_CLRDT 0x0080 // Clear Data Toggle -#define USB_RXCSRL3_STALLED 0x0040 // Endpoint Stalled -#define USB_RXCSRL3_STALL 0x0020 // Send STALL -#define USB_RXCSRL3_REQPKT 0x0020 // Request Packet -#define USB_RXCSRL3_FLUSH 0x0010 // Flush FIFO -#define USB_RXCSRL3_DATAERR 0x0008 // Data Error -#define USB_RXCSRL3_NAKTO 0x0008 // NAK Timeout -#define USB_RXCSRL3_ERROR 0x0004 // Error -#define USB_RXCSRL3_OVER 0x0004 // Overrun -#define USB_RXCSRL3_FULL 0x0002 // FIFO Full -#define USB_RXCSRL3_RXRDY 0x0001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH3 register. -// -//***************************************************************************** -#define USB_RXCSRH3_AUTOCL 0x0080 // Auto Clear -#define USB_RXCSRH3_AUTORQ 0x0040 // Auto Request -#define USB_RXCSRH3_ISO 0x0040 // Isochronous Transfers -#define USB_RXCSRH3_DMAEN 0x0020 // DMA Request Enable -#define USB_RXCSRH3_DISNYET 0x0010 // Disable NYET -#define USB_RXCSRH3_PIDERR 0x0010 // PID Error -#define USB_RXCSRH3_DMAMOD 0x0008 // DMA Request Mode -#define USB_RXCSRH3_DTWE 0x0004 // Data Toggle Write Enable -#define USB_RXCSRH3_DT 0x0002 // Data Toggle -#define USB_RXCSRH3_INCOMPRX 0x0001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. -// -//***************************************************************************** -#define USB_RXCOUNT3_COUNT_M 0x1FFF // Receive Packet Count -#define USB_RXCOUNT3_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE3 register. -// -//***************************************************************************** -#define USB_TXTYPE3_SPEED_M 0x00C0 // Operating Speed -#define USB_TXTYPE3_SPEED_DFLT 0x0000 // Default -#define USB_TXTYPE3_SPEED_HIGH 0x0040 // High -#define USB_TXTYPE3_SPEED_FULL 0x0080 // Full -#define USB_TXTYPE3_SPEED_LOW 0x00C0 // Low -#define USB_TXTYPE3_PROTO_M 0x0030 // Protocol -#define USB_TXTYPE3_PROTO_CTRL 0x0000 // Control -#define USB_TXTYPE3_PROTO_ISOC 0x0010 // Isochronous -#define USB_TXTYPE3_PROTO_BULK 0x0020 // Bulk -#define USB_TXTYPE3_PROTO_INT 0x0030 // Interrupt -#define USB_TXTYPE3_TEP_M 0x000F // Target Endpoint Number -#define USB_TXTYPE3_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL3 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL3_TXPOLL_M 0x00FF // TX Polling -#define USB_TXINTERVAL3_NAKLMT_M 0x00FF // NAK Limit -#define USB_TXINTERVAL3_TXPOLL_S 0 -#define USB_TXINTERVAL3_NAKLMT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE3 register. -// -//***************************************************************************** -#define USB_RXTYPE3_SPEED_M 0x00C0 // Operating Speed -#define USB_RXTYPE3_SPEED_DFLT 0x0000 // Default -#define USB_RXTYPE3_SPEED_HIGH 0x0040 // High -#define USB_RXTYPE3_SPEED_FULL 0x0080 // Full -#define USB_RXTYPE3_SPEED_LOW 0x00C0 // Low -#define USB_RXTYPE3_PROTO_M 0x0030 // Protocol -#define USB_RXTYPE3_PROTO_CTRL 0x0000 // Control -#define USB_RXTYPE3_PROTO_ISOC 0x0010 // Isochronous -#define USB_RXTYPE3_PROTO_BULK 0x0020 // Bulk -#define USB_RXTYPE3_PROTO_INT 0x0030 // Interrupt -#define USB_RXTYPE3_TEP_M 0x000F // Target Endpoint Number -#define USB_RXTYPE3_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL3 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL3_TXPOLL_M 0x00FF // RX Polling -#define USB_RXINTERVAL3_NAKLMT_M 0x00FF // NAK Limit -#define USB_RXINTERVAL3_TXPOLL_S 0 -#define USB_RXINTERVAL3_NAKLMT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP4 register. -// -//***************************************************************************** -#define USB_TXMAXP4_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_TXMAXP4_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL4 register. -// -//***************************************************************************** -#define USB_TXCSRL4_NAKTO 0x0080 // NAK Timeout -#define USB_TXCSRL4_CLRDT 0x0040 // Clear Data Toggle -#define USB_TXCSRL4_STALLED 0x0020 // Endpoint Stalled -#define USB_TXCSRL4_SETUP 0x0010 // Setup Packet -#define USB_TXCSRL4_STALL 0x0010 // Send STALL -#define USB_TXCSRL4_FLUSH 0x0008 // Flush FIFO -#define USB_TXCSRL4_ERROR 0x0004 // Error -#define USB_TXCSRL4_UNDRN 0x0004 // Underrun -#define USB_TXCSRL4_FIFONE 0x0002 // FIFO Not Empty -#define USB_TXCSRL4_TXRDY 0x0001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH4 register. -// -//***************************************************************************** -#define USB_TXCSRH4_AUTOSET 0x0080 // Auto Set -#define USB_TXCSRH4_ISO 0x0040 // Isochronous Transfers -#define USB_TXCSRH4_MODE 0x0020 // Mode -#define USB_TXCSRH4_DMAEN 0x0010 // DMA Request Enable -#define USB_TXCSRH4_FDT 0x0008 // Force Data Toggle -#define USB_TXCSRH4_DMAMOD 0x0004 // DMA Request Mode -#define USB_TXCSRH4_DTWE 0x0002 // Data Toggle Write Enable -#define USB_TXCSRH4_DT 0x0001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP4 register. -// -//***************************************************************************** -#define USB_RXMAXP4_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_RXMAXP4_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL4 register. -// -//***************************************************************************** -#define USB_RXCSRL4_CLRDT 0x0080 // Clear Data Toggle -#define USB_RXCSRL4_STALLED 0x0040 // Endpoint Stalled -#define USB_RXCSRL4_STALL 0x0020 // Send STALL -#define USB_RXCSRL4_REQPKT 0x0020 // Request Packet -#define USB_RXCSRL4_FLUSH 0x0010 // Flush FIFO -#define USB_RXCSRL4_NAKTO 0x0008 // NAK Timeout -#define USB_RXCSRL4_DATAERR 0x0008 // Data Error -#define USB_RXCSRL4_OVER 0x0004 // Overrun -#define USB_RXCSRL4_ERROR 0x0004 // Error -#define USB_RXCSRL4_FULL 0x0002 // FIFO Full -#define USB_RXCSRL4_RXRDY 0x0001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH4 register. -// -//***************************************************************************** -#define USB_RXCSRH4_AUTOCL 0x0080 // Auto Clear -#define USB_RXCSRH4_AUTORQ 0x0040 // Auto Request -#define USB_RXCSRH4_ISO 0x0040 // Isochronous Transfers -#define USB_RXCSRH4_DMAEN 0x0020 // DMA Request Enable -#define USB_RXCSRH4_DISNYET 0x0010 // Disable NYET -#define USB_RXCSRH4_PIDERR 0x0010 // PID Error -#define USB_RXCSRH4_DMAMOD 0x0008 // DMA Request Mode -#define USB_RXCSRH4_DTWE 0x0004 // Data Toggle Write Enable -#define USB_RXCSRH4_DT 0x0002 // Data Toggle -#define USB_RXCSRH4_INCOMPRX 0x0001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. -// -//***************************************************************************** -#define USB_RXCOUNT4_COUNT_M 0x1FFF // Receive Packet Count -#define USB_RXCOUNT4_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE4 register. -// -//***************************************************************************** -#define USB_TXTYPE4_SPEED_M 0x00C0 // Operating Speed -#define USB_TXTYPE4_SPEED_DFLT 0x0000 // Default -#define USB_TXTYPE4_SPEED_HIGH 0x0040 // High -#define USB_TXTYPE4_SPEED_FULL 0x0080 // Full -#define USB_TXTYPE4_SPEED_LOW 0x00C0 // Low -#define USB_TXTYPE4_PROTO_M 0x0030 // Protocol -#define USB_TXTYPE4_PROTO_CTRL 0x0000 // Control -#define USB_TXTYPE4_PROTO_ISOC 0x0010 // Isochronous -#define USB_TXTYPE4_PROTO_BULK 0x0020 // Bulk -#define USB_TXTYPE4_PROTO_INT 0x0030 // Interrupt -#define USB_TXTYPE4_TEP_M 0x000F // Target Endpoint Number -#define USB_TXTYPE4_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL4 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL4_TXPOLL_M 0x00FF // TX Polling -#define USB_TXINTERVAL4_NAKLMT_M 0x00FF // NAK Limit -#define USB_TXINTERVAL4_NAKLMT_S 0 -#define USB_TXINTERVAL4_TXPOLL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE4 register. -// -//***************************************************************************** -#define USB_RXTYPE4_SPEED_M 0x00C0 // Operating Speed -#define USB_RXTYPE4_SPEED_DFLT 0x0000 // Default -#define USB_RXTYPE4_SPEED_HIGH 0x0040 // High -#define USB_RXTYPE4_SPEED_FULL 0x0080 // Full -#define USB_RXTYPE4_SPEED_LOW 0x00C0 // Low -#define USB_RXTYPE4_PROTO_M 0x0030 // Protocol -#define USB_RXTYPE4_PROTO_CTRL 0x0000 // Control -#define USB_RXTYPE4_PROTO_ISOC 0x0010 // Isochronous -#define USB_RXTYPE4_PROTO_BULK 0x0020 // Bulk -#define USB_RXTYPE4_PROTO_INT 0x0030 // Interrupt -#define USB_RXTYPE4_TEP_M 0x000F // Target Endpoint Number -#define USB_RXTYPE4_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL4 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL4_TXPOLL_M 0x00FF // RX Polling -#define USB_RXINTERVAL4_NAKLMT_M 0x00FF // NAK Limit -#define USB_RXINTERVAL4_NAKLMT_S 0 -#define USB_RXINTERVAL4_TXPOLL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP5 register. -// -//***************************************************************************** -#define USB_TXMAXP5_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_TXMAXP5_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL5 register. -// -//***************************************************************************** -#define USB_TXCSRL5_NAKTO 0x0080 // NAK Timeout -#define USB_TXCSRL5_CLRDT 0x0040 // Clear Data Toggle -#define USB_TXCSRL5_STALLED 0x0020 // Endpoint Stalled -#define USB_TXCSRL5_SETUP 0x0010 // Setup Packet -#define USB_TXCSRL5_STALL 0x0010 // Send STALL -#define USB_TXCSRL5_FLUSH 0x0008 // Flush FIFO -#define USB_TXCSRL5_ERROR 0x0004 // Error -#define USB_TXCSRL5_UNDRN 0x0004 // Underrun -#define USB_TXCSRL5_FIFONE 0x0002 // FIFO Not Empty -#define USB_TXCSRL5_TXRDY 0x0001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH5 register. -// -//***************************************************************************** -#define USB_TXCSRH5_AUTOSET 0x0080 // Auto Set -#define USB_TXCSRH5_ISO 0x0040 // Isochronous Transfers -#define USB_TXCSRH5_MODE 0x0020 // Mode -#define USB_TXCSRH5_DMAEN 0x0010 // DMA Request Enable -#define USB_TXCSRH5_FDT 0x0008 // Force Data Toggle -#define USB_TXCSRH5_DMAMOD 0x0004 // DMA Request Mode -#define USB_TXCSRH5_DTWE 0x0002 // Data Toggle Write Enable -#define USB_TXCSRH5_DT 0x0001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP5 register. -// -//***************************************************************************** -#define USB_RXMAXP5_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_RXMAXP5_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL5 register. -// -//***************************************************************************** -#define USB_RXCSRL5_CLRDT 0x0080 // Clear Data Toggle -#define USB_RXCSRL5_STALLED 0x0040 // Endpoint Stalled -#define USB_RXCSRL5_STALL 0x0020 // Send STALL -#define USB_RXCSRL5_REQPKT 0x0020 // Request Packet -#define USB_RXCSRL5_FLUSH 0x0010 // Flush FIFO -#define USB_RXCSRL5_NAKTO 0x0008 // NAK Timeout -#define USB_RXCSRL5_DATAERR 0x0008 // Data Error -#define USB_RXCSRL5_ERROR 0x0004 // Error -#define USB_RXCSRL5_OVER 0x0004 // Overrun -#define USB_RXCSRL5_FULL 0x0002 // FIFO Full -#define USB_RXCSRL5_RXRDY 0x0001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH5 register. -// -//***************************************************************************** -#define USB_RXCSRH5_AUTOCL 0x0080 // Auto Clear -#define USB_RXCSRH5_AUTORQ 0x0040 // Auto Request -#define USB_RXCSRH5_ISO 0x0040 // Isochronous Transfers -#define USB_RXCSRH5_DMAEN 0x0020 // DMA Request Enable -#define USB_RXCSRH5_DISNYET 0x0010 // Disable NYET -#define USB_RXCSRH5_PIDERR 0x0010 // PID Error -#define USB_RXCSRH5_DMAMOD 0x0008 // DMA Request Mode -#define USB_RXCSRH5_DTWE 0x0004 // Data Toggle Write Enable -#define USB_RXCSRH5_DT 0x0002 // Data Toggle -#define USB_RXCSRH5_INCOMPRX 0x0001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// The following are defines for the bit fields in the USB_O_DMACTL0 register. // //***************************************************************************** -#define USB_RXCOUNT5_COUNT_M 0x1FFF // Receive Packet Count -#define USB_RXCOUNT5_COUNT_S 0 +#define USB_DMACTL0_BRSTM_M 0x0600 // Burst Mode +#define USB_DMACTL0_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define USB_DMACTL0_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define USB_DMACTL0_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL0_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL0_ERR 0x0100 // Bus Error Bit +#define USB_DMACTL0_EP_M 0x00F0 // Endpoint number +#define USB_DMACTL0_IE 0x0008 // DMA Interrupt Enable +#define USB_DMACTL0_MODE 0x0004 // DMA Transfer Mode +#define USB_DMACTL0_DIR 0x0002 // DMA Direction +#define USB_DMACTL0_ENABLE 0x0001 // DMA Transfer Enable +#define USB_DMACTL0_EP_S 4 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_TXTYPE5 register. +// The following are defines for the bit fields in the USB_O_DMAADDR0 register. // //***************************************************************************** -#define USB_TXTYPE5_SPEED_M 0x00C0 // Operating Speed -#define USB_TXTYPE5_SPEED_DFLT 0x0000 // Default -#define USB_TXTYPE5_SPEED_HIGH 0x0040 // High -#define USB_TXTYPE5_SPEED_FULL 0x0080 // Full -#define USB_TXTYPE5_SPEED_LOW 0x00C0 // Low -#define USB_TXTYPE5_PROTO_M 0x0030 // Protocol -#define USB_TXTYPE5_PROTO_CTRL 0x0000 // Control -#define USB_TXTYPE5_PROTO_ISOC 0x0010 // Isochronous -#define USB_TXTYPE5_PROTO_BULK 0x0020 // Bulk -#define USB_TXTYPE5_PROTO_INT 0x0030 // Interrupt -#define USB_TXTYPE5_TEP_M 0x000F // Target Endpoint Number -#define USB_TXTYPE5_TEP_S 0 +#define USB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR0_ADDR_S 2 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_TXINTERVAL5 +// The following are defines for the bit fields in the USB_O_DMACOUNT0 // register. // //***************************************************************************** -#define USB_TXINTERVAL5_TXPOLL_M 0x00FF // TX Polling -#define USB_TXINTERVAL5_NAKLMT_M 0x00FF // NAK Limit -#define USB_TXINTERVAL5_NAKLMT_S 0 -#define USB_TXINTERVAL5_TXPOLL_S 0 +#define USB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT0_COUNT_S 2 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_RXTYPE5 register. +// The following are defines for the bit fields in the USB_O_CTO register. // //***************************************************************************** -#define USB_RXTYPE5_SPEED_M 0x00C0 // Operating Speed -#define USB_RXTYPE5_SPEED_DFLT 0x0000 // Default -#define USB_RXTYPE5_SPEED_HIGH 0x0040 // High -#define USB_RXTYPE5_SPEED_FULL 0x0080 // Full -#define USB_RXTYPE5_SPEED_LOW 0x00C0 // Low -#define USB_RXTYPE5_PROTO_M 0x0030 // Protocol -#define USB_RXTYPE5_PROTO_CTRL 0x0000 // Control -#define USB_RXTYPE5_PROTO_ISOC 0x0010 // Isochronous -#define USB_RXTYPE5_PROTO_BULK 0x0020 // Bulk -#define USB_RXTYPE5_PROTO_INT 0x0030 // Interrupt -#define USB_RXTYPE5_TEP_M 0x000F // Target Endpoint Number -#define USB_RXTYPE5_TEP_S 0 +#define USB_CTO_CCTV_M 0xFFFF // Configurable Chirp Timeout Value +#define USB_CTO_CCTV_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_RXINTERVAL5 -// register. +// The following are defines for the bit fields in the USB_O_HHSRTN register. // //***************************************************************************** -#define USB_RXINTERVAL5_TXPOLL_M 0x00FF // RX Polling -#define USB_RXINTERVAL5_NAKLMT_M 0x00FF // NAK Limit -#define USB_RXINTERVAL5_TXPOLL_S 0 -#define USB_RXINTERVAL5_NAKLMT_S 0 +#define USB_HHSRTN_HHSRTN_M 0xFFFF // HIgh Speed to UTM Operating + // Delay +#define USB_HHSRTN_HHSRTN_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_TXMAXP6 register. -// -//***************************************************************************** -#define USB_TXMAXP6_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_TXMAXP6_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL6 register. -// -//***************************************************************************** -#define USB_TXCSRL6_NAKTO 0x0080 // NAK Timeout -#define USB_TXCSRL6_CLRDT 0x0040 // Clear Data Toggle -#define USB_TXCSRL6_STALLED 0x0020 // Endpoint Stalled -#define USB_TXCSRL6_STALL 0x0010 // Send STALL -#define USB_TXCSRL6_SETUP 0x0010 // Setup Packet -#define USB_TXCSRL6_FLUSH 0x0008 // Flush FIFO -#define USB_TXCSRL6_ERROR 0x0004 // Error -#define USB_TXCSRL6_UNDRN 0x0004 // Underrun -#define USB_TXCSRL6_FIFONE 0x0002 // FIFO Not Empty -#define USB_TXCSRL6_TXRDY 0x0001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH6 register. -// -//***************************************************************************** -#define USB_TXCSRH6_AUTOSET 0x0080 // Auto Set -#define USB_TXCSRH6_ISO 0x0040 // Isochronous Transfers -#define USB_TXCSRH6_MODE 0x0020 // Mode -#define USB_TXCSRH6_DMAEN 0x0010 // DMA Request Enable -#define USB_TXCSRH6_FDT 0x0008 // Force Data Toggle -#define USB_TXCSRH6_DMAMOD 0x0004 // DMA Request Mode -#define USB_TXCSRH6_DTWE 0x0002 // Data Toggle Write Enable -#define USB_TXCSRH6_DT 0x0001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP6 register. -// -//***************************************************************************** -#define USB_RXMAXP6_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_RXMAXP6_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL6 register. -// -//***************************************************************************** -#define USB_RXCSRL6_CLRDT 0x0080 // Clear Data Toggle -#define USB_RXCSRL6_STALLED 0x0040 // Endpoint Stalled -#define USB_RXCSRL6_REQPKT 0x0020 // Request Packet -#define USB_RXCSRL6_STALL 0x0020 // Send STALL -#define USB_RXCSRL6_FLUSH 0x0010 // Flush FIFO -#define USB_RXCSRL6_NAKTO 0x0008 // NAK Timeout -#define USB_RXCSRL6_DATAERR 0x0008 // Data Error -#define USB_RXCSRL6_ERROR 0x0004 // Error -#define USB_RXCSRL6_OVER 0x0004 // Overrun -#define USB_RXCSRL6_FULL 0x0002 // FIFO Full -#define USB_RXCSRL6_RXRDY 0x0001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH6 register. -// -//***************************************************************************** -#define USB_RXCSRH6_AUTOCL 0x0080 // Auto Clear -#define USB_RXCSRH6_AUTORQ 0x0040 // Auto Request -#define USB_RXCSRH6_ISO 0x0040 // Isochronous Transfers -#define USB_RXCSRH6_DMAEN 0x0020 // DMA Request Enable -#define USB_RXCSRH6_DISNYET 0x0010 // Disable NYET -#define USB_RXCSRH6_PIDERR 0x0010 // PID Error -#define USB_RXCSRH6_DMAMOD 0x0008 // DMA Request Mode -#define USB_RXCSRH6_DTWE 0x0004 // Data Toggle Write Enable -#define USB_RXCSRH6_DT 0x0002 // Data Toggle -#define USB_RXCSRH6_INCOMPRX 0x0001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. -// -//***************************************************************************** -#define USB_RXCOUNT6_COUNT_M 0x1FFF // Receive Packet Count -#define USB_RXCOUNT6_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE6 register. -// -//***************************************************************************** -#define USB_TXTYPE6_SPEED_M 0x00C0 // Operating Speed -#define USB_TXTYPE6_SPEED_DFLT 0x0000 // Default -#define USB_TXTYPE6_SPEED_HIGH 0x0040 // High -#define USB_TXTYPE6_SPEED_FULL 0x0080 // Full -#define USB_TXTYPE6_SPEED_LOW 0x00C0 // Low -#define USB_TXTYPE6_PROTO_M 0x0030 // Protocol -#define USB_TXTYPE6_PROTO_CTRL 0x0000 // Control -#define USB_TXTYPE6_PROTO_ISOC 0x0010 // Isochronous -#define USB_TXTYPE6_PROTO_BULK 0x0020 // Bulk -#define USB_TXTYPE6_PROTO_INT 0x0030 // Interrupt -#define USB_TXTYPE6_TEP_M 0x000F // Target Endpoint Number -#define USB_TXTYPE6_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL6 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL6_TXPOLL_M 0x00FF // TX Polling -#define USB_TXINTERVAL6_NAKLMT_M 0x00FF // NAK Limit -#define USB_TXINTERVAL6_TXPOLL_S 0 -#define USB_TXINTERVAL6_NAKLMT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE6 register. -// -//***************************************************************************** -#define USB_RXTYPE6_SPEED_M 0x00C0 // Operating Speed -#define USB_RXTYPE6_SPEED_DFLT 0x0000 // Default -#define USB_RXTYPE6_SPEED_HIGH 0x0040 // High -#define USB_RXTYPE6_SPEED_FULL 0x0080 // Full -#define USB_RXTYPE6_SPEED_LOW 0x00C0 // Low -#define USB_RXTYPE6_PROTO_M 0x0030 // Protocol -#define USB_RXTYPE6_PROTO_CTRL 0x0000 // Control -#define USB_RXTYPE6_PROTO_ISOC 0x0010 // Isochronous -#define USB_RXTYPE6_PROTO_BULK 0x0020 // Bulk -#define USB_RXTYPE6_PROTO_INT 0x0030 // Interrupt -#define USB_RXTYPE6_TEP_M 0x000F // Target Endpoint Number -#define USB_RXTYPE6_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL6 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL6_TXPOLL_M 0x00FF // RX Polling -#define USB_RXINTERVAL6_NAKLMT_M 0x00FF // NAK Limit -#define USB_RXINTERVAL6_NAKLMT_S 0 -#define USB_RXINTERVAL6_TXPOLL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXMAXP7 register. -// -//***************************************************************************** -#define USB_TXMAXP7_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_TXMAXP7_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRL7 register. -// -//***************************************************************************** -#define USB_TXCSRL7_NAKTO 0x0080 // NAK Timeout -#define USB_TXCSRL7_CLRDT 0x0040 // Clear Data Toggle -#define USB_TXCSRL7_STALLED 0x0020 // Endpoint Stalled -#define USB_TXCSRL7_STALL 0x0010 // Send STALL -#define USB_TXCSRL7_SETUP 0x0010 // Setup Packet -#define USB_TXCSRL7_FLUSH 0x0008 // Flush FIFO -#define USB_TXCSRL7_ERROR 0x0004 // Error -#define USB_TXCSRL7_UNDRN 0x0004 // Underrun -#define USB_TXCSRL7_FIFONE 0x0002 // FIFO Not Empty -#define USB_TXCSRL7_TXRDY 0x0001 // Transmit Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXCSRH7 register. -// -//***************************************************************************** -#define USB_TXCSRH7_AUTOSET 0x0080 // Auto Set -#define USB_TXCSRH7_ISO 0x0040 // Isochronous Transfers -#define USB_TXCSRH7_MODE 0x0020 // Mode -#define USB_TXCSRH7_DMAEN 0x0010 // DMA Request Enable -#define USB_TXCSRH7_FDT 0x0008 // Force Data Toggle -#define USB_TXCSRH7_DMAMOD 0x0004 // DMA Request Mode -#define USB_TXCSRH7_DTWE 0x0002 // Data Toggle Write Enable -#define USB_TXCSRH7_DT 0x0001 // Data Toggle - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXMAXP7 register. -// -//***************************************************************************** -#define USB_RXMAXP7_MAXLOAD_M 0x07FF // Maximum Payload -#define USB_RXMAXP7_MAXLOAD_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRL7 register. -// -//***************************************************************************** -#define USB_RXCSRL7_CLRDT 0x0080 // Clear Data Toggle -#define USB_RXCSRL7_STALLED 0x0040 // Endpoint Stalled -#define USB_RXCSRL7_REQPKT 0x0020 // Request Packet -#define USB_RXCSRL7_STALL 0x0020 // Send STALL -#define USB_RXCSRL7_FLUSH 0x0010 // Flush FIFO -#define USB_RXCSRL7_DATAERR 0x0008 // Data Error -#define USB_RXCSRL7_NAKTO 0x0008 // NAK Timeout -#define USB_RXCSRL7_ERROR 0x0004 // Error -#define USB_RXCSRL7_OVER 0x0004 // Overrun -#define USB_RXCSRL7_FULL 0x0002 // FIFO Full -#define USB_RXCSRL7_RXRDY 0x0001 // Receive Packet Ready - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCSRH7 register. -// -//***************************************************************************** -#define USB_RXCSRH7_AUTOCL 0x0080 // Auto Clear -#define USB_RXCSRH7_ISO 0x0040 // Isochronous Transfers -#define USB_RXCSRH7_AUTORQ 0x0040 // Auto Request -#define USB_RXCSRH7_DMAEN 0x0020 // DMA Request Enable -#define USB_RXCSRH7_PIDERR 0x0010 // PID Error -#define USB_RXCSRH7_DISNYET 0x0010 // Disable NYET -#define USB_RXCSRH7_DMAMOD 0x0008 // DMA Request Mode -#define USB_RXCSRH7_DTWE 0x0004 // Data Toggle Write Enable -#define USB_RXCSRH7_DT 0x0002 // Data Toggle -#define USB_RXCSRH7_INCOMPRX 0x0001 // Incomplete RX Transmission - // Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. -// -//***************************************************************************** -#define USB_RXCOUNT7_COUNT_M 0x1FFF // Receive Packet Count -#define USB_RXCOUNT7_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXTYPE7 register. -// -//***************************************************************************** -#define USB_TXTYPE7_SPEED_M 0x00C0 // Operating Speed -#define USB_TXTYPE7_SPEED_DFLT 0x0000 // Default -#define USB_TXTYPE7_SPEED_HIGH 0x0040 // High -#define USB_TXTYPE7_SPEED_FULL 0x0080 // Full -#define USB_TXTYPE7_SPEED_LOW 0x00C0 // Low -#define USB_TXTYPE7_PROTO_M 0x0030 // Protocol -#define USB_TXTYPE7_PROTO_CTRL 0x0000 // Control -#define USB_TXTYPE7_PROTO_ISOC 0x0010 // Isochronous -#define USB_TXTYPE7_PROTO_BULK 0x0020 // Bulk -#define USB_TXTYPE7_PROTO_INT 0x0030 // Interrupt -#define USB_TXTYPE7_TEP_M 0x000F // Target Endpoint Number -#define USB_TXTYPE7_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXINTERVAL7 -// register. -// -//***************************************************************************** -#define USB_TXINTERVAL7_TXPOLL_M 0x00FF // TX Polling -#define USB_TXINTERVAL7_NAKLMT_M 0x00FF // NAK Limit -#define USB_TXINTERVAL7_NAKLMT_S 0 -#define USB_TXINTERVAL7_TXPOLL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXTYPE7 register. -// -//***************************************************************************** -#define USB_RXTYPE7_SPEED_M 0x00C0 // Operating Speed -#define USB_RXTYPE7_SPEED_DFLT 0x0000 // Default -#define USB_RXTYPE7_SPEED_HIGH 0x0040 // High -#define USB_RXTYPE7_SPEED_FULL 0x0080 // Full -#define USB_RXTYPE7_SPEED_LOW 0x00C0 // Low -#define USB_RXTYPE7_PROTO_M 0x0030 // Protocol -#define USB_RXTYPE7_PROTO_CTRL 0x0000 // Control -#define USB_RXTYPE7_PROTO_ISOC 0x0010 // Isochronous -#define USB_RXTYPE7_PROTO_BULK 0x0020 // Bulk -#define USB_RXTYPE7_PROTO_INT 0x0030 // Interrupt -#define USB_RXTYPE7_TEP_M 0x000F // Target Endpoint Number -#define USB_RXTYPE7_TEP_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXINTERVAL7 -// register. -// -//***************************************************************************** -#define USB_RXINTERVAL7_TXPOLL_M 0x00FF // RX Polling -#define USB_RXINTERVAL7_NAKLMT_M 0x00FF // NAK Limit -#define USB_RXINTERVAL7_NAKLMT_S 0 -#define USB_RXINTERVAL7_TXPOLL_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAINTR register. -// -//***************************************************************************** -#define USB_DMAINTR_CH7 0x0080 // Channel 7 DMA Interrupt -#define USB_DMAINTR_CH6 0x0040 // Channel 6 DMA Interrupt -#define USB_DMAINTR_CH5 0x0020 // Channel 5 DMA Interrupt -#define USB_DMAINTR_CH4 0x0010 // Channel 4 DMA Interrupt -#define USB_DMAINTR_CH3 0x0008 // Channel 3 DMA Interrupt -#define USB_DMAINTR_CH2 0x0004 // Channel 2 DMA Interrupt -#define USB_DMAINTR_CH1 0x0002 // Channel 1 DMA Interrupt -#define USB_DMAINTR_CH0 0x0001 // Channel 0 DMA Interrupt - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL0 register. -// -//***************************************************************************** -#define USB_DMACTL0_BRSTM_M 0x0600 // Burst Mode -#define USB_DMACTL0_BRSTM_ANY 0x0000 // Bursts of unspecified length -#define USB_DMACTL0_BRSTM_INC4 0x0200 // INCR4 or unspecified length -#define USB_DMACTL0_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL0_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL0_ERR 0x0100 // Bus Error Bit -#define USB_DMACTL0_EP_M 0x00F0 // Endpoint number -#define USB_DMACTL0_IE 0x0008 // DMA Interrupt Enable -#define USB_DMACTL0_MODE 0x0004 // DMA Transfer Mode -#define USB_DMACTL0_DIR 0x0002 // DMA Direction -#define USB_DMACTL0_ENABLE 0x0001 // DMA Transfer Enable -#define USB_DMACTL0_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR0 register. -// -//***************************************************************************** -#define USB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR0_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT0 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT0_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL1 register. -// -//***************************************************************************** -#define USB_DMACTL1_BRSTM_M 0x0600 // Burst Mode -#define USB_DMACTL1_BRSTM_ANY 0x0000 // Bursts of unspecified length -#define USB_DMACTL1_BRSTM_INC4 0x0200 // INCR4 or unspecified length -#define USB_DMACTL1_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL1_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL1_ERR 0x0100 // Bus Error Bit -#define USB_DMACTL1_EP_M 0x00F0 // Endpoint number -#define USB_DMACTL1_IE 0x0008 // DMA Interrupt Enable -#define USB_DMACTL1_MODE 0x0004 // DMA Transfer Mode -#define USB_DMACTL1_DIR 0x0002 // DMA Direction -#define USB_DMACTL1_ENABLE 0x0001 // DMA Transfer Enable -#define USB_DMACTL1_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR1 register. -// -//***************************************************************************** -#define USB_DMAADDR1_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR1_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT1 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT1_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT1_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL2 register. -// -//***************************************************************************** -#define USB_DMACTL2_BRSTM_M 0x0600 // Burst Mode -#define USB_DMACTL2_BRSTM_ANY 0x0000 // Bursts of unspecified length -#define USB_DMACTL2_BRSTM_INC4 0x0200 // INCR4 or unspecified length -#define USB_DMACTL2_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL2_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL2_ERR 0x0100 // Bus Error Bit -#define USB_DMACTL2_EP_M 0x00F0 // Endpoint number -#define USB_DMACTL2_IE 0x0008 // DMA Interrupt Enable -#define USB_DMACTL2_MODE 0x0004 // DMA Transfer Mode -#define USB_DMACTL2_DIR 0x0002 // DMA Direction -#define USB_DMACTL2_ENABLE 0x0001 // DMA Transfer Enable -#define USB_DMACTL2_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR2 register. -// -//***************************************************************************** -#define USB_DMAADDR2_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR2_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT2 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT2_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT2_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL3 register. -// -//***************************************************************************** -#define USB_DMACTL3_BRSTM_M 0x0600 // Burst Mode -#define USB_DMACTL3_BRSTM_ANY 0x0000 // Bursts of unspecified length -#define USB_DMACTL3_BRSTM_INC4 0x0200 // INCR4 or unspecified length -#define USB_DMACTL3_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL3_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL3_ERR 0x0100 // Bus Error Bit -#define USB_DMACTL3_EP_M 0x00F0 // Endpoint number -#define USB_DMACTL3_IE 0x0008 // DMA Interrupt Enable -#define USB_DMACTL3_MODE 0x0004 // DMA Transfer Mode -#define USB_DMACTL3_DIR 0x0002 // DMA Direction -#define USB_DMACTL3_ENABLE 0x0001 // DMA Transfer Enable -#define USB_DMACTL3_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR3 register. -// -//***************************************************************************** -#define USB_DMAADDR3_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR3_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT3 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT3_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT3_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL4 register. -// -//***************************************************************************** -#define USB_DMACTL4_BRSTM_M 0x0600 // Burst Mode -#define USB_DMACTL4_BRSTM_ANY 0x0000 // Bursts of unspecified length -#define USB_DMACTL4_BRSTM_INC4 0x0200 // INCR4 or unspecified length -#define USB_DMACTL4_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL4_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL4_ERR 0x0100 // Bus Error Bit -#define USB_DMACTL4_EP_M 0x00F0 // Endpoint number -#define USB_DMACTL4_IE 0x0008 // DMA Interrupt Enable -#define USB_DMACTL4_MODE 0x0004 // DMA Transfer Mode -#define USB_DMACTL4_DIR 0x0002 // DMA Direction -#define USB_DMACTL4_ENABLE 0x0001 // DMA Transfer Enable -#define USB_DMACTL4_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR4 register. -// -//***************************************************************************** -#define USB_DMAADDR4_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR4_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT4 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT4_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT4_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL5 register. -// -//***************************************************************************** -#define USB_DMACTL5_BRSTM_M 0x0600 // Burst Mode -#define USB_DMACTL5_BRSTM_ANY 0x0000 // Bursts of unspecified length -#define USB_DMACTL5_BRSTM_INC4 0x0200 // INCR4 or unspecified length -#define USB_DMACTL5_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL5_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL5_ERR 0x0100 // Bus Error Bit -#define USB_DMACTL5_EP_M 0x00F0 // Endpoint number -#define USB_DMACTL5_IE 0x0008 // DMA Interrupt Enable -#define USB_DMACTL5_MODE 0x0004 // DMA Transfer Mode -#define USB_DMACTL5_DIR 0x0002 // DMA Direction -#define USB_DMACTL5_ENABLE 0x0001 // DMA Transfer Enable -#define USB_DMACTL5_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR5 register. -// -//***************************************************************************** -#define USB_DMAADDR5_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR5_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT5 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT5_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT5_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL6 register. -// -//***************************************************************************** -#define USB_DMACTL6_BRSTM_M 0x0600 // Burst Mode -#define USB_DMACTL6_BRSTM_ANY 0x0000 // Bursts of unspecified length -#define USB_DMACTL6_BRSTM_INC4 0x0200 // INCR4 or unspecified length -#define USB_DMACTL6_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL6_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL6_ERR 0x0100 // Bus Error Bit -#define USB_DMACTL6_EP_M 0x00F0 // Endpoint number -#define USB_DMACTL6_IE 0x0008 // DMA Interrupt Enable -#define USB_DMACTL6_MODE 0x0004 // DMA Transfer Mode -#define USB_DMACTL6_DIR 0x0002 // DMA Direction -#define USB_DMACTL6_ENABLE 0x0001 // DMA Transfer Enable -#define USB_DMACTL6_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR6 register. -// -//***************************************************************************** -#define USB_DMAADDR6_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR6_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT6 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT6_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT6_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACTL7 register. -// -//***************************************************************************** -#define USB_DMACTL7_BRSTM_M 0x0600 // Burst Mode -#define USB_DMACTL7_BRSTM_ANY 0x0000 // Bursts of unspecified length -#define USB_DMACTL7_BRSTM_INC4 0x0200 // INCR4 or unspecified length -#define USB_DMACTL7_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified - // length -#define USB_DMACTL7_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or - // unspecified length -#define USB_DMACTL7_ERR 0x0100 // Bus Error Bit -#define USB_DMACTL7_EP_M 0x00F0 // Endpoint number -#define USB_DMACTL7_IE 0x0008 // DMA Interrupt Enable -#define USB_DMACTL7_MODE 0x0004 // DMA Transfer Mode -#define USB_DMACTL7_DIR 0x0002 // DMA Direction -#define USB_DMACTL7_ENABLE 0x0001 // DMA Transfer Enable -#define USB_DMACTL7_EP_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMAADDR7 register. -// -//***************************************************************************** -#define USB_DMAADDR7_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR7_ADDR_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DMACOUNT7 -// register. -// -//***************************************************************************** -#define USB_DMACOUNT7_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT7_COUNT_S 2 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT1_M 0xFFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT1_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT2_M 0xFFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT2_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT3_M 0xFFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT3_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT4_COUNT_M 0xFFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT4_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT5_COUNT_M 0xFFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT5_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT6_COUNT_M 0xFFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT6_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 -// register. -// -//***************************************************************************** -#define USB_RQPKTCOUNT7_COUNT_M 0xFFFF // Block Transfer Packet Count -#define USB_RQPKTCOUNT7_COUNT_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS -// register. -// -//***************************************************************************** -#define USB_RXDPKTBUFDIS_EP7 0x0080 // EP7 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP6 0x0040 // EP6 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP5 0x0020 // EP5 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP4 0x0010 // EP4 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP3 0x0008 // EP3 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP2 0x0004 // EP2 RX Double-Packet Buffer - // Disable -#define USB_RXDPKTBUFDIS_EP1 0x0002 // EP1 RX Double-Packet Buffer - // Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS -// register. -// -//***************************************************************************** -#define USB_TXDPKTBUFDIS_EP7 0x0080 // EP7 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP6 0x0040 // EP6 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP5 0x0020 // EP5 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP4 0x0010 // EP4 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP3 0x0008 // EP3 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP2 0x0004 // EP2 TX Double-Packet Buffer - // Disable -#define USB_TXDPKTBUFDIS_EP1 0x0002 // EP1 TX Double-Packet Buffer - // Disable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CTO register. -// -//***************************************************************************** -#define USB_CTO_CCTV_M 0xFFFF // Configurable Chirp Timeout Value -#define USB_CTO_CCTV_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_HHSRTN register. -// -//***************************************************************************** -#define USB_HHSRTN_HHSRTN_M 0xFFFF // HIgh Speed to UTM Operating - // Delay -#define USB_HHSRTN_HHSRTN_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_HSBT register. +// The following are defines for the bit fields in the USB_O_HSBT register. // //***************************************************************************** #define USB_HSBT_HSBT_M 0x000F // High Speed Timeout Adder #define USB_HSBT_HSBT_S 0 -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMATTR register. -// -//***************************************************************************** -#define USB_LPMATTR_ENDPT_M 0xF000 // Endpoint -#define USB_LPMATTR_RMTWAK 0x0100 // Remote Wake -#define USB_LPMATTR_HIRD_M 0x00F0 // Host Initiated Resume Duration -#define USB_LPMATTR_LS_M 0x000F // Link State -#define USB_LPMATTR_LS_L1 0x0001 // Sleep State (L1) -#define USB_LPMATTR_ENDPT_S 12 -#define USB_LPMATTR_HIRD_S 4 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMCNTRL register. -// -//***************************************************************************** -#define USB_LPMCNTRL_NAK 0x0010 // LPM NAK -#define USB_LPMCNTRL_EN_M 0x000C // LPM Enable -#define USB_LPMCNTRL_EN_NONE 0x0000 // LPM and Extended transactions - // are not supported. In this case, - // the USB does not respond to LPM - // transactions and LPM - // transactions cause a timeout -#define USB_LPMCNTRL_EN_EXT 0x0004 // LPM is not supported but - // extended transactions are - // supported. In this case, the USB - // does respond to an LPM - // transaction with a STALL -#define USB_LPMCNTRL_EN_LPMEXT 0x000C // The USB supports LPM extended - // transactions. In this case, the - // USB responds with a NYET or an - // ACK as determined by the value - // of TXLPM and other conditions -#define USB_LPMCNTRL_RES 0x0002 // LPM Resume -#define USB_LPMCNTRL_TXLPM 0x0001 // Transmit LPM Transaction Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMIM register. -// -//***************************************************************************** -#define USB_LPMIM_ERR 0x0020 // LPM Error Interrupt Mask -#define USB_LPMIM_RES 0x0010 // LPM Resume Interrupt Mask -#define USB_LPMIM_NC 0x0008 // LPM NC Interrupt Mask -#define USB_LPMIM_ACK 0x0004 // LPM ACK Interrupt Mask -#define USB_LPMIM_NY 0x0002 // LPM NY Interrupt Mask -#define USB_LPMIM_STALL 0x0001 // LPM STALL Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMRIS register. -// -//***************************************************************************** -#define USB_LPMRIS_ERR 0x0020 // LPM Interrupt Status -#define USB_LPMRIS_RES 0x0010 // LPM Resume Interrupt Status -#define USB_LPMRIS_NC 0x0008 // LPM NC Interrupt Status -#define USB_LPMRIS_ACK 0x0004 // LPM ACK Interrupt Status -#define USB_LPMRIS_NY 0x0002 // LPM NY Interrupt Status -#define USB_LPMRIS_LPMST 0x0001 // LPM STALL Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_LPMFADDR register. -// -//***************************************************************************** -#define USB_LPMFADDR_ADDR_M 0x007F // LPM Function Address -#define USB_LPMFADDR_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPC register. -// -//***************************************************************************** -#define USB_EPC_PFLTACT_M 0x0300 // Power Fault Action -#define USB_EPC_PFLTACT_UNCHG 0x0000 // Unchanged -#define USB_EPC_PFLTACT_TRIS 0x0100 // Tristate -#define USB_EPC_PFLTACT_LOW 0x0200 // Low -#define USB_EPC_PFLTACT_HIGH 0x0300 // High -#define USB_EPC_PFLTAEN 0x0040 // Power Fault Action Enable -#define USB_EPC_PFLTSEN_HIGH 0x0020 // Power Fault Sense -#define USB_EPC_PFLTEN 0x0010 // Power Fault Input Enable -#define USB_EPC_EPENDE 0x0004 // EPEN Drive Enable -#define USB_EPC_EPEN_M 0x0003 // External Power Supply Enable - // Configuration -#define USB_EPC_EPEN_LOW 0x0000 // Power Enable Active Low -#define USB_EPC_EPEN_HIGH 0x0001 // Power Enable Active High -#define USB_EPC_EPEN_VBLOW 0x0002 // Power Enable High if VBUS Low - // (OTG only) -#define USB_EPC_EPEN_VBHIGH 0x0003 // Power Enable High if VBUS High - // (OTG only) - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCRIS register. -// -//***************************************************************************** -#define USB_EPCRIS_PF 0x0001 // USB Power Fault Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCIM register. -// -//***************************************************************************** -#define USB_EPCIM_PF 0x0001 // USB Power Fault Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_EPCISC register. -// -//***************************************************************************** -#define USB_EPCISC_PF 0x0001 // USB Power Fault Interrupt Status - // and Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRRIS register. -// -//***************************************************************************** -#define USB_DRRIS_RESUME 0x0001 // RESUME Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRIM register. -// -//***************************************************************************** -#define USB_DRIM_RESUME 0x0001 // RESUME Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_DRISC register. -// -//***************************************************************************** -#define USB_DRISC_RESUME 0x0001 // RESUME Interrupt Status and - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_GPCS register. -// -//***************************************************************************** -#define USB_GPCS_DEVMOD_M 0x0007 // Device Mode -#define USB_GPCS_DEVMOD_OTG 0x0000 // Use USB0VBUS and USB0ID pin -#define USB_GPCS_DEVMOD_HOST 0x0002 // Force USB0VBUS and USB0ID low -#define USB_GPCS_DEVMOD_DEV 0x0003 // Force USB0VBUS and USB0ID high -#define USB_GPCS_DEVMOD_HOSTVBUS \ - 0x0004 // Use USB0VBUS and force USB0ID - // low -#define USB_GPCS_DEVMOD_DEVVBUS 0x0005 // Use USB0VBUS and force USB0ID - // high - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDC register. -// -//***************************************************************************** -#define USB_VDC_VBDEN 0x0001 // VBUS Droop Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCRIS register. -// -//***************************************************************************** -#define USB_VDCRIS_VD 0x0001 // VBUS Droop Raw Interrupt Status - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCIM register. -// -//***************************************************************************** -#define USB_VDCIM_VD 0x0001 // VBUS Droop Interrupt Mask - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_VDCISC register. -// -//***************************************************************************** -#define USB_VDCISC_VD 0x0001 // VBUS Droop Interrupt Status and - // Clear - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_PP register. -// -//***************************************************************************** -#define USB_PP_ECNT_M 0xFF00 // Endpoint Count -#define USB_PP_USB_M 0x00C0 // USB Capability -#define USB_PP_USB_DEVICE 0x0040 // DEVICE -#define USB_PP_USB_HOSTDEVICE 0x0080 // HOST -#define USB_PP_USB_OTG 0x00C0 // OTG -#define USB_PP_ULPI 0x0020 // ULPI Present -#define USB_PP_PHY 0x0010 // PHY Present -#define USB_PP_TYPE_M 0x000F // Controller Type -#define USB_PP_TYPE_0 0x0000 // The first-generation USB - // controller -#define USB_PP_TYPE_1 0x0001 // The second-generation USB - // controller revision -#define USB_PP_ECNT_S 8 - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_PC register. -// -//***************************************************************************** -#define USB_PC_ULPIEN 0x00010000 // ULPI Enable - -//***************************************************************************** -// -// The following are defines for the bit fields in the USB_O_CC register. -// -//***************************************************************************** -#define USB_CC_CLKEN 0x0200 // USB Clock Enable -#define USB_CC_CSD 0x0100 // Clock Source/Direction -#define USB_CC_CLKDIV_M 0x000F // PLL Clock Divisor -#define USB_CC_CLKDIV_S 0 - #ifdef __cplusplus } #endif -- cgit v1.3.1 From fe7ffc8edaad069955d6ededb3fc77084338256c Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 17 Aug 2024 19:08:48 +0700 Subject: rename register bit definition to prevent conflict --- src/portable/mentor/musb/dcd_musb.c | 98 +++---- src/portable/mentor/musb/musb_type.h | 518 +++++++++++++++++------------------ 2 files changed, 308 insertions(+), 308 deletions(-) (limited to 'src/portable') diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 3dcb9cdf1..3fd4d953a 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -240,7 +240,7 @@ static void process_setup_packet(uint8_t rhport) { /* Clear RX FIFO and reverse the transaction direction */ if (len && dir_in) { musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, 0); - ep_csr->csr0l = USB_CSRL0_RXRDYC; + ep_csr->csr0l = MUSB_CSRL0_RXRDYC; } } @@ -272,7 +272,7 @@ static bool handle_xfer_in(uint8_t rhport, uint_fast8_t ep_addr) } pipe->remaining = rem - len; } - ep_csr->tx_csrl = USB_TXCSRL1_TXRDY; + ep_csr->tx_csrl = MUSB_TXCSRL1_TXRDY; // TU_LOG1(" TXCSRL%d = %x %d\r\n", epnum, ep_csr->tx_csrl, rem - len); return false; } @@ -286,7 +286,7 @@ static bool handle_xfer_out(uint8_t rhport, uint_fast8_t ep_addr) musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epnum); // TU_LOG1(" RXCSRL%d = %x\r\n", epnum_minus1 + 1, ep_csr->rx_csrl); - TU_ASSERT(ep_csr->rx_csrl & USB_RXCSRL1_RXRDY); + TU_ASSERT(ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY); const unsigned mps = ep_csr->rx_maxp; const unsigned rem = pipe->remaining; @@ -327,7 +327,7 @@ static bool edpt_n_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16 } else { musb_regs_t* musb_regs = MUSB_REGS(rhport); musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epnum); - if (ep_csr->rx_csrl & USB_RXCSRL1_RXRDY) ep_csr->rx_csrl = 0; + if (ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY) ep_csr->rx_csrl = 0; } return true; } @@ -377,9 +377,9 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; /* Change to STATUS/SETUP stage */ _dcd.status_out = 1; /* Flush TX FIFO and reverse the transaction direction. */ - ep_csr->csr0l = USB_CSRL0_TXRDY | USB_CSRL0_DATAEND; + ep_csr->csr0l = MUSB_CSRL0_TXRDY | MUSB_CSRL0_DATAEND; } else { - ep_csr->csr0l = USB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */ + ep_csr->csr0l = MUSB_CSRL0_TXRDY; /* Flush TX FIFO to return ACK. */ } // TU_LOG1(" IN ep_csr->csr0l = %x\r\n", ep_csr->csr0l); } else { @@ -387,7 +387,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ _dcd.pipe0.buf = buffer; _dcd.pipe0.length = len; _dcd.pipe0.remaining = len; - ep_csr->csr0l = USB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */ + ep_csr->csr0l = MUSB_CSRL0_RXRDYC; /* Clear RX FIFO to return ACK. */ } } else if (dir_in) { // TU_LOG1(" STATUS IN ep_csr->csr0l = %x\r\n", ep_csr->csr0l); @@ -395,7 +395,7 @@ static bool edpt0_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_ _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; /* Clear RX FIFO and reverse the transaction direction */ - ep_csr->csr0l = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; + ep_csr->csr0l = MUSB_CSRL0_RXRDYC | MUSB_CSRL0_DATAEND; } return true; } @@ -409,16 +409,16 @@ static void process_ep0(uint8_t rhport) // TU_LOG1(" EP0 ep_csr->csr0l = %x\r\n", csrl); // 21.1.5: endpoint 0 service routine as peripheral - if (csrl & USB_CSRL0_STALLED) { + if (csrl & MUSB_CSRL0_STALLED) { /* Returned STALL packet to HOST. */ ep_csr->csr0l = 0; /* Clear STALL */ return; } unsigned req = _dcd.setup_packet.bmRequestType; - if (csrl & USB_CSRL0_SETEND) { + if (csrl & MUSB_CSRL0_SETEND) { TU_LOG1(" ABORT by the next packets\r\n"); - ep_csr->csr0l = USB_CSRL0_SETENDC; + ep_csr->csr0l = MUSB_CSRL0_SETENDC; if (req != REQUEST_TYPE_INVALID && _dcd.pipe0.buf) { /* DATA stage was aborted by receiving STATUS or SETUP packet. */ _dcd.pipe0.buf = NULL; @@ -429,10 +429,10 @@ static void process_ep0(uint8_t rhport) XFER_RESULT_SUCCESS, true); } req = REQUEST_TYPE_INVALID; - if (!(csrl & USB_CSRL0_RXRDY)) return; /* Received SETUP packet */ + if (!(csrl & MUSB_CSRL0_RXRDY)) return; /* Received SETUP packet */ } - if (csrl & USB_CSRL0_RXRDY) { + if (csrl & MUSB_CSRL0_RXRDY) { /* Received SETUP or DATA OUT packet */ if (req == REQUEST_TYPE_INVALID) { /* SETUP */ @@ -496,15 +496,15 @@ static void process_edpt_n(uint8_t rhport, uint_fast8_t ep_addr) musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn); if (dir_in) { // TU_LOG1(" TX CSRL%d = %x\r\n", epn, ep_csr->tx_csrl); - if (ep_csr->tx_csrl & USB_TXCSRL1_STALLED) { - ep_csr->tx_csrl &= ~(USB_TXCSRL1_STALLED | USB_TXCSRL1_UNDRN); + if (ep_csr->tx_csrl & MUSB_TXCSRL1_STALLED) { + ep_csr->tx_csrl &= ~(MUSB_TXCSRL1_STALLED | MUSB_TXCSRL1_UNDRN); return; } completed = handle_xfer_in(rhport, ep_addr); } else { // TU_LOG1(" RX CSRL%d = %x\r\n", epn, ep_csr->rx_csrl); - if (ep_csr->rx_csrl & USB_RXCSRL1_STALLED) { - ep_csr->rx_csrl &= ~(USB_RXCSRL1_STALLED | USB_RXCSRL1_OVER); + if (ep_csr->rx_csrl & MUSB_RXCSRL1_STALLED) { + ep_csr->rx_csrl &= ~(MUSB_RXCSRL1_STALLED | MUSB_RXCSRL1_OVER); return; } completed = handle_xfer_out(rhport, ep_addr); @@ -541,7 +541,7 @@ static void process_bus_reset(uint8_t rhport) { fifo_reset(musb, i, 0); fifo_reset(musb, i, 1); } - dcd_event_bus_reset(rhport, (musb->power & USB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); + dcd_event_bus_reset(rhport, (musb->power & MUSB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); } /*------------------------------------------------------------------ @@ -576,7 +576,7 @@ void dcd_init(uint8_t rhport) { print_musb_info(musb_regs); #endif - musb_regs->intr_usben |= USB_IE_SUSPND; + musb_regs->intr_usben |= MUSB_IE_SUSPND; musb_dcd_int_clear(rhport); musb_dcd_phy_init(rhport); dcd_connect(rhport); @@ -601,33 +601,33 @@ void dcd_set_address(uint8_t rhport, uint8_t dev_addr) _dcd.pipe0.length = 0; _dcd.pipe0.remaining = 0; /* Clear RX FIFO to return ACK. */ - ep_csr->csr0l = USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND; + ep_csr->csr0l = MUSB_CSRL0_RXRDYC | MUSB_CSRL0_DATAEND; } // Wake up host void dcd_remote_wakeup(uint8_t rhport) { musb_regs_t* musb_regs = MUSB_REGS(rhport); - musb_regs->power |= USB_POWER_RESUME; + musb_regs->power |= MUSB_POWER_RESUME; unsigned cnt = SystemCoreClock / 1000; while (cnt--) __NOP(); - musb_regs->power &= ~USB_POWER_RESUME; + musb_regs->power &= ~MUSB_POWER_RESUME; } // Connect by enabling internal pull-up resistor on D+/D- void dcd_connect(uint8_t rhport) { musb_regs_t* musb_regs = MUSB_REGS(rhport); - musb_regs->power |= TUD_OPT_HIGH_SPEED ? USB_POWER_HSENAB : 0; - musb_regs->power |= USB_POWER_SOFTCONN; + musb_regs->power |= TUD_OPT_HIGH_SPEED ? MUSB_POWER_HSENAB : 0; + musb_regs->power |= MUSB_POWER_SOFTCONN; } // Disconnect by disabling internal pull-up resistor on D+/D- void dcd_disconnect(uint8_t rhport) { musb_regs_t* musb_regs = MUSB_REGS(rhport); - musb_regs->power &= ~USB_POWER_SOFTCONN; + musb_regs->power &= ~MUSB_POWER_SOFTCONN; } void dcd_sof_enable(uint8_t rhport, bool en) @@ -663,7 +663,7 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) const uint8_t is_rx = 1 - dir_in; ep_csr->maxp_csr[is_rx].maxp = mps; - ep_csr->maxp_csr[is_rx].csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? USB_RXCSRH1_ISO : 0; + ep_csr->maxp_csr[is_rx].csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? MUSB_RXCSRH1_ISO : 0; uint8_t csrl = MUSB_CSRL_CLEAR_DATA_TOGGLE(is_rx); if (ep_csr->maxp_csr[is_rx].csrl & MUSB_CSRL_PACKET_READY(is_rx)) { @@ -690,17 +690,17 @@ void dcd_edpt_close_all(uint8_t rhport) musb_ep_csr_t* ep_csr = get_ep_csr(musb, i); ep_csr->tx_maxp = 0; ep_csr->tx_csrh = 0; - if (ep_csr->tx_csrl & USB_TXCSRL1_TXRDY) - ep_csr->tx_csrl = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; + if (ep_csr->tx_csrl & MUSB_TXCSRL1_TXRDY) + ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT | MUSB_TXCSRL1_FLUSH; else - ep_csr->tx_csrl = USB_TXCSRL1_CLRDT; + ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT; ep_csr->rx_maxp = 0; ep_csr->rx_csrh = 0; - if (ep_csr->rx_csrl & USB_RXCSRL1_RXRDY) { - ep_csr->rx_csrl = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; + if (ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY) { + ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT | MUSB_RXCSRL1_FLUSH; } else { - ep_csr->rx_csrl = USB_RXCSRL1_CLRDT; + ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT; } fifo_reset(musb, i, 0); @@ -727,19 +727,19 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) musb->intr_txen &= ~TU_BIT(epn); ep_csr->tx_maxp = 0; ep_csr->tx_csrh = 0; - if (ep_csr->tx_csrl & USB_TXCSRL1_TXRDY) { - ep_csr->tx_csrl = USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH; + if (ep_csr->tx_csrl & MUSB_TXCSRL1_TXRDY) { + ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT | MUSB_TXCSRL1_FLUSH; } else { - ep_csr->tx_csrl = USB_TXCSRL1_CLRDT; + ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT; } } else { musb->intr_rxen &= ~TU_BIT(epn); ep_csr->rx_maxp = 0; ep_csr->rx_csrh = 0; - if (ep_csr->rx_csrl & USB_RXCSRL1_RXRDY) { - ep_csr->rx_csrl = USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH; + if (ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY) { + ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT | MUSB_RXCSRL1_FLUSH; } else { - ep_csr->rx_csrl = USB_RXCSRL1_CLRDT; + ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT; } } fifo_reset(musb, epn, dir_in); @@ -792,14 +792,14 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { if (!ep_addr) { /* Ignore EP80 */ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; _dcd.pipe0.buf = NULL; - ep_csr->csr0l = USB_CSRL0_STALL; + ep_csr->csr0l = MUSB_CSRL0_STALL; } } else { if (tu_edpt_dir(ep_addr)) { /* IN */ - ep_csr->tx_csrl = USB_TXCSRL1_STALL; + ep_csr->tx_csrl = MUSB_TXCSRL1_STALL; } else { /* OUT */ - TU_ASSERT(!(ep_csr->rx_csrl & USB_RXCSRL1_RXRDY),); - ep_csr->rx_csrl = USB_RXCSRL1_STALL; + TU_ASSERT(!(ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY),); + ep_csr->rx_csrl = MUSB_RXCSRL1_STALL; } } if (ie) musb_dcd_int_enable(rhport); @@ -815,9 +815,9 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); if (tu_edpt_dir(ep_addr)) { /* IN */ - ep_csr->tx_csrl = USB_TXCSRL1_CLRDT; + ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT; } else { /* OUT */ - ep_csr->rx_csrl = USB_RXCSRL1_CLRDT; + ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT; } if (ie) musb_dcd_int_enable(rhport); } @@ -838,18 +838,18 @@ void dcd_int_handler(uint8_t rhport) { // TU_LOG1("D%2x T%2x R%2x\r\n", is, txis, rxis); intr_usb &= musb_regs->intr_usben; /* Clear disabled interrupts */ - if (intr_usb & USB_IS_DISCON) { + if (intr_usb & MUSB_IS_DISCON) { } - if (intr_usb & USB_IS_SOF) { + if (intr_usb & MUSB_IS_SOF) { dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); } - if (intr_usb & USB_IS_RESET) { + if (intr_usb & MUSB_IS_RESET) { process_bus_reset(rhport); } - if (intr_usb & USB_IS_RESUME) { + if (intr_usb & MUSB_IS_RESUME) { dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); } - if (intr_usb & USB_IS_SUSPEND) { + if (intr_usb & MUSB_IS_SUSPEND) { dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); } diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h index 619eb0108..3415f74b5 100644 --- a/src/portable/mentor/musb/musb_type.h +++ b/src/portable/mentor/musb/musb_type.h @@ -307,14 +307,14 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ //--------------------------------------------------------------------+ // 0x01: Power -#define USB_POWER_ISOUP 0x0080 // Isochronous Update -#define USB_POWER_SOFTCONN 0x0040 // Soft Connect/Disconnect -#define USB_POWER_HSENAB 0x0020 // High Speed Enable -#define USB_POWER_HSMODE 0x0010 // High Speed Enable -#define USB_POWER_RESET 0x0008 // RESET Signaling -#define USB_POWER_RESUME 0x0004 // RESUME Signaling -#define USB_POWER_SUSPEND 0x0002 // SUSPEND Mode -#define USB_POWER_PWRDNPHY 0x0001 // Power Down PHY +#define MUSB_POWER_ISOUP 0x0080 // Isochronous Update +#define MUSB_POWER_SOFTCONN 0x0040 // Soft Connect/Disconnect +#define MUSB_POWER_HSENAB 0x0020 // High Speed Enable +#define MUSB_POWER_HSMODE 0x0010 // High Speed Enable +#define MUSB_POWER_RESET 0x0008 // RESET Signaling +#define MUSB_POWER_RESUME 0x0004 // RESUME Signaling +#define MUSB_POWER_SUSPEND 0x0002 // SUSPEND Mode +#define MUSB_POWER_PWRDNPHY 0x0001 // Power Down PHY // Interrupt TX/RX Status and Enable: each bit is for an endpoint @@ -340,460 +340,460 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_IS register. +// The following are defines for the bit fields in the MUSB_O_IS register. // //***************************************************************************** -#define USB_IS_VBUSERR 0x0080 // VBUS Error (OTG only) -#define USB_IS_SESREQ 0x0040 // SESSION REQUEST (OTG only) -#define USB_IS_DISCON 0x0020 // Session Disconnect (OTG only) -#define USB_IS_CONN 0x0010 // Session Connect -#define USB_IS_SOF 0x0008 // Start of Frame -#define USB_IS_BABBLE 0x0004 // Babble Detected -#define USB_IS_RESET 0x0004 // RESET Signaling Detected -#define USB_IS_RESUME 0x0002 // RESUME Signaling Detected -#define USB_IS_SUSPEND 0x0001 // SUSPEND Signaling Detected +#define MUSB_IS_VBUSERR 0x0080 // VBUS Error (OTG only) +#define MUSB_IS_SESREQ 0x0040 // SESSION REQUEST (OTG only) +#define MUSB_IS_DISCON 0x0020 // Session Disconnect (OTG only) +#define MUSB_IS_CONN 0x0010 // Session Connect +#define MUSB_IS_SOF 0x0008 // Start of Frame +#define MUSB_IS_BABBLE 0x0004 // Babble Detected +#define MUSB_IS_RESET 0x0004 // RESET Signaling Detected +#define MUSB_IS_RESUME 0x0002 // RESUME Signaling Detected +#define MUSB_IS_SUSPEND 0x0001 // SUSPEND Signaling Detected //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_IE register. +// The following are defines for the bit fields in the MUSB_O_IE register. // //***************************************************************************** -#define USB_IE_VBUSERR 0x0080 // Enable VBUS Error Interrupt (OTG only) -#define USB_IE_SESREQ 0x0040 // Enable Session Request (OTG only) -#define USB_IE_DISCON 0x0020 // Enable Disconnect Interrupt -#define USB_IE_CONN 0x0010 // Enable Connect Interrupt -#define USB_IE_SOF 0x0008 // Enable Start-of-Frame Interrupt -#define USB_IE_BABBLE 0x0004 // Enable Babble Interrupt -#define USB_IE_RESET 0x0004 // Enable RESET Interrupt -#define USB_IE_RESUME 0x0002 // Enable RESUME Interrupt -#define USB_IE_SUSPND 0x0001 // Enable SUSPEND Interrupt +#define MUSB_IE_VBUSERR 0x0080 // Enable VBUS Error Interrupt (OTG only) +#define MUSB_IE_SESREQ 0x0040 // Enable Session Request (OTG only) +#define MUSB_IE_DISCON 0x0020 // Enable Disconnect Interrupt +#define MUSB_IE_CONN 0x0010 // Enable Connect Interrupt +#define MUSB_IE_SOF 0x0008 // Enable Start-of-Frame Interrupt +#define MUSB_IE_BABBLE 0x0004 // Enable Babble Interrupt +#define MUSB_IE_RESET 0x0004 // Enable RESET Interrupt +#define MUSB_IE_RESUME 0x0002 // Enable RESUME Interrupt +#define MUSB_IE_SUSPND 0x0001 // Enable SUSPEND Interrupt //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_FRAME register. +// The following are defines for the bit fields in the MUSB_O_FRAME register. // //***************************************************************************** -#define USB_FRAME_M 0x07FF // Frame Number -#define USB_FRAME_S 0 +#define MUSB_FRAME_M 0x07FF // Frame Number +#define MUSB_FRAME_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_TEST register. +// The following are defines for the bit fields in the MUSB_O_TEST register. // //***************************************************************************** -#define USB_TEST_FORCEH 0x0080 // Force Host Mode -#define USB_TEST_FIFOACC 0x0040 // FIFO Access -#define USB_TEST_FORCEFS 0x0020 // Force Full-Speed Mode -#define USB_TEST_FORCEHS 0x0010 // Force High-Speed Mode -#define USB_TEST_TESTPKT 0x0008 // Test Packet Mode Enable -#define USB_TEST_TESTK 0x0004 // Test_K Mode Enable -#define USB_TEST_TESTJ 0x0002 // Test_J Mode Enable -#define USB_TEST_TESTSE0NAK 0x0001 // Test_SE0_NAK Test Mode Enable +#define MUSB_TEST_FORCEH 0x0080 // Force Host Mode +#define MUSB_TEST_FIFOACC 0x0040 // FIFO Access +#define MUSB_TEST_FORCEFS 0x0020 // Force Full-Speed Mode +#define MUSB_TEST_FORCEHS 0x0010 // Force High-Speed Mode +#define MUSB_TEST_TESTPKT 0x0008 // Test Packet Mode Enable +#define MUSB_TEST_TESTK 0x0004 // Test_K Mode Enable +#define MUSB_TEST_TESTJ 0x0002 // Test_J Mode Enable +#define MUSB_TEST_TESTSE0NAK 0x0001 // Test_SE0_NAK Test Mode Enable //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DEVCTL register. +// The following are defines for the bit fields in the MUSB_O_DEVCTL register. // //***************************************************************************** -#define USB_DEVCTL_DEV 0x0080 // Device Mode (OTG only) -#define USB_DEVCTL_FSDEV 0x0040 // Full-Speed Device Detected -#define USB_DEVCTL_LSDEV 0x0020 // Low-Speed Device Detected -#define USB_DEVCTL_VBUS_M 0x0018 // VBUS Level (OTG only) -#define USB_DEVCTL_VBUS_NONE 0x0000 // Below SessionEnd -#define USB_DEVCTL_VBUS_SEND 0x0008 // Above SessionEnd, below AValid -#define USB_DEVCTL_VBUS_AVALID 0x0010 // Above AValid, below VBUSValid -#define USB_DEVCTL_VBUS_VALID 0x0018 // Above VBUSValid -#define USB_DEVCTL_HOST 0x0004 // Host Mode -#define USB_DEVCTL_HOSTREQ 0x0002 // Host Request (OTG only) -#define USB_DEVCTL_SESSION 0x0001 // Session Start/End (OTG only) +#define MUSB_DEVCTL_DEV 0x0080 // Device Mode (OTG only) +#define MUSB_DEVCTL_FSDEV 0x0040 // Full-Speed Device Detected +#define MUSB_DEVCTL_LSDEV 0x0020 // Low-Speed Device Detected +#define MUSB_DEVCTL_VBUS_M 0x0018 // VBUS Level (OTG only) +#define MUSB_DEVCTL_VBUS_NONE 0x0000 // Below SessionEnd +#define MUSB_DEVCTL_VBUS_SEND 0x0008 // Above SessionEnd, below AValid +#define MUSB_DEVCTL_VBUS_AVALID 0x0010 // Above AValid, below VBUSValid +#define MUSB_DEVCTL_VBUS_VALID 0x0018 // Above VBUSValid +#define MUSB_DEVCTL_HOST 0x0004 // Host Mode +#define MUSB_DEVCTL_HOSTREQ 0x0002 // Host Request (OTG only) +#define MUSB_DEVCTL_SESSION 0x0001 // Session Start/End (OTG only) //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_CCONF register. +// The following are defines for the bit fields in the MUSB_O_CCONF register. // //***************************************************************************** -#define USB_CCONF_TXEDMA 0x0002 // TX Early DMA Enable -#define USB_CCONF_RXEDMA 0x0001 // TX Early DMA Enable +#define MUSB_CCONF_TXEDMA 0x0002 // TX Early DMA Enable +#define MUSB_CCONF_RXEDMA 0x0001 // TX Early DMA Enable //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// The following are defines for the bit fields in the MUSB_O_TXFIFOSZ register. // //***************************************************************************** -#define USB_TXFIFOSZ_DPB 0x0010 // Double Packet Buffer Support -#define USB_TXFIFOSZ_SIZE_M 0x000F // Max Packet Size -#define USB_TXFIFOSZ_SIZE_8 0x0000 // 8 -#define USB_TXFIFOSZ_SIZE_16 0x0001 // 16 -#define USB_TXFIFOSZ_SIZE_32 0x0002 // 32 -#define USB_TXFIFOSZ_SIZE_64 0x0003 // 64 -#define USB_TXFIFOSZ_SIZE_128 0x0004 // 128 -#define USB_TXFIFOSZ_SIZE_256 0x0005 // 256 -#define USB_TXFIFOSZ_SIZE_512 0x0006 // 512 -#define USB_TXFIFOSZ_SIZE_1024 0x0007 // 1024 -#define USB_TXFIFOSZ_SIZE_2048 0x0008 // 2048 +#define MUSB_TXFIFOSZ_DPB 0x0010 // Double Packet Buffer Support +#define MUSB_TXFIFOSZ_SIZE_M 0x000F // Max Packet Size +#define MUSB_TXFIFOSZ_SIZE_8 0x0000 // 8 +#define MUSB_TXFIFOSZ_SIZE_16 0x0001 // 16 +#define MUSB_TXFIFOSZ_SIZE_32 0x0002 // 32 +#define MUSB_TXFIFOSZ_SIZE_64 0x0003 // 64 +#define MUSB_TXFIFOSZ_SIZE_128 0x0004 // 128 +#define MUSB_TXFIFOSZ_SIZE_256 0x0005 // 256 +#define MUSB_TXFIFOSZ_SIZE_512 0x0006 // 512 +#define MUSB_TXFIFOSZ_SIZE_1024 0x0007 // 1024 +#define MUSB_TXFIFOSZ_SIZE_2048 0x0008 // 2048 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// The following are defines for the bit fields in the MUSB_O_RXFIFOSZ register. // //***************************************************************************** -#define USB_RXFIFOSZ_DPB 0x0010 // Double Packet Buffer Support -#define USB_RXFIFOSZ_SIZE_M 0x000F // Max Packet Size -#define USB_RXFIFOSZ_SIZE_8 0x0000 // 8 -#define USB_RXFIFOSZ_SIZE_16 0x0001 // 16 -#define USB_RXFIFOSZ_SIZE_32 0x0002 // 32 -#define USB_RXFIFOSZ_SIZE_64 0x0003 // 64 -#define USB_RXFIFOSZ_SIZE_128 0x0004 // 128 -#define USB_RXFIFOSZ_SIZE_256 0x0005 // 256 -#define USB_RXFIFOSZ_SIZE_512 0x0006 // 512 -#define USB_RXFIFOSZ_SIZE_1024 0x0007 // 1024 -#define USB_RXFIFOSZ_SIZE_2048 0x0008 // 2048 +#define MUSB_RXFIFOSZ_DPB 0x0010 // Double Packet Buffer Support +#define MUSB_RXFIFOSZ_SIZE_M 0x000F // Max Packet Size +#define MUSB_RXFIFOSZ_SIZE_8 0x0000 // 8 +#define MUSB_RXFIFOSZ_SIZE_16 0x0001 // 16 +#define MUSB_RXFIFOSZ_SIZE_32 0x0002 // 32 +#define MUSB_RXFIFOSZ_SIZE_64 0x0003 // 64 +#define MUSB_RXFIFOSZ_SIZE_128 0x0004 // 128 +#define MUSB_RXFIFOSZ_SIZE_256 0x0005 // 256 +#define MUSB_RXFIFOSZ_SIZE_512 0x0006 // 512 +#define MUSB_RXFIFOSZ_SIZE_1024 0x0007 // 1024 +#define MUSB_RXFIFOSZ_SIZE_2048 0x0008 // 2048 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_TXFIFOADD +// The following are defines for the bit fields in the MUSB_O_TXFIFOADD // register. // //***************************************************************************** -#define USB_TXFIFOADD_ADDR_M 0x01FF // Transmit/Receive Start Address -#define USB_TXFIFOADD_ADDR_S 0 +#define MUSB_TXFIFOADD_ADDR_M 0x01FF // Transmit/Receive Start Address +#define MUSB_TXFIFOADD_ADDR_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_RXFIFOADD +// The following are defines for the bit fields in the MUSB_O_RXFIFOADD // register. // //***************************************************************************** -#define USB_RXFIFOADD_ADDR_M 0x01FF // Transmit/Receive Start Address -#define USB_RXFIFOADD_ADDR_S 0 +#define MUSB_RXFIFOADD_ADDR_M 0x01FF // Transmit/Receive Start Address +#define MUSB_RXFIFOADD_ADDR_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL +// The following are defines for the bit fields in the MUSB_O_ULPIVBUSCTL // register. // //***************************************************************************** -#define USB_ULPIVBUSCTL_USEEXTVBUSIND 0x0002 // Use External VBUS Indicator -#define USB_ULPIVBUSCTL_USEEXTVBUS 0x0001 // Use External VBUS +#define MUSB_ULPIVBUSCTL_USEEXTVBUSIND 0x0002 // Use External VBUS Indicator +#define MUSB_ULPIVBUSCTL_USEEXTVBUS 0x0001 // Use External VBUS //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_ULPIREGDATA +// The following are defines for the bit fields in the MUSB_O_ULPIREGDATA // register. // //***************************************************************************** -#define USB_ULPIREGDATA_REGDATA_M 0x00FF // Register Data -#define USB_ULPIREGDATA_REGDATA_S 0 +#define MUSB_ULPIREGDATA_REGDATA_M 0x00FF // Register Data +#define MUSB_ULPIREGDATA_REGDATA_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_ULPIREGADDR +// The following are defines for the bit fields in the MUSB_O_ULPIREGADDR // register. // //***************************************************************************** -#define USB_ULPIREGADDR_ADDR_M 0x00FF // Register Address -#define USB_ULPIREGADDR_ADDR_S 0 +#define MUSB_ULPIREGADDR_ADDR_M 0x00FF // Register Address +#define MUSB_ULPIREGADDR_ADDR_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_ULPIREGCTL +// The following are defines for the bit fields in the MUSB_O_ULPIREGCTL // register. // //***************************************************************************** -#define USB_ULPIREGCTL_RDWR 0x0004 // Read/Write Control -#define USB_ULPIREGCTL_REGCMPLT 0x0002 // Register Access Complete -#define USB_ULPIREGCTL_REGACC 0x0001 // Initiate Register Access +#define MUSB_ULPIREGCTL_RDWR 0x0004 // Read/Write Control +#define MUSB_ULPIREGCTL_REGCMPLT 0x0002 // Register Access Complete +#define MUSB_ULPIREGCTL_REGACC 0x0001 // Initiate Register Access //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_EPINFO register. +// The following are defines for the bit fields in the MUSB_O_EPINFO register. // //***************************************************************************** -#define USB_EPINFO_RXEP_M 0x00F0 // RX Endpoints -#define USB_EPINFO_TXEP_M 0x000F // TX Endpoints -#define USB_EPINFO_RXEP_S 4 -#define USB_EPINFO_TXEP_S 0 +#define MUSB_EPINFO_RXEP_M 0x00F0 // RX Endpoints +#define MUSB_EPINFO_TXEP_M 0x000F // TX Endpoints +#define MUSB_EPINFO_RXEP_S 4 +#define MUSB_EPINFO_TXEP_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_RAMINFO register. +// The following are defines for the bit fields in the MUSB_O_RAMINFO register. // //***************************************************************************** -#define USB_RAMINFO_DMACHAN_M 0x00F0 // DMA Channels -#define USB_RAMINFO_RAMBITS_M 0x000F // RAM Address Bus Width -#define USB_RAMINFO_DMACHAN_S 4 -#define USB_RAMINFO_RAMBITS_S 0 +#define MUSB_RAMINFO_DMACHAN_M 0x00F0 // DMA Channels +#define MUSB_RAMINFO_RAMBITS_M 0x000F // RAM Address Bus Width +#define MUSB_RAMINFO_DMACHAN_S 4 +#define MUSB_RAMINFO_RAMBITS_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_CONTIM register. +// The following are defines for the bit fields in the MUSB_O_CONTIM register. // //***************************************************************************** -#define USB_CONTIM_WTCON_M 0x00F0 // Connect Wait -#define USB_CONTIM_WTID_M 0x000F // Wait ID -#define USB_CONTIM_WTCON_S 4 -#define USB_CONTIM_WTID_S 0 +#define MUSB_CONTIM_WTCON_M 0x00F0 // Connect Wait +#define MUSB_CONTIM_WTID_M 0x000F // Wait ID +#define MUSB_CONTIM_WTCON_S 4 +#define MUSB_CONTIM_WTID_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_VPLEN register. +// The following are defines for the bit fields in the MUSB_O_VPLEN register. // //***************************************************************************** -#define USB_VPLEN_VPLEN_M 0x00FF // VBUS Pulse Length -#define USB_VPLEN_VPLEN_S 0 +#define MUSB_VPLEN_VPLEN_M 0x00FF // VBUS Pulse Length +#define MUSB_VPLEN_VPLEN_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_HSEOF register. +// The following are defines for the bit fields in the MUSB_O_HSEOF register. // //***************************************************************************** -#define USB_HSEOF_HSEOFG_M 0x00FF // HIgh-Speed End-of-Frame Gap -#define USB_HSEOF_HSEOFG_S 0 +#define MUSB_HSEOF_HSEOFG_M 0x00FF // HIgh-Speed End-of-Frame Gap +#define MUSB_HSEOF_HSEOFG_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_FSEOF register. +// The following are defines for the bit fields in the MUSB_O_FSEOF register. // //***************************************************************************** -#define USB_FSEOF_FSEOFG_M 0x00FF // Full-Speed End-of-Frame Gap -#define USB_FSEOF_FSEOFG_S 0 +#define MUSB_FSEOF_FSEOFG_M 0x00FF // Full-Speed End-of-Frame Gap +#define MUSB_FSEOF_FSEOFG_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_LSEOF register. +// The following are defines for the bit fields in the MUSB_O_LSEOF register. // //***************************************************************************** -#define USB_LSEOF_LSEOFG_M 0x00FF // Low-Speed End-of-Frame Gap -#define USB_LSEOF_LSEOFG_S 0 +#define MUSB_LSEOF_LSEOFG_M 0x00FF // Low-Speed End-of-Frame Gap +#define MUSB_LSEOF_LSEOFG_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_CSRL0 register. +// The following are defines for the bit fields in the MUSB_O_CSRL0 register. // //***************************************************************************** -#define USB_CSRL0_NAKTO 0x0080 // NAK Timeout -#define USB_CSRL0_SETENDC 0x0080 // Setup End Clear -#define USB_CSRL0_STATUS 0x0040 // STATUS Packet -#define USB_CSRL0_RXRDYC 0x0040 // RXRDY Clear -#define USB_CSRL0_REQPKT 0x0020 // Request Packet -#define USB_CSRL0_STALL 0x0020 // Send Stall -#define USB_CSRL0_SETEND 0x0010 // Setup End -#define USB_CSRL0_ERROR 0x0010 // Error -#define USB_CSRL0_DATAEND 0x0008 // Data End -#define USB_CSRL0_SETUP 0x0008 // Setup Packet -#define USB_CSRL0_STALLED 0x0004 // Endpoint Stalled -#define USB_CSRL0_TXRDY 0x0002 // Transmit Packet Ready -#define USB_CSRL0_RXRDY 0x0001 // Receive Packet Ready +#define MUSB_CSRL0_NAKTO 0x0080 // NAK Timeout +#define MUSB_CSRL0_SETENDC 0x0080 // Setup End Clear +#define MUSB_CSRL0_STATUS 0x0040 // STATUS Packet +#define MUSB_CSRL0_RXRDYC 0x0040 // RXRDY Clear +#define MUSB_CSRL0_REQPKT 0x0020 // Request Packet +#define MUSB_CSRL0_STALL 0x0020 // Send Stall +#define MUSB_CSRL0_SETEND 0x0010 // Setup End +#define MUSB_CSRL0_ERROR 0x0010 // Error +#define MUSB_CSRL0_DATAEND 0x0008 // Data End +#define MUSB_CSRL0_SETUP 0x0008 // Setup Packet +#define MUSB_CSRL0_STALLED 0x0004 // Endpoint Stalled +#define MUSB_CSRL0_TXRDY 0x0002 // Transmit Packet Ready +#define MUSB_CSRL0_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_CSRH0 register. +// The following are defines for the bit fields in the MUSB_O_CSRH0 register. // //***************************************************************************** -#define USB_CSRH0_DISPING 0x0008 // PING Disable -#define USB_CSRH0_DTWE 0x0004 // Data Toggle Write Enable -#define USB_CSRH0_DT 0x0002 // Data Toggle -#define USB_CSRH0_FLUSH 0x0001 // Flush FIFO +#define MUSB_CSRH0_DISPING 0x0008 // PING Disable +#define MUSB_CSRH0_DTWE 0x0004 // Data Toggle Write Enable +#define MUSB_CSRH0_DT 0x0002 // Data Toggle +#define MUSB_CSRH0_FLUSH 0x0001 // Flush FIFO //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_TYPE0 register. +// The following are defines for the bit fields in the MUSB_O_TYPE0 register. // //***************************************************************************** -#define USB_TYPE0_SPEED_M 0x00C0 // Operating Speed -#define USB_TYPE0_SPEED_HIGH 0x0040 // High -#define USB_TYPE0_SPEED_FULL 0x0080 // Full -#define USB_TYPE0_SPEED_LOW 0x00C0 // Low +#define MUSB_TYPE0_SPEED_M 0x00C0 // Operating Speed +#define MUSB_TYPE0_SPEED_HIGH 0x0040 // High +#define MUSB_TYPE0_SPEED_FULL 0x0080 // Full +#define MUSB_TYPE0_SPEED_LOW 0x00C0 // Low //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_NAKLMT register. +// The following are defines for the bit fields in the MUSB_O_NAKLMT register. // //***************************************************************************** -#define USB_NAKLMT_NAKLMT_M 0x001F // EP0 NAK Limit -#define USB_NAKLMT_NAKLMT_S 0 +#define MUSB_NAKLMT_NAKLMT_M 0x001F // EP0 NAK Limit +#define MUSB_NAKLMT_NAKLMT_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// The following are defines for the bit fields in the MUSB_O_TXCSRL1 register. // //***************************************************************************** -#define USB_TXCSRL1_NAKTO 0x0080 // NAK Timeout -#define USB_TXCSRL1_CLRDT 0x0040 // Clear Data Toggle -#define USB_TXCSRL1_STALLED 0x0020 // Endpoint Stalled -#define USB_TXCSRL1_STALL 0x0010 // Send STALL -#define USB_TXCSRL1_SETUP 0x0010 // Setup Packet -#define USB_TXCSRL1_FLUSH 0x0008 // Flush FIFO -#define USB_TXCSRL1_ERROR 0x0004 // Error -#define USB_TXCSRL1_UNDRN 0x0004 // Underrun -#define USB_TXCSRL1_FIFONE 0x0002 // FIFO Not Empty -#define USB_TXCSRL1_TXRDY 0x0001 // Transmit Packet Ready +#define MUSB_TXCSRL1_NAKTO 0x0080 // NAK Timeout +#define MUSB_TXCSRL1_CLRDT 0x0040 // Clear Data Toggle +#define MUSB_TXCSRL1_STALLED 0x0020 // Endpoint Stalled +#define MUSB_TXCSRL1_STALL 0x0010 // Send STALL +#define MUSB_TXCSRL1_SETUP 0x0010 // Setup Packet +#define MUSB_TXCSRL1_FLUSH 0x0008 // Flush FIFO +#define MUSB_TXCSRL1_ERROR 0x0004 // Error +#define MUSB_TXCSRL1_UNDRN 0x0004 // Underrun +#define MUSB_TXCSRL1_FIFONE 0x0002 // FIFO Not Empty +#define MUSB_TXCSRL1_TXRDY 0x0001 // Transmit Packet Ready //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// The following are defines for the bit fields in the MUSB_O_TXCSRH1 register. // //***************************************************************************** -#define USB_TXCSRH1_AUTOSET 0x0080 // Auto Set -#define USB_TXCSRH1_ISO 0x0040 // Isochronous Transfers -#define USB_TXCSRH1_MODE 0x0020 // Mode -#define USB_TXCSRH1_DMAEN 0x0010 // DMA Request Enable -#define USB_TXCSRH1_FDT 0x0008 // Force Data Toggle -#define USB_TXCSRH1_DMAMOD 0x0004 // DMA Request Mode -#define USB_TXCSRH1_DTWE 0x0002 // Data Toggle Write Enable -#define USB_TXCSRH1_DT 0x0001 // Data Toggle +#define MUSB_TXCSRH1_AUTOSET 0x0080 // Auto Set +#define MUSB_TXCSRH1_ISO 0x0040 // Isochronous Transfers +#define MUSB_TXCSRH1_MODE 0x0020 // Mode +#define MUSB_TXCSRH1_DMAEN 0x0010 // DMA Request Enable +#define MUSB_TXCSRH1_FDT 0x0008 // Force Data Toggle +#define MUSB_TXCSRH1_DMAMOD 0x0004 // DMA Request Mode +#define MUSB_TXCSRH1_DTWE 0x0002 // Data Toggle Write Enable +#define MUSB_TXCSRH1_DT 0x0001 // Data Toggle //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// The following are defines for the bit fields in the MUSB_O_RXCSRL1 register. // //***************************************************************************** -#define USB_RXCSRL1_CLRDT 0x0080 // Clear Data Toggle -#define USB_RXCSRL1_STALLED 0x0040 // Endpoint Stalled -#define USB_RXCSRL1_STALL 0x0020 // Send STALL -#define USB_RXCSRL1_REQPKT 0x0020 // Request Packet -#define USB_RXCSRL1_FLUSH 0x0010 // Flush FIFO -#define USB_RXCSRL1_DATAERR 0x0008 // Data Error -#define USB_RXCSRL1_NAKTO 0x0008 // NAK Timeout -#define USB_RXCSRL1_OVER 0x0004 // Overrun -#define USB_RXCSRL1_ERROR 0x0004 // Error -#define USB_RXCSRL1_FULL 0x0002 // FIFO Full -#define USB_RXCSRL1_RXRDY 0x0001 // Receive Packet Ready +#define MUSB_RXCSRL1_CLRDT 0x0080 // Clear Data Toggle +#define MUSB_RXCSRL1_STALLED 0x0040 // Endpoint Stalled +#define MUSB_RXCSRL1_STALL 0x0020 // Send STALL +#define MUSB_RXCSRL1_REQPKT 0x0020 // Request Packet +#define MUSB_RXCSRL1_FLUSH 0x0010 // Flush FIFO +#define MUSB_RXCSRL1_DATAERR 0x0008 // Data Error +#define MUSB_RXCSRL1_NAKTO 0x0008 // NAK Timeout +#define MUSB_RXCSRL1_OVER 0x0004 // Overrun +#define MUSB_RXCSRL1_ERROR 0x0004 // Error +#define MUSB_RXCSRL1_FULL 0x0002 // FIFO Full +#define MUSB_RXCSRL1_RXRDY 0x0001 // Receive Packet Ready //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// The following are defines for the bit fields in the MUSB_O_RXCSRH1 register. // //***************************************************************************** -#define USB_RXCSRH1_AUTOCL 0x0080 // Auto Clear -#define USB_RXCSRH1_AUTORQ 0x0040 // Auto Request -#define USB_RXCSRH1_ISO 0x0040 // Isochronous Transfers -#define USB_RXCSRH1_DMAEN 0x0020 // DMA Request Enable -#define USB_RXCSRH1_DISNYET 0x0010 // Disable NYET -#define USB_RXCSRH1_PIDERR 0x0010 // PID Error -#define USB_RXCSRH1_DMAMOD 0x0008 // DMA Request Mode -#define USB_RXCSRH1_DTWE 0x0004 // Data Toggle Write Enable -#define USB_RXCSRH1_DT 0x0002 // Data Toggle -#define USB_RXCSRH1_INCOMPRX 0x0001 // Incomplete RX Transmission Status +#define MUSB_RXCSRH1_AUTOCL 0x0080 // Auto Clear +#define MUSB_RXCSRH1_AUTORQ 0x0040 // Auto Request +#define MUSB_RXCSRH1_ISO 0x0040 // Isochronous Transfers +#define MUSB_RXCSRH1_DMAEN 0x0020 // DMA Request Enable +#define MUSB_RXCSRH1_DISNYET 0x0010 // Disable NYET +#define MUSB_RXCSRH1_PIDERR 0x0010 // PID Error +#define MUSB_RXCSRH1_DMAMOD 0x0008 // DMA Request Mode +#define MUSB_RXCSRH1_DTWE 0x0004 // Data Toggle Write Enable +#define MUSB_RXCSRH1_DT 0x0002 // Data Toggle +#define MUSB_RXCSRH1_INCOMPRX 0x0001 // Incomplete RX Transmission Status //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// The following are defines for the bit fields in the MUSB_O_TXTYPE1 register. // //***************************************************************************** -#define USB_TXTYPE1_SPEED_M 0x00C0 // Operating Speed -#define USB_TXTYPE1_SPEED_DFLT 0x0000 // Default -#define USB_TXTYPE1_SPEED_HIGH 0x0040 // High -#define USB_TXTYPE1_SPEED_FULL 0x0080 // Full -#define USB_TXTYPE1_SPEED_LOW 0x00C0 // Low -#define USB_TXTYPE1_PROTO_M 0x0030 // Protocol -#define USB_TXTYPE1_PROTO_CTRL 0x0000 // Control -#define USB_TXTYPE1_PROTO_ISOC 0x0010 // Isochronous -#define USB_TXTYPE1_PROTO_BULK 0x0020 // Bulk -#define USB_TXTYPE1_PROTO_INT 0x0030 // Interrupt -#define USB_TXTYPE1_TEP_M 0x000F // Target Endpoint Number -#define USB_TXTYPE1_TEP_S 0 +#define MUSB_TXTYPE1_SPEED_M 0x00C0 // Operating Speed +#define MUSB_TXTYPE1_SPEED_DFLT 0x0000 // Default +#define MUSB_TXTYPE1_SPEED_HIGH 0x0040 // High +#define MUSB_TXTYPE1_SPEED_FULL 0x0080 // Full +#define MUSB_TXTYPE1_SPEED_LOW 0x00C0 // Low +#define MUSB_TXTYPE1_PROTO_M 0x0030 // Protocol +#define MUSB_TXTYPE1_PROTO_CTRL 0x0000 // Control +#define MUSB_TXTYPE1_PROTO_ISOC 0x0010 // Isochronous +#define MUSB_TXTYPE1_PROTO_BULK 0x0020 // Bulk +#define MUSB_TXTYPE1_PROTO_INT 0x0030 // Interrupt +#define MUSB_TXTYPE1_TEP_M 0x000F // Target Endpoint Number +#define MUSB_TXTYPE1_TEP_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// The following are defines for the bit fields in the MUSB_O_TXINTERVAL1 // register. // //***************************************************************************** -#define USB_TXINTERVAL1_NAKLMT_M 0x00FF // NAK Limit -#define USB_TXINTERVAL1_TXPOLL_M 0x00FF // TX Polling -#define USB_TXINTERVAL1_TXPOLL_S 0 -#define USB_TXINTERVAL1_NAKLMT_S 0 +#define MUSB_TXINTERVAL1_NAKLMT_M 0x00FF // NAK Limit +#define MUSB_TXINTERVAL1_TXPOLL_M 0x00FF // TX Polling +#define MUSB_TXINTERVAL1_TXPOLL_S 0 +#define MUSB_TXINTERVAL1_NAKLMT_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// The following are defines for the bit fields in the MUSB_O_RXTYPE1 register. // //***************************************************************************** -#define USB_RXTYPE1_SPEED_M 0x00C0 // Operating Speed -#define USB_RXTYPE1_SPEED_DFLT 0x0000 // Default -#define USB_RXTYPE1_SPEED_HIGH 0x0040 // High -#define USB_RXTYPE1_SPEED_FULL 0x0080 // Full -#define USB_RXTYPE1_SPEED_LOW 0x00C0 // Low -#define USB_RXTYPE1_PROTO_M 0x0030 // Protocol -#define USB_RXTYPE1_PROTO_CTRL 0x0000 // Control -#define USB_RXTYPE1_PROTO_ISOC 0x0010 // Isochronous -#define USB_RXTYPE1_PROTO_BULK 0x0020 // Bulk -#define USB_RXTYPE1_PROTO_INT 0x0030 // Interrupt -#define USB_RXTYPE1_TEP_M 0x000F // Target Endpoint Number -#define USB_RXTYPE1_TEP_S 0 +#define MUSB_RXTYPE1_SPEED_M 0x00C0 // Operating Speed +#define MUSB_RXTYPE1_SPEED_DFLT 0x0000 // Default +#define MUSB_RXTYPE1_SPEED_HIGH 0x0040 // High +#define MUSB_RXTYPE1_SPEED_FULL 0x0080 // Full +#define MUSB_RXTYPE1_SPEED_LOW 0x00C0 // Low +#define MUSB_RXTYPE1_PROTO_M 0x0030 // Protocol +#define MUSB_RXTYPE1_PROTO_CTRL 0x0000 // Control +#define MUSB_RXTYPE1_PROTO_ISOC 0x0010 // Isochronous +#define MUSB_RXTYPE1_PROTO_BULK 0x0020 // Bulk +#define MUSB_RXTYPE1_PROTO_INT 0x0030 // Interrupt +#define MUSB_RXTYPE1_TEP_M 0x000F // Target Endpoint Number +#define MUSB_RXTYPE1_TEP_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// The following are defines for the bit fields in the MUSB_O_RXINTERVAL1 // register. // //***************************************************************************** -#define USB_RXINTERVAL1_TXPOLL_M 0x00FF // RX Polling -#define USB_RXINTERVAL1_NAKLMT_M 0x00FF // NAK Limit -#define USB_RXINTERVAL1_TXPOLL_S 0 -#define USB_RXINTERVAL1_NAKLMT_S 0 +#define MUSB_RXINTERVAL1_TXPOLL_M 0x00FF // RX Polling +#define MUSB_RXINTERVAL1_NAKLMT_M 0x00FF // NAK Limit +#define MUSB_RXINTERVAL1_TXPOLL_S 0 +#define MUSB_RXINTERVAL1_NAKLMT_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMACTL0 register. +// The following are defines for the bit fields in the MUSB_O_DMACTL0 register. // //***************************************************************************** -#define USB_DMACTL0_BRSTM_M 0x0600 // Burst Mode -#define USB_DMACTL0_BRSTM_ANY 0x0000 // Bursts of unspecified length -#define USB_DMACTL0_BRSTM_INC4 0x0200 // INCR4 or unspecified length -#define USB_DMACTL0_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified +#define MUSB_DMACTL0_BRSTM_M 0x0600 // Burst Mode +#define MUSB_DMACTL0_BRSTM_ANY 0x0000 // Bursts of unspecified length +#define MUSB_DMACTL0_BRSTM_INC4 0x0200 // INCR4 or unspecified length +#define MUSB_DMACTL0_BRSTM_INC8 0x0400 // INCR8, INCR4 or unspecified // length -#define USB_DMACTL0_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or +#define MUSB_DMACTL0_BRSTM_INC16 0x0600 // INCR16, INCR8, INCR4 or // unspecified length -#define USB_DMACTL0_ERR 0x0100 // Bus Error Bit -#define USB_DMACTL0_EP_M 0x00F0 // Endpoint number -#define USB_DMACTL0_IE 0x0008 // DMA Interrupt Enable -#define USB_DMACTL0_MODE 0x0004 // DMA Transfer Mode -#define USB_DMACTL0_DIR 0x0002 // DMA Direction -#define USB_DMACTL0_ENABLE 0x0001 // DMA Transfer Enable -#define USB_DMACTL0_EP_S 4 +#define MUSB_DMACTL0_ERR 0x0100 // Bus Error Bit +#define MUSB_DMACTL0_EP_M 0x00F0 // Endpoint number +#define MUSB_DMACTL0_IE 0x0008 // DMA Interrupt Enable +#define MUSB_DMACTL0_MODE 0x0004 // DMA Transfer Mode +#define MUSB_DMACTL0_DIR 0x0002 // DMA Direction +#define MUSB_DMACTL0_ENABLE 0x0001 // DMA Transfer Enable +#define MUSB_DMACTL0_EP_S 4 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMAADDR0 register. +// The following are defines for the bit fields in the MUSB_O_DMAADDR0 register. // //***************************************************************************** -#define USB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address -#define USB_DMAADDR0_ADDR_S 2 +#define MUSB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address +#define MUSB_DMAADDR0_ADDR_S 2 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_DMACOUNT0 +// The following are defines for the bit fields in the MUSB_O_DMACOUNT0 // register. // //***************************************************************************** -#define USB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count -#define USB_DMACOUNT0_COUNT_S 2 +#define MUSB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count +#define MUSB_DMACOUNT0_COUNT_S 2 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_CTO register. +// The following are defines for the bit fields in the MUSB_O_CTO register. // //***************************************************************************** -#define USB_CTO_CCTV_M 0xFFFF // Configurable Chirp Timeout Value -#define USB_CTO_CCTV_S 0 +#define MUSB_CTO_CCTV_M 0xFFFF // Configurable Chirp Timeout Value +#define MUSB_CTO_CCTV_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_HHSRTN register. +// The following are defines for the bit fields in the MUSB_O_HHSRTN register. // //***************************************************************************** -#define USB_HHSRTN_HHSRTN_M 0xFFFF // HIgh Speed to UTM Operating +#define MUSB_HHSRTN_HHSRTN_M 0xFFFF // HIgh Speed to UTM Operating // Delay -#define USB_HHSRTN_HHSRTN_S 0 +#define MUSB_HHSRTN_HHSRTN_S 0 //***************************************************************************** // -// The following are defines for the bit fields in the USB_O_HSBT register. +// The following are defines for the bit fields in the MUSB_O_HSBT register. // //***************************************************************************** -#define USB_HSBT_HSBT_M 0x000F // High Speed Timeout Adder -#define USB_HSBT_HSBT_S 0 +#define MUSB_HSBT_HSBT_M 0x000F // High Speed Timeout Adder +#define MUSB_HSBT_HSBT_S 0 #ifdef __cplusplus } -- cgit v1.3.1 From 76eb2f506642968b2b0079326483905e79d20d2f Mon Sep 17 00:00:00 2001 From: hathach Date: Sun, 18 Aug 2024 16:34:58 +0700 Subject: more musb update --- src/portable/mentor/musb/dcd_musb.c | 79 +++++++++++++++++++---------------- src/portable/mentor/musb/musb_max32.h | 12 ++---- src/portable/mentor/musb/musb_type.h | 14 ++++--- 3 files changed, 54 insertions(+), 51 deletions(-) (limited to 'src/portable') diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 3fd4d953a..585480772 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -643,8 +643,7 @@ void dcd_sof_enable(uint8_t rhport, bool en) //--------------------------------------------------------------------+ // Configure endpoint's registers according to descriptor -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) -{ +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { const unsigned ep_addr = ep_desc->bEndpointAddress; const unsigned epn = tu_edpt_number(ep_addr); const unsigned dir_in = tu_edpt_dir(ep_addr); @@ -662,22 +661,30 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn); const uint8_t is_rx = 1 - dir_in; - ep_csr->maxp_csr[is_rx].maxp = mps; - ep_csr->maxp_csr[is_rx].csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? MUSB_RXCSRH1_ISO : 0; + musb_ep_maxp_csr_t* maxp_csr = &ep_csr->maxp_csr[is_rx]; + maxp_csr->maxp = mps; + maxp_csr->csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? MUSB_RXCSRH1_ISO : 0; + // flush and reset data toggle uint8_t csrl = MUSB_CSRL_CLEAR_DATA_TOGGLE(is_rx); - if (ep_csr->maxp_csr[is_rx].csrl & MUSB_CSRL_PACKET_READY(is_rx)) { + if (maxp_csr->csrl & MUSB_CSRL_PACKET_READY(is_rx)) { csrl |= MUSB_CSRL_FLUSH_FIFO(is_rx); } - ep_csr->maxp_csr[is_rx].csrl = csrl; + maxp_csr->csrl = csrl; + musb->intren_ep[is_rx] |= TU_BIT(epn); - /* Setup FIFO */ fifo_configure(musb, epn, dir_in, mps); return true; } +// bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { +// } +// +// bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) { +// } + void dcd_edpt_close_all(uint8_t rhport) { musb_regs_t* musb = MUSB_REGS(rhport); @@ -688,23 +695,20 @@ void dcd_edpt_close_all(uint8_t rhport) musb->intr_rxen = 0; for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { musb_ep_csr_t* ep_csr = get_ep_csr(musb, i); - ep_csr->tx_maxp = 0; - ep_csr->tx_csrh = 0; - if (ep_csr->tx_csrl & MUSB_TXCSRL1_TXRDY) - ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT | MUSB_TXCSRL1_FLUSH; - else - ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT; + for (unsigned d = 0; d < 2; d++) { + musb_ep_maxp_csr_t* maxp_csr = &ep_csr->maxp_csr[d]; + maxp_csr->maxp = 0; + maxp_csr->csrh = 0; + + // flush and reset data toggle + uint8_t csrl = MUSB_CSRL_CLEAR_DATA_TOGGLE(d); + if (maxp_csr->csrl & MUSB_CSRL_PACKET_READY(is_rx)) { + csrl |= MUSB_CSRL_FLUSH_FIFO(d); + } + maxp_csr->csrl = csrl; - ep_csr->rx_maxp = 0; - ep_csr->rx_csrh = 0; - if (ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY) { - ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT | MUSB_RXCSRL1_FLUSH; - } else { - ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT; + fifo_reset(musb, i, 1-d); } - - fifo_reset(musb, i, 0); - fifo_reset(musb, i, 1); } #if MUSB_CFG_DYNAMIC_FIFO @@ -755,12 +759,14 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t unsigned const epnum = tu_edpt_number(ep_addr); unsigned const ie = musb_dcd_get_int_enable(rhport); musb_dcd_int_disable(rhport); + if (epnum) { _dcd.pipe_buf_is_fifo[tu_edpt_dir(ep_addr)] &= ~TU_BIT(epnum - 1); ret = edpt_n_xfer(rhport, ep_addr, buffer, total_bytes); } else { ret = edpt0_xfer(rhport, ep_addr, buffer, total_bytes); } + if (ie) musb_dcd_int_enable(rhport); return ret; } @@ -783,11 +789,13 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_ // Stall endpoint void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - unsigned const epn = tu_edpt_number(ep_addr); unsigned const ie = musb_dcd_get_int_enable(rhport); + musb_dcd_int_disable(rhport); + + unsigned const epn = tu_edpt_number(ep_addr); musb_regs_t* musb_regs = MUSB_REGS(rhport); musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn); - musb_dcd_int_disable(rhport); + if (0 == epn) { if (!ep_addr) { /* Ignore EP80 */ _dcd.setup_packet.bmRequestType = REQUEST_TYPE_INVALID; @@ -795,13 +803,10 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { ep_csr->csr0l = MUSB_CSRL0_STALL; } } else { - if (tu_edpt_dir(ep_addr)) { /* IN */ - ep_csr->tx_csrl = MUSB_TXCSRL1_STALL; - } else { /* OUT */ - TU_ASSERT(!(ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY),); - ep_csr->rx_csrl = MUSB_RXCSRL1_STALL; - } + const uint8_t is_rx = 1 - tu_edpt_dir(ep_addr); + ep_csr->maxp_csr[is_rx].csrl = MUSB_CSRL_SEND_STALL(is_rx); } + if (ie) musb_dcd_int_enable(rhport); } @@ -809,16 +814,16 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { (void)rhport; + unsigned const ie = musb_dcd_get_int_enable(rhport); + musb_dcd_int_disable(rhport); + unsigned const epn = tu_edpt_number(ep_addr); musb_regs_t* musb_regs = MUSB_REGS(rhport); musb_ep_csr_t* ep_csr = get_ep_csr(musb_regs, epn); - unsigned const ie = musb_dcd_get_int_enable(rhport); - musb_dcd_int_disable(rhport); - if (tu_edpt_dir(ep_addr)) { /* IN */ - ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT; - } else { /* OUT */ - ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT; - } + const uint8_t is_rx = 1 - tu_edpt_dir(ep_addr); + + ep_csr->maxp_csr[is_rx].csrl = MUSB_CSRL_CLEAR_DATA_TOGGLE(is_rx); + if (ie) musb_dcd_int_enable(rhport); } diff --git a/src/portable/mentor/musb/musb_max32.h b/src/portable/mentor/musb/musb_max32.h index 38e80f680..35849b5f8 100644 --- a/src/portable/mentor/musb/musb_max32.h +++ b/src/portable/mentor/musb/musb_max32.h @@ -47,18 +47,15 @@ static const IRQn_Type musb_irqs[] = { USB_IRQn }; -TU_ATTR_ALWAYS_INLINE -static inline void musb_dcd_int_enable(uint8_t rhport) { +TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_enable(uint8_t rhport) { NVIC_EnableIRQ(musb_irqs[rhport]); } -TU_ATTR_ALWAYS_INLINE -static inline void musb_dcd_int_disable(uint8_t rhport) { +TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_disable(uint8_t rhport) { NVIC_DisableIRQ(musb_irqs[rhport]); } -TU_ATTR_ALWAYS_INLINE -static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) { +TU_ATTR_ALWAYS_INLINE static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) { #ifdef NVIC_GetEnableIRQ // only defined in CMSIS 5 return NVIC_GetEnableIRQ(musb_irqs[rhport]); #else @@ -67,8 +64,7 @@ static inline unsigned musb_dcd_get_int_enable(uint8_t rhport) { #endif } -TU_ATTR_ALWAYS_INLINE -static inline void musb_dcd_int_clear(uint8_t rhport) { +TU_ATTR_ALWAYS_INLINE static inline void musb_dcd_int_clear(uint8_t rhport) { NVIC_ClearPendingIRQ(musb_irqs[rhport]); } diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h index 3415f74b5..f8a66acce 100644 --- a/src/portable/mentor/musb/musb_type.h +++ b/src/portable/mentor/musb/musb_type.h @@ -83,6 +83,12 @@ #define __R volatile const #endif +typedef struct TU_ATTR_PACKED { + __IO uint16_t maxp; // 0x00, 0x04: MAXP + __IO uint8_t csrl; // 0x02, 0x06: CSRL + __IO uint8_t csrh; // 0x03, 0x07: CSRH +}musb_ep_maxp_csr_t; + // 0: TX (device IN, host OUT) // 1: RX (device OUT, host IN) typedef struct TU_ATTR_PACKED { @@ -103,11 +109,7 @@ typedef struct TU_ATTR_PACKED { __IO uint8_t rx_csrh; // 0x07: RX CSRH }; - struct { - __IO uint16_t maxp; // 0x00: MAXP - __IO uint8_t csrl; // 0x02: CSRL - __IO uint8_t csrh; // 0x03: CSRH - }maxp_csr[2]; + musb_ep_maxp_csr_t maxp_csr[2]; }; union { @@ -330,7 +332,7 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ #define MUSB_CSRL_PACKET_READY(_rx) (1u << 0) #define MUSB_CSRL_FLUSH_FIFO(_rx) (1u << ((_rx) ? 4 : 3)) #define MUSB_CSRL_SEND_STALL(_rx) (1u << ((_rx) ? 5 : 4)) -#define MUSB_CSRL_SENT_STALL(_rx) (1u << ((_rx) ? 6 : 5)) +#define MUSB_CSRL_STALLED(_rx) (1u << ((_rx) ? 6 : 5)) #define MUSB_CSRL_CLEAR_DATA_TOGGLE(_rx) (1u << ((_rx) ? 7 : 6)) // 0x13, 0x17: TX/RX CSRH -- cgit v1.3.1 From 8fdd8d9a7b83bfb79ac9a02142592d7ee4948b83 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 19 Aug 2024 11:59:41 +0700 Subject: implement dcd_edpt_iso_alloc/dcd_edpt_iso_activate for musb. video_capture example with iso kind of work but not smoothly. audio example does not seems to work as expected --- hw/bsp/max32690/family.cmake | 1 + src/common/tusb_mcu.h | 3 +- src/device/dcd.h | 15 +-- src/device/usbd.c | 18 +++- src/portable/mentor/musb/dcd_musb.c | 198 ++++++++++++++++++++--------------- src/portable/mentor/musb/musb_ti.h | 145 +------------------------ src/portable/mentor/musb/musb_type.h | 56 +--------- 7 files changed, 147 insertions(+), 289 deletions(-) (limited to 'src/portable') diff --git a/hw/bsp/max32690/family.cmake b/hw/bsp/max32690/family.cmake index 58647e432..736ca8eac 100644 --- a/hw/bsp/max32690/family.cmake +++ b/hw/bsp/max32690/family.cmake @@ -15,6 +15,7 @@ set(LD_FILE_Clang ${LD_FILE_GNU}) set(CMAKE_SYSTEM_PROCESSOR cortex-m4 CACHE INTERNAL "System Processor") set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) set(JLINK_DEVICE max32690) +set(OPENOCD_OPTION "-f interface/cmsis-dap.cfg -f target/max32690.cfg") set(FAMILY_MCUS MAX32690 CACHE INTERNAL "") diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index b7cbd83df..e86f55c1d 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -518,7 +518,8 @@ #define TU_ATTR_FAST_FUNC #endif -#if defined(TUP_USBIP_DWC2) || defined(TUP_USBIP_FSDEV) +// USBIP that support ISO alloc & activate API +#if defined(TUP_USBIP_DWC2) || defined(TUP_USBIP_FSDEV) || defined(TUP_USBIP_MUSB) #define TUP_DCD_EDPT_ISO_ALLOC #endif diff --git a/src/device/dcd.h b/src/device/dcd.h index 41e0fbee3..66fae0802 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -157,10 +157,6 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc // required for multiple configuration support. void dcd_edpt_close_all (uint8_t rhport); -// Close an endpoint. -// Since it is weak, caller must TU_ASSERT this function's existence before calling it. -void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) TU_ATTR_WEAK; - // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes); @@ -175,12 +171,19 @@ void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr); // This API never calls with control endpoints, since it is auto cleared when receiving setup packet void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr); +#ifdef TUP_DCD_EDPT_ISO_ALLOC // Allocate packet buffer used by ISO endpoints // Some MCU need manual packet buffer allocation, we allocate the largest size to avoid clustering -TU_ATTR_WEAK bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size); +bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size); // Configure and enable an ISO endpoint according to descriptor -TU_ATTR_WEAK bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep); +bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep); + +#else +// Close an endpoint. +void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr); + +#endif //--------------------------------------------------------------------+ // Event API (implemented by stack) diff --git a/src/device/usbd.c b/src/device/usbd.c index 7089e9cf1..d6f69fc24 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -1418,6 +1418,10 @@ bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr) { * In progress transfers on this EP may be delivered after this call. */ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr) { +#ifdef TUP_DCD_EDPT_ISO_ALLOC + (void) rhport; (void) ep_addr; + // ISO alloc/activate Should be used instead +#else rhport = _usbd_rhport; TU_ASSERT(dcd_edpt_close, /**/); @@ -1430,6 +1434,7 @@ void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr) { _usbd_dev.ep_status[epnum][dir].stalled = 0; _usbd_dev.ep_status[epnum][dir].busy = 0; _usbd_dev.ep_status[epnum][dir].claimed = 0; +#endif return; } @@ -1452,21 +1457,24 @@ void usbd_sof_enable(uint8_t rhport, sof_consumer_t consumer, bool en) { } bool usbd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { +#ifdef TUP_DCD_EDPT_ISO_ALLOC rhport = _usbd_rhport; - TU_ASSERT(dcd_edpt_iso_alloc); TU_ASSERT(tu_edpt_number(ep_addr) < CFG_TUD_ENDPPOINT_MAX); - return dcd_edpt_iso_alloc(rhport, ep_addr, largest_packet_size); +#else + (void) rhport; (void) ep_addr; (void) largest_packet_size; + return false; +#endif } bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const* desc_ep) { +#ifdef TUP_DCD_EDPT_ISO_ALLOC rhport = _usbd_rhport; uint8_t const epnum = tu_edpt_number(desc_ep->bEndpointAddress); uint8_t const dir = tu_edpt_dir(desc_ep->bEndpointAddress); - TU_ASSERT(dcd_edpt_iso_activate); TU_ASSERT(epnum < CFG_TUD_ENDPPOINT_MAX); TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed)); @@ -1474,6 +1482,10 @@ bool usbd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const* desc_ep) _usbd_dev.ep_status[epnum][dir].busy = 0; _usbd_dev.ep_status[epnum][dir].claimed = 0; return dcd_edpt_iso_activate(rhport, desc_ep); +#else + (void) rhport; (void) desc_ep; + return false; +#endif } #endif diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 585480772..dc2753ea6 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -94,64 +94,71 @@ static dcd_data_t _dcd; // First 64 bytes are reserved for EP0 static uint32_t alloced_fifo_bytes; -TU_ATTR_ALWAYS_INLINE static inline void fifo_reset(musb_regs_t* musb, unsigned epnum, unsigned dir_in) { +// ffsize is log2(mps) - 3 (round up) +TU_ATTR_ALWAYS_INLINE static inline uint8_t hwfifo_byte2size(uint16_t nbytes) { + uint8_t ffsize = 28 - tu_min8(28, __builtin_clz(nbytes)); + // round up to the next power of 2 + if ((8u << ffsize) < nbytes) { + ++ffsize; + } + + return ffsize; +} + +// index register is already set +TU_ATTR_ALWAYS_INLINE static inline void hwfifo_reset(musb_regs_t* musb, unsigned epnum, unsigned dir_in) { + (void) epnum; const uint8_t is_rx = 1 - dir_in; - musb->index = epnum; musb->fifo_size[is_rx] = 0; musb->fifo_addr[is_rx] = 0; } -TU_ATTR_ALWAYS_INLINE static inline bool fifo_configure(musb_regs_t* musb, unsigned epnum, unsigned dir_in, unsigned mps) { - // ffsize is log2(mps) - 3 (round up) - uint8_t ffsize = 28 - tu_min8(28, __builtin_clz(mps)); - // round up to the next power of 2 - if ((8u << ffsize) < mps) { - ++ffsize; - mps = 8 << ffsize; +// index register is already set +TU_ATTR_ALWAYS_INLINE static inline bool hwfifo_config(musb_regs_t* musb, unsigned epnum, unsigned dir_in, unsigned mps, bool double_packet) { + (void) epnum; + uint8_t ffsize = hwfifo_byte2size(mps); + mps = 8 << ffsize; // round up to the next power of 2 + + if (double_packet) { + ffsize |= MUSB_FIFOSZ_DOUBLE_PACKET; + mps <<= 1; } TU_ASSERT(alloced_fifo_bytes + mps <= MUSB_CFG_DYNAMIC_FIFO_SIZE); const uint8_t is_rx = 1 - dir_in; - musb->index = epnum; + musb->fifo_addr[is_rx] = alloced_fifo_bytes / 8; musb->fifo_size[is_rx] = ffsize; alloced_fifo_bytes += mps; - return true; } #else -TU_ATTR_ALWAYS_INLINE static inline void fifo_reset(musb_regs_t* musb, unsigned epnum, unsigned dir_in) { - const uint8_t is_rx = 1 - dir_in; - musb->index = epnum; - #if defined(TUP_USBIP_MUSB_ADI) - // Analog have custom double buffered in csrh register, disable it - musb->indexed_csr.maxp_csr[is_rx].csrh |= MUSB_CSRH_DISABLE_DOUBLE_PACKET(is_rx); - #else - // disable double bufeffered in extended register - #endif +// index register is already set +TU_ATTR_ALWAYS_INLINE static inline void hwfifo_reset(musb_regs_t* musb, unsigned epnum, unsigned dir_in) { + (void) musb; (void) epnum; (void) dir_in; + // nothing to do for static FIFO } -TU_ATTR_ALWAYS_INLINE static inline bool fifo_configure(musb_regs_t* musb, unsigned epnum, unsigned dir_in, unsigned mps) { - (void) mps; - const uint8_t is_rx = 1 - dir_in; - musb->index = epnum; - - uint8_t csrh = 0; - -#if defined(TUP_USBIP_MUSB_ADI) - csrh = MUSB_CSRH_DISABLE_DOUBLE_PACKET(is_rx); -#endif +// index register is already set +TU_ATTR_ALWAYS_INLINE static inline bool hwfifo_config(musb_regs_t* musb, unsigned epnum, unsigned dir_in, unsigned mps, + bool double_packet) { + (void) epnum; (void) dir_in; (void) mps; -#if MUSB_CFG_SHARED_FIFO - if (dir_in) { - csrh |= MUSB_CSRH_TX_MODE; + if (!double_packet) { + #if defined(TUP_USBIP_MUSB_ADI) + const uint8_t is_rx = 1 - dir_in; + musb->indexed_csr.maxp_csr[is_rx].csrh |= MUSB_CSRH_DISABLE_DOUBLE_PACKET(is_rx); + #else + if (is_rx) { + musb->rx_doulbe_packet_disable |= 1u << epnum; + } else { + musb->tx_double_packet_disable |= 1u << epnum; + } + #endif } -#endif - - musb->indexed_csr.maxp_csr[is_rx].csrh |= csrh; return true; } @@ -538,8 +545,9 @@ static void process_bus_reset(uint8_t rhport) { /* Clear FIFO settings */ for (unsigned i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { - fifo_reset(musb, i, 0); - fifo_reset(musb, i, 1); + musb->index = i; + hwfifo_reset(musb, i, 0); + hwfifo_reset(musb, i, 1); } dcd_event_bus_reset(rhport, (musb->power & MUSB_POWER_HSMODE) ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, true); } @@ -641,17 +649,18 @@ void dcd_sof_enable(uint8_t rhport, bool en) //--------------------------------------------------------------------+ // Endpoint API //--------------------------------------------------------------------+ +// static void edpt_setup(musb_regs_t* musb, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_size){ +// const unsigned epn = tu_edpt_number(ep_addr); +// const unsigned dir_in = tu_edpt_dir(ep_addr); +// } // Configure endpoint's registers according to descriptor bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { const unsigned ep_addr = ep_desc->bEndpointAddress; const unsigned epn = tu_edpt_number(ep_addr); const unsigned dir_in = tu_edpt_dir(ep_addr); - const unsigned xfer = ep_desc->bmAttributes.xfer; const unsigned mps = tu_edpt_packet_size(ep_desc); - TU_ASSERT(epn < TUP_DCD_ENDPOINT_MAX); - pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1]; pipe->buf = NULL; pipe->length = 0; @@ -659,11 +668,16 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { musb_regs_t* musb = MUSB_REGS(rhport); musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn); - const uint8_t is_rx = 1 - dir_in; musb_ep_maxp_csr_t* maxp_csr = &ep_csr->maxp_csr[is_rx]; + maxp_csr->maxp = mps; - maxp_csr->csrh = (xfer == TUSB_XFER_ISOCHRONOUS) ? MUSB_RXCSRH1_ISO : 0; + maxp_csr->csrh = 0; +#if MUSB_CFG_SHARED_FIFO + if (dir_in) { + maxp_csr->csrh |= MUSB_CSRH_TX_MODE; + } +#endif // flush and reset data toggle uint8_t csrl = MUSB_CSRL_CLEAR_DATA_TOGGLE(is_rx); @@ -672,18 +686,65 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { } maxp_csr->csrl = csrl; + TU_ASSERT(hwfifo_config(musb, epn, dir_in, mps, false)); musb->intren_ep[is_rx] |= TU_BIT(epn); - fifo_configure(musb, epn, dir_in, mps); - return true; } -// bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { -// } -// -// bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *desc_ep) { -// } +bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir_in = tu_edpt_dir(ep_addr); + musb_regs_t* musb = MUSB_REGS(rhport); + musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn); + const uint8_t is_rx = 1 - dir_in; + ep_csr->maxp_csr[is_rx].csrh = 0; + return hwfifo_config(musb, epn, dir_in, largest_packet_size, true); +} + +bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc ) { + const unsigned ep_addr = ep_desc->bEndpointAddress; + const unsigned epn = tu_edpt_number(ep_addr); + const unsigned dir_in = tu_edpt_dir(ep_addr); + const unsigned mps = tu_edpt_packet_size(ep_desc); + + unsigned const ie = musb_dcd_get_int_enable(rhport); + musb_dcd_int_disable(rhport); + + pipe_state_t *pipe = &_dcd.pipe[dir_in][epn - 1]; + pipe->buf = NULL; + pipe->length = 0; + pipe->remaining = 0; + + musb_regs_t* musb = MUSB_REGS(rhport); + musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn); + const uint8_t is_rx = 1 - dir_in; + musb_ep_maxp_csr_t* maxp_csr = &ep_csr->maxp_csr[is_rx]; + + maxp_csr->maxp = mps; + maxp_csr->csrh |= MUSB_CSRH_ISO; +#if MUSB_CFG_SHARED_FIFO + if (dir_in) { + maxp_csr->csrh |= MUSB_CSRH_TX_MODE; + } +#endif + + // flush fifo + if (maxp_csr->csrl & MUSB_CSRL_PACKET_READY(is_rx)) { + maxp_csr->csrl = MUSB_CSRL_FLUSH_FIFO(is_rx); + } + +#if MUSB_CFG_DYNAMIC_FIFO + // fifo space is already allocated, keep the address and just change packet size + musb->fifo_size[is_rx] = hwfifo_byte2size(mps) | MUSB_FIFOSZ_DOUBLE_PACKET; +#endif + + musb->intren_ep[is_rx] |= TU_BIT(epn); + + if (ie) musb_dcd_int_enable(rhport); + + return true; +} void dcd_edpt_close_all(uint8_t rhport) { @@ -707,7 +768,7 @@ void dcd_edpt_close_all(uint8_t rhport) } maxp_csr->csrl = csrl; - fifo_reset(musb, i, 1-d); + hwfifo_reset(musb, i, 1-d); } } @@ -718,38 +779,6 @@ void dcd_edpt_close_all(uint8_t rhport) if (ie) musb_dcd_int_enable(rhport); } -void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) -{ - // FIXME: we should implement iso_alloc() and iso_activate() - unsigned const epn = tu_edpt_number(ep_addr); - unsigned const dir_in = tu_edpt_dir(ep_addr); - musb_regs_t* musb = MUSB_REGS(rhport); - musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn); - unsigned const ie = musb_dcd_get_int_enable(rhport); - musb_dcd_int_disable(rhport); - if (dir_in) { - musb->intr_txen &= ~TU_BIT(epn); - ep_csr->tx_maxp = 0; - ep_csr->tx_csrh = 0; - if (ep_csr->tx_csrl & MUSB_TXCSRL1_TXRDY) { - ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT | MUSB_TXCSRL1_FLUSH; - } else { - ep_csr->tx_csrl = MUSB_TXCSRL1_CLRDT; - } - } else { - musb->intr_rxen &= ~TU_BIT(epn); - ep_csr->rx_maxp = 0; - ep_csr->rx_csrh = 0; - if (ep_csr->rx_csrl & MUSB_RXCSRL1_RXRDY) { - ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT | MUSB_RXCSRL1_FLUSH; - } else { - ep_csr->rx_csrl = MUSB_RXCSRL1_CLRDT; - } - } - fifo_reset(musb, epn, dir_in); - if (ie) musb_dcd_int_enable(rhport); -} - // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) { @@ -771,7 +800,8 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t return ret; } -// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c +// Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack +// - optional, however, must be listed in usbd.c bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) { (void)rhport; diff --git a/src/portable/mentor/musb/musb_ti.h b/src/portable/mentor/musb/musb_ti.h index 680bebde7..d17e836ee 100644 --- a/src/portable/mentor/musb/musb_ti.h +++ b/src/portable/mentor/musb/musb_ti.h @@ -42,8 +42,8 @@ #error "Unsupported MCUs" #endif -#define MUSB_CFG_SHARED_FIFO 0 -#define MUSB_CFG_DYNAMIC_FIFO 1 +#define MUSB_CFG_SHARED_FIFO 0 +#define MUSB_CFG_DYNAMIC_FIFO 1 #define MUSB_CFG_DYNAMIC_FIFO_SIZE 4096 const uintptr_t MUSB_BASES[] = { USB0_BASE }; @@ -51,11 +51,6 @@ const uintptr_t MUSB_BASES[] = { USB0_BASE }; // Header supports both device and host modes. Only include what's necessary #if CFG_TUD_ENABLED -// Mapping of peripheral instances to port. Currently just 1. -static USB0_Type* const musb_periph_inst[] = { - USB0 -}; - // Mapping of IRQ numbers to port. Currently just 1. static const IRQn_Type musb_irqs[] = { USB0_IRQn @@ -87,142 +82,6 @@ static inline void musb_dcd_int_handler_enter(uint8_t rhport) { //Nothing to do for this part } -#if 0 -typedef struct { - uint_fast16_t beg; /* offset of including first element */ - uint_fast16_t end; /* offset of excluding the last element */ -} free_block_t; - -static inline free_block_t *find_containing_block(free_block_t *beg, free_block_t *end, uint_fast16_t addr) { - free_block_t *cur = beg; - for (; cur < end && ((addr < cur->beg) || (cur->end <= addr)); ++cur) ; - return cur; -} - -static inline int update_free_block_list(free_block_t *blks, unsigned num, uint_fast16_t addr, uint_fast16_t size) { - free_block_t *p = find_containing_block(blks, blks + num, addr); - TU_ASSERT(p != blks + num, -2); - if (p->beg == addr) { - /* Shrink block */ - p->beg = addr + size; - if (p->beg != p->end) return 0; - /* remove block */ - free_block_t *end = blks + num; - while (p + 1 < end) { - *p = *(p + 1); - ++p; - } - return -1; - } else { - /* Split into 2 blocks */ - free_block_t tmp = { - .beg = addr + size, - .end = p->end - }; - p->end = addr; - if (p->beg == p->end) { - if (tmp.beg != tmp.end) { - *p = tmp; - return 0; - } - /* remove block */ - free_block_t *end = blks + num; - while (p + 1 < end) { - *p = *(p + 1); - ++p; - } - return -1; - } - if (tmp.beg == tmp.end) return 0; - blks[num] = tmp; - return 1; - } -} - -static inline unsigned free_block_size(free_block_t const *blk) { - return blk->end - blk->beg; -} - -#if 0 -static inline void print_block_list(free_block_t const *blk, unsigned num) -{ - TU_LOG1("*************\r\n"); - for (unsigned i = 0; i < num; ++i) { - TU_LOG1(" Blk%u %u %u\r\n", i, blk->beg, blk->end); - ++blk; - } -} -#else -#define print_block_list(a,b) -#endif - -static unsigned find_free_memory(uint8_t rhport, uint_fast16_t size_in_log2_minus3) -{ - free_block_t free_blocks[2 * (TUP_DCD_ENDPOINT_MAX - 1)]; - unsigned num_blocks = 1; - - /* Initialize free memory block list */ - free_blocks[0].beg = 64 / 8; - free_blocks[0].end = (4 << 10) / 8; /* 4KiB / 8 bytes */ - for (int i = 1; i < TUP_DCD_ENDPOINT_MAX; ++i) { - uint_fast16_t addr; - int num; - musb_periph_inst[rhport]->EPIDX = i; - addr = musb_periph_inst[rhport]->TXFIFOADD; - if (addr) { - unsigned sz = musb_periph_inst[rhport]->TXFIFOSZ; - unsigned sft = (sz & USB_TXFIFOSZ_SIZE_M) + ((sz & USB_TXFIFOSZ_DPB) ? 1: 0); - num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); - TU_ASSERT(-2 < num, 0); - num_blocks += num; - print_block_list(free_blocks, num_blocks); - } - addr = musb_periph_inst[rhport]->RXFIFOADD; - if (addr) { - unsigned sz = musb_periph_inst[rhport]->RXFIFOSZ; - unsigned sft = (sz & USB_RXFIFOSZ_SIZE_M) + ((sz & USB_RXFIFOSZ_DPB) ? 1: 0); - num = update_free_block_list(free_blocks, num_blocks, addr, 1 << sft); - TU_ASSERT(-2 < num, 0); - num_blocks += num; - print_block_list(free_blocks, num_blocks); - } - } - print_block_list(free_blocks, num_blocks); - - /* Find the best fit memory block */ - uint_fast16_t size_in_8byte_unit = 1 << size_in_log2_minus3; - free_block_t const *min = NULL; - uint_fast16_t min_sz = 0xFFFFu; - free_block_t const *end = &free_blocks[num_blocks]; - for (free_block_t const *cur = &free_blocks[0]; cur < end; ++cur) { - uint_fast16_t sz = free_block_size(cur); - if (sz < size_in_8byte_unit) continue; - if (size_in_8byte_unit == sz) return cur->beg; - if (sz < min_sz) min = cur; - } - TU_ASSERT(min, 0); - return min->beg; -} - - -static inline void musb_dcd_setup_fifo(uint8_t rhport, unsigned epnum, unsigned dir_in, unsigned mps) -{ - int size_in_log2_minus3 = 28 - TU_MIN(28, __CLZ((uint32_t)mps)); - if ((8u << size_in_log2_minus3) < mps) ++size_in_log2_minus3; - unsigned addr = find_free_memory(rhport, size_in_log2_minus3); - TU_ASSERT(addr,); - - musb_periph_inst[rhport]->EPIDX = epnum; - if (dir_in) { - musb_periph_inst[rhport]->TXFIFOADD = addr; - musb_periph_inst[rhport]->TXFIFOSZ = size_in_log2_minus3; - } else { - musb_periph_inst[rhport]->RXFIFOADD = addr; - musb_periph_inst[rhport]->RXFIFOSZ = size_in_log2_minus3; - } -} -#endif - #endif // CFG_TUD_ENABLED #ifdef __cplusplus diff --git a/src/portable/mentor/musb/musb_type.h b/src/portable/mentor/musb/musb_type.h index f8a66acce..4e448c0ed 100644 --- a/src/portable/mentor/musb/musb_type.h +++ b/src/portable/mentor/musb/musb_type.h @@ -338,6 +338,10 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ // 0x13, 0x17: TX/RX CSRH #define MUSB_CSRH_DISABLE_DOUBLE_PACKET(_rx) (1u << 1) #define MUSB_CSRH_TX_MODE (1u << 5) // 1 = TX, 0 = RX. only relevant for SHARED FIFO +#define MUSB_CSRH_ISO (1u << 6) + +// 0x62, 0x63: TXFIFO_SZ, RXFIFO_SZ +#define MUSB_FIFOSZ_DOUBLE_PACKET (1u << 4) //***************************************************************************** @@ -417,58 +421,6 @@ TU_ATTR_ALWAYS_INLINE static inline musb_ep_csr_t* get_ep_csr(musb_regs_t* musb_ #define MUSB_CCONF_TXEDMA 0x0002 // TX Early DMA Enable #define MUSB_CCONF_RXEDMA 0x0001 // TX Early DMA Enable -//***************************************************************************** -// -// The following are defines for the bit fields in the MUSB_O_TXFIFOSZ register. -// -//***************************************************************************** -#define MUSB_TXFIFOSZ_DPB 0x0010 // Double Packet Buffer Support -#define MUSB_TXFIFOSZ_SIZE_M 0x000F // Max Packet Size -#define MUSB_TXFIFOSZ_SIZE_8 0x0000 // 8 -#define MUSB_TXFIFOSZ_SIZE_16 0x0001 // 16 -#define MUSB_TXFIFOSZ_SIZE_32 0x0002 // 32 -#define MUSB_TXFIFOSZ_SIZE_64 0x0003 // 64 -#define MUSB_TXFIFOSZ_SIZE_128 0x0004 // 128 -#define MUSB_TXFIFOSZ_SIZE_256 0x0005 // 256 -#define MUSB_TXFIFOSZ_SIZE_512 0x0006 // 512 -#define MUSB_TXFIFOSZ_SIZE_1024 0x0007 // 1024 -#define MUSB_TXFIFOSZ_SIZE_2048 0x0008 // 2048 - -//***************************************************************************** -// -// The following are defines for the bit fields in the MUSB_O_RXFIFOSZ register. -// -//***************************************************************************** -#define MUSB_RXFIFOSZ_DPB 0x0010 // Double Packet Buffer Support -#define MUSB_RXFIFOSZ_SIZE_M 0x000F // Max Packet Size -#define MUSB_RXFIFOSZ_SIZE_8 0x0000 // 8 -#define MUSB_RXFIFOSZ_SIZE_16 0x0001 // 16 -#define MUSB_RXFIFOSZ_SIZE_32 0x0002 // 32 -#define MUSB_RXFIFOSZ_SIZE_64 0x0003 // 64 -#define MUSB_RXFIFOSZ_SIZE_128 0x0004 // 128 -#define MUSB_RXFIFOSZ_SIZE_256 0x0005 // 256 -#define MUSB_RXFIFOSZ_SIZE_512 0x0006 // 512 -#define MUSB_RXFIFOSZ_SIZE_1024 0x0007 // 1024 -#define MUSB_RXFIFOSZ_SIZE_2048 0x0008 // 2048 - -//***************************************************************************** -// -// The following are defines for the bit fields in the MUSB_O_TXFIFOADD -// register. -// -//***************************************************************************** -#define MUSB_TXFIFOADD_ADDR_M 0x01FF // Transmit/Receive Start Address -#define MUSB_TXFIFOADD_ADDR_S 0 - -//***************************************************************************** -// -// The following are defines for the bit fields in the MUSB_O_RXFIFOADD -// register. -// -//***************************************************************************** -#define MUSB_RXFIFOADD_ADDR_M 0x01FF // Transmit/Receive Start Address -#define MUSB_RXFIFOADD_ADDR_S 0 - //***************************************************************************** // // The following are defines for the bit fields in the MUSB_O_ULPIVBUSCTL -- cgit v1.3.1 From 0c9d7a21858d246dfaadb78122c27c6e4099109c Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 19 Aug 2024 12:38:45 +0700 Subject: add hwfifo_flush() --- src/portable/mentor/musb/dcd_musb.c | 72 ++++++++++++++++--------------------- 1 file changed, 31 insertions(+), 41 deletions(-) (limited to 'src/portable') diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index dc2753ea6..a40b3dc07 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -81,11 +81,13 @@ typedef struct uint16_t pipe_buf_is_fifo[2]; /* Bitmap. Each bit means whether 1:TU_FIFO or 0:POD. */ } dcd_data_t; -/*------------------------------------------------------------------ - * INTERNAL OBJECT & FUNCTION DECLARATION - *------------------------------------------------------------------*/ static dcd_data_t _dcd; +//-------------------------------------------------------------------- +// HW FIFO Helper +// Note: Index register is already set by caller +//-------------------------------------------------------------------- + #if MUSB_CFG_DYNAMIC_FIFO // musb is configured to use dynamic FIFO sizing. @@ -97,24 +99,20 @@ static uint32_t alloced_fifo_bytes; // ffsize is log2(mps) - 3 (round up) TU_ATTR_ALWAYS_INLINE static inline uint8_t hwfifo_byte2size(uint16_t nbytes) { uint8_t ffsize = 28 - tu_min8(28, __builtin_clz(nbytes)); - // round up to the next power of 2 if ((8u << ffsize) < nbytes) { ++ffsize; } - return ffsize; } -// index register is already set -TU_ATTR_ALWAYS_INLINE static inline void hwfifo_reset(musb_regs_t* musb, unsigned epnum, unsigned dir_in) { +TU_ATTR_ALWAYS_INLINE static inline void hwfifo_reset(musb_regs_t* musb, unsigned epnum, unsigned is_rx) { (void) epnum; - const uint8_t is_rx = 1 - dir_in; musb->fifo_size[is_rx] = 0; musb->fifo_addr[is_rx] = 0; } -// index register is already set -TU_ATTR_ALWAYS_INLINE static inline bool hwfifo_config(musb_regs_t* musb, unsigned epnum, unsigned dir_in, unsigned mps, bool double_packet) { +TU_ATTR_ALWAYS_INLINE static inline bool hwfifo_config(musb_regs_t* musb, unsigned epnum, unsigned is_rx, unsigned mps, + bool double_packet) { (void) epnum; uint8_t ffsize = hwfifo_byte2size(mps); mps = 8 << ffsize; // round up to the next power of 2 @@ -125,8 +123,6 @@ TU_ATTR_ALWAYS_INLINE static inline bool hwfifo_config(musb_regs_t* musb, unsign } TU_ASSERT(alloced_fifo_bytes + mps <= MUSB_CFG_DYNAMIC_FIFO_SIZE); - const uint8_t is_rx = 1 - dir_in; - musb->fifo_addr[is_rx] = alloced_fifo_bytes / 8; musb->fifo_size[is_rx] = ffsize; @@ -136,20 +132,16 @@ TU_ATTR_ALWAYS_INLINE static inline bool hwfifo_config(musb_regs_t* musb, unsign #else -// index register is already set -TU_ATTR_ALWAYS_INLINE static inline void hwfifo_reset(musb_regs_t* musb, unsigned epnum, unsigned dir_in) { - (void) musb; (void) epnum; (void) dir_in; +TU_ATTR_ALWAYS_INLINE static inline void hwfifo_reset(musb_regs_t* musb, unsigned epnum, unsigned is_rx) { + (void) musb; (void) epnum; (void) is_rx; // nothing to do for static FIFO } -// index register is already set -TU_ATTR_ALWAYS_INLINE static inline bool hwfifo_config(musb_regs_t* musb, unsigned epnum, unsigned dir_in, unsigned mps, +TU_ATTR_ALWAYS_INLINE static inline bool hwfifo_config(musb_regs_t* musb, unsigned epnum, unsigned is_rx, unsigned mps, bool double_packet) { - (void) epnum; (void) dir_in; (void) mps; - + (void) epnum; (void) mps; if (!double_packet) { #if defined(TUP_USBIP_MUSB_ADI) - const uint8_t is_rx = 1 - dir_in; musb->indexed_csr.maxp_csr[is_rx].csrh |= MUSB_CSRH_DISABLE_DOUBLE_PACKET(is_rx); #else if (is_rx) { @@ -165,6 +157,19 @@ TU_ATTR_ALWAYS_INLINE static inline bool hwfifo_config(musb_regs_t* musb, unsign #endif +// Flush FIFO and clear data toggle +TU_ATTR_ALWAYS_INLINE static inline void hwfifo_flush(musb_regs_t* musb, unsigned epnum, unsigned is_rx, bool clear_dtog) { + (void) epnum; + const uint8_t csrl_dtog = clear_dtog ? MUSB_CSRL_CLEAR_DATA_TOGGLE(is_rx) : 0; + musb_ep_maxp_csr_t* maxp_csr = &musb->indexed_csr.maxp_csr[is_rx]; + // may need to flush twice for double packet + for (unsigned i=0; i<2; i++) { + if (maxp_csr->csrl & MUSB_CSRL_PACKET_READY(is_rx)) { + maxp_csr->csrl = MUSB_CSRL_FLUSH_FIFO(is_rx) | csrl_dtog; + } + } +} + static void pipe_write_packet(void *buf, volatile void *fifo, unsigned len) { volatile hw_fifo_t *reg = (volatile hw_fifo_t*)fifo; @@ -679,14 +684,9 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { } #endif - // flush and reset data toggle - uint8_t csrl = MUSB_CSRL_CLEAR_DATA_TOGGLE(is_rx); - if (maxp_csr->csrl & MUSB_CSRL_PACKET_READY(is_rx)) { - csrl |= MUSB_CSRL_FLUSH_FIFO(is_rx); - } - maxp_csr->csrl = csrl; + hwfifo_flush(musb, epn, is_rx, true); - TU_ASSERT(hwfifo_config(musb, epn, dir_in, mps, false)); + TU_ASSERT(hwfifo_config(musb, epn, is_rx, mps, false)); musb->intren_ep[is_rx] |= TU_BIT(epn); return true; @@ -699,7 +699,7 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet musb_ep_csr_t* ep_csr = get_ep_csr(musb, epn); const uint8_t is_rx = 1 - dir_in; ep_csr->maxp_csr[is_rx].csrh = 0; - return hwfifo_config(musb, epn, dir_in, largest_packet_size, true); + return hwfifo_config(musb, epn, is_rx, largest_packet_size, true); } bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc ) { @@ -729,10 +729,7 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const *ep_desc ) } #endif - // flush fifo - if (maxp_csr->csrl & MUSB_CSRL_PACKET_READY(is_rx)) { - maxp_csr->csrl = MUSB_CSRL_FLUSH_FIFO(is_rx); - } + hwfifo_flush(musb, epn, is_rx, true); #if MUSB_CFG_DYNAMIC_FIFO // fifo space is already allocated, keep the address and just change packet size @@ -758,17 +755,10 @@ void dcd_edpt_close_all(uint8_t rhport) musb_ep_csr_t* ep_csr = get_ep_csr(musb, i); for (unsigned d = 0; d < 2; d++) { musb_ep_maxp_csr_t* maxp_csr = &ep_csr->maxp_csr[d]; + hwfifo_flush(musb, i, d, true); + hwfifo_reset(musb, i, d); maxp_csr->maxp = 0; maxp_csr->csrh = 0; - - // flush and reset data toggle - uint8_t csrl = MUSB_CSRL_CLEAR_DATA_TOGGLE(d); - if (maxp_csr->csrl & MUSB_CSRL_PACKET_READY(is_rx)) { - csrl |= MUSB_CSRL_FLUSH_FIFO(d); - } - maxp_csr->csrl = csrl; - - hwfifo_reset(musb, i, 1-d); } } -- cgit v1.3.1 From ea4f9ceb58f0aa6acc86bbe3083596a98b5355fd Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 19 Aug 2024 20:08:55 +0700 Subject: remove weak from dcd_edpt_close() for port without TUP_DCD_EDPT_ISO_ALLOC --- src/device/dcd.h | 2 +- src/portable/microchip/samg/dcd_samg.c | 5 +++++ src/portable/nxp/lpc17_40/dcd_lpc17_40.c | 5 +++++ src/portable/template/dcd_template.c | 16 ++++++++++++++++ src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 5 +++++ src/portable/valentyusb/eptri/dcd_eptri.c | 5 +++++ 6 files changed, 37 insertions(+), 1 deletion(-) (limited to 'src/portable') diff --git a/src/device/dcd.h b/src/device/dcd.h index d1d4e4897..3ef5188fc 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -181,7 +181,7 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep) #else // Close an endpoint. -void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) TU_ATTR_WEAK; +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr); #endif diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c index e3fa51e31..a15431937 100644 --- a/src/portable/microchip/samg/dcd_samg.c +++ b/src/portable/microchip/samg/dcd_samg.c @@ -277,6 +277,11 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) return true; } +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { + (void) rhport; (void) ep_addr; + // TODO implement dcd_edpt_close() +} + void dcd_edpt_close_all (uint8_t rhport) { (void) rhport; diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c index b880c2870..75b29faf3 100644 --- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c +++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c @@ -335,6 +335,11 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) return true; } +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { + (void) rhport; (void) ep_addr; + // TODO implement dcd_edpt_close() +} + void dcd_edpt_close_all (uint8_t rhport) { (void) rhport; diff --git a/src/portable/template/dcd_template.c b/src/portable/template/dcd_template.c index 12d610bd6..25ee507c1 100644 --- a/src/portable/template/dcd_template.c +++ b/src/portable/template/dcd_template.c @@ -102,6 +102,22 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) return false; } +// Allocate packet buffer used by ISO endpoints +// Some MCU need manual packet buffer allocation, we allocate the largest size to avoid clustering +bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { + (void) rhport; + (void) ep_addr; + (void) largest_packet_size; + return false; +} + +// Configure and enable an ISO endpoint according to descriptor +bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep) { + (void) rhport; + (void) desc_ep; + return false; +} + void dcd_edpt_close_all (uint8_t rhport) { (void) rhport; diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 8005f5f7b..6b60bc657 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -332,6 +332,11 @@ bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt) return true; } +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { + (void) rhport; (void) ep_addr; + // TODO implement dcd_edpt_close() +} + void dcd_edpt_close_all (uint8_t rhport) { (void) rhport; diff --git a/src/portable/valentyusb/eptri/dcd_eptri.c b/src/portable/valentyusb/eptri/dcd_eptri.c index 58628a8bb..8f40e3349 100644 --- a/src/portable/valentyusb/eptri/dcd_eptri.c +++ b/src/portable/valentyusb/eptri/dcd_eptri.c @@ -436,6 +436,11 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) return true; } +void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { + (void) rhport; (void) ep_addr; + // TODO implement dcd_edpt_close() +} + void dcd_edpt_close_all (uint8_t rhport) { (void) rhport; -- cgit v1.3.1 From 5bb2e66ce774fe174742f0893d82cb7895285983 Mon Sep 17 00:00:00 2001 From: Cumhur Onat Date: Sun, 21 Jul 2024 21:22:19 -0400 Subject: fix for out retry attempts with nak response --- src/portable/analog/max3421/hcd_max3421.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) (limited to 'src/portable') diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index d9b8e1fc3..342edef89 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -203,12 +203,13 @@ typedef struct { uint16_t packet_size : 11; }; + bool received_nak; uint16_t total_len; uint16_t xferred_len; uint8_t* buf; } max3421_ep_t; -TU_VERIFY_STATIC(sizeof(max3421_ep_t) == 12, "size is not correct"); +TU_VERIFY_STATIC(sizeof(max3421_ep_t) == 16, "size is not correct"); typedef struct { volatile uint16_t frame_count; @@ -625,12 +626,17 @@ static void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_i reg_write(rhport, HCTL_ADDR, hctl, in_isr); } - uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size); - TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,); - if (xact_len) { - fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr); + if (!ep->received_nak){ + // do not write to fifo or sdnbc register again if previous attempt got NAK + uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size); + TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,); + if (xact_len) { + fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr); + } + + sndbc_write(rhport, xact_len, in_isr); } - sndbc_write(rhport, xact_len, in_isr); + hxfr_write(rhport, ep->hxfr, in_isr); } @@ -844,6 +850,7 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) { return; } else if (EP_STATE_ATTEMPT_1 <= ep->state && ep->state < EP_STATE_ATTEMPT_MAX) { ep->state++; + ep->received_nak = true; } } @@ -867,6 +874,7 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) { case HRSL_SUCCESS: xfer_result = XFER_RESULT_SUCCESS; + ep->received_nak = false; break; case HRSL_STALL: -- cgit v1.3.1 From c7851e8dcbdac8f895cfe81f2479bc6fcfcc524a Mon Sep 17 00:00:00 2001 From: Cumhur Onat Date: Sun, 21 Jul 2024 23:32:48 -0400 Subject: only check SNDBAV IRQ if there is data to send --- src/portable/analog/max3421/hcd_max3421.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/portable') diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 342edef89..3d054b66e 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -629,8 +629,9 @@ static void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_i if (!ep->received_nak){ // do not write to fifo or sdnbc register again if previous attempt got NAK uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size); - TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,); if (xact_len) { + // only check SNDBAV IRQ if there is data to send + TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,); fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr); } -- cgit v1.3.1 From 27ddf19631d135df15f3388686f59e379e146dbb Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 26 Aug 2024 12:24:29 +0700 Subject: add sndfifo owner info to skip rewriting data for retrying NAKed --- README.rst | 2 +- hw/bsp/family_support.cmake | 6 + src/host/usbh.h | 2 +- src/portable/analog/max3421/hcd_max3421.c | 191 +++++++++++++++++++----------- 4 files changed, 127 insertions(+), 74 deletions(-) (limited to 'src/portable') diff --git a/README.rst b/README.rst index 6dd0e2714..2ffe3823a 100644 --- a/README.rst +++ b/README.rst @@ -197,7 +197,7 @@ Docs - `Structure`_ - `Porting`_ -.. |Build Status| image:: https://github.com/hathach/tinyusb/actions/workflows/cmake_arm.yml/badge.svg +.. |Build Status| image:: https://github.com/hathach/tinyusb/actions/workflows/build.yml/badge.svg :target: https://github.com/hathach/tinyusb/actions .. |CircleCI Status| image:: https://dl.circleci.com/status-badge/img/circleci/4AYHvUhFxdnY4rA7LEsdqW/QmrpoL2AjGqetvFQNqtWyq/tree/master.svg?style=svg :target: https://dl.circleci.com/status-badge/redirect/circleci/4AYHvUhFxdnY4rA7LEsdqW/QmrpoL2AjGqetvFQNqtWyq/tree/master diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index b457fcfac..aa5e037d1 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -418,6 +418,12 @@ exit" COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} ${OPTION_LIST} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $/${TARGET}.jlink VERBATIM ) + + # optional flash post build +# add_custom_command(TARGET ${TARGET} POST_BUILD +# COMMAND ${JLINKEXE} -device ${JLINK_DEVICE} ${OPTION_LIST} -if ${JLINK_IF} -JTAGConf -1,-1 -speed auto -CommandFile $/${TARGET}.jlink +# VERBATIM +# ) endfunction() diff --git a/src/host/usbh.h b/src/host/usbh.h index 359684169..d0a5732e5 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -81,7 +81,7 @@ enum { }; typedef struct { - uint8_t max_nak; // max NAK per endpoint per frame + uint8_t max_nak; // max NAK per endpoint per frame to save CPU/SPI bus usage uint8_t cpuctl; // R16: CPU Control Register uint8_t pinctl; // R17: Pin Control Register. FDUPSPI bit is ignored } tuh_configure_max3421_t; diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 3d054b66e..215feb481 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -168,14 +168,14 @@ enum { }; enum { - MAX_NAK_DEFAULT = 1 // Number of NAK per endpoint per usb frame + MAX_NAK_DEFAULT = 1 // Number of NAK per endpoint per usb frame to save CPU/SPI bus usage }; enum { EP_STATE_IDLE = 0, EP_STATE_COMPLETE = 1, EP_STATE_ABORTING = 2, - EP_STATE_ATTEMPT_1 = 3, // pending 1st attempt + EP_STATE_ATTEMPT_1 = 3, // Number of attempts to transfer in a frame. Incremented after each NAK EP_STATE_ATTEMPT_MAX = 15 }; @@ -183,17 +183,20 @@ enum { // //--------------------------------------------------------------------+ +typedef struct TU_ATTR_PACKED { + uint8_t ep_num : 4; + uint8_t is_setup : 1; + uint8_t is_out : 1; + uint8_t is_iso : 1; +} hxfr_bm_t; + +TU_VERIFY_STATIC(sizeof(hxfr_bm_t) == 1, "size is not correct"); + typedef struct { uint8_t daddr; - union { ; - struct TU_ATTR_PACKED { - uint8_t ep_num : 4; - uint8_t is_setup : 1; - uint8_t is_out : 1; - uint8_t is_iso : 1; - }hxfr_bm; - + union { + hxfr_bm_t hxfr_bm; uint8_t hxfr; }; @@ -203,13 +206,12 @@ typedef struct { uint16_t packet_size : 11; }; - bool received_nak; uint16_t total_len; uint16_t xferred_len; uint8_t* buf; } max3421_ep_t; -TU_VERIFY_STATIC(sizeof(max3421_ep_t) == 16, "size is not correct"); +TU_VERIFY_STATIC(sizeof(max3421_ep_t) == 12, "size is not correct"); typedef struct { volatile uint16_t frame_count; @@ -220,7 +222,16 @@ typedef struct { uint8_t hien; uint8_t mode; uint8_t peraddr; - uint8_t hxfr; + union { + hxfr_bm_t hxfr_bm; + uint8_t hxfr; + }; + + // owner of data in SNDFIFO, for retrying NAKed without re-writing to FIFO + struct { + uint8_t daddr; + uint8_t hxfr; + }sndfifo_owner; atomic_flag busy; // busy transferring @@ -318,33 +329,9 @@ bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_is return ret; } -static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint16_t len, bool in_isr) { - uint8_t hirq; - reg |= CMDBYTE_WRITE; - - max3421_spi_lock(rhport, in_isr); - - tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); - _hcd_data.hirq = hirq; - tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len); - - max3421_spi_unlock(rhport, in_isr); -} - -static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) { - uint8_t hirq; - uint8_t const reg = RCVVFIFO_ADDR; - - max3421_spi_lock(rhport, in_isr); - - tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); - _hcd_data.hirq = hirq; - tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len); - - max3421_spi_unlock(rhport, in_isr); -} - -//------------- register write helper -------------// +//-------------------------------------------------------------------- +// Register helper +//-------------------------------------------------------------------- TU_ATTR_ALWAYS_INLINE static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) { reg_write(rhport, HIRQ_ADDR, data, in_isr); // HIRQ write 1 is clear @@ -378,6 +365,47 @@ TU_ATTR_ALWAYS_INLINE static inline void sndbc_write(uint8_t rhport, uint8_t dat reg_write(rhport, SNDBC_ADDR, data, in_isr); } +//-------------------------------------------------------------------- +// FIFO access (receive, send, setup) +//-------------------------------------------------------------------- +static void hwfifo_write(uint8_t rhport, uint8_t reg, const uint8_t* buffer, uint8_t len, bool in_isr) { + uint8_t hirq; + reg |= CMDBYTE_WRITE; + + max3421_spi_lock(rhport, in_isr); + + tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); + _hcd_data.hirq = hirq; + tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len); + + max3421_spi_unlock(rhport, in_isr); +} + +// Write to SNDFIFO if len > 0 and update SNDBC +TU_ATTR_ALWAYS_INLINE static inline void hwfifo_send(uint8_t rhport, const uint8_t* buffer, uint8_t len, bool in_isr) { + if (len) { + hwfifo_write(rhport, SNDFIFO_ADDR, buffer, len, in_isr); + } + sndbc_write(rhport, len, in_isr); +} + +TU_ATTR_ALWAYS_INLINE static inline void hwfifo_setup(uint8_t rhport, const uint8_t* buffer, bool in_isr) { + hwfifo_write(rhport, SUDFIFO_ADDR, buffer, 8, in_isr); +} + +static void hwfifo_receive(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) { + uint8_t hirq; + uint8_t const reg = RCVVFIFO_ADDR; + + max3421_spi_lock(rhport, in_isr); + + tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); + _hcd_data.hirq = hirq; + tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len); + + max3421_spi_unlock(rhport, in_isr); +} + //--------------------------------------------------------------------+ // Endpoint helper //--------------------------------------------------------------------+ @@ -418,7 +446,7 @@ static void free_ep(uint8_t daddr) { } } -// Check if endpoint has an queued transfer and not reach max NAK +// Check if endpoint has a queued transfer and not reach max NAK in this frame TU_ATTR_ALWAYS_INLINE static inline bool is_ep_pending(max3421_ep_t const * ep) { uint8_t const state = ep->state; return ep->packet_size && (state >= EP_STATE_ATTEMPT_1) && @@ -488,6 +516,7 @@ bool hcd_init(uint8_t rhport) { reg_write(rhport, PINCTL_ADDR, _tuh_cfg.pinctl | PINCTL_FDUPSPI, false); // v1 is 0x01, v2 is 0x12, v3 is 0x13 + // Note: v1 and v2 has host OUT errata whose workaround is not implemented in this driver uint8_t const revision = reg_read(rhport, REVISION_ADDR, false); TU_LOG2_HEX(revision); TU_ASSERT(revision == 0x01 || revision == 0x12 || revision == 0x13, false); @@ -616,27 +645,44 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e return true; } +/* The microcontroller repeatedly writes the SNDFIFO register R2 to load the FIFO with up to 64 data bytes. + * Then the microcontroller writes the SNDBC register, which this does three things: + * 1. Tells the MAX3421E SIE (Serial Interface Engine) how many bytes in the FIFO to send. + * 2. Connects the SNDFIFO and SNDBC register to the USB logic for USB transmission. + * 3. Clears the SNDBAVIRQ interrupt flag. If the second FIFO is available for µC loading, the SNDBAVIRQ immediately re-asserts. + + +-----------+ + --->| SNDBC-A | + / | SNDFIFO-A | + / +-----------+ + +------+ +-------------+ / +----------+ + | MCU |------>| R2: SNDFIFO |---- << Write R7 Flip >> ---| MAX3241E | + |(hcd) | | R7: SNDBC | / | SIE | + +------+ +-------------+ / +----------+ + +-----------+ / + | SNDBC-B | / + | SNDFIFO-B |<--- + +-----------+ + Note: xact_out() is called when starting a new transfer, continue a transfer (isr) or retry a transfer (NAK) + For NAK retry, we do not need to write to FIFO or SNDBC register again. +*/ static void xact_out(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_isr) { // Page 12: Programming BULK-OUT Transfers - // TODO double buffered + // TODO: double buffering for ISO transfer if (switch_ep) { peraddr_write(rhport, ep->daddr, in_isr); - - uint8_t const hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0); + const uint8_t hctl = (ep->data_toggle ? HCTL_SNDTOG1 : HCTL_SNDTOG0); reg_write(rhport, HCTL_ADDR, hctl, in_isr); } - if (!ep->received_nak){ - // do not write to fifo or sdnbc register again if previous attempt got NAK - uint8_t const xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size); - if (xact_len) { - // only check SNDBAV IRQ if there is data to send - TU_ASSERT(_hcd_data.hirq & HIRQ_SNDBAV_IRQ,); - fifo_write(rhport, SNDFIFO_ADDR, ep->buf, xact_len, in_isr); - } - - sndbc_write(rhport, xact_len, in_isr); + // Only write to sndfifo and sdnbc register if it is not a NAKed retry + if (!(ep->daddr == _hcd_data.sndfifo_owner.daddr && ep->hxfr == _hcd_data.sndfifo_owner.hxfr)) { + // skip SNDBAV IRQ check, overwrite sndfifo if needed + const uint8_t xact_len = (uint8_t) tu_min16(ep->total_len - ep->xferred_len, ep->packet_size); + hwfifo_send(rhport, ep->buf, xact_len, in_isr); } + _hcd_data.sndfifo_owner.daddr = ep->daddr; + _hcd_data.sndfifo_owner.hxfr = ep->hxfr; hxfr_write(rhport, ep->hxfr, in_isr); } @@ -655,7 +701,7 @@ static void xact_in(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool in_is static void xact_setup(uint8_t rhport, max3421_ep_t *ep, bool in_isr) { peraddr_write(rhport, ep->daddr, in_isr); - fifo_write(rhport, SUDFIFO_ADDR, ep->buf, 8, in_isr); + hwfifo_setup(rhport, ep->buf, in_isr); hxfr_write(rhport, HXFR_SETUP, in_isr); } @@ -669,7 +715,7 @@ static void xact_generic(uint8_t rhport, max3421_ep_t *ep, bool switch_ep, bool // status if (ep->buf == NULL || ep->total_len == 0) { - uint8_t const hxfr = (uint8_t) (HXFR_HS | (ep->hxfr & HXFR_OUT_NIN)); + const uint8_t hxfr = (uint8_t) (HXFR_HS | (ep->hxfr & HXFR_OUT_NIN)); peraddr_write(rhport, ep->daddr, in_isr); hxfr_write(rhport, hxfr, in_isr); return; @@ -830,11 +876,11 @@ static void xfer_complete_isr(uint8_t rhport, max3421_ep_t *ep, xfer_result_t re } static void handle_xfer_done(uint8_t rhport, bool in_isr) { - uint8_t const hrsl = reg_read(rhport, HRSL_ADDR, in_isr); - uint8_t const hresult = hrsl & HRSL_RESULT_MASK; - uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; - uint8_t const hxfr_type = _hcd_data.hxfr & 0xf0; - uint8_t const ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1; + const uint8_t hrsl = reg_read(rhport, HRSL_ADDR, in_isr); + const uint8_t hresult = hrsl & HRSL_RESULT_MASK; + const uint8_t ep_num = _hcd_data.hxfr_bm.ep_num; + const uint8_t hxfr_type = _hcd_data.hxfr & 0xf0; + const uint8_t ep_dir = ((hxfr_type & HXFR_SETUP) || (hxfr_type & HXFR_OUT_NIN)) ? 0 : 1; max3421_ep_t *ep = find_opened_ep(_hcd_data.peraddr, ep_num, ep_dir); TU_VERIFY(ep, ); @@ -849,9 +895,9 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) { // control endpoint -> retry immediately and return hxfr_write(rhport, _hcd_data.hxfr, in_isr); return; - } else if (EP_STATE_ATTEMPT_1 <= ep->state && ep->state < EP_STATE_ATTEMPT_MAX) { + } + if (EP_STATE_ATTEMPT_1 <= ep->state && ep->state < EP_STATE_ATTEMPT_MAX) { ep->state++; - ep->received_nak = true; } } @@ -861,7 +907,6 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) { hxfr_write(rhport, _hcd_data.hxfr, in_isr); } else if (next_ep) { // switch to next pending endpoint - // TODO could have issue with double buffered if not clear previously out data xact_generic(rhport, next_ep, true, in_isr); } else { // no more pending in this frame -> clear busy @@ -875,7 +920,6 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) { case HRSL_SUCCESS: xfer_result = XFER_RESULT_SUCCESS; - ep->received_nak = false; break; case HRSL_STALL: @@ -905,11 +949,15 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) { if (ep->state == EP_STATE_COMPLETE) { xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr); }else { - // more to transfer - hxfr_write(rhport, _hcd_data.hxfr, in_isr); + hxfr_write(rhport, _hcd_data.hxfr, in_isr); // more to transfer } } else { // SETUP or OUT transfer + + // clear sndfifo owner since data is sent + _hcd_data.sndfifo_owner.daddr = 0xff; + _hcd_data.sndfifo_owner.hxfr = 0xff; + uint8_t xact_len; if (hxfr_type & HXFR_SETUP) { @@ -926,8 +974,7 @@ static void handle_xfer_done(uint8_t rhport, bool in_isr) { if (xact_len < ep->packet_size || ep->xferred_len >= ep->total_len) { xfer_complete_isr(rhport, ep, xfer_result, hrsl, in_isr); } else { - // more to transfer - xact_out(rhport, ep, false, in_isr); + xact_out(rhport, ep, false, in_isr); // more to transfer } } } @@ -987,16 +1034,16 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { // not call this handler again. So we need to loop until all IRQ are cleared while (hirq & (HIRQ_RCVDAV_IRQ | HIRQ_HXFRDN_IRQ)) { if (hirq & HIRQ_RCVDAV_IRQ) { - uint8_t const ep_num = _hcd_data.hxfr & HXFR_EPNUM_MASK; + const uint8_t ep_num = _hcd_data.hxfr_bm.ep_num; max3421_ep_t* ep = find_opened_ep(_hcd_data.peraddr, ep_num, 1); uint8_t xact_len = 0; // RCVDAV_IRQ can trigger 2 times (dual buffered) while (hirq & HIRQ_RCVDAV_IRQ) { - uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, in_isr); + const uint8_t rcvbc = reg_read(rhport, RCVBC_ADDR, in_isr); xact_len = (uint8_t) tu_min16(rcvbc, ep->total_len - ep->xferred_len); if (xact_len) { - fifo_read(rhport, ep->buf, xact_len, in_isr); + hwfifo_receive(rhport, ep->buf, xact_len, in_isr); ep->buf += xact_len; ep->xferred_len += xact_len; } -- cgit v1.3.1 From 1d2c9f929dd3bfaf82741da30e8dbf97b0ff385c Mon Sep 17 00:00:00 2001 From: Reinhard Griech Date: Thu, 29 Aug 2024 15:31:29 +0200 Subject: change order, fixes #2778 --- src/portable/nordic/nrf5x/dcd_nrf5x.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/portable') diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index 1cc5c1836..a63e442f3 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -441,11 +441,11 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to bool const control_status = (epnum == 0 && total_bytes == 0 && dir != tu_edpt_dir(NRF_USBD->BMREQUESTTYPE)); if (control_status) { - // Status Phase also requires EasyDMA has to be available as well !!!! - edpt_dma_start(&NRF_USBD->TASKS_EP0STATUS); - // The nRF doesn't interrupt on status transmit so we queue up a success response. dcd_event_xfer_complete(0, ep_addr, 0, XFER_RESULT_SUCCESS, is_in_isr()); + + // Status Phase also requires EasyDMA has to be available as well !!!! + edpt_dma_start(&NRF_USBD->TASKS_EP0STATUS); } else if (dir == TUSB_DIR_OUT) { xfer->started = true; if (epnum == 0) { -- cgit v1.3.1 From 6890975f80bb541ba4f229cc1c3bc165745e21ac Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Thu, 29 Aug 2024 14:04:49 -0700 Subject: Fix ESP32-SX resume The interrupt handler pipes through the resume event but the interrupt wasn't enabled in the first place. --- src/portable/espressif/esp32sx/dcd_esp32sx.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/portable') diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c index f912bef89..61911ab4c 100644 --- a/src/portable/espressif/esp32sx/dcd_esp32sx.c +++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c @@ -207,6 +207,7 @@ void dcd_init(uint8_t rhport) USB_USBRSTMSK_M | USB_ENUMDONEMSK_M | USB_RESETDETMSK_M | + USB_WKUPINT_M | USB_DISCONNINTMSK_M; // host most only dcd_connect(rhport); -- cgit v1.3.1 From 0bb7b992d8383e30a84d0114537ce777fb9d678e Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 4 Sep 2024 20:56:04 +0700 Subject: dwc2: for esp32 force disconnect/connect using USB_WRAP otg pad override (DM=DP=0) in addition to dwc2's dctrl --- .github/actions/setup_toolchain/action.yml | 2 - .../actions/setup_toolchain/espressif/action.yml | 2 +- src/common/tusb_mcu.h | 1 + src/portable/synopsys/dwc2/dcd_dwc2.c | 24 +++++++++++- src/portable/synopsys/dwc2/dwc2_esp32.h | 44 +++++++++------------- 5 files changed, 43 insertions(+), 30 deletions(-) (limited to 'src/portable') diff --git a/.github/actions/setup_toolchain/action.yml b/.github/actions/setup_toolchain/action.yml index d173d6903..5b9bc95ce 100644 --- a/.github/actions/setup_toolchain/action.yml +++ b/.github/actions/setup_toolchain/action.yml @@ -39,8 +39,6 @@ runs: TOOLCHAIN_JSON='{ "aarch64-gcc": "https://developer.arm.com/-/media/Files/downloads/gnu-a/10.3-2021.07/binrel/gcc-arm-10.3-2021.07-x86_64-aarch64-none-elf.tar.xz", "arm-clang": "https://github.com/ARM-software/LLVM-embedded-toolchain-for-Arm/releases/download/release-17.0.1/LLVMEmbeddedToolchainForArm-17.0.1-Linux-x86_64.tar.xz", - "arm-iar": "", - "arm-gcc": "", "msp430-gcc": "http://software-dl.ti.com/msp430/msp430_public_sw/mcu/msp430/MSPGCC/9_2_0_0/export/msp430-gcc-9.2.0.50_linux64.tar.bz2", "riscv-gcc": "https://github.com/xpack-dev-tools/riscv-none-elf-gcc-xpack/releases/download/v13.2.0-2/xpack-riscv-none-elf-gcc-13.2.0-2-linux-x64.tar.gz", "rx-gcc": "http://gcc-renesas.com/downloads/get.php?f=rx/8.3.0.202004-gnurx/gcc-8.3.0.202004-GNURX-ELF.run" diff --git a/.github/actions/setup_toolchain/espressif/action.yml b/.github/actions/setup_toolchain/espressif/action.yml index 3129329dd..1e3ce18f1 100644 --- a/.github/actions/setup_toolchain/espressif/action.yml +++ b/.github/actions/setup_toolchain/espressif/action.yml @@ -5,7 +5,7 @@ inputs: description: 'Toolchain name' required: true toolchain_version: - description: 'Toolchain URL or version' + description: 'Toolchain version' required: true runs: diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 52debf079..0a4462a0a 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -336,6 +336,7 @@ //--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_ESP32 #define TUP_DCD_ENDPOINT_MAX 6 #elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 9a38b46dc..daed76105 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -43,7 +43,7 @@ #if defined(TUP_USBIP_DWC2_STM32) #include "dwc2_stm32.h" -#elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) +#elif defined(TUP_USBIP_DWC2_ESP32) #include "dwc2_esp32.h" #elif TU_CHECK_MCU(OPT_MCU_GD32VF103) #include "dwc2_gd32.h" @@ -667,12 +667,34 @@ void dcd_remote_wakeup(uint8_t rhport) { void dcd_connect(uint8_t rhport) { (void) rhport; dwc2_regs_t* dwc2 = DWC2_REG(rhport); + +#ifdef TUP_USBIP_DWC2_ESP32 + usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf; + conf.pad_pull_override = 0; + conf.dp_pullup = 0; + conf.dp_pulldown = 0; + conf.dm_pullup = 0; + conf.dm_pulldown = 0; + USB_WRAP.otg_conf = conf; +#endif + dwc2->dctl &= ~DCTL_SDIS; } void dcd_disconnect(uint8_t rhport) { (void) rhport; dwc2_regs_t* dwc2 = DWC2_REG(rhport); + +#ifdef TUP_USBIP_DWC2_ESP32 + usb_wrap_otg_conf_reg_t conf = USB_WRAP.otg_conf; + conf.pad_pull_override = 1; + conf.dp_pullup = 0; + conf.dp_pulldown = 1; + conf.dm_pullup = 0; + conf.dm_pulldown = 1; + USB_WRAP.otg_conf = conf; +#endif + dwc2->dctl |= DCTL_SDIS; } diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index 932f52f40..1a938ea46 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -32,60 +32,52 @@ extern "C" { #endif +#include "freertos/task.h" + #include "esp_intr_alloc.h" #include "soc/periph_defs.h" -//#include "soc/usb_periph.h" -#include "freertos/task.h" +#include "soc/usb_wrap_struct.h" #define DWC2_REG_BASE 0x60080000UL #define DWC2_EP_MAX 6 // USB_OUT_EP_NUM. TODO ESP32Sx only has 5 tx fifo (5 endpoint IN) -static const dwc2_controller_t _dwc2_controller[] = -{ +static const dwc2_controller_t _dwc2_controller[] = { { .reg_base = DWC2_REG_BASE, .irqnum = 0, .ep_count = DWC2_EP_MAX, .ep_fifo_size = 1024 } }; static intr_handle_t usb_ih; -static void dcd_int_handler_wrap(void* arg) -{ - (void) arg; +static void dcd_int_handler_wrap(void* arg) { + (void)arg; dcd_int_handler(0); } -TU_ATTR_ALWAYS_INLINE -static inline void dwc2_dcd_int_enable (uint8_t rhport) -{ - (void) rhport; +TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { + (void)rhport; esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, dcd_int_handler_wrap, NULL, &usb_ih); } -TU_ATTR_ALWAYS_INLINE -static inline void dwc2_dcd_int_disable (uint8_t rhport) -{ - (void) rhport; +TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) { + (void)rhport; esp_intr_free(usb_ih); } -static inline void dwc2_remote_wakeup_delay(void) -{ +TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { vTaskDelay(pdMS_TO_TICKS(1)); } // MCU specific PHY init, called BEFORE core reset -static inline void dwc2_phy_init(dwc2_regs_t * dwc2, uint8_t hs_phy_type) -{ - (void) dwc2; - (void) hs_phy_type; +TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { + (void)dwc2; + (void)hs_phy_type; // nothing to do } // MCU specific PHY update, it is called AFTER init() and core reset -static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) -{ - (void) dwc2; - (void) hs_phy_type; +TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { + (void)dwc2; + (void)hs_phy_type; // nothing to do } @@ -94,4 +86,4 @@ static inline void dwc2_phy_update(dwc2_regs_t * dwc2, uint8_t hs_phy_type) } #endif -#endif /* _DWC2_ESP32_H_ */ +#endif -- cgit v1.3.1 From 616532892d913b7224806ed1e881b72ed66bb3e1 Mon Sep 17 00:00:00 2001 From: Shawn Hoffman Date: Tue, 17 Sep 2024 12:17:12 -0700 Subject: make all python files executable and standardize interpreter --- .github/workflows/ci_set_matrix.py | 1 + docs/conf.py | 1 + examples/device/audio_4_channel_mic/src/plot_audio_samples.py | 1 + examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py | 1 + examples/device/audio_test/src/plot_audio_samples.py | 1 + examples/device/audio_test_freertos/src/plot_audio_samples.py | 1 + examples/device/audio_test_multi_rate/src/plot_audio_samples.py | 1 + examples/device/hid_generic_inout/hid_test.py | 1 + examples/device/uac2_speaker_fb/src/audio_debug.py | 1 + examples/device/usbtmc/visaQuery.py | 0 hw/bsp/fomu/dfu.py | 2 +- hw/mcu/sony/cxd56/tools/flash_writer.py | 2 +- hw/mcu/sony/cxd56/tools/xmodem.py | 1 + src/portable/synopsys/dwc2/dwc2_info.py | 1 + test/hil/hil_test.py | 1 + test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py | 2 +- test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py | 1 + tools/build.py | 1 + tools/build_utils.py | 1 + tools/gen_doc.py | 1 + tools/get_deps.py | 1 + tools/iar_gen.py | 2 +- tools/make_release.py | 1 + tools/mksunxi.py | 0 tools/pcapng_to_corpus.py | 2 +- 25 files changed, 23 insertions(+), 5 deletions(-) mode change 100644 => 100755 .github/workflows/ci_set_matrix.py mode change 100644 => 100755 docs/conf.py mode change 100644 => 100755 examples/device/audio_4_channel_mic/src/plot_audio_samples.py mode change 100644 => 100755 examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py mode change 100644 => 100755 examples/device/audio_test/src/plot_audio_samples.py mode change 100644 => 100755 examples/device/audio_test_freertos/src/plot_audio_samples.py mode change 100644 => 100755 examples/device/audio_test_multi_rate/src/plot_audio_samples.py mode change 100644 => 100755 examples/device/hid_generic_inout/hid_test.py mode change 100644 => 100755 examples/device/uac2_speaker_fb/src/audio_debug.py mode change 100644 => 100755 examples/device/usbtmc/visaQuery.py mode change 100644 => 100755 hw/bsp/fomu/dfu.py mode change 100644 => 100755 hw/mcu/sony/cxd56/tools/xmodem.py mode change 100644 => 100755 src/portable/synopsys/dwc2/dwc2_info.py mode change 100644 => 100755 test/hil/hil_test.py mode change 100644 => 100755 test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py mode change 100644 => 100755 test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py mode change 100644 => 100755 tools/build.py mode change 100644 => 100755 tools/build_utils.py mode change 100644 => 100755 tools/gen_doc.py mode change 100644 => 100755 tools/get_deps.py mode change 100644 => 100755 tools/iar_gen.py mode change 100644 => 100755 tools/make_release.py mode change 100644 => 100755 tools/mksunxi.py (limited to 'src/portable') diff --git a/.github/workflows/ci_set_matrix.py b/.github/workflows/ci_set_matrix.py old mode 100644 new mode 100755 index 4da26bfea..fde6e81d6 --- a/.github/workflows/ci_set_matrix.py +++ b/.github/workflows/ci_set_matrix.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import json # toolchain, url diff --git a/docs/conf.py b/docs/conf.py old mode 100644 new mode 100755 index 878b29645..af44b7339 --- a/docs/conf.py +++ b/docs/conf.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 # Configuration file for the Sphinx documentation builder. # # This file only contains a selection of the most common options. For a full diff --git a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py old mode 100644 new mode 100755 index d17a908b6..4d61e7f5e --- a/examples/device/audio_4_channel_mic/src/plot_audio_samples.py +++ b/examples/device/audio_4_channel_mic/src/plot_audio_samples.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import sounddevice as sd import matplotlib.pyplot as plt import numpy as np diff --git a/examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py b/examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py old mode 100644 new mode 100755 index 8312b4e28..4d5ca28d6 --- a/examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py +++ b/examples/device/audio_4_channel_mic_freertos/src/plot_audio_samples.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import sounddevice as sd import matplotlib.pyplot as plt import numpy as np diff --git a/examples/device/audio_test/src/plot_audio_samples.py b/examples/device/audio_test/src/plot_audio_samples.py old mode 100644 new mode 100755 index 1504684a6..ea6aa661e --- a/examples/device/audio_test/src/plot_audio_samples.py +++ b/examples/device/audio_test/src/plot_audio_samples.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import sounddevice as sd import matplotlib.pyplot as plt import numpy as np diff --git a/examples/device/audio_test_freertos/src/plot_audio_samples.py b/examples/device/audio_test_freertos/src/plot_audio_samples.py old mode 100644 new mode 100755 index 304b2d5de..46738eb3f --- a/examples/device/audio_test_freertos/src/plot_audio_samples.py +++ b/examples/device/audio_test_freertos/src/plot_audio_samples.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import sounddevice as sd import matplotlib.pyplot as plt import numpy as np diff --git a/examples/device/audio_test_multi_rate/src/plot_audio_samples.py b/examples/device/audio_test_multi_rate/src/plot_audio_samples.py old mode 100644 new mode 100755 index c92e49957..1f33a003e --- a/examples/device/audio_test_multi_rate/src/plot_audio_samples.py +++ b/examples/device/audio_test_multi_rate/src/plot_audio_samples.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import sounddevice as sd import matplotlib.pyplot as plt import numpy as np diff --git a/examples/device/hid_generic_inout/hid_test.py b/examples/device/hid_generic_inout/hid_test.py old mode 100644 new mode 100755 index 5bdba9db0..3aaca9d2c --- a/examples/device/hid_generic_inout/hid_test.py +++ b/examples/device/hid_generic_inout/hid_test.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 # Install python3 HID package https://pypi.org/project/hid/ import hid diff --git a/examples/device/uac2_speaker_fb/src/audio_debug.py b/examples/device/uac2_speaker_fb/src/audio_debug.py old mode 100644 new mode 100755 index 336c46c01..05b49baf6 --- a/examples/device/uac2_speaker_fb/src/audio_debug.py +++ b/examples/device/uac2_speaker_fb/src/audio_debug.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 # Install python3 HID package https://pypi.org/project/hid/ # Install python3 matplotlib package https://pypi.org/project/matplotlib/ diff --git a/examples/device/usbtmc/visaQuery.py b/examples/device/usbtmc/visaQuery.py old mode 100644 new mode 100755 diff --git a/hw/bsp/fomu/dfu.py b/hw/bsp/fomu/dfu.py old mode 100644 new mode 100755 index 32479350c..8383852e3 --- a/hw/bsp/fomu/dfu.py +++ b/hw/bsp/fomu/dfu.py @@ -1,4 +1,4 @@ -#!/usr/bin/python +#!/usr/bin/env python3 # Written by Antonio Galea - 2010/11/18 # Updated for DFU 1.1 by Sean Cross - 2020/03/31 diff --git a/hw/mcu/sony/cxd56/tools/flash_writer.py b/hw/mcu/sony/cxd56/tools/flash_writer.py index bf630547a..387e679da 100755 --- a/hw/mcu/sony/cxd56/tools/flash_writer.py +++ b/hw/mcu/sony/cxd56/tools/flash_writer.py @@ -1,4 +1,4 @@ -#! /usr/bin/env python3 +#!/usr/bin/env python3 # Copyright (C) 2018 Sony Semiconductor Solutions Corp. # diff --git a/hw/mcu/sony/cxd56/tools/xmodem.py b/hw/mcu/sony/cxd56/tools/xmodem.py old mode 100644 new mode 100755 index 60fcc952c..3ee2698f7 --- a/hw/mcu/sony/cxd56/tools/xmodem.py +++ b/hw/mcu/sony/cxd56/tools/xmodem.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 ''' =============================== XMODEM file transfer protocol diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py old mode 100644 new mode 100755 index 55bec3d23..9bbc18850 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import click import ctypes import pandas as pd diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py old mode 100644 new mode 100755 index a569e7666..b2e17c8e3 --- a/test/hil/hil_test.py +++ b/test/hil/hil_test.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 # # The MIT License (MIT) # diff --git a/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py b/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py old mode 100644 new mode 100755 index 00c0da8cc..a8e5b2726 --- a/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py +++ b/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_test_summary.py @@ -1,4 +1,4 @@ -#! python3 +#!/usr/bin/env python3 # ========================================== # Unity Project - A Test Framework for C # Copyright (c) 2015 Alexander Mueller / XelaRellum@web.de diff --git a/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py b/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py old mode 100644 new mode 100755 index 71dd56888..2379ad49a --- a/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py +++ b/test/unit-test/vendor/ceedling/vendor/unity/auto/unity_to_junit.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import sys import os from glob import glob diff --git a/tools/build.py b/tools/build.py old mode 100644 new mode 100755 index f9ae68231..1f3a7e0af --- a/tools/build.py +++ b/tools/build.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import argparse import random import os diff --git a/tools/build_utils.py b/tools/build_utils.py old mode 100644 new mode 100755 index 5f88db8a2..357a95c93 --- a/tools/build_utils.py +++ b/tools/build_utils.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import subprocess import pathlib import time diff --git a/tools/gen_doc.py b/tools/gen_doc.py old mode 100644 new mode 100755 index 668c77ef6..c69f3ff29 --- a/tools/gen_doc.py +++ b/tools/gen_doc.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import pandas as pd from tabulate import tabulate from pathlib import Path diff --git a/tools/get_deps.py b/tools/get_deps.py old mode 100644 new mode 100755 index 06da54b41..84c6a9e61 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import argparse import sys import subprocess diff --git a/tools/iar_gen.py b/tools/iar_gen.py old mode 100644 new mode 100755 index ebcfa1423..8d45659db --- a/tools/iar_gen.py +++ b/tools/iar_gen.py @@ -1,4 +1,4 @@ -#!/usr/bin/python3 +#!/usr/bin/env python3 import os import sys diff --git a/tools/make_release.py b/tools/make_release.py old mode 100644 new mode 100755 index 3e653c12d..92c75baf9 --- a/tools/make_release.py +++ b/tools/make_release.py @@ -1,3 +1,4 @@ +#!/usr/bin/env python3 import re import gen_doc diff --git a/tools/mksunxi.py b/tools/mksunxi.py old mode 100644 new mode 100755 diff --git a/tools/pcapng_to_corpus.py b/tools/pcapng_to_corpus.py index 9c31365eb..3089f0bb6 100755 --- a/tools/pcapng_to_corpus.py +++ b/tools/pcapng_to_corpus.py @@ -1,4 +1,4 @@ -#!/bin/python3 +#!/usr/bin/env python3 import argparse import pcapng import zipfile -- cgit v1.3.1 From 86b4608365e66ba250cf4fb52226b0ed02488cc1 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 24 Sep 2024 17:38:31 +0700 Subject: update dfifo allocation scheme to use top pointer, update document and explanation for EPInfo address and GDFIFO. some function rename update h743 linker to use SRAM1 since USB DMA cannot access DTCM ram update xmc4500 to use uuid for testing --- hw/bsp/stm32h7/linker/stm32h743xx_flash.ld | 35 +-- hw/bsp/xmc4000/family.c | 6 + src/portable/synopsys/dwc2/dcd_dwc2.c | 361 ++++++++++++++--------------- src/portable/synopsys/dwc2/dwc2_type.h | 14 +- 4 files changed, 206 insertions(+), 210 deletions(-) (limited to 'src/portable') diff --git a/hw/bsp/stm32h7/linker/stm32h743xx_flash.ld b/hw/bsp/stm32h7/linker/stm32h743xx_flash.ld index 336afc01f..ba18c8cd1 100644 --- a/hw/bsp/stm32h7/linker/stm32h743xx_flash.ld +++ b/hw/bsp/stm32h7/linker/stm32h743xx_flash.ld @@ -32,23 +32,24 @@ /* Entry Point */ ENTRY(Reset_Handler) -/* Highest address of the user mode stack */ -_estack = 0x20020000; /* end of RAM */ -/* Generate a link error if heap and stack don't fit into RAM */ -_Min_Heap_Size = 0x200; /* required amount of heap */ -_Min_Stack_Size = 0x400; /* required amount of stack */ - /* Specify the memory areas */ MEMORY { -DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K -RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K -RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K -RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K -ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K -FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 2048K + DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K + RAM_D1 (xrw) : ORIGIN = 0x24000000, LENGTH = 512K + RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K + RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K + ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K + FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 2048K + } +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM_D1) + LENGTH(RAM_D1); /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + /* Define output sections */ SECTIONS { @@ -127,7 +128,7 @@ SECTIONS . = ALIGN(4); _edata = .; /* define a global symbol at data end */ - } >DTCMRAM AT> FLASH + } >RAM_D1 AT> FLASH /* Uninitialized data section */ @@ -144,7 +145,9 @@ SECTIONS . = ALIGN(4); _ebss = .; /* define a global symbol at bss end */ __bss_end__ = _ebss; - } >DTCMRAM + } >RAM_D1 + + /* User_heap_stack section, used to check that there is enough RAM left */ ._user_heap_stack : @@ -155,9 +158,7 @@ SECTIONS . = . + _Min_Heap_Size; . = . + _Min_Stack_Size; . = ALIGN(8); - } >DTCMRAM - - + } >RAM_D1 /* Remove information from the standard libraries */ /DISCARD/ : diff --git a/hw/bsp/xmc4000/family.c b/hw/bsp/xmc4000/family.c index 88810de7a..c776cb58a 100644 --- a/hw/bsp/xmc4000/family.c +++ b/hw/bsp/xmc4000/family.c @@ -103,6 +103,12 @@ uint32_t board_button_read(void) { return BUTTON_STATE_ACTIVE == XMC_GPIO_GetInput(BUTTON_PIN); } +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + uint8_t const len = tu_min8(16, max_len); + memcpy(id, g_chipid, len); + return len; +} + int board_uart_read(uint8_t* buf, int len) { #ifdef UART_DEV for(int i=0;igrxfsiz -static uint16_t _allocated_fifo_words_tx; // TX FIFO size in words (IN EPs) +static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type +static uint16_t _dfifo_top; // top free location in FIFO RAM // Number of IN endpoints active static uint8_t _allocated_ep_in_count; @@ -92,68 +90,125 @@ static uint8_t _allocated_ep_in_count; // SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by static bool _sof_en; -// Calculate the RX FIFO size according to minimum recommendations from reference manual -// RxFIFO = (5 * number of control endpoints + 8) + -// ((largest USB packet used / 4) + 1 for status information) + -// (2 * number of OUT endpoints) + 1 for Global NAK -// with number of control endpoints = 1 we have -// RxFIFO = 15 + (largest USB packet used / 4) + 2 * number of OUT endpoints -// we double the largest USB packet size to be able to hold up to 2 packets -static inline uint16_t calc_grxfsiz(uint16_t max_ep_size, uint8_t ep_count) { - return 15 + 2 * (max_ep_size / 4) + 2 * ep_count; +//-------------------------------------------------------------------- +// DMA +//-------------------------------------------------------------------- + +TU_ATTR_ALWAYS_INLINE static inline bool dma_enabled(const dwc2_regs_t* dwc2) { + (void) dwc2; + // DMA doesn't support fifo transfer +#ifdef TUD_AUDIO_PREFER_RING_BUFFER +#if TUD_AUDIO_PREFER_RING_BUFFER + return false; +#endif +#endif + // Internal DMA only + return (dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA); + // return false; +} + +TU_ATTR_ALWAYS_INLINE static inline uint16_t dma_cal_epfifo_base(uint8_t rhport) { + // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per endpoint direction + const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport]; + return dwc2_controller->ep_fifo_size/4 - 2*dwc2_controller->ep_count; } -TU_ATTR_ALWAYS_INLINE static inline void fifo_flush_tx(dwc2_regs_t* dwc2, uint8_t epnum) { +static void dma_setup_prepare(uint8_t rhport) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + + if (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a) { + if(dwc2->epout[0].doepctl & DOEPCTL_EPENA) { + return; + } + } + + // Receive only 1 packet + dwc2->epout[0].doeptsiz = (1 << DOEPTSIZ_STUPCNT_Pos) | (1 << DOEPTSIZ_PKTCNT_Pos) | (8 << DOEPTSIZ_XFRSIZ_Pos); + dwc2->epout[0].doepdma = (uintptr_t)_setup_packet; + dwc2->epout[0].doepctl |= DOEPCTL_EPENA | DOEPCTL_USBAEP; +} + +//--------------------------------------------------------------------+ +// Data FIFO +//--------------------------------------------------------------------+ + +TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_tx(dwc2_regs_t* dwc2, uint8_t epnum) { // flush TX fifo and wait for it cleared dwc2->grstctl = GRSTCTL_TXFFLSH | (epnum << GRSTCTL_TXFNUM_Pos); while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {} } -TU_ATTR_ALWAYS_INLINE static inline void fifo_flush_rx(dwc2_regs_t* dwc2) { +TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_rx(dwc2_regs_t* dwc2) { // flush RX fifo and wait for it cleared dwc2->grstctl = GRSTCTL_RXFFLSH; while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {} } -static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { +/* USB Data FIFO Layout + + The FIFO is split up into + - EPInfo: for storing DMA metadata, only required when use DMA. Maximum size is called + EP_LOC_CNT = ep_fifo_size - ghwcfg3.dfifo_depth. For value less than EP_LOC_CNT, gdfifocfg must be configured before + gahbcfg.dmaen is set + - Buffer mode: 1 word per endpoint direction + - Scatter/Gather DMA: 4 words per endpoint direction + - TX FIFO: one fifo for each IN endpoint. Size is dynamic depending on packet size, starting from top with EP0 IN. + - Shared RX FIFO: a shared fifo for all OUT endpoints. Typically, can hold up to 2 packets of the largest EP size. + + We allocated TX FIFO from top to bottom (using top pointer), this to allow the RX FIFO to grow dynamically which is + possible since the free space is located between the RX and TX FIFOs. + + ---------------- ep_fifo_size + | EPInfo | + | for DMA | + |-------------|-- gdfifocfg.EPINFOBASE (max is ghwcfg3.dfifo_depth) + | IN FIFO 0 | + | control | + |-------------| + | IN FIFO 1 | + |-------------| + | . . . . | + |-------------| + | IN FIFO n | + |-------------| + | FREE | + |-------------|-- GRXFSIZ (expandable) + | OUT FIFO | + | ( Shared ) | + --------------- 0 + + According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits): + - Each EP IN needs at least max packet size + - All EP OUT shared a unique OUT FIFO which uses (for Slave or Buffer DMA, Scatt/Gather DMA use different formula): + - 13 for setup packets + control words (up to 3 setup packets). + - 1 for global NAK (not required/used here). + - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4) + 1" + - 2 for each used OUT endpoint + + Therefore GRXFSIZ = 13 + 1 + 2 x (Largest-EPsize/4 + 1) + 2 x EPOUTnum +*/ + +TU_ATTR_ALWAYS_INLINE static inline uint16_t calc_grxfsiz(uint16_t largest_ep_size, uint8_t ep_count) { + return 13 + 1 + 2 * ((largest_ep_size / 4) + 1) + 2 * ep_count; +} + +static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint8_t const ep_count = _dwc2_controller[rhport].ep_count; + const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport]; + uint8_t const ep_count = dwc2_controller->ep_count; uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); TU_ASSERT(epnum < ep_count); uint16_t fifo_size = tu_div_ceil(packet_size, 4); - - // "USB Data FIFOs" section in reference manual - // Peripheral FIFO architecture - // - // --------------- 320 or 1024 ( 1280 or 4096 bytes ) - // | IN FIFO 0 | - // --------------- (320 or 1024) - 16 - // | IN FIFO 1 | - // --------------- (320 or 1024) - 16 - x - // | . . . . | - // --------------- (320 or 1024) - 16 - x - y - ... - z - // | IN FIFO MAX | - // --------------- - // | FREE | - // --------------- GRXFSIZ - // | OUT FIFO | - // | ( Shared ) | - // --------------- 0 - // - // In FIFO is allocated by following rules: - // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n". if (dir == TUSB_DIR_OUT) { // Calculate required size of RX FIFO - uint16_t const sz = calc_grxfsiz(4 * fifo_size, ep_count); + uint16_t const new_sz = calc_grxfsiz(4 * fifo_size, ep_count); - // If size_rx needs to be extended check if possible and if so enlarge it - if (dwc2->grxfsiz < sz) { - TU_ASSERT(sz + _allocated_fifo_words_tx <= _dwc2_controller[rhport].ep_fifo_size / 4); - - // Enlarge RX FIFO - dwc2->grxfsiz = sz; + // If size_rx needs to be extended check if there is enough free space + if (dwc2->grxfsiz < new_sz) { + TU_ASSERT(new_sz <= _dfifo_top); + dwc2->grxfsiz = new_sz; // Enlarge RX FIFO } } else { // Check IN endpoints concurrently active limit @@ -162,59 +217,48 @@ static bool fifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { _allocated_ep_in_count++; } - // Note if The TXFELVL is configured as half empty. In order - // to be able to write a packet at that point, the fifo must be twice the max_size. + // If The TXFELVL is configured as half empty, the fifo must be twice the max_size. if ((dwc2->gahbcfg & GAHBCFG_TXFELVL) == 0) { fifo_size *= 2; } // Check if free space is available - TU_ASSERT(_allocated_fifo_words_tx + fifo_size + dwc2->grxfsiz <= _dwc2_controller[rhport].ep_fifo_size / 4); - _allocated_fifo_words_tx += fifo_size; - TU_LOG(DWC2_DEBUG, " Allocated %u bytes at offset %" PRIu32, fifo_size * 4, - _dwc2_controller[rhport].ep_fifo_size - _allocated_fifo_words_tx * 4); + TU_ASSERT(_dfifo_top >= fifo_size + dwc2->grxfsiz); + _dfifo_top -= fifo_size; + TU_LOG(DWC2_DEBUG, " TX FIFO %u: allocated %u words at offset %u\r\n", epnum, fifo_size, _dfifo_top); - // DIEPTXF starts at FIFO #1. // Both TXFD and TXSA are in unit of 32-bit words. - dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | - (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx); + if (epnum == 0) { + dwc2->dieptxf0 = (fifo_size << DIEPTXF0_TX0FD_Pos) | _dfifo_top; + } else { + // DIEPTXF starts at FIFO #1. + dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | _dfifo_top; + } } return true; } -static inline bool dma_enabled(uint8_t rhport) -{ - // DMA doesn't support fifo transfer -#ifdef TUD_AUDIO_PREFER_RING_BUFFER -#if TUD_AUDIO_PREFER_RING_BUFFER - return false; -#endif -#endif - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - // Internal DMA only - return (dwc2->ghwcfg2_bm.arch == 2); -} - -static void dma_stpkt_rx(uint8_t rhport) -{ +static void dfifo_init(uint8_t rhport) { + const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport]; dwc2_regs_t* dwc2 = DWC2_REG(rhport); + dwc2->grxfsiz = calc_grxfsiz(CFG_TUD_ENDPOINT0_SIZE, dwc2_controller->ep_count); - if (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a) { - if(dwc2->epout[0].doepctl & DOEPCTL_EPENA) - return; + if(dma_enabled(dwc2)) { + // DMA use last DFIFO to store metadata + _dfifo_top = dma_cal_epfifo_base(rhport); + }else { + _dfifo_top = dwc2_controller->ep_fifo_size / 4; } - // Receive only 1 packet - dwc2->epout[0].doeptsiz = 0; - dwc2->epout[0].doeptsiz |= (1 << DOEPTSIZ_STUPCNT_Pos); - dwc2->epout[0].doeptsiz |= 8; - dwc2->epout[0].doeptsiz |= (1 << DOEPTSIZ_PKTCNT_Pos); - dwc2->epout[0].doepdma = (uintptr_t)_setup_packet; - - dwc2->epout[0].doepctl |= DOEPCTL_EPENA | DOEPCTL_USBAEP; + // Allocate FIFO for EP0 IN + dfifo_alloc(rhport, 0x80, CFG_TUD_ENDPOINT0_SIZE); } +//-------------------------------------------------------------------- +// Endpoint +//-------------------------------------------------------------------- + static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); @@ -235,7 +279,7 @@ static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoin dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum); } else { dwc2->epin[epnum].diepctl = dxepctl | (epnum << DIEPCTL_TXFNUM_Pos); - dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum)); + dwc2->daintmsk |= TU_BIT(DAINTMSK_IEPM_Pos + epnum); } } @@ -265,7 +309,7 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { } // Flush the FIFO, and wait until we have confirmed it cleared. - fifo_flush_tx(dwc2, epnum); + dfifo_flush_tx(dwc2, epnum); } else { dwc2_epout_t* epout = dwc2->epout; @@ -318,88 +362,27 @@ static void bus_reset(uint8_t rhport) { } } - fifo_flush_tx(dwc2, 0x10); // all tx fifo - fifo_flush_rx(dwc2); + dfifo_flush_tx(dwc2, 0x10); // all tx fifo + dfifo_flush_rx(dwc2); // 3. Set up interrupt mask dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos); dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM; dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM; - // "USB Data FIFOs" section in reference manual - // Peripheral FIFO architecture - // - // The FIFO is split up in a lower part where the RX FIFO is located and an upper part where the TX FIFOs start. - // We do this to allow the RX FIFO to grow dynamically which is possible since the free space is located - // between the RX and TX FIFOs. This is required by ISO OUT EPs which need a bigger FIFO than the standard - // configuration done below. - // - // Dynamically FIFO sizes are of interest only for ISO EPs since all others are usually not opened and closed. - // All EPs other than ISO are opened as soon as the driver starts up i.e. when the host sends a - // configure interface command. Hence, all IN EPs other the ISO will be located at the top. IN ISO EPs are usually - // opened when the host sends an additional command: setInterface. At this point in time - // the ISO EP will be located next to the free space and can change its size. In case more IN EPs change its size - // an additional memory - // - // --------------- 320 or 1024 ( 1280 or 4096 bytes ) - // | IN FIFO 0 | - // --------------- (320 or 1024) - 16 - // | IN FIFO 1 | - // --------------- (320 or 1024) - 16 - x - // | . . . . | - // --------------- (320 or 1024) - 16 - x - y - ... - z - // | IN FIFO MAX | - // --------------- - // | FREE | - // --------------- GRXFSIZ - // | OUT FIFO | - // | ( Shared ) | - // --------------- 0 - // - // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits): - // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN - // - // - All EP OUT shared a unique OUT FIFO which uses - // - 13 for setup packets + control words (up to 3 setup packets). - // - 1 for global NAK (not required/used here). - // - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4) + 1" - // - 2 for each used OUT endpoint - // - // Therefore GRXFSIZ = 13 + 1 + 1 + 2 x (Largest-EPsize/4) + 2 x EPOUTnum - // - FullSpeed (64 Bytes ): GRXFSIZ = 15 + 2 x 16 + 2 x ep_count = 47 + 2 x ep_count - // - Highspeed (512 bytes): GRXFSIZ = 15 + 2 x 128 + 2 x ep_count = 271 + 2 x ep_count - // - // NOTE: Largest-EPsize & EPOUTnum is actual used endpoints in configuration. Since DCD has no knowledge - // of the overall picture yet. We will use the worst scenario: largest possible + ep_count - // - // For Isochronous, largest EP size can be 1023/1024 for FS/HS respectively. In addition if multiple ISO - // are enabled at least "2 x (Largest-EPsize/4) + 1" are recommended. Maybe provide a macro for application to - // overwrite this. - - // EP0 out max is 64 - dwc2->grxfsiz = calc_grxfsiz(64, ep_count); - - // Setup the control endpoint 0 - _allocated_fifo_words_tx = 16; - - // DMA needs extra space for processing - if(dma_enabled(rhport)) { - uint16_t reserved = _dwc2_controller[rhport].ep_fifo_size / 4- dwc2->ghwcfg3_bm.total_fifo_size; - _allocated_fifo_words_tx += reserved; - } - - // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word ) - dwc2->dieptxf0 = (16 << DIEPTXF0_TX0FD_Pos) | (_dwc2_controller[rhport].ep_fifo_size / 4 - _allocated_fifo_words_tx); + dfifo_init(rhport); // Fixed control EP0 size to 64 bytes dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos); + dwc2->epout[0].doepctl &= ~(0x03 << DOEPCTL_MPSIZ_Pos); + xfer_status[0][TUSB_DIR_OUT].max_size = 64; xfer_status[0][TUSB_DIR_IN].max_size = 64; - dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); - - if(dma_enabled(rhport)) { - dma_stpkt_rx(rhport); + if(dma_enabled(dwc2)) { + dma_setup_prepare(rhport); + } else { + dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); } dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT; @@ -427,7 +410,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); - if(dma_enabled(rhport)) { + if(dma_enabled(dwc2)) { epin[epnum].diepdma = (uintptr_t)xfer->buffer; // For ISO endpoint set correct odd/even bit for next frame. @@ -468,7 +451,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); } - if(dma_enabled(rhport)) { + if(dma_enabled(dwc2)) { epout[epnum].doepdma = (uintptr_t)xfer->buffer; } @@ -599,7 +582,9 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347) - if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) dcfg |= DCFG_XCVRDLY; + if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) { + dcfg |= DCFG_XCVRDLY; + } dwc2->dcfg = dcfg; } @@ -625,12 +610,9 @@ void dcd_init(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Check Synopsys ID register, failed if controller clock/power is not enabled - if (!check_dwc2(dwc2)) return; + TU_ASSERT(check_dwc2(dwc2), ); dcd_disconnect(rhport); - // max number of endpoints & total_fifo_size are: - // hw_cfg2->num_dev_ep, hw_cfg2->total_fifo_size - if (phy_hs_supported(dwc2)) { phy_hs_init(dwc2); // Highspeed } else { @@ -660,8 +642,8 @@ void dcd_init(uint8_t rhport) { // (non zero-length packet), send STALL back and discard. dwc2->dcfg |= DCFG_NZLSOHSK; - fifo_flush_tx(dwc2, 0x10); // all tx fifo - fifo_flush_rx(dwc2); + dfifo_flush_tx(dwc2, 0x10); // all tx fifo + dfifo_flush_rx(dwc2); // Clear all interrupts uint32_t int_mask = dwc2->gintsts; @@ -670,20 +652,24 @@ void dcd_init(uint8_t rhport) { dwc2->gotgint |= int_mask; // Required as part of core initialization. - dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_RXFLVLM | - GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM; + dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM; // Configure TX FIFO empty level for interrupt. Default is complete empty dwc2->gahbcfg |= GAHBCFG_TXFELVL; - // Enable global interrupt - dwc2->gahbcfg |= GAHBCFG_GINT; + if (dma_enabled(dwc2)) { + const uint16_t epinfo_base = dma_cal_epfifo_base(rhport); + dwc2->gdfifocfg = (epinfo_base << GDFIFOCFG_EPINFOBASE_SHIFT) | epinfo_base; - if (dma_enabled(rhport)) { + // DMA seems to be only settable after a core reset dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2; - dwc2->gintmsk &=~GINTMSK_RXFLVLM; + }else { + dwc2->gintmsk |= GINTMSK_RXFLVLM; } + // Enable global interrupt + dwc2->gahbcfg |= GAHBCFG_GINT; + // make sure we are in device mode // TU_ASSERT(!(dwc2->gintsts & GINTSTS_CMOD), ); @@ -783,7 +769,7 @@ void dcd_sof_enable(uint8_t rhport, bool en) { *------------------------------------------------------------------*/ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) { - TU_ASSERT(fifo_alloc(rhport, desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt))); + TU_ASSERT(dfifo_alloc(rhport, desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt))); edpt_activate(rhport, desc_edpt); return true; } @@ -812,32 +798,21 @@ void dcd_edpt_close_all(uint8_t rhport) { xfer_status[n][TUSB_DIR_IN].max_size = 0; } - // reset allocated fifo OUT - dwc2->grxfsiz = calc_grxfsiz(64, ep_count); - // reset allocated fifo IN - _allocated_fifo_words_tx = 16; - - fifo_flush_tx(dwc2, 0x10); // all tx fifo - fifo_flush_rx(dwc2); + dfifo_flush_tx(dwc2, 0x10); // all tx fifo + dfifo_flush_rx(dwc2); - // DMA needs extra space for processing - if(dma_enabled(rhport)) { - uint16_t reserved = _dwc2_controller[rhport].ep_fifo_size / 4- dwc2->ghwcfg3_bm.total_fifo_size; - _allocated_fifo_words_tx += reserved; - } + dfifo_init(rhport); // re-init dfifo } bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { - TU_ASSERT(fifo_alloc(rhport, ep_addr, largest_packet_size)); + TU_ASSERT(dfifo_alloc(rhport, ep_addr, largest_packet_size)); return true; } bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { // Disable EP to clear potential incomplete transfers edpt_disable(rhport, p_endpoint_desc->bEndpointAddress, false); - edpt_activate(rhport, p_endpoint_desc); - return true; } @@ -904,8 +879,8 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { edpt_disable(rhport, ep_addr, true); - if((tu_edpt_number(ep_addr) == 0) && dma_enabled(rhport)) { - dma_stpkt_rx(rhport); + if((tu_edpt_number(ep_addr) == 0) && dma_enabled(DWC2_REG(rhport))) { + dma_setup_prepare(rhport); } } @@ -1075,13 +1050,15 @@ static void handle_epout_irq(uint8_t rhport) { uint32_t const doepint = epout->doepint; + TU_ASSERT((epout->doepint & DOEPINT_AHBERR) == 0, ); + // OUT XFER complete if (epout->doepint & DOEPINT_XFRC) { epout->doepint = DOEPINT_XFRC; xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); - if(dma_enabled(rhport)) { + if(dma_enabled(dwc2)) { if (doepint & DOEPINT_STUP) { // STPKTRX is only available for version from 3_00a if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { @@ -1103,7 +1080,7 @@ static void handle_epout_irq(uint8_t rhport) { xfer->total_len -= remain; // this is ZLP, so prepare EP0 for next setup if(n == 0 && xfer->total_len == 0) { - dma_stpkt_rx(rhport); + dma_setup_prepare(rhport); } dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); @@ -1135,8 +1112,8 @@ static void handle_epout_irq(uint8_t rhport) { if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { epout->doepint = DOEPINT_STPKTRX; } - if(dma_enabled(rhport) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { - dma_stpkt_rx(rhport); + if(dma_enabled(dwc2) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { + dma_setup_prepare(rhport); } dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); @@ -1165,8 +1142,8 @@ static void handle_epin_irq(uint8_t rhport) { // Schedule another packet to be transmitted. edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); } else { - if((n == 0) && dma_enabled(rhport)) { - dma_stpkt_rx(rhport); + if((n == 0) && dma_enabled(dwc2)) { + dma_setup_prepare(rhport); } dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); } diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 244323b51..c21bf9e94 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -100,6 +100,12 @@ enum { FS_PHY_TYPE_ULPI, }; +enum { + GHWCFG2_ARCH_SLAVE_ONLY = 0, + GHWCFG2_ARCH_EXTERNAL_DMA, // 1 + GHWCFG2_ARCH_INTERNAL_DMA, // 2 +}; + typedef struct TU_ATTR_PACKED { uint32_t op_mode : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP @@ -134,7 +140,7 @@ typedef struct TU_ATTR_PACKED uint32_t otg_enable_hsic : 1; // 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC uint32_t battery_charger_support : 1; // support battery charger uint32_t lpm_mode : 1; // LPC mode - uint32_t total_fifo_size : 16; // DFIFO depth value in terms of 32-bit words + uint32_t dfifo_depth : 16; // DFIFO depth - EP_LOC_CNT in terms of 32-bit words }dwc2_ghwcfg3_t; TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size"); @@ -1240,6 +1246,12 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GLPMCFG_ENBESL_Msk (0x1UL << GLPMCFG_ENBESL_Pos) // 0x10000000 #define GLPMCFG_ENBESL GLPMCFG_ENBESL_Msk // Enable best effort service latency +// GDFIFOCFG +#define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16) +#define GDFIFOCFG_EPINFOBASE_SHIFT 16 +#define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0) +#define GDFIFOCFG_GDFIFOCFG_SHIFT 0 + /******************** Bit definition for DIEPEACHMSK1 register ********************/ #define DIEPEACHMSK1_XFRCM_Pos (0U) #define DIEPEACHMSK1_XFRCM_Msk (0x1UL << DIEPEACHMSK1_XFRCM_Pos) // 0x00000001 -- cgit v1.3.1 From a1244381b3e68959f99bc0ba8057eea5ca35bac6 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 24 Sep 2024 17:55:15 +0700 Subject: add CFG_TUD_DWC2_DMA, make it compile time option --- src/common/tusb_mcu.h | 2 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 9 +++----- src/tusb_option.h | 39 +++++++++++++++++++++-------------- 3 files changed, 28 insertions(+), 22 deletions(-) (limited to 'src/portable') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 0a4462a0a..6ead1ea0b 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -524,7 +524,7 @@ #define TUP_DCD_EDPT_ISO_ALLOC #endif -#if defined(TUP_USBIP_DWC2) +#if defined(TUP_USBIP_DWC2) // && CFG_TUD_DWC2_DMA == 0 #define TUP_MEM_CONST_ADDR #endif diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 897f81a42..2c5e82778 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -95,16 +95,13 @@ static bool _sof_en; //-------------------------------------------------------------------- TU_ATTR_ALWAYS_INLINE static inline bool dma_enabled(const dwc2_regs_t* dwc2) { + #if !CFG_TUD_DWC2_DMA (void) dwc2; - // DMA doesn't support fifo transfer -#ifdef TUD_AUDIO_PREFER_RING_BUFFER -#if TUD_AUDIO_PREFER_RING_BUFFER return false; -#endif -#endif + #else // Internal DMA only return (dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA); - // return false; + #endif } TU_ATTR_ALWAYS_INLINE static inline uint16_t dma_cal_epfifo_base(uint8_t rhport) { diff --git a/src/tusb_option.h b/src/tusb_option.h index fb0209023..e61b3bb9e 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -228,7 +228,7 @@ #define OPT_MODE_SPEED_MASK 0xff00 //--------------------------------------------------------------------+ -// Include tusb_config.h and tusb_mcu.h +// Include tusb_config.h //--------------------------------------------------------------------+ // Allow to use command line to change the config name/location @@ -238,6 +238,29 @@ #include "tusb_config.h" #endif +//--------------------------------------------------------------------+ +// USBIP +//--------------------------------------------------------------------+ + +// DWC2 controller: use DMA for data transfer +#ifndef CFG_TUD_DWC2_DMA + #define CFG_TUD_DWC2_DMA 1 +#endif + +// Enable PIO-USB software host controller +#ifndef CFG_TUH_RPI_PIO_USB + #define CFG_TUH_RPI_PIO_USB 0 +#endif + +#ifndef CFG_TUD_RPI_PIO_USB + #define CFG_TUD_RPI_PIO_USB 0 +#endif + +// MAX3421 Host controller option +#ifndef CFG_TUH_MAX3421 + #define CFG_TUH_MAX3421 0 +#endif + #include "common/tusb_mcu.h" //-------------------------------------------------------------------- @@ -548,20 +571,6 @@ #define CFG_TUH_API_EDPT_XFER 0 #endif -// Enable PIO-USB software host controller -#ifndef CFG_TUH_RPI_PIO_USB - #define CFG_TUH_RPI_PIO_USB 0 -#endif - -#ifndef CFG_TUD_RPI_PIO_USB - #define CFG_TUD_RPI_PIO_USB 0 -#endif - -// MAX3421 Host controller option -#ifndef CFG_TUH_MAX3421 - #define CFG_TUH_MAX3421 0 -#endif - //--------------------------------------------------------------------+ // TypeC Options (Default) //--------------------------------------------------------------------+ -- cgit v1.3.1 From 6a15e7875c6bc42247210fdcebdea1a4353c51ea Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 24 Sep 2024 18:01:09 +0700 Subject: more rename --- src/portable/synopsys/dwc2/dcd_dwc2.c | 106 +++++++++++++++++----------------- src/tusb_option.h | 2 +- 2 files changed, 55 insertions(+), 53 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 2c5e82778..eb5b145e8 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -252,6 +252,55 @@ static void dfifo_init(uint8_t rhport) { dfifo_alloc(rhport, 0x80, CFG_TUD_ENDPOINT0_SIZE); } +// Read a single data packet from receive FIFO +static void dfifo_read_packet(uint8_t rhport, uint8_t* dst, uint16_t len) { + (void) rhport; + + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + volatile const uint32_t* rx_fifo = dwc2->fifo[0]; + + // Reading full available 32 bit words from fifo + uint16_t full_words = len >> 2; + while (full_words--) { + tu_unaligned_write32(dst, *rx_fifo); + dst += 4; + } + + // Read the remaining 1-3 bytes from fifo + uint8_t const bytes_rem = len & 0x03; + if (bytes_rem != 0) { + uint32_t const tmp = *rx_fifo; + dst[0] = tu_u32_byte0(tmp); + if (bytes_rem > 1) dst[1] = tu_u32_byte1(tmp); + if (bytes_rem > 2) dst[2] = tu_u32_byte2(tmp); + } +} + +// Write a single data packet to EPIN FIFO +static void dfifo_write_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const* src, uint16_t len) { + (void) rhport; + + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + volatile uint32_t* tx_fifo = dwc2->fifo[fifo_num]; + + // Pushing full available 32 bit words to fifo + uint16_t full_words = len >> 2; + while (full_words--) { + *tx_fifo = tu_unaligned_read32(src); + src += 4; + } + + // Write the remaining 1-3 bytes into fifo + uint8_t const bytes_rem = len & 0x03; + if (bytes_rem) { + uint32_t tmp_word = src[0]; + if (bytes_rem > 1) tmp_word |= (src[1] << 8); + if (bytes_rem > 2) tmp_word |= (src[2] << 16); + + *tx_fifo = tmp_word; + } +} + //-------------------------------------------------------------------- // Endpoint //-------------------------------------------------------------------- @@ -899,56 +948,9 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { } } -/*------------------------------------------------------------------*/ - -// Read a single data packet from receive FIFO -static void read_fifo_packet(uint8_t rhport, uint8_t* dst, uint16_t len) { - (void) rhport; - - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - volatile const uint32_t* rx_fifo = dwc2->fifo[0]; - - // Reading full available 32 bit words from fifo - uint16_t full_words = len >> 2; - while (full_words--) { - tu_unaligned_write32(dst, *rx_fifo); - dst += 4; - } - - // Read the remaining 1-3 bytes from fifo - uint8_t const bytes_rem = len & 0x03; - if (bytes_rem != 0) { - uint32_t const tmp = *rx_fifo; - dst[0] = tu_u32_byte0(tmp); - if (bytes_rem > 1) dst[1] = tu_u32_byte1(tmp); - if (bytes_rem > 2) dst[2] = tu_u32_byte2(tmp); - } -} - -// Write a single data packet to EPIN FIFO -static void write_fifo_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const* src, uint16_t len) { - (void) rhport; - - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - volatile uint32_t* tx_fifo = dwc2->fifo[fifo_num]; - - // Pushing full available 32 bit words to fifo - uint16_t full_words = len >> 2; - while (full_words--) { - *tx_fifo = tu_unaligned_read32(src); - src += 4; - } - - // Write the remaining 1-3 bytes into fifo - uint8_t const bytes_rem = len & 0x03; - if (bytes_rem) { - uint32_t tmp_word = src[0]; - if (bytes_rem > 1) tmp_word |= (src[1] << 8); - if (bytes_rem > 2) tmp_word |= (src[2] << 16); - - *tx_fifo = tmp_word; - } -} +//-------------------------------------------------------------------- +// Interrupt Handler +//-------------------------------------------------------------------- static void handle_rxflvl_irq(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); @@ -1002,7 +1004,7 @@ static void handle_rxflvl_irq(uint8_t rhport) { tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt); } else { // Linear buffer - read_fifo_packet(rhport, xfer->buffer, bcnt); + dfifo_read_packet(rhport, xfer->buffer, bcnt); // Increment pointer to xfer data xfer->buffer += bcnt; @@ -1171,7 +1173,7 @@ static void handle_epin_irq(uint8_t rhport) { volatile uint32_t* tx_fifo = dwc2->fifo[n]; tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, packet_size); } else { - write_fifo_packet(rhport, n, xfer->buffer, packet_size); + dfifo_write_packet(rhport, n, xfer->buffer, packet_size); // Increment pointer to xfer data xfer->buffer += packet_size; diff --git a/src/tusb_option.h b/src/tusb_option.h index e61b3bb9e..0d118eef9 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -244,7 +244,7 @@ // DWC2 controller: use DMA for data transfer #ifndef CFG_TUD_DWC2_DMA - #define CFG_TUD_DWC2_DMA 1 + #define CFG_TUD_DWC2_DMA 0 #endif // Enable PIO-USB software host controller -- cgit v1.3.1 From 47233f863a5fa5255461514fada9af7771cf2146 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 18 Sep 2024 17:59:04 +0700 Subject: update to dwc2 register struct --- src/portable/synopsys/dwc2/dwc2_info.md | 110 +++++++++++++------------- src/portable/synopsys/dwc2/dwc2_info.py | 27 +++---- src/portable/synopsys/dwc2/dwc2_type.h | 136 +++++++++++++++++++++++++++----- test/hil/hil_test.py | 5 +- 4 files changed, 187 insertions(+), 91 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index 8690a0755..a11b79671 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -1,55 +1,55 @@ -| | BCM2711 (Pi4) | EFM32GG FullSpeed | ESP32-S2 | STM32F407 Fullspeed | STM32F407 Highspeed | STM32F411 Fullspeed | STM32F412 Fullspeed | STM32F429 Fullspeed | STM32F429 Highspeed | STM32F723 Fullspeed | STM32F723 HighSpeed | STM32F767 Fullspeed | STM32H743 Highspeed | STM32L476 Fullspeed | STM32U5A5 Highspeed | GD32VF103 Fullspeed | XMC4500 | -|:----------------------------|:----------------|:--------------------|:-----------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:-----------| -| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00001200 | 0x00002000 | 0x00001200 | 0x00001100 | 0x00003000 | 0x00003100 | 0x00002000 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | -| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54281A | 0x4F54281A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | -| - specs version | 2.80a | 3.30a | 4.00a | 2.81a | 2.81a | 2.81a | 3.20a | 2.81a | 2.81a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | -| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | -| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229DCD20 | 0x229ED520 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229FE1D0 | 0x229ED520 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | -| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | -| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | -| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | -| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 2 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | -| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 3 | 5 | 3 | 5 | 5 | 8 | 5 | 8 | 5 | 8 | 0 | 6 | -| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 7 | 11 | 7 | 11 | 11 | 15 | 11 | 15 | 11 | 15 | 0 | 13 | -| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nperiod_tx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - host_period_tx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - dev_token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | -| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x020001E8 | 0x0200D1E8 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x03EED2E8 | 0x0200D1E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | -| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | -| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | -| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | -| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | -| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | -| - total_fifo_size | 4080 | 498 | 200 | 512 | 1012 | 512 | 512 | 512 | 1012 | 512 | 1006 | 512 | 952 | 512 | 952 | 0 | 634 | -| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x0FF08030 | 0x17F08030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x23F00030 | 0x17F08030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | -| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - power_optimized | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - reserved7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | -| - service_interval_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - ipg_isoc_en | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - acg_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - reserved13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - utmi_phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 0 | 2 | -| - dev_ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - iddg_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - vbus_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - a_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - b_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - num_dev_in_eps | 15 | 13 | 9 | 7 | 11 | 7 | 11 | 7 | 11 | 11 | 1 | 11 | 1 | 11 | 1 | 0 | 13 | -| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | -| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | +| | BCM2711 (Pi4) | EFM32GG FS | ESP32-S2/S3 | STM32F 407/411/429 FS | STM32F407 HS | STM32F412 FS | STM32F429 HS | STM32F723 FS | STM32F723 HS | STM32F767 FS | STM32H743 HS | STM32L476 FS | STM32U5A5 HS | GD32VF103 FS | XMC4500 | +|:----------------------------|:----------------|:-------------|:--------------|:------------------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:-----------| +| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00001100 | 0x00003000 | 0x00003100 | 0x00002000 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | +| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54281A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | +| - specs version | 2.80a | 3.30a | 4.00a | 2.81a | 2.81a | 3.20a | 2.81a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | +| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED590 | 0x229ED520 | 0x229FE1D0 | 0x229ED520 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | +| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | +| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | +| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | +| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 5 | 5 | 5 | 8 | 5 | 8 | 5 | 8 | 0 | 6 | +| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 11 | 11 | 11 | 15 | 11 | 15 | 11 | 15 | 0 | 13 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nperiod_tx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - host_period_tx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - dev_token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x03F403E8 | 0x0200D1E8 | 0x03EED2E8 | 0x0200D1E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | +| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | +| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | +| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | +| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - total_fifo_size | 4080 | 498 | 200 | 512 | 1012 | 512 | 1012 | 512 | 1006 | 512 | 952 | 512 | 952 | 0 | 634 | +| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F00030 | 0x17F08030 | 0x23F00030 | 0x17F08030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | +| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - power_optimized | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | +| - service_interval_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - ipg_isoc_en | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - acg_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - reserved13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - utmi_phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 0 | 2 | +| - dev_ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - vbus_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - a_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - b_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - num_dev_in_eps | 15 | 13 | 9 | 7 | 11 | 11 | 11 | 11 | 1 | 11 | 1 | 11 | 1 | 0 | 13 | +| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | +| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 55bec3d23..6f3f195f0 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -3,24 +3,21 @@ import ctypes import pandas as pd # hex value for register: guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4 +# Note: FS is FullSpeed, HS is HighSpeed dwc2_reg_list = ['guid', 'gsnpsid', 'ghwcfg1', 'ghwcfg2', 'ghwcfg3', 'ghwcfg4'] dwc2_reg_value = { 'BCM2711 (Pi4)': [0x2708A000, 0x4F54280A, 0, 0x228DDD50, 0xFF000E8, 0x1FF00020], - 'EFM32GG FullSpeed': [0, 0x4F54330A, 0, 0x228F5910, 0x1F204E8, 0x1BF08030], - 'ESP32-S2': [0, 0x4F54400A, 0, 0x224DD930, 0xC804B5, 0xD3F0A030], - 'STM32F407 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030], - 'STM32F407 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030], - 'STM32F411 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030], - 'STM32F412 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], - 'STM32F429 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030], - 'STM32F429 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030], - 'STM32F723 Fullspeed': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], - 'STM32F723 HighSpeed': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x3EED2E8, 0x23F00030], - 'STM32F767 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], - 'STM32H743 Highspeed': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x3B8D2E8, 0xE3F00030], # both HS cores - 'STM32L476 Fullspeed': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], - 'STM32U5A5 Highspeed': [0x00005000, 0x4F54411A, 0x00000000, 0x228FE052, 0x03B882E8, 0xE2103E30], - 'GD32VF103 Fullspeed': [0x1000, 0, 0, 0, 0, 0], + 'EFM32GG FS': [0, 0x4F54330A, 0, 0x228F5910, 0x1F204E8, 0x1BF08030], + 'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0xC804B5, 0xD3F0A030], + 'STM32F 407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030], + 'STM32F 407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030], + 'STM32F 412/767 FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], + 'STM32F723 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], + 'STM32F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x3EED2E8, 0x23F00030], + 'STM32H743 HS': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x3B8D2E8, 0xE3F00030], # both HS cores + 'STM32L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], + 'STM32U5A5 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30], + 'GD32VF103 FS': [0x1000, 0, 0, 0, 0, 0], 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x27A01E5, 0xDBF08030] } diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index c21bf9e94..97b9d1d8c 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -101,13 +101,15 @@ enum { }; enum { - GHWCFG2_ARCH_SLAVE_ONLY = 0, - GHWCFG2_ARCH_EXTERNAL_DMA, // 1 - GHWCFG2_ARCH_INTERNAL_DMA, // 2 + GHWCFG2_ARCH_SLAVE_ONLY = 0, + GHWCFG2_ARCH_EXTERNAL_DMA, // 1 + GHWCFG2_ARCH_INTERNAL_DMA, // 2 }; -typedef struct TU_ATTR_PACKED -{ +//-------------------------------------------------------------------- +// Register bitfield definitions +//-------------------------------------------------------------------- +typedef struct TU_ATTR_PACKED { uint32_t op_mode : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP uint32_t arch : 2; // 0: slave-only | 1: External DMA | 2: Internal DMA | 3: others uint32_t point2point : 1; // 0: support hub and split | 1: no hub, no split @@ -124,11 +126,9 @@ typedef struct TU_ATTR_PACKED uint32_t dev_token_q_depth : 5; // Device IN token sequence learning queue depth: 0-30 uint32_t otg_enable_ic_usb : 1; // IC_USB mode specified for mode of operation } dwc2_ghwcfg2_t; - TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg2_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint32_t xfer_size_width : 4; // Transfer size counter in bits = 11 + n (max 19 bits) uint32_t packet_size_width : 3; // Packet size counter in bits = 4 + n (max 10 bits) uint32_t otg_enable : 1; // 1 is OTG capable @@ -142,11 +142,9 @@ typedef struct TU_ATTR_PACKED uint32_t lpm_mode : 1; // LPC mode uint32_t dfifo_depth : 16; // DFIFO depth - EP_LOC_CNT in terms of 32-bit words }dwc2_ghwcfg3_t; - TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size"); -typedef struct TU_ATTR_PACKED -{ +typedef struct TU_ATTR_PACKED { uint32_t num_dev_period_in_ep : 4; // Number of Device Periodic IN Endpoints uint32_t power_optimized : 1; // Partial Power Down Enabled uint32_t ahb_freq_min : 1; // 1: minimum of AHB frequency is less than 60 MHz @@ -167,12 +165,110 @@ typedef struct TU_ATTR_PACKED uint32_t dma_desc_enable : 1; // scatter/gather DMA configuration uint32_t dma_dynamic : 1; // Dynamic scatter/gather DMA }dwc2_ghwcfg4_t; - TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size"); +typedef struct TU_ATTR_PACKED { + uint32_t ses_req_scs : 1; // 0: Session request success + uint32_t ses_req : 1; // 1: Session request + uint32_t vbval_ov_en : 1; // 2: VBUS valid override enable + uint32_t vbval_ov_val : 1; // 3: VBUS valid override value + uint32_t aval_ov_en : 1; // 4: A-peripheral session valid override enable + uint32_t aval_ov_al : 1; // 5: A-peripheral session valid override value + uint32_t bval_ov_en : 1; // 6: B-peripheral session valid override enable + uint32_t bval_ov_val : 1; // 7: B-peripheral session valid override value + uint32_t hng_scs : 1; // 8: Host negotiation success + uint32_t hnp_rq : 1; // 9: HNP (host negotiation protocol) request + uint32_t host_set_hnp_en : 1; // 10: Host set HNP enable + uint32_t dev_hnp_en : 1; // 11: Device HNP enabled + uint32_t embedded_host_en : 1; // 12: Embedded host enable + uint32_t rsv13_14 : 2; // 13..14: Reserved + uint32_t dbnc_filter_bypass : 1; // 15: Debounce filter bypass + uint32_t cid_status : 1; // 16: Connector ID status + uint32_t dbnc_done : 1; // 17: Debounce done + uint32_t ases_valid : 1; // 18: A-session valid + uint32_t bses_valid : 1; // 19: B-session valid + uint32_t otg_ver : 1; // 20: OTG version 0: v1.3, 1: v2.0 + uint32_t current_mode : 1; // 21: Current mode of operation 0: device, 1: host + uint32_t mult_val_id_bc : 5; // 22..26: Multi-valued input pin ID battery charger + uint32_t chirp_en : 1; // 27: Chirp detection enable + uint32_t rsv28_30 : 3; // 28..30: Reserved + uint32_t test_mode_corr_eusb2 : 1; // 31: Test mode control for eUSB2 PHY +} dwc2_gotgctl_t; +TU_VERIFY_STATIC(sizeof(dwc2_gotgctl_t) == 4, "incorrect size"); + +typedef struct TU_ATTR_PACKED { + uint32_t rsv0_1 : 2; // 0..1 : Reserved + uint32_t ses_end_det : 1; // 2 : Session end detected + uint32_t rsv3_7 : 5; // 3..7 : Reserved + uint32_t srs_status_change : 1; // 8 : Session request success status change + uint32_t hns_status_change : 1; // 9 : Host negotiation success status change + uint32_t rsv10_16 : 7; // 10..16 : Reserved + uint32_t hng_det : 1; // 17 : Host negotiation detected + uint32_t adev_timeout_change : 1; // 18 : A-device timeout change + uint32_t dbnc_done : 1; // 19 : Debounce done + uint32_t mult_val_lp_change : 1; // 20 : Multi-valued input pin change + uint32_t rsv21_31 :11; // 21..31 : Reserved +} dwc2_gotgint_t; +TU_VERIFY_STATIC(sizeof(dwc2_gotgint_t) == 4, "incorrect size"); + +typedef struct TU_ATTR_PACKED { + uint32_t gintmask : 1; // 0: Global interrupt mask + uint32_t hbst_len : 4; // 1..4: Burst length/type + uint32_t dma_en : 1; // 5: DMA enable + uint32_t rsv6 : 1; // 6: Reserved + uint32_t nptxf_empty_lvl : 1; // 7: Non-periodic Tx FIFO empty level + uint32_t ptxf_empty_lvl : 1; // 8: Periodic Tx FIFO empty level + uint32_t rsv9_20 : 12; // 9..20: Reserved + uint32_t remote_mem_support : 1; // 21: Remote memory support + uint32_t notify_all_dma_write : 1; // 22: Notify all DMA writes + uint32_t ahb_single : 1; // 23: AHB single + uint32_t inv_desc_endian : 1; // 24: Inverse descriptor endian + uint32_t rsv25_31 : 7; // 25..31: Reserved +} dwc2_gahbcfg_t; +TU_VERIFY_STATIC(sizeof(dwc2_gahbcfg_t) == 4, "incorrect size"); + +typedef struct TU_ATTR_PACKED { + uint32_t timeout_cal : 3; /* 0..2: Timeout calibration. + The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard + timeout value for full- speed operation is 16 to 18 (inclusive) bit times. The application must program this field + based on the speed of enumeration. The number of bit times added per PHY clock are as follows: + - High-speed: PHY clock One 30-MHz = 16 bit times, One 60-MHz = 8 bit times + - Full-speed: PHY clock One 30-MHz = 0.4 bit times, One 60-MHz = 0.2 bit times, One 48-MHz = 0.25 bit times */ + uint32_t phy_if : 1; // 3: PHY interface. 0: 8 bits, 1: 16 bits + uint32_t ulpi_utmi_sel : 1; // 4: ULPI/UTMI select. 0: UTMI+, 1: ULPI + uint32_t fs_intf_sel : 1; // 5: Fullspeed serial interface select. 0: 6-pin, 1: 3-pin + uint32_t phy_sel : 1; // 6: HS/FS PHY selection. 0: HS UTMI+ or ULPI, 1: FS serial transceiver + uint32_t ddr_sel : 1; // 7 ULPI DDR select. 0: Single data rate 8-bit, 1: Double data rate 4-bit + uint32_t srp_capable : 1; // 8: SRP-capable + uint32_t hnp_capable : 1; // 9: HNP-capable + uint32_t turnaround_time : 4; // 10..13 Turnaround time. 9: 8-bit UTMI+, 5: 16-bit UTMI+ + uint32_t rsv14 : 1; // 14: Reserved + uint32_t phy_low_power_clk_sel : 1; /* 15: PHY low-power clock select either 480-MHz or 48-MHz (low-power) PHY mode. + In FS/LS modes, the PHY can usually operate on a 48-MHz clock to save power. This bit is valid only for UTMI+ PHYs. + - 0: 480 Mhz internal PLL: the UTMI interface operates at either 60 MHz (8 bit) or 30 MHz (16-bit) + - 1 48 Mhz external clock: the UTMI interface operates at 48 MHz in FS mode and at either 48 or 6 MHz in LS mode */ + uint32_t otg_i2c_sel : 1; // 16: OTG I2C interface select. 0: UTMI-FS, 1: I2C for OTG signals + uint32_t ulpi_fsls : 1; /* 17: ULPI FS/LS select. 0: ULPI, 1: ULPI FS/LS. + valid only when the FS serial transceiver is selected on the ULPI PHY. */ + uint32_t ulpi_auto_resume : 1; // 18: ULPI Auto-resume + uint32_t ulpi_clk_sus_m : 1; // 19: ULPI Clock SuspendM + uint32_t ulpi_ext_vbus_drv : 1; // 20: ULPI External VBUS Drive + uint32_t ulpi_int_vbus_indicator : 1; // 21: ULPI Internal VBUS Indicator + uint32_t term_sel_dl_pulse : 1; // 22: TermSel DLine pulsing + uint32_t indicator_complement : 1; // 23: Indicator complement + uint32_t indicator_pass_through : 1; // 24: Indicator pass through + uint32_t ulpi_if_protect_disable : 1; // 25: ULPI interface protect disable + uint32_t ic_usb_capable : 1; // 26: IC_USB Capable + uint32_t ic_usb_traf_ctl : 1; // 27: IC_USB Traffic Control + uint32_t tx_end_delay : 1; // 28: TX end delay + uint32_t force_host_mode : 1; // 29: Force host mode + uint32_t force_dev_mode : 1; // 30: Force device mode + uint32_t corrupt_tx_pkt : 1; // 31: Corrupt Tx packet. 0: normal, 1: debug +} dwc2_gusbcfg_t; +TU_VERIFY_STATIC(sizeof(dwc2_gusbcfg_t) == 4, "incorrect size"); + // Host Channel -typedef struct -{ +typedef struct { volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics volatile uint32_t hcsplt; // 504 + 20*ch Host Channel Split Control volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt @@ -184,8 +280,7 @@ typedef struct } dwc2_channel_t; // Endpoint IN -typedef struct -{ +typedef struct { volatile uint32_t diepctl; // 900 + 20*ep Device IN Endpoint Control uint32_t reserved04; // 904 volatile uint32_t diepint; // 908 + 20*ep Device IN Endpoint Interrupt @@ -197,8 +292,7 @@ typedef struct } dwc2_epin_t; // Endpoint OUT -typedef struct -{ +typedef struct { volatile uint32_t doepctl; // B00 + 20*ep Device OUT Endpoint Control uint32_t reserved04; // B04 volatile uint32_t doepint; // B08 + 20*ep Device OUT Endpoint Interrupt @@ -208,8 +302,10 @@ typedef struct uint32_t reserved18[2]; // B18..B1C } dwc2_epout_t; -typedef struct -{ +//-------------------------------------------------------------------- +// CSR Register Map +//-------------------------------------------------------------------- +typedef struct { //------------- Core Global -------------// volatile uint32_t gotgctl; // 000 OTG Control and Status volatile uint32_t gotgint; // 004 OTG Interrupt diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py index 2d14220c5..fc2e6c777 100644 --- a/test/hil/hil_test.py +++ b/test/hil/hil_test.py @@ -459,6 +459,8 @@ def main(): """ global verbose + duration = time.time() + parser = argparse.ArgumentParser() parser.add_argument('config_file', help='Configuration JSON file') parser.add_argument('-b', '--board', action='append', default=[], help='Boards to test, all if not specified') @@ -483,9 +485,10 @@ def main(): with Pool(processes=os.cpu_count()) as pool: err_count = sum(pool.map(test_board, config_boards)) + duration = time.time() - duration print() print("-" * 30) - print(f'Total failed: {err_count}') + print(f'Total failed: {err_count} in {duration:.1f}s') print("-" * 30) sys.exit(err_count) -- cgit v1.3.1 From bb2d1dd0c1bef04d495b05d609311e3b7ba870a7 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 24 Sep 2024 22:35:07 +0700 Subject: update/rename ghwcfg registers --- src/portable/synopsys/dwc2/dcd_dwc2.c | 21 +- src/portable/synopsys/dwc2/dwc2_info.md | 113 +++---- src/portable/synopsys/dwc2/dwc2_info.py | 37 +-- src/portable/synopsys/dwc2/dwc2_stm32.h | 6 +- src/portable/synopsys/dwc2/dwc2_type.h | 518 +++++++++++++++++--------------- 5 files changed, 366 insertions(+), 329 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index eb5b145e8..13143073d 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -538,13 +538,10 @@ static void reset_core(dwc2_regs_t* dwc2) { static bool phy_hs_supported(dwc2_regs_t* dwc2) { (void) dwc2; -#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) - // note: esp32 incorrect report its hs_phy_type as utmi - return false; -#elif !TUD_OPT_HIGH_SPEED +#if !TUD_OPT_HIGH_SPEED return false; #else - return dwc2->ghwcfg2_bm.hs_phy_type != HS_PHY_TYPE_NONE; + return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED; #endif } @@ -555,7 +552,7 @@ static void phy_fs_init(dwc2_regs_t* dwc2) { dwc2->gusbcfg |= GUSBCFG_PHYSEL; // MCU specific PHY init before reset - dwc2_phy_init(dwc2, HS_PHY_TYPE_NONE); + dwc2_phy_init(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED); // Reset core after selecting PHY reset_core(dwc2); @@ -566,7 +563,7 @@ static void phy_fs_init(dwc2_regs_t* dwc2) { dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos); // MCU specific PHY update post reset - dwc2_phy_update(dwc2, HS_PHY_TYPE_NONE); + dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED); // set max speed dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos); @@ -578,7 +575,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // De-select FS PHY gusbcfg &= ~GUSBCFG_PHYSEL; - if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) { + if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { TU_LOG(DWC2_DEBUG, "Highspeed ULPI PHY init\r\n"); // Select ULPI @@ -599,7 +596,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); // Set 16-bit interface if supported - if (dwc2->ghwcfg4_bm.utmi_phy_data_width) gusbcfg |= GUSBCFG_PHYIF16; + if (dwc2->ghwcfg4_bm.phy_data_width) gusbcfg |= GUSBCFG_PHYIF16; } // Apply config @@ -615,7 +612,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // - 9 if using 8-bit PHY interface // - 5 if using 16-bit PHY interface gusbcfg &= ~GUSBCFG_TRDT_Msk; - gusbcfg |= (dwc2->ghwcfg4_bm.utmi_phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; + gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; dwc2->gusbcfg = gusbcfg; // MCU specific PHY update post reset @@ -628,7 +625,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347) - if (dwc2->ghwcfg2_bm.hs_phy_type == HS_PHY_TYPE_ULPI) { + if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { dcfg |= DCFG_XCVRDLY; } @@ -640,7 +637,7 @@ static bool check_dwc2(dwc2_regs_t* dwc2) { print_dwc2_info(dwc2); #endif - // For some reasons: GD32VF103 snpsid and all hwcfg register are always zero (skip it) + // For some reason: GD32VF103 snpsid and all hwcfg register are always zero (skip it) (void) dwc2; #if !TU_CHECK_MCU(OPT_MCU_GD32VF103) uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK; diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index a11b79671..9798fb0de 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -1,55 +1,58 @@ -| | BCM2711 (Pi4) | EFM32GG FS | ESP32-S2/S3 | STM32F 407/411/429 FS | STM32F407 HS | STM32F412 FS | STM32F429 HS | STM32F723 FS | STM32F723 HS | STM32F767 FS | STM32H743 HS | STM32L476 FS | STM32U5A5 HS | GD32VF103 FS | XMC4500 | -|:----------------------------|:----------------|:-------------|:--------------|:------------------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:-----------| -| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00001100 | 0x00003000 | 0x00003100 | 0x00002000 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | -| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54281A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | -| - specs version | 2.80a | 3.30a | 4.00a | 2.81a | 2.81a | 3.20a | 2.81a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | -| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | -| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED590 | 0x229ED520 | 0x229FE1D0 | 0x229ED520 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | -| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | -| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | -| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | -| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | -| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 5 | 5 | 5 | 8 | 5 | 8 | 5 | 8 | 0 | 6 | -| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 11 | 11 | 11 | 15 | 11 | 15 | 11 | 15 | 0 | 13 | -| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nperiod_tx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - host_period_tx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - dev_token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | -| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x03F403E8 | 0x0200D1E8 | 0x03EED2E8 | 0x0200D1E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | -| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | -| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | -| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | -| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | -| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | -| - total_fifo_size | 4080 | 498 | 200 | 512 | 1012 | 512 | 1012 | 512 | 1006 | 512 | 952 | 512 | 952 | 0 | 634 | -| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F00030 | 0x17F08030 | 0x23F00030 | 0x17F08030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | -| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - power_optimized | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - reserved7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | -| - service_interval_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - ipg_isoc_en | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - acg_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - reserved13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - utmi_phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 0 | 2 | -| - dev_ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - iddg_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - vbus_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - a_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - b_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - num_dev_in_eps | 15 | 13 | 9 | 7 | 11 | 11 | 11 | 11 | 1 | 11 | 1 | 11 | 1 | 0 | 13 | -| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | -| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | +| | BCM2711 (Pi4) | EFM32GG FS | ESP32-S2/S3 | STM32F 407/411/429 FS | STM32F 407/429 HS | STM32F 412/767 FS | STM32F723 FS | STM32F723 HS | STM32H743 HS | STM32L476 FS | STM32U5A5 HS | GD32VF103 FS | XMC4500 | +|:---------------------------|:----------------|:-------------|:--------------|:------------------------|:--------------------|:--------------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:-----------| +| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | +| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | +| - specs version | 2.80a | 3.30a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | +| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | +| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 2 | 2 | 0 | 2 | 0 | 2 | +| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | +| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 3 | 2 | 0 | 1 | 0 | 0 | +| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 5 | 5 | 8 | 8 | 5 | 8 | 0 | 6 | +| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 11 | 11 | 15 | 15 | 11 | 15 | 0 | 13 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nptx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - ptx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | +| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | +| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | +| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | +| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - dfifo_depth | 4080 | 498 | 200 | 512 | 1012 | 512 | 512 | 1006 | 952 | 512 | 952 | 0 | 634 | +| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | +| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - enhanced_lpm_support | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 2 | +| - ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - num_dev_in_eps | 7 | 6 | 4 | 3 | 5 | 5 | 5 | 8 | 8 | 5 | 8 | 0 | 6 | +| - dma_desc_enable | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | +| - dma_desc_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 6f3f195f0..871ac112d 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -47,9 +47,9 @@ class GHWCFG2(ctypes.LittleEndianStructure): ("enable_dynamic_fifo", ctypes.c_uint32, 1), ("mul_cpu_int", ctypes.c_uint32, 1), ("reserved21", ctypes.c_uint32, 1), - ("nperiod_tx_q_depth", ctypes.c_uint32, 2), - ("host_period_tx_q_depth", ctypes.c_uint32, 2), - ("dev_token_q_depth", ctypes.c_uint32, 5), + ("nptx_q_depth", ctypes.c_uint32, 2), + ("ptx_q_depth", ctypes.c_uint32, 2), + ("token_q_depth", ctypes.c_uint32, 5), ("otg_enable_ic_usb", ctypes.c_uint32, 1) ] @@ -67,31 +67,34 @@ class GHWCFG3(ctypes.LittleEndianStructure): ("otg_enable_hsic", ctypes.c_uint32, 1), ("battery_charger_support", ctypes.c_uint32, 1), ("lpm_mode", ctypes.c_uint32, 1), - ("total_fifo_size", ctypes.c_uint32, 16) + ("dfifo_depth", ctypes.c_uint32, 16) ] class GHWCFG4(ctypes.LittleEndianStructure): _fields_ = [ ("num_dev_period_in_ep", ctypes.c_uint32, 4), - ("power_optimized", ctypes.c_uint32, 1), + ("partial_powerdown", ctypes.c_uint32, 1), ("ahb_freq_min", ctypes.c_uint32, 1), ("hibernation", ctypes.c_uint32, 1), - ("reserved7", ctypes.c_uint32, 3), - ("service_interval_mode", ctypes.c_uint32, 1), - ("ipg_isoc_en", ctypes.c_uint32, 1), - ("acg_enable", ctypes.c_uint32, 1), - ("reserved13", ctypes.c_uint32, 1), - ("utmi_phy_data_width", ctypes.c_uint32, 2), - ("dev_ctrl_ep_num", ctypes.c_uint32, 4), - ("iddg_filter_enabled", ctypes.c_uint32, 1), - ("vbus_valid_filter_enabled", ctypes.c_uint32, 1), - ("a_valid_filter_enabled", ctypes.c_uint32, 1), - ("b_valid_filter_enabled", ctypes.c_uint32, 1), + ("extended_hibernation", ctypes.c_uint32, 1), + ("reserved8", ctypes.c_uint32, 1), + ("enhanced_lpm_support1", ctypes.c_uint32, 1), + ("service_interval_flow", ctypes.c_uint32, 1), + ("ipg_isoc_support", ctypes.c_uint32, 1), + ("acg_support", ctypes.c_uint32, 1), + ("enhanced_lpm_support", ctypes.c_uint32, 1), + ("phy_data_width", ctypes.c_uint32, 2), + ("ctrl_ep_num", ctypes.c_uint32, 4), + ("iddg_filter", ctypes.c_uint32, 1), + ("vbus_valid_filter", ctypes.c_uint32, 1), + ("a_valid_filter", ctypes.c_uint32, 1), + ("b_valid_filter", ctypes.c_uint32, 1), + ("session_end_filter", ctypes.c_uint32, 1), ("dedicated_fifos", ctypes.c_uint32, 1), ("num_dev_in_eps", ctypes.c_uint32, 4), ("dma_desc_enable", ctypes.c_uint32, 1), - ("dma_dynamic", ctypes.c_uint32, 1) + ("dma_desc_dynamic", ctypes.c_uint32, 1) ] diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index 3237a50f6..395b6d870 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -142,7 +142,7 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { // - dwc2 3.30a (H5) use USB_HS_PHYC // - dwc2 4.11a (U5) use femtoPHY static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { - if (hs_phy_type == HS_PHY_TYPE_NONE) { + if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) { // Enable on-chip FS PHY dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN; @@ -175,7 +175,7 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { #endif // Enable on-chip HS PHY - if (hs_phy_type == HS_PHY_TYPE_UTMI || hs_phy_type == HS_PHY_TYPE_UTMI_ULPI) { + if (hs_phy_type == GHWCFG2_HSPHY_UTMI || hs_phy_type == GHWCFG2_HSPHY_UTMI_ULPI) { #ifdef USB_HS_PHYC // Enable UTMI HS PHY dwc2->stm32_gccfg |= STM32_GCCFG_PHYHSEN; @@ -218,7 +218,7 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { // MCU specific PHY update, it is called AFTER init() and core reset static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { // used to set turnaround time for fullspeed, nothing to do in highspeed mode - if (hs_phy_type == HS_PHY_TYPE_NONE) { + if (hs_phy_type == GHWCFG2_HSPHY_NOT_SUPPORTED) { // Turnaround timeout depends on the AHB clock dictated by STM32 Reference Manual uint32_t turnaround; diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 97b9d1d8c..ac88dd24d 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -87,186 +87,220 @@ typedef struct #endif enum { - HS_PHY_TYPE_NONE = 0 , // not supported - HS_PHY_TYPE_UTMI , // internal PHY (mostly) - HS_PHY_TYPE_ULPI , // external PHY - HS_PHY_TYPE_UTMI_ULPI , + GHWCFG2_OPMODE_HNP_SRP = 0, + GHWCFG2_OPMODE_SRP = 1, + GHWCFG2_OPMODE_NON_HNP_NON_SRP = 2, + GHWCFG2_OPMODE_SRP_DEVICE = 3, + GHWCFFG2_OPMODE_NON_OTG_DEVICE = 4, + GHWCFG2_OPMODE_SRP_HOST = 5, + GHWCFG2_OPMODE_NON_OTG_HOST = 6, +}; +enum { + GHWCFG2_ARCH_SLAVE_ONLY = 0, + GHWCFG2_ARCH_EXTERNAL_DMA = 1, + GHWCFG2_ARCH_INTERNAL_DMA = 2, +}; + +enum { + GHWCFG2_HSPHY_NOT_SUPPORTED = 0, + GHWCFG2_HSPHY_UTMI = 1, // internal PHY (mostly) + GHWCFG2_HSPHY_ULPI = 2, // external PHY (mostly) + GHWCFG2_HSPHY_UTMI_ULPI = 3, // both + }; enum { - FS_PHY_TYPE_NONE = 0, // not supported - FS_PHY_TYPE_DEDICATED, - FS_PHY_TYPE_UTMI, - FS_PHY_TYPE_ULPI, + GHWCFG2_FSPHY_NOT_SUPPORTED = 0, + GHWCFG2_FSPHY_DEDICATED = 1, // have dedicated FS PHY + GHWCFG2_FSPHY_UTMI = 2, // shared with UTMI+ + GHWCFG2_FSPHY_ULPI = 3, // shared with ULPI }; enum { - GHWCFG2_ARCH_SLAVE_ONLY = 0, - GHWCFG2_ARCH_EXTERNAL_DMA, // 1 - GHWCFG2_ARCH_INTERNAL_DMA, // 2 + GHWCFFG4_PHY_DATA_WIDTH_8 = 0, + GHWCFFG4_PHY_DATA_WIDTH_16 = 1, + GHWCFFG4_PHY_DATA_WIDTH_8_16 = 2, // software selectable }; //-------------------------------------------------------------------- // Register bitfield definitions //-------------------------------------------------------------------- typedef struct TU_ATTR_PACKED { - uint32_t op_mode : 3; // 0: HNP and SRP | 1: SRP | 2: non-HNP, non-SRP - uint32_t arch : 2; // 0: slave-only | 1: External DMA | 2: Internal DMA | 3: others - uint32_t point2point : 1; // 0: support hub and split | 1: no hub, no split - uint32_t hs_phy_type : 2; // 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI - uint32_t fs_phy_type : 2; // 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI - uint32_t num_dev_ep : 4; // Number of device endpoints (not including EP0) - uint32_t num_host_ch : 4; // Number of host channel - uint32_t period_channel_support : 1; // Support Periodic OUT Host Channel - uint32_t enable_dynamic_fifo : 1; // Dynamic FIFO Sizing Enabled - uint32_t mul_cpu_int : 1; // Multi-Processor Interrupt Enabled - uint32_t reserved21 : 1; - uint32_t nperiod_tx_q_depth : 2; // Non-periodic request queue depth: 0 = 2. 1 = 4, 2 = 8 - uint32_t host_period_tx_q_depth : 2; // Host periodic request queue depth: 0 = 2. 1 = 4, 2 = 8 - uint32_t dev_token_q_depth : 5; // Device IN token sequence learning queue depth: 0-30 - uint32_t otg_enable_ic_usb : 1; // IC_USB mode specified for mode of operation -} dwc2_ghwcfg2_t; -TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg2_t) == 4, "incorrect size"); - -typedef struct TU_ATTR_PACKED { - uint32_t xfer_size_width : 4; // Transfer size counter in bits = 11 + n (max 19 bits) - uint32_t packet_size_width : 3; // Packet size counter in bits = 4 + n (max 10 bits) - uint32_t otg_enable : 1; // 1 is OTG capable - uint32_t i2c_enable : 1; // I2C interface is available - uint32_t vendor_ctrl_itf : 1; // Vendor control interface is available - uint32_t optional_feature_removed : 1; // remove User ID, GPIO, SOF toggle & counter - uint32_t synch_reset : 1; // 0: async reset | 1: synch reset - uint32_t otg_adp_support : 1; // ADP logic is present along with HSOTG controller - uint32_t otg_enable_hsic : 1; // 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC - uint32_t battery_charger_support : 1; // support battery charger - uint32_t lpm_mode : 1; // LPC mode - uint32_t dfifo_depth : 16; // DFIFO depth - EP_LOC_CNT in terms of 32-bit words -}dwc2_ghwcfg3_t; -TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size"); - -typedef struct TU_ATTR_PACKED { - uint32_t num_dev_period_in_ep : 4; // Number of Device Periodic IN Endpoints - uint32_t power_optimized : 1; // Partial Power Down Enabled - uint32_t ahb_freq_min : 1; // 1: minimum of AHB frequency is less than 60 MHz - uint32_t hibernation : 1; // Hibernation feature is enabled - uint32_t reserved7 : 3; - uint32_t service_interval_mode : 1; // Service Interval supported - uint32_t ipg_isoc_en : 1; // IPG ISOC supported - uint32_t acg_enable : 1; // ACG enabled - uint32_t reserved13 : 1; - uint32_t utmi_phy_data_width : 2; // 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable - uint32_t dev_ctrl_ep_num : 4; // Number of Device control endpoints in addition to EP0 - uint32_t iddg_filter_enabled : 1; - uint32_t vbus_valid_filter_enabled : 1; - uint32_t a_valid_filter_enabled : 1; - uint32_t b_valid_filter_enabled : 1; - uint32_t dedicated_fifos : 1; // Dedicated tx fifo for device IN Endpoint is enabled - uint32_t num_dev_in_eps : 4; // Number of Device IN Endpoints including EP0 - uint32_t dma_desc_enable : 1; // scatter/gather DMA configuration - uint32_t dma_dynamic : 1; // Dynamic scatter/gather DMA -}dwc2_ghwcfg4_t; -TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size"); - -typedef struct TU_ATTR_PACKED { - uint32_t ses_req_scs : 1; // 0: Session request success - uint32_t ses_req : 1; // 1: Session request - uint32_t vbval_ov_en : 1; // 2: VBUS valid override enable - uint32_t vbval_ov_val : 1; // 3: VBUS valid override value - uint32_t aval_ov_en : 1; // 4: A-peripheral session valid override enable - uint32_t aval_ov_al : 1; // 5: A-peripheral session valid override value - uint32_t bval_ov_en : 1; // 6: B-peripheral session valid override enable - uint32_t bval_ov_val : 1; // 7: B-peripheral session valid override value - uint32_t hng_scs : 1; // 8: Host negotiation success - uint32_t hnp_rq : 1; // 9: HNP (host negotiation protocol) request - uint32_t host_set_hnp_en : 1; // 10: Host set HNP enable - uint32_t dev_hnp_en : 1; // 11: Device HNP enabled - uint32_t embedded_host_en : 1; // 12: Embedded host enable - uint32_t rsv13_14 : 2; // 13..14: Reserved - uint32_t dbnc_filter_bypass : 1; // 15: Debounce filter bypass - uint32_t cid_status : 1; // 16: Connector ID status - uint32_t dbnc_done : 1; // 17: Debounce done - uint32_t ases_valid : 1; // 18: A-session valid - uint32_t bses_valid : 1; // 19: B-session valid - uint32_t otg_ver : 1; // 20: OTG version 0: v1.3, 1: v2.0 - uint32_t current_mode : 1; // 21: Current mode of operation 0: device, 1: host - uint32_t mult_val_id_bc : 5; // 22..26: Multi-valued input pin ID battery charger - uint32_t chirp_en : 1; // 27: Chirp detection enable - uint32_t rsv28_30 : 3; // 28..30: Reserved - uint32_t test_mode_corr_eusb2 : 1; // 31: Test mode control for eUSB2 PHY + uint32_t ses_req_scs : 1; // 0 Session request success + uint32_t ses_req : 1; // 1 Session request + uint32_t vbval_ov_en : 1; // 2 VBUS valid override enable + uint32_t vbval_ov_val : 1; // 3 VBUS valid override value + uint32_t aval_ov_en : 1; // 4 A-peripheral session valid override enable + uint32_t aval_ov_al : 1; // 5 A-peripheral session valid override value + uint32_t bval_ov_en : 1; // 6 B-peripheral session valid override enable + uint32_t bval_ov_val : 1; // 7 B-peripheral session valid override value + uint32_t hng_scs : 1; // 8 Host negotiation success + uint32_t hnp_rq : 1; // 9 HNP (host negotiation protocol) request + uint32_t host_set_hnp_en : 1; // 10 Host set HNP enable + uint32_t dev_hnp_en : 1; // 11 Device HNP enabled + uint32_t embedded_host_en : 1; // 12 Embedded host enable + uint32_t rsv13_14 : 2; // 13.14 Reserved + uint32_t dbnc_filter_bypass : 1; // 15 Debounce filter bypass + uint32_t cid_status : 1; // 16 Connector ID status + uint32_t dbnc_done : 1; // 17 Debounce done + uint32_t ases_valid : 1; // 18 A-session valid + uint32_t bses_valid : 1; // 19 B-session valid + uint32_t otg_ver : 1; // 20 OTG version 0: v1.3, 1: v2.0 + uint32_t current_mode : 1; // 21 Current mode of operation 0: device, 1: host + uint32_t mult_val_id_bc : 5; // 22..26 Multi-valued input pin ID battery charger + uint32_t chirp_en : 1; // 27 Chirp detection enable + uint32_t rsv28_30 : 3; // 28.30: Reserved + uint32_t test_mode_corr_eusb2 : 1; // 31 Test mode control for eUSB2 PHY } dwc2_gotgctl_t; TU_VERIFY_STATIC(sizeof(dwc2_gotgctl_t) == 4, "incorrect size"); typedef struct TU_ATTR_PACKED { - uint32_t rsv0_1 : 2; // 0..1 : Reserved - uint32_t ses_end_det : 1; // 2 : Session end detected - uint32_t rsv3_7 : 5; // 3..7 : Reserved - uint32_t srs_status_change : 1; // 8 : Session request success status change - uint32_t hns_status_change : 1; // 9 : Host negotiation success status change - uint32_t rsv10_16 : 7; // 10..16 : Reserved - uint32_t hng_det : 1; // 17 : Host negotiation detected - uint32_t adev_timeout_change : 1; // 18 : A-device timeout change - uint32_t dbnc_done : 1; // 19 : Debounce done - uint32_t mult_val_lp_change : 1; // 20 : Multi-valued input pin change - uint32_t rsv21_31 :11; // 21..31 : Reserved + uint32_t rsv0_1 : 2; // 0..1 Reserved + uint32_t ses_end_det : 1; // 2 Session end detected + uint32_t rsv3_7 : 5; // 3..7 Reserved + uint32_t srs_status_change : 1; // 8 Session request success status change + uint32_t hns_status_change : 1; // 9 Host negotiation success status change + uint32_t rsv10_16 : 7; // 10..16 Reserved + uint32_t hng_det : 1; // 17 Host negotiation detected + uint32_t adev_timeout_change : 1; // 18 A-device timeout change + uint32_t dbnc_done : 1; // 19 Debounce done + uint32_t mult_val_lp_change : 1; // 20 Multi-valued input pin change + uint32_t rsv21_31 :11; // 21..31 Reserved } dwc2_gotgint_t; TU_VERIFY_STATIC(sizeof(dwc2_gotgint_t) == 4, "incorrect size"); typedef struct TU_ATTR_PACKED { - uint32_t gintmask : 1; // 0: Global interrupt mask - uint32_t hbst_len : 4; // 1..4: Burst length/type - uint32_t dma_en : 1; // 5: DMA enable - uint32_t rsv6 : 1; // 6: Reserved - uint32_t nptxf_empty_lvl : 1; // 7: Non-periodic Tx FIFO empty level - uint32_t ptxf_empty_lvl : 1; // 8: Periodic Tx FIFO empty level - uint32_t rsv9_20 : 12; // 9..20: Reserved - uint32_t remote_mem_support : 1; // 21: Remote memory support - uint32_t notify_all_dma_write : 1; // 22: Notify all DMA writes - uint32_t ahb_single : 1; // 23: AHB single - uint32_t inv_desc_endian : 1; // 24: Inverse descriptor endian - uint32_t rsv25_31 : 7; // 25..31: Reserved + uint32_t gintmask : 1; // 0 Global interrupt mask + uint32_t hbst_len : 4; // 1..4 Burst length/type + uint32_t dma_en : 1; // 5 DMA enable + uint32_t rsv6 : 1; // 6 Reserved + uint32_t nptxf_empty_lvl : 1; // 7 Non-periodic Tx FIFO empty level + uint32_t ptxf_empty_lvl : 1; // 8 Periodic Tx FIFO empty level + uint32_t rsv9_20 : 12; // 9.20: Reserved + uint32_t remote_mem_support : 1; // 21 Remote memory support + uint32_t notify_all_dma_write : 1; // 22 Notify all DMA writes + uint32_t ahb_single : 1; // 23 AHB single + uint32_t inv_desc_endian : 1; // 24 Inverse descriptor endian + uint32_t rsv25_31 : 7; // 25..31 Reserved } dwc2_gahbcfg_t; TU_VERIFY_STATIC(sizeof(dwc2_gahbcfg_t) == 4, "incorrect size"); typedef struct TU_ATTR_PACKED { - uint32_t timeout_cal : 3; /* 0..2: Timeout calibration. + uint32_t timeout_cal : 3; /* 0..2 Timeout calibration. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times. The USB standard timeout value for full- speed operation is 16 to 18 (inclusive) bit times. The application must program this field based on the speed of enumeration. The number of bit times added per PHY clock are as follows: - High-speed: PHY clock One 30-MHz = 16 bit times, One 60-MHz = 8 bit times - Full-speed: PHY clock One 30-MHz = 0.4 bit times, One 60-MHz = 0.2 bit times, One 48-MHz = 0.25 bit times */ - uint32_t phy_if : 1; // 3: PHY interface. 0: 8 bits, 1: 16 bits - uint32_t ulpi_utmi_sel : 1; // 4: ULPI/UTMI select. 0: UTMI+, 1: ULPI - uint32_t fs_intf_sel : 1; // 5: Fullspeed serial interface select. 0: 6-pin, 1: 3-pin - uint32_t phy_sel : 1; // 6: HS/FS PHY selection. 0: HS UTMI+ or ULPI, 1: FS serial transceiver - uint32_t ddr_sel : 1; // 7 ULPI DDR select. 0: Single data rate 8-bit, 1: Double data rate 4-bit - uint32_t srp_capable : 1; // 8: SRP-capable - uint32_t hnp_capable : 1; // 9: HNP-capable - uint32_t turnaround_time : 4; // 10..13 Turnaround time. 9: 8-bit UTMI+, 5: 16-bit UTMI+ - uint32_t rsv14 : 1; // 14: Reserved - uint32_t phy_low_power_clk_sel : 1; /* 15: PHY low-power clock select either 480-MHz or 48-MHz (low-power) PHY mode. + uint32_t phy_if : 1; // 3 PHY interface. 0: 8 bits, 1: 16 bits + uint32_t ulpi_utmi_sel : 1; // 4 ULPI/UTMI select. 0: UTMI+, 1: ULPI + uint32_t fs_intf_sel : 1; // 5 Fullspeed serial interface select. 0: 6-pin, 1: 3-pin + uint32_t phy_sel : 1; // 6 HS/FS PHY selection. 0: HS UTMI+ or ULPI, 1: FS serial transceiver + uint32_t ddr_sel : 1; // 7 ULPI DDR select. 0: Single data rate 8-bit, 1: Double data rate 4-bit + uint32_t srp_capable : 1; // 8 SRP-capable + uint32_t hnp_capable : 1; // 9 HNP-capable + uint32_t turnaround_time : 4; // 10..13 Turnaround time. 9: 8-bit UTMI+, 5: 16-bit UTMI+ + uint32_t rsv14 : 1; // 14 Reserved + uint32_t phy_low_power_clk_sel : 1; /* 15 PHY low-power clock select either 480-MHz or 48-MHz (low-power) PHY mode. In FS/LS modes, the PHY can usually operate on a 48-MHz clock to save power. This bit is valid only for UTMI+ PHYs. - 0: 480 Mhz internal PLL: the UTMI interface operates at either 60 MHz (8 bit) or 30 MHz (16-bit) - 1 48 Mhz external clock: the UTMI interface operates at 48 MHz in FS mode and at either 48 or 6 MHz in LS mode */ - uint32_t otg_i2c_sel : 1; // 16: OTG I2C interface select. 0: UTMI-FS, 1: I2C for OTG signals - uint32_t ulpi_fsls : 1; /* 17: ULPI FS/LS select. 0: ULPI, 1: ULPI FS/LS. - valid only when the FS serial transceiver is selected on the ULPI PHY. */ - uint32_t ulpi_auto_resume : 1; // 18: ULPI Auto-resume - uint32_t ulpi_clk_sus_m : 1; // 19: ULPI Clock SuspendM - uint32_t ulpi_ext_vbus_drv : 1; // 20: ULPI External VBUS Drive - uint32_t ulpi_int_vbus_indicator : 1; // 21: ULPI Internal VBUS Indicator - uint32_t term_sel_dl_pulse : 1; // 22: TermSel DLine pulsing - uint32_t indicator_complement : 1; // 23: Indicator complement - uint32_t indicator_pass_through : 1; // 24: Indicator pass through - uint32_t ulpi_if_protect_disable : 1; // 25: ULPI interface protect disable - uint32_t ic_usb_capable : 1; // 26: IC_USB Capable - uint32_t ic_usb_traf_ctl : 1; // 27: IC_USB Traffic Control - uint32_t tx_end_delay : 1; // 28: TX end delay - uint32_t force_host_mode : 1; // 29: Force host mode - uint32_t force_dev_mode : 1; // 30: Force device mode - uint32_t corrupt_tx_pkt : 1; // 31: Corrupt Tx packet. 0: normal, 1: debug + uint32_t otg_i2c_sel : 1; // 16 OTG I2C interface select. 0: UTMI-FS, 1: I2C for OTG signals + uint32_t ulpi_fsls : 1; /* 17 ULPI FS/LS select. 0: ULPI, 1: ULPI FS/LS. + valid only when the FS serial transceiver is selected on the ULPI PHY. */ + uint32_t ulpi_auto_resume : 1; // 18 ULPI Auto-resume + uint32_t ulpi_clk_sus_m : 1; // 19 ULPI Clock SuspendM + uint32_t ulpi_ext_vbus_drv : 1; // 20 ULPI External VBUS Drive + uint32_t ulpi_int_vbus_indicator : 1; // 21 ULPI Internal VBUS Indicator + uint32_t term_sel_dl_pulse : 1; // 22 TermSel DLine pulsing + uint32_t indicator_complement : 1; // 23 Indicator complement + uint32_t indicator_pass_through : 1; // 24 Indicator pass through + uint32_t ulpi_if_protect_disable : 1; // 25 ULPI interface protect disable + uint32_t ic_usb_capable : 1; // 26 IC_USB Capable + uint32_t ic_usb_traf_ctl : 1; // 27 IC_USB Traffic Control + uint32_t tx_end_delay : 1; // 28 TX end delay + uint32_t force_host_mode : 1; // 29 Force host mode + uint32_t force_dev_mode : 1; // 30 Force device mode + uint32_t corrupt_tx_pkt : 1; // 31 Corrupt Tx packet. 0: normal, 1: debug } dwc2_gusbcfg_t; TU_VERIFY_STATIC(sizeof(dwc2_gusbcfg_t) == 4, "incorrect size"); +typedef struct TU_ATTR_PACKED { + uint32_t core_soft_rst : 1; // 0 Core Soft Reset + uint32_t piufs_soft_rst : 1; // 1 PIU FS Dedicated Controller Soft Reset + uint32_t frame_counter_rst : 1; // 2 Frame Counter Reset (host) + uint32_t intoken_q_flush : 1; // 3 IN Token Queue Flush + uint32_t rx_fifo_flush : 1; // 4 RX FIFO Flush + uint32_t tx_fifo_flush : 1; // 5 TX FIFO Flush + uint32_t tx_fifo_num : 5; // 6..10 TX FIFO Number + uint32_t rsv11_28 :18; // 11..28 Reserved + uint32_t core_soft_rst_done : 1; // 29 Core Soft Reset Done, from v4.20a + uint32_t dma_req : 1; // 30 DMA Request + uint32_t ahb_idle : 1; // 31 AHB Idle +} dwc2_grstctl_t; +TU_VERIFY_STATIC(sizeof(dwc2_grstctl_t) == 4, "incorrect size"); + +typedef struct TU_ATTR_PACKED { + uint32_t op_mode : 3; // 0..2 HNP/SRP Host/Device/OTG mode + uint32_t arch : 2; // 3..4 Slave/External/Internal DMA + uint32_t point2point : 1; // 5 0: support hub and split | 1: no hub, no split + uint32_t hs_phy_type : 2; // 6..7 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI + uint32_t fs_phy_type : 2; // 8..9 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI + uint32_t num_dev_ep : 4; // 10..13 Number of device endpoints (excluding EP0) + uint32_t num_host_ch : 4; // 14..17 Number of host channel (excluding control) + uint32_t period_channel_support : 1; // 18 Support Periodic OUT Host Channel + uint32_t enable_dynamic_fifo : 1; // 19 Dynamic FIFO Sizing Enabled + uint32_t mul_cpu_int : 1; // 20 Multi-Processor Interrupt Enabled + uint32_t reserved21 : 1; // 21 reserved + uint32_t nptx_q_depth : 2; // 22..23 Non-periodic request queue depth: 0 = 2. 1 = 4, 2 = 8 + uint32_t ptx_q_depth : 2; // 24..25 Host periodic request queue depth: 0 = 2. 1 = 4, 2 = 8 + uint32_t token_q_depth : 5; // 26..30 Device IN token sequence learning queue depth: 0-30 + uint32_t otg_enable_ic_usb : 1; // 31 IC_USB mode specified for mode of operation +} dwc2_ghwcfg2_t; +TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg2_t) == 4, "incorrect size"); + +typedef struct TU_ATTR_PACKED { + uint32_t xfer_size_width : 4; // 0..3 Transfer size counter in bits = 11 + n (max 19 bits) + uint32_t packet_size_width : 3; // 4..6 Packet size counter in bits = 4 + n (max 10 bits) + uint32_t otg_enable : 1; // 7 OTG capable + uint32_t i2c_enable : 1; // 8 I2C interface is available + uint32_t vendor_ctrl_itf : 1; // 9 Vendor control interface is available + uint32_t optional_feature_removed : 1; // 10 remove User ID, GPIO, SOF toggle & counter to save gate count + uint32_t synch_reset : 1; // 11 0: async reset | 1: synch reset + uint32_t otg_adp_support : 1; // 12 ADP logic is present along with HSOTG controller + uint32_t otg_enable_hsic : 1; // 13 1: HSIC-capable with shared UTMI PHY interface | 0: non-HSIC + uint32_t battery_charger_support : 1; // s14 upport battery charger + uint32_t lpm_mode : 1; // 15 LPM mode + uint32_t dfifo_depth : 16; // DFIFO depth - EP_LOC_CNT in terms of 32-bit words +}dwc2_ghwcfg3_t; +TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg3_t) == 4, "incorrect size"); + +typedef struct TU_ATTR_PACKED { + uint32_t num_dev_period_in_ep : 4; // 0..3 Number of Device Periodic IN Endpoints + uint32_t partial_powerdown : 1; // 4 Partial Power Down Enabled + uint32_t ahb_freq_min : 1; // 5 1: minimum of AHB frequency is less than 60 MHz + uint32_t hibernation : 1; // 6 Hibernation feature is enabled + uint32_t extended_hibernation : 1; // 7 Extended Hibernation feature is enabled + uint32_t reserved8 : 1; // 8 Reserved + uint32_t enhanced_lpm_support1 : 1; // 9 Enhanced LPM Support1 + uint32_t service_interval_flow : 1; // 10 Service Interval flow is supported + uint32_t ipg_isoc_support : 1; // 11 Interpacket GAP ISO OUT worst-case is supported + uint32_t acg_support : 1; // 12 Active clock gating is supported + uint32_t enhanced_lpm_support : 1; // 13 Enhanced LPM Support + uint32_t phy_data_width : 2; // 14..15 0: 8 bits | 1: 16 bits | 2: 8/16 software selectable + uint32_t ctrl_ep_num : 4; // 16..19 Number of Device control endpoints in addition to EP0 + uint32_t iddg_filter : 1; // 20 IDDG Filter Enabled + uint32_t vbus_valid_filter : 1; // 21 VBUS Valid Filter Enabled + uint32_t a_valid_filter : 1; // 22 A Valid Filter Enabled + uint32_t b_valid_filter : 1; // 23 B Valid Filter Enabled + uint32_t session_end_filter : 1; // 24 Session End Filter Enabled + uint32_t dedicated_fifos : 1; // 25 Dedicated tx fifo for device IN Endpoint + uint32_t num_dev_in_eps : 4; // 26..29 Number of Device IN Endpoints including EP0 + uint32_t dma_desc_enabled : 1; // scatter/gather DMA configuration enabled + uint32_t dma_desc_dynamic : 1; // Dynamic scatter/gather DMA +}dwc2_ghwcfg4_t; +TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size"); + // Host Channel typedef struct { volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics @@ -306,103 +340,103 @@ typedef struct { // CSR Register Map //-------------------------------------------------------------------- typedef struct { - //------------- Core Global -------------// - volatile uint32_t gotgctl; // 000 OTG Control and Status - volatile uint32_t gotgint; // 004 OTG Interrupt - volatile uint32_t gahbcfg; // 008 AHB Configuration - volatile uint32_t gusbcfg; // 00c USB Configuration - volatile uint32_t grstctl; // 010 Reset - volatile uint32_t gintsts; // 014 Interrupt - volatile uint32_t gintmsk; // 018 Interrupt Mask - volatile uint32_t grxstsr; // 01c Receive Status Debug Read - volatile uint32_t grxstsp; // 020 Receive Status Read/Pop - volatile uint32_t grxfsiz; // 024 Receive FIFO Size -union { - volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size - volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size -}; - volatile uint32_t gnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status - volatile uint32_t gi2cctl; // 030 I2C Address - volatile uint32_t gpvndctl; // 034 PHY Vendor Control -union { - volatile uint32_t ggpio; // 038 General Purpose IO - volatile uint32_t stm32_gccfg; // 038 STM32 General Core Configuration -}; - volatile uint32_t guid; // 03C User (Application programmable) ID - volatile uint32_t gsnpsid; // 040 Synopsys ID + Release version - volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep) -union { - volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2 - volatile dwc2_ghwcfg2_t ghwcfg2_bm; -}; -union { - volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3 - volatile dwc2_ghwcfg3_t ghwcfg3_bm; -}; -union { - volatile uint32_t ghwcfg4; // 050 User Hardware Configuration4 - volatile dwc2_ghwcfg4_t ghwcfg4_bm; -}; - volatile uint32_t glpmcfg; // 054 Core LPM Configuration - volatile uint32_t gpwrdn; // 058 Power Down - volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration - volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status - uint32_t reserved64[39]; // 064..0FF - volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size - volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size - uint32_t reserved140[176]; // 140..3FF - - //------------- Host -------------// - volatile uint32_t hcfg; // 400 Host Configuration - volatile uint32_t hfir; // 404 Host Frame Interval - volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining - uint32_t reserved40c; // 40C - volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status - volatile uint32_t haint; // 414 Host All Channels Interrupt - volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask - volatile uint32_t hflbaddr; // 41C Host Frame List Base Address - uint32_t reserved420[8]; // 420..43F - volatile uint32_t hprt; // 440 Host Port Control and Status - uint32_t reserved444[47]; // 444..4FF - - //------------- Host Channel -------------// - dwc2_channel_t channel[16]; // 500..6FF Host Channels 0-15 - uint32_t reserved700[64]; // 700..7FF - - //------------- Device -------------// - volatile uint32_t dcfg; // 800 Device Configuration - volatile uint32_t dctl; // 804 Device Control - volatile uint32_t dsts; // 808 Device Status (RO) - uint32_t reserved80c; // 80C - volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask - volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask - volatile uint32_t daint; // 818 Device All Endpoints Interrupt - volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask - volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read1 - volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read2 - volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time - volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time - volatile uint32_t dthrctl; // 830 Device threshold Control - volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask - volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt - volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt msk - volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask - volatile uint32_t doepeachmsk[16]; // 880..8BF Device Each OUT Endpoint mask - uint32_t reserved8c0[16]; // 8C0..8FF - - //------------- Device Endpoint -------------// - dwc2_epin_t epin[16]; // 900..AFF IN Endpoints - dwc2_epout_t epout[16]; // B00..CFF OUT Endpoints - uint32_t reservedd00[64]; // D00..DFF - - //------------- Power Clock -------------// - volatile uint32_t pcgctl; // E00 Power and Clock Gating Control - volatile uint32_t pcgctl1; // E04 - uint32_t reservede08[126]; // E08..FFF - - //------------- FIFOs -------------// - // Word-accessed only using first pointer since it auto shift - volatile uint32_t fifo[16][0x400]; // 1000..FFFF Endpoint FIFO + //------------- Core Global -------------// + volatile uint32_t gotgctl; // 000 OTG Control and Status + volatile uint32_t gotgint; // 004 OTG Interrupt + volatile uint32_t gahbcfg; // 008 AHB Configuration + volatile uint32_t gusbcfg; // 00c USB Configuration + volatile uint32_t grstctl; // 010 Reset + volatile uint32_t gintsts; // 014 Interrupt + volatile uint32_t gintmsk; // 018 Interrupt Mask + volatile uint32_t grxstsr; // 01c Receive Status Debug Read + volatile uint32_t grxstsp; // 020 Receive Status Read/Pop + volatile uint32_t grxfsiz; // 024 Receive FIFO Size + union { + volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size + volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size + }; + volatile uint32_t gnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status + volatile uint32_t gi2cctl; // 030 I2C Address + volatile uint32_t gpvndctl; // 034 PHY Vendor Control + union { + volatile uint32_t ggpio; // 038 General Purpose IO + volatile uint32_t stm32_gccfg; // 038 STM32 General Core Configuration + }; + volatile uint32_t guid; // 03C User (Application programmable) ID + volatile uint32_t gsnpsid; // 040 Synopsys ID + Release version + volatile uint32_t ghwcfg1; // 044 User Hardware Configuration1: endpoint dir (2 bit per ep) + union { + volatile uint32_t ghwcfg2; // 048 User Hardware Configuration2 + volatile dwc2_ghwcfg2_t ghwcfg2_bm; + }; + union { + volatile uint32_t ghwcfg3; // 04C User Hardware Configuration3 + volatile dwc2_ghwcfg3_t ghwcfg3_bm; + }; + union { + volatile uint32_t ghwcfg4; // 050 User Hardware Configuration4 + volatile dwc2_ghwcfg4_t ghwcfg4_bm; + }; + volatile uint32_t glpmcfg; // 054 Core LPM Configuration + volatile uint32_t gpwrdn; // 058 Power Down + volatile uint32_t gdfifocfg; // 05C DFIFO Software Configuration + volatile uint32_t gadpctl; // 060 ADP Timer, Control and Status + uint32_t reserved64[39]; // 064..0FF + volatile uint32_t hptxfsiz; // 100 Host Periodic Tx FIFO Size + volatile uint32_t dieptxf[15]; // 104..13C Device Periodic Transmit FIFO Size + uint32_t reserved140[176]; // 140..3FF + + //------------ Host -------------// + volatile uint32_t hcfg; // 400 Host Configuration + volatile uint32_t hfir; // 404 Host Frame Interval + volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining + uint32_t reserved40c; // 40C + volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status + volatile uint32_t haint; // 414 Host All Channels Interrupt + volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask + volatile uint32_t hflbaddr; // 41C Host Frame List Base Address + uint32_t reserved420[8]; // 420..43F + volatile uint32_t hprt; // 440 Host Port Control and Status + uint32_t reserved444[47]; // 444..4FF + + //------------- Host Channel -------------// + dwc2_channel_t channel[16]; // 500..6FF Host Channels 0-15 + uint32_t reserved700[64]; // 700..7FF + + //------------- Device -----------// + volatile uint32_t dcfg; // 800 Device Configuration + volatile uint32_t dctl; // 804 Device Control + volatile uint32_t dsts; // 808 Device Status (RO) + uint32_t reserved80c; // 80C + volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask + volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask + volatile uint32_t daint; // 818 Device All Endpoints Interrupt + volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask + volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read1 + volatile uint32_t dtknqr2; // 824 Device IN token sequence learning queue read2 + volatile uint32_t dvbusdis; // 828 Device VBUS Discharge Time + volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time + volatile uint32_t dthrctl; // 830 Device threshold Control + volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask + volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt + volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt msk + volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask + volatile uint32_t doepeachmsk[16]; // 880..8BF Device Each OUT Endpoint mask + uint32_t reserved8c0[16]; // 8C0..8FF + + //------------- Device Endpoint -------------// + dwc2_epin_t epin[16]; // 900..AFF IN Endpoints + dwc2_epout_t epout[16]; // B00..CFF OUT Endpoints + uint32_t reservedd00[64]; // D00..DFF + + //------------- Power Clock -------------// + volatile uint32_t pcgctl; // E00 Power and Clock Gating Control + volatile uint32_t pcgctl1; // E04 + uint32_t reservede08[126]; // E08..FFF + + //------------- FIFOs -------------// + // Word-accessed only using first pointer since it auto shift + volatile uint32_t fifo[16][0x400]; // 1000..FFFF Endpoint FIFO } dwc2_regs_t; TU_VERIFY_STATIC(offsetof(dwc2_regs_t, hcfg ) == 0x0400, "incorrect size"); -- cgit v1.3.1 From 67e5577b428e70878d99c4f83039cef020a272cb Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 25 Sep 2024 20:36:16 +0700 Subject: added p4, seems to work well and enumerated --- .idea/cmake.xml | 9 +- .../boards/espressif_p4_function_ev/board.cmake | 2 + .../boards/espressif_p4_function_ev/board.h | 43 ++++++++ hw/bsp/espressif/family.cmake | 3 + src/common/tusb_mcu.h | 6 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 23 ++-- src/portable/synopsys/dwc2/dwc2_esp32.h | 48 +++++++-- src/portable/synopsys/dwc2/dwc2_info.md | 116 ++++++++++----------- src/portable/synopsys/dwc2/dwc2_info.py | 1 + 9 files changed, 164 insertions(+), 87 deletions(-) create mode 100644 hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake create mode 100644 hw/bsp/espressif/boards/espressif_p4_function_ev/board.h (limited to 'src/portable') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 96ff19c89..b6a237a1d 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -37,7 +37,7 @@ - + @@ -145,6 +145,13 @@ + + + + + + + \ No newline at end of file diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake new file mode 100644 index 000000000..fe4db4fc1 --- /dev/null +++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.cmake @@ -0,0 +1,2 @@ +# Apply board specific content here +set(IDF_TARGET "esp32p4") diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h new file mode 100644 index 000000000..9c8aa409f --- /dev/null +++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h @@ -0,0 +1,43 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +// #define NEOPIXEL_PIN 48 + +#define BUTTON_PIN 0 +#define BUTTON_STATE_ACTIVE 0 + +#ifdef __cplusplus + } +#endif + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake index eb97401c3..b0786f1cc 100644 --- a/hw/bsp/espressif/family.cmake +++ b/hw/bsp/espressif/family.cmake @@ -8,4 +8,7 @@ string(TOUPPER ${IDF_TARGET} FAMILY_MCUS) # Add example src and bsp directories set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components") +# set SDKCONFIG for each IDF Target +set(SDKCONFIG ${CMAKE_SOURCE_DIR}/sdkconfig.${IDF_TARGET}) + include($ENV{IDF_PATH}/tools/cmake/project.cmake) diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 26a8ee26b..6b19ac9fe 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -337,13 +337,13 @@ #elif TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) #define TUP_USBIP_DWC2 #define TUP_USBIP_DWC2_ESP32 - #define TUP_DCD_ENDPOINT_MAX 6 + #define TUP_DCD_ENDPOINT_MAX 7 // only 5 TX FIFO for endpoint IN #elif TU_CHECK_MCU(OPT_MCU_ESP32P4) #define TUP_USBIP_DWC2 #define TUP_USBIP_DWC2_ESP32 - #define TUP_RHPORT_HIGHSPEED 1 // 1 port FS, 1 port HS - #define TUP_DCD_ENDPOINT_MAX 8 // FS 6 ep, HS 8 ep + #define TUP_RHPORT_HIGHSPEED 1 // port0 FS, port1 HS + #define TUP_DCD_ENDPOINT_MAX 16 // FS 7 ep, HS 16 ep #elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2) #if (CFG_TUD_ENABLED || !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 13143073d..d1eb22ed7 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -508,18 +508,6 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ -#if CFG_TUSB_DEBUG >= DWC2_DEBUG -void print_dwc2_info(dwc2_regs_t* dwc2) { - // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4 - // use dwc2_info.py/md for bit-field value and comparison with other ports - volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid; - TU_LOG(DWC2_DEBUG, "guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n"); - for (size_t i = 0; i < 5; i++) { - TU_LOG(DWC2_DEBUG, "0x%08" PRIX32 ", ", p[i]); - } - TU_LOG(DWC2_DEBUG, "0x%08" PRIX32 "\r\n", p[5]); -} -#endif static void reset_core(dwc2_regs_t* dwc2) { // reset core @@ -633,8 +621,15 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { } static bool check_dwc2(dwc2_regs_t* dwc2) { -#if CFG_TUSB_DEBUG >= DWC2_DEBUG - print_dwc2_info(dwc2); +#if CFG_TUSB_DEBUG >= DWC2_DEBUG || 1 + // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4 + // Run 'dwc2_info.py render-md' and check dwc2_info.md for bit-field value and comparison with other ports + volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid; + TU_LOG1("guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n"); + for (size_t i = 0; i < 5; i++) { + TU_LOG1("0x%08" PRIX32 ", ", p[i]); + } + TU_LOG1("0x%08" PRIX32 "\r\n", p[5]); #endif // For some reason: GD32VF103 snpsid and all hwcfg register are always zero (skip it) diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index 921cee29e..af04347d1 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -38,29 +38,55 @@ #include "soc/periph_defs.h" #include "soc/usb_wrap_struct.h" -#define DWC2_REG_BASE 0x60080000UL -#define DWC2_EP_MAX 7 -#define DWC2_EP_IN_MAX 5 +#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) +#define DWC2_PERIPH_COUNT 1 +#define DWC2_FS_REG_BASE 0x60080000UL +#define DWC2_EP_MAX 7 static const dwc2_controller_t _dwc2_controller[] = { - { .reg_base = DWC2_REG_BASE, .irqnum = 0, .ep_count = DWC2_EP_MAX, .ep_in_count = DWC2_EP_IN_MAX, .ep_fifo_size = 1024 } + { .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 } }; -static intr_handle_t usb_ih; +#elif TU_CHECK_MCU(OPT_MCU_ESP32P4) + +#define DWC2_PERIPH_COUNT 2 +#define DWC2_FS_REG_BASE 0x50040000UL +#define DWC2_HS_REG_BASE 0x50000000UL +#define DWC2_EP_MAX 16 + +// On ESP32 for consistency we associate +// - Port0 to OTG_FS, and Port1 to OTG_HS +static const dwc2_controller_t _dwc2_controller[] = { + { + .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, + .ep_fifo_size = 4096 + }, +{ + .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, + .ep_fifo_size = 1024 +} + +}; +#endif + +enum { + DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller) +}; + +static intr_handle_t usb_ih[DWC2_CONTROLLER_COUNT]; static void dcd_int_handler_wrap(void* arg) { - (void)arg; - dcd_int_handler(0); + const uint8_t rhport = (uint8_t) arg; + dcd_int_handler(rhport); } TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { - (void)rhport; - esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, dcd_int_handler_wrap, NULL, &usb_ih); + esp_intr_alloc(_dwc2_controller[rhport].irqnum, ESP_INTR_FLAG_LOWMED, + dcd_int_handler_wrap, (void*) rhport, &usb_ih[rhport]); } TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) { - (void)rhport; - esp_intr_free(usb_ih); + esp_intr_free(usb_ih[rhport]); } TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index 9798fb0de..462b5856a 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -1,58 +1,58 @@ -| | BCM2711 (Pi4) | EFM32GG FS | ESP32-S2/S3 | STM32F 407/411/429 FS | STM32F 407/429 HS | STM32F 412/767 FS | STM32F723 FS | STM32F723 HS | STM32H743 HS | STM32L476 FS | STM32U5A5 HS | GD32VF103 FS | XMC4500 | -|:---------------------------|:----------------|:-------------|:--------------|:------------------------|:--------------------|:--------------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:-----------| -| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | -| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | -| - specs version | 2.80a | 3.30a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | -| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | -| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | -| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | -| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 2 | 2 | 0 | 2 | 0 | 2 | -| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | -| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 3 | 2 | 0 | 1 | 0 | 0 | -| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 5 | 5 | 8 | 8 | 5 | 8 | 0 | 6 | -| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 11 | 11 | 15 | 15 | 11 | 15 | 0 | 13 | -| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nptx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - ptx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | -| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | -| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | -| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | -| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | -| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | -| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | -| - dfifo_depth | 4080 | 498 | 200 | 512 | 1012 | 512 | 512 | 1006 | 952 | 512 | 952 | 0 | 634 | -| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | -| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - enhanced_lpm_support | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 2 | -| - ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - num_dev_in_eps | 7 | 6 | 4 | 3 | 5 | 5 | 5 | 8 | 8 | 5 | 8 | 0 | 6 | -| - dma_desc_enable | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | -| - dma_desc_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | +| | BCM2711 (Pi4) | EFM32GG FS | ESP32-S2/S3 | ESP32-P4 | STM32F 407/411/429 FS | STM32F 407/429 HS | STM32F 412/767 FS | STM32F723 FS | STM32F723 HS | STM32H743 HS | STM32L476 FS | STM32U5A5 HS | GD32VF103 FS | XMC4500 | +|:---------------------------|:----------------|:-------------|:--------------|:-----------|:------------------------|:--------------------|:--------------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:-----------| +| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | +| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | +| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | +| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | +| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| - arch | 2 | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 2 | 2 | 0 | 2 | 0 | 2 | +| - point2point | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | +| - hs_phy_type | 1 | 0 | 0 | 3 | 0 | 2 | 0 | 0 | 3 | 2 | 0 | 1 | 0 | 0 | +| - fs_phy_type | 1 | 1 | 1 | 3 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 5 | 8 | 0 | 6 | +| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 11 | 15 | 0 | 13 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nptx_q_depth | 2 | 2 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - ptx_q_depth | 2 | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | +| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | +| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | +| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | +| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 952 | 512 | 952 | 0 | 634 | +| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | +| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - phy_data_width | 0 | 2 | 2 | 2 | 2 | 0 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 2 | +| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 5 | 8 | 0 | 6 | +| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | +| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 871ac112d..e382ba011 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -9,6 +9,7 @@ dwc2_reg_value = { 'BCM2711 (Pi4)': [0x2708A000, 0x4F54280A, 0, 0x228DDD50, 0xFF000E8, 0x1FF00020], 'EFM32GG FS': [0, 0x4F54330A, 0, 0x228F5910, 0x1F204E8, 0x1BF08030], 'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0xC804B5, 0xD3F0A030], + 'ESP32-P4': [0, 0x4F54400A, 0, 0x215FFFD0, 0x03805EB5, 0xDFF1A030], 'STM32F 407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030], 'STM32F 407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030], 'STM32F 412/767 FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], -- cgit v1.3.1 From 87f199330405f0a51f8ad4b3b8b2d69c9a21ac3e Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 27 Sep 2024 15:32:47 +0700 Subject: esp32p4 use port0 as fs, port1 as highspeed --- .idea/cmake.xml | 16 +++++----- hw/bsp/espressif/boards/CMakeLists.txt | 2 -- .../components/tinyusb_src/CMakeLists.txt | 3 ++ hw/bsp/espressif/family.cmake | 10 +++++- src/portable/synopsys/dwc2/dcd_dwc2.c | 30 +++++++++++++----- src/portable/synopsys/dwc2/dwc2_esp32.h | 36 ++++++---------------- 6 files changed, 52 insertions(+), 45 deletions(-) (limited to 'src/portable') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index b6a237a1d..37cd73c65 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -37,7 +37,7 @@ - + @@ -65,6 +65,13 @@ + + + + + + + @@ -145,13 +152,6 @@ - - - - - - - \ No newline at end of file diff --git a/hw/bsp/espressif/boards/CMakeLists.txt b/hw/bsp/espressif/boards/CMakeLists.txt index fe1273d4c..434f77704 100644 --- a/hw/bsp/espressif/boards/CMakeLists.txt +++ b/hw/bsp/espressif/boards/CMakeLists.txt @@ -4,5 +4,3 @@ idf_component_register(SRCS family.c INCLUDE_DIRS "." ${BOARD} ${hw_dir} PRIV_REQUIRES driver usb REQUIRES led_strip src tinyusb_src) - -target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-error=format) diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt index 8bdb3802e..26c7e4030 100644 --- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt +++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt @@ -9,6 +9,9 @@ string(TOUPPER OPT_MCU_${target} tusb_mcu) list(APPEND compile_definitions CFG_TUSB_MCU=${tusb_mcu} CFG_TUSB_OS=OPT_OS_FREERTOS + # EXAMPLE port selection: port0 is fullspeed, port1 is highspeed + BOARD_TUD_RHPORT=${TUD_PORT} + BOARD_TUD_MAX_SPEED=$ ) list(APPEND srcs diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake index b0786f1cc..ada082c76 100644 --- a/hw/bsp/espressif/family.cmake +++ b/hw/bsp/espressif/family.cmake @@ -2,9 +2,17 @@ cmake_minimum_required(VERSION 3.5) # Apply board specific content i.e IDF_TARGET must be set before project.cmake is included include("${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake") - string(TOUPPER ${IDF_TARGET} FAMILY_MCUS) +# Device port default to Port1 for P4 (highspeed), Port0 for others (fullspeed) +if (NOT DEFINED TUD_PORT) + if (IDF_TARGET STREQUAL "esp32p4") + set(TUD_PORT 1) + else () + set(TUD_PORT 0) + endif () +endif() + # Add example src and bsp directories set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components") diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index d1eb22ed7..4fa869241 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -31,6 +31,9 @@ #if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2) +// Debug level for DWC2 +#define DWC2_DEBUG 2 + #include "device/dcd.h" #include "dwc2_type.h" @@ -57,15 +60,24 @@ #error "Unsupported MCUs" #endif -//--------------------------------------------------------------------+ -// MACRO TYPEDEF CONSTANT ENUM -//--------------------------------------------------------------------+ +enum { + DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller) +}; // DWC2 registers -#define DWC2_REG(_port) ((dwc2_regs_t*) _dwc2_controller[_port].reg_base) +//#define DWC2_REG(_port) ((dwc2_regs_t*) _dwc2_controller[_port].reg_base) -// Debug level for DWC2 -#define DWC2_DEBUG 2 +TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { + if (rhport >= DWC2_CONTROLLER_COUNT) { + // user mis-configured, ignore and use first controller + rhport = 0; + } + return (dwc2_regs_t*) _dwc2_controller[rhport].reg_base; +} + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2]; @@ -584,7 +596,9 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); // Set 16-bit interface if supported - if (dwc2->ghwcfg4_bm.phy_data_width) gusbcfg |= GUSBCFG_PHYIF16; + if (dwc2->ghwcfg4_bm.phy_data_width) { + gusbcfg |= GUSBCFG_PHYIF16; + } } // Apply config @@ -621,7 +635,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { } static bool check_dwc2(dwc2_regs_t* dwc2) { -#if CFG_TUSB_DEBUG >= DWC2_DEBUG || 1 +#if CFG_TUSB_DEBUG >= DWC2_DEBUG // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4 // Run 'dwc2_info.py render-md' and check dwc2_info.md for bit-field value and comparison with other ports volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid; diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index af04347d1..4cdbcdb7a 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -39,50 +39,36 @@ #include "soc/usb_wrap_struct.h" #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) -#define DWC2_PERIPH_COUNT 1 -#define DWC2_FS_REG_BASE 0x60080000UL -#define DWC2_EP_MAX 7 +#define DWC2_FS_REG_BASE 0x60080000UL +#define DWC2_EP_MAX 7 static const dwc2_controller_t _dwc2_controller[] = { { .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 } }; #elif TU_CHECK_MCU(OPT_MCU_ESP32P4) - -#define DWC2_PERIPH_COUNT 2 -#define DWC2_FS_REG_BASE 0x50040000UL -#define DWC2_HS_REG_BASE 0x50000000UL -#define DWC2_EP_MAX 16 +#define DWC2_FS_REG_BASE 0x50040000UL +#define DWC2_HS_REG_BASE 0x50000000UL +#define DWC2_EP_MAX 16 // On ESP32 for consistency we associate // - Port0 to OTG_FS, and Port1 to OTG_HS static const dwc2_controller_t _dwc2_controller[] = { - { - .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, - .ep_fifo_size = 4096 - }, -{ - .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, - .ep_fifo_size = 1024 -} - +{ .reg_base = DWC2_FS_REG_BASE, .irqnum = ETS_USB_OTG11_CH0_INTR_SOURCE, .ep_count = 7, .ep_in_count = 5, .ep_fifo_size = 1024 }, +{ .reg_base = DWC2_HS_REG_BASE, .irqnum = ETS_USB_OTG_INTR_SOURCE, .ep_count = 16, .ep_in_count = 8, .ep_fifo_size = 4096 } }; #endif -enum { - DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller) -}; - -static intr_handle_t usb_ih[DWC2_CONTROLLER_COUNT]; +static intr_handle_t usb_ih[TU_ARRAY_SIZE(_dwc2_controller)]; static void dcd_int_handler_wrap(void* arg) { - const uint8_t rhport = (uint8_t) arg; + const uint8_t rhport = (uint8_t)(uintptr_t) arg; dcd_int_handler(rhport); } TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { esp_intr_alloc(_dwc2_controller[rhport].irqnum, ESP_INTR_FLAG_LOWMED, - dcd_int_handler_wrap, (void*) rhport, &usb_ih[rhport]); + dcd_int_handler_wrap, (void*)(uintptr_t) rhport, &usb_ih[rhport]); } TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) { @@ -97,7 +83,6 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { (void)dwc2; (void)hs_phy_type; - // nothing to do } @@ -105,7 +90,6 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { (void)dwc2; (void)hs_phy_type; - // nothing to do } -- cgit v1.3.1 From 3fa7da95bd2a7189020ba6fe2d6aa17577f83abd Mon Sep 17 00:00:00 2001 From: "Haefner, Martin" Date: Tue, 1 Oct 2024 15:24:11 +0200 Subject: support stm32U0 device --- src/common/tusb_mcu.h | 5 +++++ src/portable/st/stm32_fsdev/fsdev_stm32.h | 26 ++++++++++++++++++++++++++ src/portable/synopsys/dwc2/dwc2_stm32.h | 7 +++++++ src/tusb_option.h | 1 + 4 files changed, 39 insertions(+) (limited to 'src/portable') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 0a4462a0a..87f47e732 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -293,6 +293,11 @@ #define TUP_USBIP_FSDEV_STM32 #define TUP_DCD_ENDPOINT_MAX 8 +#elif TU_CHECK_MCU(OPT_MCU_STM32U0) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_STM32 + #define TUP_DCD_ENDPOINT_MAX 8 + //--------------------------------------------------------------------+ // Sony //--------------------------------------------------------------------+ diff --git a/src/portable/st/stm32_fsdev/fsdev_stm32.h b/src/portable/st/stm32_fsdev/fsdev_stm32.h index 99fe8d55f..03ea4c67e 100644 --- a/src/portable/st/stm32_fsdev/fsdev_stm32.h +++ b/src/portable/st/stm32_fsdev/fsdev_stm32.h @@ -170,6 +170,30 @@ #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY #define USB_CNTR_FSUSP USB_CNTR_SUSPEN +#elif CFG_TUSB_MCU == OPT_MCU_STM32U0 + #include "stm32u0xx.h" + #define FSDEV_PMA_SIZE (2048u) + #define USB USB_DRD_FS + + #define USB_EP_CTR_RX USB_EP_VTRX + #define USB_EP_CTR_TX USB_EP_VTTX + #define USB_EP_T_FIELD USB_CHEP_UTYPE + #define USB_EPREG_MASK USB_CHEP_REG_MASK + #define USB_EPTX_DTOGMASK USB_CHEP_TX_DTOGMASK + #define USB_EPRX_DTOGMASK USB_CHEP_RX_DTOGMASK + #define USB_EPTX_DTOG1 USB_CHEP_TX_DTOG1 + #define USB_EPTX_DTOG2 USB_CHEP_TX_DTOG2 + #define USB_EPRX_DTOG1 USB_CHEP_RX_DTOG1 + #define USB_EPRX_DTOG2 USB_CHEP_RX_DTOG2 + #define USB_EPRX_STAT USB_CH_RX_VALID + #define USB_EPKIND_MASK USB_EP_KIND_MASK + #define USB_CNTR_FRES USB_CNTR_USBRST + #define USB_CNTR_RESUME USB_CNTR_L2RES + #define USB_ISTR_EP_ID USB_ISTR_IDN + #define USB_EPADDR_FIELD USB_CHEP_ADDR + #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY + #define USB_CNTR_FSUSP USB_CNTR_SUSPEN + #else #error You are using an untested or unimplemented STM32 variant. Please update the driver. // This includes U0 @@ -249,6 +273,8 @@ static const IRQn_Type fsdev_irq[] = { USB_LP_IRQn, #elif CFG_TUSB_MCU == OPT_MCU_STM32U5 USB_IRQn, + #elif CFG_TUSB_MCU == OPT_MCU_STM32U0 + USB_DRD_FS_IRQn, #else #error Unknown arch in USB driver #endif diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index 3237a50f6..906538779 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -94,6 +94,13 @@ extern "C" { #define EP_MAX_HS 9 #define EP_FIFO_SIZE_HS 4096 #endif + +#elif CFG_TUSB_MCU == OPT_MCU_STM32U0 + #include "stm32u0xx.h" + #define USB_OTG_FS_PERIPH_BASE USB_OTG_FS_BASE + #define EP_MAX_FS 6 + #define EP_FIFO_SIZE_FS 1280 + #else #error "Unsupported MCUs" #endif diff --git a/src/tusb_option.h b/src/tusb_option.h index fb0209023..690859120 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -91,6 +91,7 @@ #define OPT_MCU_STM32U5 313 ///< ST U5 #define OPT_MCU_STM32L5 314 ///< ST L5 #define OPT_MCU_STM32H5 315 ///< ST H5 +#define OPT_MCU_STM32U0 316 ///< ST U0 // Sony #define OPT_MCU_CXD56 400 ///< SONY CXD56 -- cgit v1.3.1 From 73f7ce7103c0d002d787abfc1ae73d1f9e087f0b Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 4 Oct 2024 17:26:14 +0700 Subject: U0 does not have dwc2 controller --- src/portable/synopsys/dwc2/dwc2_stm32.h | 7 ------- 1 file changed, 7 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index e9f6bdd91..395b6d870 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -94,13 +94,6 @@ extern "C" { #define EP_MAX_HS 9 #define EP_FIFO_SIZE_HS 4096 #endif - -#elif CFG_TUSB_MCU == OPT_MCU_STM32U0 - #include "stm32u0xx.h" - #define USB_OTG_FS_PERIPH_BASE USB_OTG_FS_BASE - #define EP_MAX_FS 6 - #define EP_FIFO_SIZE_FS 1280 - #else #error "Unsupported MCUs" #endif -- cgit v1.3.1 From cb5e273e9a9bde61970101191366b3845007eff9 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 4 Oct 2024 22:12:38 +0700 Subject: enhance dwc2 markdown with field mapping --- src/portable/synopsys/dwc2/dwc2_info.md | 116 +++++++++++++------------- src/portable/synopsys/dwc2/dwc2_info.py | 140 +++++++++++++++++++------------- 2 files changed, 140 insertions(+), 116 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index 462b5856a..cd8a57ec3 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -1,58 +1,58 @@ -| | BCM2711 (Pi4) | EFM32GG FS | ESP32-S2/S3 | ESP32-P4 | STM32F 407/411/429 FS | STM32F 407/429 HS | STM32F 412/767 FS | STM32F723 FS | STM32F723 HS | STM32H743 HS | STM32L476 FS | STM32U5A5 HS | GD32VF103 FS | XMC4500 | -|:---------------------------|:----------------|:-------------|:--------------|:-----------|:------------------------|:--------------------|:--------------------|:---------------|:---------------|:---------------|:---------------|:---------------|:---------------|:-----------| -| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | -| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | -| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | -| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | -| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | -| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | -| - arch | 2 | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 2 | 2 | 0 | 2 | 0 | 2 | -| - point2point | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | -| - hs_phy_type | 1 | 0 | 0 | 3 | 0 | 2 | 0 | 0 | 3 | 2 | 0 | 1 | 0 | 0 | -| - fs_phy_type | 1 | 1 | 1 | 3 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 5 | 8 | 0 | 6 | -| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 11 | 15 | 0 | 13 | -| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nptx_q_depth | 2 | 2 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - ptx_q_depth | 2 | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | -| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | -| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | -| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | -| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | -| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | -| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | -| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 952 | 512 | 952 | 0 | 634 | -| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | -| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - phy_data_width | 0 | 2 | 2 | 2 | 2 | 0 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 2 | -| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 5 | 8 | 0 | 6 | -| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | -| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | +| | BCM2711 (Pi4) | EFM32GG FS | ESP32-S2/S3 | ESP32-P4 | ST F407/411/429 FS | ST F407/429 HS | ST F412/767 FS | ST F723 FS | ST F723 HS | ST F769 | ST H743 HS | ST L476 FS | ST U5A5 HS | GD32VF103 FS | XMC4500 | +|:---------------------------|:----------------|:-------------|:--------------|:-------------|:---------------------|:-----------------|:-----------------|:-------------|:-------------|:-------------|:-------------|:-------------|:-------------|:---------------|:-------------| +| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | +| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | +| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | +| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | +| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | +| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | DMA internal | +| - p2p (hub support) | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | +| - hs_phy_type | UTMI+ | N/A | N/A | UTMI+/ULPI | N/A | ULPI | N/A | N/A | UTMI+/ULPI | ULPI | ULPI | N/A | UTMI+ | N/A | N/A | +| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | N/A | N/A | Dedicated | +| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | +| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 0 | 13 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nptx_q_depth | 2 | 2 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - ptx_q_depth | 2 | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | +| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | +| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | +| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | +| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 0 | 634 | +| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | +| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | +| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | +| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | +| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 33997ca19..62437cfde 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -1,24 +1,27 @@ #!/usr/bin/env python3 -import click + import ctypes +import argparse +import click import pandas as pd # hex value for register: guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4 # Note: FS is FullSpeed, HS is HighSpeed -dwc2_reg_list = ['guid', 'gsnpsid', 'ghwcfg1', 'ghwcfg2', 'ghwcfg3', 'ghwcfg4'] +dwc2_reg_list = ['GUID', 'GSNPSID', 'GHWCFG1', 'GHWCFG2', 'GHWCFG3', 'GHWCFG4'] dwc2_reg_value = { 'BCM2711 (Pi4)': [0x2708A000, 0x4F54280A, 0, 0x228DDD50, 0xFF000E8, 0x1FF00020], 'EFM32GG FS': [0, 0x4F54330A, 0, 0x228F5910, 0x1F204E8, 0x1BF08030], 'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0xC804B5, 0xD3F0A030], 'ESP32-P4': [0, 0x4F54400A, 0, 0x215FFFD0, 0x03805EB5, 0xDFF1A030], - 'STM32F 407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030], - 'STM32F 407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030], - 'STM32F 412/767 FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], - 'STM32F723 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], - 'STM32F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x3EED2E8, 0x23F00030], - 'STM32H743 HS': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x3B8D2E8, 0xE3F00030], # both HS cores - 'STM32L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], - 'STM32U5A5 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30], + 'ST F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030], + 'ST F407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030], + 'ST F412/767 FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], + 'ST F723 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], + 'ST F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x3EED2E8, 0x23F00030], + 'ST F769': [0x2100, 0x4F54320A, 0, 0x229FE190, 0x03EED2E8, 0x23F00030], + 'ST H743 HS': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x3B8D2E8, 0xE3F00030], # both HS cores + 'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], + 'ST U5A5 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30], 'GD32VF103 FS': [0x1000, 0, 0, 0, 0, 0], 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x27A01E5, 0xDBF08030] } @@ -26,12 +29,12 @@ dwc2_reg_value = { # Combine dwc2_info with dwc2_reg_list # dwc2_info = { # 'BCM2711 (Pi4)': { -# 'guid': 0x2708A000, -# 'gsnpsid': 0x4F54280A, -# 'ghwcfg1': 0, -# 'ghwcfg2': 0x228DDD50, -# 'ghwcfg3': 0xFF000E8, -# 'ghwcfg4': 0x1FF00020 +# 'GUID': 0x2708A000, +# 'GSNPSID': 0x4F54280A, +# 'GHWCFG1': 0, +# 'GHWCFG2': 0x228DDD50, +# 'GHWCFG3': 0xFF000E8, +# 'GHWCFG4': 0x1FF00020 # }, dwc2_info = {key: {field: value for field, value in zip(dwc2_reg_list, values)} for key, values in dwc2_reg_value.items()} @@ -40,7 +43,7 @@ class GHWCFG2(ctypes.LittleEndianStructure): _fields_ = [ ("op_mode", ctypes.c_uint32, 3), ("arch", ctypes.c_uint32, 2), - ("point2point", ctypes.c_uint32, 1), + ("p2p (hub support)", ctypes.c_uint32, 1), ("hs_phy_type", ctypes.c_uint32, 2), ("fs_phy_type", ctypes.c_uint32, 2), ("num_dev_ep", ctypes.c_uint32, 4), @@ -99,63 +102,84 @@ class GHWCFG4(ctypes.LittleEndianStructure): ("dma_desc_dynamic", ctypes.c_uint32, 1) ] +# mapping for specific fields in GHWCFG2 +GHWCFG2_field = { + 'op_mode': { + 0: "HNP SRP", + 1: "SRP", + 2: "noHNP noSRP", + 3: "SRP Device", + 4: "noOTG Device", + 5: "SRP Host", + 6: "noOTG Host" + }, + 'arch': { + 0: "Slave only", + 1: "DMA external", + 2: "DMA internal" + }, + 'hs_phy_type': { + 0: "N/A", + 1: "UTMI+", + 2: "ULPI", + 3: "UTMI+/ULPI" + }, + 'fs_phy_type': { + 0: "N/A", + 1: "Dedicated", + 2: "Shared UTMI+", + 3: "Shared ULPI" + } +} -@click.group() -def cli(): - pass - - -@cli.command() -@click.argument('mcus', nargs=-1) -@click.option('-a', '--all', is_flag=True, help='Print all bit-field values') -def info(mcus, all): - """Print DWC2 register values for given MCU(s)""" - if len(mcus) == 0: - mcus = dwc2_info - - for mcu in mcus: - for entry in dwc2_info: - if mcu.lower() in entry.lower(): - print(f"## {entry}") - for r_name, r_value in dwc2_info[entry].items(): - print(f"{r_name} = 0x{r_value:08X}") - # Print bit-field values - if all and r_name.upper() in globals(): - class_name = globals()[r_name.upper()] - ghwcfg = class_name.from_buffer_copy(r_value.to_bytes(4, byteorder='little')) - for field_name, field_type, _ in class_name._fields_: - print(f" {field_name} = {getattr(ghwcfg, field_name)}") +# mapping for specific fields in GHWCFG4 +GHWCFG4_field = { + 'phy_data_width': { + 0: "8 bit", + 1: "16 bit", + 2: "8/16 bit", + 3: "Reserved" + }, + } + +def main(): + """Render dwc2_info to Markdown table""" + parser = argparse.ArgumentParser() + args = parser.parse_args() -@cli.command() -def render_md(): - """Render dwc2_info to Markdown table""" # Create an empty list to hold the dictionaries - dwc2_info_list = [] + md_table = [] # Iterate over the dwc2_info dictionary and extract fields for device, reg_values in dwc2_info.items(): - entry_dict = {"Device": device} + md_item = {"Device": device} for r_name, r_value in reg_values.items(): - entry_dict[r_name] = f"0x{r_value:08X}" + md_item[r_name] = f"0x{r_value:08X}" - if r_name == 'gsnpsid': + if r_name == 'GSNPSID': # Get dwc2 specs version major = ((r_value >> 8) >> 4) & 0x0F minor = (r_value >> 4) & 0xFF patch = chr((r_value & 0x0F) + ord('a') - 0xA) - entry_dict[f' - specs version'] = f"{major:X}.{minor:02X}{patch}" - elif r_name.upper() in globals(): + md_item[f' - specs version'] = f"{major:X}.{minor:02X}{patch}" + elif r_name in globals(): # Get bit-field values which exist as ctypes structures - class_name = globals()[r_name.upper()] - ghwcfg = class_name.from_buffer_copy(r_value.to_bytes(4, byteorder='little')) - for field_name, field_type, _ in class_name._fields_: - entry_dict[f' - {field_name}'] = getattr(ghwcfg, field_name) + class_hdl = globals()[r_name] + ghwcfg = class_hdl.from_buffer_copy(r_value.to_bytes(4, byteorder='little')) + for field_name, field_type, _ in class_hdl._fields_: + field_value = getattr(ghwcfg, field_name) + if class_hdl == GHWCFG2 and field_name in GHWCFG2_field: + field_value = GHWCFG2_field[field_name].get(field_value, f"Unknown ({field_value})") + if class_hdl == GHWCFG4 and field_name in GHWCFG4_field: + field_value = GHWCFG4_field[field_name].get(field_value, f"Unknown ({field_value})") + + md_item[f' - {field_name}'] = field_value - dwc2_info_list.append(entry_dict) + md_table.append(md_item) # Create a Pandas DataFrame from the list of dictionaries - df = pd.DataFrame(dwc2_info_list).set_index('Device') + df = pd.DataFrame(md_table).set_index('Device') # Transpose the DataFrame to switch rows and columns df = df.T @@ -168,4 +192,4 @@ def render_md(): if __name__ == '__main__': - cli() + main() -- cgit v1.3.1 From b2a98eadabf3b48f3d9316b32444f0b9cfbc2d1f Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 4 Oct 2024 22:21:08 +0700 Subject: add stm32f769disco to hil pool --- src/portable/synopsys/dwc2/dcd_dwc2.c | 2 +- test/hil/tinyusb.json | 36 ++++++++++++++++++++++------------- 2 files changed, 24 insertions(+), 14 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 4fa869241..210ce1bba 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -637,7 +637,7 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { static bool check_dwc2(dwc2_regs_t* dwc2) { #if CFG_TUSB_DEBUG >= DWC2_DEBUG // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4 - // Run 'dwc2_info.py render-md' and check dwc2_info.md for bit-field value and comparison with other ports + // Run 'python dwc2_info.py' and check dwc2_info.md for bit-field value and comparison with other ports volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid; TU_LOG1("guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n"); for (size_t i = 0; i < 5; i++) { diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json index 1eaa08207..2358c3c4f 100644 --- a/test/hil/tinyusb.json +++ b/test/hil/tinyusb.json @@ -1,5 +1,18 @@ { "boards": [ + { + "name": "espressif_s3_devkitm", + "uid": "84F703C084E4", + "build" : { + "flags_on": ["", "CFG_TUD_DWC2_DMA"] + }, + "tests": { + "only": ["device/cdc_msc_freertos", "device/hid_composite_freertos"] + }, + "flasher": "esptool", + "flasher_sn": "3ea619acd1cdeb11a0a0b806e93fd3f1", + "flasher_args": "-b 1500000" + }, { "name": "feather_nrf52840_express", "uid": "1F0479CD0F764471", @@ -69,25 +82,22 @@ "flasher_sn": "779541626", "flasher_args": "-device stm32f072rb" }, + { + "name": "stm32f769disco", + "uid": "21002F000F51363531383437", + "build" : { + "flags_on": ["", "CFG_TUD_DWC2_DMA"] + }, + "flasher": "jlink", + "flasher_sn": "000778170924", + "flasher_args": "-device stm32f769ni" + }, { "name": "stm32g0b1nucleo", "uid": "4D0038000450434E37343120", "flasher": "openocd", "flasher_sn": "066FFF495087534867063844", "flasher_args": "-f interface/stlink.cfg -f target/stm32g0x.cfg" - }, - { - "name": "espressif_s3_devkitm", - "uid": "84F703C084E4", - "build" : { - "flags_on": ["", "CFG_TUD_DWC2_DMA"] - }, - "tests": { - "only": ["device/cdc_msc_freertos", "device/hid_composite_freertos"] - }, - "flasher": "esptool", - "flasher_sn": "3ea619acd1cdeb11a0a0b806e93fd3f1", - "flasher_args": "-b 921600" } ], "boards-skip": [ -- cgit v1.3.1 From 599bb0c8227f659b15302dac6a04706c7d3b2a4e Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 4 Oct 2024 22:26:40 +0700 Subject: improving dwc2, merging diep and doep if possible --- .idea/cmake.xml | 62 +++--- hw/bsp/stm32h7/boards/stm32h743eval/board.cmake | 1 + hw/bsp/stm32l4/boards/stm32l476disco/board.cmake | 2 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 230 ++++++++++++----------- src/portable/synopsys/dwc2/dwc2_info.md | 6 +- src/portable/synopsys/dwc2/dwc2_info.py | 6 +- src/portable/synopsys/dwc2/dwc2_type.h | 108 +++++++++-- 7 files changed, 246 insertions(+), 169 deletions(-) (limited to 'src/portable') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index 37cd73c65..d4ad3a748 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -9,49 +9,49 @@ - + - + - + - + - + - + - + @@ -65,19 +65,15 @@ - - - - - - - + + + @@ -86,33 +82,22 @@ - - - - - - - - - - - - - - + + + - + - + @@ -124,22 +109,31 @@ - + + + + + - - + + + + + + + + - diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake index a28aa87bd..6d7a97741 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake @@ -1,5 +1,6 @@ set(MCU_VARIANT stm32h743xx) set(JLINK_DEVICE stm32h743xi) +# set(JLINK_OPTION "-USB jtrace") set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld) diff --git a/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake b/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake index 4ade0a5c9..fd1c931c2 100644 --- a/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake +++ b/hw/bsp/stm32l4/boards/stm32l476disco/board.cmake @@ -1,6 +1,6 @@ set(MCU_VARIANT stm32l476xx) set(JLINK_DEVICE stm32l476vg) - +# set(JLINK_OPTION "-USB 000777632258") set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32L476VGTx_FLASH.ld) function(update_board TARGET) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 210ce1bba..99cf3fdaa 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -327,53 +327,49 @@ static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoin xfer->interval = p_endpoint_desc->bInterval; // USBAEP, EPTYP, SD0PID_SEVNFRM, MPSIZ are the same for IN and OUT endpoints. - uint32_t const dxepctl = (1 << DOEPCTL_USBAEP_Pos) | - (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) | - (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << DOEPCTL_MPSIZ_Pos); - - if (dir == TUSB_DIR_OUT) { - dwc2->epout[epnum].doepctl = dxepctl; - dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum); - } else { - dwc2->epin[epnum].diepctl = dxepctl | (epnum << DIEPCTL_TXFNUM_Pos); - dwc2->daintmsk |= TU_BIT(DAINTMSK_IEPM_Pos + epnum); + uint32_t epctl = (1 << DOEPCTL_USBAEP_Pos) | + (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) | + (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | + (xfer->max_size << DOEPCTL_MPSIZ_Pos); + if (dir == TUSB_DIR_IN) { + epctl |= (epnum << DIEPCTL_TXFNUM_Pos); } + + dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum]; + dep->ctl = epctl; + dwc2->daintmsk |= TU_BIT(epnum + DAINT_SHIFT(dir)); } static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { (void) rhport; dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + const uint8_t epnum = tu_edpt_number(ep_addr); + const uint8_t dir = tu_edpt_dir(ep_addr); + dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum]; if (dir == TUSB_DIR_IN) { - dwc2_epin_t* epin = dwc2->epin; - // Only disable currently enabled non-control endpoint - if ((epnum == 0) || !(epin[epnum].diepctl & DIEPCTL_EPENA)) { - epin[epnum].diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0); + if ((epnum == 0) || !(dep->diepctl & DIEPCTL_EPENA)) { + dep->diepctl |= DIEPCTL_SNAK | (stall ? DIEPCTL_STALL : 0); } else { // Stop transmitting packets and NAK IN xfers. - epin[epnum].diepctl |= DIEPCTL_SNAK; - while ((epin[epnum].diepint & DIEPINT_INEPNE) == 0) {} + dep->diepctl |= DIEPCTL_SNAK; + while ((dep->diepint & DIEPINT_INEPNE) == 0) {} // Disable the endpoint. - epin[epnum].diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0); - while ((epin[epnum].diepint & DIEPINT_EPDISD_Msk) == 0) {} + dep->diepctl |= DIEPCTL_EPDIS | (stall ? DIEPCTL_STALL : 0); + while ((dep->diepint & DIEPINT_EPDISD_Msk) == 0) {} - epin[epnum].diepint = DIEPINT_EPDISD; + dep->diepint = DIEPINT_EPDISD; } // Flush the FIFO, and wait until we have confirmed it cleared. dfifo_flush_tx(dwc2, epnum); } else { - dwc2_epout_t* epout = dwc2->epout; - // Only disable currently enabled non-control endpoint - if ((epnum == 0) || !(epout[epnum].doepctl & DOEPCTL_EPENA)) { - epout[epnum].doepctl |= stall ? DOEPCTL_STALL : 0; + if ((epnum == 0) || !(dep->doepctl & DOEPCTL_EPENA)) { + dep->doepctl |= stall ? DOEPCTL_STALL : 0; } else { // Asserting GONAK is required to STALL an OUT endpoint. // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt @@ -382,11 +378,11 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { dwc2->dctl |= DCTL_SGONAK; while ((dwc2->gintsts & GINTSTS_BOUTNAKEFF_Msk) == 0) {} - // Ditto here- disable the endpoint. - epout[epnum].doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); - while ((epout[epnum].doepint & DOEPINT_EPDISD_Msk) == 0) {} + // Ditto here disable the endpoint. + dep->doepctl |= DOEPCTL_EPDIS | (stall ? DOEPCTL_STALL : 0); + while ((dep->doepint & DOEPINT_EPDISD_Msk) == 0) {} - epout[epnum].doepint = DOEPINT_EPDISD; + dep->doepint = DOEPINT_EPDISD; // Allow other OUT endpoints to keep receiving. dwc2->dctl |= DCTL_CGONAK; @@ -430,7 +426,7 @@ static void bus_reset(uint8_t rhport) { dfifo_init(rhport); - // Fixed control EP0 size to 64 bytes + // Fixed both control EP0 size to 64 bytes dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos); dwc2->epout[0].doepctl &= ~(0x03 << DOEPCTL_MPSIZ_Pos); @@ -461,33 +457,33 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c } // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here. - if (dir == TUSB_DIR_IN) { - dwc2_epin_t* epin = dwc2->epin; + const uint8_t is_epout = 1 - dir; + dwc2_dep_t* dep = &dwc2->ep[is_epout][epnum]; + if (dir == TUSB_DIR_IN) { // A full IN transfer (multiple packets, possibly) triggers XFRC. - epin[epnum].dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | + dep->dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); if(dma_enabled(dwc2)) { - epin[epnum].diepdma = (uintptr_t)xfer->buffer; + dep->diepdma = (uintptr_t)xfer->buffer; // For ISO endpoint set correct odd/even bit for next frame. - if ((epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { + if ((dep->diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { // Take odd/even bit from frame counter. uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); - epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); + dep->diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); } - epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; + dep->diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; } else { - - epin[epnum].diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; + dep->diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; // For ISO endpoint set correct odd/even bit for next frame. - if ((epin[epnum].diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { + if ((dep->diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { // Take odd/even bit from frame counter. uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); - epin[epnum].diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); + dep->diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); } // Enable fifo empty interrupt only if there are something to put in the fifo. if (total_bytes != 0) { @@ -495,25 +491,23 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c } } } else { - dwc2_epout_t* epout = dwc2->epout; - // A full OUT transfer (multiple packets, possibly) triggers XFRC. - epout[epnum].doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ); - epout[epnum].doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) | + dep->doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ); + dep->doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) | ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk); - if ((epout[epnum].doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && + if ((dep->doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && XFER_CTL_BASE(epnum, dir)->interval == 1) { // Take odd/even bit from frame counter. uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); - epout[epnum].doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); + dep->doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); } if(dma_enabled(dwc2)) { - epout[epnum].doepdma = (uintptr_t)xfer->buffer; + dep->doepdma = (uintptr_t)xfer->buffer; } - epout[epnum].doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK; + dep->doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK; } } @@ -837,17 +831,13 @@ void dcd_edpt_close_all(uint8_t rhport) { dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); for (uint8_t n = 1; n < ep_count; n++) { - // disable OUT endpoint - if (dwc2->epout[n].doepctl & DOEPCTL_EPENA) { - dwc2->epout[n].doepctl |= DOEPCTL_SNAK | DOEPCTL_EPDIS; - } - xfer_status[n][TUSB_DIR_OUT].max_size = 0; - - // disable IN endpoint - if (dwc2->epin[n].diepctl & DIEPCTL_EPENA) { - dwc2->epin[n].diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS; + for (uint8_t d = 0; d < 2; d++) { + dwc2_dep_t* dep = &dwc2->ep[d][n]; + if (dep->ctl & EPCTL_EPENA) { + dep->ctl |= EPCTL_SNAK | EPCTL_EPDIS; + } + xfer_status[n][1-d].max_size = 0; } - xfer_status[n][TUSB_DIR_IN].max_size = 0; } dfifo_flush_tx(dwc2, 0x10); // all tx fifo @@ -937,21 +927,14 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { } void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - (void) rhport; - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); + dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum]; // Clear stall and reset data toggle - if (dir == TUSB_DIR_IN) { - dwc2->epin[epnum].diepctl &= ~DIEPCTL_STALL; - dwc2->epin[epnum].diepctl |= DIEPCTL_SD0PID_SEVNFRM; - } else { - dwc2->epout[epnum].doepctl &= ~DOEPCTL_STALL; - dwc2->epout[epnum].doepctl |= DOEPCTL_SD0PID_SEVNFRM; - } + dep->ctl &= ~EPCTL_STALL;; + dep->ctl |= EPCTL_SD0PID_SEVNFRM; } //-------------------------------------------------------------------- @@ -963,10 +946,10 @@ static void handle_rxflvl_irq(uint8_t rhport) { volatile uint32_t const* rx_fifo = dwc2->fifo[0]; // Pop control word off FIFO - uint32_t const ctl_word = dwc2->grxstsp; - uint8_t const pktsts = (ctl_word & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; - uint8_t const epnum = (ctl_word & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; - uint16_t const bcnt = (ctl_word & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; + uint32_t const grxstsp = dwc2->grxstsp; + uint8_t const pktsts = (grxstsp & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; + uint8_t const epnum = (grxstsp & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; + uint16_t const bcnt = (grxstsp & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; dwc2_epout_t* epout = &dwc2->epout[epnum]; @@ -1024,20 +1007,16 @@ static void handle_rxflvl_irq(uint8_t rhport) { ep0_pending[TUSB_DIR_OUT] = 0; } } - } break; + } - // Out packet done (Interrupt) case GRXSTS_PKTSTS_OUTDONE: - // Occurred on STM32L47 with dwc2 version 3.10a but not found on other version like 2.80a or 3.30a - // May (or not) be 3.10a specific feature/bug or depending on MCU configuration - // XFRC complete is additionally generated when - // - setup packet is received - // - complete the data stage of control write is complete - // It will be handled in handle_epout_irq() + /* Out packet done (Interrupt) + After this entry is popped from the receive FIFO, the controller asserts a Transfer Completed interrupt on + the specified OUT endpoint which will be handled by handle_epout_irq() */ break; - default: // Invalid + default: TU_BREAKPOINT(); break; } @@ -1049,73 +1028,73 @@ static void handle_epout_irq(uint8_t rhport) { // DAINT for a given EP clears when DOEPINTx is cleared. // OEPINT will be cleared when DAINT's out bits are cleared. - for (uint8_t n = 0; n < ep_count; n++) { - if (dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + n)) { - dwc2_epout_t* epout = &dwc2->epout[n]; - - uint32_t const doepint = epout->doepint; - + for (uint8_t epnum = 0; epnum < ep_count; epnum++) { + if (dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + epnum)) { + dwc2_epout_t* epout = &dwc2->epout[epnum]; + const uint32_t doepint = epout->doepint; TU_ASSERT((epout->doepint & DOEPINT_AHBERR) == 0, ); // OUT XFER complete - if (epout->doepint & DOEPINT_XFRC) { + if (doepint & DOEPINT_XFRC) { epout->doepint = DOEPINT_XFRC; - xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT); + xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); if(dma_enabled(dwc2)) { - if (doepint & DOEPINT_STUP) { + if (doepint & DOEPINT_SETUP) { // STPKTRX is only available for version from 3_00a - if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { - epout->doepint = DOEPINT_STPKTRX; + if ((doepint & DOEPINT_DMA_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { + epout->doepint = DOEPINT_DMA_STPKTRX; } - } else if (doepint & DOEPINT_OTEPSPR) { - epout->doepint = DOEPINT_OTEPSPR; + } else if (doepint & DOEPINT_STSPHSRX) { + epout->doepint = DOEPINT_STSPHSRX; } else { - if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { - epout->doepint = DOEPINT_STPKTRX; + if ((doepint & DOEPINT_DMA_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { + epout->doepint = DOEPINT_DMA_STPKTRX; } else { // EP0 can only handle one packet - if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) { + if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { // Schedule another packet to be received. - edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); } else { // Fix packet length uint16_t remain = (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; xfer->total_len -= remain; // this is ZLP, so prepare EP0 for next setup - if(n == 0 && xfer->total_len == 0) { + if(epnum == 0 && xfer->total_len == 0) { dma_setup_prepare(rhport); } - dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); + dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); } } } } else { - if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid == DWC2_CORE_REV_3_10a)) { - epout->doepint = DOEPINT_STPKTRX; + // DMA_STPKTRX should only be set in Buffer DMA Mode. However, STM32L476 (slave-only) with v3.10a + // incorrectly set this along with SETUP bit. This may (or not) be STM32L476 or 3.10a specific bug + if ((doepint & DOEPINT_DMA_STPKTRX) && (dwc2->gsnpsid == DWC2_CORE_REV_3_10a)) { + epout->doepint = DOEPINT_DMA_STPKTRX; } else { - if ((doepint & DOEPINT_OTEPSPR) && (dwc2->gsnpsid == DWC2_CORE_REV_3_10a)) { - epout->doepint = DOEPINT_OTEPSPR; + if ((doepint & DOEPINT_STSPHSRX) && (dwc2->gsnpsid == DWC2_CORE_REV_3_10a)) { + epout->doepint = DOEPINT_STSPHSRX; } // EP0 can only handle one packet - if ((n == 0) && ep0_pending[TUSB_DIR_OUT]) { + if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { // Schedule another packet to be received. - edpt_schedule_packets(rhport, n, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); } else { - dcd_event_xfer_complete(rhport, n, xfer->total_len, XFER_RESULT_SUCCESS, true); + dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); } } } } // SETUP packet Setup Phase done. - if (doepint & DOEPINT_STUP) { - epout->doepint = DOEPINT_STUP; - if ((doepint & DOEPINT_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { - epout->doepint = DOEPINT_STPKTRX; + if (doepint & DOEPINT_SETUP) { + epout->doepint = DOEPINT_SETUP; + if ((doepint & DOEPINT_DMA_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { + epout->doepint = DOEPINT_DMA_STPKTRX; } if(dma_enabled(dwc2) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { dma_setup_prepare(rhport); @@ -1195,6 +1174,29 @@ static void handle_epin_irq(uint8_t rhport) { } } +/* Interrupt Hierarchy + + DxEPMSK.XferComplMsk DxEPINTn.XferCompl + | | + +---------- AND --------+ + | + DAINT.xEPnInt DAINTMSK.xEPnMsk + | | + +---------- AND --------+ + | + GINTSTS.xEPInt GINTMSK.xEPIntMsk + | | + +---------- AND --------+ + | + GAHBCFG.GblIntrMsk + | + IRQn + + Note: when OTG_MULTI_PROC_INTRPT = 1, Device Each endpoint interrupt deachint/deachmsk/diepeachmsk/doepeachmsk + are combined to generate dedicated interrupt line for each endpoint. + */ + + void dcd_int_handler(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); @@ -1276,8 +1278,8 @@ void dcd_int_handler(uint8_t rhport) { // Mask out RXFLVL while reading data from FIFO dwc2->gintmsk &= ~GINTMSK_RXFLVLM; - // Loop until all available packets were handled do { + // Loop until all available packets were handled handle_rxflvl_irq(rhport); } while(dwc2->gintsts & GINTSTS_RXFLVL); diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index cd8a57ec3..5c7e5e688 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -8,13 +8,13 @@ | - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | | - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | DMA internal | | - p2p (hub support) | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | -| - hs_phy_type | UTMI+ | N/A | N/A | UTMI+/ULPI | N/A | ULPI | N/A | N/A | UTMI+/ULPI | ULPI | ULPI | N/A | UTMI+ | N/A | N/A | -| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | N/A | N/A | Dedicated | +| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | +| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | n/a | Dedicated | | - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | | - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 0 | 13 | | - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | | - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | | - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | - nptx_q_depth | 2 | 2 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | | - ptx_q_depth | 2 | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 62437cfde..ac32eb585 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -50,7 +50,7 @@ class GHWCFG2(ctypes.LittleEndianStructure): ("num_host_ch", ctypes.c_uint32, 4), ("period_channel_support", ctypes.c_uint32, 1), ("enable_dynamic_fifo", ctypes.c_uint32, 1), - ("mul_cpu_int", ctypes.c_uint32, 1), + ("mul_proc_intrpt", ctypes.c_uint32, 1), ("reserved21", ctypes.c_uint32, 1), ("nptx_q_depth", ctypes.c_uint32, 2), ("ptx_q_depth", ctypes.c_uint32, 2), @@ -119,13 +119,13 @@ GHWCFG2_field = { 2: "DMA internal" }, 'hs_phy_type': { - 0: "N/A", + 0: "n/a", 1: "UTMI+", 2: "ULPI", 3: "UTMI+/ULPI" }, 'fs_phy_type': { - 0: "N/A", + 0: "n/a", 1: "Dedicated", 2: "Shared UTMI+", 3: "Shared ULPI" diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index ac88dd24d..d5a51fb09 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -250,7 +250,7 @@ typedef struct TU_ATTR_PACKED { uint32_t num_host_ch : 4; // 14..17 Number of host channel (excluding control) uint32_t period_channel_support : 1; // 18 Support Periodic OUT Host Channel uint32_t enable_dynamic_fifo : 1; // 19 Dynamic FIFO Sizing Enabled - uint32_t mul_cpu_int : 1; // 20 Multi-Processor Interrupt Enabled + uint32_t mul_proc_intrpt : 1; // 20 Multi-Processor Interrupt enabled (OTG_MULTI_PROC_INTRPT) uint32_t reserved21 : 1; // 21 reserved uint32_t nptx_q_depth : 2; // 22..23 Non-periodic request queue depth: 0 = 2. 1 = 4, 2 = 8 uint32_t ptx_q_depth : 2; // 24..25 Host periodic request queue depth: 0 = 2. 1 = 4, 2 = 8 @@ -336,6 +336,32 @@ typedef struct { uint32_t reserved18[2]; // B18..B1C } dwc2_epout_t; +typedef struct { + union { + volatile uint32_t diepctl; + volatile uint32_t doepctl; + volatile uint32_t ctl; + }; + uint32_t rsv04; + union { + volatile uint32_t diepint; + volatile uint32_t doepint; + }; + uint32_t rsv0c; + union { + volatile uint32_t dieptsiz; + volatile uint32_t doeptsiz; + }; + union { + volatile uint32_t diepdma; + volatile uint32_t doepdma; + }; + volatile uint32_t dtxfsts; + uint32_t rsv1c; +}dwc2_dep_t; + +TU_VERIFY_STATIC(sizeof(dwc2_dep_t) == 0x20, "incorrect size"); + //-------------------------------------------------------------------- // CSR Register Map //-------------------------------------------------------------------- @@ -418,16 +444,24 @@ typedef struct { volatile uint32_t dvbuspulse; // 82C Device VBUS Pulsing Time volatile uint32_t dthrctl; // 830 Device threshold Control volatile uint32_t diepempmsk; // 834 Device IN Endpoint FIFO Empty Interrupt Mask + + // Device Each Endpoint (IN/OUT) Interrupt/Mask for generating dedicated EP interrupt line + // require OTG_MULTI_PROC_INTRPT=1 volatile uint32_t deachint; // 838 Device Each Endpoint Interrupt - volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt msk + volatile uint32_t deachmsk; // 83C Device Each Endpoint Interrupt mask volatile uint32_t diepeachmsk[16]; // 840..87C Device Each IN Endpoint mask volatile uint32_t doepeachmsk[16]; // 880..8BF Device Each OUT Endpoint mask uint32_t reserved8c0[16]; // 8C0..8FF //------------- Device Endpoint -------------// - dwc2_epin_t epin[16]; // 900..AFF IN Endpoints - dwc2_epout_t epout[16]; // B00..CFF OUT Endpoints - uint32_t reservedd00[64]; // D00..DFF + union { + dwc2_dep_t ep[2][16]; // 0: IN, 1 OUT + struct { + dwc2_epin_t epin[16]; // 900..AFF IN Endpoints + dwc2_epout_t epout[16]; // B00..CFF OUT Endpoints + }; + }; + uint32_t reservedd00[64]; // D00..DFF //------------- Power Clock -------------// volatile uint32_t pcgctl; // E00 Power and Clock Gating Control @@ -1094,6 +1128,8 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DAINTMSK_OEPM_Msk (0xFFFFUL << DAINTMSK_OEPM_Pos) // 0xFFFF0000 #define DAINTMSK_OEPM DAINTMSK_OEPM_Msk // OUT EP interrupt mask bits +#define DAINT_SHIFT(_dir) ((_dir == TUSB_DIR_IN) ? 0 : 16) + #if 0 /******************** Bit definition for OTG register ********************/ #define CHNUM_Pos (0U) @@ -1803,6 +1839,45 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DIEPTXF_INEPTXFD_Msk (0xFFFFUL << DIEPTXF_INEPTXFD_Pos) // 0xFFFF0000 #define DIEPTXF_INEPTXFD DIEPTXF_INEPTXFD_Msk // IN endpoint TxFIFO depth + +/******************** Bit definition for Common EPCTL register ********************/ +#define EPCTL_MPSIZ_Pos (0U) +#define EPCTL_MPSIZ_Msk (0x7FFUL << EPCTL_MPSIZ_Pos) // 0x000007FF +#define EPCTL_MPSIZ EPCTL_MPSIZ_Msk // Maximum packet size //Bit 1 +#define EPCTL_USBAEP_Pos (15U) +#define EPCTL_USBAEP_Msk (0x1UL << EPCTL_USBAEP_Pos) // 0x00008000 +#define EPCTL_USBAEP EPCTL_USBAEP_Msk // USB active endpoint +#define EPCTL_NAKSTS_Pos (17U) +#define EPCTL_NAKSTS_Msk (0x1UL << EPCTL_NAKSTS_Pos) // 0x00020000 +#define EPCTL_NAKSTS EPCTL_NAKSTS_Msk // NAK status +#define EPCTL_EPTYP_Pos (18U) +#define EPCTL_EPTYP_Msk (0x3UL << EPCTL_EPTYP_Pos) // 0x000C0000 +#define EPCTL_EPTYP EPCTL_EPTYP_Msk // Endpoint type +#define EPCTL_EPTYP_0 (0x1UL << EPCTL_EPTYP_Pos) // 0x00040000 +#define EPCTL_EPTYP_1 (0x2UL << EPCTL_EPTYP_Pos) // 0x00080000 +#define EPCTL_SNPM EPCTL_SNPM_Msk // Snoop mode +#define EPCTL_STALL_Pos (21U) +#define EPCTL_STALL_Msk (0x1UL << EPCTL_STALL_Pos) // 0x00200000 +#define EPCTL_STALL EPCTL_STALL_Msk // STALL handshake +#define EPCTL_CNAK_Pos (26U) +#define EPCTL_CNAK_Msk (0x1UL << EPCTL_CNAK_Pos) // 0x04000000 +#define EPCTL_CNAK EPCTL_CNAK_Msk // Clear NAK +#define EPCTL_SNAK_Pos (27U) +#define EPCTL_SNAK_Msk (0x1UL << EPCTL_SNAK_Pos) // 0x08000000 +#define EPCTL_SNAK EPCTL_SNAK_Msk // Set NAK +#define EPCTL_SD0PID_SEVNFRM_Pos (28U) +#define EPCTL_SD0PID_SEVNFRM_Msk (0x1UL << EPCTL_SD0PID_SEVNFRM_Pos) // 0x10000000 +#define EPCTL_SD0PID_SEVNFRM EPCTL_SD0PID_SEVNFRM_Msk // Set DATA0 PID +#define EPCTL_SODDFRM_Pos (29U) +#define EPCTL_SODDFRM_Msk (0x1UL << EPCTL_SODDFRM_Pos) // 0x20000000 +#define EPCTL_SODDFRM EPCTL_SODDFRM_Msk // Set odd frame +#define EPCTL_EPDIS_Pos (30U) +#define EPCTL_EPDIS_Msk (0x1UL << EPCTL_EPDIS_Pos) // 0x40000000 +#define EPCTL_EPDIS EPCTL_EPDIS_Msk // Endpoint disable +#define EPCTL_EPENA_Pos (31U) +#define EPCTL_EPENA_Msk (0x1UL << EPCTL_EPENA_Pos) // 0x80000000 +#define EPCTL_EPENA EPCTL_EPENA_Msk // Endpoint enable + /******************** Bit definition for DOEPCTL register ********************/ #define DOEPCTL_MPSIZ_Pos (0U) #define DOEPCTL_MPSIZ_Msk (0x7FFUL << DOEPCTL_MPSIZ_Pos) // 0x000007FF @@ -1853,15 +1928,19 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DOEPINT_AHBERR_Pos (2U) #define DOEPINT_AHBERR_Msk (0x1UL << DOEPINT_AHBERR_Pos) // 0x00000004 #define DOEPINT_AHBERR DOEPINT_AHBERR_Msk // AHB Error (AHBErr) during an OUT transaction -#define DOEPINT_STUP_Pos (3U) -#define DOEPINT_STUP_Msk (0x1UL << DOEPINT_STUP_Pos) // 0x00000008 -#define DOEPINT_STUP DOEPINT_STUP_Msk // SETUP phase done + +#define DOEPINT_SETUP_Pos (3U) +#define DOEPINT_SETUP_Msk (0x1UL << DOEPINT_SETUP_Pos) // 0x00000008 +#define DOEPINT_SETUP DOEPINT_SETUP_Msk // SETUP phase done + #define DOEPINT_OTEPDIS_Pos (4U) #define DOEPINT_OTEPDIS_Msk (0x1UL << DOEPINT_OTEPDIS_Pos) // 0x00000010 #define DOEPINT_OTEPDIS DOEPINT_OTEPDIS_Msk // OUT token received when endpoint disabled -#define DOEPINT_OTEPSPR_Pos (5U) -#define DOEPINT_OTEPSPR_Msk (0x1UL << DOEPINT_OTEPSPR_Pos) // 0x00000020 -#define DOEPINT_OTEPSPR DOEPINT_OTEPSPR_Msk // Status Phase Received For Control Write + +#define DOEPINT_STSPHSRX_Pos (5U) +#define DOEPINT_STSPHSRX_Msk (0x1UL << DOEPINT_STSPHSRX_Pos) // 0x00000020 +#define DOEPINT_STSPHSRX DOEPINT_STSPHSRX_Msk // Status Phase Received For Control Write + #define DOEPINT_B2BSTUP_Pos (6U) #define DOEPINT_B2BSTUP_Msk (0x1UL << DOEPINT_B2BSTUP_Pos) // 0x00000040 #define DOEPINT_B2BSTUP DOEPINT_B2BSTUP_Msk // Back-to-back SETUP packets received @@ -1874,9 +1953,10 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DOEPINT_NYET_Pos (14U) #define DOEPINT_NYET_Msk (0x1UL << DOEPINT_NYET_Pos) // 0x00004000 #define DOEPINT_NYET DOEPINT_NYET_Msk // NYET interrupt -#define DOEPINT_STPKTRX_Pos (15U) -#define DOEPINT_STPKTRX_Msk (0x1UL << DOEPINT_STPKTRX_Pos) // 0x00008000 -#define DOEPINT_STPKTRX DOEPINT_STPKTRX_Msk // Setup Packet Received + +#define DOEPINT_DMA_STPKTRX_Pos (15U) +#define DOEPINT_DMA_STPKTRX_Msk (0x1UL << DOEPINT_DMA_STPKTRX_Pos) // 0x00008000 +#define DOEPINT_DMA_STPKTRX DOEPINT_DMA_STPKTRX_Msk // Setup Packet Received in Buffer DMA Mode /******************** Bit definition for DOEPTSIZ register ********************/ #define DOEPTSIZ_XFRSIZ_Pos (0U) -- cgit v1.3.1 From 07c14f30a6d6cfb1758e3496c3ea73275ae4a062 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 8 Oct 2024 12:36:45 +0700 Subject: add f407disco to hil pool --- hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake | 16 ++ hw/bsp/stm32h7/boards/stm32h750_weact/board.h | 132 ++++++++++++++++ hw/bsp/stm32h7/boards/stm32h750_weact/board.mk | 21 +++ .../stm32h750_weact/stm32h750xx_flash_CM7.ld | 170 +++++++++++++++++++++ hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake | 2 +- hw/bsp/stm32h7/boards/stm32h750bdk/board.mk | 2 +- hw/bsp/stm32h7/family.c | 12 +- src/portable/synopsys/dwc2/dwc2_info.md | 116 +++++++------- src/portable/synopsys/dwc2/dwc2_info.py | 23 +-- test/hil/hil_test.py | 2 +- test/hil/tinyusb.json | 24 ++- 11 files changed, 438 insertions(+), 82 deletions(-) create mode 100644 hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake create mode 100644 hw/bsp/stm32h7/boards/stm32h750_weact/board.h create mode 100644 hw/bsp/stm32h7/boards/stm32h750_weact/board.mk create mode 100644 hw/bsp/stm32h7/boards/stm32h750_weact/stm32h750xx_flash_CM7.ld (limited to 'src/portable') diff --git a/hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake b/hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake new file mode 100644 index 000000000..6303ca462 --- /dev/null +++ b/hw/bsp/stm32h7/boards/stm32h750_weact/board.cmake @@ -0,0 +1,16 @@ +set(MCU_VARIANT stm32h750xx) +set(JLINK_DEVICE stm32h750vb) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${MCU_VARIANT}_flash_CM7.ld) +set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + STM32H750xx + HSE_VALUE=25000000 + CORE_CM7 + # default to PORT 0 + BOARD_TUD_RHPORT=0 + BOARD_TUD_MAX_SPEED=OPT_MODE_FULL_SPEED + ) +endfunction() diff --git a/hw/bsp/stm32h7/boards/stm32h750_weact/board.h b/hw/bsp/stm32h7/boards/stm32h750_weact/board.h new file mode 100644 index 000000000..d117637a5 --- /dev/null +++ b/hw/bsp/stm32h7/boards/stm32h750_weact/board.h @@ -0,0 +1,132 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021, Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#define LED_PORT GPIOE +#define LED_PIN GPIO_PIN_3 +#define LED_STATE_ON 1 + +// Blue push-button +#define BUTTON_PORT GPIOC +#define BUTTON_PIN GPIO_PIN_13 +#define BUTTON_STATE_ACTIVE 1 + +// UART +//#define UART_DEV USART3 +//#define UART_CLK_EN __HAL_RCC_USART3_CLK_ENABLE +//#define UART_GPIO_PORT GPIOB +//#define UART_GPIO_AF GPIO_AF7_USART3 +//#define UART_TX_PIN GPIO_PIN_10 +//#define UART_RX_PIN GPIO_PIN_11 + +// VBUS Sense detection +#define OTG_FS_VBUS_SENSE 1 +#define OTG_HS_VBUS_SENSE 0 + +//--------------------------------------------------------------------+ +// RCC Clock +//--------------------------------------------------------------------+ +static inline void SystemClock_Config(void) { + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + + // Supply configuration update enable + HAL_PWREx_ConfigSupply(PWR_LDO_SUPPLY); + + // Configure the main internal regulator output voltage + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); + while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {} + + // Configure the PLL clock source + __HAL_RCC_PLL_PLLSOURCE_CONFIG(RCC_PLLSOURCE_HSE); + + // Initializes the CPU, AHB and APB busses clocks + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI|RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.LSIState = RCC_LSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 5; + RCC_OscInitStruct.PLL.PLLN = 96; + RCC_OscInitStruct.PLL.PLLP = 2; + RCC_OscInitStruct.PLL.PLLQ = 2; + RCC_OscInitStruct.PLL.PLLR = 2; + RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1VCIRANGE_2; + RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1VCOWIDE; + RCC_OscInitStruct.PLL.PLLFRACN = 0; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + // Initializes the CPU, AHB and APB busses clocks + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 + |RCC_CLOCKTYPE_D3PCLK1|RCC_CLOCKTYPE_D1PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; + RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV1; + RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV1; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1); + + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC|RCC_PERIPHCLK_SPI4 + |RCC_PERIPHCLK_SPI1|RCC_PERIPHCLK_USB + |RCC_PERIPHCLK_QSPI; + PeriphClkInitStruct.PLL3.PLL3M = 10; + PeriphClkInitStruct.PLL3.PLL3N = 96; + PeriphClkInitStruct.PLL3.PLL3P = 5; + PeriphClkInitStruct.PLL3.PLL3Q = 5; + PeriphClkInitStruct.PLL3.PLL3R = 2; + PeriphClkInitStruct.PLL3.PLL3RGE = RCC_PLL3VCIRANGE_1; + PeriphClkInitStruct.PLL3.PLL3VCOSEL = RCC_PLL3VCOWIDE; + PeriphClkInitStruct.PLL3.PLL3FRACN = 0; + PeriphClkInitStruct.QspiClockSelection = RCC_QSPICLKSOURCE_D1HCLK; + PeriphClkInitStruct.Spi123ClockSelection = RCC_SPI123CLKSOURCE_PLL; + PeriphClkInitStruct.Spi45ClockSelection = RCC_SPI45CLKSOURCE_D2PCLK1; + PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3; + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSI; + HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); + + // Enable USB Voltage detector + HAL_PWREx_EnableUSBVoltageDetector(); +} + +static inline void board_stm32h7_post_init(void) { + // For this board does nothing +} + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/hw/bsp/stm32h7/boards/stm32h750_weact/board.mk b/hw/bsp/stm32h7/boards/stm32h750_weact/board.mk new file mode 100644 index 000000000..a50172cb0 --- /dev/null +++ b/hw/bsp/stm32h7/boards/stm32h750_weact/board.mk @@ -0,0 +1,21 @@ +# STM32H745I-DISCO uses OTG_FS +# FIXME: Reset enumerates, un/replug USB plug does not enumerate + +CFLAGS += -DSTM32H750xx -DCORE_CM7 -DHSE_VALUE=25000000 + +# Default is FulSpeed port +PORT ?= 0 + +# GCC +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32h750xx.s +LD_FILE_GCC = $(BOARD_PATH)/stm32h750xx_flash_CM7.ld + +# IAR +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h750xx.s +LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h750xx_flash.icf + +# For flash-jlink target +JLINK_DEVICE = stm32h750vb + +# flash target using on-board stlink +flash: flash-jlink diff --git a/hw/bsp/stm32h7/boards/stm32h750_weact/stm32h750xx_flash_CM7.ld b/hw/bsp/stm32h7/boards/stm32h750_weact/stm32h750xx_flash_CM7.ld new file mode 100644 index 000000000..30f220a42 --- /dev/null +++ b/hw/bsp/stm32h7/boards/stm32h750_weact/stm32h750xx_flash_CM7.ld @@ -0,0 +1,170 @@ +/* +****************************************************************************** +** + +** File : LinkerScript.ld +** +** +** Abstract : Linker script for STM32H7 series +** 128Kbytes FLASH and 1Mbytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used. +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed ďż˝as is,ďż˝ without any warranty +** of any kind. +** +***************************************************************************** +** @attention +** +** Copyright (c) 2019 STMicroelectronics. +** All rights reserved. +** +** This software component is licensed by ST under BSD 3-Clause license, +** the "License"; You may not use this file except in compliance with the +** License. You may obtain a copy of the License at: +** opensource.org/licenses/BSD-3-Clause +** +**************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = 0x20020000; /* end of RAM */ +/* Generate a link error if heap and stack don't fit into RAM */ +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Specify the memory areas */ +MEMORY +{ +FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 128K +RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 1M +ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K +} + +/* Define output sections */ +SECTIONS +{ + /* The startup code goes first into FLASH */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data goes into FLASH */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data goes into FLASH */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH + .ARM : { + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + } >FLASH + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >FLASH + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + } >FLASH + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >FLASH + + /* used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections goes into RAM, load LMA copy after code */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + } >RAM AT> FLASH + + + /* Uninitialized data section */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough RAM left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + + /* Remove information from the standard libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake b/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake index 6eff708a8..e87be8255 100644 --- a/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake +++ b/hw/bsp/stm32h7/boards/stm32h750bdk/board.cmake @@ -1,5 +1,5 @@ set(MCU_VARIANT stm32h750xx) -set(JLINK_DEVICE stm32h750xb_m7) +set(JLINK_DEVICE stm32h750xb) set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/${MCU_VARIANT}_flash_CM7.ld) set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) diff --git a/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk b/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk index d37a425fb..923c90753 100644 --- a/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk +++ b/hw/bsp/stm32h7/boards/stm32h750bdk/board.mk @@ -15,7 +15,7 @@ SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32h750xx.s LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32h750xx_flash.icf # For flash-jlink target -JLINK_DEVICE = stm32h750xb_m7 +JLINK_DEVICE = stm32h750xb # flash target using on-board stlink flash: flash-stlink diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c index adeb38e74..c81437958 100644 --- a/hw/bsp/stm32h7/family.c +++ b/hw/bsp/stm32h7/family.c @@ -102,9 +102,6 @@ void board_init(void) { trace_etm_init(); - // Enable UART Clock - UART_CLK_EN(); - #if CFG_TUSB_OS == OPT_OS_NONE // 1ms tick timer SysTick_Config(SystemCoreClock / 1000); @@ -136,7 +133,10 @@ void board_init(void) { GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; HAL_GPIO_Init(BUTTON_PORT, &GPIO_InitStruct); +#ifdef UART_DEV // Uart + UART_CLK_EN(); + GPIO_InitStruct.Pin = UART_TX_PIN | UART_RX_PIN; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Pull = GPIO_PULLUP; @@ -153,6 +153,7 @@ void board_init(void) { UartHandle.Init.Mode = UART_MODE_TX_RX; UartHandle.Init.OverSampling = UART_OVERSAMPLING_16; HAL_UART_Init(&UartHandle); +#endif #if BOARD_TUD_RHPORT == 0 // Despite being call USB2_OTG @@ -280,8 +281,13 @@ int board_uart_read(uint8_t *buf, int len) { } int board_uart_write(void const *buf, int len) { +#ifdef UART_DEV HAL_UART_Transmit(&UartHandle, (uint8_t * )(uintptr_t) buf, len, 0xffff); +#else + (void) buf; +#endif + return len; } diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index 5c7e5e688..cfd0c81a8 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -1,58 +1,58 @@ -| | BCM2711 (Pi4) | EFM32GG FS | ESP32-S2/S3 | ESP32-P4 | ST F407/411/429 FS | ST F407/429 HS | ST F412/767 FS | ST F723 FS | ST F723 HS | ST F769 | ST H743 HS | ST L476 FS | ST U5A5 HS | GD32VF103 FS | XMC4500 | -|:---------------------------|:----------------|:-------------|:--------------|:-------------|:---------------------|:-----------------|:-----------------|:-------------|:-------------|:-------------|:-------------|:-------------|:-------------|:---------------|:-------------| -| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | -| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | -| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | -| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | -| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | -| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | -| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | DMA internal | -| - p2p (hub support) | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | -| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | -| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | n/a | Dedicated | -| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | -| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 0 | 13 | -| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nptx_q_depth | 2 | 2 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - ptx_q_depth | 2 | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | -| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | -| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | -| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | -| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | -| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | -| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | -| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 0 | 634 | -| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | -| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | -| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | -| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | -| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | +| | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/767 FS | ST F723/L4P5 FS | ST F723 HS | ST F769 | ST H743/H750 | ST L476 FS | ST U5A5 HS | GD32VF103 | XMC4500 | +|:---------------------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:-------------|:------------|:-------------| +| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | +| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | +| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | +| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | +| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | +| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | DMA internal | +| - p2p (hub support) | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | +| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | +| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | n/a | Dedicated | +| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | +| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 0 | 13 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nptx_q_depth | 2 | 2 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - ptx_q_depth | 2 | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | +| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | +| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | +| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | +| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 0 | 634 | +| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | +| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | +| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | +| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | +| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index ac32eb585..d1793a005 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -10,20 +10,21 @@ import pandas as pd dwc2_reg_list = ['GUID', 'GSNPSID', 'GHWCFG1', 'GHWCFG2', 'GHWCFG3', 'GHWCFG4'] dwc2_reg_value = { 'BCM2711 (Pi4)': [0x2708A000, 0x4F54280A, 0, 0x228DDD50, 0xFF000E8, 0x1FF00020], - 'EFM32GG FS': [0, 0x4F54330A, 0, 0x228F5910, 0x1F204E8, 0x1BF08030], - 'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0xC804B5, 0xD3F0A030], + 'EFM32GG': [0, 0x4F54330A, 0, 0x228F5910, 0x01F204E8, 0x1BF08030], + 'ESP32-S2/S3': [0, 0x4F54400A, 0, 0x224DD930, 0x0C804B5, 0xD3F0A030], 'ESP32-P4': [0, 0x4F54400A, 0, 0x215FFFD0, 0x03805EB5, 0xDFF1A030], - 'ST F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030], - 'ST F407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030], - 'ST F412/767 FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], - 'ST F723 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], - 'ST F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x3EED2E8, 0x23F00030], + 'ST F207/F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x020001E8, 0x0FF08030], + 'ST F407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x03F403E8, 0x17F00030], + 'ST F412/767 FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], + 'ST F723/L4P5 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], + 'ST F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x03EED2E8, 0x23F00030], 'ST F769': [0x2100, 0x4F54320A, 0, 0x229FE190, 0x03EED2E8, 0x23F00030], - 'ST H743 HS': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x3B8D2E8, 0xE3F00030], # both HS cores - 'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], + 'ST H743/H750': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x03B8D2E8, 0xE3F00030], + 'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], 'ST U5A5 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30], - 'GD32VF103 FS': [0x1000, 0, 0, 0, 0, 0], - 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x27A01E5, 0xDBF08030] + 'GD32VF103': [0x1000, 0, 0, 0, 0, 0], + 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030] + } # Combine dwc2_info with dwc2_reg_list diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py index 60bba9bd2..0d7cae77e 100755 --- a/test/hil/hil_test.py +++ b/test/hil/hil_test.py @@ -245,7 +245,7 @@ def test_dual_host_info_to_device_cdc(board): # for pico/pico2 make this test optional failed_msg = f'Enumerated devices {enum_dev_sn} not match with declared {declared_devs}' if 'raspberry_pi_pico' in board['name']: - print(f'\r\n {failed_msg} ', end='') + print(f'\r\n {failed_msg} {STATUS_FAILED} ', end='') else: assert False, failed_msg return 0 diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json index 2358c3c4f..44d4a617c 100644 --- a/test/hil/tinyusb.json +++ b/test/hil/tinyusb.json @@ -20,6 +20,13 @@ "flasher_sn": "000682804350", "flasher_args": "-device nrf52840_xxaa" }, + { + "name": "max32666fthr", + "uid": "0C81464124010B20FF0A08CC2C", + "flasher": "openocd_adi", + "flasher_sn": "E6614C311B597D32", + "flasher_args": "-f interface/cmsis-dap.cfg -f target/max32665.cfg" + }, { "name": "metro_m4_express", "uid": "9995AD485337433231202020FF100A34", @@ -30,13 +37,6 @@ "dual_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002130"}] } }, - { - "name": "max32666fthr", - "uid": "0C81464124010B20FF0A08CC2C", - "flasher": "openocd_adi", - "flasher_sn": "E6614C311B597D32", - "flasher_args": "-f interface/cmsis-dap.cfg -f target/max32665.cfg" - }, { "name": "lpcxpresso11u37", "uid": "17121919", @@ -82,6 +82,16 @@ "flasher_sn": "779541626", "flasher_args": "-device stm32f072rb" }, + { + "name": "stm32f407disco", + "uid": "30001A000647313332353735", + "build" : { + "flags_on": ["", "CFG_TUD_DWC2_DMA"] + }, + "flasher": "jlink", + "flasher_sn": "000773661813", + "flasher_args": "-device stm32f407vg" + }, { "name": "stm32f769disco", "uid": "21002F000F51363531383437", -- cgit v1.3.1 From 98e94a5d6d5dfd2bb468f3c2f4c9e82925fedd91 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 9 Oct 2024 21:47:23 +0700 Subject: enhance dwc2 --- hw/bsp/xmc4000/boards/xmc4500_relax/board.cmake | 1 + src/portable/synopsys/dwc2/dcd_dwc2.c | 135 ++++++++++-------------- src/portable/synopsys/dwc2/dwc2_type.h | 6 +- 3 files changed, 61 insertions(+), 81 deletions(-) (limited to 'src/portable') diff --git a/hw/bsp/xmc4000/boards/xmc4500_relax/board.cmake b/hw/bsp/xmc4000/boards/xmc4500_relax/board.cmake index ec36bcc4d..e18741a9b 100644 --- a/hw/bsp/xmc4000/boards/xmc4500_relax/board.cmake +++ b/hw/bsp/xmc4000/boards/xmc4500_relax/board.cmake @@ -1,6 +1,7 @@ set(MCU_VARIANT XMC4500) set(JLINK_DEVICE XMC4500-1024) +#set(JLINK_OPTION "-USB 000551005307") set(LD_FILE_GNU ${SDK_DIR}/CMSIS/Infineon/COMPONENT_${MCU_VARIANT}/Source/TOOLCHAIN_GCC_ARM/XMC4500x1024.ld) function(update_board TARGET) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 99cf3fdaa..c0700633d 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -398,12 +398,8 @@ static void bus_reset(uint8_t rhport) { tu_memclr(xfer_status, sizeof(xfer_status)); _sof_en = false; - _allocated_ep_in_count = 1; - // clear device address - dwc2->dcfg &= ~DCFG_DAD_Msk; - // 1. NAK for all OUT endpoints for (uint8_t n = 0; n < ep_count; n++) { dwc2->epout[n].doepctl |= DOEPCTL_SNAK; @@ -419,13 +415,17 @@ static void bus_reset(uint8_t rhport) { dfifo_flush_tx(dwc2, 0x10); // all tx fifo dfifo_flush_rx(dwc2); - // 3. Set up interrupt mask + // 3. Set up interrupt mask for EP0 dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos); dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM; dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM; + // 4. Set up DFIFO dfifo_init(rhport); + // 5. Reset device address + dwc2->dcfg &= ~DCFG_DAD_Msk; + // Fixed both control EP0 size to 64 bytes dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos); dwc2->epout[0].doepctl &= ~(0x03 << DOEPCTL_MPSIZ_Pos); @@ -907,7 +907,9 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t uint16_t const short_packet_size = total_bytes % xfer->max_size; // Zero-size packet is special case. - if (short_packet_size > 0 || (total_bytes == 0)) num_packets++; + if (short_packet_size > 0 || (total_bytes == 0)) { + num_packets++; + } // Schedule packets to be sent within interrupt edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); @@ -941,6 +943,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { // Interrupt Handler //-------------------------------------------------------------------- +// Process shared receive FIFO, this interrupt is only used in Slave mode static void handle_rxflvl_irq(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); volatile uint32_t const* rx_fifo = dwc2->fifo[0]; @@ -950,20 +953,8 @@ static void handle_rxflvl_irq(uint8_t rhport) { uint8_t const pktsts = (grxstsp & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; uint8_t const epnum = (grxstsp & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; uint16_t const bcnt = (grxstsp & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; - dwc2_epout_t* epout = &dwc2->epout[epnum]; -//#if CFG_TUSB_DEBUG >= DWC2_DEBUG -// const char * pktsts_str[] = -// { -// "ASSERT", "Global NAK (ISR)", "Out Data Received", "Out Transfer Complete (ISR)", -// "Setup Complete (ISR)", "ASSERT", "Setup Data Received" -// }; -// TU_LOG_LOCATION(); -// TU_LOG(DWC2_DEBUG, " EP %02X, Byte Count %u, %s\r\n", epnum, bcnt, pktsts_str[pktsts]); -// TU_LOG(DWC2_DEBUG, " daint = %08lX, doepint = %04X\r\n", (unsigned long) dwc2->daint, (unsigned int) epout->doepint); -//#endif - switch (pktsts) { // Global OUT NAK: do nothing case GRXSTS_PKTSTS_GLOBALOUTNAK: @@ -971,15 +962,14 @@ static void handle_rxflvl_irq(uint8_t rhport) { case GRXSTS_PKTSTS_SETUPRX: // Setup packet received - - // We can receive up to three setup packets in succession, but - // only the last one is valid. + // We can receive up to three setup packets in succession, but only the last one is valid. _setup_packet[0] = (*rx_fifo); _setup_packet[1] = (*rx_fifo); break; case GRXSTS_PKTSTS_SETUPDONE: - // Setup packet done (Interrupt) + // Setup packet done: + // After popping this out, dwc2 asserts a DOEPINT_SETUP interrupt which is handled by handle_epout_irq() epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); break; @@ -1011,8 +1001,8 @@ static void handle_rxflvl_irq(uint8_t rhport) { } case GRXSTS_PKTSTS_OUTDONE: - /* Out packet done (Interrupt) - After this entry is popped from the receive FIFO, the controller asserts a Transfer Completed interrupt on + /* Out packet done + After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed interrupt on the specified OUT endpoint which will be handled by handle_epout_irq() */ break; @@ -1034,51 +1024,56 @@ static void handle_epout_irq(uint8_t rhport) { const uint32_t doepint = epout->doepint; TU_ASSERT((epout->doepint & DOEPINT_AHBERR) == 0, ); + TU_LOG1_HEX(doepint); + + // Setup and/or STPKTRX/STSPHSRX (from 3.00a) can be set along with XFRC, and also set independently. + if (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a) { + if (doepint & DOEPINT_STSPHSRX) { + // Status phase received for control write: In token received from Host + epout->doepint = DOEPINT_STSPHSRX; + } + + if (doepint & DOEPINT_STPKTRX) { + // New setup packet received, but wait for Setup done, since we can receive up to 3 setup consecutively + epout->doepint = DOEPINT_STPKTRX; + } + } + + if (doepint & DOEPINT_SETUP) { + epout->doepint = DOEPINT_SETUP; + + if(dma_enabled(dwc2)) { + dma_setup_prepare(rhport); + } + + dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); + } + // OUT XFER complete if (doepint & DOEPINT_XFRC) { epout->doepint = DOEPINT_XFRC; - xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); + // only handle data skip if it is setup or status related + // Normal OUT transfer complete + if (!(doepint & (DOEPINT_SETUP | DOEPINT_STPKTRX | DOEPINT_STSPHSRX))) { + xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - if(dma_enabled(dwc2)) { - if (doepint & DOEPINT_SETUP) { - // STPKTRX is only available for version from 3_00a - if ((doepint & DOEPINT_DMA_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { - epout->doepint = DOEPINT_DMA_STPKTRX; - } - } else if (doepint & DOEPINT_STSPHSRX) { - epout->doepint = DOEPINT_STSPHSRX; - } else { - if ((doepint & DOEPINT_DMA_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { - epout->doepint = DOEPINT_DMA_STPKTRX; + if(dma_enabled(dwc2)) { + if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { + // EP0 can only handle one packet Schedule another packet to be received. + edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); } else { - // EP0 can only handle one packet - if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { - // Schedule another packet to be received. - edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); - } else { - // Fix packet length - uint16_t remain = (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; - xfer->total_len -= remain; - // this is ZLP, so prepare EP0 for next setup - if(epnum == 0 && xfer->total_len == 0) { - dma_setup_prepare(rhport); - } - - dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); + // Fix packet length + uint16_t remain = (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; + xfer->total_len -= remain; + // this is ZLP, so prepare EP0 for next setup + if(epnum == 0 && xfer->total_len == 0) { + dma_setup_prepare(rhport); } + + dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); } - } - } else { - // DMA_STPKTRX should only be set in Buffer DMA Mode. However, STM32L476 (slave-only) with v3.10a - // incorrectly set this along with SETUP bit. This may (or not) be STM32L476 or 3.10a specific bug - if ((doepint & DOEPINT_DMA_STPKTRX) && (dwc2->gsnpsid == DWC2_CORE_REV_3_10a)) { - epout->doepint = DOEPINT_DMA_STPKTRX; } else { - if ((doepint & DOEPINT_STSPHSRX) && (dwc2->gsnpsid == DWC2_CORE_REV_3_10a)) { - epout->doepint = DOEPINT_STSPHSRX; - } - // EP0 can only handle one packet if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { // Schedule another packet to be received. @@ -1089,19 +1084,6 @@ static void handle_epout_irq(uint8_t rhport) { } } } - - // SETUP packet Setup Phase done. - if (doepint & DOEPINT_SETUP) { - epout->doepint = DOEPINT_SETUP; - if ((doepint & DOEPINT_DMA_STPKTRX) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { - epout->doepint = DOEPINT_DMA_STPKTRX; - } - if(dma_enabled(dwc2) && (dwc2->gsnpsid > DWC2_CORE_REV_3_00a)) { - dma_setup_prepare(rhport); - } - - dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); - } } } } @@ -1274,13 +1256,10 @@ void dcd_int_handler(uint8_t rhport) { // RxFIFO non-empty interrupt handling. if (int_status & GINTSTS_RXFLVL) { // RXFLVL bit is read-only - - // Mask out RXFLVL while reading data from FIFO - dwc2->gintmsk &= ~GINTMSK_RXFLVLM; + dwc2->gintmsk &= ~GINTMSK_RXFLVLM; // disable RXFLVL interrupt while reading do { - // Loop until all available packets were handled - handle_rxflvl_irq(rhport); + handle_rxflvl_irq(rhport); // read all packets } while(dwc2->gintsts & GINTSTS_RXFLVL); dwc2->gintmsk |= GINTMSK_RXFLVLM; diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index d5a51fb09..cf05bbfec 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -1954,9 +1954,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DOEPINT_NYET_Msk (0x1UL << DOEPINT_NYET_Pos) // 0x00004000 #define DOEPINT_NYET DOEPINT_NYET_Msk // NYET interrupt -#define DOEPINT_DMA_STPKTRX_Pos (15U) -#define DOEPINT_DMA_STPKTRX_Msk (0x1UL << DOEPINT_DMA_STPKTRX_Pos) // 0x00008000 -#define DOEPINT_DMA_STPKTRX DOEPINT_DMA_STPKTRX_Msk // Setup Packet Received in Buffer DMA Mode +#define DOEPINT_STPKTRX_Pos (15U) +#define DOEPINT_STPKTRX_Msk (0x1UL << DOEPINT_STPKTRX_Pos) // 0x00008000 +#define DOEPINT_STPKTRX DOEPINT_STPKTRX_Msk // Setup Packet Received /******************** Bit definition for DOEPTSIZ register ********************/ #define DOEPTSIZ_XFRSIZ_Pos (0U) -- cgit v1.3.1 From 1406ad84e3cd7e39771303dd23e6be361b51de96 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 10 Oct 2024 11:05:32 +0700 Subject: remove debug code --- src/portable/synopsys/dwc2/dcd_dwc2.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index c0700633d..1ba3507ef 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -1024,8 +1024,6 @@ static void handle_epout_irq(uint8_t rhport) { const uint32_t doepint = epout->doepint; TU_ASSERT((epout->doepint & DOEPINT_AHBERR) == 0, ); - TU_LOG1_HEX(doepint); - // Setup and/or STPKTRX/STSPHSRX (from 3.00a) can be set along with XFRC, and also set independently. if (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a) { if (doepint & DOEPINT_STSPHSRX) { -- cgit v1.3.1 From d997f0071ea5d2d07e340d183fffb97e09526773 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 11 Oct 2024 15:21:32 +0700 Subject: change dcd_init() to take rhport struct --- .pre-commit-config.yaml | 15 +++++++++++++++ src/device/dcd.h | 2 +- src/device/usbd.c | 2 +- src/portable/bridgetek/ft9xx/dcd_ft9xx.c | 4 ++-- src/portable/chipidea/ci_fs/dcd_ci_fs.c | 4 ++-- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 4 ++-- src/portable/dialog/da146xx/dcd_da146xx.c | 4 ++-- src/portable/espressif/esp32sx/dcd_esp32sx.c | 4 ++-- src/portable/mentor/musb/dcd_musb.c | 3 ++- src/portable/microchip/pic/dcd_pic.c | 4 ++-- src/portable/microchip/pic32mz/dcd_pic32mz.c | 4 ++-- src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c | 4 ++-- src/portable/nordic/nrf5x/dcd_nrf5x.c | 3 ++- src/portable/nuvoton/nuc120/dcd_nuc120.c | 4 ++-- src/portable/nuvoton/nuc121/dcd_nuc121.c | 4 ++-- src/portable/nuvoton/nuc505/dcd_nuc505.c | 4 ++-- src/portable/nxp/khci/dcd_khci.c | 4 ++-- src/portable/nxp/lpc17_40/dcd_lpc17_40.c | 4 ++-- src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 4 ++-- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 3 ++- src/portable/renesas/rusb2/dcd_rusb2.c | 4 ++-- src/portable/sony/cxd56/dcd_cxd56.c | 4 ++-- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 3 ++- src/portable/sunxi/dcd_sunxi_musb.c | 4 ++-- src/portable/synopsys/dwc2/dcd_dwc2.c | 3 ++- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 12 ++++++++---- src/portable/valentyusb/eptri/dcd_eptri.c | 4 ++-- src/portable/wch/dcd_ch32_usbfs.c | 3 ++- src/portable/wch/dcd_ch32_usbhs.c | 3 ++- test/unit-test/test/device/msc/test_msc_device.c | 7 +++---- test/unit-test/test/device/usbd/test_usbd.c | 10 +++++----- 31 files changed, 83 insertions(+), 58 deletions(-) (limited to 'src/portable') diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index bba217cc9..21da285c1 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -42,3 +42,18 @@ repos: pass_filenames: false types_or: [c, header] language: system + + - id: build-fuzzer + name: build-fuzzer + files: ^(src/|test/fuzz/) + language: system + types_or: [c, header] + entry: | + export CC=clang + export CXX=clang++ + fuzz_harness=$(ls -d test/fuzz/device/*/) + for h in $fuzz_harness + do + make -C $h get-deps + make -C $h all + done diff --git a/src/device/dcd.h b/src/device/dcd.h index 3ef5188fc..8fa7b8bc1 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -108,7 +108,7 @@ void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_W //--------------------------------------------------------------------+ // Initialize controller to device mode -void dcd_init(uint8_t rhport); +void dcd_init(const tusb_rhport_init_t* rh_init); // Deinitialize controller, unset device mode. bool dcd_deinit(uint8_t rhport); diff --git a/src/device/usbd.c b/src/device/usbd.c index 7e35c976c..12f95ab40 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -490,7 +490,7 @@ bool tud_rhport_init(const tusb_rhport_init_t* rh_init) { _usbd_rhport = rh_init->rhport; // Init device controller driver - dcd_init(rh_init->rhport); + dcd_init(rh_init); dcd_int_enable(rh_init->rhport); return true; diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c index f02415904..f4b236da6 100644 --- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c +++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c @@ -517,8 +517,8 @@ static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t len *------------------------------------------------------------------*/ // Initialize controller to device mode -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; TU_LOG2("FT9xx initialisation\r\n"); _dcd_ft9xx_attach(); diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c index 02f813ab5..315e9a86d 100644 --- a/src/portable/chipidea/ci_fs/dcd_ci_fs.c +++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c @@ -267,8 +267,8 @@ static void process_bus_resume(uint8_t rhport) /*------------------------------------------------------------------*/ /* Device API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; (void) rhport; // save crystal-less setting (if available) diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index 93e1d78dd..bdb7abe41 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -234,8 +234,8 @@ static void bus_reset(uint8_t rhport) dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); } -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; tu_memclr(&_dcd_data, sizeof(dcd_data_t)); ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index d1e85c2df..05cebea0b 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -804,8 +804,8 @@ static void handle_ep0_nak(void) /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; (void) rhport; _dcd.init_called = true; diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c index 61911ab4c..3d4757f03 100644 --- a/src/portable/espressif/esp32sx/dcd_esp32sx.c +++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c @@ -172,8 +172,8 @@ static void enum_done_processing(void) /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; ESP_LOGV(TAG, "DCD init - Start"); // A. Disconnect diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index a40b3dc07..a8437ad5b 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -582,7 +582,8 @@ void print_musb_info(musb_regs_t* musb_regs) { } #endif -void dcd_init(uint8_t rhport) { +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; musb_regs_t* musb_regs = MUSB_REGS(rhport); #if CFG_TUSB_DEBUG >= MUSB_DEBUG diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c index ccc27c3c9..3ee0ab6d5 100644 --- a/src/portable/microchip/pic/dcd_pic.c +++ b/src/portable/microchip/pic/dcd_pic.c @@ -470,8 +470,8 @@ static void process_bus_resume(uint8_t rhport) /*------------------------------------------------------------------*/ /* Device API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; intr_disable(rhport); intr_clear(rhport); diff --git a/src/portable/microchip/pic32mz/dcd_pic32mz.c b/src/portable/microchip/pic32mz/dcd_pic32mz.c index 9ad755670..004990046 100644 --- a/src/portable/microchip/pic32mz/dcd_pic32mz.c +++ b/src/portable/microchip/pic32mz/dcd_pic32mz.c @@ -120,8 +120,8 @@ static ep0_stage_t ep0_get_stage(void) /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; // Disable endpoint interrupts for now USB_REGS->INTRRXEbits.w = 0; USB_REGS->INTRTXEbits.w = 0; diff --git a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c index d5c0daaeb..4117ab45f 100644 --- a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c +++ b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c @@ -245,8 +245,8 @@ static void process_bus_active(uint8_t rhport) /*------------------------------------------------------------------*/ /* Device API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; (void) rhport; tu_memclr(&_dcd, sizeof(_dcd)); diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index a63e442f3..c1084c20c 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -230,7 +230,8 @@ static void xact_in_dma(uint8_t epnum) { //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ -void dcd_init(uint8_t rhport) { +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; TU_LOG2("dcd init\r\n"); (void) rhport; } diff --git a/src/portable/nuvoton/nuc120/dcd_nuc120.c b/src/portable/nuvoton/nuc120/dcd_nuc120.c index fb12122e0..c9e8d86fd 100644 --- a/src/portable/nuvoton/nuc120/dcd_nuc120.c +++ b/src/portable/nuvoton/nuc120/dcd_nuc120.c @@ -201,8 +201,8 @@ static const uint32_t enabled_irqs = USBD_INTSTS_FLDET_STS_Msk | USBD_INTSTS_BUS NUC100/NUC120 TinyUSB API driver implementation */ -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; (void) rhport; USBD->ATTR = 0x7D0; diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c index 873b1b7ef..78c65a91c 100644 --- a/src/portable/nuvoton/nuc121/dcd_nuc121.c +++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c @@ -209,8 +209,8 @@ enum { NUC121/NUC125/NUC126 TinyUSB API driver implementation */ -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; (void) rhport; #ifdef SUPPORT_LPM diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c index 3a92c9794..caeb89a0a 100644 --- a/src/portable/nuvoton/nuc505/dcd_nuc505.c +++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c @@ -279,8 +279,8 @@ static const uint32_t enabled_irqs = USBD_GINTEN_USBIEN_Msk | \ NUC505 TinyUSB API driver implementation */ -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; (void) rhport; /* configure interrupts in their initial state; BUSINTEN and CEPINTEN will be subsequently and dynamically re-written as needed */ diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index ef61146aa..2d08e84a5 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -265,8 +265,8 @@ static void process_bus_resume(uint8_t rhport) /*------------------------------------------------------------------*/ /* Device API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; (void) rhport; // save crystal-less setting (if available) diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c index 75b29faf3..e28b27919 100644 --- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c +++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c @@ -167,8 +167,8 @@ static void bus_reset(void) tu_memclr(&_dcd, sizeof(dcd_data_t)); } -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; (void) rhport; //------------- user manual 11.13 usb device controller initialization -------------// diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c index cc18cf59b..06a82c4e7 100644 --- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c +++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c @@ -289,8 +289,8 @@ static void edpt_reset_all(uint8_t rhport) } prepare_setup_packet(rhport); } -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; edpt_reset_all(rhport); dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index bc0deee32..9473d3bd8 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -369,7 +369,8 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) { #define PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY 0xff #endif -void dcd_init(uint8_t rhport) { +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; assert(rhport == 0); TU_LOG(2, "Chip Version B%u\r\n", rp2040_chip_version()); diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 7c6044ca0..e8e1bf041 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -657,8 +657,8 @@ static void enable_interrupt(uint32_t pswi) } #endif -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; rusb2_reg_t* rusb = RUSB2_REG(rhport); rusb2_module_start(rhport, true); diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c index 41814370e..fe1c42249 100644 --- a/src/portable/sony/cxd56/dcd_cxd56.c +++ b/src/portable/sony/cxd56/dcd_cxd56.c @@ -201,8 +201,8 @@ static void _dcd_resume(FAR struct usbdevclass_driver_s *driver, FAR struct usbd dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); } -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; (void) rhport; usbdcd_driver.usbdevclass_driver.speed = USB_SPEED_HIGH; diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 6eea1ab32..8e9bb0b30 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -184,7 +184,8 @@ TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t *xfer_ctl_ptr(uint8_t epnum, uint //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ -void dcd_init(uint8_t rhport) { +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; // Follow the RM mentions to use a special ordering of PDWN and FRES for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us asm("NOP"); diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c index 6f36ad441..d7bf1068a 100644 --- a/src/portable/sunxi/dcd_sunxi_musb.c +++ b/src/portable/sunxi/dcd_sunxi_musb.c @@ -867,8 +867,8 @@ static void usb_isr_handler(void) { dcd_int_handler(0); } -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; dcd_disconnect(rhport); USBC_HardwareReset(); USBC_PhyConfig(); diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 1ba3507ef..580960e24 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -650,9 +650,10 @@ static bool check_dwc2(dwc2_regs_t* dwc2) { return true; } -void dcd_init(uint8_t rhport) { +void dcd_init(const tusb_rhport_init_t* rh_init) { // Programming model begins in the last section of the chapter on the USB // peripheral in each Reference Manual. + const uint8_t rhport = rh_init->rhport; dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Check Synopsys ID register, failed if controller clock/power is not enabled diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 6b60bc657..120d5c4b9 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -130,9 +130,8 @@ static void enable_functional_reset(const bool enable) /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ -void dcd_init (uint8_t rhport) -{ - (void) rhport; +void dcd_init(const tusb_rhport_init_t* rh_init) { + (void) rh_init; USBKEYPID = USBKEY; @@ -699,7 +698,12 @@ static void handle_bus_power_event(void *param) { // A successful lock is indicated by all PLL-related interrupt flags being cleared. if(!USBPLLIR) { - dcd_init(0); // Re-initialize the USB module. + const tusb_rhport_init_t rhport_init = { + .rhport = 0, + .role = TUSB_ROLE_DEVICE, + .speed = TUSB_SPEED_FULL + }; + dcd_init(&rhport_init); // Re-initialize the USB module. } } else { // Event caused by removal of bus power. USBPWRCTL |= VBONIE; // Enable bus-power-applied interrupt. diff --git a/src/portable/valentyusb/eptri/dcd_eptri.c b/src/portable/valentyusb/eptri/dcd_eptri.c index 8f40e3349..da7a5a81a 100644 --- a/src/portable/valentyusb/eptri/dcd_eptri.c +++ b/src/portable/valentyusb/eptri/dcd_eptri.c @@ -336,8 +336,8 @@ static void dcd_reset(void) } // Initializes the USB peripheral for device mode and enables it. -void dcd_init(uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; (void) rhport; usb_pullup_out_write(0); diff --git a/src/portable/wch/dcd_ch32_usbfs.c b/src/portable/wch/dcd_ch32_usbfs.c index 9ed370b40..4a7ad704b 100644 --- a/src/portable/wch/dcd_ch32_usbfs.c +++ b/src/portable/wch/dcd_ch32_usbfs.c @@ -123,7 +123,8 @@ static void update_out(uint8_t rhport, uint8_t ep, size_t rx_len) { } /* public functions */ -void dcd_init(uint8_t rhport) { +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; // init registers USBOTG_FS->BASE_CTRL = USBFS_CTRL_SYS_CTRL | USBFS_CTRL_INT_BUSY | USBFS_CTRL_DMA_EN; USBOTG_FS->UDEV_CTRL = USBFS_UDEV_CTRL_PD_DIS | USBFS_UDEV_CTRL_PORT_EN; diff --git a/src/portable/wch/dcd_ch32_usbhs.c b/src/portable/wch/dcd_ch32_usbhs.c index 622f9c508..77ebc378c 100644 --- a/src/portable/wch/dcd_ch32_usbhs.c +++ b/src/portable/wch/dcd_ch32_usbhs.c @@ -131,7 +131,8 @@ static void xfer_data_packet(uint8_t ep_num, tusb_dir_t ep_dir, xfer_ctl_t* xfer ep_set_response_and_toggle(ep_num, ep_dir, USBHS_EP_R_RES_ACK); } -void dcd_init(uint8_t rhport) { +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; (void) rhport; memset(&xfer_status, 0, sizeof(xfer_status)); diff --git a/test/unit-test/test/device/msc/test_msc_device.c b/test/unit-test/test/device/msc/test_msc_device.c index 3444d81c5..4033bf158 100644 --- a/test/unit-test/test/device/msc/test_msc_device.c +++ b/test/unit-test/test/device/msc/test_msc_device.c @@ -197,15 +197,14 @@ void setUp(void) dcd_int_disable_Ignore(); dcd_int_enable_Ignore(); - if ( !tud_inited() ) - { - dcd_init_Expect(rhport); - + if ( !tud_inited() ) { tusb_rhport_init_t dev_init = { .rhport = 0, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; + + dcd_init_Expect(&dev_init); tusb_init(&dev_init); } diff --git a/test/unit-test/test/device/usbd/test_usbd.c b/test/unit-test/test/device/usbd/test_usbd.c index faa6b159e..8f900f656 100644 --- a/test/unit-test/test/device/usbd/test_usbd.c +++ b/test/unit-test/test/device/usbd/test_usbd.c @@ -124,16 +124,16 @@ void setUp(void) dcd_int_disable_Ignore(); dcd_int_enable_Ignore(); - if ( !tud_inited() ) - { - mscd_init_Expect(); - dcd_init_Expect(rhport); - + if ( !tud_inited() ) { tusb_rhport_init_t dev_init = { .rhport = 0, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; + + mscd_init_Expect(); + dcd_init_Expect(&dev_init); + tusb_init(&dev_init); } } -- cgit v1.3.1 From f3b7d7515e9cae834013dc9ee3a67d87111090eb Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 11 Oct 2024 16:00:51 +0700 Subject: fix fuzzing build --- .pre-commit-config.yaml | 28 +++++++-------- src/device/dcd.h | 23 +++++++----- src/portable/microchip/samd/dcd_samd.c | 5 ++- src/portable/microchip/samg/dcd_samg.c | 4 +-- src/portable/microchip/samx7x/dcd_samx7x.c | 4 +-- src/portable/raspberrypi/pio_usb/dcd_pio_usb.c | 6 ++-- src/portable/template/dcd_template.c | 48 ++++++++------------------ test/fuzz/dcd_fuzz.cc | 4 +-- 8 files changed, 54 insertions(+), 68 deletions(-) (limited to 'src/portable') diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 21da285c1..9cd4a5ed1 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -43,17 +43,17 @@ repos: types_or: [c, header] language: system - - id: build-fuzzer - name: build-fuzzer - files: ^(src/|test/fuzz/) - language: system - types_or: [c, header] - entry: | - export CC=clang - export CXX=clang++ - fuzz_harness=$(ls -d test/fuzz/device/*/) - for h in $fuzz_harness - do - make -C $h get-deps - make -C $h all - done +# - id: build-fuzzer +# name: build-fuzzer +# files: ^(src/|test/fuzz/) +# language: system +# types_or: [c, header] +# entry: | +# bash -c 'export CC=clang +# export CXX=clang++ +# fuzz_harness=$(ls -d test/fuzz/device/*/) +# for h in $fuzz_harness +# do +# make -C $h get-deps +# make -C $h all +# done' diff --git a/src/device/dcd.h b/src/device/dcd.h index 8fa7b8bc1..02f3847ff 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -194,38 +194,45 @@ extern void dcd_event_handler(dcd_event_t const * event, bool in_isr); // helper to send bus signal event TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_signal (uint8_t rhport, dcd_eventid_t eid, bool in_isr) { - dcd_event_t event = { .rhport = rhport, .event_id = eid }; + dcd_event_t event; + event.rhport = rhport; + event.event_id = eid; dcd_event_handler(&event, in_isr); } // helper to send bus reset event TU_ATTR_ALWAYS_INLINE static inline void dcd_event_bus_reset (uint8_t rhport, tusb_speed_t speed, bool in_isr) { - dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_BUS_RESET }; + dcd_event_t event; + event.rhport = rhport; + event.event_id = DCD_EVENT_BUS_RESET; event.bus_reset.speed = speed; dcd_event_handler(&event, in_isr); } // helper to send setup received TU_ATTR_ALWAYS_INLINE static inline void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr) { - dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SETUP_RECEIVED }; + dcd_event_t event; + event.rhport = rhport; + event.event_id = DCD_EVENT_SETUP_RECEIVED; memcpy(&event.setup_received, setup, sizeof(tusb_control_request_t)); - dcd_event_handler(&event, in_isr); } // helper to send transfer complete event TU_ATTR_ALWAYS_INLINE static inline void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr) { - dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_XFER_COMPLETE }; - + dcd_event_t event; + event.rhport = rhport; + event.event_id = DCD_EVENT_XFER_COMPLETE; event.xfer_complete.ep_addr = ep_addr; event.xfer_complete.len = xferred_bytes; event.xfer_complete.result = result; - dcd_event_handler(&event, in_isr); } TU_ATTR_ALWAYS_INLINE static inline void dcd_event_sof(uint8_t rhport, uint32_t frame_count, bool in_isr) { - dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SOF }; + dcd_event_t event; + event.rhport = rhport; + event.event_id = DCD_EVENT_SOF; event.sof.frame_count = frame_count; dcd_event_handler(&event, in_isr); } diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c index 005b63faf..c3a74ad0f 100644 --- a/src/portable/microchip/samd/dcd_samd.c +++ b/src/portable/microchip/samd/dcd_samd.c @@ -78,9 +78,8 @@ static void bus_reset(void) /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ -void dcd_init (uint8_t rhport) -{ - (void) rhport; +void dcd_init(const tusb_rhport_init_t* rh_init) { + (void) rh_init; // Reset to get in a clean state. USB->DEVICE.CTRLA.bit.SWRST = true; diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c index a15431937..2242d3336 100644 --- a/src/portable/microchip/samg/dcd_samg.c +++ b/src/portable/microchip/samg/dcd_samg.c @@ -155,8 +155,8 @@ static void bus_reset(void) } // Initialize controller to device mode -void dcd_init (uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; tu_memclr(_dcd_xfer, sizeof(_dcd_xfer)); dcd_connect(rhport); } diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c index 9586df84d..d57db6e55 100644 --- a/src/portable/microchip/samx7x/dcd_samx7x.c +++ b/src/portable/microchip/samx7x/dcd_samx7x.c @@ -104,8 +104,8 @@ TU_ATTR_ALWAYS_INLINE static inline void CleanInValidateCache(uint32_t *addr, in //------------------------------------------------------------------ // Initialize controller to device mode -void dcd_init (uint8_t rhport) -{ +void dcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; dcd_connect(rhport); } diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c index e6daf6827..83589efa0 100644 --- a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c @@ -50,10 +50,8 @@ static usb_descriptor_buffers_t desc; *------------------------------------------------------------------*/ // Initialize controller to device mode -void dcd_init (uint8_t rhport) -{ - (void) rhport; - +void dcd_init(const tusb_rhport_init_t* rh_init) { + (void) rh_init; static pio_usb_configuration_t config = PIO_USB_DEFAULT_CONFIG; usb_device = pio_usb_device_init(&config, &desc); } diff --git a/src/portable/template/dcd_template.c b/src/portable/template/dcd_template.c index 25ee507c1..56a89e89a 100644 --- a/src/portable/template/dcd_template.c +++ b/src/portable/template/dcd_template.c @@ -40,54 +40,44 @@ *------------------------------------------------------------------*/ // Initialize controller to device mode -void dcd_init (uint8_t rhport) -{ - (void) rhport; +void dcd_init(const tusb_rhport_init_t* rh_init) { + (void) rh_init; } // Enable device interrupt -void dcd_int_enable (uint8_t rhport) -{ +void dcd_int_enable (uint8_t rhport) { (void) rhport; } // Disable device interrupt -void dcd_int_disable (uint8_t rhport) -{ +void dcd_int_disable (uint8_t rhport) { (void) rhport; } // Receive Set Address request, mcu port must also include status IN response -void dcd_set_address (uint8_t rhport, uint8_t dev_addr) -{ +void dcd_set_address (uint8_t rhport, uint8_t dev_addr) { (void) rhport; (void) dev_addr; } // Wake up host -void dcd_remote_wakeup (uint8_t rhport) -{ +void dcd_remote_wakeup (uint8_t rhport) { (void) rhport; } // Connect by enabling internal pull-up resistor on D+/D- -void dcd_connect(uint8_t rhport) -{ +void dcd_connect(uint8_t rhport) { (void) rhport; } // Disconnect by disabling internal pull-up resistor on D+/D- -void dcd_disconnect(uint8_t rhport) -{ +void dcd_disconnect(uint8_t rhport) { (void) rhport; } -void dcd_sof_enable(uint8_t rhport, bool en) -{ +void dcd_sof_enable(uint8_t rhport, bool en) { (void) rhport; (void) en; - - // TODO implement later } //--------------------------------------------------------------------+ @@ -95,8 +85,7 @@ void dcd_sof_enable(uint8_t rhport, bool en) //--------------------------------------------------------------------+ // Configure endpoint's registers according to descriptor -bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) -{ +bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { (void) rhport; (void) ep_desc; return false; @@ -118,14 +107,12 @@ bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep) return false; } -void dcd_edpt_close_all (uint8_t rhport) -{ +void dcd_edpt_close_all (uint8_t rhport) { (void) rhport; } // Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack -bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) -{ +bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes) { (void) rhport; (void) ep_addr; (void) buffer; @@ -134,8 +121,7 @@ bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t } // Submit a transfer where is managed by FIFO, When complete dcd_event_xfer_complete() is invoked to notify the stack - optional, however, must be listed in usbd.c -bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) -{ +bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) { (void) rhport; (void) ep_addr; (void) ff; @@ -144,19 +130,15 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 } // Stall endpoint -void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) -{ +void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr) { (void) rhport; (void) ep_addr; } // clear stall, data toggle is also reset to DATA0 -void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) -{ +void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) { (void) rhport; (void) ep_addr; } - - #endif diff --git a/test/fuzz/dcd_fuzz.cc b/test/fuzz/dcd_fuzz.cc index 06ddddc4a..7ef0c7446 100644 --- a/test/fuzz/dcd_fuzz.cc +++ b/test/fuzz/dcd_fuzz.cc @@ -46,8 +46,8 @@ tu_static State state = {false, 0, 0}; // All no-ops as we are fuzzing. //--------------------------------------------------------------------+ extern "C" { -void dcd_init(uint8_t rhport) { - UNUSED(rhport); +void dcd_init(const tusb_rhport_init_t* rh_init) { + UNUSED(rh_init); return; } -- cgit v1.3.1 From 1587d48e89cbaa8d0d1c870809bc40c3c8d1056f Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 11 Oct 2024 17:53:39 +0700 Subject: hcd_init() take init struct --- src/host/hcd.h | 19 ++++++------------- src/host/usbh.c | 2 +- src/portable/analog/max3421/hcd_max3421.c | 4 ++-- src/portable/chipidea/ci_hs/hcd_ci_hs.c | 3 ++- src/portable/mentor/musb/hcd_musb.c | 5 ++--- src/portable/nxp/khci/hcd_khci.c | 6 ++---- src/portable/ohci/ohci.c | 4 ++-- src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 4 ++-- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 5 ++--- src/portable/renesas/rusb2/hcd_rusb2.c | 4 ++-- src/portable/template/hcd_template.c | 5 ++--- 11 files changed, 25 insertions(+), 36 deletions(-) (limited to 'src/portable') diff --git a/src/host/hcd.h b/src/host/hcd.h index 5547c7cc5..97cb01754 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -53,26 +53,21 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ -typedef enum -{ +typedef enum { HCD_EVENT_DEVICE_ATTACH, HCD_EVENT_DEVICE_REMOVE, HCD_EVENT_XFER_COMPLETE, - // Not an HCD event, just a convenient way to defer ISR function - USBH_EVENT_FUNC_CALL, - + USBH_EVENT_FUNC_CALL, // Not an HCD event HCD_EVENT_COUNT } hcd_eventid_t; -typedef struct -{ +typedef struct { uint8_t rhport; uint8_t event_id; uint8_t dev_addr; - union - { + union { // Attach, Remove struct { uint8_t hub_addr; @@ -93,11 +88,9 @@ typedef struct void* param; }func_call; }; - } hcd_event_t; -typedef struct -{ +typedef struct { uint8_t rhport; uint8_t hub_addr; uint8_t hub_port; @@ -128,7 +121,7 @@ bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_W bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param); // Initialize controller to host mode -bool hcd_init(uint8_t rhport); +bool hcd_init(const tusb_rhport_init_t* rh_init); // De-initialize controller bool hcd_deinit(uint8_t rhport); diff --git a/src/host/usbh.c b/src/host/usbh.c index 39bc8d63a..f9e6c4e97 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -405,7 +405,7 @@ bool tuh_rhport_init(const tusb_rhport_init_t* rh_init) { // Init host controller _usbh_controller = rh_init->rhport; - TU_ASSERT(hcd_init(rh_init->rhport)); + TU_ASSERT(hcd_init(rh_init)); hcd_int_enable(rh_init->rhport); return true; diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 215feb481..30d822c3b 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -494,8 +494,8 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { } // Initialize controller to host mode -bool hcd_init(uint8_t rhport) { - (void) rhport; +bool hcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; tuh_max3421_int_api(rhport, false); diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index 462cbd301..fbc51f6df 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -70,7 +70,8 @@ bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { // Controller API //--------------------------------------------------------------------+ -bool hcd_init(uint8_t rhport) { +bool hcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; ci_hs_regs_t *hcd_reg = CI_HS_REG(rhport); // Reset controller diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c index 8fc225676..9324c6a34 100644 --- a/src/portable/mentor/musb/hcd_musb.c +++ b/src/portable/mentor/musb/hcd_musb.c @@ -556,9 +556,8 @@ static void process_pipe_rx(uint8_t rhport, uint_fast8_t pipenum) * Host API *------------------------------------------------------------------*/ -bool hcd_init(uint8_t rhport) -{ - (void)rhport; +bool hcd_init(const tusb_rhport_init_t* rh_init) { + (void) rh_init; NVIC_ClearPendingIRQ(USB0_IRQn); _hcd.bmRequestType = REQUEST_TYPE_INVALID; diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c index 57684b259..e9c00b8f9 100644 --- a/src/portable/nxp/khci/hcd_khci.c +++ b/src/portable/nxp/khci/hcd_khci.c @@ -368,10 +368,8 @@ static void process_bus_reset(uint8_t rhport) /*------------------------------------------------------------------*/ /* Host API *------------------------------------------------------------------*/ -bool hcd_init(uint8_t rhport) -{ - (void)rhport; - +bool hcd_init(const tusb_rhport_init_t* rh_init) { + (void) rh_init; KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK; while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK); diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index c59d4755e..fbaa5208e 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -178,8 +178,8 @@ TU_ATTR_ALWAYS_INLINE static inline void *_virt_addr(void *physical_address) } // Initialization according to 5.1.1.4 -bool hcd_init(uint8_t rhport) -{ +bool hcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; (void) rhport; //------------- Data Structure init -------------// diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c index f4de3c51d..4386bbce4 100644 --- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c @@ -55,8 +55,8 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void *cfg_param) { return true; } -bool hcd_init(uint8_t rhport) { - (void) rhport; +bool hcd_init(const tusb_rhport_init_t* rh_init) { + (void) rh_init; // To run USB SOF interrupt in core1, call this init in core1 pio_usb_host_init(&pio_host_cfg); diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 222dbbbf0..a870418a8 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -375,9 +375,8 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t //--------------------------------------------------------------------+ // HCD API //--------------------------------------------------------------------+ -bool hcd_init(uint8_t rhport) -{ - (void) rhport; +bool hcd_init(const tusb_rhport_init_t* rh_init) { + (void) rh_init; pico_trace("hcd_init %d\n", rhport); assert(rhport == 0); diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index f140da690..35e85a3b0 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -466,8 +466,8 @@ static void enable_interrupt(uint32_t pswi) } #endif -bool hcd_init(uint8_t rhport) -{ +bool hcd_init(const tusb_rhport_init_t* rh_init) { + const uint8_t rhport = rh_init->rhport; rusb2_reg_t* rusb = RUSB2_REG(rhport); rusb2_module_start(rhport, true); diff --git a/src/portable/template/hcd_template.c b/src/portable/template/hcd_template.c index b073d6057..9386e95cc 100644 --- a/src/portable/template/hcd_template.c +++ b/src/portable/template/hcd_template.c @@ -44,9 +44,8 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { } // Initialize controller to host mode -bool hcd_init(uint8_t rhport) { - (void) rhport; - +bool hcd_init(const tusb_rhport_init_t* rh_init) { + (void) rh_init; return false; } -- cgit v1.3.1 From 1f18be93db39dbc57bbf34f982dbe07e209a2ae3 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 14 Oct 2024 18:27:52 +0700 Subject: change the tusb_rhport_init_t struct, exclude the rhport to make API more consistent --- .github/workflows/pre-commit.yml | 2 +- .idea/cmake.xml | 13 +++++++------ examples/device/audio_4_channel_mic/src/main.c | 3 +-- .../device/audio_4_channel_mic_freertos/src/main.c | 3 +-- examples/device/audio_test/src/main.c | 3 +-- examples/device/audio_test_freertos/src/main.c | 3 +-- examples/device/audio_test_multi_rate/src/main.c | 3 +-- examples/device/cdc_dual_ports/src/main.c | 3 +-- examples/device/cdc_msc/src/main.c | 3 +-- examples/device/cdc_msc_freertos/src/main.c | 3 +-- examples/device/cdc_uac2/src/main.c | 3 +-- examples/device/dfu/src/main.c | 3 +-- examples/device/dfu_runtime/src/main.c | 3 +-- examples/device/dynamic_configuration/src/main.c | 3 +-- examples/device/hid_boot_interface/src/main.c | 3 +-- examples/device/hid_composite/src/main.c | 3 +-- examples/device/hid_composite_freertos/src/main.c | 3 +-- examples/device/hid_generic_inout/src/main.c | 3 +-- examples/device/hid_multiple_interface/src/main.c | 3 +-- examples/device/midi_test/src/main.c | 3 +-- examples/device/msc_dual_lun/src/main.c | 3 +-- examples/device/net_lwip_webserver/src/main.c | 3 +-- examples/device/uac2_headset/src/main.c | 3 +-- examples/device/uac2_speaker_fb/src/main.c | 3 +-- examples/device/usbtmc/src/main.c | 3 +-- examples/device/video_capture/src/main.c | 6 ++---- examples/device/video_capture_2ch/src/main.c | 6 ++---- examples/device/webusb_serial/src/main.c | 3 +-- examples/dual/host_hid_to_device_cdc/src/main.c | 6 ++---- examples/dual/host_info_to_device_cdc/src/main.c | 6 ++---- examples/host/bare_api/src/main.c | 3 +-- examples/host/cdc_msc_hid/src/main.c | 3 +-- examples/host/cdc_msc_hid_freertos/src/main.c | 3 +-- examples/host/device_info/src/main.c | 3 +-- examples/host/hid_controller/src/main.c | 3 +-- examples/host/msc_file_explorer/src/main.c | 3 +-- src/class/video/video_device.c | 2 +- src/common/tusb_types.h | 1 - src/device/dcd.h | 2 +- src/device/usbd.c | 8 ++++---- src/device/usbd.h | 7 +++---- src/host/hcd.h | 2 +- src/host/usbh.c | 10 +++++----- src/host/usbh.h | 7 +++---- src/portable/analog/max3421/hcd_max3421.c | 4 ++-- src/portable/bridgetek/ft9xx/dcd_ft9xx.c | 4 ++-- src/portable/chipidea/ci_fs/dcd_ci_fs.c | 4 ++-- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 4 ++-- src/portable/chipidea/ci_hs/hcd_ci_hs.c | 8 +++++--- src/portable/dialog/da146xx/dcd_da146xx.c | 4 ++-- src/portable/espressif/esp32sx/dcd_esp32sx.c | 4 ++-- src/portable/mentor/musb/dcd_musb.c | 4 ++-- src/portable/mentor/musb/hcd_musb.c | 3 ++- src/portable/microchip/pic/dcd_pic.c | 4 ++-- src/portable/microchip/pic32mz/dcd_pic32mz.c | 4 ++-- src/portable/microchip/samd/dcd_samd.c | 4 ++-- src/portable/microchip/samg/dcd_samg.c | 5 +++-- src/portable/microchip/samx7x/dcd_samx7x.c | 4 ++-- src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c | 4 ++-- src/portable/nordic/nrf5x/dcd_nrf5x.c | 6 +++--- src/portable/nuvoton/nuc120/dcd_nuc120.c | 4 ++-- src/portable/nuvoton/nuc121/dcd_nuc121.c | 4 ++-- src/portable/nuvoton/nuc505/dcd_nuc505.c | 4 ++-- src/portable/nxp/khci/dcd_khci.c | 4 ++-- src/portable/nxp/khci/hcd_khci.c | 3 ++- src/portable/nxp/lpc17_40/dcd_lpc17_40.c | 4 ++-- src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 4 ++-- src/portable/ohci/ohci.c | 4 ++-- src/portable/raspberrypi/pio_usb/dcd_pio_usb.c | 3 ++- src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 3 ++- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 4 ++-- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 3 ++- src/portable/renesas/rusb2/dcd_rusb2.c | 4 ++-- src/portable/renesas/rusb2/hcd_rusb2.c | 4 ++-- src/portable/sony/cxd56/dcd_cxd56.c | 4 ++-- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 4 ++-- src/portable/sunxi/dcd_sunxi_musb.c | 4 ++-- src/portable/synopsys/dwc2/dcd_dwc2.c | 4 ++-- src/portable/template/dcd_template.c | 4 ++-- src/portable/template/hcd_template.c | 3 ++- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 7 +++---- src/portable/valentyusb/eptri/dcd_eptri.c | 4 ++-- src/portable/wch/dcd_ch32_usbfs.c | 4 ++-- src/portable/wch/dcd_ch32_usbhs.c | 4 ++-- src/tusb.c | 16 +++++++--------- src/tusb.h | 11 ++++++----- test/fuzz/dcd_fuzz.cc | 3 ++- test/unit-test/test/device/msc/test_msc_device.c | 5 ++--- test/unit-test/test/device/usbd/test_usbd.c | 20 +++++++------------- 89 files changed, 174 insertions(+), 213 deletions(-) (limited to 'src/portable') diff --git a/.github/workflows/pre-commit.yml b/.github/workflows/pre-commit.yml index 379a22ee2..530484079 100644 --- a/.github/workflows/pre-commit.yml +++ b/.github/workflows/pre-commit.yml @@ -29,7 +29,7 @@ jobs: #ceedling test:all - name: Run pre-commit - uses: pre-commit/action@v3.0.0 + uses: pre-commit/action@v3.0.1 - name: Build Fuzzer run: | diff --git a/.idea/cmake.xml b/.idea/cmake.xml index c0b55a82e..05dceda5a 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -2,6 +2,9 @@ + + + @@ -80,7 +83,7 @@ - + @@ -94,11 +97,11 @@ - + - + @@ -109,9 +112,6 @@ - - - @@ -148,6 +148,7 @@ + \ No newline at end of file diff --git a/examples/device/audio_4_channel_mic/src/main.c b/examples/device/audio_4_channel_mic/src/main.c index ca0e67fae..e8c40309e 100644 --- a/examples/device/audio_4_channel_mic/src/main.c +++ b/examples/device/audio_4_channel_mic/src/main.c @@ -87,11 +87,10 @@ int main(void) // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/audio_4_channel_mic_freertos/src/main.c b/examples/device/audio_4_channel_mic_freertos/src/main.c index c1ebc4899..2ac7516cd 100644 --- a/examples/device/audio_4_channel_mic_freertos/src/main.c +++ b/examples/device/audio_4_channel_mic_freertos/src/main.c @@ -210,11 +210,10 @@ void usb_device_task(void* param) // This should be called after scheduler/kernel is started. // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/audio_test/src/main.c b/examples/device/audio_test/src/main.c index f4c1bf95f..018c48994 100644 --- a/examples/device/audio_test/src/main.c +++ b/examples/device/audio_test/src/main.c @@ -80,11 +80,10 @@ int main(void) // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/audio_test_freertos/src/main.c b/examples/device/audio_test_freertos/src/main.c index b7d7dc042..4e2264b5d 100644 --- a/examples/device/audio_test_freertos/src/main.c +++ b/examples/device/audio_test_freertos/src/main.c @@ -157,11 +157,10 @@ void usb_device_task(void* param) // This should be called after scheduler/kernel is started. // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/audio_test_multi_rate/src/main.c b/examples/device/audio_test_multi_rate/src/main.c index a1c4d32db..f9dcd1b8a 100644 --- a/examples/device/audio_test_multi_rate/src/main.c +++ b/examples/device/audio_test_multi_rate/src/main.c @@ -98,11 +98,10 @@ int main(void) // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/cdc_dual_ports/src/main.c b/examples/device/cdc_dual_ports/src/main.c index b446bca0b..63ae8a8c9 100644 --- a/examples/device/cdc_dual_ports/src/main.c +++ b/examples/device/cdc_dual_ports/src/main.c @@ -53,11 +53,10 @@ int main(void) { // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/cdc_msc/src/main.c b/examples/device/cdc_msc/src/main.c index 47ba5a887..f36c910d7 100644 --- a/examples/device/cdc_msc/src/main.c +++ b/examples/device/cdc_msc/src/main.c @@ -52,11 +52,10 @@ int main(void) { // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index a08e063ac..f70267e33 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -133,11 +133,10 @@ static void usb_device_task(void *param) { // This should be called after scheduler/kernel is started. // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/cdc_uac2/src/main.c b/examples/device/cdc_uac2/src/main.c index 384d910ec..b148593da 100644 --- a/examples/device/cdc_uac2/src/main.c +++ b/examples/device/cdc_uac2/src/main.c @@ -47,11 +47,10 @@ int main(void) // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); #if (CFG_TUSB_MCU == OPT_MCU_RP2040) stdio_init_all(); diff --git a/examples/device/dfu/src/main.c b/examples/device/dfu/src/main.c index f2aea7cfc..af9e99857 100644 --- a/examples/device/dfu/src/main.c +++ b/examples/device/dfu/src/main.c @@ -76,11 +76,10 @@ int main(void) // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/dfu_runtime/src/main.c b/examples/device/dfu_runtime/src/main.c index 5d6b907b7..4740c18c4 100644 --- a/examples/device/dfu_runtime/src/main.c +++ b/examples/device/dfu_runtime/src/main.c @@ -71,11 +71,10 @@ int main(void) // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/dynamic_configuration/src/main.c b/examples/device/dynamic_configuration/src/main.c index 143570c5c..32ff58232 100644 --- a/examples/device/dynamic_configuration/src/main.c +++ b/examples/device/dynamic_configuration/src/main.c @@ -58,11 +58,10 @@ int main(void) // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/hid_boot_interface/src/main.c b/examples/device/hid_boot_interface/src/main.c index dfee7421d..570e4e801 100644 --- a/examples/device/hid_boot_interface/src/main.c +++ b/examples/device/hid_boot_interface/src/main.c @@ -58,11 +58,10 @@ int main(void) // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/hid_composite/src/main.c b/examples/device/hid_composite/src/main.c index 56c485982..5302af3b8 100644 --- a/examples/device/hid_composite/src/main.c +++ b/examples/device/hid_composite/src/main.c @@ -59,11 +59,10 @@ int main(void) // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c index fc07a1a39..ae091571e 100644 --- a/examples/device/hid_composite_freertos/src/main.c +++ b/examples/device/hid_composite_freertos/src/main.c @@ -137,11 +137,10 @@ void usb_device_task(void* param) // This should be called after scheduler/kernel is started. // Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API. tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/hid_generic_inout/src/main.c b/examples/device/hid_generic_inout/src/main.c index 1bbcbf7a4..73f51002d 100644 --- a/examples/device/hid_generic_inout/src/main.c +++ b/examples/device/hid_generic_inout/src/main.c @@ -82,11 +82,10 @@ int main(void) // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/hid_multiple_interface/src/main.c b/examples/device/hid_multiple_interface/src/main.c index edcedd3ca..92c7e8332 100644 --- a/examples/device/hid_multiple_interface/src/main.c +++ b/examples/device/hid_multiple_interface/src/main.c @@ -63,11 +63,10 @@ int main(void) // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/midi_test/src/main.c b/examples/device/midi_test/src/main.c index b05307d1b..d7849a2c4 100644 --- a/examples/device/midi_test/src/main.c +++ b/examples/device/midi_test/src/main.c @@ -64,11 +64,10 @@ int main(void) // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/msc_dual_lun/src/main.c b/examples/device/msc_dual_lun/src/main.c index fe3896ca7..012095dca 100644 --- a/examples/device/msc_dual_lun/src/main.c +++ b/examples/device/msc_dual_lun/src/main.c @@ -55,11 +55,10 @@ int main(void) { // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/net_lwip_webserver/src/main.c b/examples/device/net_lwip_webserver/src/main.c index 6041b56e2..8af7a9de6 100644 --- a/examples/device/net_lwip_webserver/src/main.c +++ b/examples/device/net_lwip_webserver/src/main.c @@ -217,11 +217,10 @@ int main(void) { // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/uac2_headset/src/main.c b/examples/device/uac2_headset/src/main.c index 4d28f73a4..6b2ab0973 100644 --- a/examples/device/uac2_headset/src/main.c +++ b/examples/device/uac2_headset/src/main.c @@ -101,11 +101,10 @@ int main(void) // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/uac2_speaker_fb/src/main.c b/examples/device/uac2_speaker_fb/src/main.c index 1250b041d..53bbec9b6 100644 --- a/examples/device/uac2_speaker_fb/src/main.c +++ b/examples/device/uac2_speaker_fb/src/main.c @@ -107,11 +107,10 @@ int main(void) // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/usbtmc/src/main.c b/examples/device/usbtmc/src/main.c index 2af581bc1..aa7902a15 100644 --- a/examples/device/usbtmc/src/main.c +++ b/examples/device/usbtmc/src/main.c @@ -56,11 +56,10 @@ int main(void) // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index c5d87c660..aeeeb8930 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -69,11 +69,10 @@ int main(void) { #else // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); @@ -325,11 +324,10 @@ void usb_device_task(void *param) { // This should be called after scheduler/kernel is started. // Otherwise, it could cause kernel issue since USB IRQ handler does use RTOS queue API. tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/video_capture_2ch/src/main.c b/examples/device/video_capture_2ch/src/main.c index a45e62ab0..dd6983766 100644 --- a/examples/device/video_capture_2ch/src/main.c +++ b/examples/device/video_capture_2ch/src/main.c @@ -69,11 +69,10 @@ int main(void) { #else // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); @@ -333,11 +332,10 @@ void usb_device_task(void *param) { // This should be called after scheduler/kernel is started. // Otherwise, it could cause kernel issue since USB IRQ handler does use RTOS queue API. tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/device/webusb_serial/src/main.c b/examples/device/webusb_serial/src/main.c index 46215ec13..d189af91f 100644 --- a/examples/device/webusb_serial/src/main.c +++ b/examples/device/webusb_serial/src/main.c @@ -92,11 +92,10 @@ int main(void) { // init device stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/dual/host_hid_to_device_cdc/src/main.c b/examples/dual/host_hid_to_device_cdc/src/main.c index 061958aae..633f7a6ac 100644 --- a/examples/dual/host_hid_to_device_cdc/src/main.c +++ b/examples/dual/host_hid_to_device_cdc/src/main.c @@ -80,18 +80,16 @@ int main(void) { // init device and host stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); tusb_rhport_init_t host_init = { - .rhport = BOARD_TUH_RHPORT, .role = TUSB_ROLE_HOST, .speed = TUSB_SPEED_AUTO }; - tusb_init(&host_init); + tusb_init(BOARD_TUH_RHPORT, &host_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/dual/host_info_to_device_cdc/src/main.c b/examples/dual/host_info_to_device_cdc/src/main.c index e4d802a0c..668808db2 100644 --- a/examples/dual/host_info_to_device_cdc/src/main.c +++ b/examples/dual/host_info_to_device_cdc/src/main.c @@ -83,18 +83,16 @@ int main(void) { // init device and host stack on configured roothub port tusb_rhport_init_t dev_init = { - .rhport = BOARD_TUD_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - tusb_init(&dev_init); + tusb_init(BOARD_TUD_RHPORT, &dev_init); tusb_rhport_init_t host_init = { - .rhport = BOARD_TUH_RHPORT, .role = TUSB_ROLE_HOST, .speed = TUSB_SPEED_AUTO }; - tusb_init(&host_init); + tusb_init(BOARD_TUH_RHPORT, &host_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c index e710e3caa..f582f4f5a 100644 --- a/examples/host/bare_api/src/main.c +++ b/examples/host/bare_api/src/main.c @@ -63,11 +63,10 @@ int main(void) // init host stack on configured roothub port tusb_rhport_init_t host_init = { - .rhport = BOARD_TUH_RHPORT, .role = TUSB_ROLE_HOST, .speed = TUSB_SPEED_AUTO }; - tusb_init(&host_init); + tusb_init(BOARD_TUH_RHPORT, &host_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/host/cdc_msc_hid/src/main.c b/examples/host/cdc_msc_hid/src/main.c index 3a6e762b7..71257c0fe 100644 --- a/examples/host/cdc_msc_hid/src/main.c +++ b/examples/host/cdc_msc_hid/src/main.c @@ -51,11 +51,10 @@ int main(void) { // init host stack on configured roothub port tusb_rhport_init_t host_init = { - .rhport = BOARD_TUH_RHPORT, .role = TUSB_ROLE_HOST, .speed = TUSB_SPEED_AUTO }; - tusb_init(&host_init); + tusb_init(BOARD_TUH_RHPORT, &host_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c index 9d2f347c3..7fb84a40f 100644 --- a/examples/host/cdc_msc_hid_freertos/src/main.c +++ b/examples/host/cdc_msc_hid_freertos/src/main.c @@ -127,12 +127,11 @@ static void usb_host_task(void *param) { // init host stack on configured roothub port tusb_rhport_init_t host_init = { - .rhport = BOARD_TUH_RHPORT, .role = TUSB_ROLE_HOST, .speed = TUSB_SPEED_AUTO }; - if (!tusb_init(&host_init)) { + if (!tusb_init(BOARD_TUH_RHPORT, &host_init)) { printf("Failed to init USB Host Stack\r\n"); vTaskSuspend(NULL); } diff --git a/examples/host/device_info/src/main.c b/examples/host/device_info/src/main.c index 8ca3d8a3a..0ff4f32e9 100644 --- a/examples/host/device_info/src/main.c +++ b/examples/host/device_info/src/main.c @@ -67,11 +67,10 @@ int main(void) { // init host stack on configured roothub port tusb_rhport_init_t host_init = { - .rhport = BOARD_TUH_RHPORT, .role = TUSB_ROLE_HOST, .speed = TUSB_SPEED_AUTO }; - tusb_init(&host_init); + tusb_init(BOARD_TUH_RHPORT, &host_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/host/hid_controller/src/main.c b/examples/host/hid_controller/src/main.c index 6db47792c..ba12774bd 100644 --- a/examples/host/hid_controller/src/main.c +++ b/examples/host/hid_controller/src/main.c @@ -53,11 +53,10 @@ int main(void) // init host stack on configured roothub port tusb_rhport_init_t host_init = { - .rhport = BOARD_TUH_RHPORT, .role = TUSB_ROLE_HOST, .speed = TUSB_SPEED_AUTO }; - tusb_init(&host_init); + tusb_init(BOARD_TUH_RHPORT, &host_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c index 11512ab65..9509035b4 100644 --- a/examples/host/msc_file_explorer/src/main.c +++ b/examples/host/msc_file_explorer/src/main.c @@ -79,11 +79,10 @@ int main(void) { // init host stack on configured roothub port tusb_rhport_init_t host_init = { - .rhport = BOARD_TUH_RHPORT, .role = TUSB_ROLE_HOST, .speed = TUSB_SPEED_AUTO }; - tusb_init(&host_init); + tusb_init(BOARD_TUH_RHPORT, &host_init); if (board_init_after_tusb) { board_init_after_tusb(); diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index c544a09fe..70dbb5b9e 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -707,7 +707,7 @@ static bool _open_vc_itf(uint8_t rhport, videod_interface_t *self, uint_fast8_t /* The first descriptor is a video control interface descriptor. */ uint8_t const *cur = _find_desc_itf(beg, end, _desc_itfnum(beg), altnum); - TU_LOG_DRV(" cur %d\r\n", cur - beg); + TU_LOG_DRV(" cur %" PRId32 "\r\n", (int32_t) (cur - beg)); TU_VERIFY(cur < end); tusb_desc_vc_itf_t const *vc = (tusb_desc_vc_itf_t const *)cur; diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 5dfe3ff98..53bb367cb 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -278,7 +278,6 @@ enum { // //--------------------------------------------------------------------+ typedef struct { - uint8_t rhport; tusb_role_t role; tusb_speed_t speed; } tusb_rhport_init_t; diff --git a/src/device/dcd.h b/src/device/dcd.h index 02f3847ff..64dffbaef 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -108,7 +108,7 @@ void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_W //--------------------------------------------------------------------+ // Initialize controller to device mode -void dcd_init(const tusb_rhport_init_t* rh_init); +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init); // Deinitialize controller, unset device mode. bool dcd_deinit(uint8_t rhport); diff --git a/src/device/usbd.c b/src/device/usbd.c index 12f95ab40..4b6600eb2 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -448,7 +448,7 @@ bool tud_inited(void) { return _usbd_rhport != RHPORT_INVALID; } -bool tud_rhport_init(const tusb_rhport_init_t* rh_init) { +bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { if (tud_inited()) { return true; // skip if already initialized } @@ -487,11 +487,11 @@ bool tud_rhport_init(const tusb_rhport_init_t* rh_init) { driver->init(); } - _usbd_rhport = rh_init->rhport; + _usbd_rhport = rhport; // Init device controller driver - dcd_init(rh_init); - dcd_int_enable(rh_init->rhport); + dcd_init(rhport, rh_init); + dcd_int_enable(rhport); return true; } diff --git a/src/device/usbd.h b/src/device/usbd.h index 05eb0173f..de6007fb3 100644 --- a/src/device/usbd.h +++ b/src/device/usbd.h @@ -38,19 +38,18 @@ extern "C" { //--------------------------------------------------------------------+ // New API to replace tud_init() to init device stack on specific roothub port -bool tud_rhport_init(const tusb_rhport_init_t* rh_init); +bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init); // Init device stack on roothub port #if TUSB_VERSION_NUMBER > 2000 // 0.20.0 -TU_ATTR_DEPRECATED("Please use tusb_init(tusb_rhport_init_t*) instead") +TU_ATTR_DEPRECATED("Please use tusb_init(rhport, rh_init) instead") #endif TU_ATTR_ALWAYS_INLINE static inline bool tud_init (uint8_t rhport) { const tusb_rhport_init_t rh_init = { - .rhport = rhport, .role = TUSB_ROLE_DEVICE, .speed = TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL }; - return tud_rhport_init(&rh_init); + return tud_rhport_init(rhport, &rh_init); } // Deinit device stack on roothub port diff --git a/src/host/hcd.h b/src/host/hcd.h index 97cb01754..6518e6fd2 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -121,7 +121,7 @@ bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_W bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param); // Initialize controller to host mode -bool hcd_init(const tusb_rhport_init_t* rh_init); +bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init); // De-initialize controller bool hcd_deinit(uint8_t rhport); diff --git a/src/host/usbh.c b/src/host/usbh.c index f9e6c4e97..b5df29f50 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -352,8 +352,8 @@ bool tuh_inited(void) { return _usbh_controller != TUSB_INDEX_INVALID_8; } -bool tuh_rhport_init(const tusb_rhport_init_t* rh_init) { - if (tuh_rhport_is_active(rh_init->rhport)) { +bool tuh_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + if (tuh_rhport_is_active(rhport)) { return true; // skip if already initialized } @@ -404,9 +404,9 @@ bool tuh_rhport_init(const tusb_rhport_init_t* rh_init) { } // Init host controller - _usbh_controller = rh_init->rhport; - TU_ASSERT(hcd_init(rh_init)); - hcd_int_enable(rh_init->rhport); + _usbh_controller = rhport; + TU_ASSERT(hcd_init(rhport, rh_init)); + hcd_int_enable(rhport); return true; } diff --git a/src/host/usbh.h b/src/host/usbh.h index 9b865ac1b..20fad284e 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -121,19 +121,18 @@ void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr); bool tuh_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param); // New API to replace tuh_init() to init host stack on specific roothub port -bool tuh_rhport_init(const tusb_rhport_init_t* rh_init); +bool tuh_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init); // Init host stack #if TUSB_VERSION_NUMBER > 2000 // 0.20.0 -TU_ATTR_DEPRECATED("Please use tusb_init(tusb_rhport_init_t*) instead") +TU_ATTR_DEPRECATED("Please use tusb_init(rhport, rh_init) instead") #endif TU_ATTR_ALWAYS_INLINE static inline bool tuh_init(uint8_t rhport) { const tusb_rhport_init_t rh_init = { - .rhport = rhport, .role = TUSB_ROLE_HOST, .speed = TUH_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL, }; - return tuh_rhport_init(&rh_init); + return tuh_rhport_init(rhport, &rh_init); } // Deinit host stack on rhport diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 30d822c3b..c5e924266 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -494,8 +494,8 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { } // Initialize controller to host mode -bool hcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; tuh_max3421_int_api(rhport, false); diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c index f4b236da6..4e7b28825 100644 --- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c +++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c @@ -517,8 +517,8 @@ static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t len *------------------------------------------------------------------*/ // Initialize controller to device mode -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; TU_LOG2("FT9xx initialisation\r\n"); _dcd_ft9xx_attach(); diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c index 315e9a86d..6038160cf 100644 --- a/src/portable/chipidea/ci_fs/dcd_ci_fs.c +++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c @@ -267,9 +267,9 @@ static void process_bus_resume(uint8_t rhport) /*------------------------------------------------------------------*/ /* Device API *------------------------------------------------------------------*/ -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; + (void) rh_init; // save crystal-less setting (if available) #if defined(FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED == 1 diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index bdb7abe41..5204dee66 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -234,8 +234,8 @@ static void bus_reset(uint8_t rhport) dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); } -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; tu_memclr(&_dcd_data, sizeof(dcd_data_t)); ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index fbc51f6df..14f8acb45 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -70,8 +70,8 @@ bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { // Controller API //--------------------------------------------------------------------+ -bool hcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; ci_hs_regs_t *hcd_reg = CI_HS_REG(rhport); // Reset controller @@ -83,7 +83,9 @@ bool hcd_init(const tusb_rhport_init_t* rh_init) { // LPC18XX/43XX need to set VBUS Power Select to HIGH // RHPORT1 is fullspeed only (need external PHY for Highspeed) hcd_reg->USBMODE = USBMODE_CM_HOST | USBMODE_VBUS_POWER_SELECT; - if ( rhport == 1 ) hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED; + if (rhport == 1) { + hcd_reg->PORTSC1 |= PORTSC1_FORCE_FULL_SPEED; + } #else hcd_reg->USBMODE = USBMODE_CM_HOST; #endif diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index 05cebea0b..558e1269a 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -804,9 +804,9 @@ static void handle_ep0_nak(void) /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; + (void) rh_init; _dcd.init_called = true; if (_dcd.vbus_present) diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c index 3d4757f03..d233813d4 100644 --- a/src/portable/espressif/esp32sx/dcd_esp32sx.c +++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c @@ -172,8 +172,8 @@ static void enum_done_processing(void) /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; ESP_LOGV(TAG, "DCD init - Start"); // A. Disconnect diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index a8437ad5b..02c8da1e0 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -582,8 +582,8 @@ void print_musb_info(musb_regs_t* musb_regs) { } #endif -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; musb_regs_t* musb_regs = MUSB_REGS(rhport); #if CFG_TUSB_DEBUG >= MUSB_DEBUG diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c index 9324c6a34..1c0740193 100644 --- a/src/portable/mentor/musb/hcd_musb.c +++ b/src/portable/mentor/musb/hcd_musb.c @@ -556,7 +556,8 @@ static void process_pipe_rx(uint8_t rhport, uint_fast8_t pipenum) * Host API *------------------------------------------------------------------*/ -bool hcd_init(const tusb_rhport_init_t* rh_init) { +bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rhport; (void) rh_init; NVIC_ClearPendingIRQ(USB0_IRQn); diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c index 3ee0ab6d5..089d3f520 100644 --- a/src/portable/microchip/pic/dcd_pic.c +++ b/src/portable/microchip/pic/dcd_pic.c @@ -470,8 +470,8 @@ static void process_bus_resume(uint8_t rhport) /*------------------------------------------------------------------*/ /* Device API *------------------------------------------------------------------*/ -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; intr_disable(rhport); intr_clear(rhport); diff --git a/src/portable/microchip/pic32mz/dcd_pic32mz.c b/src/portable/microchip/pic32mz/dcd_pic32mz.c index 004990046..f1614f30c 100644 --- a/src/portable/microchip/pic32mz/dcd_pic32mz.c +++ b/src/portable/microchip/pic32mz/dcd_pic32mz.c @@ -120,8 +120,8 @@ static ep0_stage_t ep0_get_stage(void) /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; // Disable endpoint interrupts for now USB_REGS->INTRRXEbits.w = 0; USB_REGS->INTRTXEbits.w = 0; diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c index c3a74ad0f..8120681a7 100644 --- a/src/portable/microchip/samd/dcd_samd.c +++ b/src/portable/microchip/samd/dcd_samd.c @@ -78,8 +78,8 @@ static void bus_reset(void) /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ -void dcd_init(const tusb_rhport_init_t* rh_init) { - (void) rh_init; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rhport; (void) rh_init; // Reset to get in a clean state. USB->DEVICE.CTRLA.bit.SWRST = true; diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c index 2242d3336..b02889b24 100644 --- a/src/portable/microchip/samg/dcd_samg.c +++ b/src/portable/microchip/samg/dcd_samg.c @@ -155,8 +155,9 @@ static void bus_reset(void) } // Initialize controller to device mode -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rhport; + (void) rh_init; tu_memclr(_dcd_xfer, sizeof(_dcd_xfer)); dcd_connect(rhport); } diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c index d57db6e55..a85d2306e 100644 --- a/src/portable/microchip/samx7x/dcd_samx7x.c +++ b/src/portable/microchip/samx7x/dcd_samx7x.c @@ -104,8 +104,8 @@ TU_ATTR_ALWAYS_INLINE static inline void CleanInValidateCache(uint32_t *addr, in //------------------------------------------------------------------ // Initialize controller to device mode -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; dcd_connect(rhport); } diff --git a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c index 4117ab45f..b74ca847a 100644 --- a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c +++ b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c @@ -245,9 +245,9 @@ static void process_bus_active(uint8_t rhport) /*------------------------------------------------------------------*/ /* Device API *------------------------------------------------------------------*/ -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; + (void) rh_init; tu_memclr(&_dcd, sizeof(_dcd)); USB_OTG_FS->BDT_PAGE_01 = (uint8_t)((uintptr_t)_dcd.bdt >> 8); diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index c1084c20c..06474e65d 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -230,10 +230,10 @@ static void xact_in_dma(uint8_t epnum) { //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; - TU_LOG2("dcd init\r\n"); +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; + (void) rh_init; + TU_LOG2("dcd init\r\n"); } void dcd_int_enable(uint8_t rhport) { diff --git a/src/portable/nuvoton/nuc120/dcd_nuc120.c b/src/portable/nuvoton/nuc120/dcd_nuc120.c index c9e8d86fd..89fca021f 100644 --- a/src/portable/nuvoton/nuc120/dcd_nuc120.c +++ b/src/portable/nuvoton/nuc120/dcd_nuc120.c @@ -201,9 +201,9 @@ static const uint32_t enabled_irqs = USBD_INTSTS_FLDET_STS_Msk | USBD_INTSTS_BUS NUC100/NUC120 TinyUSB API driver implementation */ -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; + (void) rh_init; USBD->ATTR = 0x7D0; diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c index 78c65a91c..b813eea77 100644 --- a/src/portable/nuvoton/nuc121/dcd_nuc121.c +++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c @@ -209,9 +209,9 @@ enum { NUC121/NUC125/NUC126 TinyUSB API driver implementation */ -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; + (void) rh_init; #ifdef SUPPORT_LPM USBD->ATTR = 0x7D0 | USBD_LPMACK; diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c index caeb89a0a..3821b6ec8 100644 --- a/src/portable/nuvoton/nuc505/dcd_nuc505.c +++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c @@ -279,9 +279,9 @@ static const uint32_t enabled_irqs = USBD_GINTEN_USBIEN_Msk | \ NUC505 TinyUSB API driver implementation */ -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; + (void) rh_init; /* configure interrupts in their initial state; BUSINTEN and CEPINTEN will be subsequently and dynamically re-written as needed */ USBD->GINTEN = enabled_irqs; diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 2d08e84a5..1b7f56e8c 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -265,9 +265,9 @@ static void process_bus_resume(uint8_t rhport) /*------------------------------------------------------------------*/ /* Device API *------------------------------------------------------------------*/ -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; + (void) rh_init; // save crystal-less setting (if available) #if defined(FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED) && FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED == 1 diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c index e9c00b8f9..f5ca73c18 100644 --- a/src/portable/nxp/khci/hcd_khci.c +++ b/src/portable/nxp/khci/hcd_khci.c @@ -368,7 +368,8 @@ static void process_bus_reset(uint8_t rhport) /*------------------------------------------------------------------*/ /* Host API *------------------------------------------------------------------*/ -bool hcd_init(const tusb_rhport_init_t* rh_init) { +bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rhport; (void) rh_init; KHCI->USBTRC0 |= USB_USBTRC0_USBRESET_MASK; while (KHCI->USBTRC0 & USB_USBTRC0_USBRESET_MASK); diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c index e28b27919..22b4500c5 100644 --- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c +++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c @@ -167,9 +167,9 @@ static void bus_reset(void) tu_memclr(&_dcd, sizeof(dcd_data_t)); } -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; + (void) rh_init; //------------- user manual 11.13 usb device controller initialization -------------// // step 6 : set up control endpoint diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c index 06a82c4e7..e59a0f526 100644 --- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c +++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c @@ -289,8 +289,8 @@ static void edpt_reset_all(uint8_t rhport) } prepare_setup_packet(rhport); } -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; edpt_reset_all(rhport); dcd_registers_t* dcd_reg = _dcd_controller[rhport].regs; diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index fbaa5208e..ce35eab70 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -178,9 +178,9 @@ TU_ATTR_ALWAYS_INLINE static inline void *_virt_addr(void *physical_address) } // Initialization according to 5.1.1.4 -bool hcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; + (void) rh_init; //------------- Data Structure init -------------// tu_memclr(&ohci_data, sizeof(ohci_data_t)); diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c index 83589efa0..89d60a21e 100644 --- a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c @@ -50,7 +50,8 @@ static usb_descriptor_buffers_t desc; *------------------------------------------------------------------*/ // Initialize controller to device mode -void dcd_init(const tusb_rhport_init_t* rh_init) { +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rhport; (void) rh_init; static pio_usb_configuration_t config = PIO_USB_DEFAULT_CONFIG; usb_device = pio_usb_device_init(&config, &desc); diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c index 4386bbce4..6422afff1 100644 --- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c @@ -55,7 +55,8 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void *cfg_param) { return true; } -bool hcd_init(const tusb_rhport_init_t* rh_init) { +bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rhport; (void) rh_init; // To run USB SOF interrupt in core1, call this init in core1 diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 9473d3bd8..9a945caf8 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -369,8 +369,8 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) { #define PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY 0xff #endif -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; assert(rhport == 0); TU_LOG(2, "Chip Version B%u\r\n", rp2040_chip_version()); diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index a870418a8..2c0a3fd49 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -375,7 +375,8 @@ static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t //--------------------------------------------------------------------+ // HCD API //--------------------------------------------------------------------+ -bool hcd_init(const tusb_rhport_init_t* rh_init) { +bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rhport; (void) rh_init; pico_trace("hcd_init %d\n", rhport); assert(rhport == 0); diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index e8e1bf041..3da4ef50b 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -657,8 +657,8 @@ static void enable_interrupt(uint32_t pswi) } #endif -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; rusb2_reg_t* rusb = RUSB2_REG(rhport); rusb2_module_start(rhport, true); diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 35e85a3b0..4c81b05be 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -466,8 +466,8 @@ static void enable_interrupt(uint32_t pswi) } #endif -bool hcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; rusb2_reg_t* rusb = RUSB2_REG(rhport); rusb2_module_start(rhport, true); diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c index fe1c42249..93eb8674e 100644 --- a/src/portable/sony/cxd56/dcd_cxd56.c +++ b/src/portable/sony/cxd56/dcd_cxd56.c @@ -201,9 +201,9 @@ static void _dcd_resume(FAR struct usbdevclass_driver_s *driver, FAR struct usbd dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); } -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; + (void) rh_init; usbdcd_driver.usbdevclass_driver.speed = USB_SPEED_HIGH; usbdcd_driver.usbdevclass_driver.ops = &g_driverops; diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index 8e9bb0b30..a4bd2da10 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -184,8 +184,8 @@ TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t *xfer_ctl_ptr(uint8_t epnum, uint //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; // Follow the RM mentions to use a special ordering of PDWN and FRES for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us asm("NOP"); diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c index d7bf1068a..85c7bef5d 100644 --- a/src/portable/sunxi/dcd_sunxi_musb.c +++ b/src/portable/sunxi/dcd_sunxi_musb.c @@ -867,8 +867,8 @@ static void usb_isr_handler(void) { dcd_int_handler(0); } -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; dcd_disconnect(rhport); USBC_HardwareReset(); USBC_PhyConfig(); diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 580960e24..e44ca96d1 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -650,10 +650,10 @@ static bool check_dwc2(dwc2_regs_t* dwc2) { return true; } -void dcd_init(const tusb_rhport_init_t* rh_init) { +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rhport; (void) rh_init; // Programming model begins in the last section of the chapter on the USB // peripheral in each Reference Manual. - const uint8_t rhport = rh_init->rhport; dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Check Synopsys ID register, failed if controller clock/power is not enabled diff --git a/src/portable/template/dcd_template.c b/src/portable/template/dcd_template.c index 56a89e89a..5ce650844 100644 --- a/src/portable/template/dcd_template.c +++ b/src/portable/template/dcd_template.c @@ -40,8 +40,8 @@ *------------------------------------------------------------------*/ // Initialize controller to device mode -void dcd_init(const tusb_rhport_init_t* rh_init) { - (void) rh_init; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rhport; (void) rh_init; } // Enable device interrupt diff --git a/src/portable/template/hcd_template.c b/src/portable/template/hcd_template.c index 9386e95cc..d8bca196f 100644 --- a/src/portable/template/hcd_template.c +++ b/src/portable/template/hcd_template.c @@ -44,7 +44,8 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { } // Initialize controller to host mode -bool hcd_init(const tusb_rhport_init_t* rh_init) { +bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rhport; (void) rh_init; return false; } diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 120d5c4b9..6150c254f 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -130,8 +130,8 @@ static void enable_functional_reset(const bool enable) /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ -void dcd_init(const tusb_rhport_init_t* rh_init) { - (void) rh_init; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rhport; (void) rh_init; USBKEYPID = USBKEY; @@ -699,11 +699,10 @@ static void handle_bus_power_event(void *param) { // A successful lock is indicated by all PLL-related interrupt flags being cleared. if(!USBPLLIR) { const tusb_rhport_init_t rhport_init = { - .rhport = 0, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_FULL }; - dcd_init(&rhport_init); // Re-initialize the USB module. + dcd_init(0, &rhport_init); // Re-initialize the USB module. } } else { // Event caused by removal of bus power. USBPWRCTL |= VBONIE; // Enable bus-power-applied interrupt. diff --git a/src/portable/valentyusb/eptri/dcd_eptri.c b/src/portable/valentyusb/eptri/dcd_eptri.c index da7a5a81a..8287230a4 100644 --- a/src/portable/valentyusb/eptri/dcd_eptri.c +++ b/src/portable/valentyusb/eptri/dcd_eptri.c @@ -336,9 +336,9 @@ static void dcd_reset(void) } // Initializes the USB peripheral for device mode and enables it. -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; + (void) rh_init; usb_pullup_out_write(0); diff --git a/src/portable/wch/dcd_ch32_usbfs.c b/src/portable/wch/dcd_ch32_usbfs.c index 4a7ad704b..9af3a1acb 100644 --- a/src/portable/wch/dcd_ch32_usbfs.c +++ b/src/portable/wch/dcd_ch32_usbfs.c @@ -123,8 +123,8 @@ static void update_out(uint8_t rhport, uint8_t ep, size_t rx_len) { } /* public functions */ -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; // init registers USBOTG_FS->BASE_CTRL = USBFS_CTRL_SYS_CTRL | USBFS_CTRL_INT_BUSY | USBFS_CTRL_DMA_EN; USBOTG_FS->UDEV_CTRL = USBFS_UDEV_CTRL_PD_DIS | USBFS_UDEV_CTRL_PORT_EN; diff --git a/src/portable/wch/dcd_ch32_usbhs.c b/src/portable/wch/dcd_ch32_usbhs.c index 77ebc378c..64a88914f 100644 --- a/src/portable/wch/dcd_ch32_usbhs.c +++ b/src/portable/wch/dcd_ch32_usbhs.c @@ -131,9 +131,9 @@ static void xfer_data_packet(uint8_t ep_num, tusb_dir_t ep_dir, xfer_ctl_t* xfer ep_set_response_and_toggle(ep_num, ep_dir, USBHS_EP_R_RES_ACK); } -void dcd_init(const tusb_rhport_init_t* rh_init) { - const uint8_t rhport = rh_init->rhport; +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; + (void) rh_init; memset(&xfer_status, 0, sizeof(xfer_status)); diff --git a/src/tusb.c b/src/tusb.c index 3eb299dff..e6f8055b7 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -47,29 +47,27 @@ static tusb_role_t _rhport_role[TUP_USBIP_CONTROLLER_NUM] = { 0 }; // Public API //--------------------------------------------------------------------+ -bool tusb_rhport_init(const tusb_rhport_init_t* rh_init) { +bool tusb_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // backward compatible called with tusb_init(void) #if defined(TUD_OPT_RHPORT) || defined(TUH_OPT_RHPORT) if (rh_init == NULL) { #if CFG_TUD_ENABLED && defined(TUD_OPT_RHPORT) // init device stack CFG_TUSB_RHPORTx_MODE must be defined const tusb_rhport_init_t dev_init = { - .rhport = TUD_OPT_RHPORT, .role = TUSB_ROLE_DEVICE, .speed = TUD_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL }; - TU_ASSERT ( tud_rhport_init(&dev_init) ); + TU_ASSERT ( tud_rhport_init(rhport, &dev_init) ); _rhport_role[TUD_OPT_RHPORT] = TUSB_ROLE_DEVICE; #endif #if CFG_TUH_ENABLED && defined(TUH_OPT_RHPORT) // init host stack CFG_TUSB_RHPORTx_MODE must be defined const tusb_rhport_init_t host_init = { - .rhport = TUH_OPT_RHPORT, .role = TUSB_ROLE_HOST, .speed = TUH_OPT_HIGH_SPEED ? TUSB_SPEED_HIGH : TUSB_SPEED_FULL }; - TU_ASSERT( tuh_rhport_init(&host_init) ); + TU_ASSERT( tuh_rhport_init(TUH_OPT_RHPORT, &host_init) ); _rhport_role[TUH_OPT_RHPORT] = TUSB_ROLE_HOST; #endif @@ -78,21 +76,21 @@ bool tusb_rhport_init(const tusb_rhport_init_t* rh_init) { #endif // new API with explicit rhport and role - TU_ASSERT(rh_init->rhport < TUP_USBIP_CONTROLLER_NUM && rh_init->role != TUSB_ROLE_INVALID); + TU_ASSERT(rhport < TUP_USBIP_CONTROLLER_NUM && rh_init->role != TUSB_ROLE_INVALID); #if CFG_TUD_ENABLED if (rh_init->role == TUSB_ROLE_DEVICE) { - TU_ASSERT( tud_rhport_init(rh_init) ); + TU_ASSERT(tud_rhport_init(rhport, rh_init)); } #endif #if CFG_TUH_ENABLED if (rh_init->role == TUSB_ROLE_HOST) { - TU_ASSERT( tuh_rhport_init(rh_init) ); + TU_ASSERT(tuh_rhport_init(rhport, rh_init)); } #endif - _rhport_role[rh_init->rhport] = rh_init->role; + _rhport_role[rhport] = rh_init->role; return true; } diff --git a/src/tusb.h b/src/tusb.h index c12abba8b..2f30a5739 100644 --- a/src/tusb.h +++ b/src/tusb.h @@ -134,20 +134,21 @@ #if CFG_TUH_ENABLED || CFG_TUD_ENABLED // Internal helper for backward compatible with tusb_init(void) -bool tusb_rhport_init(const tusb_rhport_init_t* rh_init); +bool tusb_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init); // Initialize roothub port with device/host role // Note: when using with RTOS, this should be called after scheduler/kernel is started. // Otherwise, it could cause kernel issue since USB IRQ handler does use RTOS queue API. // Note2: defined as macro for backward compatible with tusb_init(void), can be changed to function in the future. #if defined(TUD_OPT_RHPORT) || defined(TUH_OPT_RHPORT) -#define _tusb_init_arg0() tusb_rhport_init(NULL) + #define _tusb_init_arg0() tusb_rhport_init(0, NULL) #else -#define _tusb_init_arg0() TU_VERIFY_STATIC(false, "CFG_TUSB_RHPORT0_MODE/CFG_TUSB_RHPORT1_MODE must be defined") + #define _tusb_init_arg0() TU_VERIFY_STATIC(false, "CFG_TUSB_RHPORT0_MODE/CFG_TUSB_RHPORT1_MODE must be defined") #endif -#define _tusb_init_arg1(_rh_init) tusb_rhport_init(_rh_init) -#define tusb_init(...) TU_FUNC_OPTIONAL_ARG(_tusb_init, __VA_ARGS__) +#define _tusb_init_arg1(_rhport) _tusb_init_arg0() +#define _tusb_init_arg2(_rhport, _rh_init) tusb_rhport_init(_rhport, _rh_init) +#define tusb_init(...) TU_FUNC_OPTIONAL_ARG(_tusb_init, __VA_ARGS__) // Check if stack is initialized bool tusb_inited(void); diff --git a/test/fuzz/dcd_fuzz.cc b/test/fuzz/dcd_fuzz.cc index 7ef0c7446..e76ae5087 100644 --- a/test/fuzz/dcd_fuzz.cc +++ b/test/fuzz/dcd_fuzz.cc @@ -46,7 +46,8 @@ tu_static State state = {false, 0, 0}; // All no-ops as we are fuzzing. //--------------------------------------------------------------------+ extern "C" { -void dcd_init(const tusb_rhport_init_t* rh_init) { +void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + UNUSED(rhport); UNUSED(rh_init); return; } diff --git a/test/unit-test/test/device/msc/test_msc_device.c b/test/unit-test/test/device/msc/test_msc_device.c index 4033bf158..60fcdb41c 100644 --- a/test/unit-test/test/device/msc/test_msc_device.c +++ b/test/unit-test/test/device/msc/test_msc_device.c @@ -199,13 +199,12 @@ void setUp(void) if ( !tud_inited() ) { tusb_rhport_init_t dev_init = { - .rhport = 0, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; - dcd_init_Expect(&dev_init); - tusb_init(&dev_init); + dcd_init_Expect(0, &dev_init); + tusb_init(0, &dev_init); } dcd_event_bus_reset(rhport, TUSB_SPEED_HIGH, false); diff --git a/test/unit-test/test/device/usbd/test_usbd.c b/test/unit-test/test/device/usbd/test_usbd.c index 8f900f656..598dac641 100644 --- a/test/unit-test/test/device/usbd/test_usbd.c +++ b/test/unit-test/test/device/usbd/test_usbd.c @@ -102,44 +102,38 @@ uint8_t const* desc_configuration; //--------------------------------------------------------------------+ // //--------------------------------------------------------------------+ -uint8_t const * tud_descriptor_device_cb(void) -{ +uint8_t const * tud_descriptor_device_cb(void) { return desc_device; } -uint8_t const * tud_descriptor_configuration_cb(uint8_t index) -{ +uint8_t const * tud_descriptor_configuration_cb(uint8_t index) { return desc_configuration; } -uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) -{ +uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid) { (void) langid; return NULL; } -void setUp(void) -{ +void setUp(void) { dcd_int_disable_Ignore(); dcd_int_enable_Ignore(); if ( !tud_inited() ) { tusb_rhport_init_t dev_init = { - .rhport = 0, .role = TUSB_ROLE_DEVICE, .speed = TUSB_SPEED_AUTO }; mscd_init_Expect(); - dcd_init_Expect(&dev_init); + dcd_init_Expect(0, &dev_init); - tusb_init(&dev_init); + tusb_init(0, &dev_init); } } -void tearDown(void) -{ +void tearDown(void) { } //--------------------------------------------------------------------+ -- cgit v1.3.1 From e83e08343afca86b2bacf26822ef9032571e6f56 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 14 Oct 2024 19:42:22 +0700 Subject: change dcd_init() return from void to bool --- src/device/dcd.h | 2 +- src/device/usbd.c | 9 +++++---- src/portable/bridgetek/ft9xx/dcd_ft9xx.c | 3 ++- src/portable/chipidea/ci_fs/dcd_ci_fs.c | 3 ++- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 6 ++++-- src/portable/dialog/da146xx/dcd_da146xx.c | 7 ++++--- src/portable/espressif/esp32sx/dcd_esp32sx.c | 3 ++- src/portable/mentor/musb/dcd_musb.c | 3 ++- src/portable/microchip/pic/dcd_pic.c | 3 ++- src/portable/microchip/pic32mz/dcd_pic32mz.c | 3 ++- src/portable/microchip/samd/dcd_samd.c | 7 +++++-- src/portable/microchip/samg/dcd_samg.c | 4 +++- src/portable/microchip/samx7x/dcd_samx7x.c | 3 ++- src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c | 3 ++- src/portable/nordic/nrf5x/dcd_nrf5x.c | 3 ++- src/portable/nuvoton/nuc120/dcd_nuc120.c | 4 +++- src/portable/nuvoton/nuc121/dcd_nuc121.c | 4 +++- src/portable/nuvoton/nuc505/dcd_nuc505.c | 4 +++- src/portable/nxp/khci/dcd_khci.c | 4 +++- src/portable/nxp/lpc17_40/dcd_lpc17_40.c | 4 +++- src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 4 +++- src/portable/raspberrypi/pio_usb/dcd_pio_usb.c | 4 +++- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 3 ++- src/portable/renesas/rusb2/dcd_rusb2.c | 10 ++++++---- src/portable/sony/cxd56/dcd_cxd56.c | 4 +++- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 4 +++- src/portable/sunxi/dcd_sunxi_musb.c | 5 ++++- src/portable/synopsys/dwc2/dcd_dwc2.c | 9 ++++++--- src/portable/template/dcd_template.c | 3 ++- src/portable/ti/msp430x5xx/dcd_msp430x5xx.c | 4 +++- src/portable/valentyusb/eptri/dcd_eptri.c | 4 +++- src/portable/wch/dcd_ch32_usbfs.c | 4 +++- src/portable/wch/dcd_ch32_usbhs.c | 4 +++- test/fuzz/dcd_fuzz.cc | 4 ++-- test/unit-test/test/device/msc/test_msc_device.c | 2 +- test/unit-test/test/device/usbd/test_usbd.c | 2 +- 36 files changed, 103 insertions(+), 49 deletions(-) (limited to 'src/portable') diff --git a/src/device/dcd.h b/src/device/dcd.h index 64dffbaef..d01f82e01 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -108,7 +108,7 @@ void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_W //--------------------------------------------------------------------+ // Initialize controller to device mode -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init); +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init); // Deinitialize controller, unset device mode. bool dcd_deinit(uint8_t rhport); diff --git a/src/device/usbd.c b/src/device/usbd.c index 4b6600eb2..a730b745b 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -454,7 +454,7 @@ bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { } TU_ASSERT(rh_init); - TU_LOG_USBD("USBD init on controller %u, speed = %s\r\n", rh_init->rhport, + TU_LOG_USBD("USBD init on controller %u, speed = %s\r\n", rhport, rh_init->speed == TUSB_SPEED_HIGH ? "High" : "Full"); TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(usbd_device_t)); TU_LOG_INT(CFG_TUD_LOG_LEVEL, sizeof(dcd_event_t)); @@ -490,15 +490,16 @@ bool tud_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { _usbd_rhport = rhport; // Init device controller driver - dcd_init(rhport, rh_init); + TU_ASSERT(dcd_init(rhport, rh_init)); dcd_int_enable(rhport); return true; } bool tud_deinit(uint8_t rhport) { - // skip if not initialized - if (!tud_inited()) return true; + if (!tud_inited()) { + return true; // skip if not initialized + } TU_LOG_USBD("USBD deinit on controller %u\r\n", rhport); diff --git a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c index 4e7b28825..34a8be3b6 100644 --- a/src/portable/bridgetek/ft9xx/dcd_ft9xx.c +++ b/src/portable/bridgetek/ft9xx/dcd_ft9xx.c @@ -517,7 +517,7 @@ static uint16_t _ft9xx_dusb_out(uint8_t ep_number, uint8_t *buffer, uint16_t len *------------------------------------------------------------------*/ // Initialize controller to device mode -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; TU_LOG2("FT9xx initialisation\r\n"); @@ -526,6 +526,7 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { interrupt_attach(interrupt_usb_device, (int8_t)interrupt_usb_device, _ft9xx_usbd_ISR); dcd_connect(rhport); + return true; } // Enable device interrupt diff --git a/src/portable/chipidea/ci_fs/dcd_ci_fs.c b/src/portable/chipidea/ci_fs/dcd_ci_fs.c index 6038160cf..11ddb683f 100644 --- a/src/portable/chipidea/ci_fs/dcd_ci_fs.c +++ b/src/portable/chipidea/ci_fs/dcd_ci_fs.c @@ -267,7 +267,7 @@ static void process_bus_resume(uint8_t rhport) /*------------------------------------------------------------------*/ /* Device API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; (void) rh_init; @@ -296,6 +296,7 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dcd_connect(rhport); // NVIC_ClearPendingIRQ(CIFS_IRQN); + return true; } void dcd_set_address(uint8_t rhport, uint8_t dev_addr) diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index 5204dee66..430a0aad1 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -234,13 +234,13 @@ static void bus_reset(uint8_t rhport) dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); } -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; tu_memclr(&_dcd_data, sizeof(dcd_data_t)); ci_hs_regs_t* dcd_reg = CI_HS_REG(rhport); - TU_ASSERT(ci_ep_count(dcd_reg) <= TUP_DCD_ENDPOINT_MAX, ); + TU_ASSERT(ci_ep_count(dcd_reg) <= TUP_DCD_ENDPOINT_MAX); // Reset controller dcd_reg->USBCMD |= USBCMD_RESET; @@ -268,6 +268,8 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { usbcmd |= USBCMD_RUN_STOP; // run dcd_reg->USBCMD = usbcmd; + + return true; } void dcd_int_enable(uint8_t rhport) diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index 558e1269a..887f59588 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -804,15 +804,16 @@ static void handle_ep0_nak(void) /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; (void) rh_init; _dcd.init_called = true; - if (_dcd.vbus_present) - { + if (_dcd.vbus_present) { dcd_connect(rhport); } + + return true; } void dcd_int_enable(uint8_t rhport) diff --git a/src/portable/espressif/esp32sx/dcd_esp32sx.c b/src/portable/espressif/esp32sx/dcd_esp32sx.c index d233813d4..1b6aae026 100644 --- a/src/portable/espressif/esp32sx/dcd_esp32sx.c +++ b/src/portable/espressif/esp32sx/dcd_esp32sx.c @@ -172,7 +172,7 @@ static void enum_done_processing(void) /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; ESP_LOGV(TAG, "DCD init - Start"); @@ -211,6 +211,7 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { USB_DISCONNINTMSK_M; // host most only dcd_connect(rhport); + return true; } void dcd_set_address(uint8_t rhport, uint8_t dev_addr) diff --git a/src/portable/mentor/musb/dcd_musb.c b/src/portable/mentor/musb/dcd_musb.c index 02c8da1e0..4fce08dd9 100644 --- a/src/portable/mentor/musb/dcd_musb.c +++ b/src/portable/mentor/musb/dcd_musb.c @@ -582,7 +582,7 @@ void print_musb_info(musb_regs_t* musb_regs) { } #endif -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; musb_regs_t* musb_regs = MUSB_REGS(rhport); @@ -594,6 +594,7 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { musb_dcd_int_clear(rhport); musb_dcd_phy_init(rhport); dcd_connect(rhport); + return true; } void dcd_int_enable(uint8_t rhport) { diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c index 089d3f520..d40c4794a 100644 --- a/src/portable/microchip/pic/dcd_pic.c +++ b/src/portable/microchip/pic/dcd_pic.c @@ -470,7 +470,7 @@ static void process_bus_resume(uint8_t rhport) /*------------------------------------------------------------------*/ /* Device API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; intr_disable(rhport); intr_clear(rhport); @@ -502,6 +502,7 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { U1IE = _U1IE_URSTIE_MASK; dcd_connect(rhport); + return true; } void dcd_int_enable(uint8_t rhport) diff --git a/src/portable/microchip/pic32mz/dcd_pic32mz.c b/src/portable/microchip/pic32mz/dcd_pic32mz.c index f1614f30c..8709baf67 100644 --- a/src/portable/microchip/pic32mz/dcd_pic32mz.c +++ b/src/portable/microchip/pic32mz/dcd_pic32mz.c @@ -120,7 +120,7 @@ static ep0_stage_t ep0_get_stage(void) /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; // Disable endpoint interrupts for now USB_REGS->INTRRXEbits.w = 0; @@ -129,6 +129,7 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { USB_REGS->INTRUSBEbits.w = 7; dcd_connect(rhport); + return true; } void dcd_int_enable(uint8_t rhport) diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c index 8120681a7..0c96f6ac4 100644 --- a/src/portable/microchip/samd/dcd_samd.c +++ b/src/portable/microchip/samd/dcd_samd.c @@ -78,8 +78,9 @@ static void bus_reset(void) /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { - (void) rhport; (void) rh_init; +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rhport; + (void) rh_init; // Reset to get in a clean state. USB->DEVICE.CTRLA.bit.SWRST = true; @@ -101,6 +102,8 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { USB->DEVICE.INTFLAG.reg |= USB->DEVICE.INTFLAG.reg; // clear pending USB->DEVICE.INTENSET.reg = /* USB_DEVICE_INTENSET_SOF | */ USB_DEVICE_INTENSET_EORST; + + return true; } #if CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c index b02889b24..c88b31514 100644 --- a/src/portable/microchip/samg/dcd_samg.c +++ b/src/portable/microchip/samg/dcd_samg.c @@ -155,11 +155,13 @@ static void bus_reset(void) } // Initialize controller to device mode -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; (void) rh_init; + tu_memclr(_dcd_xfer, sizeof(_dcd_xfer)); dcd_connect(rhport); + return true; } // Enable device interrupt diff --git a/src/portable/microchip/samx7x/dcd_samx7x.c b/src/portable/microchip/samx7x/dcd_samx7x.c index a85d2306e..8aec1568d 100644 --- a/src/portable/microchip/samx7x/dcd_samx7x.c +++ b/src/portable/microchip/samx7x/dcd_samx7x.c @@ -104,9 +104,10 @@ TU_ATTR_ALWAYS_INLINE static inline void CleanInValidateCache(uint32_t *addr, in //------------------------------------------------------------------ // Initialize controller to device mode -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; dcd_connect(rhport); + return true; } // Enable device interrupt diff --git a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c index b74ca847a..1ce3da27e 100644 --- a/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c +++ b/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c @@ -245,7 +245,7 @@ static void process_bus_active(uint8_t rhport) /*------------------------------------------------------------------*/ /* Device API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; (void) rh_init; @@ -256,6 +256,7 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dcd_connect(rhport); NVIC_ClearPendingIRQ(USB_FS_IRQn); + return true; } #define USB_DEVICE_INTERRUPT_PRIORITY (3U) void dcd_int_enable(uint8_t rhport) diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index 06474e65d..3f53ee26e 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -230,10 +230,11 @@ static void xact_in_dma(uint8_t epnum) { //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; (void) rh_init; TU_LOG2("dcd init\r\n"); + return true; } void dcd_int_enable(uint8_t rhport) { diff --git a/src/portable/nuvoton/nuc120/dcd_nuc120.c b/src/portable/nuvoton/nuc120/dcd_nuc120.c index 89fca021f..b0b6fe857 100644 --- a/src/portable/nuvoton/nuc120/dcd_nuc120.c +++ b/src/portable/nuvoton/nuc120/dcd_nuc120.c @@ -201,7 +201,7 @@ static const uint32_t enabled_irqs = USBD_INTSTS_FLDET_STS_Msk | USBD_INTSTS_BUS NUC100/NUC120 TinyUSB API driver implementation */ -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; (void) rh_init; @@ -215,6 +215,8 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { USBD->INTSTS = enabled_irqs; USBD->INTEN = enabled_irqs; + + return true; } void dcd_int_enable(uint8_t rhport) diff --git a/src/portable/nuvoton/nuc121/dcd_nuc121.c b/src/portable/nuvoton/nuc121/dcd_nuc121.c index b813eea77..f4af97ca7 100644 --- a/src/portable/nuvoton/nuc121/dcd_nuc121.c +++ b/src/portable/nuvoton/nuc121/dcd_nuc121.c @@ -209,7 +209,7 @@ enum { NUC121/NUC125/NUC126 TinyUSB API driver implementation */ -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; (void) rh_init; @@ -227,6 +227,8 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { USBD->INTSTS = ENABLED_IRQS; USBD->INTEN = ENABLED_IRQS; + + return true; } void dcd_int_enable(uint8_t rhport) diff --git a/src/portable/nuvoton/nuc505/dcd_nuc505.c b/src/portable/nuvoton/nuc505/dcd_nuc505.c index 3821b6ec8..1c98a0a49 100644 --- a/src/portable/nuvoton/nuc505/dcd_nuc505.c +++ b/src/portable/nuvoton/nuc505/dcd_nuc505.c @@ -279,7 +279,7 @@ static const uint32_t enabled_irqs = USBD_GINTEN_USBIEN_Msk | \ NUC505 TinyUSB API driver implementation */ -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; (void) rh_init; @@ -291,6 +291,8 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { bus_reset(); usb_attach(); + + return true; } void dcd_int_enable(uint8_t rhport) diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 1b7f56e8c..8398b09bf 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -265,7 +265,7 @@ static void process_bus_resume(uint8_t rhport) /*------------------------------------------------------------------*/ /* Device API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; (void) rh_init; @@ -294,6 +294,8 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dcd_connect(rhport); NVIC_ClearPendingIRQ(USB0_IRQn); + + return true; } void dcd_int_enable(uint8_t rhport) diff --git a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c index 22b4500c5..855c59cd1 100644 --- a/src/portable/nxp/lpc17_40/dcd_lpc17_40.c +++ b/src/portable/nxp/lpc17_40/dcd_lpc17_40.c @@ -167,7 +167,7 @@ static void bus_reset(void) tu_memclr(&_dcd, sizeof(dcd_data_t)); } -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; (void) rh_init; @@ -186,6 +186,8 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Clear pending IRQ NVIC_ClearPendingIRQ(USB_IRQn); + + return true; } void dcd_int_enable(uint8_t rhport) diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c index e59a0f526..7d5cfb5b0 100644 --- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c +++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c @@ -289,7 +289,7 @@ static void edpt_reset_all(uint8_t rhport) } prepare_setup_packet(rhport); } -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; edpt_reset_all(rhport); @@ -303,6 +303,8 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { DEVCMDSTAT_RESET_CHANGE_MASK | DEVCMDSTAT_CONNECT_CHANGE_MASK | DEVCMDSTAT_SUSPEND_CHANGE_MASK; NVIC_ClearPendingIRQ(_dcd_controller[rhport].irqnum); + + return true; } void dcd_int_enable(uint8_t rhport) diff --git a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c index 89d60a21e..60afbd435 100644 --- a/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c @@ -50,11 +50,13 @@ static usb_descriptor_buffers_t desc; *------------------------------------------------------------------*/ // Initialize controller to device mode -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; (void) rh_init; static pio_usb_configuration_t config = PIO_USB_DEFAULT_CONFIG; usb_device = pio_usb_device_init(&config, &desc); + + return true; } // Enable device interrupt diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 9a945caf8..2e177d5cb 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -369,7 +369,7 @@ static void __tusb_irq_path_func(dcd_rp2040_irq)(void) { #define PICO_SHARED_IRQ_HANDLER_HIGHEST_ORDER_PRIORITY 0xff #endif -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; assert(rhport == 0); @@ -406,6 +406,7 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (FORCE_VBUS_DETECT ? 0 : USB_INTS_DEV_CONN_DIS_BITS); dcd_connect(rhport); + return true; } bool dcd_deinit(uint8_t rhport) { diff --git a/src/portable/renesas/rusb2/dcd_rusb2.c b/src/portable/renesas/rusb2/dcd_rusb2.c index 3da4ef50b..ecd28973c 100644 --- a/src/portable/renesas/rusb2/dcd_rusb2.c +++ b/src/portable/renesas/rusb2/dcd_rusb2.c @@ -657,14 +657,14 @@ static void enable_interrupt(uint32_t pswi) } #endif -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; rusb2_reg_t* rusb = RUSB2_REG(rhport); rusb2_module_start(rhport, true); -// We disable SOF for now until needed later on. -// Since TinyUSB doesn't use SOF for now, and this interrupt often (1ms interval) -_dcd.sof_enabled = false; + // We disable SOF for now until needed later on. + // Since TinyUSB doesn't use SOF for now, and this interrupt often (1ms interval) + _dcd.sof_enabled = false; #ifdef RUSB2_SUPPORT_HIGHSPEED if ( rusb2_is_highspeed_rhport(rhport) ) { @@ -719,6 +719,8 @@ _dcd.sof_enabled = false; if (rusb->INTSTS0_b.VBSTS) { dcd_connect(rhport); } + + return true; } void dcd_int_enable(uint8_t rhport) { diff --git a/src/portable/sony/cxd56/dcd_cxd56.c b/src/portable/sony/cxd56/dcd_cxd56.c index 93eb8674e..b16509c6f 100644 --- a/src/portable/sony/cxd56/dcd_cxd56.c +++ b/src/portable/sony/cxd56/dcd_cxd56.c @@ -201,7 +201,7 @@ static void _dcd_resume(FAR struct usbdevclass_driver_s *driver, FAR struct usbd dcd_event_bus_signal(0, DCD_EVENT_RESUME, true); } -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; (void) rh_init; @@ -211,6 +211,8 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { usbdcd_driver.setup_queue = osal_queue_create(&_setup_queue_def); usbdev_register(&usbdcd_driver.usbdevclass_driver); + + return true; } // Enable device interrupt diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index a4bd2da10..d921429e2 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -184,7 +184,7 @@ TU_ATTR_ALWAYS_INLINE static inline xfer_ctl_t *xfer_ctl_ptr(uint8_t epnum, uint //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; // Follow the RM mentions to use a special ordering of PDWN and FRES for (volatile uint32_t i = 0; i < 200; i++) { // should be a few us @@ -224,6 +224,8 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Enable pull-up if supported dcd_connect(rhport); + + return true; } void dcd_sof_enable(uint8_t rhport, bool en) { diff --git a/src/portable/sunxi/dcd_sunxi_musb.c b/src/portable/sunxi/dcd_sunxi_musb.c index 85c7bef5d..21f13b279 100644 --- a/src/portable/sunxi/dcd_sunxi_musb.c +++ b/src/portable/sunxi/dcd_sunxi_musb.c @@ -867,8 +867,9 @@ static void usb_isr_handler(void) { dcd_int_handler(0); } -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; + dcd_disconnect(rhport); USBC_HardwareReset(); USBC_PhyConfig(); @@ -895,6 +896,8 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { f1c100s_intc_set_isr(F1C100S_IRQ_USBOTG, usb_isr_handler); dcd_connect(rhport); + + return true; } // Connect by enabling internal pull-up resistor on D+/D- diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index e44ca96d1..f30ec5ee3 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -650,14 +650,15 @@ static bool check_dwc2(dwc2_regs_t* dwc2) { return true; } -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { - (void) rhport; (void) rh_init; +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rhport; + (void) rh_init; // Programming model begins in the last section of the chapter on the USB // peripheral in each Reference Manual. dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Check Synopsys ID register, failed if controller clock/power is not enabled - TU_ASSERT(check_dwc2(dwc2), ); + TU_ASSERT(check_dwc2(dwc2)); dcd_disconnect(rhport); if (phy_hs_supported(dwc2)) { @@ -726,6 +727,8 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // TU_LOG_HEX(DWC2_DEBUG, dwc2->gahbcfg); dcd_connect(rhport); + + return true; } void dcd_int_enable(uint8_t rhport) { diff --git a/src/portable/template/dcd_template.c b/src/portable/template/dcd_template.c index 5ce650844..3738ac0cb 100644 --- a/src/portable/template/dcd_template.c +++ b/src/portable/template/dcd_template.c @@ -40,8 +40,9 @@ *------------------------------------------------------------------*/ // Initialize controller to device mode -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; (void) rh_init; + return true; } // Enable device interrupt diff --git a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c index 6150c254f..3752ae251 100644 --- a/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c +++ b/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c @@ -130,7 +130,7 @@ static void enable_functional_reset(const bool enable) /*------------------------------------------------------------------*/ /* Controller API *------------------------------------------------------------------*/ -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; (void) rh_init; USBKEYPID = USBKEY; @@ -163,6 +163,8 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { } USBKEYPID = 0; + + return true; } // There is no "USB peripheral interrupt disable" bit on MSP430, so we have diff --git a/src/portable/valentyusb/eptri/dcd_eptri.c b/src/portable/valentyusb/eptri/dcd_eptri.c index 8287230a4..a03c94558 100644 --- a/src/portable/valentyusb/eptri/dcd_eptri.c +++ b/src/portable/valentyusb/eptri/dcd_eptri.c @@ -336,7 +336,7 @@ static void dcd_reset(void) } // Initializes the USB peripheral for device mode and enables it. -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; (void) rh_init; @@ -352,6 +352,8 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Turn on the external pullup usb_pullup_out_write(1); + + return true; } // Enables or disables the USB device interrupt(s). May be used to diff --git a/src/portable/wch/dcd_ch32_usbfs.c b/src/portable/wch/dcd_ch32_usbfs.c index 9af3a1acb..4e8e25a00 100644 --- a/src/portable/wch/dcd_ch32_usbfs.c +++ b/src/portable/wch/dcd_ch32_usbfs.c @@ -123,7 +123,7 @@ static void update_out(uint8_t rhport, uint8_t ep, size_t rx_len) { } /* public functions */ -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; // init registers USBOTG_FS->BASE_CTRL = USBFS_CTRL_SYS_CTRL | USBFS_CTRL_INT_BUSY | USBFS_CTRL_DMA_EN; @@ -154,6 +154,8 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { EP_DMA(3) = (uint32_t) &data.ep3_buffer.out[0]; dcd_connect(rhport); + + return true; } void dcd_int_handler(uint8_t rhport) { diff --git a/src/portable/wch/dcd_ch32_usbhs.c b/src/portable/wch/dcd_ch32_usbhs.c index 64a88914f..f8bf3c889 100644 --- a/src/portable/wch/dcd_ch32_usbhs.c +++ b/src/portable/wch/dcd_ch32_usbhs.c @@ -131,7 +131,7 @@ static void xfer_data_packet(uint8_t ep_num, tusb_dir_t ep_dir, xfer_ctl_t* xfer ep_set_response_and_toggle(ep_num, ep_dir, USBHS_EP_R_RES_ACK); } -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rhport; (void) rh_init; @@ -171,6 +171,8 @@ void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { USBHSD->DEV_AD = 0; USBHSD->CONTROL |= USBHS_DEV_PU_EN; + + return true; } void dcd_int_enable(uint8_t rhport) { diff --git a/test/fuzz/dcd_fuzz.cc b/test/fuzz/dcd_fuzz.cc index e76ae5087..046a90555 100644 --- a/test/fuzz/dcd_fuzz.cc +++ b/test/fuzz/dcd_fuzz.cc @@ -46,10 +46,10 @@ tu_static State state = {false, 0, 0}; // All no-ops as we are fuzzing. //--------------------------------------------------------------------+ extern "C" { -void dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { UNUSED(rhport); UNUSED(rh_init); - return; + return true; } void dcd_int_handler(uint8_t rhport) { diff --git a/test/unit-test/test/device/msc/test_msc_device.c b/test/unit-test/test/device/msc/test_msc_device.c index 60fcdb41c..f2a4fa295 100644 --- a/test/unit-test/test/device/msc/test_msc_device.c +++ b/test/unit-test/test/device/msc/test_msc_device.c @@ -203,7 +203,7 @@ void setUp(void) .speed = TUSB_SPEED_AUTO }; - dcd_init_Expect(0, &dev_init); + dcd_init_ExpectAndReturn(0, &dev_init, true); tusb_init(0, &dev_init); } diff --git a/test/unit-test/test/device/usbd/test_usbd.c b/test/unit-test/test/device/usbd/test_usbd.c index 598dac641..9879cd4ba 100644 --- a/test/unit-test/test/device/usbd/test_usbd.c +++ b/test/unit-test/test/device/usbd/test_usbd.c @@ -127,7 +127,7 @@ void setUp(void) { }; mscd_init_Expect(); - dcd_init_Expect(0, &dev_init); + dcd_init_ExpectAndReturn(0, &dev_init, true); tusb_init(0, &dev_init); } -- cgit v1.3.1 From 10a3aa3cc8f58a783d2109f5a6c9a4012992f982 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 15 Oct 2024 13:03:12 +0700 Subject: adding hcd dwc2 --- examples/dual/host_hid_to_device_cdc/only.txt | 1 + examples/dual/host_info_to_device_cdc/only.txt | 1 + examples/host/device_info/only.txt | 1 + hw/bsp/stm32h7/family.c | 7 +- hw/bsp/stm32h7/family.cmake | 2 + src/portable/synopsys/dwc2/dcd_dwc2.c | 194 +----------------------- src/portable/synopsys/dwc2/dwc2_common.c | 196 +++++++++++++++++++++++++ src/portable/synopsys/dwc2/dwc2_common.h | 70 +++++++++ src/portable/synopsys/dwc2/dwc2_type.h | 4 +- src/portable/synopsys/dwc2/hcd_dwc2.c | 167 +++++++++++++++++++++ 10 files changed, 447 insertions(+), 196 deletions(-) create mode 100644 src/portable/synopsys/dwc2/dwc2_common.c create mode 100644 src/portable/synopsys/dwc2/dwc2_common.h create mode 100644 src/portable/synopsys/dwc2/hcd_dwc2.c (limited to 'src/portable') diff --git a/examples/dual/host_hid_to_device_cdc/only.txt b/examples/dual/host_hid_to_device_cdc/only.txt index cfc87eb4e..149ece856 100644 --- a/examples/dual/host_hid_to_device_cdc/only.txt +++ b/examples/dual/host_hid_to_device_cdc/only.txt @@ -4,3 +4,4 @@ board:mcb1800 mcu:RP2040 mcu:ra6m5 mcu:MAX3421 +mcu:STM32H7 diff --git a/examples/dual/host_info_to_device_cdc/only.txt b/examples/dual/host_info_to_device_cdc/only.txt index cfc87eb4e..149ece856 100644 --- a/examples/dual/host_info_to_device_cdc/only.txt +++ b/examples/dual/host_info_to_device_cdc/only.txt @@ -4,3 +4,4 @@ board:mcb1800 mcu:RP2040 mcu:ra6m5 mcu:MAX3421 +mcu:STM32H7 diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt index b3f4468bb..a38fc251b 100644 --- a/examples/host/device_info/only.txt +++ b/examples/host/device_info/only.txt @@ -12,3 +12,4 @@ mcu:MSP432E4 mcu:RP2040 mcu:RX65X mcu:RAXXX +mcu:STM32H7 diff --git a/hw/bsp/stm32h7/family.c b/hw/bsp/stm32h7/family.c index 6e4b388d6..3bed1f5ec 100644 --- a/hw/bsp/stm32h7/family.c +++ b/hw/bsp/stm32h7/family.c @@ -151,7 +151,7 @@ void board_init(void) { HAL_UART_Init(&UartHandle); #endif -#if BOARD_TUD_RHPORT == 0 + //------------- USB FS -------------// // Despite being call USB2_OTG // OTG_FS is marked as RHPort0 by TinyUSB to be consistent across stm32 port // PA9 VUSB, PA10 ID, PA11 DM, PA12 DP @@ -195,10 +195,9 @@ void board_init(void) { USB_OTG_FS->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; #endif // vbus sense -#elif BOARD_TUD_RHPORT == 1 + //------------- USB HS -------------// // Despite being call USB2_OTG // OTG_HS is marked as RHPort1 by TinyUSB to be consistent across stm32 port - struct { GPIO_TypeDef* port; uint32_t pin; @@ -238,8 +237,6 @@ void board_init(void) { // For waveshare openh743 ULPI PHY reset walkaround board_stm32h7_post_init(); -#endif // rhport = 1 - } //--------------------------------------------------------------------+ diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake index 026c7c3df..e4161ffe5 100644 --- a/hw/bsp/stm32h7/family.cmake +++ b/hw/bsp/stm32h7/family.cmake @@ -106,6 +106,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_STM32H7 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index f30ec5ee3..a9b3770ee 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -35,45 +35,7 @@ #define DWC2_DEBUG 2 #include "device/dcd.h" -#include "dwc2_type.h" - -// Following symbols must be defined by port header -// - _dwc2_controller[]: array of controllers -// - DWC2_EP_MAX: largest EP counts of all controllers -// - dwc2_phy_init/dwc2_phy_update: phy init called before and after core reset -// - dwc2_dcd_int_enable/dwc2_dcd_int_disable -// - dwc2_remote_wakeup_delay - -#if defined(TUP_USBIP_DWC2_STM32) - #include "dwc2_stm32.h" -#elif defined(TUP_USBIP_DWC2_ESP32) - #include "dwc2_esp32.h" -#elif TU_CHECK_MCU(OPT_MCU_GD32VF103) - #include "dwc2_gd32.h" -#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837) - #include "dwc2_bcm.h" -#elif TU_CHECK_MCU(OPT_MCU_EFM32GG) - #include "dwc2_efm32.h" -#elif TU_CHECK_MCU(OPT_MCU_XMC4000) - #include "dwc2_xmc.h" -#else - #error "Unsupported MCUs" -#endif - -enum { - DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller) -}; - -// DWC2 registers -//#define DWC2_REG(_port) ((dwc2_regs_t*) _dwc2_controller[_port].reg_base) - -TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { - if (rhport >= DWC2_CONTROLLER_COUNT) { - // user mis-configured, ignore and use first controller - rhport = 0; - } - return (dwc2_regs_t*) _dwc2_controller[rhport].reg_base; -} +#include "dwc2_common.h" //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM @@ -511,162 +473,16 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c } } -/*------------------------------------------------------------------*/ -/* Controller API - *------------------------------------------------------------------*/ - -static void reset_core(dwc2_regs_t* dwc2) { - // reset core - dwc2->grstctl |= GRSTCTL_CSRST; - - // wait for reset bit is cleared - // TODO version 4.20a should wait for RESET DONE mask - while (dwc2->grstctl & GRSTCTL_CSRST) {} - - // wait for AHB master IDLE - while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {} - - // wait for device mode ? -} - -static bool phy_hs_supported(dwc2_regs_t* dwc2) { - (void) dwc2; - -#if !TUD_OPT_HIGH_SPEED - return false; -#else - return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED; -#endif -} - -static void phy_fs_init(dwc2_regs_t* dwc2) { - TU_LOG(DWC2_DEBUG, "Fullspeed PHY init\r\n"); - - // Select FS PHY - dwc2->gusbcfg |= GUSBCFG_PHYSEL; - - // MCU specific PHY init before reset - dwc2_phy_init(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED); - - // Reset core after selecting PHY - reset_core(dwc2); - - // USB turnaround time is critical for certification where long cables and 5-Hubs are used. - // So if you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical, - // these bits can be programmed to a larger value. Default is 5 - dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos); - - // MCU specific PHY update post reset - dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED); - - // set max speed - dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos); -} - -static void phy_hs_init(dwc2_regs_t* dwc2) { - uint32_t gusbcfg = dwc2->gusbcfg; - - // De-select FS PHY - gusbcfg &= ~GUSBCFG_PHYSEL; - - if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { - TU_LOG(DWC2_DEBUG, "Highspeed ULPI PHY init\r\n"); - - // Select ULPI - gusbcfg |= GUSBCFG_ULPI_UTMI_SEL; - - // ULPI 8-bit interface, single data rate - gusbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL); - - // default internal VBUS Indicator and Drive - gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); - - // Disable FS/LS ULPI - gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM); - } else { - TU_LOG(DWC2_DEBUG, "Highspeed UTMI+ PHY init\r\n"); - - // Select UTMI+ with 8-bit interface - gusbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16); - - // Set 16-bit interface if supported - if (dwc2->ghwcfg4_bm.phy_data_width) { - gusbcfg |= GUSBCFG_PHYIF16; - } - } - - // Apply config - dwc2->gusbcfg = gusbcfg; - - // mcu specific phy init - dwc2_phy_init(dwc2, dwc2->ghwcfg2_bm.hs_phy_type); - - // Reset core after selecting PHY - reset_core(dwc2); - - // Set turn-around, must after core reset otherwise it will be clear - // - 9 if using 8-bit PHY interface - // - 5 if using 16-bit PHY interface - gusbcfg &= ~GUSBCFG_TRDT_Msk; - gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; - dwc2->gusbcfg = gusbcfg; - - // MCU specific PHY update post reset - dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type); - - // Set max speed - uint32_t dcfg = dwc2->dcfg; - dcfg &= ~DCFG_DSPD_Msk; - dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos; - - // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required - // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347) - if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { - dcfg |= DCFG_XCVRDLY; - } - - dwc2->dcfg = dcfg; -} - -static bool check_dwc2(dwc2_regs_t* dwc2) { -#if CFG_TUSB_DEBUG >= DWC2_DEBUG - // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4 - // Run 'python dwc2_info.py' and check dwc2_info.md for bit-field value and comparison with other ports - volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid; - TU_LOG1("guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n"); - for (size_t i = 0; i < 5; i++) { - TU_LOG1("0x%08" PRIX32 ", ", p[i]); - } - TU_LOG1("0x%08" PRIX32 "\r\n", p[5]); -#endif - - // For some reason: GD32VF103 snpsid and all hwcfg register are always zero (skip it) - (void) dwc2; -#if !TU_CHECK_MCU(OPT_MCU_GD32VF103) - uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK; - TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID); -#endif - - return true; -} - +//-------------------------------------------------------------------- +// Controller API +//-------------------------------------------------------------------- bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { - (void) rhport; (void) rh_init; - // Programming model begins in the last section of the chapter on the USB - // peripheral in each Reference Manual. dwc2_regs_t* dwc2 = DWC2_REG(rhport); - // Check Synopsys ID register, failed if controller clock/power is not enabled - TU_ASSERT(check_dwc2(dwc2)); + TU_ASSERT(dwc2_controller_init(rhport, rh_init)); dcd_disconnect(rhport); - if (phy_hs_supported(dwc2)) { - phy_hs_init(dwc2); // Highspeed - } else { - phy_fs_init(dwc2); // core does not support highspeed or hs phy is not present - } - // Restart PHY clock dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE); diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c new file mode 100644 index 000000000..7fd2311db --- /dev/null +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -0,0 +1,196 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#define DWC2_COMMON_DEBUG 2 + +#if defined(TUP_USBIP_DWC2) && (CFG_TUH_ENABLED || CFG_TUD_ENABLED) + +#include "common/tusb_common.h" +#include "dwc2_common.h" + +static void reset_core(dwc2_regs_t* dwc2) { + // reset core + dwc2->grstctl |= GRSTCTL_CSRST; + + // wait for reset bit is cleared + // TODO version 4.20a should wait for RESET DONE mask + while (dwc2->grstctl & GRSTCTL_CSRST) {} + + // wait for AHB master IDLE + while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {} + + // wait for device mode ? +} + +static bool phy_hs_supported(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { + (void) dwc2; + + +#if !TUD_OPT_HIGH_SPEED + return false; +#else + return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED; +#endif +} + +static void phy_fs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { + TU_LOG(DWC2_COMMON_DEBUG, "Fullspeed PHY init\r\n"); + + // Select FS PHY + dwc2->gusbcfg |= GUSBCFG_PHYSEL; + + // MCU specific PHY init before reset + dwc2_phy_init(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED); + + // Reset core after selecting PHY + reset_core(dwc2); + + // USB turnaround time is critical for certification where long cables and 5-Hubs are used. + // So if you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical, + // these bits can be programmed to a larger value. Default is 5 + dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos); + + // MCU specific PHY update post reset + dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED); + + // set max speed + dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos); +} + +static void phy_hs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { + uint32_t gusbcfg = dwc2->gusbcfg; + + // De-select FS PHY + gusbcfg &= ~GUSBCFG_PHYSEL; + + if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { + TU_LOG(DWC2_COMMON_DEBUG, "Highspeed ULPI PHY init\r\n"); + + // Select ULPI PHY (external) + gusbcfg |= GUSBCFG_ULPI_UTMI_SEL; + + // ULPI is always 8-bit interface + gusbcfg &= ~GUSBCFG_PHYIF16; + + // ULPI select single data rate + gusbcfg &= ~GUSBCFG_DDRSEL; + + // default internal VBUS Indicator and Drive + gusbcfg &= ~(GUSBCFG_ULPIEVBUSD | GUSBCFG_ULPIEVBUSI); + + // Disable FS/LS ULPI + gusbcfg &= ~(GUSBCFG_ULPIFSLS | GUSBCFG_ULPICSM); + } else { + TU_LOG(DWC2_COMMON_DEBUG, "Highspeed UTMI+ PHY init\r\n"); + + // Select UTMI+ PHY (internal) + gusbcfg &= ~GUSBCFG_ULPI_UTMI_SEL; + + // Set 16-bit interface if supported + if (dwc2->ghwcfg4_bm.phy_data_width) { + gusbcfg |= GUSBCFG_PHYIF16; // 16 bit + }else { + gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit + } + } + + // Apply config + dwc2->gusbcfg = gusbcfg; + + // mcu specific phy init + dwc2_phy_init(dwc2, dwc2->ghwcfg2_bm.hs_phy_type); + + // Reset core after selecting PHY + reset_core(dwc2); + + // Set turn-around, must after core reset otherwise it will be clear + // - 9 if using 8-bit PHY interface + // - 5 if using 16-bit PHY interface + gusbcfg &= ~GUSBCFG_TRDT_Msk; + gusbcfg |= (dwc2->ghwcfg4_bm.phy_data_width ? 5u : 9u) << GUSBCFG_TRDT_Pos; + dwc2->gusbcfg = gusbcfg; + + // MCU specific PHY update post reset + dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type); + + // Set max speed + uint32_t dcfg = dwc2->dcfg; + dcfg &= ~DCFG_DSPD_Msk; + dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos; + + // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required + // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347) + if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { + dcfg |= DCFG_XCVRDLY; + } + + dwc2->dcfg = dcfg; +} + +static bool check_dwc2(dwc2_regs_t* dwc2) { +#if CFG_TUSB_DEBUG >= DWC2_COMMON_DEBUG + // print guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4 + // Run 'python dwc2_info.py' and check dwc2_info.md for bit-field value and comparison with other ports + volatile uint32_t const* p = (volatile uint32_t const*) &dwc2->guid; + TU_LOG1("guid, gsnpsid, ghwcfg1, ghwcfg2, ghwcfg3, ghwcfg4\r\n"); + for (size_t i = 0; i < 5; i++) { + TU_LOG1("0x%08" PRIX32 ", ", p[i]); + } + TU_LOG1("0x%08" PRIX32 "\r\n", p[5]); +#endif + + // For some reason: GD32VF103 gsnpsid and all hwcfg register are always zero (skip it) + (void) dwc2; +#if !TU_CHECK_MCU(OPT_MCU_GD32VF103) + uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK; + TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID); +#endif + + return true; +} + +//-------------------------------------------------------------------- +// +//-------------------------------------------------------------------- +bool dwc2_controller_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + + // Check Synopsys ID register, failed if controller clock/power is not enabled + TU_ASSERT(check_dwc2(dwc2)); + + if (phy_hs_supported(dwc2, rh_init)) { + phy_hs_init(dwc2, rh_init); // Highspeed + } else { + phy_fs_init(dwc2, rh_init); // core does not support highspeed or hs phy is not present + } + + return true; +} + +#endif diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h new file mode 100644 index 000000000..2a48654c0 --- /dev/null +++ b/src/portable/synopsys/dwc2/dwc2_common.h @@ -0,0 +1,70 @@ +/* +* The MIT License (MIT) + * + * Copyright (c) 2024 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef TUSB_DWC2_COMMON_H +#define TUSB_DWC2_COMMON_H + +#include "dwc2_type.h" + +// Following symbols must be defined by port header +// - _dwc2_controller[]: array of controllers +// - DWC2_EP_MAX: largest EP counts of all controllers +// - dwc2_phy_init/dwc2_phy_update: phy init called before and after core reset +// - dwc2_dcd_int_enable/dwc2_dcd_int_disable +// - dwc2_remote_wakeup_delay + +#if defined(TUP_USBIP_DWC2_STM32) + #include "dwc2_stm32.h" +#elif defined(TUP_USBIP_DWC2_ESP32) + #include "dwc2_esp32.h" +#elif TU_CHECK_MCU(OPT_MCU_GD32VF103) + #include "dwc2_gd32.h" +#elif TU_CHECK_MCU(OPT_MCU_BCM2711, OPT_MCU_BCM2835, OPT_MCU_BCM2837) + #include "dwc2_bcm.h" +#elif TU_CHECK_MCU(OPT_MCU_EFM32GG) + #include "dwc2_efm32.h" +#elif TU_CHECK_MCU(OPT_MCU_XMC4000) + #include "dwc2_xmc.h" +#else + #error "Unsupported MCUs" +#endif + +enum { + DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller) +}; + +TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { + if (rhport >= DWC2_CONTROLLER_COUNT) { + // user mis-configured, ignore and use first controller + rhport = 0; + } + return (dwc2_regs_t*)_dwc2_controller[rhport].reg_base; +} + + +bool dwc2_controller_init(uint8_t rhport, const tusb_rhport_init_t* rh_init); + +#endif diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index cf05bbfec..b9dc413b1 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -31,8 +31,8 @@ * opensource.org/licenses/BSD-3-Clause */ -#ifndef _TUSB_DWC2_TYPES_H_ -#define _TUSB_DWC2_TYPES_H_ +#ifndef TUSB_DWC2_TYPES_H_ +#define TUSB_DWC2_TYPES_H_ #include "stdint.h" diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c new file mode 100644 index 000000000..8798f982c --- /dev/null +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -0,0 +1,167 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2024 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUH_ENABLED && defined(TUP_USBIP_DWC2) + +// Debug level for DWC2 +#define DWC2_DEBUG 2 + +#include "host/hcd.h" +#include "dwc2_common.h" + +//--------------------------------------------------------------------+ +// Controller API +//--------------------------------------------------------------------+ + +// optional hcd configuration, called by tuh_configure() +bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { + (void) rhport; + (void) cfg_id; + (void) cfg_param; + + return false; +} + +// Initialize controller to host mode +bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rhport; + (void) rh_init; + return false; +} + +// Interrupt Handler +void hcd_int_handler(uint8_t rhport, bool in_isr) { + (void) rhport; + (void) in_isr; +} + +// Enable USB interrupt +void hcd_int_enable (uint8_t rhport) { + (void) rhport; +} + +// Disable USB interrupt +void hcd_int_disable(uint8_t rhport) { + (void) rhport; +} + +// Get frame number (1ms) +uint32_t hcd_frame_number(uint8_t rhport) { + (void) rhport; + + return 0; +} + +//--------------------------------------------------------------------+ +// Port API +//--------------------------------------------------------------------+ + +// Get the current connect status of roothub port +bool hcd_port_connect_status(uint8_t rhport) { + (void) rhport; + + return false; +} + +// Reset USB bus on the port. Return immediately, bus reset sequence may not be complete. +// Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence. +void hcd_port_reset(uint8_t rhport) { + (void) rhport; +} + +// Complete bus reset sequence, may be required by some controllers +void hcd_port_reset_end(uint8_t rhport) { + (void) rhport; +} + +// Get port link speed +tusb_speed_t hcd_port_speed_get(uint8_t rhport) { + (void) rhport; + + return TUSB_SPEED_FULL; +} + +// HCD closes all opened endpoints belong to this device +void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { + (void) rhport; + (void) dev_addr; +} + +//--------------------------------------------------------------------+ +// Endpoints API +//--------------------------------------------------------------------+ + +// Open an endpoint +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { + (void) rhport; + (void) dev_addr; + (void) ep_desc; + + return false; +} + +// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked +bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + (void) buffer; + (void) buflen; + + return false; +} + +// Abort a queued transfer. Note: it can only abort transfer that has not been started +// Return true if a queued transfer is aborted, false if there is no transfer to abort +bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + + return false; +} + +// Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked +bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { + (void) rhport; + (void) dev_addr; + (void) setup_packet; + + return false; +} + +// clear stall, data toggle is also reset to DATA0 +bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { + (void) rhport; + (void) dev_addr; + (void) ep_addr; + + return false; +} + +#endif -- cgit v1.3.1 From 4012e150757b517620465d93a22b0787c6400c5d Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 15 Oct 2024 17:55:24 +0700 Subject: move core init code to dwc2 common. update/correct build for esppressif --- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- .../device/audio_4_channel_mic_freertos/src/main.c | 6 +-- .../audio_4_channel_mic_freertos/src/tusb_config.h | 2 +- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- examples/device/audio_test_freertos/src/main.c | 9 ++-- .../device/audio_test_freertos/src/tusb_config.h | 2 +- examples/device/board_test/src/main.c | 2 +- examples/device/board_test/src/tusb_config.h | 2 +- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- examples/device/cdc_msc_freertos/src/main.c | 6 +-- examples/device/cdc_msc_freertos/src/tusb_config.h | 2 +- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- examples/device/hid_composite_freertos/src/main.c | 6 +-- .../hid_composite_freertos/src/tusb_config.h | 2 +- examples/device/video_capture/src/main.c | 4 +- examples/device/video_capture/src/tusb_config.h | 2 +- examples/device/video_capture_2ch/src/main.c | 4 +- .../device/video_capture_2ch/src/tusb_config.h | 2 +- .../src/FreeRTOSConfig/FreeRTOSConfig.h | 2 +- examples/host/cdc_msc_hid_freertos/src/cdc_app.c | 2 +- examples/host/cdc_msc_hid_freertos/src/main.c | 6 +-- .../host/cdc_msc_hid_freertos/src/tusb_config.h | 2 +- examples/typec/power_delivery/src/main.c | 2 +- hw/bsp/board_api.h | 2 +- hw/bsp/broadcom_32bit/family.cmake | 2 + hw/bsp/broadcom_64bit/family.cmake | 2 + .../components/tinyusb_src/CMakeLists.txt | 2 + hw/bsp/gd32vf103/family.cmake | 2 + hw/bsp/stm32f2/family.cmake | 2 + hw/bsp/stm32f4/family.cmake | 2 + hw/bsp/stm32f7/family.cmake | 2 + hw/bsp/stm32h7/boards/stm32h743eval/board.cmake | 2 +- hw/bsp/stm32u5/family.cmake | 17 +++--- hw/bsp/xmc4000/family.cmake | 2 + src/common/tusb_verify.h | 2 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 34 +++++++----- src/portable/synopsys/dwc2/dwc2_common.c | 63 ++++++++++++---------- src/portable/synopsys/dwc2/dwc2_common.h | 5 +- src/portable/synopsys/dwc2/dwc2_esp32.h | 5 +- src/portable/synopsys/dwc2/dwc2_type.h | 60 ++++++++++----------- src/tusb_option.h | 3 +- tools/build_utils.py | 29 +++++----- 42 files changed, 171 insertions(+), 140 deletions(-) (limited to 'src/portable') diff --git a/examples/device/audio_4_channel_mic_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/audio_4_channel_mic_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h index 869500ad2..902a54f08 100644 --- a/examples/device/audio_4_channel_mic_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h +++ b/examples/device/audio_4_channel_mic_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -48,7 +48,7 @@ // Include MCU header #include "bsp/board_mcu.h" -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 +#if TUSB_MCU_VENDOR_ESPRESSIF #error "ESP32-Sx should use IDF's FreeRTOSConfig.h" #endif diff --git a/examples/device/audio_4_channel_mic_freertos/src/main.c b/examples/device/audio_4_channel_mic_freertos/src/main.c index 2ac7516cd..c9de4029a 100644 --- a/examples/device/audio_4_channel_mic_freertos/src/main.c +++ b/examples/device/audio_4_channel_mic_freertos/src/main.c @@ -39,7 +39,7 @@ #include "bsp/board_api.h" #include "tusb.h" -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" @@ -186,14 +186,14 @@ int main(void) #endif // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 - #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) + #if !TUSB_MCU_VENDOR_ESPRESSIF vTaskStartScheduler(); #endif return 0; } -#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) +#if TUSB_MCU_VENDOR_ESPRESSIF void app_main(void) { main(); diff --git a/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h b/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h index 88f20278b..5cd93b0d6 100644 --- a/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h +++ b/examples/device/audio_4_channel_mic_freertos/src/tusb_config.h @@ -59,7 +59,7 @@ extern "C" { #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/audio_test_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/audio_test_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h index 869500ad2..902a54f08 100644 --- a/examples/device/audio_test_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h +++ b/examples/device/audio_test_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -48,7 +48,7 @@ // Include MCU header #include "bsp/board_mcu.h" -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 +#if TUSB_MCU_VENDOR_ESPRESSIF #error "ESP32-Sx should use IDF's FreeRTOSConfig.h" #endif diff --git a/examples/device/audio_test_freertos/src/main.c b/examples/device/audio_test_freertos/src/main.c index 4e2264b5d..c5143c3fc 100644 --- a/examples/device/audio_test_freertos/src/main.c +++ b/examples/device/audio_test_freertos/src/main.c @@ -38,7 +38,7 @@ #include "bsp/board_api.h" #include "tusb.h" -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" @@ -133,16 +133,15 @@ int main(void) #endif // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 - #if !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) + #if !TUSB_MCU_VENDOR_ESPRESSIF vTaskStartScheduler(); #endif return 0; } -#if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) -void app_main(void) -{ +#if TUSB_MCU_VENDOR_ESPRESSIF +void app_main(void) { main(); } #endif diff --git a/examples/device/audio_test_freertos/src/tusb_config.h b/examples/device/audio_test_freertos/src/tusb_config.h index 8b376a4c3..61c5cbb96 100644 --- a/examples/device/audio_test_freertos/src/tusb_config.h +++ b/examples/device/audio_test_freertos/src/tusb_config.h @@ -59,7 +59,7 @@ extern "C" { #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/board_test/src/main.c b/examples/device/board_test/src/main.c index 91799eb89..2269d45f1 100644 --- a/examples/device/board_test/src/main.c +++ b/examples/device/board_test/src/main.c @@ -67,7 +67,7 @@ int main(void) { } } -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 +#if TUSB_MCU_VENDOR_ESPRESSIF void app_main(void) { main(); } diff --git a/examples/device/board_test/src/tusb_config.h b/examples/device/board_test/src/tusb_config.h index 89c27d1c0..8ac3bc8de 100644 --- a/examples/device/board_test/src/tusb_config.h +++ b/examples/device/board_test/src/tusb_config.h @@ -44,7 +44,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h index 869500ad2..902a54f08 100644 --- a/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h +++ b/examples/device/cdc_msc_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -48,7 +48,7 @@ // Include MCU header #include "bsp/board_mcu.h" -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 +#if TUSB_MCU_VENDOR_ESPRESSIF #error "ESP32-Sx should use IDF's FreeRTOSConfig.h" #endif diff --git a/examples/device/cdc_msc_freertos/src/main.c b/examples/device/cdc_msc_freertos/src/main.c index f70267e33..a05ceff58 100644 --- a/examples/device/cdc_msc_freertos/src/main.c +++ b/examples/device/cdc_msc_freertos/src/main.c @@ -30,7 +30,7 @@ #include "bsp/board_api.h" #include "tusb.h" -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" @@ -111,14 +111,14 @@ int main(void) { #endif // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 -#if !TUP_MCU_ESPRESSIF +#if !TUSB_MCU_VENDOR_ESPRESSIF vTaskStartScheduler(); #endif return 0; } -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF void app_main(void) { main(); } diff --git a/examples/device/cdc_msc_freertos/src/tusb_config.h b/examples/device/cdc_msc_freertos/src/tusb_config.h index e743c9148..c3f2f7fb5 100644 --- a/examples/device/cdc_msc_freertos/src/tusb_config.h +++ b/examples/device/cdc_msc_freertos/src/tusb_config.h @@ -59,7 +59,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h index 869500ad2..902a54f08 100644 --- a/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h +++ b/examples/device/hid_composite_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -48,7 +48,7 @@ // Include MCU header #include "bsp/board_mcu.h" -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 +#if TUSB_MCU_VENDOR_ESPRESSIF #error "ESP32-Sx should use IDF's FreeRTOSConfig.h" #endif diff --git a/examples/device/hid_composite_freertos/src/main.c b/examples/device/hid_composite_freertos/src/main.c index ae091571e..30c0331ef 100644 --- a/examples/device/hid_composite_freertos/src/main.c +++ b/examples/device/hid_composite_freertos/src/main.c @@ -31,7 +31,7 @@ #include "tusb.h" #include "usb_descriptors.h" -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" @@ -113,14 +113,14 @@ int main(void) xTimerStart(blinky_tm, 0); // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 -#if !TUP_MCU_ESPRESSIF +#if !TUSB_MCU_VENDOR_ESPRESSIF vTaskStartScheduler(); #endif return 0; } -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF void app_main(void) { main(); diff --git a/examples/device/hid_composite_freertos/src/tusb_config.h b/examples/device/hid_composite_freertos/src/tusb_config.h index 0689e0f23..6ec38b95c 100644 --- a/examples/device/hid_composite_freertos/src/tusb_config.h +++ b/examples/device/hid_composite_freertos/src/tusb_config.h @@ -59,7 +59,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index aeeeb8930..8bb924c61 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -292,7 +292,7 @@ void led_blinking_task(void* param) { #define BLINKY_STACK_SIZE configMINIMAL_STACK_SIZE #define VIDEO_STACK_SIZE (configMINIMAL_STACK_SIZE*4) -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define USBD_STACK_SIZE 4096 int main(void); void app_main(void) { @@ -352,7 +352,7 @@ void freertos_init_task(void) { #endif // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 - #if !TUP_MCU_ESPRESSIF + #if !TUSB_MCU_VENDOR_ESPRESSIF vTaskStartScheduler(); #endif } diff --git a/examples/device/video_capture/src/tusb_config.h b/examples/device/video_capture/src/tusb_config.h index 3a6daa3d3..6dbd6f2a5 100644 --- a/examples/device/video_capture/src/tusb_config.h +++ b/examples/device/video_capture/src/tusb_config.h @@ -58,7 +58,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/device/video_capture_2ch/src/main.c b/examples/device/video_capture_2ch/src/main.c index dd6983766..245e7abb8 100644 --- a/examples/device/video_capture_2ch/src/main.c +++ b/examples/device/video_capture_2ch/src/main.c @@ -300,7 +300,7 @@ void led_blinking_task(void* param) { #define BLINKY_STACK_SIZE configMINIMAL_STACK_SIZE #define VIDEO_STACK_SIZE (configMINIMAL_STACK_SIZE*4) -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define USBD_STACK_SIZE 4096 int main(void); void app_main(void) { @@ -360,7 +360,7 @@ void freertos_init_task(void) { #endif // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 - #if !TUP_MCU_ESPRESSIF + #if !TUSB_MCU_VENDOR_ESPRESSIF vTaskStartScheduler(); #endif } diff --git a/examples/device/video_capture_2ch/src/tusb_config.h b/examples/device/video_capture_2ch/src/tusb_config.h index 43c7dfc90..91775a327 100644 --- a/examples/device/video_capture_2ch/src/tusb_config.h +++ b/examples/device/video_capture_2ch/src/tusb_config.h @@ -58,7 +58,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h b/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h index bd754518d..6a886adec 100644 --- a/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h +++ b/examples/host/cdc_msc_hid_freertos/src/FreeRTOSConfig/FreeRTOSConfig.h @@ -48,7 +48,7 @@ // Include MCU header #include "bsp/board_mcu.h" -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 +#if TUSB_MCU_VENDOR_ESPRESSIF #error "ESP32-Sx should use IDF's FreeRTOSConfig.h" #endif diff --git a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c index f3495ab28..dfe1418f6 100644 --- a/examples/host/cdc_msc_hid_freertos/src/cdc_app.c +++ b/examples/host/cdc_msc_hid_freertos/src/cdc_app.c @@ -27,7 +27,7 @@ #include "tusb.h" #include "bsp/board_api.h" -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" diff --git a/examples/host/cdc_msc_hid_freertos/src/main.c b/examples/host/cdc_msc_hid_freertos/src/main.c index 7fb84a40f..fe050d334 100644 --- a/examples/host/cdc_msc_hid_freertos/src/main.c +++ b/examples/host/cdc_msc_hid_freertos/src/main.c @@ -30,7 +30,7 @@ #include "bsp/board_api.h" #include "tusb.h" -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" @@ -107,14 +107,14 @@ int main(void) { xTimerStart(blinky_tm, 0); // skip starting scheduler (and return) for ESP32-S2 or ESP32-S3 -#if !TUP_MCU_ESPRESSIF +#if !TUSB_MCU_VENDOR_ESPRESSIF vTaskStartScheduler(); #endif return 0; } -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF void app_main(void) { main(); } diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h index 0aab2cd2f..02de4197b 100644 --- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h +++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h @@ -44,7 +44,7 @@ #endif // Espressif IDF requires "freertos/" prefix in include path -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF #define CFG_TUSB_OS_INC_PATH freertos/ #endif diff --git a/examples/typec/power_delivery/src/main.c b/examples/typec/power_delivery/src/main.c index a8214f34e..068dbbeb1 100644 --- a/examples/typec/power_delivery/src/main.c +++ b/examples/typec/power_delivery/src/main.c @@ -71,7 +71,7 @@ int main(void) } } -#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3 +#if TUSB_MCU_VENDOR_ESPRESSIF void app_main(void) { main(); diff --git a/hw/bsp/board_api.h b/hw/bsp/board_api.h index a458a3fdc..eaee1ee97 100644 --- a/hw/bsp/board_api.h +++ b/hw/bsp/board_api.h @@ -39,7 +39,7 @@ extern "C" { #include "tusb.h" #if CFG_TUSB_OS == OPT_OS_FREERTOS -#if TUP_MCU_ESPRESSIF +#if TUSB_MCU_VENDOR_ESPRESSIF // ESP-IDF need "freertos/" prefix in include path. // CFG_TUSB_OS_INC_PATH should be defined accordingly. #include "freertos/FreeRTOS.h" diff --git a/hw/bsp/broadcom_32bit/family.cmake b/hw/bsp/broadcom_32bit/family.cmake index 6205d4e1b..93e7d3545 100644 --- a/hw/bsp/broadcom_32bit/family.cmake +++ b/hw/bsp/broadcom_32bit/family.cmake @@ -97,6 +97,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_BCM2835 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/broadcom_64bit/family.cmake b/hw/bsp/broadcom_64bit/family.cmake index f373dc633..d790944bc 100644 --- a/hw/bsp/broadcom_64bit/family.cmake +++ b/hw/bsp/broadcom_64bit/family.cmake @@ -104,6 +104,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_BCM${BCM_VERSION} ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt index 26c7e4030..ae94a0ea4 100644 --- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt +++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt @@ -34,6 +34,8 @@ list(APPEND srcs ${tusb_src}/class/vendor/vendor_device.c ${tusb_src}/class/video/video_device.c ${tusb_src}/portable/synopsys/dwc2/dcd_dwc2.c + ${tusb_src}/portable/synopsys/dwc2/hcd_dwc2.c + ${tusb_src}/portable/synopsys/dwc2/dwc2_common.c # host ${tusb_src}/host/usbh.c ${tusb_src}/host/hub.c diff --git a/hw/bsp/gd32vf103/family.cmake b/hw/bsp/gd32vf103/family.cmake index 5f4a3da8d..1441e41de 100644 --- a/hw/bsp/gd32vf103/family.cmake +++ b/hw/bsp/gd32vf103/family.cmake @@ -108,6 +108,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_GD32VF103 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/stm32f2/family.cmake b/hw/bsp/stm32f2/family.cmake index a01ebef5c..538a6cd66 100644 --- a/hw/bsp/stm32f2/family.cmake +++ b/hw/bsp/stm32f2/family.cmake @@ -102,6 +102,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_STM32F2 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/stm32f4/family.cmake b/hw/bsp/stm32f4/family.cmake index f24ef366e..a2832763a 100644 --- a/hw/bsp/stm32f4/family.cmake +++ b/hw/bsp/stm32f4/family.cmake @@ -102,6 +102,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_STM32F4 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/stm32f7/family.cmake b/hw/bsp/stm32f7/family.cmake index 938c2697a..798dc4dbb 100644 --- a/hw/bsp/stm32f7/family.cmake +++ b/hw/bsp/stm32f7/family.cmake @@ -104,6 +104,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_STM32F7 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake index 6d7a97741..2ff874690 100644 --- a/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake +++ b/hw/bsp/stm32h7/boards/stm32h743eval/board.cmake @@ -1,6 +1,6 @@ set(MCU_VARIANT stm32h743xx) set(JLINK_DEVICE stm32h743xi) -# set(JLINK_OPTION "-USB jtrace") +set(JLINK_OPTION "-USB jtrace") set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/../../linker/${MCU_VARIANT}_flash.ld) diff --git a/hw/bsp/stm32u5/family.cmake b/hw/bsp/stm32u5/family.cmake index f7a7aeb33..3ab7cdf8b 100644 --- a/hw/bsp/stm32u5/family.cmake +++ b/hw/bsp/stm32u5/family.cmake @@ -102,16 +102,13 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_STM32U5 ${RTOS}) - if ((${MCU_VARIANT} STREQUAL "stm32u535xx") OR (${MCU_VARIANT} STREQUAL "stm32u545xx")) - target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c - ) - else () - target_sources(${TARGET}-tinyusb PUBLIC - ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c - #${TOP}/src/portable/st/typec/typec_stm32.c - ) - endif () + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c + #${TOP}/src/portable/st/typec/typec_stm32.c + ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) # Link dependencies diff --git a/hw/bsp/xmc4000/family.cmake b/hw/bsp/xmc4000/family.cmake index d91e6f0b6..85444db28 100644 --- a/hw/bsp/xmc4000/family.cmake +++ b/hw/bsp/xmc4000/family.cmake @@ -86,6 +86,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_XMC4000 ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/src/common/tusb_verify.h b/src/common/tusb_verify.h index 3e0f1f106..6d02d3572 100644 --- a/src/common/tusb_verify.h +++ b/src/common/tusb_verify.h @@ -83,7 +83,7 @@ if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */ \ } while(0) -#elif defined(__riscv) && !TUP_MCU_ESPRESSIF +#elif defined(__riscv) && !TUSB_MCU_VENDOR_ESPRESSIF #define TU_BREAKPOINT() do { __asm("ebreak\n"); } while(0) #elif defined(_mips) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index a9b3770ee..c67c34404 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -480,21 +480,28 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; dwc2_regs_t* dwc2 = DWC2_REG(rhport); - TU_ASSERT(dwc2_controller_init(rhport, rh_init)); + TU_ASSERT(dwc2_core_init(rhport, rh_init)); + + // Device Initialization dcd_disconnect(rhport); - // Restart PHY clock - dwc2->pcgctl &= ~(PCGCTL_STOPPCLK | PCGCTL_GATEHCLK | PCGCTL_PWRCLMP | PCGCTL_RSTPDWNMODULE); + // Set device max speed + uint32_t dcfg = dwc2->dcfg & ~DCFG_DSPD_Msk; + if (dwc2_core_is_highspeed(dwc2, rh_init)) { + dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos; + + // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required + // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347) + if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { + dcfg |= DCFG_XCVRDLY; + } + }else { + dcfg |= DCFG_DSPD_FS << DCFG_DSPD_Pos; + } + dwc2->dcfg = dcfg; - /* Set HS/FS Timeout Calibration to 7 (max available value). - * The number of PHY clocks that the application programs in - * this field is added to the high/full speed interpacket timeout - * duration in the core to account for any additional delays - * introduced by the PHY. This can be required, because the delay - * introduced by the PHY in generating the linestate condition - * can vary from one PHY to another. - */ - dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos); + // Enable PHY clock TODO stop/gate clock when suspended mode + dwc2->pcgcctl &= ~(PCGCCTL_STOPPCLK | PCGCCTL_GATEHCLK | PCGCCTL_PWRCLMP | PCGCCTL_RSTPDWNMODULE); // Force device mode dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD; @@ -502,8 +509,7 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Clear A override, force B Valid dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL; - // If USB host misbehaves during status portion of control xfer - // (non zero-length packet), send STALL back and discard. + // If USB host misbehaves during status portion of control xfer (non zero-length packet), send STALL back and discard dwc2->dcfg |= DCFG_NZLSOHSK; dfifo_flush_tx(dwc2, 0x10); // all tx fifo diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index 7fd2311db..190dc0734 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -30,7 +30,14 @@ #if defined(TUP_USBIP_DWC2) && (CFG_TUH_ENABLED || CFG_TUD_ENABLED) -#include "common/tusb_common.h" +#if CFG_TUD_ENABLED +#include "device/dcd.h" +#endif + +#if CFG_TUH_ENABLED +#include "host/hcd.h" +#endif + #include "dwc2_common.h" static void reset_core(dwc2_regs_t* dwc2) { @@ -47,18 +54,24 @@ static void reset_core(dwc2_regs_t* dwc2) { // wait for device mode ? } -static bool phy_hs_supported(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { +bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { (void) dwc2; +#if CFG_TUD_ENABLED + if (rh_init->role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) { + return false; + } +#endif +#if CFG_TUH_ENABLED + if (rh_init->role == TUSB_ROLE_DEVICE && !TUH_OPT_HIGH_SPEED) { + return false; + } +#endif -#if !TUD_OPT_HIGH_SPEED - return false; -#else return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED; -#endif } -static void phy_fs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { +static void phy_fs_init(dwc2_regs_t* dwc2) { TU_LOG(DWC2_COMMON_DEBUG, "Fullspeed PHY init\r\n"); // Select FS PHY @@ -77,12 +90,9 @@ static void phy_fs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { // MCU specific PHY update post reset dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED); - - // set max speed - dwc2->dcfg = (dwc2->dcfg & ~DCFG_DSPD_Msk) | (DCFG_DSPD_FS << DCFG_DSPD_Pos); } -static void phy_hs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { +static void phy_hs_init(dwc2_regs_t* dwc2) { uint32_t gusbcfg = dwc2->gusbcfg; // De-select FS PHY @@ -137,19 +147,6 @@ static void phy_hs_init(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { // MCU specific PHY update post reset dwc2_phy_update(dwc2, dwc2->ghwcfg2_bm.hs_phy_type); - - // Set max speed - uint32_t dcfg = dwc2->dcfg; - dcfg &= ~DCFG_DSPD_Msk; - dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos; - - // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required - // when using with some PHYs such as USB334x (USB3341, USB3343, USB3346, USB3347) - if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { - dcfg |= DCFG_XCVRDLY; - } - - dwc2->dcfg = dcfg; } static bool check_dwc2(dwc2_regs_t* dwc2) { @@ -177,19 +174,29 @@ static bool check_dwc2(dwc2_regs_t* dwc2) { //-------------------------------------------------------------------- // //-------------------------------------------------------------------- -bool dwc2_controller_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { +bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Check Synopsys ID register, failed if controller clock/power is not enabled TU_ASSERT(check_dwc2(dwc2)); - if (phy_hs_supported(dwc2, rh_init)) { - phy_hs_init(dwc2, rh_init); // Highspeed + if (dwc2_core_is_highspeed(dwc2, rh_init)) { + phy_hs_init(dwc2); // Highspeed } else { - phy_fs_init(dwc2, rh_init); // core does not support highspeed or hs phy is not present + phy_fs_init(dwc2); // core does not support highspeed or hs phy is not present } + /* Set HS/FS Timeout Calibration to 7 (max available value). + * The number of PHY clocks that the application programs in + * this field is added to the high/full speed interpacket timeout + * duration in the core to account for any additional delays + * introduced by the PHY. This can be required, because the delay + * introduced by the PHY in generating the linestate condition + * can vary from one PHY to another. + */ + dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos); + return true; } diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h index 2a48654c0..4039ebaa3 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.h +++ b/src/portable/synopsys/dwc2/dwc2_common.h @@ -27,6 +27,7 @@ #ifndef TUSB_DWC2_COMMON_H #define TUSB_DWC2_COMMON_H +#include "common/tusb_common.h" #include "dwc2_type.h" // Following symbols must be defined by port header @@ -64,7 +65,7 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { return (dwc2_regs_t*)_dwc2_controller[rhport].reg_base; } - -bool dwc2_controller_init(uint8_t rhport, const tusb_rhport_init_t* rh_init); +bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init); +bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init); #endif diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index 4cdbcdb7a..c8c5bffd0 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -25,13 +25,14 @@ */ -#ifndef _DWC2_ESP32_H_ -#define _DWC2_ESP32_H_ +#ifndef TUSB_DWC2_ESP32_H_ +#define TUSB_DWC2_ESP32_H_ #ifdef __cplusplus extern "C" { #endif +#include "freertos/FreeRTOS.h" #include "freertos/task.h" #include "esp_intr_alloc.h" diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index b9dc413b1..81e3ab6b8 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -464,8 +464,8 @@ typedef struct { uint32_t reservedd00[64]; // D00..DFF //------------- Power Clock -------------// - volatile uint32_t pcgctl; // E00 Power and Clock Gating Control - volatile uint32_t pcgctl1; // E04 + volatile uint32_t pcgcctl; // E00 Power and Clock Gating Characteristic Control + volatile uint32_t pcgcctl1; // E04 Power and Clock Gating Characteristic Control 1 uint32_t reservede08[126]; // E08..FFF //------------- FIFOs -------------// @@ -478,7 +478,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, channel) == 0x0500, "incorrect size"); TU_VERIFY_STATIC(offsetof(dwc2_regs_t, dcfg ) == 0x0800, "incorrect size"); TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epin ) == 0x0900, "incorrect size"); TU_VERIFY_STATIC(offsetof(dwc2_regs_t, epout ) == 0x0B00, "incorrect size"); -TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgctl ) == 0x0E00, "incorrect size"); +TU_VERIFY_STATIC(offsetof(dwc2_regs_t, pcgcctl) == 0x0E00, "incorrect size"); TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); //--------------------------------------------------------------------+ @@ -720,7 +720,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); /******************** Bit definition for GUSBCFG register ********************/ #define GUSBCFG_TOCAL_Pos (0U) #define GUSBCFG_TOCAL_Msk (0x7UL << GUSBCFG_TOCAL_Pos) // 0x00000007 -#define GUSBCFG_TOCAL GUSBCFG_TOCAL_Msk // FS timeout calibration +#define GUSBCFG_TOCAL GUSBCFG_TOCAL_Msk // HS/FS timeout calibration #define GUSBCFG_PHYIF16_Pos (3U) #define GUSBCFG_PHYIF16_Msk (0x1UL << GUSBCFG_PHYIF16_Pos) // 0x00000008 #define GUSBCFG_PHYIF16 GUSBCFG_PHYIF16_Msk // PHY Interface (PHYIf) @@ -1973,32 +1973,32 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DOEPTSIZ_STUPCNT_1 (0x2UL << DOEPTSIZ_STUPCNT_Pos) // 0x40000000 /******************** Bit definition for PCGCTL register ********************/ -#define PCGCTL_IF_DEV_MODE TU_BIT(31) -#define PCGCTL_P2HD_PRT_SPD_MASK (0x3ul << 29) -#define PCGCTL_P2HD_PRT_SPD_SHIFT 29 -#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3ul << 27) -#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27 -#define PCGCTL_MAC_DEV_ADDR_MASK (0x7ful << 20) -#define PCGCTL_MAC_DEV_ADDR_SHIFT 20 -#define PCGCTL_MAX_TERMSEL TU_BIT(19) -#define PCGCTL_MAX_XCVRSELECT_MASK (0x3ul << 17) -#define PCGCTL_MAX_XCVRSELECT_SHIFT 17 -#define PCGCTL_PORT_POWER TU_BIT(16) -#define PCGCTL_PRT_CLK_SEL_MASK (0x3ul << 14) -#define PCGCTL_PRT_CLK_SEL_SHIFT 14 -#define PCGCTL_ESS_REG_RESTORED TU_BIT(13) -#define PCGCTL_EXTND_HIBER_SWITCH TU_BIT(12) -#define PCGCTL_EXTND_HIBER_PWRCLMP TU_BIT(11) -#define PCGCTL_ENBL_EXTND_HIBER TU_BIT(10) -#define PCGCTL_RESTOREMODE TU_BIT(9) -#define PCGCTL_RESETAFTSUSP TU_BIT(8) -#define PCGCTL_DEEP_SLEEP TU_BIT(7) -#define PCGCTL_PHY_IN_SLEEP TU_BIT(6) -#define PCGCTL_ENBL_SLEEP_GATING TU_BIT(5) -#define PCGCTL_RSTPDWNMODULE TU_BIT(3) -#define PCGCTL_PWRCLMP TU_BIT(2) -#define PCGCTL_GATEHCLK TU_BIT(1) -#define PCGCTL_STOPPCLK TU_BIT(0) +#define PCGCCTL_IF_DEV_MODE TU_BIT(31) +#define PCGCCTL_P2HD_PRT_SPD_MASK (0x3ul << 29) +#define PCGCCTL_P2HD_PRT_SPD_SHIFT 29 +#define PCGCCTL_P2HD_DEV_ENUM_SPD_MASK (0x3ul << 27) +#define PCGCCTL_P2HD_DEV_ENUM_SPD_SHIFT 27 +#define PCGCCTL_MAC_DEV_ADDR_MASK (0x7ful << 20) +#define PCGCCTL_MAC_DEV_ADDR_SHIFT 20 +#define PCGCCTL_MAX_TERMSEL TU_BIT(19) +#define PCGCCTL_MAX_XCVRSELECT_MASK (0x3ul << 17) +#define PCGCCTL_MAX_XCVRSELECT_SHIFT 17 +#define PCGCCTL_PORT_POWER TU_BIT(16) +#define PCGCCTL_PRT_CLK_SEL_MASK (0x3ul << 14) +#define PCGCCTL_PRT_CLK_SEL_SHIFT 14 +#define PCGCCTL_ESS_REG_RESTORED TU_BIT(13) +#define PCGCCTL_EXTND_HIBER_SWITCH TU_BIT(12) +#define PCGCCTL_EXTND_HIBER_PWRCLMP TU_BIT(11) +#define PCGCCTL_ENBL_EXTND_HIBER TU_BIT(10) +#define PCGCCTL_RESTOREMODE TU_BIT(9) +#define PCGCCTL_RESETAFTSUSP TU_BIT(8) +#define PCGCCTL_DEEP_SLEEP TU_BIT(7) +#define PCGCCTL_PHY_IN_SLEEP TU_BIT(6) +#define PCGCCTL_ENBL_SLEEP_GATING TU_BIT(5) +#define PCGCCTL_RSTPDWNMODULE TU_BIT(3) +#define PCGCCTL_PWRCLMP TU_BIT(2) +#define PCGCCTL_GATEHCLK TU_BIT(1) +#define PCGCCTL_STOPPCLK TU_BIT(0) #define PCGCTL1_TIMER (0x3ul << 1) #define PCGCTL1_GATEEN TU_BIT(0) diff --git a/src/tusb_option.h b/src/tusb_option.h index fdc949747..d36d0bcad 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -125,7 +125,8 @@ #define OPT_MCU_ESP32C2 905 ///< Espressif ESP32-C2 #define OPT_MCU_ESP32H2 906 ///< Espressif ESP32-H2 #define OPT_MCU_ESP32P4 907 ///< Espressif ESP32-P4 -#define TUP_MCU_ESPRESSIF (CFG_TUSB_MCU >= 900 && CFG_TUSB_MCU < 1000) // check if Espressif MCU +#define TUSB_MCU_VENDOR_ESPRESSIF (CFG_TUSB_MCU >= 900 && CFG_TUSB_MCU < 1000) // check if Espressif MCU +#define TUP_MCU_ESPRESSIF TUSB_MCU_VENDOR_ESPRESSIF // for backward compatibility // Dialog #define OPT_MCU_DA1469X 1000 ///< Dialog Semiconductor DA1469x diff --git a/tools/build_utils.py b/tools/build_utils.py index 5462829e2..b4a1dc096 100755 --- a/tools/build_utils.py +++ b/tools/build_utils.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 import subprocess import pathlib -import time +import re build_format = '| {:29} | {:30} | {:18} | {:7} | {:6} | {:6} |' @@ -36,18 +36,21 @@ def skip_example(example, board): mk_contents = board_mk.read_text() mcu = "NONE" - for token in mk_contents.split(): - if "CFG_TUSB_MCU=OPT_MCU_" in token: - # Strip " because cmake files has them. - token = token.strip("\"") - _, opt_mcu = token.split("=") - mcu = opt_mcu[len("OPT_MCU_"):] - if "esp32s2" in token: - mcu = "ESP32S2" - if "esp32s3" in token: - mcu = "ESP32S3" - if mcu != "NONE": - break + if family == "espressif": + for line in mk_contents.splitlines(): + match = re.search(r'set\(IDF_TARGET\s+"([^"]+)"\)', line) + if match: + mcu = match.group(1) + break + else: + for token in mk_contents.split(): + if "CFG_TUSB_MCU=OPT_MCU_" in token: + # Strip " because cmake files has them. + token = token.strip("\"") + _, opt_mcu = token.split("=") + mcu = opt_mcu[len("OPT_MCU_"):] + if mcu != "NONE": + break # Skip all OPT_MCU_NONE these are WIP port if mcu == "NONE": -- cgit v1.3.1 From 1b17bc04f964301857abb80e9a9ed46f02803fc1 Mon Sep 17 00:00:00 2001 From: pschatzmann Date: Tue, 15 Oct 2024 22:22:24 +0200 Subject: RP2040 New ISO API --- src/class/video/video_device.c | 2 +- src/common/tusb_mcu.h | 1 + src/portable/raspberrypi/rp2040/dcd_rp2040.c | 99 ++++++++++++++++++++++------ 3 files changed, 81 insertions(+), 21 deletions(-) (limited to 'src/portable') diff --git a/src/class/video/video_device.c b/src/class/video/video_device.c index 70dbb5b9e..ec41e0991 100644 --- a/src/class/video/video_device.c +++ b/src/class/video/video_device.c @@ -1307,7 +1307,7 @@ uint16_t videod_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uin #ifdef TUP_DCD_EDPT_ISO_ALLOC /* Allocate ISO endpoints */ uint16_t ep_size = 0; - uint16_t ep_addr = 0; + uint8_t ep_addr = 0; uint8_t const *p_desc = (uint8_t const*)itf_desc + stm->desc.beg; uint8_t const *p_desc_end = (uint8_t const*)itf_desc + stm->desc.end; while (p_desc < p_desc_end) { diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index c77afecad..c64356028 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -366,6 +366,7 @@ // Raspberry Pi //--------------------------------------------------------------------+ #elif TU_CHECK_MCU(OPT_MCU_RP2040) + #define TUP_DCD_EDPT_ISO_ALLOC #define TUP_DCD_ENDPOINT_MAX 16 #define TU_ATTR_FAST_FUNC __attribute__((section(".time_critical.tinyusb"))) diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index 2e177d5cb..bb0a2f3fb 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -46,9 +46,11 @@ /*------------------------------------------------------------------*/ /* Low level controller *------------------------------------------------------------------*/ +static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type); +static void hw_set_endpoint_control_reg(struct hw_endpoint* ep, uint dpram_offset); // Init these in dcd_init -static uint8_t* next_buffer_ptr; +static uint8_t* next_buffer_ptr = NULL; // USB_MAX_ENDPOINTS Endpoints, direction TUSB_DIR_OUT for out and TUSB_DIR_IN for in. static struct hw_endpoint hw_endpoints[USB_MAX_ENDPOINTS][2]; @@ -66,31 +68,82 @@ TU_ATTR_ALWAYS_INLINE static inline struct hw_endpoint* hw_endpoint_get_by_addr( return hw_endpoint_get_by_num(num, dir); } -static void _hw_endpoint_alloc(struct hw_endpoint* ep, uint8_t transfer_type) { +// Allocate from the USB buffer space (max 3840 bytes) +static void hw_endpoint_alloc(struct hw_endpoint* ep, size_t size) { + static uint8_t *end; + // determine buffer end + if (end == NULL){ + end = &usb_dpram->epx_data[0] + 0xF00; + } + // determine first next_buffer_ptr if necessary + if (next_buffer_ptr == NULL){ + next_buffer_ptr = &usb_dpram->epx_data[0]; + } + // assign buffer + ep->hw_data_buf = next_buffer_ptr; + next_buffer_ptr += size; + + hard_assert(next_buffer_ptr < end); + + pico_info(" Allocated %d bytes (0x%p)\r\n", size, ep->hw_data_buf); +} + +// allocate endpoint and fill endpoint control registers +static void hw_endpoint_alloc_and_control(struct hw_endpoint* ep, uint8_t transfer_type) { // size must be multiple of 64 uint size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u; - // double buffered Bulk endpoint if (transfer_type == TUSB_XFER_BULK) { size *= 2u; } + ep->transfer_type = transfer_type; + hw_endpoint_alloc(ep, size); - ep->hw_data_buf = next_buffer_ptr; - next_buffer_ptr += size; - - assert(((uintptr_t) next_buffer_ptr & 0b111111u) == 0); uint dpram_offset = hw_data_offset(ep->hw_data_buf); - hard_assert(hw_data_offset(next_buffer_ptr) <= USB_DPRAM_MAX); - pico_info(" Allocated %d bytes at offset 0x%x (0x%p)\r\n", size, dpram_offset, ep->hw_data_buf); - // Fill in endpoint control register with buffer offset - uint32_t const reg = EP_CTRL_ENABLE_BITS | ((uint) transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset; + hw_set_endpoint_control_reg(ep, dpram_offset); +} +static void hw_set_endpoint_control_reg(struct hw_endpoint* ep, uint dpram_offset) { + // Fill in endpoint control register with buffer offset + uint32_t const reg = EP_CTRL_ENABLE_BITS | ((uint) ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset; *ep->endpoint_control = reg; } -static void _hw_endpoint_close(struct hw_endpoint* ep) { +// New API: Allocate packet buffer used by ISO endpoints +// Some MCU need manual packet buffer allocation, we allocate the largest size to avoid clustering +bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { + (void) rhport; + assert(rhport == 0); + struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); + // size must be multiple of 64 + uint16_t size = (uint16_t)tu_div_ceil(largest_packet_size, 64) * 64u; + ep->wMaxPacketSize = size; + hw_endpoint_alloc(ep, size); + return true; +} + +// New API: Configure and enable an ISO endpoint according to descriptor +bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { + (void) rhport; + assert(rhport == 0); + const uint8_t ep_addr = ep_desc->bEndpointAddress; + const uint16_t mps = ep_desc->wMaxPacketSize; + uint16_t size = (uint16_t)tu_div_ceil(mps, 64) * 64u; + + // init w/o allocate + hw_endpoint_init(ep_addr, size, TUSB_XFER_ISOCHRONOUS); + + // Fill in endpoint control register with buffer offset + struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); + uint dpram_offset = hw_data_offset(ep->hw_data_buf); + hw_set_endpoint_control_reg(ep, dpram_offset); + return true; +} + +static void hw_endpoint_close(uint8_t ep_addr) { + struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); // Clear hardware registers and then zero the struct // Clears endpoint enable *ep->endpoint_control = 0; @@ -113,11 +166,20 @@ static void _hw_endpoint_close(struct hw_endpoint* ep) { } } -static void hw_endpoint_close(uint8_t ep_addr) { +// Legacy init called by dcd_init (which does allocation) +static void hw_endpoint_init_and_alloc(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type) { struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); - _hw_endpoint_close(ep); + uint16_t size = (uint16_t) tu_div_ceil(wMaxPacketSize, 64) * 64u; + // size must be multiple of 64 + hw_endpoint_init(ep_addr, size, transfer_type); + const uint8_t num = tu_edpt_number(ep_addr); + if (num != 0) { + // alloc a buffer and fill in endpoint control register + hw_endpoint_alloc_and_control(ep, transfer_type); + } } +// main processing for dcd_edpt_iso_activate static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type) { struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); @@ -156,9 +218,6 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t t } else { ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].out; } - - // alloc a buffer and fill in endpoint control register - _hw_endpoint_alloc(ep, transfer_type); } } @@ -387,8 +446,8 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Init control endpoints tu_memclr(hw_endpoints[0], 2 * sizeof(hw_endpoint_t)); - hw_endpoint_init(0x0, 64, TUSB_XFER_CONTROL); - hw_endpoint_init(0x80, 64, TUSB_XFER_CONTROL); + hw_endpoint_init_and_alloc(0x0, 64, TUSB_XFER_CONTROL); + hw_endpoint_init_and_alloc(0x80, 64, TUSB_XFER_CONTROL); // Init non-control endpoints reset_non_control_endpoints(); @@ -495,7 +554,7 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const* req bool dcd_edpt_open(__unused uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) { assert(rhport == 0); - hw_endpoint_init(desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt), desc_edpt->bmAttributes.xfer); + hw_endpoint_init_and_alloc(desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt), desc_edpt->bmAttributes.xfer); return true; } -- cgit v1.3.1 From 8d9d3d9a2ac51378e7cb973628972e93ba356e1d Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 16 Oct 2024 13:19:28 +0700 Subject: move gahbcfg/gintmsk with dma to dwc2 common --- src/portable/synopsys/dwc2/dcd_dwc2.c | 84 +++------------------ src/portable/synopsys/dwc2/dwc2_common.c | 35 ++++++++- src/portable/synopsys/dwc2/dwc2_common.h | 37 ++++++++++ src/portable/synopsys/dwc2/dwc2_type.h | 121 ++++++++++++++++++------------- src/portable/synopsys/dwc2/hcd_dwc2.c | 64 ++++++++++++++-- src/tusb_option.h | 4 + 6 files changed, 212 insertions(+), 133 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index c67c34404..6760af3f3 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -68,22 +68,6 @@ static bool _sof_en; // DMA //-------------------------------------------------------------------- -TU_ATTR_ALWAYS_INLINE static inline bool dma_enabled(const dwc2_regs_t* dwc2) { - #if !CFG_TUD_DWC2_DMA - (void) dwc2; - return false; - #else - // Internal DMA only - return (dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA); - #endif -} - -TU_ATTR_ALWAYS_INLINE static inline uint16_t dma_cal_epfifo_base(uint8_t rhport) { - // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per endpoint direction - const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport]; - return dwc2_controller->ep_fifo_size/4 - 2*dwc2_controller->ep_count; -} - static void dma_setup_prepare(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); @@ -103,16 +87,6 @@ static void dma_setup_prepare(uint8_t rhport) { // Data FIFO //--------------------------------------------------------------------+ -TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_tx(dwc2_regs_t* dwc2, uint8_t epnum) { - // flush TX fifo and wait for it cleared - dwc2->grstctl = GRSTCTL_TXFFLSH | (epnum << GRSTCTL_TXFNUM_Pos); - while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {} -} -TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_rx(dwc2_regs_t* dwc2) { - // flush RX fifo and wait for it cleared - dwc2->grstctl = GRSTCTL_RXFFLSH; - while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {} -} /* USB Data FIFO Layout @@ -215,7 +189,7 @@ static void dfifo_init(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); dwc2->grxfsiz = calc_grxfsiz(CFG_TUD_ENDPOINT0_SIZE, dwc2_controller->ep_count); - if(dma_enabled(dwc2)) { + if(dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE)) { // DMA use last DFIFO to store metadata _dfifo_top = dma_cal_epfifo_base(rhport); }else { @@ -395,7 +369,7 @@ static void bus_reset(uint8_t rhport) { xfer_status[0][TUSB_DIR_OUT].max_size = 64; xfer_status[0][TUSB_DIR_IN].max_size = 64; - if(dma_enabled(dwc2)) { + if(dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE)) { dma_setup_prepare(rhport); } else { dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); @@ -427,7 +401,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c dep->dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); - if(dma_enabled(dwc2)) { + if(dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE)) { dep->diepdma = (uintptr_t)xfer->buffer; // For ISO endpoint set correct odd/even bit for next frame. @@ -465,7 +439,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c dep->doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); } - if(dma_enabled(dwc2)) { + if(dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE)) { dep->doepdma = (uintptr_t)xfer->buffer; } @@ -477,9 +451,9 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c // Controller API //-------------------------------------------------------------------- bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { - (void) rh_init; dwc2_regs_t* dwc2 = DWC2_REG(rhport); + // Core Initialization TU_ASSERT(dwc2_core_init(rhport, rh_init)); // Device Initialization @@ -500,9 +474,6 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { } dwc2->dcfg = dcfg; - // Enable PHY clock TODO stop/gate clock when suspended mode - dwc2->pcgcctl &= ~(PCGCCTL_STOPPCLK | PCGCCTL_GATEHCLK | PCGCCTL_PWRCLMP | PCGCCTL_RSTPDWNMODULE); - // Force device mode dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD; @@ -512,44 +483,13 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // If USB host misbehaves during status portion of control xfer (non zero-length packet), send STALL back and discard dwc2->dcfg |= DCFG_NZLSOHSK; - dfifo_flush_tx(dwc2, 0x10); // all tx fifo - dfifo_flush_rx(dwc2); - - // Clear all interrupts - uint32_t int_mask = dwc2->gintsts; - dwc2->gintsts |= int_mask; - int_mask = dwc2->gotgint; - dwc2->gotgint |= int_mask; - - // Required as part of core initialization. - dwc2->gintmsk = GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM; + // Enable required interrupts + dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM; // Configure TX FIFO empty level for interrupt. Default is complete empty dwc2->gahbcfg |= GAHBCFG_TXFELVL; - if (dma_enabled(dwc2)) { - const uint16_t epinfo_base = dma_cal_epfifo_base(rhport); - dwc2->gdfifocfg = (epinfo_base << GDFIFOCFG_EPINFOBASE_SHIFT) | epinfo_base; - - // DMA seems to be only settable after a core reset - dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2; - }else { - dwc2->gintmsk |= GINTMSK_RXFLVLM; - } - - // Enable global interrupt - dwc2->gahbcfg |= GAHBCFG_GINT; - - // make sure we are in device mode -// TU_ASSERT(!(dwc2->gintsts & GINTSTS_CMOD), ); - -// TU_LOG_HEX(DWC2_DEBUG, dwc2->gotgctl); -// TU_LOG_HEX(DWC2_DEBUG, dwc2->gusbcfg); -// TU_LOG_HEX(DWC2_DEBUG, dwc2->dcfg); -// TU_LOG_HEX(DWC2_DEBUG, dwc2->gahbcfg); - dcd_connect(rhport); - return true; } @@ -749,7 +689,7 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { edpt_disable(rhport, ep_addr, true); - if((tu_edpt_number(ep_addr) == 0) && dma_enabled(DWC2_REG(rhport))) { + if((tu_edpt_number(ep_addr) == 0) && dwc2_dma_enabled(DWC2_REG(rhport), TUSB_ROLE_DEVICE)) { dma_setup_prepare(rhport); } } @@ -866,7 +806,7 @@ static void handle_epout_irq(uint8_t rhport) { if (doepint & DOEPINT_SETUP) { epout->doepint = DOEPINT_SETUP; - if(dma_enabled(dwc2)) { + if(dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE)) { dma_setup_prepare(rhport); } @@ -882,7 +822,7 @@ static void handle_epout_irq(uint8_t rhport) { if (!(doepint & (DOEPINT_SETUP | DOEPINT_STPKTRX | DOEPINT_STSPHSRX))) { xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - if(dma_enabled(dwc2)) { + if(dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE)) { if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { // EP0 can only handle one packet Schedule another packet to be received. edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); @@ -932,7 +872,7 @@ static void handle_epin_irq(uint8_t rhport) { // Schedule another packet to be transmitted. edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); } else { - if((n == 0) && dma_enabled(dwc2)) { + if((n == 0) && dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE)) { dma_setup_prepare(rhport); } dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); @@ -982,7 +922,7 @@ static void handle_epin_irq(uint8_t rhport) { /* Interrupt Hierarchy - DxEPMSK.XferComplMsk DxEPINTn.XferCompl + DxEPINTn.XferCompl DxEPMSK.XferComplMsk | | +---------- AND --------+ | diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index 190dc0734..50d0c28b3 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -63,7 +63,7 @@ bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init } #endif #if CFG_TUH_ENABLED - if (rh_init->role == TUSB_ROLE_DEVICE && !TUH_OPT_HIGH_SPEED) { + if (rh_init->role == TUSB_ROLE_HOST && !TUH_OPT_HIGH_SPEED) { return false; } #endif @@ -193,10 +193,39 @@ bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { * duration in the core to account for any additional delays * introduced by the PHY. This can be required, because the delay * introduced by the PHY in generating the linestate condition - * can vary from one PHY to another. - */ + * can vary from one PHY to another. */ dwc2->gusbcfg |= (7ul << GUSBCFG_TOCAL_Pos); + // Enable PHY clock TODO stop/gate clock when suspended mode + dwc2->pcgcctl &= ~(PCGCCTL_STOPPCLK | PCGCCTL_GATEHCLK | PCGCCTL_PWRCLMP | PCGCCTL_RSTPDWNMODULE); + + dfifo_flush_tx(dwc2, 0x10); // all tx fifo + dfifo_flush_rx(dwc2); + + // Clear all pending interrupts + uint32_t int_mask; + + int_mask = dwc2->gintsts; + dwc2->gintsts |= int_mask; + + int_mask = dwc2->gotgint; + dwc2->gotgint |= int_mask; + + dwc2->gintmsk = GINTMSK_OTGINT; + + if (dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE)) { + const uint16_t epinfo_base = dma_cal_epfifo_base(rhport); + dwc2->gdfifocfg = (epinfo_base << GDFIFOCFG_EPINFOBASE_SHIFT) | epinfo_base; + + // DMA seems to be only settable after a core reset, and not possible to switch on-the-fly + dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2; + }else { + dwc2->gintmsk |= GINTMSK_RXFLVLM; + } + + // Enable global interrupt + dwc2->gahbcfg |= GAHBCFG_GINT; + return true; } diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h index 4039ebaa3..538fcd179 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.h +++ b/src/portable/synopsys/dwc2/dwc2_common.h @@ -57,6 +57,8 @@ enum { DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller) }; + +//------------- Core -------------// TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { if (rhport >= DWC2_CONTROLLER_COUNT) { // user mis-configured, ignore and use first controller @@ -68,4 +70,39 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init); bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init); +//------------- DFIFO -------------// +TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_tx(dwc2_regs_t* dwc2, uint8_t fnum) { + // flush TX fifo and wait for it cleared + dwc2->grstctl = GRSTCTL_TXFFLSH | (fnum << GRSTCTL_TXFNUM_Pos); + while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {} +} +TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_rx(dwc2_regs_t* dwc2) { + // flush RX fifo and wait for it cleared + dwc2->grstctl = GRSTCTL_RXFFLSH; + while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {} +} + +//------------- DMA -------------// +TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dma_enabled(const dwc2_regs_t* dwc2, tusb_role_t role) { + (void) dwc2; + + if (CFG_TUD_DWC2_DMA == 0 && role == TUSB_ROLE_DEVICE) { + return false; + } + + if (CFG_TUH_DWC2_DMA == 0 && role == TUSB_ROLE_HOST) { + return false; + } + + // Internal DMA only + return dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; +} + +TU_ATTR_ALWAYS_INLINE static inline uint16_t dma_cal_epfifo_base(uint8_t rhport) { + // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per endpoint direction + const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport]; + return dwc2_controller->ep_fifo_size/4 - 2*dwc2_controller->ep_count; +} + + #endif diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 81e3ab6b8..c8f6a5d1f 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -122,6 +122,12 @@ enum { GHWCFFG4_PHY_DATA_WIDTH_8_16 = 2, // software selectable }; +enum { + HPRT_SPEED_HIGH = 0, + HPRT_SPEED_FULL = 1, + HPRT_SPEED_LOW = 2 +}; + //-------------------------------------------------------------------- // Register bitfield definitions //-------------------------------------------------------------------- @@ -301,6 +307,24 @@ typedef struct TU_ATTR_PACKED { }dwc2_ghwcfg4_t; TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size"); +typedef struct TU_ATTR_PACKED { + uint32_t conn_status : 1; // 0 Port connect status + uint32_t conn_detected : 1; // 1 Port connect detected + uint32_t enable : 1; // 2 Port enable status + uint32_t enable_change : 1; // 3 Port enable change + uint32_t over_current_active : 1; // 4 Port Over-current active + uint32_t over_current_change : 1; // 5 Port Over-current change + uint32_t resume : 1; // 6 Port resume + uint32_t suspend : 1; // 7 Port suspend + uint32_t reset : 1; // 8 Port reset + uint32_t rsv9 : 1; // 9 Reserved + uint32_t line_status : 2; // 10..11 Line status + uint32_t power : 1; // 12 Port power + uint32_t test_control : 4; // 13..16 Port Test control + uint32_t speed : 2; // 17..18 Port speed + uint32_t rsv19_31 :13; // 19..31 Reserved +}dwc2_hprt_t; + // Host Channel typedef struct { volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics @@ -1448,56 +1472,53 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DIEPEACHMSK1_NAKM DIEPEACHMSK1_NAKM_Msk // NAK interrupt mask /******************** Bit definition for HPRT register ********************/ -#define HPRT_PCSTS_Pos (0U) -#define HPRT_PCSTS_Msk (0x1UL << HPRT_PCSTS_Pos) // 0x00000001 -#define HPRT_PCSTS HPRT_PCSTS_Msk // Port connect status -#define HPRT_PCDET_Pos (1U) -#define HPRT_PCDET_Msk (0x1UL << HPRT_PCDET_Pos) // 0x00000002 -#define HPRT_PCDET HPRT_PCDET_Msk // Port connect detected -#define HPRT_PENA_Pos (2U) -#define HPRT_PENA_Msk (0x1UL << HPRT_PENA_Pos) // 0x00000004 -#define HPRT_PENA HPRT_PENA_Msk // Port enable -#define HPRT_PENCHNG_Pos (3U) -#define HPRT_PENCHNG_Msk (0x1UL << HPRT_PENCHNG_Pos) // 0x00000008 -#define HPRT_PENCHNG HPRT_PENCHNG_Msk // Port enable/disable change -#define HPRT_POCA_Pos (4U) -#define HPRT_POCA_Msk (0x1UL << HPRT_POCA_Pos) // 0x00000010 -#define HPRT_POCA HPRT_POCA_Msk // Port overcurrent active -#define HPRT_POCCHNG_Pos (5U) -#define HPRT_POCCHNG_Msk (0x1UL << HPRT_POCCHNG_Pos) // 0x00000020 -#define HPRT_POCCHNG HPRT_POCCHNG_Msk // Port overcurrent change -#define HPRT_PRES_Pos (6U) -#define HPRT_PRES_Msk (0x1UL << HPRT_PRES_Pos) // 0x00000040 -#define HPRT_PRES HPRT_PRES_Msk // Port resume -#define HPRT_PSUSP_Pos (7U) -#define HPRT_PSUSP_Msk (0x1UL << HPRT_PSUSP_Pos) // 0x00000080 -#define HPRT_PSUSP HPRT_PSUSP_Msk // Port suspend -#define HPRT_PRST_Pos (8U) -#define HPRT_PRST_Msk (0x1UL << HPRT_PRST_Pos) // 0x00000100 -#define HPRT_PRST HPRT_PRST_Msk // Port reset - -#define HPRT_PLSTS_Pos (10U) -#define HPRT_PLSTS_Msk (0x3UL << HPRT_PLSTS_Pos) // 0x00000C00 -#define HPRT_PLSTS HPRT_PLSTS_Msk // Port line status -#define HPRT_PLSTS_0 (0x1UL << HPRT_PLSTS_Pos) // 0x00000400 -#define HPRT_PLSTS_1 (0x2UL << HPRT_PLSTS_Pos) // 0x00000800 -#define HPRT_PPWR_Pos (12U) -#define HPRT_PPWR_Msk (0x1UL << HPRT_PPWR_Pos) // 0x00001000 -#define HPRT_PPWR HPRT_PPWR_Msk // Port power - -#define HPRT_PTCTL_Pos (13U) -#define HPRT_PTCTL_Msk (0xFUL << HPRT_PTCTL_Pos) // 0x0001E000 -#define HPRT_PTCTL HPRT_PTCTL_Msk // Port test control -#define HPRT_PTCTL_0 (0x1UL << HPRT_PTCTL_Pos) // 0x00002000 -#define HPRT_PTCTL_1 (0x2UL << HPRT_PTCTL_Pos) // 0x00004000 -#define HPRT_PTCTL_2 (0x4UL << HPRT_PTCTL_Pos) // 0x00008000 -#define HPRT_PTCTL_3 (0x8UL << HPRT_PTCTL_Pos) // 0x00010000 - -#define HPRT_PSPD_Pos (17U) -#define HPRT_PSPD_Msk (0x3UL << HPRT_PSPD_Pos) // 0x00060000 -#define HPRT_PSPD HPRT_PSPD_Msk // Port speed -#define HPRT_PSPD_0 (0x1UL << HPRT_PSPD_Pos) // 0x00020000 -#define HPRT_PSPD_1 (0x2UL << HPRT_PSPD_Pos) // 0x00040000 +#define HPRT_CONN_STATUS_Pos (0U) +#define HPRT_CONN_STATUS_Msk (0x1UL << HPRT_CONN_STATUS_Pos) // 0x00000001 +#define HPRT_CONN_STATUS HPRT_CONN_STATUS_Msk // Port connect status +#define HPRT_CONN_DETECTEDT_Pos (1U) +#define HPRT_CONN_DETECTEDT_Msk (0x1UL << HPRT_CONN_DETECTEDT_Pos) // 0x00000002 +#define HPRT_CONN_DETECTEDT HPRT_CONN_DETECTEDT_Msk // Port connect detected +#define HPRT_ENABLE_Pos (2U) +#define HPRT_ENABLE_Msk (0x1UL << HPRT_ENABLE_Pos) // 0x00000004 +#define HPRT_ENABLE HPRT_ENABLE_Msk // Port enable +#define HPRT_EN_CHANGE_Pos (3U) +#define HPRT_EN_CHANGE_Msk (0x1UL << HPRT_EN_CHANGE_Pos) // 0x00000008 +#define HPRT_EN_CHANGE HPRT_EN_CHANGE_Msk // Port enable/disable change +#define HPRT_OVER_CURRENT_ACTIVE_Pos (4U) +#define HPRT_OVER_CURRENT_ACTIVE_Msk (0x1UL << HPRT_OVER_CURRENT_ACTIVE_Pos) // 0x00000010 +#define HPRT_OVER_CURRENT_ACTIVE HPRT_OVER_CURRENT_ACTIVE_Msk // Port overcurrent active +#define HPRT_OVER_CURRENT_CHANGE_Pos (5U) +#define HPRT_OVER_CURRENT_CHANGE_Msk (0x1UL << HPRT_OVER_CURRENT_CHANGE_Pos) // 0x00000020 +#define HPRT_OVER_CURRENT_CHANGE HPRT_OVER_CURRENT_CHANGE_Msk // Port overcurrent change +#define HPRT_RESUME_Pos (6U) +#define HPRT_RESUME_Msk (0x1UL << HPRT_RESUME_Pos) // 0x00000040 +#define HPRT_RESUME HPRT_RESUME_Msk // Port resume +#define HPRT_SUSPEND_Pos (7U) +#define HPRT_SUSPEND_Msk (0x1UL << HPRT_SUSPEND_Pos) // 0x00000080 +#define HPRT_SUSPEND HPRT_SUSPEND_Msk // Port suspend +#define HPRT_RESET_Pos (8U) +#define HPRT_RESET_Msk (0x1UL << HPRT_RESET_Pos) // 0x00000100 +#define HPRT_RESET HPRT_RESET_Msk // Port reset +#define HPRT_LINE_STATUS_Pos (10U) +#define HPRT_LINE_STATUS_Msk (0x3UL << HPRT_LINE_STATUS_Pos) // 0x00000C00 +#define HPRT_LINE_STATUS HPRT_LINE_STATUS_Msk // Port line status +#define HPRT_LINE_STATUS_0 (0x1UL << HPRT_LINE_STATUS_Pos) // 0x00000400 +#define HPRT_LINE_STATUS_1 (0x2UL << HPRT_LINE_STATUS_Pos) // 0x00000800 +#define HPRT_POWER_Pos (12U) +#define HPRT_POWER_Msk (0x1UL << HPRT_POWER_Pos) // 0x00001000 +#define HPRT_POWER HPRT_POWER_Msk // Port power +#define HPRT_TEST_CONTROL_Pos (13U) +#define HPRT_TEST_CONTROL_Msk (0xFUL << HPRT_TEST_CONTROL_Pos) // 0x0001E000 +#define HPRT_TEST_CONTROL HPRT_TEST_CONTROL_Msk // Port test control +#define HPRT_TEST_CONTROL_0 (0x1UL << HPRT_TEST_CONTROL_Pos) // 0x00002000 +#define HPRT_TEST_CONTROL_1 (0x2UL << HPRT_TEST_CONTROL_Pos) // 0x00004000 +#define HPRT_TEST_CONTROL_2 (0x4UL << HPRT_TEST_CONTROL_Pos) // 0x00008000 +#define HPRT_TEST_CONTROL_3 (0x8UL << HPRT_TEST_CONTROL_Pos) // 0x00010000 +#define HPRT_SPEED_Pos (17U) +#define HPRT_SPEED_Msk (0x3UL << HPRT_SPEED_Pos) // 0x00060000 +#define HPRT_SPEED HPRT_SPEED_Msk // Port speed +#define HPRT_SPEED_0 (0x1UL << HPRT_SPEED_Pos) // 0x00020000 +#define HPRT_SPEED_1 (0x2UL << HPRT_SPEED_Pos) // 0x00040000 /******************** Bit definition for DOEPEACHMSK1 register ********************/ #define DOEPEACHMSK1_XFRCM_Pos (0U) diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 8798f982c..b383b4069 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -49,15 +49,29 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { // Initialize controller to host mode bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { - (void) rhport; - (void) rh_init; - return false; -} + dwc2_regs_t* dwc2 = DWC2_REG(rhport); -// Interrupt Handler -void hcd_int_handler(uint8_t rhport, bool in_isr) { - (void) rhport; - (void) in_isr; + // Core Initialization + TU_ASSERT(dwc2_core_init(rhport, rh_init)); + + // force host mode + dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD; + + //------------- 3.1 Host Initialization -------------// + // Enable required interrupts + dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_PRTIM | GINTMSK_WUIM; + + // max speed + if (dwc2_core_is_highspeed(dwc2, rh_init)) { + dwc2->hcfg &= ~HCFG_FSLSS; + } else { + dwc2->hcfg |= HCFG_FSLSS; + } + + // port power on -> drive VBUS + dwc2->hprt = HPRT_POWER; + + return true; } // Enable USB interrupt @@ -164,4 +178,38 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { return false; } +//-------------------------------------------------------------------- +// HCD Event Handler +//-------------------------------------------------------------------- + +/* Interrupt Hierarchy + + HCINTn.XferCompl HCINTMSKn.XferComplMsk + | | + +---------- AND --------+ + | + HAINT.CHn HAINTMSK.CHn + | | + +---------- AND --------+ + | + GINTSTS.PrtInt GINTMSK.PrtInt + | | + +---------- AND --------+ + | + GAHBCFG.GblIntrMsk + | + IRQn + */ +void hcd_int_handler(uint8_t rhport, bool in_isr) { + (void) in_isr; + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + + const uint32_t int_mask = dwc2->gintmsk; + const uint32_t int_status = dwc2->gintsts & int_mask; + + if (int_status & GINTSTS_HPRTINT) { + TU_LOG1_HEX(dwc2->hprt); + } +} + #endif diff --git a/src/tusb_option.h b/src/tusb_option.h index d36d0bcad..3607a8c1a 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -254,6 +254,10 @@ #define CFG_TUD_DWC2_DMA 0 #endif +#ifndef CFG_TUH_DWC2_DMA + #define CFG_TUH_DWC2_DMA 0 +#endif + // Enable PIO-USB software host controller #ifndef CFG_TUH_RPI_PIO_USB #define CFG_TUH_RPI_PIO_USB 0 -- cgit v1.3.1 From b5a4f18879110d9f5f8fe27c473818f2416e40e4 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 17 Oct 2024 15:56:12 +0700 Subject: get hpri triggered --- src/portable/synopsys/dwc2/dcd_dwc2.c | 4 +- src/portable/synopsys/dwc2/dwc2_common.c | 76 ++++++++++----- src/portable/synopsys/dwc2/dwc2_stm32.h | 16 +++- src/portable/synopsys/dwc2/dwc2_type.h | 27 +++--- src/portable/synopsys/dwc2/hcd_dwc2.c | 156 +++++++++++++++++++++++++++---- src/tusb.c | 2 +- 6 files changed, 217 insertions(+), 64 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 6760af3f3..55d8f5766 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -486,8 +486,8 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Enable required interrupts dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM; - // Configure TX FIFO empty level for interrupt. Default is complete empty - dwc2->gahbcfg |= GAHBCFG_TXFELVL; + // Enable global interrupt + dwc2->gahbcfg |= GAHBCFG_GINT; dcd_connect(rhport); return true; diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index 50d0c28b3..12dcdb7c6 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -44,18 +44,21 @@ static void reset_core(dwc2_regs_t* dwc2) { // reset core dwc2->grstctl |= GRSTCTL_CSRST; - // wait for reset bit is cleared - // TODO version 4.20a should wait for RESET DONE mask - while (dwc2->grstctl & GRSTCTL_CSRST) {} - - // wait for AHB master IDLE - while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {} + if ((dwc2->gsnpsid & DWC2_CORE_REV_MASK) < (DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) { + // prior v42.0 CSRST is self-clearing + while (dwc2->grstctl & GRSTCTL_CSRST) {} + } else { + // From v4.20a CSRST bit is write only, CSRT_DONE (w1c) is introduced for checking. + // CSRST must also be explicitly cleared + while (!(dwc2->grstctl & GRSTCTL_CSRST_DONE)) {} + dwc2->grstctl = (dwc2->grstctl & ~GRSTCTL_CSRST) | GRSTCTL_CSRST_DONE; + } - // wait for device mode ? + while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {} // wait for AHB master IDLE } bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { - (void) dwc2; + (void)dwc2; #if CFG_TUD_ENABLED if (rh_init->role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) { @@ -71,11 +74,14 @@ bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED; } -static void phy_fs_init(dwc2_regs_t* dwc2) { +static void phy_fs_init(dwc2_regs_t* dwc2, tusb_role_t role) { TU_LOG(DWC2_COMMON_DEBUG, "Fullspeed PHY init\r\n"); + uint32_t gusbcfg = dwc2->gusbcfg; + // Select FS PHY - dwc2->gusbcfg |= GUSBCFG_PHYSEL; + gusbcfg |= GUSBCFG_PHYSEL; + dwc2->gusbcfg = gusbcfg; // MCU specific PHY init before reset dwc2_phy_init(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED); @@ -86,13 +92,33 @@ static void phy_fs_init(dwc2_regs_t* dwc2) { // USB turnaround time is critical for certification where long cables and 5-Hubs are used. // So if you need the AHB to run at less than 30 MHz, and if USB turnaround time is not critical, // these bits can be programmed to a larger value. Default is 5 - dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_TRDT_Msk) | (5u << GUSBCFG_TRDT_Pos); + gusbcfg &= ~GUSBCFG_TRDT_Msk; + gusbcfg |= 5u << GUSBCFG_TRDT_Pos; + dwc2->gusbcfg = gusbcfg; + + // FS/LS PHY Clock Select + if (role == TUSB_ROLE_HOST) { + uint32_t hcfg = dwc2->hcfg; + hcfg |= HCFG_FSLS_ONLY; + hcfg &= ~HCFG_FSLS_PHYCLK_SEL; + + if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI && + dwc2->ghwcfg2_bm.fs_phy_type == GHWCFG2_FSPHY_DEDICATED) { + // dedicated FS PHY with 48 mhz + hcfg |= HCFG_FSLS_PHYCLK_SEL_48MHZ; + } else { + // shared HS PHY running at full speed + hcfg |= HCFG_FSLS_PHYCLK_SEL_30_60MHZ; + } + dwc2->hcfg = hcfg; + } // MCU specific PHY update post reset dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED); } -static void phy_hs_init(dwc2_regs_t* dwc2) { +static void phy_hs_init(dwc2_regs_t* dwc2, tusb_role_t role) { + (void) role; uint32_t gusbcfg = dwc2->gusbcfg; // De-select FS PHY @@ -123,8 +149,8 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // Set 16-bit interface if supported if (dwc2->ghwcfg4_bm.phy_data_width) { - gusbcfg |= GUSBCFG_PHYIF16; // 16 bit - }else { + gusbcfg |= GUSBCFG_PHYIF16; // 16 bit + } else { gusbcfg &= ~GUSBCFG_PHYIF16; // 8 bit } } @@ -138,6 +164,10 @@ static void phy_hs_init(dwc2_regs_t* dwc2) { // Reset core after selecting PHY reset_core(dwc2); + if (role == TUSB_ROLE_HOST) { + dwc2->hcfg &= ~HCFG_FSLS_ONLY; + } + // Set turn-around, must after core reset otherwise it will be clear // - 9 if using 8-bit PHY interface // - 5 if using 16-bit PHY interface @@ -162,7 +192,7 @@ static bool check_dwc2(dwc2_regs_t* dwc2) { #endif // For some reason: GD32VF103 gsnpsid and all hwcfg register are always zero (skip it) - (void) dwc2; + (void)dwc2; #if !TU_CHECK_MCU(OPT_MCU_GD32VF103) uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK; TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID); @@ -175,16 +205,16 @@ static bool check_dwc2(dwc2_regs_t* dwc2) { // //-------------------------------------------------------------------- bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { - (void) rh_init; + (void)rh_init; dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Check Synopsys ID register, failed if controller clock/power is not enabled TU_ASSERT(check_dwc2(dwc2)); if (dwc2_core_is_highspeed(dwc2, rh_init)) { - phy_hs_init(dwc2); // Highspeed + phy_hs_init(dwc2, rh_init->role); } else { - phy_fs_init(dwc2); // core does not support highspeed or hs phy is not present + phy_fs_init(dwc2, rh_init->role); } /* Set HS/FS Timeout Calibration to 7 (max available value). @@ -211,20 +241,20 @@ bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { int_mask = dwc2->gotgint; dwc2->gotgint |= int_mask; - dwc2->gintmsk = GINTMSK_OTGINT; + dwc2->gintmsk = 0; - if (dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE)) { + if (dwc2_dma_enabled(dwc2, rh_init->role)) { const uint16_t epinfo_base = dma_cal_epfifo_base(rhport); dwc2->gdfifocfg = (epinfo_base << GDFIFOCFG_EPINFOBASE_SHIFT) | epinfo_base; // DMA seems to be only settable after a core reset, and not possible to switch on-the-fly dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2; - }else { + } else { dwc2->gintmsk |= GINTMSK_RXFLVLM; } - // Enable global interrupt - dwc2->gahbcfg |= GAHBCFG_GINT; + // Configure TX FIFO empty level for interrupt. Default is complete empty + dwc2->gahbcfg |= GAHBCFG_TXFELVL; return true; } diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index 395b6d870..8719c4820 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -124,13 +124,19 @@ static const dwc2_controller_t _dwc2_controller[] = { // SystemCoreClock is already included by family header // extern uint32_t SystemCoreClock; -TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { - NVIC_EnableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum); +TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) { + (void) role; + const IRQn_Type irqn = (IRQn_Type) _dwc2_controller[rhport].irqnum; + if (enabled) { + NVIC_EnableIRQ(irqn); + } else { + NVIC_DisableIRQ(irqn); + } } -TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) { - NVIC_DisableIRQ((IRQn_Type) _dwc2_controller[rhport].irqnum); -} +#define dwc2_dcd_int_enable(_rhport) dwc2_int_set(_rhport, TUSB_ROLE_DEVICE, true) +#define dwc2_dcd_int_disable(_rhport) dwc2_int_set(_rhport, TUSB_ROLE_DEVICE, false) + TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { // try to delay for 1 ms diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index c8f6a5d1f..f99bf3e85 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -566,14 +566,15 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GOTGCTL_OTGVER GOTGCTL_OTGVER_Msk // OTG version /******************** Bit definition for HCFG register ********************/ -#define HCFG_FSLSPCS_Pos (0U) -#define HCFG_FSLSPCS_Msk (0x3UL << HCFG_FSLSPCS_Pos) // 0x00000003 -#define HCFG_FSLSPCS HCFG_FSLSPCS_Msk // FS/LS PHY clock select -#define HCFG_FSLSPCS_0 (0x1UL << HCFG_FSLSPCS_Pos) // 0x00000001 -#define HCFG_FSLSPCS_1 (0x2UL << HCFG_FSLSPCS_Pos) // 0x00000002 -#define HCFG_FSLSS_Pos (2U) -#define HCFG_FSLSS_Msk (0x1UL << HCFG_FSLSS_Pos) // 0x00000004 -#define HCFG_FSLSS HCFG_FSLSS_Msk // FS- and LS-only support +#define HCFG_FSLS_PHYCLK_SEL_Pos (0U) +#define HCFG_FSLS_PHYCLK_SEL_Msk (0x3UL << HCFG_FSLS_PHYCLK_SEL_Pos) // 0x00000003 +#define HCFG_FSLS_PHYCLK_SEL HCFG_FSLS_PHYCLK_SEL_Msk // FS/LS PHY clock select +#define HCFG_FSLS_PHYCLK_SEL_30_60MHZ (0x0UL << HCFG_FSLS_PHYCLK_SEL_Pos) // 0x00000000 +#define HCFG_FSLS_PHYCLK_SEL_48MHZ (0x1UL << HCFG_FSLS_PHYCLK_SEL_Pos) // 0x00000001 + +#define HCFG_FSLS_ONLY_Pos (2U) +#define HCFG_FSLS_ONLY_Msk (0x1UL << HCFG_FSLS_ONLY_Pos) // 0x00000004 +#define HCFG_FSLS_ONLY HCFG_FSLS_ONLY_Msk // FS- and LS-only support /******************** Bit definition for PCGCR register ********************/ #define PCGCR_STPPCLK_Pos (0U) @@ -828,8 +829,8 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GRSTCTL_TXFNUM_2 (0x04UL << GRSTCTL_TXFNUM_Pos) // 0x00000100 #define GRSTCTL_TXFNUM_3 (0x08UL << GRSTCTL_TXFNUM_Pos) // 0x00000200 #define GRSTCTL_TXFNUM_4 (0x10UL << GRSTCTL_TXFNUM_Pos) // 0x00000400 -#define GRSTCTL_CSFTRST_DONE_Pos (29) -#define GRSTCTL_CSFTRST_DONE (1u << GRSTCTL_CSFTRST_DONE_Pos) // Reset Done, only available from v4.20a +#define GRSTCTL_CSRST_DONE_Pos (29) +#define GRSTCTL_CSRST_DONE (1u << GRSTCTL_CSRST_DONE_Pos) // Reset Done, only available from v4.20a #define GRSTCTL_DMAREQ_Pos (30U) #define GRSTCTL_DMAREQ_Msk (0x1UL << GRSTCTL_DMAREQ_Pos) // 0x40000000 #define GRSTCTL_DMAREQ GRSTCTL_DMAREQ_Msk // DMA request signal @@ -1475,9 +1476,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define HPRT_CONN_STATUS_Pos (0U) #define HPRT_CONN_STATUS_Msk (0x1UL << HPRT_CONN_STATUS_Pos) // 0x00000001 #define HPRT_CONN_STATUS HPRT_CONN_STATUS_Msk // Port connect status -#define HPRT_CONN_DETECTEDT_Pos (1U) -#define HPRT_CONN_DETECTEDT_Msk (0x1UL << HPRT_CONN_DETECTEDT_Pos) // 0x00000002 -#define HPRT_CONN_DETECTEDT HPRT_CONN_DETECTEDT_Msk // Port connect detected +#define HPRT_CONN_DETECT_Pos (1U) +#define HPRT_CONN_DETECT_Msk (0x1UL << HPRT_CONN_DETECT_Pos) // 0x00000002 +#define HPRT_CONN_DETECT HPRT_CONN_DETECT_Msk // Port connect detected #define HPRT_ENABLE_Pos (2U) #define HPRT_ENABLE_Msk (0x1UL << HPRT_ENABLE_Pos) // 0x00000004 #define HPRT_ENABLE HPRT_ENABLE_Msk // Port enable diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index b383b4069..97068d4c5 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -34,6 +34,10 @@ #include "host/hcd.h" #include "dwc2_common.h" +enum { + HPRT_W1C_MASK = HPRT_CONN_DETECT | HPRT_ENABLE | HPRT_EN_CHANGE | HPRT_OVER_CURRENT_CHANGE +}; + //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ @@ -54,40 +58,41 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Core Initialization TU_ASSERT(dwc2_core_init(rhport, rh_init)); + //------------- 3.1 Host Initialization -------------// + + // max speed + // if (dwc2_core_is_highspeed(dwc2, rh_init)) { + // dwc2->hcfg &= ~HCFG_FSLS_ONLY; + // } else { + // dwc2->hcfg |= HCFG_FSLS_ONLY; + // } + // force host mode dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD; - //------------- 3.1 Host Initialization -------------// + dwc2->hprt = HPRT_W1C_MASK; // clear all write-1-clear bits + dwc2->hprt = HPRT_POWER; // port power on -> drive VBUS + // Enable required interrupts dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_PRTIM | GINTMSK_WUIM; - - // max speed - if (dwc2_core_is_highspeed(dwc2, rh_init)) { - dwc2->hcfg &= ~HCFG_FSLSS; - } else { - dwc2->hcfg |= HCFG_FSLSS; - } - - // port power on -> drive VBUS - dwc2->hprt = HPRT_POWER; + dwc2->gahbcfg |= GAHBCFG_GINT; // Enable global interrupt return true; } // Enable USB interrupt void hcd_int_enable (uint8_t rhport) { - (void) rhport; + dwc2_int_set(rhport, TUSB_ROLE_HOST, true); } // Disable USB interrupt void hcd_int_disable(uint8_t rhport) { - (void) rhport; + dwc2_int_set(rhport, TUSB_ROLE_HOST, false); } // Get frame number (1ms) uint32_t hcd_frame_number(uint8_t rhport) { (void) rhport; - return 0; } @@ -97,20 +102,23 @@ uint32_t hcd_frame_number(uint8_t rhport) { // Get the current connect status of roothub port bool hcd_port_connect_status(uint8_t rhport) { - (void) rhport; - - return false; + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + return dwc2->hprt & HPRT_CONN_STATUS; } // Reset USB bus on the port. Return immediately, bus reset sequence may not be complete. // Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence. void hcd_port_reset(uint8_t rhport) { - (void) rhport; + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + dwc2->hprt = HPRT_RESET; } // Complete bus reset sequence, may be required by some controllers void hcd_port_reset_end(uint8_t rhport) { - (void) rhport; + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + uint32_t hprt = dwc2->hprt & ~HPRT_W1C_MASK; // skip w1c bits + hprt &= ~HPRT_RESET; + dwc2->hprt = hprt; } // Get port link speed @@ -182,6 +190,101 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { // HCD Event Handler //-------------------------------------------------------------------- +#if 1 +static void handle_rxflvl_irq(uint8_t rhport) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + volatile uint32_t const* rx_fifo = dwc2->fifo[0]; + + // Pop control word off FIFO + uint32_t const grxstsp = dwc2->grxstsp; + uint8_t const pktsts = (grxstsp & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; + uint8_t const epnum = (grxstsp & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; + uint16_t const bcnt = (grxstsp & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; + // dwc2_epout_t* epout = &dwc2->epout[epnum]; + + (void) epnum; (void) bcnt; (void) rx_fifo; + + TU_LOG1_INT(pktsts); + + // switch (pktsts) { + // // Global OUT NAK: do nothing + // case GRXSTS_PKTSTS_GLOBALOUTNAK: + // break; + // + // case GRXSTS_PKTSTS_SETUPRX: + // // Setup packet received + // // We can receive up to three setup packets in succession, but only the last one is valid. + // _setup_packet[0] = (*rx_fifo); + // _setup_packet[1] = (*rx_fifo); + // break; + // + // case GRXSTS_PKTSTS_SETUPDONE: + // // Setup packet done: + // // After popping this out, dwc2 asserts a DOEPINT_SETUP interrupt which is handled by handle_epout_irq() + // epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); + // break; + // + // case GRXSTS_PKTSTS_OUTRX: { + // // Out packet received + // xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); + // + // // Read packet off RxFIFO + // if (xfer->ff) { + // // Ring buffer + // tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt); + // } else { + // // Linear buffer + // dfifo_read_packet(rhport, xfer->buffer, bcnt); + // + // // Increment pointer to xfer data + // xfer->buffer += bcnt; + // } + // + // // Truncate transfer length in case of short packet + // if (bcnt < xfer->max_size) { + // xfer->total_len -= (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; + // if (epnum == 0) { + // xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; + // ep0_pending[TUSB_DIR_OUT] = 0; + // } + // } + // break; + // } + // + // case GRXSTS_PKTSTS_OUTDONE: + // /* Out packet done + // After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed interrupt on + // the specified OUT endpoint which will be handled by handle_epout_irq() */ + // break; + // + // default: + // TU_BREAKPOINT(); + // break; + // } +} +#endif + +/* Handle Host Port interrupt, possible source are: + - Connection Detection + - Enable Change + - Over Current Change +*/ +TU_ATTR_ALWAYS_INLINE static inline void handle_hprt_irq(uint8_t rhport, bool in_isr) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + uint32_t hprt = dwc2->hprt; + + if (hprt & HPRT_CONN_DETECT) { + // Port Connect Detect + dwc2->hprt = HPRT_CONN_DETECT; // clear + + if (hprt & HPRT_CONN_STATUS) { + hcd_event_device_attach(rhport, in_isr); + } else { + hcd_event_device_remove(rhport, in_isr); + } + } +} + /* Interrupt Hierarchy HCINTn.XferCompl HCINTMSKn.XferComplMsk @@ -201,7 +304,6 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { IRQn */ void hcd_int_handler(uint8_t rhport, bool in_isr) { - (void) in_isr; dwc2_regs_t* dwc2 = DWC2_REG(rhport); const uint32_t int_mask = dwc2->gintmsk; @@ -209,7 +311,21 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { if (int_status & GINTSTS_HPRTINT) { TU_LOG1_HEX(dwc2->hprt); + handle_hprt_irq(rhport, in_isr); } + + // RxFIFO non-empty interrupt handling. + if (int_status & GINTSTS_RXFLVL) { + // RXFLVL bit is read-only + dwc2->gintmsk &= ~GINTMSK_RXFLVLM; // disable RXFLVL interrupt while reading + + do { + handle_rxflvl_irq(rhport); // read all packets + } while(dwc2->gintsts & GINTSTS_RXFLVL); + + dwc2->gintmsk |= GINTMSK_RXFLVLM; + } + } #endif diff --git a/src/tusb.c b/src/tusb.c index e6f8055b7..6a0cc0805 100644 --- a/src/tusb.c +++ b/src/tusb.c @@ -77,6 +77,7 @@ bool tusb_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // new API with explicit rhport and role TU_ASSERT(rhport < TUP_USBIP_CONTROLLER_NUM && rh_init->role != TUSB_ROLE_INVALID); + _rhport_role[rhport] = rh_init->role; #if CFG_TUD_ENABLED if (rh_init->role == TUSB_ROLE_DEVICE) { @@ -90,7 +91,6 @@ bool tusb_rhport_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { } #endif - _rhport_role[rhport] = rh_init->role; return true; } -- cgit v1.3.1 From f5978876d2a5d8cdc6cfd3bf99f9b820c5a6ac8a Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 21 Oct 2024 11:43:37 +0700 Subject: get hprt interrupt triggered --- examples/dual/host_info_to_device_cdc/only.txt | 1 + examples/host/device_info/only.txt | 1 + src/portable/synopsys/dwc2/dcd_dwc2.c | 4 +- src/portable/synopsys/dwc2/dwc2_common.c | 95 ++++++++++---------- src/portable/synopsys/dwc2/dwc2_common.h | 6 +- src/portable/synopsys/dwc2/dwc2_type.h | 27 ++++-- src/portable/synopsys/dwc2/hcd_dwc2.c | 117 +++++++++---------------- 7 files changed, 120 insertions(+), 131 deletions(-) (limited to 'src/portable') diff --git a/examples/dual/host_info_to_device_cdc/only.txt b/examples/dual/host_info_to_device_cdc/only.txt index 149ece856..f9db1db85 100644 --- a/examples/dual/host_info_to_device_cdc/only.txt +++ b/examples/dual/host_info_to_device_cdc/only.txt @@ -5,3 +5,4 @@ mcu:RP2040 mcu:ra6m5 mcu:MAX3421 mcu:STM32H7 +mcu:STM32F7 diff --git a/examples/host/device_info/only.txt b/examples/host/device_info/only.txt index a38fc251b..aed9583b4 100644 --- a/examples/host/device_info/only.txt +++ b/examples/host/device_info/only.txt @@ -13,3 +13,4 @@ mcu:RP2040 mcu:RX65X mcu:RAXXX mcu:STM32H7 +mcu:STM32F7 diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 55d8f5766..e7440529a 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -454,7 +454,9 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Core Initialization - TU_ASSERT(dwc2_core_init(rhport, rh_init)); + const bool is_highspeed = dwc2_core_is_highspeed(dwc2, rh_init); + const bool is_dma = dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE); + TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma)); // Device Initialization dcd_disconnect(rhport); diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index 12dcdb7c6..a5f1c2b08 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -40,6 +40,9 @@ #include "dwc2_common.h" +//-------------------------------------------------------------------- +// +//-------------------------------------------------------------------- static void reset_core(dwc2_regs_t* dwc2) { // reset core dwc2->grstctl |= GRSTCTL_CSRST; @@ -57,24 +60,7 @@ static void reset_core(dwc2_regs_t* dwc2) { while (!(dwc2->grstctl & GRSTCTL_AHBIDL)) {} // wait for AHB master IDLE } -bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { - (void)dwc2; - -#if CFG_TUD_ENABLED - if (rh_init->role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) { - return false; - } -#endif -#if CFG_TUH_ENABLED - if (rh_init->role == TUSB_ROLE_HOST && !TUH_OPT_HIGH_SPEED) { - return false; - } -#endif - - return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED; -} - -static void phy_fs_init(dwc2_regs_t* dwc2, tusb_role_t role) { +static void phy_fs_init(dwc2_regs_t* dwc2) { TU_LOG(DWC2_COMMON_DEBUG, "Fullspeed PHY init\r\n"); uint32_t gusbcfg = dwc2->gusbcfg; @@ -96,29 +82,11 @@ static void phy_fs_init(dwc2_regs_t* dwc2, tusb_role_t role) { gusbcfg |= 5u << GUSBCFG_TRDT_Pos; dwc2->gusbcfg = gusbcfg; - // FS/LS PHY Clock Select - if (role == TUSB_ROLE_HOST) { - uint32_t hcfg = dwc2->hcfg; - hcfg |= HCFG_FSLS_ONLY; - hcfg &= ~HCFG_FSLS_PHYCLK_SEL; - - if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI && - dwc2->ghwcfg2_bm.fs_phy_type == GHWCFG2_FSPHY_DEDICATED) { - // dedicated FS PHY with 48 mhz - hcfg |= HCFG_FSLS_PHYCLK_SEL_48MHZ; - } else { - // shared HS PHY running at full speed - hcfg |= HCFG_FSLS_PHYCLK_SEL_30_60MHZ; - } - dwc2->hcfg = hcfg; - } - // MCU specific PHY update post reset dwc2_phy_update(dwc2, GHWCFG2_HSPHY_NOT_SUPPORTED); } -static void phy_hs_init(dwc2_regs_t* dwc2, tusb_role_t role) { - (void) role; +static void phy_hs_init(dwc2_regs_t* dwc2) { uint32_t gusbcfg = dwc2->gusbcfg; // De-select FS PHY @@ -164,10 +132,6 @@ static void phy_hs_init(dwc2_regs_t* dwc2, tusb_role_t role) { // Reset core after selecting PHY reset_core(dwc2); - if (role == TUSB_ROLE_HOST) { - dwc2->hcfg &= ~HCFG_FSLS_ONLY; - } - // Set turn-around, must after core reset otherwise it will be clear // - 9 if using 8-bit PHY interface // - 5 if using 16-bit PHY interface @@ -204,17 +168,36 @@ static bool check_dwc2(dwc2_regs_t* dwc2) { //-------------------------------------------------------------------- // //-------------------------------------------------------------------- -bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { - (void)rh_init; +bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { + (void)dwc2; + +#if CFG_TUD_ENABLED + if (rh_init->role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) { + return false; + } +#endif +#if CFG_TUH_ENABLED + if (rh_init->role == TUSB_ROLE_HOST && !TUH_OPT_HIGH_SPEED) { + return false; + } +#endif + + return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED; +} + +bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Check Synopsys ID register, failed if controller clock/power is not enabled TU_ASSERT(check_dwc2(dwc2)); - if (dwc2_core_is_highspeed(dwc2, rh_init)) { - phy_hs_init(dwc2, rh_init->role); + // disable global interrupt + // dwc2->gahbcfg &= ~GAHBCFG_GINT; + + if (is_highspeed) { + phy_hs_init(dwc2); } else { - phy_fs_init(dwc2, rh_init->role); + phy_fs_init(dwc2); } /* Set HS/FS Timeout Calibration to 7 (max available value). @@ -243,7 +226,12 @@ bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dwc2->gintmsk = 0; - if (dwc2_dma_enabled(dwc2, rh_init->role)) { + // TODO can be enabled with device as well but tested with host for now + // if (rh_init->role == TUSB_ROLE_HOST) { + // dwc2->gintmsk |= OTG_INT_COMMON; + // } + + if (is_dma) { const uint16_t epinfo_base = dma_cal_epfifo_base(rhport); dwc2->gdfifocfg = (epinfo_base << GDFIFOCFG_EPINFOBASE_SHIFT) | epinfo_base; @@ -259,4 +247,17 @@ bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { return true; } +// void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr) { +// (void) in_isr; +// dwc2_regs_t * const dwc2 = DWC2_REG(rhport); +// const uint32_t int_mask = dwc2->gintmsk; +// const uint32_t int_status = dwc2->gintsts & int_mask; +// +// // Device disconnect +// if (int_status & GINTSTS_DISCINT) { +// dwc2->gintsts = GINTSTS_DISCINT; +// } +// +// } + #endif diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h index 538fcd179..7088ff3c3 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.h +++ b/src/portable/synopsys/dwc2/dwc2_common.h @@ -57,6 +57,9 @@ enum { DWC2_CONTROLLER_COUNT = TU_ARRAY_SIZE(_dwc2_controller) }; +enum { + OTG_INT_COMMON = 0 // GINTSTS_DISCINT | GINTSTS_CONIDSTSCHNG +}; //------------- Core -------------// TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { @@ -68,7 +71,8 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { } bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init); -bool dwc2_core_init(uint8_t rhport, const tusb_rhport_init_t* rh_init); +bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma); +void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr); //------------- DFIFO -------------// TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_tx(dwc2_regs_t* dwc2, uint8_t fnum) { diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index f99bf3e85..8fb926a21 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -86,6 +86,11 @@ typedef struct } HS_PHYC_GlobalTypeDef; #endif +enum { + GOTGCTL_OTG_VERSION_1_3 = 0, + GOTGCTL_OTG_VERSION_2_0 = 1, +}; + enum { GHWCFG2_OPMODE_HNP_SRP = 0, GHWCFG2_OPMODE_SRP = 1, @@ -128,6 +133,11 @@ enum { HPRT_SPEED_LOW = 2 }; +enum { + GINTSTS_CMODE_DEVICE = 0, + GINTSTS_CMODE_HOST = 1, +}; + //-------------------------------------------------------------------- // Register bitfield definitions //-------------------------------------------------------------------- @@ -152,7 +162,7 @@ typedef struct TU_ATTR_PACKED { uint32_t ases_valid : 1; // 18 A-session valid uint32_t bses_valid : 1; // 19 B-session valid uint32_t otg_ver : 1; // 20 OTG version 0: v1.3, 1: v2.0 - uint32_t current_mode : 1; // 21 Current mode of operation 0: device, 1: host + uint32_t current_mode : 1; // 21 Current mode of operation. Only from v3.00a uint32_t mult_val_id_bc : 5; // 22..26 Multi-valued input pin ID battery charger uint32_t chirp_en : 1; // 27 Chirp detection enable uint32_t rsv28_30 : 3; // 28.30: Reserved @@ -391,7 +401,10 @@ TU_VERIFY_STATIC(sizeof(dwc2_dep_t) == 0x20, "incorrect size"); //-------------------------------------------------------------------- typedef struct { //------------- Core Global -------------// + union { volatile uint32_t gotgctl; // 000 OTG Control and Status + volatile dwc2_gotgctl_t gotgctl_bm; + }; volatile uint32_t gotgint; // 004 OTG Interrupt volatile uint32_t gahbcfg; // 008 AHB Configuration volatile uint32_t gusbcfg; // 00c USB Configuration @@ -1008,9 +1021,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GINTSTS_LPMINT_Pos (27U) #define GINTSTS_LPMINT_Msk (0x1UL << GINTSTS_LPMINT_Pos) // 0x08000000 #define GINTSTS_LPMINT GINTSTS_LPMINT_Msk // LPM interrupt -#define GINTSTS_CIDSCHG_Pos (28U) -#define GINTSTS_CIDSCHG_Msk (0x1UL << GINTSTS_CIDSCHG_Pos) // 0x10000000 -#define GINTSTS_CIDSCHG GINTSTS_CIDSCHG_Msk // Connector ID status change +#define GINTSTS_CONIDSTSCHNG_Pos (28U) +#define GINTSTS_CONIDSTSCHNG_Msk (0x1UL << GINTSTS_CONIDSTSCHNG_Pos) // 0x10000000 +#define GINTSTS_CONIDSTSCHNG GINTSTS_CONIDSTSCHNG_Msk // Connector ID status change #define GINTSTS_DISCINT_Pos (29U) #define GINTSTS_DISCINT_Msk (0x1UL << GINTSTS_DISCINT_Pos) // 0x20000000 #define GINTSTS_DISCINT GINTSTS_DISCINT_Msk // Disconnect detected interrupt @@ -1094,9 +1107,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GINTMSK_LPMINTM_Pos (27U) #define GINTMSK_LPMINTM_Msk (0x1UL << GINTMSK_LPMINTM_Pos) // 0x08000000 #define GINTMSK_LPMINTM GINTMSK_LPMINTM_Msk // LPM interrupt Mask -#define GINTMSK_CIDSCHGM_Pos (28U) -#define GINTMSK_CIDSCHGM_Msk (0x1UL << GINTMSK_CIDSCHGM_Pos) // 0x10000000 -#define GINTMSK_CIDSCHGM GINTMSK_CIDSCHGM_Msk // Connector ID status change mask +#define GINTMSK_CONIDSTSCHNGM_Pos (28U) +#define GINTMSK_CONIDSTSCHNGM_Msk (0x1UL << GINTMSK_CONIDSTSCHNGM_Pos) // 0x10000000 +#define GINTMSK_CONIDSTSCHNGM GINTMSK_CONIDSTSCHNGM_Msk // Connector ID status change mask #define GINTMSK_DISCINT_Pos (29U) #define GINTMSK_DISCINT_Msk (0x1UL << GINTMSK_DISCINT_Pos) // 0x20000000 #define GINTMSK_DISCINT GINTMSK_DISCINT_Msk // Disconnect detected interrupt mask diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 97068d4c5..2d4368e94 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -56,25 +56,40 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Core Initialization - TU_ASSERT(dwc2_core_init(rhport, rh_init)); + const bool is_highspeed = dwc2_core_is_highspeed(dwc2, rh_init); + const bool is_dma = dwc2_dma_enabled(dwc2, TUSB_ROLE_HOST); + TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma)); //------------- 3.1 Host Initialization -------------// - // max speed - // if (dwc2_core_is_highspeed(dwc2, rh_init)) { - // dwc2->hcfg &= ~HCFG_FSLS_ONLY; - // } else { - // dwc2->hcfg |= HCFG_FSLS_ONLY; - // } + // FS/LS PHY Clock Select + uint32_t hcfg = dwc2->hcfg; + if (is_highspeed) { + hcfg &= ~HCFG_FSLS_ONLY; + } else { + hcfg &= ~HCFG_FSLS_ONLY; // since we are using FS PHY + hcfg &= ~HCFG_FSLS_PHYCLK_SEL; + + if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI && + dwc2->ghwcfg2_bm.fs_phy_type == GHWCFG2_FSPHY_DEDICATED) { + // dedicated FS PHY with 48 mhz + hcfg |= HCFG_FSLS_PHYCLK_SEL_48MHZ; + } else { + // shared HS PHY running at full speed + hcfg |= HCFG_FSLS_PHYCLK_SEL_30_60MHZ; + } + } + dwc2->hcfg = hcfg; - // force host mode + // force host mode and wait for mode switch dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD; + while( (dwc2->gintsts & GINTSTS_CMOD) != GINTSTS_CMODE_HOST) {} dwc2->hprt = HPRT_W1C_MASK; // clear all write-1-clear bits - dwc2->hprt = HPRT_POWER; // port power on -> drive VBUS + dwc2->hprt = HPRT_POWER; // turn on VBUS // Enable required interrupts - dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_PRTIM | GINTMSK_WUIM; + dwc2->gintmsk |= GINTMSK_OTGINT | GINTSTS_CONIDSTSCHNG | GINTMSK_PRTIM; // | GINTMSK_WUIM; dwc2->gahbcfg |= GAHBCFG_GINT; // Enable global interrupt return true; @@ -193,74 +208,15 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { #if 1 static void handle_rxflvl_irq(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - volatile uint32_t const* rx_fifo = dwc2->fifo[0]; + // volatile uint32_t const* rx_fifo = dwc2->fifo[0]; // Pop control word off FIFO uint32_t const grxstsp = dwc2->grxstsp; - uint8_t const pktsts = (grxstsp & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; - uint8_t const epnum = (grxstsp & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; - uint16_t const bcnt = (grxstsp & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; + (void) grxstsp; + // uint8_t const pktsts = (grxstsp & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; + // uint8_t const epnum = (grxstsp & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; + // uint16_t const bcnt = (grxstsp & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; // dwc2_epout_t* epout = &dwc2->epout[epnum]; - - (void) epnum; (void) bcnt; (void) rx_fifo; - - TU_LOG1_INT(pktsts); - - // switch (pktsts) { - // // Global OUT NAK: do nothing - // case GRXSTS_PKTSTS_GLOBALOUTNAK: - // break; - // - // case GRXSTS_PKTSTS_SETUPRX: - // // Setup packet received - // // We can receive up to three setup packets in succession, but only the last one is valid. - // _setup_packet[0] = (*rx_fifo); - // _setup_packet[1] = (*rx_fifo); - // break; - // - // case GRXSTS_PKTSTS_SETUPDONE: - // // Setup packet done: - // // After popping this out, dwc2 asserts a DOEPINT_SETUP interrupt which is handled by handle_epout_irq() - // epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); - // break; - // - // case GRXSTS_PKTSTS_OUTRX: { - // // Out packet received - // xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - // - // // Read packet off RxFIFO - // if (xfer->ff) { - // // Ring buffer - // tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt); - // } else { - // // Linear buffer - // dfifo_read_packet(rhport, xfer->buffer, bcnt); - // - // // Increment pointer to xfer data - // xfer->buffer += bcnt; - // } - // - // // Truncate transfer length in case of short packet - // if (bcnt < xfer->max_size) { - // xfer->total_len -= (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; - // if (epnum == 0) { - // xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; - // ep0_pending[TUSB_DIR_OUT] = 0; - // } - // } - // break; - // } - // - // case GRXSTS_PKTSTS_OUTDONE: - // /* Out packet done - // After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed interrupt on - // the specified OUT endpoint which will be handled by handle_epout_irq() */ - // break; - // - // default: - // TU_BREAKPOINT(); - // break; - // } } #endif @@ -305,10 +261,21 @@ TU_ATTR_ALWAYS_INLINE static inline void handle_hprt_irq(uint8_t rhport, bool in */ void hcd_int_handler(uint8_t rhport, bool in_isr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - const uint32_t int_mask = dwc2->gintmsk; const uint32_t int_status = dwc2->gintsts & int_mask; + TU_LOG1_HEX(int_status); + + if (int_status & GINTSTS_CONIDSTSCHNG) { + // Connector ID status change + dwc2->gintsts = GINTSTS_CONIDSTSCHNG; + + //if (dwc2->gotgctl) + // dwc2->hprt = HPRT_POWER; // power on port to turn on VBUS + //dwc2->gintmsk |= GINTMSK_PRTIM; + // TODO wait for SRP if OTG + } + if (int_status & GINTSTS_HPRTINT) { TU_LOG1_HEX(dwc2->hprt); handle_hprt_irq(rhport, in_isr); -- cgit v1.3.1 From 8461525d48cb4a97a7b18816f65b548a875ffe50 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 21 Oct 2024 17:45:40 +0700 Subject: add tusb_time_millis(), able to reset and enable dwc2 port and get SOF active --- hw/bsp/board.c | 5 ++ src/host/usbh.c | 21 ++++++--- src/portable/synopsys/dwc2/dwc2_common.c | 8 ++++ src/portable/synopsys/dwc2/dwc2_info.md | 2 +- src/portable/synopsys/dwc2/dwc2_info.py | 6 ++- src/portable/synopsys/dwc2/dwc2_type.h | 20 +++++--- src/portable/synopsys/dwc2/hcd_dwc2.c | 81 +++++++++++++++++++++++++++----- src/tusb.h | 10 ++-- 8 files changed, 123 insertions(+), 30 deletions(-) (limited to 'src/portable') diff --git a/hw/bsp/board.c b/hw/bsp/board.c index bb339f613..d4fdb7586 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -134,3 +134,8 @@ int board_getchar(void) { char c; return (sys_read(0, &c, 1) > 0) ? (int) c : (-1); } + + +uint32_t tusb_time_millis(void) { + return board_millis(); +} diff --git a/src/host/usbh.c b/src/host/usbh.c index b5df29f50..8bf40a607 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -447,9 +447,9 @@ bool tuh_deinit(uint8_t rhport) { } bool tuh_task_event_ready(void) { - // Skip if stack is not initialized - if ( !tuh_inited() ) return false; - + if (!tuh_inited()) { + return false; // Skip if stack is not initialized + } return !osal_queue_empty(_usbh_q); } @@ -1520,10 +1520,17 @@ static bool enum_new_device(hcd_event_t* event) { _dev0.hub_port = event->connection.hub_port; if (_dev0.hub_addr == 0) { - // connected/disconnected directly with roothub + // connected directly to roothub hcd_port_reset(_dev0.rhport); - osal_task_delay(ENUM_RESET_DELAY); // TODO may not work for no-OS on MCU that require reset_end() since - // sof of controller may not running while resetting +#if CFG_TUSB_OS == OPT_OS_NONE + // Since we are in middle of rhport reset, frame number is not available for time delay + // need to depend on tusb_time_millis() instead + const uint32_t start_reset = tusb_time_millis(); + while ((tusb_time_millis() - start_reset) < ENUM_RESET_DELAY) {} +#else + osal_task_delay(ENUM_RESET_DELAY); +#endif + hcd_port_reset_end(_dev0.rhport); // wait until device connection is stable TODO non blocking @@ -1548,7 +1555,7 @@ static bool enum_new_device(hcd_event_t* event) { } #if CFG_TUH_HUB else { - // connected/disconnected via external hub + // connected via external hub // wait until device connection is stable TODO non blocking osal_task_delay(ENUM_CONTACT_DEBOUNCING_DELAY); diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index a5f1c2b08..d0ad764a5 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -185,6 +185,14 @@ bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init return dwc2->ghwcfg2_bm.hs_phy_type != GHWCFG2_HSPHY_NOT_SUPPORTED; } +/* dwc2 has several PHYs option + * - UTMI+ is internal highspeed PHY, clock can be 30 Mhz (8-bit) or 60 Mhz (16-bit) + * - ULPI is external highspeed PHY, clock is 60Mhz with only 8-bit interface + * - Dedicated FS PHY is internal with clock 48Mhz. + * + * In addition, UTMI+/ULPI can be shared to run at fullspeed mode with 48Mhz + * +*/ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index cfd0c81a8..92293a072 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -7,7 +7,7 @@ | GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | | - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | | - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | DMA internal | -| - p2p (hub support) | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | +| - single_point | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | hub | n/a | | - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | | - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | n/a | Dedicated | | - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index d1793a005..d97a1192e 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -44,7 +44,7 @@ class GHWCFG2(ctypes.LittleEndianStructure): _fields_ = [ ("op_mode", ctypes.c_uint32, 3), ("arch", ctypes.c_uint32, 2), - ("p2p (hub support)", ctypes.c_uint32, 1), + ("single_point", ctypes.c_uint32, 1), ("hs_phy_type", ctypes.c_uint32, 2), ("fs_phy_type", ctypes.c_uint32, 2), ("num_dev_ep", ctypes.c_uint32, 4), @@ -119,6 +119,10 @@ GHWCFG2_field = { 1: "DMA external", 2: "DMA internal" }, + 'single_point': { + 0: "hub", + 1: "n/a" + }, 'hs_phy_type': { 0: "n/a", 1: "UTMI+", diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 8fb926a21..d2993bdd9 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -208,7 +208,7 @@ typedef struct TU_ATTR_PACKED { based on the speed of enumeration. The number of bit times added per PHY clock are as follows: - High-speed: PHY clock One 30-MHz = 16 bit times, One 60-MHz = 8 bit times - Full-speed: PHY clock One 30-MHz = 0.4 bit times, One 60-MHz = 0.2 bit times, One 48-MHz = 0.25 bit times */ - uint32_t phy_if : 1; // 3 PHY interface. 0: 8 bits, 1: 16 bits + uint32_t phy_if16 : 1; // 3 PHY interface. 0: 8 bits, 1: 16 bits uint32_t ulpi_utmi_sel : 1; // 4 ULPI/UTMI select. 0: UTMI+, 1: ULPI uint32_t fs_intf_sel : 1; // 5 Fullspeed serial interface select. 0: 6-pin, 1: 3-pin uint32_t phy_sel : 1; // 6 HS/FS PHY selection. 0: HS UTMI+ or ULPI, 1: FS serial transceiver @@ -259,7 +259,7 @@ TU_VERIFY_STATIC(sizeof(dwc2_grstctl_t) == 4, "incorrect size"); typedef struct TU_ATTR_PACKED { uint32_t op_mode : 3; // 0..2 HNP/SRP Host/Device/OTG mode uint32_t arch : 2; // 3..4 Slave/External/Internal DMA - uint32_t point2point : 1; // 5 0: support hub and split | 1: no hub, no split + uint32_t single_point : 1; // 5 0: support hub and split | 1: no hub, no split uint32_t hs_phy_type : 2; // 6..7 0: not supported | 1: UTMI+ | 2: ULPI | 3: UTMI+ and ULPI uint32_t fs_phy_type : 2; // 8..9 0: not supported | 1: dedicated | 2: UTMI+ | 3: ULPI uint32_t num_dev_ep : 4; // 10..13 Number of device endpoints (excluding EP0) @@ -407,7 +407,10 @@ typedef struct { }; volatile uint32_t gotgint; // 004 OTG Interrupt volatile uint32_t gahbcfg; // 008 AHB Configuration + union { volatile uint32_t gusbcfg; // 00c USB Configuration + volatile dwc2_gusbcfg_t gusbcfg_bm; + }; volatile uint32_t grstctl; // 010 Reset volatile uint32_t gintsts; // 014 Interrupt volatile uint32_t gintmsk; // 018 Interrupt Mask @@ -459,7 +462,10 @@ typedef struct { volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask volatile uint32_t hflbaddr; // 41C Host Frame List Base Address uint32_t reserved420[8]; // 420..43F + union { volatile uint32_t hprt; // 440 Host Port Control and Status + volatile dwc2_hprt_t hprt_bm; + }; uint32_t reserved444[47]; // 444..4FF //------------- Host Channel -------------// @@ -1490,14 +1496,14 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define HPRT_CONN_STATUS_Msk (0x1UL << HPRT_CONN_STATUS_Pos) // 0x00000001 #define HPRT_CONN_STATUS HPRT_CONN_STATUS_Msk // Port connect status #define HPRT_CONN_DETECT_Pos (1U) -#define HPRT_CONN_DETECT_Msk (0x1UL << HPRT_CONN_DETECT_Pos) // 0x00000002 -#define HPRT_CONN_DETECT HPRT_CONN_DETECT_Msk // Port connect detected +#define HPRT_CONN_DETECT_Msk (0x1UL << HPRT_CONN_DETECT_Pos) // 0x00000002 +#define HPRT_CONN_DETECT HPRT_CONN_DETECT_Msk // Port connect detected #define HPRT_ENABLE_Pos (2U) #define HPRT_ENABLE_Msk (0x1UL << HPRT_ENABLE_Pos) // 0x00000004 #define HPRT_ENABLE HPRT_ENABLE_Msk // Port enable -#define HPRT_EN_CHANGE_Pos (3U) -#define HPRT_EN_CHANGE_Msk (0x1UL << HPRT_EN_CHANGE_Pos) // 0x00000008 -#define HPRT_EN_CHANGE HPRT_EN_CHANGE_Msk // Port enable/disable change +#define HPRT_ENABLE_CHANGE_Pos (3U) +#define HPRT_ENABLE_CHANGE_Msk (0x1UL << HPRT_ENABLE_CHANGE_Pos) // 0x00000008 +#define HPRT_ENABLE_CHANGE HPRT_ENABLE_CHANGE_Msk // Port enable/disable change #define HPRT_OVER_CURRENT_ACTIVE_Pos (4U) #define HPRT_OVER_CURRENT_ACTIVE_Msk (0x1UL << HPRT_OVER_CURRENT_ACTIVE_Pos) // 0x00000010 #define HPRT_OVER_CURRENT_ACTIVE HPRT_OVER_CURRENT_ACTIVE_Msk // Port overcurrent active diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 2d4368e94..bb5086631 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -35,9 +35,20 @@ #include "dwc2_common.h" enum { - HPRT_W1C_MASK = HPRT_CONN_DETECT | HPRT_ENABLE | HPRT_EN_CHANGE | HPRT_OVER_CURRENT_CHANGE + HPRT_W1C_MASK = HPRT_CONN_DETECT | HPRT_ENABLE | HPRT_ENABLE_CHANGE | HPRT_OVER_CURRENT_CHANGE }; +TU_ATTR_ALWAYS_INLINE static inline tusb_speed_t convert_hprt_speed(uint32_t hprt_speed) { + tusb_speed_t speed; + switch(hprt_speed) { + case HPRT_SPEED_HIGH: speed = TUSB_SPEED_HIGH; break; + case HPRT_SPEED_FULL: speed = TUSB_SPEED_FULL; break; + case HPRT_SPEED_LOW : speed = TUSB_SPEED_LOW ; break; + default: TU_BREAKPOINT(); break; + } + return speed; +} + //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ @@ -81,6 +92,8 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { } dwc2->hcfg = hcfg; + // Enable HFIR reload + // force host mode and wait for mode switch dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD; while( (dwc2->gintsts & GINTSTS_CMOD) != GINTSTS_CMODE_HOST) {} @@ -107,8 +120,8 @@ void hcd_int_disable(uint8_t rhport) { // Get frame number (1ms) uint32_t hcd_frame_number(uint8_t rhport) { - (void) rhport; - return 0; + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + return dwc2->hfnum & HFNUM_FRNUM_Msk; } //--------------------------------------------------------------------+ @@ -125,7 +138,9 @@ bool hcd_port_connect_status(uint8_t rhport) { // Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence. void hcd_port_reset(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - dwc2->hprt = HPRT_RESET; + uint32_t hprt = dwc2->hprt & ~HPRT_W1C_MASK; + hprt |= HPRT_RESET; + dwc2->hprt = hprt; } // Complete bus reset sequence, may be required by some controllers @@ -138,9 +153,9 @@ void hcd_port_reset_end(uint8_t rhport) { // Get port link speed tusb_speed_t hcd_port_speed_get(uint8_t rhport) { - (void) rhport; - - return TUSB_SPEED_FULL; + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + const tusb_speed_t speed = convert_hprt_speed(dwc2->hprt_bm.speed); + return speed; } // HCD closes all opened endpoints belong to this device @@ -227,18 +242,62 @@ static void handle_rxflvl_irq(uint8_t rhport) { */ TU_ATTR_ALWAYS_INLINE static inline void handle_hprt_irq(uint8_t rhport, bool in_isr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint32_t hprt = dwc2->hprt; + uint32_t hprt = dwc2->hprt & ~HPRT_W1C_MASK; + const dwc2_hprt_t hprt_bm = dwc2->hprt_bm; - if (hprt & HPRT_CONN_DETECT) { + if (dwc2->hprt & HPRT_CONN_DETECT) { // Port Connect Detect - dwc2->hprt = HPRT_CONN_DETECT; // clear + hprt |= HPRT_CONN_DETECT; - if (hprt & HPRT_CONN_STATUS) { + if (hprt_bm.conn_status) { hcd_event_device_attach(rhport, in_isr); } else { hcd_event_device_remove(rhport, in_isr); } } + + if (dwc2->hprt & HPRT_ENABLE_CHANGE) { + // Port enable change + hprt |= HPRT_ENABLE_CHANGE; + + if (hprt_bm.enable) { + // Port enable + // Config HCFG FS/LS clock and HFIR for SOF interval according to link speed (value is in PHY clock unit) + const tusb_speed_t speed = convert_hprt_speed(hprt_bm.speed); + uint32_t hcfg = dwc2->hcfg & ~HCFG_FSLS_PHYCLK_SEL; + + const dwc2_gusbcfg_t gusbcfg_bm = dwc2->gusbcfg_bm; + uint32_t clock = 60; + if (gusbcfg_bm.phy_sel) { + // dedicated FS is 48Mhz + clock = 48; + hcfg |= HCFG_FSLS_PHYCLK_SEL_48MHZ; + } else { + // UTMI+ or ULPI + if (gusbcfg_bm.ulpi_utmi_sel) { + clock = 60; // ULPI 8-bit is 60Mhz + } else if (gusbcfg_bm.phy_if16) { + clock = 30; // UTMI+ 16-bit is 30Mhz + } else { + clock = 60; // UTMI+ 8-bit is 60Mhz + } + hcfg |= HCFG_FSLS_PHYCLK_SEL_30_60MHZ; + } + + dwc2->hcfg = hcfg; + + uint32_t hfir = dwc2->hfir & ~HFIR_FRIVL_Msk; + if (speed == TUSB_SPEED_HIGH) { + hfir |= 125*clock; + } else { + hfir |= 1000*clock; + } + + dwc2->hfir = hfir; + } + } + + dwc2->hprt = hprt; // clear interrupt } /* Interrupt Hierarchy diff --git a/src/tusb.h b/src/tusb.h index 2f30a5739..3ffaafded 100644 --- a/src/tusb.h +++ b/src/tusb.h @@ -127,10 +127,8 @@ //--------------------------------------------------------------------+ -// APPLICATION API +// User API //--------------------------------------------------------------------+ - - #if CFG_TUH_ENABLED || CFG_TUD_ENABLED // Internal helper for backward compatible with tusb_init(void) @@ -167,6 +165,12 @@ void tusb_int_handler(uint8_t rhport, bool in_isr); #endif +//--------------------------------------------------------------------+ +// API Implemented by user +//--------------------------------------------------------------------+ + +// Get current milliseconds, maybe required by some port with no RTOS +uint32_t tusb_time_millis(void); #ifdef __cplusplus } -- cgit v1.3.1 From 063661e3a32429e2d5f74c097da72aa3679cc889 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 25 Oct 2024 00:20:34 +0700 Subject: more progress on dwc2 hcd, initial code for edpt xfer --- src/common/tusb_common.h | 8 +- src/common/tusb_types.h | 8 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 61 ++++--- src/portable/synopsys/dwc2/dwc2_common.c | 14 +- src/portable/synopsys/dwc2/dwc2_common.h | 35 +--- src/portable/synopsys/dwc2/dwc2_info.py | 1 - src/portable/synopsys/dwc2/dwc2_type.h | 149 ++++++++------- src/portable/synopsys/dwc2/hcd_dwc2.c | 301 +++++++++++++++++++++++++++---- src/tusb_option.h | 2 +- 9 files changed, 407 insertions(+), 172 deletions(-) (limited to 'src/portable') diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index d3e0cf888..59cc0fb48 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -123,11 +123,15 @@ TU_ATTR_ALWAYS_INLINE static inline int tu_memcpy_s(void *dest, size_t destsz, c //------------- Bytes -------------// TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b3, uint8_t b2, uint8_t b1, uint8_t b0) { - return ( ((uint32_t) b3) << 24) | ( ((uint32_t) b2) << 16) | ( ((uint32_t) b1) << 8) | b0; + return (((uint32_t)b3) << 24) | (((uint32_t)b2) << 16) | (((uint32_t)b1) << 8) | b0; +} + +TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32_from_u16(uint16_t high, uint16_t low) { + return (((uint32_t)high) << 16) | low; } TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low) { - return (uint16_t) ((((uint16_t) high) << 8) | low); + return (uint16_t)((((uint16_t)high) << 8) | low); } TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte3(uint32_t ui32) { return TU_U32_BYTE3(ui32); } diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 0faa6eee9..3e5aa6818 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -56,10 +56,10 @@ typedef enum { /// defined base on USB Specs Endpoint's bmAttributes typedef enum { - TUSB_XFER_CONTROL = 0 , - TUSB_XFER_ISOCHRONOUS , - TUSB_XFER_BULK , - TUSB_XFER_INTERRUPT + TUSB_XFER_CONTROL = 0, + TUSB_XFER_ISOCHRONOUS = 1, + TUSB_XFER_BULK = 2, + TUSB_XFER_INTERRUPT = 3 } tusb_xfer_type_t; typedef enum { diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index e7440529a..0731a88c1 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -56,7 +56,7 @@ static xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; // EP0 transfers are limited to 1 packet - larger sizes has to be split static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type -static uint16_t _dfifo_top; // top free location in FIFO RAM +static uint16_t _dfifo_top; // top free location in DFIFO in words // Number of IN endpoints active static uint8_t _allocated_ep_in_count; @@ -68,6 +68,12 @@ static bool _sof_en; // DMA //-------------------------------------------------------------------- +TU_ATTR_ALWAYS_INLINE static inline bool dma_device_enabled(const dwc2_regs_t* dwc2) { + (void) dwc2; + // Internal DMA only + return CFG_TUD_DWC2_DMA && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; +} + static void dma_setup_prepare(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); @@ -103,11 +109,9 @@ static void dma_setup_prepare(uint8_t rhport) { possible since the free space is located between the RX and TX FIFOs. ---------------- ep_fifo_size - | EPInfo | - | for DMA | + | EPInfo DMA | |-------------|-- gdfifocfg.EPINFOBASE (max is ghwcfg3.dfifo_depth) - | IN FIFO 0 | - | control | + | IN FIFO 0 | control EP |-------------| | IN FIFO 1 | |-------------| @@ -126,13 +130,13 @@ static void dma_setup_prepare(uint8_t rhport) { - All EP OUT shared a unique OUT FIFO which uses (for Slave or Buffer DMA, Scatt/Gather DMA use different formula): - 13 for setup packets + control words (up to 3 setup packets). - 1 for global NAK (not required/used here). - - Largest-EPsize / 4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4) + 1" + - Largest-EPsize/4 + 1. ( FS: 64 bytes, HS: 512 bytes). Recommended is "2 x (Largest-EPsize/4 + 1)" - 2 for each used OUT endpoint Therefore GRXFSIZ = 13 + 1 + 2 x (Largest-EPsize/4 + 1) + 2 x EPOUTnum */ -TU_ATTR_ALWAYS_INLINE static inline uint16_t calc_grxfsiz(uint16_t largest_ep_size, uint8_t ep_count) { +TU_ATTR_ALWAYS_INLINE static inline uint16_t calc_device_grxfsiz(uint16_t largest_ep_size, uint8_t ep_count) { return 13 + 1 + 2 * ((largest_ep_size / 4) + 1) + 2 * ep_count; } @@ -148,7 +152,7 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { uint16_t fifo_size = tu_div_ceil(packet_size, 4); if (dir == TUSB_DIR_OUT) { // Calculate required size of RX FIFO - uint16_t const new_sz = calc_grxfsiz(4 * fifo_size, ep_count); + uint16_t const new_sz = calc_device_grxfsiz(4 * fifo_size, ep_count); // If size_rx needs to be extended check if there is enough free space if (dwc2->grxfsiz < new_sz) { @@ -184,17 +188,18 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { return true; } -static void dfifo_init(uint8_t rhport) { +static void dfifo_device_init(uint8_t rhport) { const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport]; dwc2_regs_t* dwc2 = DWC2_REG(rhport); - dwc2->grxfsiz = calc_grxfsiz(CFG_TUD_ENDPOINT0_SIZE, dwc2_controller->ep_count); + dwc2->grxfsiz = calc_device_grxfsiz(CFG_TUD_ENDPOINT0_SIZE, dwc2_controller->ep_count); - if(dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE)) { - // DMA use last DFIFO to store metadata - _dfifo_top = dma_cal_epfifo_base(rhport); - }else { - _dfifo_top = dwc2_controller->ep_fifo_size / 4; + // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per endpoint direction + const bool is_dma = dma_device_enabled(dwc2); + _dfifo_top = dwc2_controller->ep_fifo_size/4; + if (is_dma) { + _dfifo_top -= 2 * dwc2_controller->ep_count; } + dwc2->gdfifocfg = (_dfifo_top << GDFIFOCFG_EPINFOBASE_SHIFT) | _dfifo_top; // Allocate FIFO for EP0 IN dfifo_alloc(rhport, 0x80, CFG_TUD_ENDPOINT0_SIZE); @@ -357,7 +362,7 @@ static void bus_reset(uint8_t rhport) { dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM; // 4. Set up DFIFO - dfifo_init(rhport); + dfifo_device_init(rhport); // 5. Reset device address dwc2->dcfg &= ~DCFG_DAD_Msk; @@ -369,7 +374,7 @@ static void bus_reset(uint8_t rhport) { xfer_status[0][TUSB_DIR_OUT].max_size = 64; xfer_status[0][TUSB_DIR_IN].max_size = 64; - if(dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE)) { + if(dma_device_enabled(dwc2)) { dma_setup_prepare(rhport); } else { dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); @@ -401,7 +406,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c dep->dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); - if(dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE)) { + if(dma_device_enabled(dwc2)) { dep->diepdma = (uintptr_t)xfer->buffer; // For ISO endpoint set correct odd/even bit for next frame. @@ -439,7 +444,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c dep->doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); } - if(dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE)) { + if(dma_device_enabled(dwc2)) { dep->doepdma = (uintptr_t)xfer->buffer; } @@ -451,11 +456,12 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c // Controller API //-------------------------------------------------------------------- bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Core Initialization - const bool is_highspeed = dwc2_core_is_highspeed(dwc2, rh_init); - const bool is_dma = dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE); + const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE); + const bool is_dma = dma_device_enabled(dwc2); TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma)); // Device Initialization @@ -463,7 +469,7 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Set device max speed uint32_t dcfg = dwc2->dcfg & ~DCFG_DSPD_Msk; - if (dwc2_core_is_highspeed(dwc2, rh_init)) { + if (is_highspeed) { dcfg |= DCFG_DSPD_HS << DCFG_DSPD_Pos; // XCVRDLY: transceiver delay between xcvr_sel and txvalid during device chirp is required @@ -611,7 +617,7 @@ void dcd_edpt_close_all(uint8_t rhport) { dfifo_flush_tx(dwc2, 0x10); // all tx fifo dfifo_flush_rx(dwc2); - dfifo_init(rhport); // re-init dfifo + dfifo_device_init(rhport); // re-init dfifo } bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { @@ -690,8 +696,9 @@ void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { } void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); edpt_disable(rhport, ep_addr, true); - if((tu_edpt_number(ep_addr) == 0) && dwc2_dma_enabled(DWC2_REG(rhport), TUSB_ROLE_DEVICE)) { + if((tu_edpt_number(ep_addr) == 0) && dma_device_enabled(dwc2)) { dma_setup_prepare(rhport); } } @@ -808,7 +815,7 @@ static void handle_epout_irq(uint8_t rhport) { if (doepint & DOEPINT_SETUP) { epout->doepint = DOEPINT_SETUP; - if(dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE)) { + if(dma_device_enabled(dwc2)) { dma_setup_prepare(rhport); } @@ -824,7 +831,7 @@ static void handle_epout_irq(uint8_t rhport) { if (!(doepint & (DOEPINT_SETUP | DOEPINT_STPKTRX | DOEPINT_STSPHSRX))) { xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - if(dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE)) { + if(dma_device_enabled(dwc2)) { if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { // EP0 can only handle one packet Schedule another packet to be received. edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); @@ -874,7 +881,7 @@ static void handle_epin_irq(uint8_t rhport) { // Schedule another packet to be transmitted. edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); } else { - if((n == 0) && dwc2_dma_enabled(dwc2, TUSB_ROLE_DEVICE)) { + if((n == 0) && dma_device_enabled(dwc2)) { dma_setup_prepare(rhport); } dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index d0ad764a5..c5990c53f 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -168,16 +168,16 @@ static bool check_dwc2(dwc2_regs_t* dwc2) { //-------------------------------------------------------------------- // //-------------------------------------------------------------------- -bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init) { +bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role) { (void)dwc2; #if CFG_TUD_ENABLED - if (rh_init->role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) { + if (role == TUSB_ROLE_DEVICE && !TUD_OPT_HIGH_SPEED) { return false; } #endif #if CFG_TUH_ENABLED - if (rh_init->role == TUSB_ROLE_HOST && !TUH_OPT_HIGH_SPEED) { + if (role == TUSB_ROLE_HOST && !TUH_OPT_HIGH_SPEED) { return false; } #endif @@ -234,15 +234,7 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) { dwc2->gintmsk = 0; - // TODO can be enabled with device as well but tested with host for now - // if (rh_init->role == TUSB_ROLE_HOST) { - // dwc2->gintmsk |= OTG_INT_COMMON; - // } - if (is_dma) { - const uint16_t epinfo_base = dma_cal_epfifo_base(rhport); - dwc2->gdfifocfg = (epinfo_base << GDFIFOCFG_EPINFOBASE_SHIFT) | epinfo_base; - // DMA seems to be only settable after a core reset, and not possible to switch on-the-fly dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2; } else { diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h index 7088ff3c3..fff21ca5c 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.h +++ b/src/portable/synopsys/dwc2/dwc2_common.h @@ -61,7 +61,9 @@ enum { OTG_INT_COMMON = 0 // GINTSTS_DISCINT | GINTSTS_CONIDSTSCHNG }; -//------------- Core -------------// +//--------------------------------------------------------------------+ +// Core/Controller +//--------------------------------------------------------------------+ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { if (rhport >= DWC2_CONTROLLER_COUNT) { // user mis-configured, ignore and use first controller @@ -70,11 +72,13 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { return (dwc2_regs_t*)_dwc2_controller[rhport].reg_base; } -bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, const tusb_rhport_init_t* rh_init); +bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role); bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma); void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr); -//------------- DFIFO -------------// +//--------------------------------------------------------------------+ +// DFIFO +//--------------------------------------------------------------------+ TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_tx(dwc2_regs_t* dwc2, uint8_t fnum) { // flush TX fifo and wait for it cleared dwc2->grstctl = GRSTCTL_TXFFLSH | (fnum << GRSTCTL_TXFNUM_Pos); @@ -86,27 +90,8 @@ TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_rx(dwc2_regs_t* dwc2) { while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {} } -//------------- DMA -------------// -TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dma_enabled(const dwc2_regs_t* dwc2, tusb_role_t role) { - (void) dwc2; - - if (CFG_TUD_DWC2_DMA == 0 && role == TUSB_ROLE_DEVICE) { - return false; - } - - if (CFG_TUH_DWC2_DMA == 0 && role == TUSB_ROLE_HOST) { - return false; - } - - // Internal DMA only - return dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; -} - -TU_ATTR_ALWAYS_INLINE static inline uint16_t dma_cal_epfifo_base(uint8_t rhport) { - // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per endpoint direction - const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport]; - return dwc2_controller->ep_fifo_size/4 - 2*dwc2_controller->ep_count; -} - +//--------------------------------------------------------------------+ +// DMA +//--------------------------------------------------------------------+ #endif diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index d97a1192e..fe08ecce9 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -24,7 +24,6 @@ dwc2_reg_value = { 'ST U5A5 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30], 'GD32VF103': [0x1000, 0, 0, 0, 0, 0], 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030] - } # Combine dwc2_info with dwc2_reg_list diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index d2993bdd9..ed335f1a3 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -138,6 +138,13 @@ enum { GINTSTS_CMODE_HOST = 1, }; +enum { + HCTSIZ_PID_DATA0 = 0, + HCTSIZ_PID_DATA2 = 1, + HCTSIZ_PID_DATA1 = 2, + HCTSIZ_PID_SETUP = 3, +}; + //-------------------------------------------------------------------- // Register bitfield definitions //-------------------------------------------------------------------- @@ -334,17 +341,49 @@ typedef struct TU_ATTR_PACKED { uint32_t speed : 2; // 17..18 Port speed uint32_t rsv19_31 :13; // 19..31 Reserved }dwc2_hprt_t; +TU_VERIFY_STATIC(sizeof(dwc2_hprt_t) == 4, "incorrect size"); + +typedef struct TU_ATTR_PACKED { + uint32_t ep_size : 11; // 0..10 Maximum packet size + uint32_t ep_num : 4; // 11..14 Endpoint number + uint32_t ep_dir : 1; // 15 Endpoint direction + uint32_t rsv16 : 1; // 16 Reserved + uint32_t low_speed_dev : 1; // 17 Low-speed device + uint32_t ep_type : 2; // 18..19 Endpoint type + uint32_t err_multi_count : 2; // 20..21 Error (splitEn = 1) / Multi (SplitEn = 0) count + uint32_t dev_addr : 7; // 22..28 Device address + uint32_t odd_frame : 1; // 29 Odd frame + uint32_t disable : 1; // 30 Channel disable + uint32_t enable : 1; // 31 Channel enable +} dwc2_channel_char_t; +TU_VERIFY_STATIC(sizeof(dwc2_channel_char_t) == 4, "incorrect size"); + +typedef struct TU_ATTR_PACKED { + uint32_t hub_port : 7; // 0..6 Hub port number + uint32_t hub_addr : 7; // 7..13 Hub address + uint32_t xact_pos : 2; // 14..15 Transaction position + uint32_t split_compl : 1; // 16 Split completion + uint32_t rsv17_30 : 14; // 17..30 Reserved + uint32_t split_en : 1; // 31 Split enable +} dwc2_channel_split_t; +TU_VERIFY_STATIC(sizeof(dwc2_channel_split_t) == 4, "incorrect size"); // Host Channel typedef struct { - volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics - volatile uint32_t hcsplt; // 504 + 20*ch Host Channel Split Control - volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt - volatile uint32_t hcintmsk; // 50C + 20*ch Host Channel Interrupt Mask - volatile uint32_t hctsiz; // 510 + 20*ch Host Channel Transfer Size - volatile uint32_t hcdma; // 514 + 20*ch Host Channel DMA Address - uint32_t reserved518; // 518 + 20*ch - volatile uint32_t hcdmab; // 51C + 20*ch Host Channel DMA Address + union { + volatile uint32_t hcchar; // 500 + 20*ch Host Channel Characteristics + volatile dwc2_channel_char_t hcchar_bm; + }; + union { + volatile uint32_t hcsplt; // 504 + 20*ch Host Channel Split Control + volatile dwc2_channel_split_t hcsplt_bm; + }; + volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt + volatile uint32_t hcintmsk; // 50C + 20*ch Host Channel Interrupt Mask + volatile uint32_t hctsiz; // 510 + 20*ch Host Channel Transfer Size + volatile uint32_t hcdma; // 514 + 20*ch Host Channel DMA Address + uint32_t reserved518; // 518 + 20*ch + volatile uint32_t hcdmab; // 51C + 20*ch Host Channel DMA Address } dwc2_channel_t; // Endpoint IN @@ -1720,15 +1759,15 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define HCSPLT_SPLITEN HCSPLT_SPLITEN_Msk // Split enable /******************** Bit definition for HCINT register ********************/ -#define HCINT_XFRC_Pos (0U) -#define HCINT_XFRC_Msk (0x1UL << HCINT_XFRC_Pos) // 0x00000001 -#define HCINT_XFRC HCINT_XFRC_Msk // Transfer completed -#define HCINT_CHH_Pos (1U) -#define HCINT_CHH_Msk (0x1UL << HCINT_CHH_Pos) // 0x00000002 -#define HCINT_CHH HCINT_CHH_Msk // Channel halted -#define HCINT_AHBERR_Pos (2U) -#define HCINT_AHBERR_Msk (0x1UL << HCINT_AHBERR_Pos) // 0x00000004 -#define HCINT_AHBERR HCINT_AHBERR_Msk // AHB error +#define HCINT_XFER_COMPLETE_Pos (0U) +#define HCINT_XFER_COMPLETE_Msk (0x1UL << HCINT_XFER_COMPLETE_Pos) // 0x00000001 +#define HCINT_XFER_COMPLETE HCINT_XFER_COMPLETE_Msk // Transfer completed +#define HCINT_CHANNEL_HALTED_Pos (1U) +#define HCINT_CHANNEL_HALTED_Msk (0x1UL << HCINT_CHANNEL_HALTED_Pos) // 0x00000002 +#define HCINT_CHANNEL_HALTED HCINT_CHANNEL_HALTED_Msk // Channel halted +#define HCINT_AHB_ERR_Pos (2U) +#define HCINT_AHB_ERR_Msk (0x1UL << HCINT_AHB_ERR_Pos) // 0x00000004 +#define HCINT_AHB_ERR HCINT_AHB_ERR_Msk // AHB error #define HCINT_STALL_Pos (3U) #define HCINT_STALL_Msk (0x1UL << HCINT_STALL_Pos) // 0x00000008 #define HCINT_STALL HCINT_STALL_Msk // STALL response received interrupt @@ -1741,18 +1780,27 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define HCINT_NYET_Pos (6U) #define HCINT_NYET_Msk (0x1UL << HCINT_NYET_Pos) // 0x00000040 #define HCINT_NYET HCINT_NYET_Msk // Response received interrupt -#define HCINT_TXERR_Pos (7U) -#define HCINT_TXERR_Msk (0x1UL << HCINT_TXERR_Pos) // 0x00000080 -#define HCINT_TXERR HCINT_TXERR_Msk // Transaction error -#define HCINT_BBERR_Pos (8U) -#define HCINT_BBERR_Msk (0x1UL << HCINT_BBERR_Pos) // 0x00000100 -#define HCINT_BBERR HCINT_BBERR_Msk // Babble error -#define HCINT_FRMOR_Pos (9U) -#define HCINT_FRMOR_Msk (0x1UL << HCINT_FRMOR_Pos) // 0x00000200 -#define HCINT_FRMOR HCINT_FRMOR_Msk // Frame overrun -#define HCINT_DTERR_Pos (10U) -#define HCINT_DTERR_Msk (0x1UL << HCINT_DTERR_Pos) // 0x00000400 -#define HCINT_DTERR HCINT_DTERR_Msk // Data toggle error +#define HCINT_XACT_ERR_Pos (7U) +#define HCINT_XACT_ERR_Msk (0x1UL << HCINT_XACT_ERR_Pos) // 0x00000080 +#define HCINT_XACT_ERR HCINT_XACT_ERR_Msk // Transaction error +#define HCINT_BABBLE_ERR_Pos (8U) +#define HCINT_BABBLE_ERR_Msk (0x1UL << HCINT_BABBLE_ERR_Pos) // 0x00000100 +#define HCINT_BABBLE_ERR HCINT_BABBLE_ERR_Msk // Babble error +#define HCINT_FARME_OVERRUN_Pos (9U) +#define HCINT_FARME_OVERRUN_Msk (0x1UL << HCINT_FARME_OVERRUN_Pos) // 0x00000200 +#define HCINT_FARME_OVERRUN HCINT_FARME_OVERRUN_Msk // Frame overrun +#define HCINT_DATATOGGLE_ERR_Pos (10U) +#define HCINT_DATATOGGLE_ERR_Msk (0x1UL << HCINT_DATATOGGLE_ERR_Pos) // 0x00000400 +#define HCINT_DATATOGGLE_ERR HCINT_DATATOGGLE_ERR_Msk // Data toggle error +#define HCINT_BUFFER_NAK_Pos (11U) +#define HCINT_BUFFER_NAK_Msk (0x1UL << HCINT_BUFFER_NAK_Pos) // 0x00000800 +#define HCINT_BUFFER_NAK HCINT_BUFFER_NAK_Msk // Buffer not available interrupt +#define HCINT_XCS_XACT_ERR_Pos (12U) +#define HCINT_XCS_XACT_ERR_Msk (0x1UL << HCINT_XCS_XACT_ERR_Pos) // 0x00001000 +#define HCINT_XCS_XACT_ERR HCINT_XCS_XACT_ERR_Msk // Excessive transaction error +#define HCINT_DESC_ROLLOVER_Pos (13U) +#define HCINT_DESC_ROLLOVER_Msk (0x1UL << HCINT_DESC_ROLLOVER_Pos) // 0x00002000 +#define HCINT_DESC_ROLLOVER HCINT_DESC_ROLLOVER_Msk // Descriptor rollover /******************** Bit definition for DIEPINT register ********************/ #define DIEPINT_XFRC_Pos (0U) @@ -1795,41 +1843,6 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define DIEPINT_NAK_Msk (0x1UL << DIEPINT_NAK_Pos) // 0x00002000 #define DIEPINT_NAK DIEPINT_NAK_Msk // NAK interrupt -/******************** Bit definition for HCINTMSK register ********************/ -#define HCINTMSK_XFRCM_Pos (0U) -#define HCINTMSK_XFRCM_Msk (0x1UL << HCINTMSK_XFRCM_Pos) // 0x00000001 -#define HCINTMSK_XFRCM HCINTMSK_XFRCM_Msk // Transfer completed mask -#define HCINTMSK_CHHM_Pos (1U) -#define HCINTMSK_CHHM_Msk (0x1UL << HCINTMSK_CHHM_Pos) // 0x00000002 -#define HCINTMSK_CHHM HCINTMSK_CHHM_Msk // Channel halted mask -#define HCINTMSK_AHBERR_Pos (2U) -#define HCINTMSK_AHBERR_Msk (0x1UL << HCINTMSK_AHBERR_Pos) // 0x00000004 -#define HCINTMSK_AHBERR HCINTMSK_AHBERR_Msk // AHB error -#define HCINTMSK_STALLM_Pos (3U) -#define HCINTMSK_STALLM_Msk (0x1UL << HCINTMSK_STALLM_Pos) // 0x00000008 -#define HCINTMSK_STALLM HCINTMSK_STALLM_Msk // STALL response received interrupt mask -#define HCINTMSK_NAKM_Pos (4U) -#define HCINTMSK_NAKM_Msk (0x1UL << HCINTMSK_NAKM_Pos) // 0x00000010 -#define HCINTMSK_NAKM HCINTMSK_NAKM_Msk // NAK response received interrupt mask -#define HCINTMSK_ACKM_Pos (5U) -#define HCINTMSK_ACKM_Msk (0x1UL << HCINTMSK_ACKM_Pos) // 0x00000020 -#define HCINTMSK_ACKM HCINTMSK_ACKM_Msk // ACK response received/transmitted interrupt mask -#define HCINTMSK_NYET_Pos (6U) -#define HCINTMSK_NYET_Msk (0x1UL << HCINTMSK_NYET_Pos) // 0x00000040 -#define HCINTMSK_NYET HCINTMSK_NYET_Msk // response received interrupt mask -#define HCINTMSK_TXERRM_Pos (7U) -#define HCINTMSK_TXERRM_Msk (0x1UL << HCINTMSK_TXERRM_Pos) // 0x00000080 -#define HCINTMSK_TXERRM HCINTMSK_TXERRM_Msk // Transaction error mask -#define HCINTMSK_BBERRM_Pos (8U) -#define HCINTMSK_BBERRM_Msk (0x1UL << HCINTMSK_BBERRM_Pos) // 0x00000100 -#define HCINTMSK_BBERRM HCINTMSK_BBERRM_Msk // Babble error mask -#define HCINTMSK_FRMORM_Pos (9U) -#define HCINTMSK_FRMORM_Msk (0x1UL << HCINTMSK_FRMORM_Pos) // 0x00000200 -#define HCINTMSK_FRMORM HCINTMSK_FRMORM_Msk // Frame overrun mask -#define HCINTMSK_DTERRM_Pos (10U) -#define HCINTMSK_DTERRM_Msk (0x1UL << HCINTMSK_DTERRM_Pos) // 0x00000400 -#define HCINTMSK_DTERRM HCINTMSK_DTERRM_Msk // Data toggle error mask - /******************** Bit definition for DIEPTSIZ register ********************/ #define DIEPTSIZ_XFRSIZ_Pos (0U) @@ -1851,11 +1864,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define HCTSIZ_DOPING_Pos (31U) #define HCTSIZ_DOPING_Msk (0x1UL << HCTSIZ_DOPING_Pos) // 0x80000000 #define HCTSIZ_DOPING HCTSIZ_DOPING_Msk // Do PING -#define HCTSIZ_DPID_Pos (29U) -#define HCTSIZ_DPID_Msk (0x3UL << HCTSIZ_DPID_Pos) // 0x60000000 -#define HCTSIZ_DPID HCTSIZ_DPID_Msk // Data PID -#define HCTSIZ_DPID_0 (0x1UL << HCTSIZ_DPID_Pos) // 0x20000000 -#define HCTSIZ_DPID_1 (0x2UL << HCTSIZ_DPID_Pos) // 0x40000000 +#define HCTSIZ_PID_Pos (29U) +#define HCTSIZ_PID_Msk (0x3UL << HCTSIZ_PID_Pos) // 0x60000000 +#define HCTSIZ_PID HCTSIZ_PID_Msk // Data PID /******************** Bit definition for DIEPDMA register ********************/ #define DIEPDMA_DMAADDR_Pos (0U) diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index bb5086631..f37bf717d 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -34,10 +34,37 @@ #include "host/hcd.h" #include "dwc2_common.h" +// DWC2 has limit number of channel, in order to support all endpoints we can store channel char/split to swap later on +#ifndef CFG_TUH_DWC2_CHANNEL_MAX +#define CFG_TUH_DWC2_CHANNEL_MAX (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX + CFG_TUH_HUB) +#endif + enum { HPRT_W1C_MASK = HPRT_CONN_DETECT | HPRT_ENABLE | HPRT_ENABLE_CHANGE | HPRT_OVER_CURRENT_CHANGE }; +typedef struct { + union { + uint32_t hcchar; + dwc2_channel_char_t hcchar_bm; + }; + union { + uint32_t hcsplt; + dwc2_channel_split_t hcsplt_bm; + }; + + uint8_t next_data_toggle; +} hcd_pipe_t; + +typedef struct { + hcd_pipe_t pipe[CFG_TUH_DWC2_CHANNEL_MAX]; +} dwc2_hcd_t; + +dwc2_hcd_t _hcd_data; + +//-------------------------------------------------------------------- +// +//-------------------------------------------------------------------- TU_ATTR_ALWAYS_INLINE static inline tusb_speed_t convert_hprt_speed(uint32_t hprt_speed) { tusb_speed_t speed; switch(hprt_speed) { @@ -49,6 +76,85 @@ TU_ATTR_ALWAYS_INLINE static inline tusb_speed_t convert_hprt_speed(uint32_t hpr return speed; } +TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc2) { + (void) dwc2; + // Internal DMA only + return CFG_TUH_DWC2_DMA && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; +} + +/* USB Data FIFO Layout + + The FIFO is split up into + - EPInfo: for storing DMA metadata (check dcd_dwc2.c for more details) + - 1 RX FIFO: for receiving data + - 1 TX FIFO for non-periodic (NPTX) + - 1 TX FIFO for periodic (PTX) + + We allocated TX FIFO from top to bottom (using top pointer), this to allow the RX FIFO to grow dynamically which is + possible since the free space is located between the RX and TX FIFOs. + + ----------------- ep_fifo_size + | EPInfo DMA | + |--------------|-- gdfifocfg.EPINFOBASE (max is ghwcfg3.dfifo_depth) + | Non-Periodic | + | TX FIFO | + |--------------|--- GNPTXFSIZ.addr (fixed size) + | Periodic | + | TX FIFO | + |--------------|--- HPTXFSIZ.addr (expandable downward) + | FREE | + | | + |--------------|-- GRXFSIZ (expandable upward) + | RX FIFO | + ---------------- 0 +*/ + +/* Programming Guide 2.1.2 FIFO RAM allocation + * RX + * - Largest-EPsize/4 + 2 (status info). recommended x2 if high bandwidth or multiple ISO are used. + * - 2 for transfer complete and channel halted status + * - 1 for each Control/Bulk out endpoint to Handle NAK/NYET (i.e max is number of host channel) + * + * TX non-periodic (NPTX) + * - At least largest-EPsize/4, recommended x2 + * + * TX periodic (PTX) + * - At least largest-EPsize*MulCount/4 (MulCount up to 3 for high-bandwidth ISO/interrupt) +*/ +static void dfifo_host_init(uint8_t rhport) { + const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport]; + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + + // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per channel + const bool is_dma = dma_host_enabled(dwc2); + uint16_t dfifo_top = dwc2_controller->ep_fifo_size/4; + if (is_dma) { + dfifo_top -= dwc2->ghwcfg2_bm.num_host_ch; + } + + // fixed allocation for now, improve later: + // - ptx_largest is limited to 256 for FS since most FS core only has 1024 bytes total + bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_HOST); + uint32_t nptx_largest = is_highspeed ? TUSB_EPSIZE_BULK_HS/4 : TUSB_EPSIZE_BULK_FS/4; + uint32_t ptx_largest = is_highspeed ? TUSB_EPSIZE_ISO_HS_MAX/4 : 256/4; + + uint16_t nptxfsiz = 2 * nptx_largest; + uint16_t rxfsiz = 2 * (ptx_largest + 2) + dwc2->ghwcfg2_bm.num_host_ch; + TU_ASSERT(dfifo_top >= (nptxfsiz + rxfsiz),); + uint16_t ptxfsiz = dfifo_top - (nptxfsiz + rxfsiz); + + dwc2->gdfifocfg = (dfifo_top << GDFIFOCFG_EPINFOBASE_SHIFT) | dfifo_top; + + dfifo_top -= rxfsiz; + dwc2->grxfsiz = rxfsiz; + + dfifo_top -= nptxfsiz; + dwc2->gnptxfsiz = tu_u32_from_u16(nptxfsiz, dfifo_top); + + dfifo_top -= ptxfsiz; + dwc2->hptxfsiz = tu_u32_from_u16(ptxfsiz, dfifo_top); +} + //--------------------------------------------------------------------+ // Controller API //--------------------------------------------------------------------+ @@ -64,11 +170,14 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { // Initialize controller to host mode bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { + (void) rh_init; dwc2_regs_t* dwc2 = DWC2_REG(rhport); + tu_memclr(&_hcd_data, sizeof(_hcd_data)); + // Core Initialization - const bool is_highspeed = dwc2_core_is_highspeed(dwc2, rh_init); - const bool is_dma = dwc2_dma_enabled(dwc2, TUSB_ROLE_HOST); + const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_HOST); + const bool is_dma = dma_host_enabled(dwc2); TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma)); //------------- 3.1 Host Initialization -------------// @@ -98,6 +207,9 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD; while( (dwc2->gintsts & GINTSTS_CMOD) != GINTSTS_CMODE_HOST) {} + // configure fixed-allocated fifo scheme + dfifo_host_init(rhport); + dwc2->hprt = HPRT_W1C_MASK; // clear all write-1-clear bits dwc2->hprt = HPRT_POWER; // turn on VBUS @@ -169,23 +281,108 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { //--------------------------------------------------------------------+ // Open an endpoint -bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { +// channel0 is reserved for dev0 control endpoint +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep) { (void) rhport; - (void) dev_addr; - (void) ep_desc; + //dwc2_regs_t* dwc2 = DWC2_REG(rhport); + + hcd_devtree_info_t devtree_info; + hcd_devtree_get_info(dev_addr, &devtree_info); + + // find a free pipe + for (uint32_t i = 0; i < CFG_TUH_DWC2_CHANNEL_MAX; i++) { + hcd_pipe_t* pipe = &_hcd_data.pipe[i]; + dwc2_channel_char_t* hcchar_bm = &pipe->hcchar_bm; + dwc2_channel_split_t* hcsplt_bm = &pipe->hcsplt_bm; + + if (hcchar_bm->enable == 0) { + hcchar_bm->ep_size = tu_edpt_packet_size(desc_ep); + hcchar_bm->ep_num = tu_edpt_number(desc_ep->bEndpointAddress); + hcchar_bm->ep_dir = tu_edpt_dir(desc_ep->bEndpointAddress); + hcchar_bm->low_speed_dev = (devtree_info.speed == TUSB_SPEED_LOW) ? 1 : 0; + hcchar_bm->ep_type = desc_ep->bmAttributes.xfer; + hcchar_bm->err_multi_count = 0; + hcchar_bm->dev_addr = dev_addr; + hcchar_bm->odd_frame = 0; + hcchar_bm->disable = 0; + hcchar_bm->enable = 1; + + hcsplt_bm->hub_port = devtree_info.hub_port; + hcsplt_bm->hub_addr = devtree_info.hub_addr; + // TODO not support split transaction yet + hcsplt_bm->xact_pos = 0; + hcsplt_bm->split_compl = 0; + hcsplt_bm->split_en = 0; + + pipe->next_data_toggle = HCTSIZ_PID_DATA0; + + return true; + } + } return false; } +TU_ATTR_ALWAYS_INLINE static inline uint8_t find_free_channel(dwc2_regs_t* dwc2) { + const uint8_t max_channel = tu_min8(dwc2->ghwcfg2_bm.num_host_ch, 16); + for (uint8_t i=0; ihaintmsk, i)) { + return i; + } + } + return TUSB_INDEX_INVALID_8; +} + +TU_ATTR_ALWAYS_INLINE static inline uint8_t find_opened_pipe(uint8_t dev_addr, uint8_t ep_addr) { + for (uint32_t i = 0; i < CFG_TUH_DWC2_CHANNEL_MAX; i++) { + const dwc2_channel_char_t* hcchar_bm = &_hcd_data.pipe[i].hcchar_bm; + if (hcchar_bm->enable && hcchar_bm->dev_addr == dev_addr && + ep_addr == tu_edpt_addr(hcchar_bm->ep_num, hcchar_bm->ep_dir)) { + return i; + } + } + return TUSB_INDEX_INVALID_8; +} + // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { - (void) rhport; - (void) dev_addr; - (void) ep_addr; - (void) buffer; - (void) buflen; + dwc2_regs_t* dwc2 = DWC2_REG(rhport); - return false; + uint8_t pipe_id = find_opened_pipe(dev_addr, ep_addr); + TU_ASSERT(pipe_id < CFG_TUH_DWC2_CHANNEL_MAX); // no opened pipe + hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; + const dwc2_channel_char_t* hcchar_bm = &pipe->hcchar_bm; + + uint8_t ch_id = find_free_channel(dwc2); + TU_ASSERT(ch_id < 16); // all channel are in use + dwc2->haintmsk |= TU_BIT(ch_id); + + dwc2_channel_t* channel = &dwc2->channel[ch_id]; + channel->hcintmsk = HCINT_XFER_COMPLETE | HCINT_CHANNEL_HALTED | HCINT_STALL | + HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR; + + const uint16_t packet_count = tu_div_ceil(buflen, hcchar_bm->ep_size); + channel->hctsiz = (pipe->next_data_toggle << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | buflen; + + // Control transfer always start with DATA1 for data and status stage. May has issue with ZLP + if (pipe->next_data_toggle == HCTSIZ_PID_DATA0 || tu_edpt_number(ep_addr) == 0) { + pipe->next_data_toggle = HCTSIZ_PID_DATA1; + } else { + pipe->next_data_toggle = HCTSIZ_PID_DATA0; + } + + if (dma_host_enabled(dwc2)) { + channel->hcdma = (uint32_t) buffer; + } else { + TU_ASSERT(false); // not yet support + } + + // TODO support split transaction + channel->hcsplt = pipe->hcsplt; + channel->hcchar = pipe->hcchar; // kick-off transfer + + return true; } // Abort a queued transfer. Note: it can only abort transfer that has not been started @@ -199,12 +396,13 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { } // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked -bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { - (void) rhport; - (void) dev_addr; - (void) setup_packet; +bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, const uint8_t setup_packet[8]) { + uint8_t pipe_id = find_opened_pipe(dev_addr, 0); + TU_ASSERT(pipe_id < CFG_TUH_DWC2_CHANNEL_MAX); // no opened pipe + hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; + pipe->next_data_toggle = HCTSIZ_PID_SETUP; - return false; + return hcd_edpt_xfer(rhport, dev_addr, 0, (uint8_t*)(uintptr_t) setup_packet, 8); } // clear stall, data toggle is also reset to DATA0 @@ -300,23 +498,55 @@ TU_ATTR_ALWAYS_INLINE static inline void handle_hprt_irq(uint8_t rhport, bool in dwc2->hprt = hprt; // clear interrupt } -/* Interrupt Hierarchy +void handle_channel_irq(uint8_t rhport, bool in_isr) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + for(uint8_t ch_id=0; ch_id<32; ch_id++) { + if (tu_bit_test(dwc2->haint, ch_id)) { + dwc2_channel_t* channel = &dwc2->channel[ch_id]; + uint32_t hcint = channel->hcint; + hcint &= channel->hcintmsk; + + xfer_result_t result = XFER_RESULT_FAILED; + if (hcint & HCINT_XFER_COMPLETE) { + result = XFER_RESULT_SUCCESS; + } + if (hcint & HCINT_STALL) { + result = XFER_RESULT_STALLED; + } + if (hcint & (HCINT_CHANNEL_HALTED | HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR | + HCINT_BUFFER_NAK | HCINT_XCS_XACT_ERR | HCINT_DESC_ROLLOVER)) { + result = XFER_RESULT_FAILED; + } + + const uint8_t ep_addr = tu_edpt_addr(channel->hcchar_bm.ep_num, channel->hcchar_bm.ep_dir); + hcd_event_xfer_complete(channel->hcchar_bm.dev_addr, ep_addr, 0, result, in_isr); - HCINTn.XferCompl HCINTMSKn.XferComplMsk - | | - +---------- AND --------+ - | - HAINT.CHn HAINTMSK.CHn - | | - +---------- AND --------+ - | - GINTSTS.PrtInt GINTMSK.PrtInt - | | - +---------- AND --------+ - | - GAHBCFG.GblIntrMsk - | - IRQn + channel->hcint = hcint; // clear all interrupt flags + + // de-allocate channel by clearing haintmsk + dwc2->haintmsk &= ~TU_BIT(ch_id); + } + } +} + +/* Interrupt Hierarchy + HCINTn.XferCompl HCINTMSKn.XferComplMsk HPRT ConnDetect PrtEnChng OverCurChng + | | | | | + +---------- AND --------+ +------------ OR -----------+ + | | + HAINT.CHn HAINTMSK.CHn | + | | | + +---------- AND --------+ | + | | + GINTSTS.HCInt GINTMSK.HCInt GINTSTS.PrtInt GINTMSK.PrtInt + | | | | + +---------- AND ---------+ +---------- AND ---------+ + | | + +-------------------- OR ---------------------------+ + | + GAHBCFG.GblIntrMsk + | + IRQn */ void hcd_int_handler(uint8_t rhport, bool in_isr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); @@ -336,10 +566,17 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { } if (int_status & GINTSTS_HPRTINT) { + // Host port interrupt: source is cleared in HPRT register TU_LOG1_HEX(dwc2->hprt); handle_hprt_irq(rhport, in_isr); } + if (int_status & GINTSTS_HCINT) { + // Host Channel interrupt: source is cleared in HCINT register + TU_LOG1_HEX(dwc2->hprt); + handle_channel_irq(rhport, in_isr); + } + // RxFIFO non-empty interrupt handling. if (int_status & GINTSTS_RXFLVL) { // RXFLVL bit is read-only diff --git a/src/tusb_option.h b/src/tusb_option.h index 3607a8c1a..f3a8bb724 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -255,7 +255,7 @@ #endif #ifndef CFG_TUH_DWC2_DMA - #define CFG_TUH_DWC2_DMA 0 + #define CFG_TUH_DWC2_DMA 1 #endif // Enable PIO-USB software host controller -- cgit v1.3.1 From 07abc722b69ea95c6234c3dfc9a1473b43150915 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 25 Oct 2024 19:00:45 +0700 Subject: hcd able to send setup packet --- src/portable/synopsys/dwc2/dcd_dwc2.c | 99 +++++-------------- src/portable/synopsys/dwc2/dwc2_common.c | 63 +++++++++++- src/portable/synopsys/dwc2/dwc2_common.h | 4 + src/portable/synopsys/dwc2/dwc2_type.h | 110 ++++++++++++++------- src/portable/synopsys/dwc2/hcd_dwc2.c | 163 +++++++++++++++++++++++-------- 5 files changed, 287 insertions(+), 152 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 0731a88c1..b389b0f74 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -94,7 +94,7 @@ static void dma_setup_prepare(uint8_t rhport) { //--------------------------------------------------------------------+ -/* USB Data FIFO Layout +/* Device Data FIFO scheme The FIFO is split up into - EPInfo: for storing DMA metadata, only required when use DMA. Maximum size is called @@ -109,7 +109,7 @@ static void dma_setup_prepare(uint8_t rhport) { possible since the free space is located between the RX and TX FIFOs. ---------------- ep_fifo_size - | EPInfo DMA | + | DxEPIDMAn | |-------------|-- gdfifocfg.EPINFOBASE (max is ghwcfg3.dfifo_depth) | IN FIFO 0 | control EP |-------------| @@ -167,7 +167,7 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { } // If The TXFELVL is configured as half empty, the fifo must be twice the max_size. - if ((dwc2->gahbcfg & GAHBCFG_TXFELVL) == 0) { + if ((dwc2->gahbcfg & GAHBCFG_TX_FIFO_EPMTY_LVL) == 0) { fifo_size *= 2; } @@ -205,59 +205,10 @@ static void dfifo_device_init(uint8_t rhport) { dfifo_alloc(rhport, 0x80, CFG_TUD_ENDPOINT0_SIZE); } -// Read a single data packet from receive FIFO -static void dfifo_read_packet(uint8_t rhport, uint8_t* dst, uint16_t len) { - (void) rhport; - - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - volatile const uint32_t* rx_fifo = dwc2->fifo[0]; - - // Reading full available 32 bit words from fifo - uint16_t full_words = len >> 2; - while (full_words--) { - tu_unaligned_write32(dst, *rx_fifo); - dst += 4; - } - - // Read the remaining 1-3 bytes from fifo - uint8_t const bytes_rem = len & 0x03; - if (bytes_rem != 0) { - uint32_t const tmp = *rx_fifo; - dst[0] = tu_u32_byte0(tmp); - if (bytes_rem > 1) dst[1] = tu_u32_byte1(tmp); - if (bytes_rem > 2) dst[2] = tu_u32_byte2(tmp); - } -} - -// Write a single data packet to EPIN FIFO -static void dfifo_write_packet(uint8_t rhport, uint8_t fifo_num, uint8_t const* src, uint16_t len) { - (void) rhport; - - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - volatile uint32_t* tx_fifo = dwc2->fifo[fifo_num]; - - // Pushing full available 32 bit words to fifo - uint16_t full_words = len >> 2; - while (full_words--) { - *tx_fifo = tu_unaligned_read32(src); - src += 4; - } - - // Write the remaining 1-3 bytes into fifo - uint8_t const bytes_rem = len & 0x03; - if (bytes_rem) { - uint32_t tmp_word = src[0]; - if (bytes_rem > 1) tmp_word |= (src[1] << 8); - if (bytes_rem > 2) tmp_word |= (src[2] << 16); - - *tx_fifo = tmp_word; - } -} //-------------------------------------------------------------------- // Endpoint //-------------------------------------------------------------------- - static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); @@ -404,7 +355,7 @@ static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t c if (dir == TUSB_DIR_IN) { // A full IN transfer (multiple packets, possibly) triggers XFRC. dep->dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | - ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); + ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); if(dma_device_enabled(dwc2)) { dep->diepdma = (uintptr_t)xfer->buffer; @@ -648,11 +599,10 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to // Schedule the first transaction for EP0 transfer edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]); } else { - uint16_t num_packets = (total_bytes / xfer->max_size); - uint16_t const short_packet_size = total_bytes % xfer->max_size; - - // Zero-size packet is special case. - if ((short_packet_size > 0) || (total_bytes == 0)) num_packets++; + uint16_t num_packets = tu_div_ceil(total_bytes, xfer->max_size); + if (num_packets == 0) { + num_packets = 1; // zero length packet still count as 1 + } // Schedule packets to be sent within interrupt edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); @@ -758,7 +708,7 @@ static void handle_rxflvl_irq(uint8_t rhport) { tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt); } else { // Linear buffer - dfifo_read_packet(rhport, xfer->buffer, bcnt); + dfifo_read_packet(dwc2, xfer->buffer, bcnt); // Increment pointer to xfer data xfer->buffer += bcnt; @@ -863,8 +813,7 @@ static void handle_epout_irq(uint8_t rhport) { static void handle_epin_irq(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint8_t const ep_count = _dwc2_controller[rhport].ep_count; - dwc2_epin_t* epin = dwc2->epin; + const uint8_t ep_count = _dwc2_controller[rhport].ep_count; // DAINT for a given EP clears when DIEPINTx is cleared. // IEPINT will be cleared when DAINT's out bits are cleared. @@ -872,9 +821,10 @@ static void handle_epin_irq(uint8_t rhport) { if (dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + n)) { // IN XFER complete (entire xfer). xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_IN); + dwc2_epin_t* epin = &dwc2->epin[n]; - if (epin[n].diepint & DIEPINT_XFRC) { - epin[n].diepint = DIEPINT_XFRC; + if (epin->diepint & DIEPINT_XFRC) { + epin->diepint = DIEPINT_XFRC; // EP0 can only handle one packet if ((n == 0) && ep0_pending[TUSB_DIR_IN]) { @@ -889,39 +839,38 @@ static void handle_epin_irq(uint8_t rhport) { } // XFER FIFO empty - if ((epin[n].diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n))) { + if ((epin->diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n))) { // diepint's TXFE bit is read-only, software cannot clear it. // It will only be cleared by hardware when written bytes is more than // - 64 bytes or - // - Half of TX FIFO size (configured by DIEPTXF) - - uint16_t remaining_packets = (epin[n].dieptsiz & DIEPTSIZ_PKTCNT_Msk) >> DIEPTSIZ_PKTCNT_Pos; + // - Half/Empty of TX FIFO size (configured by GAHBCFG.TXFELVL) + const uint16_t remain_packets = epin->dieptsiz_bm.packet_count; // Process every single packet (only whole packets can be written to fifo) - for (uint16_t i = 0; i < remaining_packets; i++) { - uint16_t const remaining_bytes = (epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos; + for (uint16_t i = 0; i < remain_packets; i++) { + const uint16_t remain_bytes = epin->dieptsiz_bm.xfer_size; // Packet can not be larger than ep max size - uint16_t const packet_size = tu_min16(remaining_bytes, xfer->max_size); + const uint16_t packet_size = tu_min16(remain_bytes, xfer->max_size); // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current // EP has to be checked if the buffer can take another WHOLE packet - if (packet_size > ((epin[n].dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) break; + if (packet_size > ((epin->dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) { + break; + } // Push packet to Tx-FIFO if (xfer->ff) { volatile uint32_t* tx_fifo = dwc2->fifo[n]; tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, packet_size); } else { - dfifo_write_packet(rhport, n, xfer->buffer, packet_size); - - // Increment pointer to xfer data + dfifo_write_packet(dwc2, n, xfer->buffer, packet_size); xfer->buffer += packet_size; } } // Turn off TXFE if all bytes are written. - if (((epin[n].dieptsiz & DIEPTSIZ_XFRSIZ_Msk) >> DIEPTSIZ_XFRSIZ_Pos) == 0) { + if (epin->dieptsiz_bm.xfer_size == 0) { dwc2->diepempmsk &= ~(1 << n); } } diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index c5990c53f..1527932a5 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -158,7 +158,8 @@ static bool check_dwc2(dwc2_regs_t* dwc2) { // For some reason: GD32VF103 gsnpsid and all hwcfg register are always zero (skip it) (void)dwc2; #if !TU_CHECK_MCU(OPT_MCU_GD32VF103) - uint32_t const gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK; + enum { GSNPSID_ID_MASK = TU_GENMASK(31, 16) }; + const uint32_t gsnpsid = dwc2->gsnpsid & GSNPSID_ID_MASK; TU_ASSERT(gsnpsid == DWC2_OTG_ID || gsnpsid == DWC2_FS_IOT_ID || gsnpsid == DWC2_HS_IOT_ID); #endif @@ -200,7 +201,7 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) { TU_ASSERT(check_dwc2(dwc2)); // disable global interrupt - // dwc2->gahbcfg &= ~GAHBCFG_GINT; + dwc2->gahbcfg &= ~GAHBCFG_GINT; if (is_highspeed) { phy_hs_init(dwc2); @@ -241,8 +242,8 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) { dwc2->gintmsk |= GINTMSK_RXFLVLM; } - // Configure TX FIFO empty level for interrupt. Default is complete empty - dwc2->gahbcfg |= GAHBCFG_TXFELVL; + // (non-periodic) TX FIFO empty level for interrupt is complete empty + dwc2->gahbcfg |= GAHBCFG_TX_FIFO_EPMTY_LVL; return true; } @@ -260,4 +261,58 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) { // // } +//-------------------------------------------------------------------- +// DFIFO +//-------------------------------------------------------------------- +// Read a single data packet from receive DFIFO +void dfifo_read_packet(dwc2_regs_t* dwc2, uint8_t* dst, uint16_t len) { + const volatile uint32_t* rx_fifo = dwc2->fifo[0]; + + // Reading full available 32 bit words from fifo + uint16_t word_count = len >> 2; + while (word_count--) { + tu_unaligned_write32(dst, *rx_fifo); + dst += 4; + } + + // Read the remaining 1-3 bytes from fifo + const uint8_t bytes_rem = len & 0x03; + if (bytes_rem != 0) { + const uint32_t tmp = *rx_fifo; + dst[0] = tu_u32_byte0(tmp); + if (bytes_rem > 1) { + dst[1] = tu_u32_byte1(tmp); + } + if (bytes_rem > 2) { + dst[2] = tu_u32_byte2(tmp); + } + } +} + +// Write a single data packet to DFIFO +void dfifo_write_packet(dwc2_regs_t* dwc2, uint8_t fifo_num, const uint8_t* src, uint16_t len) { + volatile uint32_t* tx_fifo = dwc2->fifo[fifo_num]; + + // Pushing full available 32 bit words to fifo + uint16_t word_count = len >> 2; + while (word_count--) { + *tx_fifo = tu_unaligned_read32(src); + src += 4; + } + + // Write the remaining 1-3 bytes into fifo + const uint8_t bytes_rem = len & 0x03; + if (bytes_rem) { + uint32_t tmp_word = src[0]; + if (bytes_rem > 1) { + tmp_word |= (src[1] << 8); + } + if (bytes_rem > 2) { + tmp_word |= (src[2] << 16); + } + + *tx_fifo = tmp_word; + } +} + #endif diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h index fff21ca5c..18b93894f 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.h +++ b/src/portable/synopsys/dwc2/dwc2_common.h @@ -84,12 +84,16 @@ TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_tx(dwc2_regs_t* dwc2, uint8 dwc2->grstctl = GRSTCTL_TXFFLSH | (fnum << GRSTCTL_TXFNUM_Pos); while (dwc2->grstctl & GRSTCTL_TXFFLSH_Msk) {} } + TU_ATTR_ALWAYS_INLINE static inline void dfifo_flush_rx(dwc2_regs_t* dwc2) { // flush RX fifo and wait for it cleared dwc2->grstctl = GRSTCTL_RXFFLSH; while (dwc2->grstctl & GRSTCTL_RXFFLSH_Msk) {} } +void dfifo_read_packet(dwc2_regs_t* dwc2, uint8_t* dst, uint16_t len); +void dfifo_write_packet(dwc2_regs_t* dwc2, uint8_t fifo_num, uint8_t const* src, uint16_t len); + //--------------------------------------------------------------------+ // DMA //--------------------------------------------------------------------+ diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index ed335f1a3..36e917d43 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -146,7 +146,7 @@ enum { }; //-------------------------------------------------------------------- -// Register bitfield definitions +// Common Register Bitfield //-------------------------------------------------------------------- typedef struct TU_ATTR_PACKED { uint32_t ses_req_scs : 1; // 0 Session request success @@ -324,6 +324,20 @@ typedef struct TU_ATTR_PACKED { }dwc2_ghwcfg4_t; TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size"); +//-------------------------------------------------------------------- +// Host Register Bitfield +//-------------------------------------------------------------------- + +typedef struct TU_ATTR_PACKED { + uint32_t fifo_available : 16; // 0..15 Number of words available in the Tx FIFO + uint32_t queue_available : 8; // 16..23 Number of spaces available in the NPT transmit request queue for both IN and OUT + // 24..31 is top entry in the request queue that is currently being processed by the MAC + uint32_t qtop_terminate : 1; // 24 Last entry for selected channel + uint32_t qtop_token : 2; // 25..26 Token 0: In/Out 1: ZLP, 2: Ping/cspit, 3: Channel halt command + uint32_t qtop_ch_num : 4; // 27..30 Channel number +} dwc2_hnptxsts_t; +TU_VERIFY_STATIC(sizeof(dwc2_hnptxsts_t) == 4, "incorrect size"); + typedef struct TU_ATTR_PACKED { uint32_t conn_status : 1; // 0 Port connect status uint32_t conn_detected : 1; // 1 Port connect detected @@ -368,6 +382,13 @@ typedef struct TU_ATTR_PACKED { } dwc2_channel_split_t; TU_VERIFY_STATIC(sizeof(dwc2_channel_split_t) == 4, "incorrect size"); +typedef struct TU_ATTR_PACKED { + uint32_t xfer_size : 19; // 0..18 Transfer size in bytes + uint32_t packet_count : 10; // 19..28 Number of packets + uint32_t pid : 2; // 29..30 Packet ID +} dwc2_channel_tsize_t; +TU_VERIFY_STATIC(sizeof(dwc2_channel_tsize_t) == 4, "incorrect size"); + // Host Channel typedef struct { union { @@ -380,35 +401,55 @@ typedef struct { }; volatile uint32_t hcint; // 508 + 20*ch Host Channel Interrupt volatile uint32_t hcintmsk; // 50C + 20*ch Host Channel Interrupt Mask + union { volatile uint32_t hctsiz; // 510 + 20*ch Host Channel Transfer Size + volatile dwc2_channel_tsize_t hctsiz_bm; + }; volatile uint32_t hcdma; // 514 + 20*ch Host Channel DMA Address uint32_t reserved518; // 518 + 20*ch volatile uint32_t hcdmab; // 51C + 20*ch Host Channel DMA Address } dwc2_channel_t; +//-------------------------------------------------------------------- +// Device Register Bitfield +//-------------------------------------------------------------------- +typedef struct TU_ATTR_PACKED { + uint32_t xfer_size : 19; // 0..18 Transfer size in bytes + uint32_t packet_count : 10; // 19..28 Number of packets + uint32_t mc_pid : 2; // 29..30 IN: Multi Count, OUT: PID +} dwc2_ep_tsize_t; +TU_VERIFY_STATIC(sizeof(dwc2_ep_tsize_t) == 4, "incorrect size"); + // Endpoint IN typedef struct { - volatile uint32_t diepctl; // 900 + 20*ep Device IN Endpoint Control - uint32_t reserved04; // 904 - volatile uint32_t diepint; // 908 + 20*ep Device IN Endpoint Interrupt - uint32_t reserved0c; // 90C - volatile uint32_t dieptsiz; // 910 + 20*ep Device IN Endpoint Transfer Size - volatile uint32_t diepdma; // 914 + 20*ep Device IN Endpoint DMA Address - volatile uint32_t dtxfsts; // 918 + 20*ep Device IN Endpoint Tx FIFO Status - uint32_t reserved1c; // 91C + volatile uint32_t diepctl; // 900 + 20*ep Device IN Endpoint Control + uint32_t reserved04; // 904 + volatile uint32_t diepint; // 908 + 20*ep Device IN Endpoint Interrupt + uint32_t reserved0c; // 90C + union { + volatile uint32_t dieptsiz; // 910 + 20*ep Device IN Endpoint Transfer Size + volatile dwc2_ep_tsize_t dieptsiz_bm; + }; + volatile uint32_t diepdma; // 914 + 20*ep Device IN Endpoint DMA Address + volatile uint32_t dtxfsts; // 918 + 20*ep Device IN Endpoint Tx FIFO Status + uint32_t reserved1c; // 91C } dwc2_epin_t; // Endpoint OUT typedef struct { - volatile uint32_t doepctl; // B00 + 20*ep Device OUT Endpoint Control - uint32_t reserved04; // B04 - volatile uint32_t doepint; // B08 + 20*ep Device OUT Endpoint Interrupt - uint32_t reserved0c; // B0C - volatile uint32_t doeptsiz; // B10 + 20*ep Device OUT Endpoint Transfer Size - volatile uint32_t doepdma; // B14 + 20*ep Device OUT Endpoint DMA Address - uint32_t reserved18[2]; // B18..B1C + volatile uint32_t doepctl; // B00 + 20*ep Device OUT Endpoint Control + uint32_t reserved04; // B04 + volatile uint32_t doepint; // B08 + 20*ep Device OUT Endpoint Interrupt + uint32_t reserved0c; // B0C + union { + volatile uint32_t doeptsiz; // B10 + 20*ep Device OUT Endpoint Transfer Size + volatile dwc2_ep_tsize_t doeptsiz_bm; + }; + volatile uint32_t doepdma; // B14 + 20*ep Device OUT Endpoint DMA Address + uint32_t reserved18[2]; // B18..B1C } dwc2_epout_t; +// Universal Endpoint typedef struct { union { volatile uint32_t diepctl; @@ -424,6 +465,7 @@ typedef struct { union { volatile uint32_t dieptsiz; volatile uint32_t doeptsiz; + volatile dwc2_ep_tsize_t deptsiz_bm; }; union { volatile uint32_t diepdma; @@ -460,7 +502,11 @@ typedef struct { volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size volatile uint32_t gnptxfsiz; // 028 Non-periodic Transmit FIFO Size }; - volatile uint32_t gnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status + union { + volatile uint32_t hnptxsts; // 02c Non-periodic Transmit FIFO/Queue Status + volatile dwc2_hnptxsts_t hnptxsts_bm; + volatile uint32_t gnptxsts; + }; volatile uint32_t gi2cctl; // 030 I2C Address volatile uint32_t gpvndctl; // 034 PHY Vendor Control union { @@ -791,14 +837,12 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GAHBCFG_DMAEN_Pos (5U) #define GAHBCFG_DMAEN_Msk (0x1UL << GAHBCFG_DMAEN_Pos) // 0x00000020 #define GAHBCFG_DMAEN GAHBCFG_DMAEN_Msk // DMA enable -#define GAHBCFG_TXFELVL_Pos (7U) -#define GAHBCFG_TXFELVL_Msk (0x1UL << GAHBCFG_TXFELVL_Pos) // 0x00000080 -#define GAHBCFG_TXFELVL GAHBCFG_TXFELVL_Msk // TxFIFO empty level -#define GAHBCFG_PTXFELVL_Pos (8U) -#define GAHBCFG_PTXFELVL_Msk (0x1UL << GAHBCFG_PTXFELVL_Pos) // 0x00000100 -#define GAHBCFG_PTXFELVL GAHBCFG_PTXFELVL_Msk // Periodic TxFIFO empty level - -#define GSNPSID_ID_MASK TU_GENMASK(31, 16) +#define GAHBCFG_TX_FIFO_EPMTY_LVL_Pos (7U) +#define GAHBCFG_TX_FIFO_EPMTY_LVL_Msk (0x1UL << GAHBCFG_TX_FIFO_EPMTY_LVL_Pos) // 0x00000080 +#define GAHBCFG_TX_FIFO_EPMTY_LVL GAHBCFG_TX_FIFO_EPMTY_LVL_Msk // TxFIFO empty level +#define GAHBCFG_PTX_FIFO_EPMTY_LVL_Pos (8U) +#define GAHBCFG_PTX_FIFO_EPMTY_LVL_Msk (0x1UL << GAHBCFG_PTX_FIFO_EPMTY_LVL_Pos) // 0x00000100 +#define GAHBCFG_PTX_FIFO_EPMTY_LVL GAHBCFG_PTX_FIFO_EPMTY_LVL_Msk // Periodic TxFIFO empty level /******************** Bit definition for GUSBCFG register ********************/ #define GUSBCFG_TOCAL_Pos (0U) @@ -1009,9 +1053,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GINTSTS_RXFLVL_Pos (4U) #define GINTSTS_RXFLVL_Msk (0x1UL << GINTSTS_RXFLVL_Pos) // 0x00000010 #define GINTSTS_RXFLVL GINTSTS_RXFLVL_Msk // RxFIFO nonempty -#define GINTSTS_NPTXFE_Pos (5U) -#define GINTSTS_NPTXFE_Msk (0x1UL << GINTSTS_NPTXFE_Pos) // 0x00000020 -#define GINTSTS_NPTXFE GINTSTS_NPTXFE_Msk // Nonperiodic TxFIFO empty +#define GINTSTS_NPTX_FIFO_EMPTY_Pos (5U) +#define GINTSTS_NPTX_FIFO_EMPTY_Msk (0x1UL << GINTSTS_NPTX_FIFO_EMPTY_Pos) // 0x00000020 +#define GINTSTS_NPTX_FIFO_EMPTY GINTSTS_NPTX_FIFO_EMPTY_Msk // Nonperiodic TxFIFO empty #define GINTSTS_GINAKEFF_Pos (6U) #define GINTSTS_GINAKEFF_Msk (0x1UL << GINTSTS_GINAKEFF_Pos) // 0x00000040 #define GINTSTS_GINAKEFF GINTSTS_GINAKEFF_Msk // Global IN nonperiodic NAK effective @@ -1060,15 +1104,15 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GINTSTS_HCINT_Pos (25U) #define GINTSTS_HCINT_Msk (0x1UL << GINTSTS_HCINT_Pos) // 0x02000000 #define GINTSTS_HCINT GINTSTS_HCINT_Msk // Host channels interrupt -#define GINTSTS_PTXFE_Pos (26U) -#define GINTSTS_PTXFE_Msk (0x1UL << GINTSTS_PTXFE_Pos) // 0x04000000 -#define GINTSTS_PTXFE GINTSTS_PTXFE_Msk // Periodic TxFIFO empty +#define GINTSTS_PTX_FIFO_EMPTY_Pos (26U) +#define GINTSTS_PTX_FIFO_EMPTY_Msk (0x1UL << GINTSTS_PTX_FIFO_EMPTY_Pos) // 0x04000000 +#define GINTSTS_PTX_FIFO_EMPTY GINTSTS_PTX_FIFO_EMPTY_Msk // Periodic TxFIFO empty #define GINTSTS_LPMINT_Pos (27U) #define GINTSTS_LPMINT_Msk (0x1UL << GINTSTS_LPMINT_Pos) // 0x08000000 #define GINTSTS_LPMINT GINTSTS_LPMINT_Msk // LPM interrupt #define GINTSTS_CONIDSTSCHNG_Pos (28U) -#define GINTSTS_CONIDSTSCHNG_Msk (0x1UL << GINTSTS_CONIDSTSCHNG_Pos) // 0x10000000 -#define GINTSTS_CONIDSTSCHNG GINTSTS_CONIDSTSCHNG_Msk // Connector ID status change +#define GINTSTS_CONIDSTSCHNG_Msk (0x1UL << GINTSTS_CONIDSTSCHNG_Pos) // 0x10000000 +#define GINTSTS_CONIDSTSCHNG GINTSTS_CONIDSTSCHNG_Msk // Connector ID status change #define GINTSTS_DISCINT_Pos (29U) #define GINTSTS_DISCINT_Msk (0x1UL << GINTSTS_DISCINT_Pos) // 0x20000000 #define GINTSTS_DISCINT GINTSTS_DISCINT_Msk // Disconnect detected interrupt diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index f37bf717d..f388776c5 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -35,14 +35,15 @@ #include "dwc2_common.h" // DWC2 has limit number of channel, in order to support all endpoints we can store channel char/split to swap later on -#ifndef CFG_TUH_DWC2_CHANNEL_MAX -#define CFG_TUH_DWC2_CHANNEL_MAX (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX + CFG_TUH_HUB) +#ifndef CFG_TUH_DWC2_ENDPOINT_MAX +#define CFG_TUH_DWC2_ENDPOINT_MAX (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX + CFG_TUH_HUB) #endif enum { HPRT_W1C_MASK = HPRT_CONN_DETECT | HPRT_ENABLE | HPRT_ENABLE_CHANGE | HPRT_OVER_CURRENT_CHANGE }; +// Host driver for each opened endpoint typedef struct { union { uint32_t hcchar; @@ -53,11 +54,14 @@ typedef struct { dwc2_channel_split_t hcsplt_bm; }; + uint8_t* buf; + uint16_t total_len; uint8_t next_data_toggle; + bool pending_tx; } hcd_pipe_t; typedef struct { - hcd_pipe_t pipe[CFG_TUH_DWC2_CHANNEL_MAX]; + hcd_pipe_t pipe[CFG_TUH_DWC2_ENDPOINT_MAX]; } dwc2_hcd_t; dwc2_hcd_t _hcd_data; @@ -94,7 +98,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc possible since the free space is located between the RX and TX FIFOs. ----------------- ep_fifo_size - | EPInfo DMA | + | HCDMAn | |--------------|-- gdfifocfg.EPINFOBASE (max is ghwcfg3.dfifo_depth) | Non-Periodic | | TX FIFO | @@ -214,8 +218,12 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dwc2->hprt = HPRT_POWER; // turn on VBUS // Enable required interrupts - dwc2->gintmsk |= GINTMSK_OTGINT | GINTSTS_CONIDSTSCHNG | GINTMSK_PRTIM; // | GINTMSK_WUIM; - dwc2->gahbcfg |= GAHBCFG_GINT; // Enable global interrupt + dwc2->gintmsk |= GINTMSK_OTGINT | GINTSTS_CONIDSTSCHNG | GINTMSK_PRTIM ; // | GINTMSK_WUIM; + + // NPTX can hold at least 2 packet, change interrupt level to half-empty + uint32_t gahbcfg = dwc2->gahbcfg & ~GAHBCFG_TX_FIFO_EPMTY_LVL; + gahbcfg |= GAHBCFG_GINT; // Enable global interrupt + dwc2->gahbcfg = gahbcfg; return true; } @@ -290,7 +298,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const hcd_devtree_get_info(dev_addr, &devtree_info); // find a free pipe - for (uint32_t i = 0; i < CFG_TUH_DWC2_CHANNEL_MAX; i++) { + for (uint32_t i = 0; i < CFG_TUH_DWC2_ENDPOINT_MAX; i++) { hcd_pipe_t* pipe = &_hcd_data.pipe[i]; dwc2_channel_char_t* hcchar_bm = &pipe->hcchar_bm; dwc2_channel_split_t* hcsplt_bm = &pipe->hcsplt_bm; @@ -334,25 +342,40 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t find_free_channel(dwc2_regs_t* dwc2) return TUSB_INDEX_INVALID_8; } -TU_ATTR_ALWAYS_INLINE static inline uint8_t find_opened_pipe(uint8_t dev_addr, uint8_t ep_addr) { - for (uint32_t i = 0; i < CFG_TUH_DWC2_CHANNEL_MAX; i++) { +TU_ATTR_ALWAYS_INLINE static inline uint8_t find_opened_pipe(uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) { + for (uint8_t i = 0; i < (uint8_t) CFG_TUH_DWC2_ENDPOINT_MAX; i++) { const dwc2_channel_char_t* hcchar_bm = &_hcd_data.pipe[i].hcchar_bm; + // find enabled pipe: note EP0 is bidirectional if (hcchar_bm->enable && hcchar_bm->dev_addr == dev_addr && - ep_addr == tu_edpt_addr(hcchar_bm->ep_num, hcchar_bm->ep_dir)) { + hcchar_bm->ep_num == ep_num && (ep_num == 0 || hcchar_bm->ep_dir == ep_dir)) { return i; } } return TUSB_INDEX_INVALID_8; } +void schedule_out_packet(dwc2_regs_t* dwc2, uint8_t pipe_id, uint8_t ch_id) { + // To prevent conflict with other channel, we will enable periodic/non-periodic FIFO empty interrupt accordingly. + // And write packet in the interrupt handler + hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; + dwc2_channel_t* channel = &dwc2->channel[ch_id]; + (void) channel; + const uint8_t ep_type = pipe->hcchar_bm.ep_type; + const bool is_periodic = ep_type == TUSB_XFER_INTERRUPT || ep_type == TUSB_XFER_ISOCHRONOUS; + pipe->pending_tx = true; + dwc2->gintmsk |= (is_periodic ? GINTSTS_PTX_FIFO_EMPTY : GINTSTS_NPTX_FIFO_EMPTY); +} + // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint8_t pipe_id = find_opened_pipe(dev_addr, ep_addr); - TU_ASSERT(pipe_id < CFG_TUH_DWC2_CHANNEL_MAX); // no opened pipe + const uint8_t ep_num = tu_edpt_number(ep_addr); + const uint8_t ep_dir = tu_edpt_dir(ep_addr); + uint8_t pipe_id = find_opened_pipe(dev_addr, ep_num, ep_dir); + TU_ASSERT(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX); // no opened pipe hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; - const dwc2_channel_char_t* hcchar_bm = &pipe->hcchar_bm; + dwc2_channel_char_t* hcchar_bm = &pipe->hcchar_bm; uint8_t ch_id = find_free_channel(dwc2); TU_ASSERT(ch_id < 16); // all channel are in use @@ -362,25 +385,44 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * channel->hcintmsk = HCINT_XFER_COMPLETE | HCINT_CHANNEL_HALTED | HCINT_STALL | HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR; - const uint16_t packet_count = tu_div_ceil(buflen, hcchar_bm->ep_size); + uint16_t packet_count = tu_div_ceil(buflen, hcchar_bm->ep_size); + if (packet_count == 0) { + packet_count = 1; // zero length packet still count as 1 + } channel->hctsiz = (pipe->next_data_toggle << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | buflen; // Control transfer always start with DATA1 for data and status stage. May has issue with ZLP - if (pipe->next_data_toggle == HCTSIZ_PID_DATA0 || tu_edpt_number(ep_addr) == 0) { + if (pipe->next_data_toggle == HCTSIZ_PID_DATA0 || ep_num == 0) { pipe->next_data_toggle = HCTSIZ_PID_DATA1; } else { pipe->next_data_toggle = HCTSIZ_PID_DATA0; } + // TODO support split transaction + channel->hcsplt = pipe->hcsplt; + + hcchar_bm->odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame + hcchar_bm->ep_dir = ep_dir; // control endpoint can switch direction + channel->hcchar = pipe->hcchar & ~HCCHAR_CHENA; // restore hcchar but don't enable yet + if (dma_host_enabled(dwc2)) { channel->hcdma = (uint32_t) buffer; } else { - TU_ASSERT(false); // not yet support - } + if (ep_dir == TUSB_DIR_IN) { + TU_ASSERT(false); // not yet support + } else { + pipe->buf = buffer; + pipe->total_len = buflen; - // TODO support split transaction - channel->hcsplt = pipe->hcsplt; - channel->hcchar = pipe->hcchar; // kick-off transfer + channel->hcchar |= HCCHAR_CHENA; // enable channel before writing to FIFO + + if (ep_dir == TUSB_DIR_OUT && buflen > 0) { + schedule_out_packet(dwc2, pipe_id, ch_id); + } else { + TU_ASSERT(false); // not yet support + } + } + } return true; } @@ -397,8 +439,8 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, const uint8_t setup_packet[8]) { - uint8_t pipe_id = find_opened_pipe(dev_addr, 0); - TU_ASSERT(pipe_id < CFG_TUH_DWC2_CHANNEL_MAX); // no opened pipe + uint8_t pipe_id = find_opened_pipe(dev_addr, 0, TUSB_DIR_OUT); + TU_ASSERT(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX); // no opened pipe hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; pipe->next_data_toggle = HCTSIZ_PID_SETUP; @@ -529,25 +571,57 @@ void handle_channel_irq(uint8_t rhport, bool in_isr) { } } +bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { + bool ff_written = false; + volatile uint32_t* tx_sts = is_periodic ? &dwc2->hptxsts : &dwc2->hnptxsts; + + // find which channel have pending packet + for (uint8_t ch_id = 0; ch_id < 32; ch_id++) { + if (tu_bit_test(dwc2->haintmsk, ch_id)) { + dwc2_channel_t* channel = &dwc2->channel[ch_id]; + const dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; + if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { + uint8_t pipe_id = find_opened_pipe(hcchar_bm.dev_addr, hcchar_bm.ep_num, TUSB_DIR_OUT); + if (pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX) { + hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; + if (pipe->pending_tx) { + const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + for (uint16_t i = 0; i < remain_packets; i++) { + const uint16_t remain_bytes = channel->hctsiz_bm.xfer_size; + const uint16_t packet_bytes = tu_min16(remain_bytes, hcchar_bm.ep_size); + + // check if there is enough space in FIFO + if (packet_bytes > (*tx_sts & HPTXSTS_PTXQSAV)) { + break; + } + + dfifo_write_packet(dwc2, ch_id, pipe->buf, packet_bytes); + pipe->buf += packet_bytes; + + if (channel->hctsiz_bm.xfer_size == 0) { + pipe->pending_tx = false; // all data has been written + } + + ff_written = true; + } + } + } + } + } + } + + return ff_written; +} + /* Interrupt Hierarchy - HCINTn.XferCompl HCINTMSKn.XferComplMsk HPRT ConnDetect PrtEnChng OverCurChng - | | | | | - +---------- AND --------+ +------------ OR -----------+ - | | - HAINT.CHn HAINTMSK.CHn | - | | | - +---------- AND --------+ | - | | - GINTSTS.HCInt GINTMSK.HCInt GINTSTS.PrtInt GINTMSK.PrtInt - | | | | - +---------- AND ---------+ +---------- AND ---------+ - | | - +-------------------- OR ---------------------------+ - | - GAHBCFG.GblIntrMsk - | - IRQn - */ + HCINTn HPRT + | | + HAINT.CHn | + | | + GINTSTS HCInt PrtInt NPTxFEmp PTxFEmpp RXFLVL + + +*/ void hcd_int_handler(uint8_t rhport, bool in_isr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); const uint32_t int_mask = dwc2->gintmsk; @@ -577,6 +651,15 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { handle_channel_irq(rhport, in_isr); } + if (int_status & GINTSTS_NPTX_FIFO_EMPTY) { + // NPTX FIFO empty interrupt, this is read-only and cleared by hardware when FIFO is written + const bool ff_written = handle_txfifo_empty(dwc2, false); + if (!ff_written) { + // no more pending packet, disable interrupt + dwc2->gintmsk &= ~GINTSTS_NPTX_FIFO_EMPTY; + } + } + // RxFIFO non-empty interrupt handling. if (int_status & GINTSTS_RXFLVL) { // RXFLVL bit is read-only -- cgit v1.3.1 From 79c0a249e878c425f3a5f926f444bb5178a748ef Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 25 Oct 2024 22:56:11 +0700 Subject: got In transfer working, able to get 1st device descriptor and set address --- hw/bsp/stm32u5/family.mk | 2 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 30 +++---- src/portable/synopsys/dwc2/dwc2_common.c | 3 - src/portable/synopsys/dwc2/dwc2_type.h | 40 +++++++--- src/portable/synopsys/dwc2/hcd_dwc2.c | 130 +++++++++++++++++++++---------- 5 files changed, 135 insertions(+), 70 deletions(-) (limited to 'src/portable') diff --git a/hw/bsp/stm32u5/family.mk b/hw/bsp/stm32u5/family.mk index 0e3c54c4b..05fe4608a 100644 --- a/hw/bsp/stm32u5/family.mk +++ b/hw/bsp/stm32u5/family.mk @@ -48,7 +48,7 @@ else SRC_C += \ src/portable/synopsys/dwc2/dcd_dwc2.c \ src/portable/synopsys/dwc2/hcd_dwc2.c \ - src/portable/synopsys/dwc2/dwc2_common.c \ + src/portable/synopsys/dwc2/dwc2_common.c endif INC += \ diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index b389b0f74..a04f03b50 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -445,8 +445,11 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Enable required interrupts dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM; - // Enable global interrupt - dwc2->gahbcfg |= GAHBCFG_GINT; + // TX FIFO empty level for interrupt is complete empty + uint32_t gahbcfg = dwc2->gahbcfg; + gahbcfg |= GAHBCFG_TX_FIFO_EPMTY_LVL; + gahbcfg |= GAHBCFG_GINT; // Enable global interrupt + dwc2->gahbcfg = gahbcfg; dcd_connect(rhport); return true; @@ -671,16 +674,15 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { // Process shared receive FIFO, this interrupt is only used in Slave mode static void handle_rxflvl_irq(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - volatile uint32_t const* rx_fifo = dwc2->fifo[0]; + const volatile uint32_t* rx_fifo = dwc2->fifo[0]; // Pop control word off FIFO - uint32_t const grxstsp = dwc2->grxstsp; - uint8_t const pktsts = (grxstsp & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; - uint8_t const epnum = (grxstsp & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; - uint16_t const bcnt = (grxstsp & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; + const dwc2_grxstsp_t grxstsp_bm = dwc2->grxstsp_bm; + const uint8_t epnum = grxstsp_bm.ep_ch_num; + const uint16_t byte_count = grxstsp_bm.byte_count; dwc2_epout_t* epout = &dwc2->epout[epnum]; - switch (pktsts) { + switch (grxstsp_bm.packet_status) { // Global OUT NAK: do nothing case GRXSTS_PKTSTS_GLOBALOUTNAK: break; @@ -705,18 +707,18 @@ static void handle_rxflvl_irq(uint8_t rhport) { // Read packet off RxFIFO if (xfer->ff) { // Ring buffer - tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, bcnt); + tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, byte_count); } else { // Linear buffer - dfifo_read_packet(dwc2, xfer->buffer, bcnt); + dfifo_read_packet(dwc2, xfer->buffer, byte_count); // Increment pointer to xfer data - xfer->buffer += bcnt; + xfer->buffer += byte_count; } - // Truncate transfer length in case of short packet - if (bcnt < xfer->max_size) { - xfer->total_len -= (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; + // short packet, minus remaining bytes (xfer_size) + if (byte_count < xfer->max_size) { + xfer->total_len -= epout->doeptsiz_bm.xfer_size; if (epnum == 0) { xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; ep0_pending[TUSB_DIR_OUT] = 0; diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index 1527932a5..66dc59b11 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -242,9 +242,6 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) { dwc2->gintmsk |= GINTMSK_RXFLVLM; } - // (non-periodic) TX FIFO empty level for interrupt is complete empty - dwc2->gahbcfg |= GAHBCFG_TX_FIFO_EPMTY_LVL; - return true; } diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 36e917d43..9aaa8f0bd 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -145,6 +145,21 @@ enum { HCTSIZ_PID_SETUP = 3, }; +enum { + GRXSTS_PKTSTS_GLOBALOUTNAK = 1, + GRXSTS_PKTSTS_OUTRX = 2, + GRXSTS_PKTSTS_OUTDONE = 3, + GRXSTS_PKTSTS_SETUPDONE = 4, + GRXSTS_PKTSTS_SETUPRX = 6 +}; + +enum { + GRXSTS_PKTSTS_HOST_IN_RECEIVED = 2, + GRXSTS_PKTSTS_HOST_IN_XFER_COMPL = 3, + GRXSTS_PKTSTS_HOST_DATATOGGLE_ERR = 5, + GRXSTS_PKTSTS_HOST_CHANNEL_HALTED = 7 +}; + //-------------------------------------------------------------------- // Common Register Bitfield //-------------------------------------------------------------------- @@ -263,6 +278,17 @@ typedef struct TU_ATTR_PACKED { } dwc2_grstctl_t; TU_VERIFY_STATIC(sizeof(dwc2_grstctl_t) == 4, "incorrect size"); +typedef struct TU_ATTR_PACKED { + uint32_t ep_ch_num : 4; // 0..3 Endpoint/Channel Number + uint32_t byte_count :11; // 4..14 Byte Count + uint32_t dpid : 2; // 15..16 Data PID + uint32_t packet_status : 4; // 17..20 Packet Status + uint32_t frame_number : 4; // 21..24 Frame Number + uint32_t rsv25_31 : 7; // 25..31 Reserved +} dwc2_grxstsp_t; +TU_VERIFY_STATIC(sizeof(dwc2_grxstsp_t) == 4, "incorrect size"); + +// Hardware Configuration typedef struct TU_ATTR_PACKED { uint32_t op_mode : 3; // 0..2 HNP/SRP Host/Device/OTG mode uint32_t arch : 2; // 3..4 Slave/External/Internal DMA @@ -496,7 +522,10 @@ typedef struct { volatile uint32_t gintsts; // 014 Interrupt volatile uint32_t gintmsk; // 018 Interrupt Mask volatile uint32_t grxstsr; // 01c Receive Status Debug Read + union { volatile uint32_t grxstsp; // 020 Receive Status Read/Pop + volatile dwc2_grxstsp_t grxstsp_bm; + }; volatile uint32_t grxfsiz; // 024 Receive FIFO Size union { volatile uint32_t dieptxf0; // 028 EP0 Tx FIFO Size @@ -1236,17 +1265,6 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define GRXSTSP_PKTSTS_Msk (0xFUL << GRXSTSP_PKTSTS_Pos) // 0x001E0000 #define GRXSTSP_PKTSTS GRXSTSP_PKTSTS_Msk // OUT EP interrupt mask bits -#define GRXSTS_PKTSTS_GLOBALOUTNAK 1 -#define GRXSTS_PKTSTS_OUTRX 2 -#define GRXSTS_PKTSTS_HCHIN 2 -#define GRXSTS_PKTSTS_OUTDONE 3 -#define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3 -#define GRXSTS_PKTSTS_SETUPDONE 4 -#define GRXSTS_PKTSTS_DATATOGGLEERR 5 -#define GRXSTS_PKTSTS_SETUPRX 6 -#define GRXSTS_PKTSTS_HCHHALTED 7 - - /******************** Bit definition for DAINTMSK register ********************/ #define DAINTMSK_IEPM_Pos (0U) #define DAINTMSK_IEPM_Msk (0xFFFFUL << DAINTMSK_IEPM_Pos) // 0x0000FFFF diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index f388776c5..7d74d7a33 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -54,7 +54,7 @@ typedef struct { dwc2_channel_split_t hcsplt_bm; }; - uint8_t* buf; + uint8_t* buffer; uint16_t total_len; uint8_t next_data_toggle; bool pending_tx; @@ -218,7 +218,7 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dwc2->hprt = HPRT_POWER; // turn on VBUS // Enable required interrupts - dwc2->gintmsk |= GINTMSK_OTGINT | GINTSTS_CONIDSTSCHNG | GINTMSK_PRTIM ; // | GINTMSK_WUIM; + dwc2->gintmsk |= GINTSTS_OTGINT | GINTSTS_CONIDSTSCHNG | GINTSTS_HPRTINT | GINTSTS_HCINT; // NPTX can hold at least 2 packet, change interrupt level to half-empty uint32_t gahbcfg = dwc2->gahbcfg & ~GAHBCFG_TX_FIFO_EPMTY_LVL; @@ -354,6 +354,11 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t find_opened_pipe(uint8_t dev_addr, u return TUSB_INDEX_INVALID_8; } +TU_ATTR_ALWAYS_INLINE static inline uint8_t find_opened_pipe_by_channel(const dwc2_channel_t* channel) { + const dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; + return find_opened_pipe(hcchar_bm.dev_addr, hcchar_bm.ep_num, hcchar_bm.ep_dir); +} + void schedule_out_packet(dwc2_regs_t* dwc2, uint8_t pipe_id, uint8_t ch_id) { // To prevent conflict with other channel, we will enable periodic/non-periodic FIFO empty interrupt accordingly. // And write packet in the interrupt handler @@ -382,8 +387,12 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * dwc2->haintmsk |= TU_BIT(ch_id); dwc2_channel_t* channel = &dwc2->channel[ch_id]; - channel->hcintmsk = HCINT_XFER_COMPLETE | HCINT_CHANNEL_HALTED | HCINT_STALL | - HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR; + uint32_t hcintmsk = HCINT_XFER_COMPLETE | HCINT_CHANNEL_HALTED | HCINT_STALL | + HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR; + if (ep_dir == TUSB_DIR_IN) { + hcintmsk |= HCINT_NAK; + } + channel->hcintmsk = hcintmsk; uint16_t packet_count = tu_div_ceil(buflen, hcchar_bm->ep_size); if (packet_count == 0) { @@ -405,21 +414,24 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * hcchar_bm->ep_dir = ep_dir; // control endpoint can switch direction channel->hcchar = pipe->hcchar & ~HCCHAR_CHENA; // restore hcchar but don't enable yet + pipe->buffer = buffer; + pipe->total_len = buflen; + if (dma_host_enabled(dwc2)) { channel->hcdma = (uint32_t) buffer; } else { - if (ep_dir == TUSB_DIR_IN) { - TU_ASSERT(false); // not yet support - } else { - pipe->buf = buffer; - pipe->total_len = buflen; + // enable channel for: + // - OUT endpoint: it will enable corresponding FIFO channel + // - IN endpoint: it will write an IN request to the Non-periodic Request Queue, this will have dwc2 trying to send + // IN Token. If we got NAK, we have to re-enable the channel again in the interrupt. Due to the way usbh stack only + // call hcd_edpt_xfer() once, we will need to manage de-allocate/re-allocate IN channel dynamically. + channel->hcchar |= HCCHAR_CHENA; - channel->hcchar |= HCCHAR_CHENA; // enable channel before writing to FIFO + if (ep_dir == TUSB_DIR_IN) { - if (ep_dir == TUSB_DIR_OUT && buflen > 0) { + } else { + if (buflen > 0) { schedule_out_packet(dwc2, pipe_id, ch_id); - } else { - TU_ASSERT(false); // not yet support } } } @@ -460,20 +472,50 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { // HCD Event Handler //-------------------------------------------------------------------- -#if 1 static void handle_rxflvl_irq(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - // volatile uint32_t const* rx_fifo = dwc2->fifo[0]; // Pop control word off FIFO - uint32_t const grxstsp = dwc2->grxstsp; - (void) grxstsp; - // uint8_t const pktsts = (grxstsp & GRXSTSP_PKTSTS_Msk) >> GRXSTSP_PKTSTS_Pos; - // uint8_t const epnum = (grxstsp & GRXSTSP_EPNUM_Msk) >> GRXSTSP_EPNUM_Pos; - // uint16_t const bcnt = (grxstsp & GRXSTSP_BCNT_Msk) >> GRXSTSP_BCNT_Pos; - // dwc2_epout_t* epout = &dwc2->epout[epnum]; + const dwc2_grxstsp_t grxstsp_bm = dwc2->grxstsp_bm; + const uint8_t ch_id = grxstsp_bm.ep_ch_num; + dwc2_channel_t* channel = &dwc2->channel[ch_id]; + + switch (grxstsp_bm.packet_status) { + case GRXSTS_PKTSTS_HOST_IN_RECEIVED: { + // In packet received + const uint16_t byte_count = grxstsp_bm.byte_count; + const uint8_t pipe_id = find_opened_pipe_by_channel(channel); + TU_VERIFY(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX, ); + hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; + + dfifo_read_packet(dwc2, pipe->buffer, byte_count); + pipe->buffer += byte_count; + + // short packet, minus remaining bytes (xfer_size) + if (byte_count < channel->hctsiz_bm.xfer_size) { + pipe->total_len -= channel->hctsiz_bm.xfer_size; + } + + break; + } + + case GRXSTS_PKTSTS_HOST_IN_XFER_COMPL: + // In transfer complete: After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed + // interrupt --> handle_channel_irq() + break; + + case GRXSTS_PKTSTS_HOST_DATATOGGLE_ERR: + TU_ASSERT(0, ); // maybe try to change DToggle + break; + + case GRXSTS_PKTSTS_HOST_CHANNEL_HALTED: + // triggered when channel.hcchar_bm.disable is set + // TODO handle later + break; + + default: break; // ignore other status + } } -#endif /* Handle Host Port interrupt, possible source are: - Connection Detection @@ -548,25 +590,31 @@ void handle_channel_irq(uint8_t rhport, bool in_isr) { uint32_t hcint = channel->hcint; hcint &= channel->hcintmsk; - xfer_result_t result = XFER_RESULT_FAILED; - if (hcint & HCINT_XFER_COMPLETE) { - result = XFER_RESULT_SUCCESS; - } - if (hcint & HCINT_STALL) { - result = XFER_RESULT_STALLED; - } - if (hcint & (HCINT_CHANNEL_HALTED | HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR | - HCINT_BUFFER_NAK | HCINT_XCS_XACT_ERR | HCINT_DESC_ROLLOVER)) { - result = XFER_RESULT_FAILED; - } + if (hcint & HCINT_NAK) { + // NAK received, re-enable channel. Check if request queue is available + channel->hcchar |= HCCHAR_CHENA; + } else { + // transfer result interrupt + xfer_result_t result = XFER_RESULT_FAILED; + if (hcint & HCINT_XFER_COMPLETE) { + result = XFER_RESULT_SUCCESS; + } + if (hcint & HCINT_STALL) { + result = XFER_RESULT_STALLED; + } + if (hcint & (HCINT_CHANNEL_HALTED | HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR | + HCINT_BUFFER_NAK | HCINT_XCS_XACT_ERR | HCINT_DESC_ROLLOVER)) { + result = XFER_RESULT_FAILED; + } - const uint8_t ep_addr = tu_edpt_addr(channel->hcchar_bm.ep_num, channel->hcchar_bm.ep_dir); - hcd_event_xfer_complete(channel->hcchar_bm.dev_addr, ep_addr, 0, result, in_isr); + const uint8_t ep_addr = tu_edpt_addr(channel->hcchar_bm.ep_num, channel->hcchar_bm.ep_dir); + hcd_event_xfer_complete(channel->hcchar_bm.dev_addr, ep_addr, 0, result, in_isr); - channel->hcint = hcint; // clear all interrupt flags + // de-allocate channel by clearing haintmsk + dwc2->haintmsk &= ~TU_BIT(ch_id); + } - // de-allocate channel by clearing haintmsk - dwc2->haintmsk &= ~TU_BIT(ch_id); + channel->hcint = hcint; // clear all interrupt flags } } } @@ -581,7 +629,7 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; const dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { - uint8_t pipe_id = find_opened_pipe(hcchar_bm.dev_addr, hcchar_bm.ep_num, TUSB_DIR_OUT); + uint8_t pipe_id = find_opened_pipe_by_channel(channel); if (pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX) { hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; if (pipe->pending_tx) { @@ -595,8 +643,8 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { break; } - dfifo_write_packet(dwc2, ch_id, pipe->buf, packet_bytes); - pipe->buf += packet_bytes; + dfifo_write_packet(dwc2, ch_id, pipe->buffer, packet_bytes); + pipe->buffer += packet_bytes; if (channel->hctsiz_bm.xfer_size == 0) { pipe->pending_tx = false; // all data has been written -- cgit v1.3.1 From dd99da9dcea3bd25fba44b3946f01476fc58a243 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 28 Oct 2024 17:45:44 +0700 Subject: implement hcd_edpt_abort_xfer, hcd_device_close, check request queue available before making usb attempt. Though there is no handling when queue is full. device_info example work well --- src/portable/synopsys/dwc2/dcd_dwc2.c | 20 +-- src/portable/synopsys/dwc2/dwc2_info.md | 4 +- src/portable/synopsys/dwc2/dwc2_info.py | 13 +- src/portable/synopsys/dwc2/dwc2_type.h | 38 ++++- src/portable/synopsys/dwc2/hcd_dwc2.c | 277 +++++++++++++++++++++----------- 5 files changed, 231 insertions(+), 121 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index a04f03b50..bcfdb546b 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -882,21 +882,11 @@ static void handle_epin_irq(uint8_t rhport) { /* Interrupt Hierarchy - DxEPINTn.XferCompl DxEPMSK.XferComplMsk - | | - +---------- AND --------+ - | - DAINT.xEPnInt DAINTMSK.xEPnMsk - | | - +---------- AND --------+ - | - GINTSTS.xEPInt GINTMSK.xEPIntMsk - | | - +---------- AND --------+ - | - GAHBCFG.GblIntrMsk - | - IRQn + DxEPINTn + | + DAINT.xEPn + | + GINTSTS: xEPInt Note: when OTG_MULTI_PROC_INTRPT = 1, Device Each endpoint interrupt deachint/deachmsk/diepeachmsk/doepeachmsk are combined to generate dedicated interrupt line for each endpoint. diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index 92293a072..78c2c50f8 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -16,8 +16,8 @@ | - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | | - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | | - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nptx_q_depth | 2 | 2 | 1 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - ptx_q_depth | 2 | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - nptx_q_depth | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | 8 | +| - ptx_q_depth | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | 8 | | - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | | - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index fe08ecce9..5884cd455 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -133,7 +133,18 @@ GHWCFG2_field = { 1: "Dedicated", 2: "Shared UTMI+", 3: "Shared ULPI" - } + }, + 'nptx_q_depth': { + 0: "2", + 1: "4", + 2: "8", + }, + 'ptx_q_depth': { + 0: "2", + 1: "4", + 2: "8", + 3: "16" + }, } # mapping for specific fields in GHWCFG4 diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 9aaa8f0bd..0d62c404c 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -160,6 +160,14 @@ enum { GRXSTS_PKTSTS_HOST_CHANNEL_HALTED = 7 }; +// Same as TUSB_XFER_* +enum { + HCCHAR_EPTYPE_CONTROL = 0, + HCCHAR_EPTYPE_ISOCHRONOUS = 1, + HCCHAR_EPTYPE_BULK = 2, + HCCHAR_EPTYPE_INTERRUPT = 3 +}; + //-------------------------------------------------------------------- // Common Register Bitfield //-------------------------------------------------------------------- @@ -355,15 +363,26 @@ TU_VERIFY_STATIC(sizeof(dwc2_ghwcfg4_t) == 4, "incorrect size"); //-------------------------------------------------------------------- typedef struct TU_ATTR_PACKED { - uint32_t fifo_available : 16; // 0..15 Number of words available in the Tx FIFO - uint32_t queue_available : 8; // 16..23 Number of spaces available in the NPT transmit request queue for both IN and OUT + uint32_t fifo_available : 16; // 0..15 Number of words available in the Tx FIFO + uint32_t req_queue_available : 8; // 16..23 Number of spaces available in the NPT transmit request queue for both IN and OU // 24..31 is top entry in the request queue that is currently being processed by the MAC - uint32_t qtop_terminate : 1; // 24 Last entry for selected channel - uint32_t qtop_token : 2; // 25..26 Token 0: In/Out 1: ZLP, 2: Ping/cspit, 3: Channel halt command - uint32_t qtop_ch_num : 4; // 27..30 Channel number + uint32_t qtop_terminate : 1; // 24 Last entry for selected channel + uint32_t qtop_type : 2; // 25..26 Token (0) In/Out (1) ZLP, (2) Ping/cspit, (3) Channel halt command + uint32_t qtop_ch_num : 4; // 27..30 Channel number } dwc2_hnptxsts_t; TU_VERIFY_STATIC(sizeof(dwc2_hnptxsts_t) == 4, "incorrect size"); +typedef struct TU_ATTR_PACKED { + uint32_t fifo_available : 16; // 0..15 Number of words available in the Tx FIFO + uint32_t req_queue_available : 7; // 16..22 Number of spaces available in the PTX transmit request queue + uint32_t qtop_terminate : 1; // 23 Last entry for selected channel + uint32_t qtop_last_period : 1; // 24 Last entry for selected channel is a periodic entry + uint32_t qtop_type : 2; // 25..26 Token (0) In/Out (1) ZLP, (2) Ping/cspit, (3) Channel halt command + uint32_t qtop_ch_num : 4; // 27..30 Channel number + uint32_t qtop_odd_frame : 1; // 31 Send in odd frame +} dwc2_hptxsts_t; +TU_VERIFY_STATIC(sizeof(dwc2_hptxsts_t) == 4, "incorrect size"); + typedef struct TU_ATTR_PACKED { uint32_t conn_status : 1; // 0 Port connect status uint32_t conn_detected : 1; // 1 Port connect detected @@ -571,7 +590,10 @@ typedef struct { volatile uint32_t hfir; // 404 Host Frame Interval volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining uint32_t reserved40c; // 40C + union { volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status + volatile dwc2_hptxsts_t hptxsts_bm; + }; volatile uint32_t haint; // 414 Host All Channels Interrupt volatile uint32_t haintmsk; // 418 Host All Channels Interrupt Mask volatile uint32_t hflbaddr; // 41C Host Frame List Base Address @@ -1854,9 +1876,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define HCINT_DATATOGGLE_ERR_Pos (10U) #define HCINT_DATATOGGLE_ERR_Msk (0x1UL << HCINT_DATATOGGLE_ERR_Pos) // 0x00000400 #define HCINT_DATATOGGLE_ERR HCINT_DATATOGGLE_ERR_Msk // Data toggle error -#define HCINT_BUFFER_NAK_Pos (11U) -#define HCINT_BUFFER_NAK_Msk (0x1UL << HCINT_BUFFER_NAK_Pos) // 0x00000800 -#define HCINT_BUFFER_NAK HCINT_BUFFER_NAK_Msk // Buffer not available interrupt +#define HCINT_BUFFER_NA_Pos (11U) +#define HCINT_BUFFER_NA_Msk (0x1UL << HCINT_BUFFER_NA_Pos) // 0x00000800 +#define HCINT_BUFFER_NA HCINT_BUFFER_NA_Msk // Buffer not available interrupt #define HCINT_XCS_XACT_ERR_Pos (12U) #define HCINT_XCS_XACT_ERR_Msk (0x1UL << HCINT_XCS_XACT_ERR_Pos) // 0x00001000 #define HCINT_XCS_XACT_ERR HCINT_XCS_XACT_ERR_Msk // Excessive transaction error diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 7d74d7a33..464ade9bf 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -34,16 +34,20 @@ #include "host/hcd.h" #include "dwc2_common.h" -// DWC2 has limit number of channel, in order to support all endpoints we can store channel char/split to swap later on +// Max number of endpoints application can open #ifndef CFG_TUH_DWC2_ENDPOINT_MAX -#define CFG_TUH_DWC2_ENDPOINT_MAX (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX + CFG_TUH_HUB) +#define CFG_TUH_DWC2_ENDPOINT_MAX 16 #endif +TU_VERIFY_STATIC(CFG_TUH_DWC2_ENDPOINT_MAX <= 255, "currently only use 8-bit for index"); + enum { HPRT_W1C_MASK = HPRT_CONN_DETECT | HPRT_ENABLE | HPRT_ENABLE_CHANGE | HPRT_OVER_CURRENT_CHANGE }; -// Host driver for each opened endpoint +// Host driver struct for each opened endpoint +// When making an usb transfer, we will find an inactive channel and use it by enabled haintmsk. When the transfer is +// complete, haintmsk will be cleared, and channel is deactivated/deallocated. typedef struct { union { uint32_t hcchar; @@ -57,14 +61,14 @@ typedef struct { uint8_t* buffer; uint16_t total_len; uint8_t next_data_toggle; - bool pending_tx; + bool pending_data; } hcd_pipe_t; typedef struct { hcd_pipe_t pipe[CFG_TUH_DWC2_ENDPOINT_MAX]; -} dwc2_hcd_t; +} hcd_data_t; -dwc2_hcd_t _hcd_data; +hcd_data_t _hcd_data; //-------------------------------------------------------------------- // @@ -75,7 +79,10 @@ TU_ATTR_ALWAYS_INLINE static inline tusb_speed_t convert_hprt_speed(uint32_t hpr case HPRT_SPEED_HIGH: speed = TUSB_SPEED_HIGH; break; case HPRT_SPEED_FULL: speed = TUSB_SPEED_FULL; break; case HPRT_SPEED_LOW : speed = TUSB_SPEED_LOW ; break; - default: TU_BREAKPOINT(); break; + default: + speed = TUSB_SPEED_INVALID; + TU_BREAKPOINT(); + break; } return speed; } @@ -86,6 +93,71 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc return CFG_TUH_DWC2_DMA && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; } +// Check if channel is periodic (interrupt/isochronous) +TU_ATTR_ALWAYS_INLINE static inline bool channel_is_periodic(dwc2_channel_char_t hcchar_bm) { + return hcchar_bm.ep_type == HCCHAR_EPTYPE_INTERRUPT || hcchar_bm.ep_type == HCCHAR_EPTYPE_ISOCHRONOUS; +} + +TU_ATTR_ALWAYS_INLINE static inline uint8_t request_queue_avail(const dwc2_regs_t* dwc2, bool is_period) { + if (is_period) { + return dwc2->hptxsts_bm.req_queue_available; + } else { + return dwc2->hnptxsts_bm.req_queue_available; + } +} + +// Find a free channel for new transfer +TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_free(dwc2_regs_t* dwc2) { + const uint8_t max_channel = tu_min8(dwc2->ghwcfg2_bm.num_host_ch, 16); + for (uint8_t ch_id=0; ch_idhaintmsk, ch_id)) { + return ch_id; + } + } + return TUSB_INDEX_INVALID_8; +} + +// Find currently enabled/active channel associated with a pipe +TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_enabled_by_pipe(dwc2_regs_t* dwc2, const hcd_pipe_t* pipe) { + const uint8_t max_channel = tu_min8(dwc2->ghwcfg2_bm.num_host_ch, 16); + for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { + if (tu_bit_test(dwc2->haintmsk, ch_id)) { + const dwc2_channel_char_t hcchar_bm = dwc2->channel[ch_id].hcchar_bm; + if (hcchar_bm.dev_addr == pipe->hcchar_bm.dev_addr && + hcchar_bm.ep_num == pipe->hcchar_bm.ep_num && + (hcchar_bm.ep_num == 0 || hcchar_bm.ep_dir == pipe->hcchar_bm.ep_dir)) { + return ch_id; + } + } + } + + return TUSB_INDEX_INVALID_8; +} + +// Find a pipe that is opened previously with hcd_edpt_open() +TU_ATTR_ALWAYS_INLINE static inline uint8_t pipe_find_opened(uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) { + for (uint8_t i = 0; i < (uint8_t)CFG_TUH_DWC2_ENDPOINT_MAX; i++) { + const dwc2_channel_char_t* hcchar_bm = &_hcd_data.pipe[i].hcchar_bm; + // find enabled pipe: note EP0 is bidirectional + if (hcchar_bm->enable && hcchar_bm->dev_addr == dev_addr && + hcchar_bm->ep_num == ep_num && (ep_num == 0 || hcchar_bm->ep_dir == ep_dir)) { + return i; + } + } + return TUSB_INDEX_INVALID_8; +} + +// Find a pipe that is opened previously with hcd_edpt_open() and associated with a channel +TU_ATTR_ALWAYS_INLINE static inline uint8_t pipe_find_opened_by_channel(const dwc2_channel_t* channel) { + const dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; + return pipe_find_opened(hcchar_bm.dev_addr, hcchar_bm.ep_num, hcchar_bm.ep_dir); +} + +//-------------------------------------------------------------------- +// +//-------------------------------------------------------------------- + /* USB Data FIFO Layout The FIFO is split up into @@ -169,7 +241,7 @@ bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { (void) cfg_id; (void) cfg_param; - return false; + return true; } // Initialize controller to host mode @@ -281,7 +353,12 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport) { // HCD closes all opened endpoints belong to this device void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { (void) rhport; - (void) dev_addr; + for (uint8_t i = 0; i < (uint8_t) CFG_TUH_DWC2_ENDPOINT_MAX; i++) { + hcd_pipe_t* pipe = &_hcd_data.pipe[i]; + if (pipe->hcchar_bm.enable && pipe->hcchar_bm.dev_addr == dev_addr) { + tu_memclr(pipe, sizeof(hcd_pipe_t)); + } + } } //--------------------------------------------------------------------+ @@ -308,7 +385,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const hcchar_bm->ep_num = tu_edpt_number(desc_ep->bEndpointAddress); hcchar_bm->ep_dir = tu_edpt_dir(desc_ep->bEndpointAddress); hcchar_bm->low_speed_dev = (devtree_info.speed == TUSB_SPEED_LOW) ? 1 : 0; - hcchar_bm->ep_type = desc_ep->bmAttributes.xfer; + hcchar_bm->ep_type = desc_ep->bmAttributes.xfer; // ep_type matches TUSB_XFER_* hcchar_bm->err_multi_count = 0; hcchar_bm->dev_addr = dev_addr; hcchar_bm->odd_frame = 0; @@ -331,58 +408,18 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const return false; } -TU_ATTR_ALWAYS_INLINE static inline uint8_t find_free_channel(dwc2_regs_t* dwc2) { - const uint8_t max_channel = tu_min8(dwc2->ghwcfg2_bm.num_host_ch, 16); - for (uint8_t i=0; ihaintmsk, i)) { - return i; - } - } - return TUSB_INDEX_INVALID_8; -} - -TU_ATTR_ALWAYS_INLINE static inline uint8_t find_opened_pipe(uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) { - for (uint8_t i = 0; i < (uint8_t) CFG_TUH_DWC2_ENDPOINT_MAX; i++) { - const dwc2_channel_char_t* hcchar_bm = &_hcd_data.pipe[i].hcchar_bm; - // find enabled pipe: note EP0 is bidirectional - if (hcchar_bm->enable && hcchar_bm->dev_addr == dev_addr && - hcchar_bm->ep_num == ep_num && (ep_num == 0 || hcchar_bm->ep_dir == ep_dir)) { - return i; - } - } - return TUSB_INDEX_INVALID_8; -} - -TU_ATTR_ALWAYS_INLINE static inline uint8_t find_opened_pipe_by_channel(const dwc2_channel_t* channel) { - const dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; - return find_opened_pipe(hcchar_bm.dev_addr, hcchar_bm.ep_num, hcchar_bm.ep_dir); -} - -void schedule_out_packet(dwc2_regs_t* dwc2, uint8_t pipe_id, uint8_t ch_id) { - // To prevent conflict with other channel, we will enable periodic/non-periodic FIFO empty interrupt accordingly. - // And write packet in the interrupt handler - hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; - dwc2_channel_t* channel = &dwc2->channel[ch_id]; - (void) channel; - const uint8_t ep_type = pipe->hcchar_bm.ep_type; - const bool is_periodic = ep_type == TUSB_XFER_INTERRUPT || ep_type == TUSB_XFER_ISOCHRONOUS; - pipe->pending_tx = true; - dwc2->gintmsk |= (is_periodic ? GINTSTS_PTX_FIFO_EMPTY : GINTSTS_NPTX_FIFO_EMPTY); -} - // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); const uint8_t ep_num = tu_edpt_number(ep_addr); const uint8_t ep_dir = tu_edpt_dir(ep_addr); - uint8_t pipe_id = find_opened_pipe(dev_addr, ep_num, ep_dir); + uint8_t pipe_id = pipe_find_opened(dev_addr, ep_num, ep_dir); TU_ASSERT(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX); // no opened pipe hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; dwc2_channel_char_t* hcchar_bm = &pipe->hcchar_bm; - uint8_t ch_id = find_free_channel(dwc2); + uint8_t ch_id = channel_find_free(dwc2); TU_ASSERT(ch_id < 16); // all channel are in use dwc2->haintmsk |= TU_BIT(ch_id); @@ -420,18 +457,24 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * if (dma_host_enabled(dwc2)) { channel->hcdma = (uint32_t) buffer; } else { - // enable channel for: + bool const is_period = channel_is_periodic(*hcchar_bm); + + // enable channel for slave mode: // - OUT endpoint: it will enable corresponding FIFO channel // - IN endpoint: it will write an IN request to the Non-periodic Request Queue, this will have dwc2 trying to send // IN Token. If we got NAK, we have to re-enable the channel again in the interrupt. Due to the way usbh stack only // call hcd_edpt_xfer() once, we will need to manage de-allocate/re-allocate IN channel dynamically. - channel->hcchar |= HCCHAR_CHENA; - if (ep_dir == TUSB_DIR_IN) { - + pipe->pending_data = true; + TU_ASSERT(request_queue_avail(dwc2, is_period)); + channel->hcchar |= HCCHAR_CHENA; } else { + channel->hcchar |= HCCHAR_CHENA; if (buflen > 0) { - schedule_out_packet(dwc2, pipe_id, ch_id); + // To prevent conflict with other channel, we will enable periodic/non-periodic FIFO empty interrupt accordingly. + // And write packet in the interrupt handler + pipe->pending_data = true; + dwc2->gintmsk |= (is_period ? GINTSTS_PTX_FIFO_EMPTY : GINTSTS_NPTX_FIFO_EMPTY); } } } @@ -442,16 +485,34 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * // Abort a queued transfer. Note: it can only abort transfer that has not been started // Return true if a queued transfer is aborted, false if there is no transfer to abort bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { - (void) rhport; - (void) dev_addr; - (void) ep_addr; + dwc2_regs_t* dwc2 = DWC2_REG(rhport); - return false; + const uint8_t pipe_id = pipe_find_opened(dev_addr, tu_edpt_number(ep_addr), tu_edpt_dir(ep_addr)); + TU_VERIFY(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX); + hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; + + hcd_int_disable(rhport); + + // Find enabled channeled and disable it, channel will be de-allocated in the interrupt handler + const uint8_t ch_id = channel_find_enabled_by_pipe(dwc2, pipe); + if (ch_id < 16) { + dwc2_channel_t* channel = &dwc2->channel[ch_id]; + // disable also require request queue + if (request_queue_avail(dwc2, channel_is_periodic(pipe->hcchar_bm))) { + channel->hcchar |= HCCHAR_CHDIS; + } else { + TU_BREAKPOINT(); + } + } + + hcd_int_enable(rhport); + + return true; } // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, const uint8_t setup_packet[8]) { - uint8_t pipe_id = find_opened_pipe(dev_addr, 0, TUSB_DIR_OUT); + uint8_t pipe_id = pipe_find_opened(dev_addr, 0, TUSB_DIR_OUT); TU_ASSERT(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX); // no opened pipe hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; pipe->next_data_toggle = HCTSIZ_PID_SETUP; @@ -484,7 +545,7 @@ static void handle_rxflvl_irq(uint8_t rhport) { case GRXSTS_PKTSTS_HOST_IN_RECEIVED: { // In packet received const uint16_t byte_count = grxstsp_bm.byte_count; - const uint8_t pipe_id = find_opened_pipe_by_channel(channel); + const uint8_t pipe_id = pipe_find_opened_by_channel(channel); TU_VERIFY(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX, ); hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; @@ -590,28 +651,53 @@ void handle_channel_irq(uint8_t rhport, bool in_isr) { uint32_t hcint = channel->hcint; hcint &= channel->hcintmsk; + dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; + + xfer_result_t result = XFER_RESULT_INVALID; // invalid means transfer is not complete + + if (hcint & HCINT_XFER_COMPLETE) { + result = XFER_RESULT_SUCCESS; + } + if (hcint & HCINT_STALL) { + result = XFER_RESULT_STALLED; + } + // DMA related error: HCINT_BUFFER_NA | HCINT_DESC_ROLLOVER + // if (hcint & (HCINT_BUFFER_NA | HCINT_DESC_ROLLOVER)) { + // result = XFER_RESULT_FAILED; + // } + const uint32_t xact_err = hcint & (HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | + HCINT_DATATOGGLE_ERR | HCINT_XCS_XACT_ERR); + if (xact_err) { + result = XFER_RESULT_FAILED; + } + + if (!xact_err && (hcint & HCINT_CHANNEL_HALTED)) { + // Channel halted without error, this is a response to channel disable + result = XFER_RESULT_INVALID; + } + if (hcint & HCINT_NAK) { - // NAK received, re-enable channel. Check if request queue is available + // NAK received, re-enable channel if request queue is available + result = XFER_RESULT_INVALID; + TU_ASSERT(request_queue_avail(dwc2, channel_is_periodic(hcchar_bm)), ); channel->hcchar |= HCCHAR_CHENA; - } else { - // transfer result interrupt - xfer_result_t result = XFER_RESULT_FAILED; - if (hcint & HCINT_XFER_COMPLETE) { - result = XFER_RESULT_SUCCESS; - } - if (hcint & HCINT_STALL) { - result = XFER_RESULT_STALLED; + } + + // Transfer is complete (success, stalled, failed) or channel is disabled + if (result != XFER_RESULT_INVALID || (hcint & HCINT_CHANNEL_HALTED)) { + uint8_t pipe_id = pipe_find_opened_by_channel(channel); + if (pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX) { + hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; + pipe->pending_data = false; } - if (hcint & (HCINT_CHANNEL_HALTED | HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR | - HCINT_BUFFER_NAK | HCINT_XCS_XACT_ERR | HCINT_DESC_ROLLOVER)) { - result = XFER_RESULT_FAILED; - } + const uint8_t ep_addr = tu_edpt_addr(hcchar_bm.ep_num, hcchar_bm.ep_dir); - const uint8_t ep_addr = tu_edpt_addr(channel->hcchar_bm.ep_num, channel->hcchar_bm.ep_dir); - hcd_event_xfer_complete(channel->hcchar_bm.dev_addr, ep_addr, 0, result, in_isr); + dwc2->haintmsk &= ~TU_BIT(ch_id); // de-allocate channel - // de-allocate channel by clearing haintmsk - dwc2->haintmsk &= ~TU_BIT(ch_id); + // notify usbh if transfer is complete (skip if channel is disabled) + if (result != XFER_RESULT_INVALID) { + hcd_event_xfer_complete(hcchar_bm.dev_addr, ep_addr, 0, result, in_isr); + } } channel->hcint = hcint; // clear all interrupt flags @@ -620,26 +706,28 @@ void handle_channel_irq(uint8_t rhport, bool in_isr) { } bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { - bool ff_written = false; - volatile uint32_t* tx_sts = is_periodic ? &dwc2->hptxsts : &dwc2->hnptxsts; + // Use period txsts for both p/np to get request queue space available (1-bit difference, it is small enough) + volatile dwc2_hptxsts_t* txsts_bm = (volatile dwc2_hptxsts_t*) (is_periodic ? &dwc2->hptxsts : &dwc2->hnptxsts); // find which channel have pending packet + bool ff_written = false; for (uint8_t ch_id = 0; ch_id < 32; ch_id++) { if (tu_bit_test(dwc2->haintmsk, ch_id)) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; const dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { - uint8_t pipe_id = find_opened_pipe_by_channel(channel); + uint8_t pipe_id = pipe_find_opened_by_channel(channel); if (pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX) { hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; - if (pipe->pending_tx) { + if (pipe->pending_data) { const uint16_t remain_packets = channel->hctsiz_bm.packet_count; for (uint16_t i = 0; i < remain_packets; i++) { const uint16_t remain_bytes = channel->hctsiz_bm.xfer_size; const uint16_t packet_bytes = tu_min16(remain_bytes, hcchar_bm.ep_size); - // check if there is enough space in FIFO - if (packet_bytes > (*tx_sts & HPTXSTS_PTXQSAV)) { + // check if there is enough space in FIFO and request queue. + // the last dword written to FIFO will trigger dwc2 controller to write to RequestQueue + if ((packet_bytes > txsts_bm->fifo_available) && (txsts_bm->req_queue_available > 0)) { break; } @@ -647,7 +735,7 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { pipe->buffer += packet_bytes; if (channel->hctsiz_bm.xfer_size == 0) { - pipe->pending_tx = false; // all data has been written + pipe->pending_data = false; // all data has been written } ff_written = true; @@ -662,11 +750,11 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { } /* Interrupt Hierarchy - HCINTn HPRT - | | - HAINT.CHn | - | | - GINTSTS HCInt PrtInt NPTxFEmp PTxFEmpp RXFLVL + HCINTn HPRT + | | + HAINT.CHn | + | | + GINTSTS : HCInt PrtInt NPTxFEmp PTxFEmpp RXFLVL */ @@ -675,7 +763,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { const uint32_t int_mask = dwc2->gintmsk; const uint32_t int_status = dwc2->gintsts & int_mask; - TU_LOG1_HEX(int_status); + // TU_LOG1_HEX(int_status); if (int_status & GINTSTS_CONIDSTSCHNG) { // Connector ID status change @@ -689,13 +777,12 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { if (int_status & GINTSTS_HPRTINT) { // Host port interrupt: source is cleared in HPRT register - TU_LOG1_HEX(dwc2->hprt); + // TU_LOG1_HEX(dwc2->hprt); handle_hprt_irq(rhport, in_isr); } if (int_status & GINTSTS_HCINT) { // Host Channel interrupt: source is cleared in HCINT register - TU_LOG1_HEX(dwc2->hprt); handle_channel_irq(rhport, in_isr); } -- cgit v1.3.1 From f953b6bf9253814ea45a76739101d478ac3f9ad1 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 28 Oct 2024 18:40:21 +0700 Subject: minor rename --- examples/host/msc_file_explorer/only.txt | 1 + hw/bsp/stm32l4/family.cmake | 2 ++ src/portable/synopsys/dwc2/dwc2_type.h | 4 +-- src/portable/synopsys/dwc2/hcd_dwc2.c | 42 ++++++++++++++++---------------- 4 files changed, 26 insertions(+), 23 deletions(-) (limited to 'src/portable') diff --git a/examples/host/msc_file_explorer/only.txt b/examples/host/msc_file_explorer/only.txt index fee10f9e2..9b3d6994e 100644 --- a/examples/host/msc_file_explorer/only.txt +++ b/examples/host/msc_file_explorer/only.txt @@ -12,3 +12,4 @@ mcu:MSP432E4 mcu:RX65X mcu:RAXXX mcu:MAX3421 +mcu:STM32F7 diff --git a/hw/bsp/stm32l4/family.cmake b/hw/bsp/stm32l4/family.cmake index b6eae7c7f..77876cb8b 100644 --- a/hw/bsp/stm32l4/family.cmake +++ b/hw/bsp/stm32l4/family.cmake @@ -104,6 +104,8 @@ function(family_configure_example TARGET RTOS) family_add_tinyusb(${TARGET} OPT_MCU_${FAMILY_MCUS} ${RTOS}) target_sources(${TARGET}-tinyusb PUBLIC ${TOP}/src/portable/synopsys/dwc2/dcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/hcd_dwc2.c + ${TOP}/src/portable/synopsys/dwc2/dwc2_common.c ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c ) target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 0d62c404c..7296475cf 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -154,8 +154,8 @@ enum { }; enum { - GRXSTS_PKTSTS_HOST_IN_RECEIVED = 2, - GRXSTS_PKTSTS_HOST_IN_XFER_COMPL = 3, + GRXSTS_PKTSTS_RX_DATA = 2, + GRXSTS_PKTSTS_RX_COMPLETE = 3, GRXSTS_PKTSTS_HOST_DATATOGGLE_ERR = 5, GRXSTS_PKTSTS_HOST_CHANNEL_HALTED = 7 }; diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 464ade9bf..027a839bb 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -59,9 +59,9 @@ typedef struct { }; uint8_t* buffer; - uint16_t total_len; + uint16_t total_bytes; uint8_t next_data_toggle; - bool pending_data; + volatile bool pending_data; } hcd_pipe_t; typedef struct { @@ -70,6 +70,8 @@ typedef struct { hcd_data_t _hcd_data; +#define DWC2_CHANNEL_MAX(_dwc2) tu_min8((_dwc2)->ghwcfg2_bm.num_host_ch + 1, 16) + //-------------------------------------------------------------------- // //-------------------------------------------------------------------- @@ -108,8 +110,8 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t request_queue_avail(const dwc2_regs_ // Find a free channel for new transfer TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_free(dwc2_regs_t* dwc2) { - const uint8_t max_channel = tu_min8(dwc2->ghwcfg2_bm.num_host_ch, 16); - for (uint8_t ch_id=0; ch_idhaintmsk, ch_id)) { return ch_id; @@ -120,7 +122,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_free(dwc2_regs_t* dwc2) // Find currently enabled/active channel associated with a pipe TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_enabled_by_pipe(dwc2_regs_t* dwc2, const hcd_pipe_t* pipe) { - const uint8_t max_channel = tu_min8(dwc2->ghwcfg2_bm.num_host_ch, 16); + const uint8_t max_channel = DWC2_CHANNEL_MAX(dwc2); for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { if (tu_bit_test(dwc2->haintmsk, ch_id)) { const dwc2_channel_char_t hcchar_bm = dwc2->channel[ch_id].hcchar_bm; @@ -366,7 +368,6 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { //--------------------------------------------------------------------+ // Open an endpoint -// channel0 is reserved for dev0 control endpoint bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep) { (void) rhport; //dwc2_regs_t* dwc2 = DWC2_REG(rhport); @@ -452,7 +453,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * channel->hcchar = pipe->hcchar & ~HCCHAR_CHENA; // restore hcchar but don't enable yet pipe->buffer = buffer; - pipe->total_len = buflen; + pipe->total_bytes = buflen; if (dma_host_enabled(dwc2)) { channel->hcdma = (uint32_t) buffer; @@ -542,7 +543,7 @@ static void handle_rxflvl_irq(uint8_t rhport) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; switch (grxstsp_bm.packet_status) { - case GRXSTS_PKTSTS_HOST_IN_RECEIVED: { + case GRXSTS_PKTSTS_RX_DATA: { // In packet received const uint16_t byte_count = grxstsp_bm.byte_count; const uint8_t pipe_id = pipe_find_opened_by_channel(channel); @@ -554,13 +555,13 @@ static void handle_rxflvl_irq(uint8_t rhport) { // short packet, minus remaining bytes (xfer_size) if (byte_count < channel->hctsiz_bm.xfer_size) { - pipe->total_len -= channel->hctsiz_bm.xfer_size; + pipe->total_bytes -= channel->hctsiz_bm.xfer_size; } break; } - case GRXSTS_PKTSTS_HOST_IN_XFER_COMPL: + case GRXSTS_PKTSTS_RX_COMPLETE: // In transfer complete: After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed // interrupt --> handle_channel_irq() break; @@ -645,14 +646,13 @@ TU_ATTR_ALWAYS_INLINE static inline void handle_hprt_irq(uint8_t rhport, bool in void handle_channel_irq(uint8_t rhport, bool in_isr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - for(uint8_t ch_id=0; ch_id<32; ch_id++) { + for (uint8_t ch_id = 0; ch_id < 32; ch_id++) { if (tu_bit_test(dwc2->haint, ch_id)) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; uint32_t hcint = channel->hcint; hcint &= channel->hcintmsk; dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; - xfer_result_t result = XFER_RESULT_INVALID; // invalid means transfer is not complete if (hcint & HCINT_XFER_COMPLETE) { @@ -686,12 +686,11 @@ void handle_channel_irq(uint8_t rhport, bool in_isr) { // Transfer is complete (success, stalled, failed) or channel is disabled if (result != XFER_RESULT_INVALID || (hcint & HCINT_CHANNEL_HALTED)) { uint8_t pipe_id = pipe_find_opened_by_channel(channel); - if (pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX) { - hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; - pipe->pending_data = false; - } + TU_ASSERT(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX, ); + hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; const uint8_t ep_addr = tu_edpt_addr(hcchar_bm.ep_num, hcchar_bm.ep_dir); + pipe->pending_data = false; dwc2->haintmsk &= ~TU_BIT(ch_id); // de-allocate channel // notify usbh if transfer is complete (skip if channel is disabled) @@ -709,8 +708,9 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { // Use period txsts for both p/np to get request queue space available (1-bit difference, it is small enough) volatile dwc2_hptxsts_t* txsts_bm = (volatile dwc2_hptxsts_t*) (is_periodic ? &dwc2->hptxsts : &dwc2->hnptxsts); - // find which channel have pending packet + // find OUT channel with pending data bool ff_written = false; + //const uint8_t max_channel = DWC2_CHANNEL_MAX(dwc2); for (uint8_t ch_id = 0; ch_id < 32; ch_id++) { if (tu_bit_test(dwc2->haintmsk, ch_id)) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; @@ -723,16 +723,16 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { const uint16_t remain_packets = channel->hctsiz_bm.packet_count; for (uint16_t i = 0; i < remain_packets; i++) { const uint16_t remain_bytes = channel->hctsiz_bm.xfer_size; - const uint16_t packet_bytes = tu_min16(remain_bytes, hcchar_bm.ep_size); + const uint16_t xact_bytes = tu_min16(remain_bytes, hcchar_bm.ep_size); // check if there is enough space in FIFO and request queue. // the last dword written to FIFO will trigger dwc2 controller to write to RequestQueue - if ((packet_bytes > txsts_bm->fifo_available) && (txsts_bm->req_queue_available > 0)) { + if ((xact_bytes > txsts_bm->fifo_available) && (txsts_bm->req_queue_available > 0)) { break; } - dfifo_write_packet(dwc2, ch_id, pipe->buffer, packet_bytes); - pipe->buffer += packet_bytes; + dfifo_write_packet(dwc2, ch_id, pipe->buffer, xact_bytes); + pipe->buffer += xact_bytes; if (channel->hctsiz_bm.xfer_size == 0) { pipe->pending_data = false; // all data has been written -- cgit v1.3.1 From c93d3eda5f49c925855998f4e693dfcb2122228d Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 29 Oct 2024 13:01:48 +0700 Subject: restructure, add hcd endpoint, xfer to minimize footprint for managing xfer. --- src/portable/synopsys/dwc2/hcd_dwc2.c | 352 ++++++++++++++++++++-------------- 1 file changed, 203 insertions(+), 149 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 027a839bb..8dfc99692 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -34,20 +34,35 @@ #include "host/hcd.h" #include "dwc2_common.h" -// Max number of endpoints application can open +// Max number of endpoints application can open, can be larger than DWC2_CHANNEL_COUNT_MAX #ifndef CFG_TUH_DWC2_ENDPOINT_MAX #define CFG_TUH_DWC2_ENDPOINT_MAX 16 #endif +#define DWC2_CHANNEL_COUNT_MAX 16 // absolute max channel count +#define DWC2_CHANNEL_COUNT(_dwc2) tu_min8((_dwc2)->ghwcfg2_bm.num_host_ch + 1, DWC2_CHANNEL_COUNT_MAX) + TU_VERIFY_STATIC(CFG_TUH_DWC2_ENDPOINT_MAX <= 255, "currently only use 8-bit for index"); enum { HPRT_W1C_MASK = HPRT_CONN_DETECT | HPRT_ENABLE | HPRT_ENABLE_CHANGE | HPRT_OVER_CURRENT_CHANGE }; +enum { + HCD_XFER_ERROR_MAX = 3 +}; + +enum { + HCD_XFER_STATE_UNALLOCATED = 0, + HCD_XFER_STATE_ACTIVE = 1, + HCD_XFER_STATE_DISABLING = 2, +}; + +//-------------------------------------------------------------------- +// +//-------------------------------------------------------------------- + // Host driver struct for each opened endpoint -// When making an usb transfer, we will find an inactive channel and use it by enabled haintmsk. When the transfer is -// complete, haintmsk will be cleared, and channel is deactivated/deallocated. typedef struct { union { uint32_t hcchar; @@ -58,20 +73,26 @@ typedef struct { dwc2_channel_split_t hcsplt_bm; }; - uint8_t* buffer; - uint16_t total_bytes; uint8_t next_data_toggle; + // uint8_t resv[3]; +} hcd_endpoint_t; + +// Additional info for each channel when it is active +typedef struct { + volatile uint8_t state; volatile bool pending_data; -} hcd_pipe_t; + uint8_t err_count; + uint8_t* buffer; + uint16_t total_bytes; +} hcd_xfer_t; typedef struct { - hcd_pipe_t pipe[CFG_TUH_DWC2_ENDPOINT_MAX]; + hcd_xfer_t xfer[DWC2_CHANNEL_COUNT_MAX]; + hcd_endpoint_t edpt[CFG_TUH_DWC2_ENDPOINT_MAX]; } hcd_data_t; hcd_data_t _hcd_data; -#define DWC2_CHANNEL_MAX(_dwc2) tu_min8((_dwc2)->ghwcfg2_bm.num_host_ch + 1, 16) - //-------------------------------------------------------------------- // //-------------------------------------------------------------------- @@ -95,11 +116,6 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc return CFG_TUH_DWC2_DMA && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; } -// Check if channel is periodic (interrupt/isochronous) -TU_ATTR_ALWAYS_INLINE static inline bool channel_is_periodic(dwc2_channel_char_t hcchar_bm) { - return hcchar_bm.ep_type == HCCHAR_EPTYPE_INTERRUPT || hcchar_bm.ep_type == HCCHAR_EPTYPE_ISOCHRONOUS; -} - TU_ATTR_ALWAYS_INLINE static inline uint8_t request_queue_avail(const dwc2_regs_t* dwc2, bool is_period) { if (is_period) { return dwc2->hptxsts_bm.req_queue_available; @@ -108,40 +124,49 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t request_queue_avail(const dwc2_regs_ } } +// Check if channel is periodic (interrupt/isochronous) +TU_ATTR_ALWAYS_INLINE static inline bool channel_is_periodic(dwc2_channel_char_t hcchar_bm) { + return hcchar_bm.ep_type == HCCHAR_EPTYPE_INTERRUPT || hcchar_bm.ep_type == HCCHAR_EPTYPE_ISOCHRONOUS; +} + // Find a free channel for new transfer -TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_free(dwc2_regs_t* dwc2) { - const uint8_t max_channel = DWC2_CHANNEL_MAX(dwc2); +TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) { + const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { - // haintmsk bit enabled means channel is currently in use - if (!tu_bit_test(dwc2->haintmsk, ch_id)) { + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + if (HCD_XFER_STATE_UNALLOCATED == xfer->state) { + tu_memclr(xfer, sizeof(hcd_xfer_t)); + xfer->state = HCD_XFER_STATE_ACTIVE; return ch_id; } } return TUSB_INDEX_INVALID_8; } -// Find currently enabled/active channel associated with a pipe -TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_enabled_by_pipe(dwc2_regs_t* dwc2, const hcd_pipe_t* pipe) { - const uint8_t max_channel = DWC2_CHANNEL_MAX(dwc2); +TU_ATTR_ALWAYS_INLINE static inline void channel_dealloc(dwc2_regs_t* dwc2, uint8_t ch_id) { + (void) dwc2; + _hcd_data.xfer[ch_id].state = HCD_XFER_STATE_UNALLOCATED; +} + +// Find currently enabled channel. Note: EP0 is bidirectional +TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_enabled(dwc2_regs_t* dwc2, uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) { + const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { - if (tu_bit_test(dwc2->haintmsk, ch_id)) { + if (_hcd_data.xfer[ch_id].state != HCD_XFER_STATE_UNALLOCATED) { const dwc2_channel_char_t hcchar_bm = dwc2->channel[ch_id].hcchar_bm; - if (hcchar_bm.dev_addr == pipe->hcchar_bm.dev_addr && - hcchar_bm.ep_num == pipe->hcchar_bm.ep_num && - (hcchar_bm.ep_num == 0 || hcchar_bm.ep_dir == pipe->hcchar_bm.ep_dir)) { + if (hcchar_bm.dev_addr == dev_addr && hcchar_bm.ep_num == ep_num && (ep_num == 0 || hcchar_bm.ep_dir == ep_dir)) { return ch_id; } } } - return TUSB_INDEX_INVALID_8; } -// Find a pipe that is opened previously with hcd_edpt_open() -TU_ATTR_ALWAYS_INLINE static inline uint8_t pipe_find_opened(uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) { +// Find a endpoint that is opened previously with hcd_edpt_open() +// Note: EP0 is bidirectional +TU_ATTR_ALWAYS_INLINE static inline uint8_t edpt_find_opened(uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) { for (uint8_t i = 0; i < (uint8_t)CFG_TUH_DWC2_ENDPOINT_MAX; i++) { - const dwc2_channel_char_t* hcchar_bm = &_hcd_data.pipe[i].hcchar_bm; - // find enabled pipe: note EP0 is bidirectional + const dwc2_channel_char_t* hcchar_bm = &_hcd_data.edpt[i].hcchar_bm; if (hcchar_bm->enable && hcchar_bm->dev_addr == dev_addr && hcchar_bm->ep_num == ep_num && (ep_num == 0 || hcchar_bm->ep_dir == ep_dir)) { return i; @@ -150,12 +175,6 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t pipe_find_opened(uint8_t dev_addr, u return TUSB_INDEX_INVALID_8; } -// Find a pipe that is opened previously with hcd_edpt_open() and associated with a channel -TU_ATTR_ALWAYS_INLINE static inline uint8_t pipe_find_opened_by_channel(const dwc2_channel_t* channel) { - const dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; - return pipe_find_opened(hcchar_bm.dev_addr, hcchar_bm.ep_num, hcchar_bm.ep_dir); -} - //-------------------------------------------------------------------- // //-------------------------------------------------------------------- @@ -356,9 +375,9 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport) { void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { (void) rhport; for (uint8_t i = 0; i < (uint8_t) CFG_TUH_DWC2_ENDPOINT_MAX; i++) { - hcd_pipe_t* pipe = &_hcd_data.pipe[i]; - if (pipe->hcchar_bm.enable && pipe->hcchar_bm.dev_addr == dev_addr) { - tu_memclr(pipe, sizeof(hcd_pipe_t)); + hcd_endpoint_t* edpt = &_hcd_data.edpt[i]; + if (edpt->hcchar_bm.enable && edpt->hcchar_bm.dev_addr == dev_addr) { + tu_memclr(edpt, sizeof(hcd_endpoint_t)); } } } @@ -368,18 +387,18 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { //--------------------------------------------------------------------+ // Open an endpoint -bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep) { +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* desc_ep) { (void) rhport; //dwc2_regs_t* dwc2 = DWC2_REG(rhport); hcd_devtree_info_t devtree_info; hcd_devtree_get_info(dev_addr, &devtree_info); - // find a free pipe + // find a free endpoint for (uint32_t i = 0; i < CFG_TUH_DWC2_ENDPOINT_MAX; i++) { - hcd_pipe_t* pipe = &_hcd_data.pipe[i]; - dwc2_channel_char_t* hcchar_bm = &pipe->hcchar_bm; - dwc2_channel_split_t* hcsplt_bm = &pipe->hcsplt_bm; + hcd_endpoint_t* edpt = &_hcd_data.edpt[i]; + dwc2_channel_char_t* hcchar_bm = &edpt->hcchar_bm; + dwc2_channel_split_t* hcsplt_bm = &edpt->hcsplt_bm; if (hcchar_bm->enable == 0) { hcchar_bm->ep_size = tu_edpt_packet_size(desc_ep); @@ -400,7 +419,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const hcsplt_bm->split_compl = 0; hcsplt_bm->split_en = 0; - pipe->next_data_toggle = HCTSIZ_PID_DATA0; + edpt->next_data_toggle = HCTSIZ_PID_DATA0; return true; } @@ -412,48 +431,56 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - const uint8_t ep_num = tu_edpt_number(ep_addr); const uint8_t ep_dir = tu_edpt_dir(ep_addr); - uint8_t pipe_id = pipe_find_opened(dev_addr, ep_num, ep_dir); - TU_ASSERT(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX); // no opened pipe - hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; - dwc2_channel_char_t* hcchar_bm = &pipe->hcchar_bm; + uint8_t ep_id = edpt_find_opened(dev_addr, ep_num, ep_dir); + TU_ASSERT(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); + hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; + dwc2_channel_char_t* hcchar_bm = &edpt->hcchar_bm; + + uint8_t ch_id = channel_alloc(dwc2); + TU_ASSERT(ch_id < 16); // all channel are in used + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; - uint8_t ch_id = channel_find_free(dwc2); - TU_ASSERT(ch_id < 16); // all channel are in use dwc2->haintmsk |= TU_BIT(ch_id); dwc2_channel_t* channel = &dwc2->channel[ch_id]; - uint32_t hcintmsk = HCINT_XFER_COMPLETE | HCINT_CHANNEL_HALTED | HCINT_STALL | - HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR; - if (ep_dir == TUSB_DIR_IN) { - hcintmsk |= HCINT_NAK; + + uint32_t hcintmsk = HCINT_NAK | HCINT_XACT_ERR | HCINT_STALL | HCINT_XFER_COMPLETE | HCINT_DATATOGGLE_ERR; + if (dma_host_enabled(dwc2)) { + TU_ASSERT(false); // not yet supported + } else { + if (hcchar_bm->ep_dir == TUSB_DIR_OUT) { + hcintmsk |= HCINT_NYET; + } else { + hcintmsk |= HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR; + } } + channel->hcintmsk = hcintmsk; uint16_t packet_count = tu_div_ceil(buflen, hcchar_bm->ep_size); if (packet_count == 0) { packet_count = 1; // zero length packet still count as 1 } - channel->hctsiz = (pipe->next_data_toggle << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | buflen; + channel->hctsiz = (edpt->next_data_toggle << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | buflen; // Control transfer always start with DATA1 for data and status stage. May has issue with ZLP - if (pipe->next_data_toggle == HCTSIZ_PID_DATA0 || ep_num == 0) { - pipe->next_data_toggle = HCTSIZ_PID_DATA1; + if (edpt->next_data_toggle == HCTSIZ_PID_DATA0 || ep_num == 0) { + edpt->next_data_toggle = HCTSIZ_PID_DATA1; } else { - pipe->next_data_toggle = HCTSIZ_PID_DATA0; + edpt->next_data_toggle = HCTSIZ_PID_DATA0; } // TODO support split transaction - channel->hcsplt = pipe->hcsplt; + channel->hcsplt = edpt->hcsplt; hcchar_bm->odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame hcchar_bm->ep_dir = ep_dir; // control endpoint can switch direction - channel->hcchar = pipe->hcchar & ~HCCHAR_CHENA; // restore hcchar but don't enable yet + channel->hcchar = edpt->hcchar & ~HCCHAR_CHENA; // restore hcchar but don't enable yet - pipe->buffer = buffer; - pipe->total_bytes = buflen; + xfer->buffer = buffer; + xfer->total_bytes = buflen; if (dma_host_enabled(dwc2)) { channel->hcdma = (uint32_t) buffer; @@ -466,15 +493,15 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * // IN Token. If we got NAK, we have to re-enable the channel again in the interrupt. Due to the way usbh stack only // call hcd_edpt_xfer() once, we will need to manage de-allocate/re-allocate IN channel dynamically. if (ep_dir == TUSB_DIR_IN) { - pipe->pending_data = true; + xfer->pending_data = true; TU_ASSERT(request_queue_avail(dwc2, is_period)); channel->hcchar |= HCCHAR_CHENA; } else { channel->hcchar |= HCCHAR_CHENA; if (buflen > 0) { - // To prevent conflict with other channel, we will enable periodic/non-periodic FIFO empty interrupt accordingly. + // To prevent conflict with other channel, we will enable periodic/non-periodic FIFO empty interrupt accordingly // And write packet in the interrupt handler - pipe->pending_data = true; + xfer->pending_data = true; dwc2->gintmsk |= (is_period ? GINTSTS_PTX_FIFO_EMPTY : GINTSTS_NPTX_FIFO_EMPTY); } } @@ -487,36 +514,37 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * // Return true if a queued transfer is aborted, false if there is no transfer to abort bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); + const uint8_t ep_num = tu_edpt_number(ep_addr); + const uint8_t ep_dir = tu_edpt_dir(ep_addr); + const uint8_t ep_id = edpt_find_opened(dev_addr, ep_num, ep_dir); + TU_VERIFY(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); + hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; - const uint8_t pipe_id = pipe_find_opened(dev_addr, tu_edpt_number(ep_addr), tu_edpt_dir(ep_addr)); - TU_VERIFY(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX); - hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; - - hcd_int_disable(rhport); + // hcd_int_disable(rhport); // Find enabled channeled and disable it, channel will be de-allocated in the interrupt handler - const uint8_t ch_id = channel_find_enabled_by_pipe(dwc2, pipe); + const uint8_t ch_id = channel_find_enabled(dwc2, dev_addr, ep_num, ep_dir); if (ch_id < 16) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; // disable also require request queue - if (request_queue_avail(dwc2, channel_is_periodic(pipe->hcchar_bm))) { + if (request_queue_avail(dwc2, channel_is_periodic(edpt->hcchar_bm))) { channel->hcchar |= HCCHAR_CHDIS; } else { TU_BREAKPOINT(); } } - hcd_int_enable(rhport); + // hcd_int_enable(rhport); return true; } // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, const uint8_t setup_packet[8]) { - uint8_t pipe_id = pipe_find_opened(dev_addr, 0, TUSB_DIR_OUT); - TU_ASSERT(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX); // no opened pipe - hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; - pipe->next_data_toggle = HCTSIZ_PID_SETUP; + uint8_t ep_id = edpt_find_opened(dev_addr, 0, TUSB_DIR_OUT); + TU_ASSERT(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); // no opened endpoint + hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; + edpt->next_data_toggle = HCTSIZ_PID_SETUP; return hcd_edpt_xfer(rhport, dev_addr, 0, (uint8_t*)(uintptr_t) setup_packet, 8); } @@ -546,16 +574,14 @@ static void handle_rxflvl_irq(uint8_t rhport) { case GRXSTS_PKTSTS_RX_DATA: { // In packet received const uint16_t byte_count = grxstsp_bm.byte_count; - const uint8_t pipe_id = pipe_find_opened_by_channel(channel); - TU_VERIFY(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX, ); - hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; - dfifo_read_packet(dwc2, pipe->buffer, byte_count); - pipe->buffer += byte_count; + dfifo_read_packet(dwc2, xfer->buffer, byte_count); + xfer->buffer += byte_count; // short packet, minus remaining bytes (xfer_size) if (byte_count < channel->hctsiz_bm.xfer_size) { - pipe->total_bytes -= channel->hctsiz_bm.xfer_size; + xfer->total_bytes -= channel->hctsiz_bm.xfer_size; } break; @@ -644,58 +670,89 @@ TU_ATTR_ALWAYS_INLINE static inline void handle_hprt_irq(uint8_t rhport, bool in dwc2->hprt = hprt; // clear interrupt } +// DMA related error: HCINT_BUFFER_NA | HCINT_DESC_ROLLOVER +// if (hcint & (HCINT_BUFFER_NA | HCINT_DESC_ROLLOVER)) { +// result = XFER_RESULT_FAILED; +// } void handle_channel_irq(uint8_t rhport, bool in_isr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - for (uint8_t ch_id = 0; ch_id < 32; ch_id++) { + const bool is_dma = dma_host_enabled(dwc2); + const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); + + for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { // if (tu_bit_test(dwc2->haint, ch_id)) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + uint32_t hcint = channel->hcint; hcint &= channel->hcintmsk; dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; - xfer_result_t result = XFER_RESULT_INVALID; // invalid means transfer is not complete + xfer_result_t result = XFER_RESULT_INVALID; // invalid means not DONE - if (hcint & HCINT_XFER_COMPLETE) { - result = XFER_RESULT_SUCCESS; - } - if (hcint & HCINT_STALL) { - result = XFER_RESULT_STALLED; - } - // DMA related error: HCINT_BUFFER_NA | HCINT_DESC_ROLLOVER - // if (hcint & (HCINT_BUFFER_NA | HCINT_DESC_ROLLOVER)) { - // result = XFER_RESULT_FAILED; - // } - const uint32_t xact_err = hcint & (HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | - HCINT_DATATOGGLE_ERR | HCINT_XCS_XACT_ERR); - if (xact_err) { - result = XFER_RESULT_FAILED; - } - - if (!xact_err && (hcint & HCINT_CHANNEL_HALTED)) { - // Channel halted without error, this is a response to channel disable - result = XFER_RESULT_INVALID; - } + if (is_dma) { - if (hcint & HCINT_NAK) { - // NAK received, re-enable channel if request queue is available - result = XFER_RESULT_INVALID; - TU_ASSERT(request_queue_avail(dwc2, channel_is_periodic(hcchar_bm)), ); - channel->hcchar |= HCCHAR_CHENA; - } + } else { + if (hcint & HCINT_XFER_COMPLETE) { + result = XFER_RESULT_SUCCESS; + channel->hcintmsk &= ~HCINT_ACK; + channel_dealloc(dwc2, ch_id); + } else if (hcint & HCINT_STALL) { + result = XFER_RESULT_STALLED; + channel->hcintmsk |= HCINT_CHANNEL_HALTED; + channel->hcchar_bm.disable = 1; + } else if (hcint & (HCINT_NAK | HCINT_XACT_ERR | HCINT_NYET)) { + if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { + // rewind buffer + } else { + if (hcint & HCINT_NAK) { + // NAK received, re-enable channel if request queue is available + TU_ASSERT(request_queue_avail(dwc2, channel_is_periodic(hcchar_bm)), ); + channel->hcchar |= HCCHAR_CHENA; + } + } - // Transfer is complete (success, stalled, failed) or channel is disabled - if (result != XFER_RESULT_INVALID || (hcint & HCINT_CHANNEL_HALTED)) { - uint8_t pipe_id = pipe_find_opened_by_channel(channel); - TU_ASSERT(pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX, ); - hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; - const uint8_t ep_addr = tu_edpt_addr(hcchar_bm.ep_num, hcchar_bm.ep_dir); + // unmask halted + // disable channel + if (hcint & HCINT_XACT_ERR) { + xfer->err_count++; + channel->hcintmsk |= HCINT_ACK; + }else { + xfer->err_count = 0; + } + } else if (hcint & HCINT_CHANNEL_HALTED) { + if (channel->hcchar_bm.err_multi_count == HCD_XFER_ERROR_MAX) { - pipe->pending_data = false; - dwc2->haintmsk &= ~TU_BIT(ch_id); // de-allocate channel + } else { + // Re-initialize Channel (Do ping protocol for HS) + } + } else if (hcint & HCINT_ACK) { + // ACK received, reset error count + xfer->err_count = 0; + channel->hcintmsk &= ~HCINT_ACK; + } - // notify usbh if transfer is complete (skip if channel is disabled) - if (result != XFER_RESULT_INVALID) { - hcd_event_xfer_complete(hcchar_bm.dev_addr, ep_addr, 0, result, in_isr); + // const uint32_t xact_err = hcint & (HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | + // HCINT_DATATOGGLE_ERR | HCINT_XCS_XACT_ERR); + // if (xact_err) { + // result = XFER_RESULT_FAILED; + // } + // if (!xact_err && (hcint & HCINT_CHANNEL_HALTED)) { + // // Channel halted without error, this is a response to channel disable + // result = XFER_RESULT_INVALID; + // } + + + // Transfer is complete (success, stalled, failed) or channel is disabled + if (result != XFER_RESULT_INVALID || (hcint & HCINT_CHANNEL_HALTED)) { + xfer->pending_data = false; + dwc2->haintmsk &= ~TU_BIT(ch_id); // de-allocate channel + + // notify usbh if transfer is complete (skip if channel is disabled) + const uint8_t ep_addr = tu_edpt_addr(hcchar_bm.ep_num, hcchar_bm.ep_dir); + if (result != XFER_RESULT_INVALID) { + hcd_event_xfer_complete(hcchar_bm.dev_addr, ep_addr, 0, result, in_isr); + } } } @@ -710,36 +767,33 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { // find OUT channel with pending data bool ff_written = false; - //const uint8_t max_channel = DWC2_CHANNEL_MAX(dwc2); - for (uint8_t ch_id = 0; ch_id < 32; ch_id++) { + //const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); + for (uint8_t ch_id = 0; ch_id < 32 /* 16 */ ; ch_id++) { if (tu_bit_test(dwc2->haintmsk, ch_id)) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; const dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { - uint8_t pipe_id = pipe_find_opened_by_channel(channel); - if (pipe_id < CFG_TUH_DWC2_ENDPOINT_MAX) { - hcd_pipe_t* pipe = &_hcd_data.pipe[pipe_id]; - if (pipe->pending_data) { - const uint16_t remain_packets = channel->hctsiz_bm.packet_count; - for (uint16_t i = 0; i < remain_packets; i++) { - const uint16_t remain_bytes = channel->hctsiz_bm.xfer_size; - const uint16_t xact_bytes = tu_min16(remain_bytes, hcchar_bm.ep_size); - - // check if there is enough space in FIFO and request queue. - // the last dword written to FIFO will trigger dwc2 controller to write to RequestQueue - if ((xact_bytes > txsts_bm->fifo_available) && (txsts_bm->req_queue_available > 0)) { - break; - } - - dfifo_write_packet(dwc2, ch_id, pipe->buffer, xact_bytes); - pipe->buffer += xact_bytes; - - if (channel->hctsiz_bm.xfer_size == 0) { - pipe->pending_data = false; // all data has been written - } - - ff_written = true; + if (xfer->pending_data) { + const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + for (uint16_t i = 0; i < remain_packets; i++) { + const uint16_t remain_bytes = channel->hctsiz_bm.xfer_size; + const uint16_t xact_bytes = tu_min16(remain_bytes, hcchar_bm.ep_size); + + // check if there is enough space in FIFO and request queue. + // the last dword written to FIFO will trigger dwc2 controller to write to RequestQueue + if ((xact_bytes > txsts_bm->fifo_available) && (txsts_bm->req_queue_available > 0)) { + break; } + + dfifo_write_packet(dwc2, ch_id, xfer->buffer, xact_bytes); + xfer->buffer += xact_bytes; + + if (channel->hctsiz_bm.xfer_size == 0) { + xfer->pending_data = false; // all data has been written + } + + ff_written = true; } } } -- cgit v1.3.1 From 4797c4f508d183c949b5554ac4d32a7ea71d020c Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 29 Oct 2024 14:47:44 +0700 Subject: fix nptx fifo empty handling --- src/portable/synopsys/dwc2/hcd_dwc2.c | 63 +++++++++++++---------------------- 1 file changed, 24 insertions(+), 39 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 8dfc99692..edbdce45c 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -80,7 +80,6 @@ typedef struct { // Additional info for each channel when it is active typedef struct { volatile uint8_t state; - volatile bool pending_data; uint8_t err_count; uint8_t* buffer; uint16_t total_bytes; @@ -441,9 +440,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * uint8_t ch_id = channel_alloc(dwc2); TU_ASSERT(ch_id < 16); // all channel are in used hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; - - dwc2->haintmsk |= TU_BIT(ch_id); - dwc2_channel_t* channel = &dwc2->channel[ch_id]; uint32_t hcintmsk = HCINT_NAK | HCINT_XACT_ERR | HCINT_STALL | HCINT_XFER_COMPLETE | HCINT_DATATOGGLE_ERR; @@ -457,8 +453,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * } } - channel->hcintmsk = hcintmsk; - uint16_t packet_count = tu_div_ceil(buflen, hcchar_bm->ep_size); if (packet_count == 0) { packet_count = 1; // zero length packet still count as 1 @@ -477,7 +471,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * hcchar_bm->odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame hcchar_bm->ep_dir = ep_dir; // control endpoint can switch direction - channel->hcchar = edpt->hcchar & ~HCCHAR_CHENA; // restore hcchar but don't enable yet + channel->hcchar = (edpt->hcchar & ~HCCHAR_CHENA); // restore hcchar but don't enable yet xfer->buffer = buffer; xfer->total_bytes = buflen; @@ -493,7 +487,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * // IN Token. If we got NAK, we have to re-enable the channel again in the interrupt. Due to the way usbh stack only // call hcd_edpt_xfer() once, we will need to manage de-allocate/re-allocate IN channel dynamically. if (ep_dir == TUSB_DIR_IN) { - xfer->pending_data = true; TU_ASSERT(request_queue_avail(dwc2, is_period)); channel->hcchar |= HCCHAR_CHENA; } else { @@ -501,12 +494,14 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * if (buflen > 0) { // To prevent conflict with other channel, we will enable periodic/non-periodic FIFO empty interrupt accordingly // And write packet in the interrupt handler - xfer->pending_data = true; dwc2->gintmsk |= (is_period ? GINTSTS_PTX_FIFO_EMPTY : GINTSTS_NPTX_FIFO_EMPTY); } } } + channel->hcintmsk = hcintmsk; + dwc2->haintmsk |= TU_BIT(ch_id); + return true; } @@ -745,7 +740,6 @@ void handle_channel_irq(uint8_t rhport, bool in_isr) { // Transfer is complete (success, stalled, failed) or channel is disabled if (result != XFER_RESULT_INVALID || (hcint & HCINT_CHANNEL_HALTED)) { - xfer->pending_data = false; dwc2->haintmsk &= ~TU_BIT(ch_id); // de-allocate channel // notify usbh if transfer is complete (skip if channel is disabled) @@ -761,46 +755,37 @@ void handle_channel_irq(uint8_t rhport, bool in_isr) { } } +// return true if there is still pending data and need more ISR bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { // Use period txsts for both p/np to get request queue space available (1-bit difference, it is small enough) volatile dwc2_hptxsts_t* txsts_bm = (volatile dwc2_hptxsts_t*) (is_periodic ? &dwc2->hptxsts : &dwc2->hnptxsts); - // find OUT channel with pending data - bool ff_written = false; - //const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); - for (uint8_t ch_id = 0; ch_id < 32 /* 16 */ ; ch_id++) { - if (tu_bit_test(dwc2->haintmsk, ch_id)) { + const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); + for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + if (xfer->state == HCD_XFER_STATE_ACTIVE) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; const dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; - hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { - if (xfer->pending_data) { - const uint16_t remain_packets = channel->hctsiz_bm.packet_count; - for (uint16_t i = 0; i < remain_packets; i++) { - const uint16_t remain_bytes = channel->hctsiz_bm.xfer_size; - const uint16_t xact_bytes = tu_min16(remain_bytes, hcchar_bm.ep_size); - - // check if there is enough space in FIFO and request queue. - // the last dword written to FIFO will trigger dwc2 controller to write to RequestQueue - if ((xact_bytes > txsts_bm->fifo_available) && (txsts_bm->req_queue_available > 0)) { - break; - } - - dfifo_write_packet(dwc2, ch_id, xfer->buffer, xact_bytes); - xfer->buffer += xact_bytes; - - if (channel->hctsiz_bm.xfer_size == 0) { - xfer->pending_data = false; // all data has been written - } - - ff_written = true; + const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + for (uint16_t i = 0; i < remain_packets; i++) { + const uint16_t remain_bytes = channel->hctsiz_bm.xfer_size; + const uint16_t xact_bytes = tu_min16(remain_bytes, hcchar_bm.ep_size); + + // check if there is enough space in FIFO and RequestQueue. + // Packet's last word written to FIFO will trigger a request queue + if ((xact_bytes > txsts_bm->fifo_available) && (txsts_bm->req_queue_available > 0)) { + return true; } + + dfifo_write_packet(dwc2, ch_id, xfer->buffer, xact_bytes); + xfer->buffer += xact_bytes; } } } } - return ff_written; + return false; // all data written } /* Interrupt Hierarchy @@ -842,8 +827,8 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { if (int_status & GINTSTS_NPTX_FIFO_EMPTY) { // NPTX FIFO empty interrupt, this is read-only and cleared by hardware when FIFO is written - const bool ff_written = handle_txfifo_empty(dwc2, false); - if (!ff_written) { + const bool more_isr = handle_txfifo_empty(dwc2, false); + if (!more_isr) { // no more pending packet, disable interrupt dwc2->gintmsk &= ~GINTSTS_NPTX_FIFO_EMPTY; } -- cgit v1.3.1 From cef9bab4b54ec038636738cf0969800ac7dd19fe Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 29 Oct 2024 15:07:28 +0700 Subject: minor clean up --- src/portable/synopsys/dwc2/hcd_dwc2.c | 70 +++++++++++++++++------------------ 1 file changed, 33 insertions(+), 37 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index edbdce45c..ce5d34cb7 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -123,11 +123,6 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t request_queue_avail(const dwc2_regs_ } } -// Check if channel is periodic (interrupt/isochronous) -TU_ATTR_ALWAYS_INLINE static inline bool channel_is_periodic(dwc2_channel_char_t hcchar_bm) { - return hcchar_bm.ep_type == HCCHAR_EPTYPE_INTERRUPT || hcchar_bm.ep_type == HCCHAR_EPTYPE_ISOCHRONOUS; -} - // Find a free channel for new transfer TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) { const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); @@ -161,6 +156,11 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_enabled(dwc2_regs_t* dw return TUSB_INDEX_INVALID_8; } +// Check if is periodic (interrupt/isochronous) +TU_ATTR_ALWAYS_INLINE static inline bool edpt_is_periodic(uint8_t ep_type) { + return ep_type == HCCHAR_EPTYPE_INTERRUPT || ep_type == HCCHAR_EPTYPE_ISOCHRONOUS; +} + // Find a endpoint that is opened previously with hcd_edpt_open() // Note: EP0 is bidirectional TU_ATTR_ALWAYS_INLINE static inline uint8_t edpt_find_opened(uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) { @@ -400,25 +400,26 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* dwc2_channel_split_t* hcsplt_bm = &edpt->hcsplt_bm; if (hcchar_bm->enable == 0) { - hcchar_bm->ep_size = tu_edpt_packet_size(desc_ep); - hcchar_bm->ep_num = tu_edpt_number(desc_ep->bEndpointAddress); - hcchar_bm->ep_dir = tu_edpt_dir(desc_ep->bEndpointAddress); - hcchar_bm->low_speed_dev = (devtree_info.speed == TUSB_SPEED_LOW) ? 1 : 0; - hcchar_bm->ep_type = desc_ep->bmAttributes.xfer; // ep_type matches TUSB_XFER_* + hcchar_bm->ep_size = tu_edpt_packet_size(desc_ep); + hcchar_bm->ep_num = tu_edpt_number(desc_ep->bEndpointAddress); + hcchar_bm->ep_dir = tu_edpt_dir(desc_ep->bEndpointAddress); + hcchar_bm->low_speed_dev = (devtree_info.speed == TUSB_SPEED_LOW) ? 1 : 0; + hcchar_bm->ep_type = desc_ep->bmAttributes.xfer; // ep_type matches TUSB_XFER_* hcchar_bm->err_multi_count = 0; - hcchar_bm->dev_addr = dev_addr; - hcchar_bm->odd_frame = 0; - hcchar_bm->disable = 0; - hcchar_bm->enable = 1; + hcchar_bm->dev_addr = dev_addr; + hcchar_bm->odd_frame = 0; + hcchar_bm->disable = 0; + hcchar_bm->enable = 1; - hcsplt_bm->hub_port = devtree_info.hub_port; - hcsplt_bm->hub_addr = devtree_info.hub_addr; - // TODO not support split transaction yet - hcsplt_bm->xact_pos = 0; - hcsplt_bm->split_compl = 0; - hcsplt_bm->split_en = 0; + hcsplt_bm->hub_port = devtree_info.hub_port; + hcsplt_bm->hub_addr = devtree_info.hub_addr; + hcsplt_bm->xact_pos = 0; + hcsplt_bm->split_compl = 0; + hcsplt_bm->split_en = 0; + + edpt->next_data_toggle = HCTSIZ_PID_DATA0; - edpt->next_data_toggle = HCTSIZ_PID_DATA0; + // TODO not support split transaction yet return true; } @@ -442,17 +443,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; - uint32_t hcintmsk = HCINT_NAK | HCINT_XACT_ERR | HCINT_STALL | HCINT_XFER_COMPLETE | HCINT_DATATOGGLE_ERR; - if (dma_host_enabled(dwc2)) { - TU_ASSERT(false); // not yet supported - } else { - if (hcchar_bm->ep_dir == TUSB_DIR_OUT) { - hcintmsk |= HCINT_NYET; - } else { - hcintmsk |= HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR; - } - } - uint16_t packet_count = tu_div_ceil(buflen, hcchar_bm->ep_size); if (packet_count == 0) { packet_count = 1; // zero length packet still count as 1 @@ -476,19 +466,23 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * xfer->buffer = buffer; xfer->total_bytes = buflen; + uint32_t hcintmsk = HCINT_NAK | HCINT_XACT_ERR | HCINT_STALL | HCINT_XFER_COMPLETE | HCINT_DATATOGGLE_ERR; if (dma_host_enabled(dwc2)) { channel->hcdma = (uint32_t) buffer; + TU_ASSERT(false); // not yet supported } else { - bool const is_period = channel_is_periodic(*hcchar_bm); + bool const is_period = edpt_is_periodic(hcchar_bm->ep_type); // enable channel for slave mode: - // - OUT endpoint: it will enable corresponding FIFO channel - // - IN endpoint: it will write an IN request to the Non-periodic Request Queue, this will have dwc2 trying to send + // - OUT: it will enable corresponding FIFO channel + // - IN : it will write an IN request to the Non-periodic Request Queue, this will have dwc2 trying to send // IN Token. If we got NAK, we have to re-enable the channel again in the interrupt. Due to the way usbh stack only // call hcd_edpt_xfer() once, we will need to manage de-allocate/re-allocate IN channel dynamically. if (ep_dir == TUSB_DIR_IN) { TU_ASSERT(request_queue_avail(dwc2, is_period)); channel->hcchar |= HCCHAR_CHENA; + + hcintmsk |= HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR; } else { channel->hcchar |= HCCHAR_CHENA; if (buflen > 0) { @@ -496,6 +490,8 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * // And write packet in the interrupt handler dwc2->gintmsk |= (is_period ? GINTSTS_PTX_FIFO_EMPTY : GINTSTS_NPTX_FIFO_EMPTY); } + + hcintmsk |= HCINT_NYET; } } @@ -522,7 +518,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { if (ch_id < 16) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; // disable also require request queue - if (request_queue_avail(dwc2, channel_is_periodic(edpt->hcchar_bm))) { + if (request_queue_avail(dwc2, edpt_is_periodic(edpt->hcchar_bm.ep_type))) { channel->hcchar |= HCCHAR_CHDIS; } else { TU_BREAKPOINT(); @@ -702,7 +698,7 @@ void handle_channel_irq(uint8_t rhport, bool in_isr) { } else { if (hcint & HCINT_NAK) { // NAK received, re-enable channel if request queue is available - TU_ASSERT(request_queue_avail(dwc2, channel_is_periodic(hcchar_bm)), ); + TU_ASSERT(request_queue_avail(dwc2, edpt_is_periodic(hcchar_bm.ep_type)), ); channel->hcchar |= HCCHAR_CHENA; } } -- cgit v1.3.1 From 1e164412bf791cb682c386f9d1e8e3b806faf72a Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 29 Oct 2024 16:06:44 +0700 Subject: split handle channel slave out/in --- src/portable/synopsys/dwc2/dwc2_type.h | 6 +- src/portable/synopsys/dwc2/hcd_dwc2.c | 154 ++++++++++++++++++++------------- 2 files changed, 95 insertions(+), 65 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 7296475cf..d2ab1e94d 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -1846,9 +1846,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define HCINT_XFER_COMPLETE_Pos (0U) #define HCINT_XFER_COMPLETE_Msk (0x1UL << HCINT_XFER_COMPLETE_Pos) // 0x00000001 #define HCINT_XFER_COMPLETE HCINT_XFER_COMPLETE_Msk // Transfer completed -#define HCINT_CHANNEL_HALTED_Pos (1U) -#define HCINT_CHANNEL_HALTED_Msk (0x1UL << HCINT_CHANNEL_HALTED_Pos) // 0x00000002 -#define HCINT_CHANNEL_HALTED HCINT_CHANNEL_HALTED_Msk // Channel halted +#define HCINT_HALTED_Pos (1U) +#define HCINT_HALTED_Msk (0x1UL << HCINT_HALTED_Pos) // 0x00000002 +#define HCINT_HALTED HCINT_HALTED_Msk // Channel halted #define HCINT_AHB_ERR_Pos (2U) #define HCINT_AHB_ERR_Msk (0x1UL << HCINT_AHB_ERR_Pos) // 0x00000004 #define HCINT_AHB_ERR HCINT_AHB_ERR_Msk // AHB error diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index ce5d34cb7..568ce0c1f 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -55,7 +55,7 @@ enum { enum { HCD_XFER_STATE_UNALLOCATED = 0, HCD_XFER_STATE_ACTIVE = 1, - HCD_XFER_STATE_DISABLING = 2, + HCD_XFER_STATE_DONE = 2, }; //-------------------------------------------------------------------- @@ -138,8 +138,16 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) { } TU_ATTR_ALWAYS_INLINE static inline void channel_dealloc(dwc2_regs_t* dwc2, uint8_t ch_id) { - (void) dwc2; _hcd_data.xfer[ch_id].state = HCD_XFER_STATE_UNALLOCATED; + dwc2->haintmsk &= ~TU_BIT(ch_id); +} + +TU_ATTR_ALWAYS_INLINE static inline void channel_disable(dwc2_channel_t* channel) { + channel->hcintmsk |= HCINT_HALTED; + + uint32_t hcchar = channel->hcchar & ~HCCHAR_CHENA; // skip w1s enabled bit + hcchar |= HCCHAR_CHDIS; + channel->hcchar = hcchar; } // Find currently enabled channel. Note: EP0 is bidirectional @@ -661,10 +669,79 @@ TU_ATTR_ALWAYS_INLINE static inline void handle_hprt_irq(uint8_t rhport, bool in dwc2->hprt = hprt; // clear interrupt } -// DMA related error: HCINT_BUFFER_NA | HCINT_DESC_ROLLOVER -// if (hcint & (HCINT_BUFFER_NA | HCINT_DESC_ROLLOVER)) { -// result = XFER_RESULT_FAILED; -// } +xfer_result_t handle_channel_slave_in(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + dwc2_channel_t* channel = &dwc2->channel[ch_id]; + xfer_result_t result = XFER_RESULT_INVALID; + + if (hcint & HCINT_XFER_COMPLETE) { + result = XFER_RESULT_SUCCESS; + channel_disable(channel); + channel->hcintmsk &= ~HCINT_ACK; + } else if (hcint & (HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_STALL)) { + channel_disable(channel); + if (hcint & HCINT_XACT_ERR) { + xfer->err_count++; + channel->hcintmsk |= HCINT_ACK; + } + } else if (hcint & HCINT_HALTED) { + channel->hcintmsk &= ~HCINT_HALTED; + if (channel->hcchar_bm.err_multi_count == HCD_XFER_ERROR_MAX) { + channel_dealloc(dwc2, ch_id); + } else { + // Re-initialize Channel + } + } else if (hcint & HCINT_ACK) { + xfer->err_count = 0; + channel->hcintmsk &= ~HCINT_ACK; + } else if (hcint & HCINT_DATATOGGLE_ERR) { + xfer->err_count = 0; + } else if (hcint & HCINT_NAK) { + // NAK received, re-enable channel if request queue is available + TU_ASSERT(request_queue_avail(dwc2, is_period), XFER_RESULT_INVALID); + channel->hcchar |= HCCHAR_CHENA; + } + + return result; +} + +xfer_result_t handle_channel_slave_out(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { + (void) is_period; + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + dwc2_channel_t* channel = &dwc2->channel[ch_id]; + xfer_result_t result = XFER_RESULT_INVALID; + + if (hcint & HCINT_XFER_COMPLETE) { + result = XFER_RESULT_SUCCESS; + channel->hcintmsk &= ~HCINT_ACK; + channel_dealloc(dwc2, ch_id); + } else if (hcint & HCINT_STALL) { + xfer->state = HCD_XFER_STATE_DONE; + channel_disable(channel); + } else if (hcint & (HCINT_NAK | HCINT_XACT_ERR | HCINT_NYET)) { + channel_disable(channel); + if (hcint & HCINT_XACT_ERR) { + xfer->err_count++; + channel->hcintmsk |= HCINT_ACK; + } else { + xfer->err_count = 0; + } + } else if (hcint & HCINT_HALTED) { + channel->hcintmsk &= ~HCINT_HALTED; + if (xfer->state == HCD_XFER_STATE_DONE || channel->hcchar_bm.err_multi_count == HCD_XFER_ERROR_MAX) { + result = (xfer->state == HCD_XFER_STATE_DONE ? XFER_RESULT_STALLED : XFER_RESULT_FAILED); + channel_dealloc(dwc2, ch_id); + } else { + // Re-initialize Channel (Do ping protocol for HS) + } + } else if (hcint & HCINT_ACK) { + xfer->err_count = 0; + channel->hcintmsk &= ~HCINT_ACK; + } + + return result; +} + void handle_channel_irq(uint8_t rhport, bool in_isr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); const bool is_dma = dma_host_enabled(dwc2); @@ -674,75 +751,28 @@ void handle_channel_irq(uint8_t rhport, bool in_isr) { if (tu_bit_test(dwc2->haint, ch_id)) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; + const bool is_period = edpt_is_periodic(hcchar_bm.ep_type); uint32_t hcint = channel->hcint; hcint &= channel->hcintmsk; - dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; - xfer_result_t result = XFER_RESULT_INVALID; // invalid means not DONE - if (is_dma) { } else { - if (hcint & HCINT_XFER_COMPLETE) { - result = XFER_RESULT_SUCCESS; - channel->hcintmsk &= ~HCINT_ACK; - channel_dealloc(dwc2, ch_id); - } else if (hcint & HCINT_STALL) { - result = XFER_RESULT_STALLED; - channel->hcintmsk |= HCINT_CHANNEL_HALTED; - channel->hcchar_bm.disable = 1; - } else if (hcint & (HCINT_NAK | HCINT_XACT_ERR | HCINT_NYET)) { - if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { - // rewind buffer - } else { - if (hcint & HCINT_NAK) { - // NAK received, re-enable channel if request queue is available - TU_ASSERT(request_queue_avail(dwc2, edpt_is_periodic(hcchar_bm.ep_type)), ); - channel->hcchar |= HCCHAR_CHENA; - } - } + xfer_result_t result; - // unmask halted - // disable channel - if (hcint & HCINT_XACT_ERR) { - xfer->err_count++; - channel->hcintmsk |= HCINT_ACK; - }else { - xfer->err_count = 0; - } - } else if (hcint & HCINT_CHANNEL_HALTED) { - if (channel->hcchar_bm.err_multi_count == HCD_XFER_ERROR_MAX) { - - } else { - // Re-initialize Channel (Do ping protocol for HS) - } - } else if (hcint & HCINT_ACK) { - // ACK received, reset error count - xfer->err_count = 0; - channel->hcintmsk &= ~HCINT_ACK; + if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { + result = handle_channel_slave_out(dwc2, ch_id, is_period, hcint); + } else { + result = handle_channel_slave_in(dwc2, ch_id, is_period, hcint); } - // const uint32_t xact_err = hcint & (HCINT_AHB_ERR | HCINT_XACT_ERR | HCINT_BABBLE_ERR | - // HCINT_DATATOGGLE_ERR | HCINT_XCS_XACT_ERR); - // if (xact_err) { - // result = XFER_RESULT_FAILED; - // } - // if (!xact_err && (hcint & HCINT_CHANNEL_HALTED)) { - // // Channel halted without error, this is a response to channel disable - // result = XFER_RESULT_INVALID; - // } - - // Transfer is complete (success, stalled, failed) or channel is disabled - if (result != XFER_RESULT_INVALID || (hcint & HCINT_CHANNEL_HALTED)) { - dwc2->haintmsk &= ~TU_BIT(ch_id); // de-allocate channel - + if (result != XFER_RESULT_INVALID ) { // notify usbh if transfer is complete (skip if channel is disabled) const uint8_t ep_addr = tu_edpt_addr(hcchar_bm.ep_num, hcchar_bm.ep_dir); - if (result != XFER_RESULT_INVALID) { - hcd_event_xfer_complete(hcchar_bm.dev_addr, ep_addr, 0, result, in_isr); - } + hcd_event_xfer_complete(hcchar_bm.dev_addr, ep_addr, xfer->total_bytes, result, in_isr); } } -- cgit v1.3.1 From df55d587dfe8b24d72eb20cd027cd54821d0bf09 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 29 Oct 2024 18:23:56 +0700 Subject: update handle in/out, separate allocated and xfer result to make it easier to manage. Fix channel disable/deallocated. --- src/common/tusb_types.h | 8 +- src/portable/synopsys/dwc2/hcd_dwc2.c | 191 ++++++++++++++++++---------------- 2 files changed, 103 insertions(+), 96 deletions(-) (limited to 'src/portable') diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 3e5aa6818..92cebc42b 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -224,10 +224,10 @@ enum { // USB 2.0 Spec Table 9-7: Test Mode Selectors typedef enum { TUSB_FEATURE_TEST_J = 1, - TUSB_FEATURE_TEST_K, - TUSB_FEATURE_TEST_SE0_NAK, - TUSB_FEATURE_TEST_PACKET, - TUSB_FEATURE_TEST_FORCE_ENABLE, + TUSB_FEATURE_TEST_K = 2, + TUSB_FEATURE_TEST_SE0_NAK = 3, + TUSB_FEATURE_TEST_PACKET = 4, + TUSB_FEATURE_TEST_FORCE_ENABLE = 5, } tusb_feature_test_mode_t; //--------------------------------------------------------------------+ diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 568ce0c1f..5d843537b 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -52,12 +52,6 @@ enum { HCD_XFER_ERROR_MAX = 3 }; -enum { - HCD_XFER_STATE_UNALLOCATED = 0, - HCD_XFER_STATE_ACTIVE = 1, - HCD_XFER_STATE_DONE = 2, -}; - //-------------------------------------------------------------------- // //-------------------------------------------------------------------- @@ -79,7 +73,8 @@ typedef struct { // Additional info for each channel when it is active typedef struct { - volatile uint8_t state; + volatile bool allocated; + uint8_t result; uint8_t err_count; uint8_t* buffer; uint16_t total_bytes; @@ -128,9 +123,9 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) { const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; - if (HCD_XFER_STATE_UNALLOCATED == xfer->state) { + if (!xfer->allocated) { tu_memclr(xfer, sizeof(hcd_xfer_t)); - xfer->state = HCD_XFER_STATE_ACTIVE; + xfer->allocated = true; return ch_id; } } @@ -138,23 +133,20 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) { } TU_ATTR_ALWAYS_INLINE static inline void channel_dealloc(dwc2_regs_t* dwc2, uint8_t ch_id) { - _hcd_data.xfer[ch_id].state = HCD_XFER_STATE_UNALLOCATED; + _hcd_data.xfer[ch_id].allocated = false; dwc2->haintmsk &= ~TU_BIT(ch_id); } TU_ATTR_ALWAYS_INLINE static inline void channel_disable(dwc2_channel_t* channel) { channel->hcintmsk |= HCINT_HALTED; - - uint32_t hcchar = channel->hcchar & ~HCCHAR_CHENA; // skip w1s enabled bit - hcchar |= HCCHAR_CHDIS; - channel->hcchar = hcchar; + channel->hcchar |= HCCHAR_CHDIS | HCCHAR_CHENA; // must set both CHDIS and CHENA } // Find currently enabled channel. Note: EP0 is bidirectional TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_enabled(dwc2_regs_t* dwc2, uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) { const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { - if (_hcd_data.xfer[ch_id].state != HCD_XFER_STATE_UNALLOCATED) { + if (_hcd_data.xfer[ch_id].allocated) { const dwc2_channel_char_t hcchar_bm = dwc2->channel[ch_id].hcchar_bm; if (hcchar_bm.dev_addr == dev_addr && hcchar_bm.ep_num == ep_num && (ep_num == 0 || hcchar_bm.ep_dir == ep_dir)) { return ch_id; @@ -169,6 +161,18 @@ TU_ATTR_ALWAYS_INLINE static inline bool edpt_is_periodic(uint8_t ep_type) { return ep_type == HCCHAR_EPTYPE_INTERRUPT || ep_type == HCCHAR_EPTYPE_ISOCHRONOUS; } +// Allocate a new endpoint +TU_ATTR_ALWAYS_INLINE static inline uint8_t edpt_alloc(void) { + for (uint32_t i = 0; i < CFG_TUH_DWC2_ENDPOINT_MAX; i++) { + hcd_endpoint_t* edpt = &_hcd_data.edpt[i]; + if (edpt->hcchar_bm.enable == 0) { + edpt->hcchar_bm.enable = 1; + return i; + } + } + return TUSB_INDEX_INVALID_8; +} + // Find a endpoint that is opened previously with hcd_edpt_open() // Note: EP0 is bidirectional TU_ATTR_ALWAYS_INLINE static inline uint8_t edpt_find_opened(uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) { @@ -402,38 +406,32 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* hcd_devtree_get_info(dev_addr, &devtree_info); // find a free endpoint - for (uint32_t i = 0; i < CFG_TUH_DWC2_ENDPOINT_MAX; i++) { - hcd_endpoint_t* edpt = &_hcd_data.edpt[i]; - dwc2_channel_char_t* hcchar_bm = &edpt->hcchar_bm; - dwc2_channel_split_t* hcsplt_bm = &edpt->hcsplt_bm; - - if (hcchar_bm->enable == 0) { - hcchar_bm->ep_size = tu_edpt_packet_size(desc_ep); - hcchar_bm->ep_num = tu_edpt_number(desc_ep->bEndpointAddress); - hcchar_bm->ep_dir = tu_edpt_dir(desc_ep->bEndpointAddress); - hcchar_bm->low_speed_dev = (devtree_info.speed == TUSB_SPEED_LOW) ? 1 : 0; - hcchar_bm->ep_type = desc_ep->bmAttributes.xfer; // ep_type matches TUSB_XFER_* - hcchar_bm->err_multi_count = 0; - hcchar_bm->dev_addr = dev_addr; - hcchar_bm->odd_frame = 0; - hcchar_bm->disable = 0; - hcchar_bm->enable = 1; - - hcsplt_bm->hub_port = devtree_info.hub_port; - hcsplt_bm->hub_addr = devtree_info.hub_addr; - hcsplt_bm->xact_pos = 0; - hcsplt_bm->split_compl = 0; - hcsplt_bm->split_en = 0; - - edpt->next_data_toggle = HCTSIZ_PID_DATA0; - - // TODO not support split transaction yet - - return true; - } - } + const uint8_t ep_id = edpt_alloc(); + TU_ASSERT(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); + hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; - return false; + dwc2_channel_char_t* hcchar_bm = &edpt->hcchar_bm; + hcchar_bm->ep_size = tu_edpt_packet_size(desc_ep); + hcchar_bm->ep_num = tu_edpt_number(desc_ep->bEndpointAddress); + hcchar_bm->ep_dir = tu_edpt_dir(desc_ep->bEndpointAddress); + hcchar_bm->low_speed_dev = (devtree_info.speed == TUSB_SPEED_LOW) ? 1 : 0; + hcchar_bm->ep_type = desc_ep->bmAttributes.xfer; // ep_type matches TUSB_XFER_* + hcchar_bm->err_multi_count = 0; + hcchar_bm->dev_addr = dev_addr; + hcchar_bm->odd_frame = 0; + hcchar_bm->disable = 0; + hcchar_bm->enable = 1; + + dwc2_channel_split_t* hcsplt_bm = &edpt->hcsplt_bm; + hcsplt_bm->hub_port = devtree_info.hub_port; + hcsplt_bm->hub_addr = devtree_info.hub_addr; + hcsplt_bm->xact_pos = 0; + hcsplt_bm->split_compl = 0; + hcsplt_bm->split_en = 0; + + edpt->next_data_toggle = HCTSIZ_PID_DATA0; + + return true; } // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked @@ -473,12 +471,21 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * xfer->buffer = buffer; xfer->total_bytes = buflen; + xfer->result = XFER_RESULT_INVALID; - uint32_t hcintmsk = HCINT_NAK | HCINT_XACT_ERR | HCINT_STALL | HCINT_XFER_COMPLETE | HCINT_DATATOGGLE_ERR; if (dma_host_enabled(dwc2)) { channel->hcdma = (uint32_t) buffer; TU_ASSERT(false); // not yet supported } else { + uint32_t hcintmsk = HCINT_NAK | HCINT_XACT_ERR | HCINT_STALL | HCINT_XFER_COMPLETE | HCINT_DATATOGGLE_ERR; + if (ep_dir == TUSB_DIR_IN) { + hcintmsk |= HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR; + } else { + hcintmsk |= HCINT_NYET; + } + channel->hcintmsk = hcintmsk; + dwc2->haintmsk |= TU_BIT(ch_id); + bool const is_period = edpt_is_periodic(hcchar_bm->ep_type); // enable channel for slave mode: @@ -489,8 +496,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * if (ep_dir == TUSB_DIR_IN) { TU_ASSERT(request_queue_avail(dwc2, is_period)); channel->hcchar |= HCCHAR_CHENA; - - hcintmsk |= HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR; } else { channel->hcchar |= HCCHAR_CHENA; if (buflen > 0) { @@ -498,14 +503,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * // And write packet in the interrupt handler dwc2->gintmsk |= (is_period ? GINTSTS_PTX_FIFO_EMPTY : GINTSTS_NPTX_FIFO_EMPTY); } - - hcintmsk |= HCINT_NYET; } } - channel->hcintmsk = hcintmsk; - dwc2->haintmsk |= TU_BIT(ch_id); - return true; } @@ -527,7 +527,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; // disable also require request queue if (request_queue_avail(dwc2, edpt_is_periodic(edpt->hcchar_bm.ep_type))) { - channel->hcchar |= HCCHAR_CHDIS; + channel_disable(channel); } else { TU_BREAKPOINT(); } @@ -669,13 +669,14 @@ TU_ATTR_ALWAYS_INLINE static inline void handle_hprt_irq(uint8_t rhport, bool in dwc2->hprt = hprt; // clear interrupt } -xfer_result_t handle_channel_slave_in(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { +bool handle_channel_slave_in(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; - xfer_result_t result = XFER_RESULT_INVALID; + + bool is_done = false; if (hcint & HCINT_XFER_COMPLETE) { - result = XFER_RESULT_SUCCESS; + xfer->result = XFER_RESULT_SUCCESS; channel_disable(channel); channel->hcintmsk &= ~HCINT_ACK; } else if (hcint & (HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_STALL)) { @@ -686,8 +687,11 @@ xfer_result_t handle_channel_slave_in(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_ } } else if (hcint & HCINT_HALTED) { channel->hcintmsk &= ~HCINT_HALTED; - if (channel->hcchar_bm.err_multi_count == HCD_XFER_ERROR_MAX) { - channel_dealloc(dwc2, ch_id); + if (xfer->result != XFER_RESULT_INVALID) { + is_done = true; + } else if (channel->hcchar_bm.err_multi_count == HCD_XFER_ERROR_MAX) { + xfer->result = XFER_RESULT_FAILED; + is_done = true; } else { // Re-initialize Channel } @@ -698,25 +702,26 @@ xfer_result_t handle_channel_slave_in(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_ xfer->err_count = 0; } else if (hcint & HCINT_NAK) { // NAK received, re-enable channel if request queue is available - TU_ASSERT(request_queue_avail(dwc2, is_period), XFER_RESULT_INVALID); + TU_ASSERT(request_queue_avail(dwc2, is_period)); channel->hcchar |= HCCHAR_CHENA; } - return result; + return is_done; } -xfer_result_t handle_channel_slave_out(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { +bool handle_channel_slave_out(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { (void) is_period; hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; - xfer_result_t result = XFER_RESULT_INVALID; + + bool is_notify = false; if (hcint & HCINT_XFER_COMPLETE) { - result = XFER_RESULT_SUCCESS; + is_notify = true; + xfer->result = XFER_RESULT_SUCCESS; channel->hcintmsk &= ~HCINT_ACK; - channel_dealloc(dwc2, ch_id); } else if (hcint & HCINT_STALL) { - xfer->state = HCD_XFER_STATE_DONE; + xfer->result = XFER_RESULT_STALLED; channel_disable(channel); } else if (hcint & (HCINT_NAK | HCINT_XACT_ERR | HCINT_NYET)) { channel_disable(channel); @@ -728,9 +733,11 @@ xfer_result_t handle_channel_slave_out(dwc2_regs_t* dwc2, uint8_t ch_id, bool is } } else if (hcint & HCINT_HALTED) { channel->hcintmsk &= ~HCINT_HALTED; - if (xfer->state == HCD_XFER_STATE_DONE || channel->hcchar_bm.err_multi_count == HCD_XFER_ERROR_MAX) { - result = (xfer->state == HCD_XFER_STATE_DONE ? XFER_RESULT_STALLED : XFER_RESULT_FAILED); - channel_dealloc(dwc2, ch_id); + if (xfer->result != XFER_RESULT_INVALID) { + is_notify = true; + } else if (channel->hcchar_bm.err_multi_count == HCD_XFER_ERROR_MAX) { + xfer->result = XFER_RESULT_FAILED; + is_notify = true; } else { // Re-initialize Channel (Do ping protocol for HS) } @@ -739,7 +746,7 @@ xfer_result_t handle_channel_slave_out(dwc2_regs_t* dwc2, uint8_t ch_id, bool is channel->hcintmsk &= ~HCINT_ACK; } - return result; + return is_notify; } void handle_channel_irq(uint8_t rhport, bool in_isr) { @@ -760,19 +767,20 @@ void handle_channel_irq(uint8_t rhport, bool in_isr) { if (is_dma) { } else { - xfer_result_t result; + bool is_done; if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { - result = handle_channel_slave_out(dwc2, ch_id, is_period, hcint); + is_done = handle_channel_slave_out(dwc2, ch_id, is_period, hcint); } else { - result = handle_channel_slave_in(dwc2, ch_id, is_period, hcint); + is_done = handle_channel_slave_in(dwc2, ch_id, is_period, hcint); } - // Transfer is complete (success, stalled, failed) or channel is disabled - if (result != XFER_RESULT_INVALID ) { - // notify usbh if transfer is complete (skip if channel is disabled) + // notify usbh if done + if (is_done) { const uint8_t ep_addr = tu_edpt_addr(hcchar_bm.ep_num, hcchar_bm.ep_dir); - hcd_event_xfer_complete(hcchar_bm.dev_addr, ep_addr, xfer->total_bytes, result, in_isr); + hcd_event_xfer_complete(hcchar_bm.dev_addr, ep_addr, xfer->total_bytes, xfer->result, in_isr); + + channel_dealloc(dwc2, ch_id); } } @@ -789,7 +797,7 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; - if (xfer->state == HCD_XFER_STATE_ACTIVE) { + if (xfer->allocated) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; const dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { @@ -846,6 +854,18 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { handle_hprt_irq(rhport, in_isr); } + // RxFIFO non-empty interrupt handling, must be handled before HCINT + if (int_status & GINTSTS_RXFLVL) { + // RXFLVL bit is read-only + dwc2->gintmsk &= ~GINTMSK_RXFLVLM; // disable RXFLVL interrupt while reading + + do { + handle_rxflvl_irq(rhport); // read all packets + } while(dwc2->gintsts & GINTSTS_RXFLVL); + + dwc2->gintmsk |= GINTMSK_RXFLVLM; + } + if (int_status & GINTSTS_HCINT) { // Host Channel interrupt: source is cleared in HCINT register handle_channel_irq(rhport, in_isr); @@ -859,19 +879,6 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { dwc2->gintmsk &= ~GINTSTS_NPTX_FIFO_EMPTY; } } - - // RxFIFO non-empty interrupt handling. - if (int_status & GINTSTS_RXFLVL) { - // RXFLVL bit is read-only - dwc2->gintmsk &= ~GINTMSK_RXFLVLM; // disable RXFLVL interrupt while reading - - do { - handle_rxflvl_irq(rhport); // read all packets - } while(dwc2->gintsts & GINTSTS_RXFLVL); - - dwc2->gintmsk |= GINTMSK_RXFLVLM; - } - } #endif -- cgit v1.3.1 From 074811c2514161972c75337601b915f21828ba91 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 29 Oct 2024 19:08:45 +0700 Subject: refactor channel_send_in_token(), support IN token for multiple transaction per transfer --- src/portable/synopsys/dwc2/hcd_dwc2.c | 58 ++++++++++++++++++++--------------- 1 file changed, 33 insertions(+), 25 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 5d843537b..4456955db 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -110,14 +110,6 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc return CFG_TUH_DWC2_DMA && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; } -TU_ATTR_ALWAYS_INLINE static inline uint8_t request_queue_avail(const dwc2_regs_t* dwc2, bool is_period) { - if (is_period) { - return dwc2->hptxsts_bm.req_queue_available; - } else { - return dwc2->hnptxsts_bm.req_queue_available; - } -} - // Find a free channel for new transfer TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) { const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); @@ -138,10 +130,27 @@ TU_ATTR_ALWAYS_INLINE static inline void channel_dealloc(dwc2_regs_t* dwc2, uint } TU_ATTR_ALWAYS_INLINE static inline void channel_disable(dwc2_channel_t* channel) { + // disable also require request queue + // request_queue_avail(); channel->hcintmsk |= HCINT_HALTED; channel->hcchar |= HCCHAR_CHDIS | HCCHAR_CHENA; // must set both CHDIS and CHENA } +TU_ATTR_ALWAYS_INLINE static inline uint8_t request_queue_avail(const dwc2_regs_t* dwc2, bool is_period) { + if (is_period) { + return dwc2->hptxsts_bm.req_queue_available; + } else { + return dwc2->hnptxsts_bm.req_queue_available; + } +} + +// attempt to send IN token to receive data +TU_ATTR_ALWAYS_INLINE static inline bool channel_send_in_token(const dwc2_regs_t* dwc2, dwc2_channel_t* channel, bool is_period) { + TU_ASSERT(request_queue_avail(dwc2, is_period)); + channel->hcchar_bm.enable = 1; + return true; +} + // Find currently enabled channel. Note: EP0 is bidirectional TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_enabled(dwc2_regs_t* dwc2, uint8_t dev_addr, uint8_t ep_num, uint8_t ep_dir) { const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); @@ -494,8 +503,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * // IN Token. If we got NAK, we have to re-enable the channel again in the interrupt. Due to the way usbh stack only // call hcd_edpt_xfer() once, we will need to manage de-allocate/re-allocate IN channel dynamically. if (ep_dir == TUSB_DIR_IN) { - TU_ASSERT(request_queue_avail(dwc2, is_period)); - channel->hcchar |= HCCHAR_CHENA; + channel_send_in_token(dwc2, channel, is_period); } else { channel->hcchar |= HCCHAR_CHENA; if (buflen > 0) { @@ -517,7 +525,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { const uint8_t ep_dir = tu_edpt_dir(ep_addr); const uint8_t ep_id = edpt_find_opened(dev_addr, ep_num, ep_dir); TU_VERIFY(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); - hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; + //hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; // hcd_int_disable(rhport); @@ -525,12 +533,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { const uint8_t ch_id = channel_find_enabled(dwc2, dev_addr, ep_num, ep_dir); if (ch_id < 16) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; - // disable also require request queue - if (request_queue_avail(dwc2, edpt_is_periodic(edpt->hcchar_bm.ep_type))) { - channel_disable(channel); - } else { - TU_BREAKPOINT(); - } + channel_disable(channel); } // hcd_int_enable(rhport); @@ -578,9 +581,17 @@ static void handle_rxflvl_irq(uint8_t rhport) { dfifo_read_packet(dwc2, xfer->buffer, byte_count); xfer->buffer += byte_count; - // short packet, minus remaining bytes (xfer_size) - if (byte_count < channel->hctsiz_bm.xfer_size) { - xfer->total_bytes -= channel->hctsiz_bm.xfer_size; + if (byte_count < channel->hcchar_bm.ep_size) { + // short packet, minus remaining bytes + const uint16_t remain_bytes = (uint16_t) channel->hctsiz_bm.xfer_size; + xfer->total_bytes -= remain_bytes; + } else { + // still more packet to send + const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + if (remain_packets) { + bool const is_period = edpt_is_periodic(channel->hcchar_bm.ep_type); + channel_send_in_token(dwc2, channel, is_period); + } } break; @@ -702,8 +713,7 @@ bool handle_channel_slave_in(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, u xfer->err_count = 0; } else if (hcint & HCINT_NAK) { // NAK received, re-enable channel if request queue is available - TU_ASSERT(request_queue_avail(dwc2, is_period)); - channel->hcchar |= HCCHAR_CHENA; + channel_send_in_token(dwc2, channel, is_period); } return is_done; @@ -775,11 +785,9 @@ void handle_channel_irq(uint8_t rhport, bool in_isr) { is_done = handle_channel_slave_in(dwc2, ch_id, is_period, hcint); } - // notify usbh if done if (is_done) { const uint8_t ep_addr = tu_edpt_addr(hcchar_bm.ep_num, hcchar_bm.ep_dir); hcd_event_xfer_complete(hcchar_bm.dev_addr, ep_addr, xfer->total_bytes, xfer->result, in_isr); - channel_dealloc(dwc2, ch_id); } } @@ -803,7 +811,7 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { const uint16_t remain_packets = channel->hctsiz_bm.packet_count; for (uint16_t i = 0; i < remain_packets; i++) { - const uint16_t remain_bytes = channel->hctsiz_bm.xfer_size; + const uint16_t remain_bytes = (uint16_t) channel->hctsiz_bm.xfer_size; const uint16_t xact_bytes = tu_min16(remain_bytes, hcchar_bm.ep_size); // check if there is enough space in FIFO and RequestQueue. -- cgit v1.3.1 From 616b5770f279fee1aeec7c94258124762ad0aa65 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 29 Oct 2024 21:54:21 +0700 Subject: fix pid token calculation, implement hcd_edpt_clear_stall(). msc explorer example read work, but write10 still wip --- src/portable/synopsys/dwc2/dwc2_type.h | 11 ++++--- src/portable/synopsys/dwc2/hcd_dwc2.c | 58 +++++++++++++++++++++++----------- 2 files changed, 47 insertions(+), 22 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index d2ab1e94d..342a4cb2d 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -139,10 +139,13 @@ enum { }; enum { - HCTSIZ_PID_DATA0 = 0, - HCTSIZ_PID_DATA2 = 1, - HCTSIZ_PID_DATA1 = 2, - HCTSIZ_PID_SETUP = 3, + HCTSIZ_PID_DATA0 = 0, // 00b + HCTSIZ_PID_DATA2 = 1, // 01b + HCTSIZ_PID_DATA1 = 2, // 10b + HCTSIZ_PID_SETUP = 3, // 11b +}; +enum { + HCTSIZ_PID_MDATA = 3, }; enum { diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 4456955db..d64a95393 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -67,13 +67,14 @@ typedef struct { dwc2_channel_split_t hcsplt_bm; }; - uint8_t next_data_toggle; + uint8_t next_pid; // uint8_t resv[3]; } hcd_endpoint_t; // Additional info for each channel when it is active typedef struct { volatile bool allocated; + uint8_t ep_id; // associated edpt uint8_t result; uint8_t err_count; uint8_t* buffer; @@ -125,7 +126,8 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) { } TU_ATTR_ALWAYS_INLINE static inline void channel_dealloc(dwc2_regs_t* dwc2, uint8_t ch_id) { - _hcd_data.xfer[ch_id].allocated = false; + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + xfer->allocated = false; dwc2->haintmsk &= ~TU_BIT(ch_id); } @@ -195,6 +197,14 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t edpt_find_opened(uint8_t dev_addr, u return TUSB_INDEX_INVALID_8; } +TU_ATTR_ALWAYS_INLINE static inline uint8_t cal_next_pid(uint8_t pid, uint8_t packet_count) { + if (packet_count & 0x01) { + return pid ^ 0x02; // toggle DATA0 and DATA1 + } else { + return pid; + } +} + //-------------------------------------------------------------------- // //-------------------------------------------------------------------- @@ -322,7 +332,7 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // force host mode and wait for mode switch dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD; - while( (dwc2->gintsts & GINTSTS_CMOD) != GINTSTS_CMODE_HOST) {} + while ((dwc2->gintsts & GINTSTS_CMOD) != GINTSTS_CMODE_HOST) {} // configure fixed-allocated fifo scheme dfifo_host_init(rhport); @@ -438,7 +448,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* hcsplt_bm->split_compl = 0; hcsplt_bm->split_en = 0; - edpt->next_data_toggle = HCTSIZ_PID_DATA0; + edpt->next_pid = HCTSIZ_PID_DATA0; return true; } @@ -448,6 +458,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * dwc2_regs_t* dwc2 = DWC2_REG(rhport); const uint8_t ep_num = tu_edpt_number(ep_addr); const uint8_t ep_dir = tu_edpt_dir(ep_addr); + uint8_t ep_id = edpt_find_opened(dev_addr, ep_num, ep_dir); TU_ASSERT(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; @@ -456,19 +467,21 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * uint8_t ch_id = channel_alloc(dwc2); TU_ASSERT(ch_id < 16); // all channel are in used hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + xfer->ep_id = ep_id; + dwc2_channel_t* channel = &dwc2->channel[ch_id]; uint16_t packet_count = tu_div_ceil(buflen, hcchar_bm->ep_size); if (packet_count == 0) { packet_count = 1; // zero length packet still count as 1 } - channel->hctsiz = (edpt->next_data_toggle << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | buflen; + channel->hctsiz = (edpt->next_pid << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | buflen; - // Control transfer always start with DATA1 for data and status stage. May has issue with ZLP - if (edpt->next_data_toggle == HCTSIZ_PID_DATA0 || ep_num == 0) { - edpt->next_data_toggle = HCTSIZ_PID_DATA1; + // pre-calculate next PID based on packet count, adjusted in transfer complete interrupt if short packet + if (ep_num == 0) { + edpt->next_pid = HCTSIZ_PID_DATA1; // control data and status stage always start with DATA1 } else { - edpt->next_data_toggle = HCTSIZ_PID_DATA0; + edpt->next_pid = cal_next_pid(edpt->next_pid, packet_count); } // TODO support split transaction @@ -546,7 +559,7 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, const uint8_t setup_packet uint8_t ep_id = edpt_find_opened(dev_addr, 0, TUSB_DIR_OUT); TU_ASSERT(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); // no opened endpoint hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; - edpt->next_data_toggle = HCTSIZ_PID_SETUP; + edpt->next_pid = HCTSIZ_PID_SETUP; return hcd_edpt_xfer(rhport, dev_addr, 0, (uint8_t*)(uintptr_t) setup_packet, 8); } @@ -554,10 +567,15 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, const uint8_t setup_packet // clear stall, data toggle is also reset to DATA0 bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { (void) rhport; - (void) dev_addr; - (void) ep_addr; + const uint8_t ep_num = tu_edpt_number(ep_addr); + const uint8_t ep_dir = tu_edpt_dir(ep_addr); + const uint8_t ep_id = edpt_find_opened(dev_addr, ep_num, ep_dir); + TU_VERIFY(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); + hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; + + edpt->next_pid = HCTSIZ_PID_DATA0; - return false; + return true; } //-------------------------------------------------------------------- @@ -581,24 +599,28 @@ static void handle_rxflvl_irq(uint8_t rhport) { dfifo_read_packet(dwc2, xfer->buffer, byte_count); xfer->buffer += byte_count; + const uint16_t remain_bytes = (uint16_t) channel->hctsiz_bm.xfer_size; + const uint16_t remain_packets = channel->hctsiz_bm.packet_count; if (byte_count < channel->hcchar_bm.ep_size) { // short packet, minus remaining bytes - const uint16_t remain_bytes = (uint16_t) channel->hctsiz_bm.xfer_size; xfer->total_bytes -= remain_bytes; + + // update PID since we got short packet + TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX,); + hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; // update PID + edpt->next_pid = cal_next_pid(edpt->next_pid, remain_packets); } else { - // still more packet to send - const uint16_t remain_packets = channel->hctsiz_bm.packet_count; if (remain_packets) { + // still more packet to send bool const is_period = edpt_is_periodic(channel->hcchar_bm.ep_type); channel_send_in_token(dwc2, channel, is_period); } } - break; } case GRXSTS_PKTSTS_RX_COMPLETE: - // In transfer complete: After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed + // In transfer complete: After this entry is popped from the rx FIFO, dwc2 asserts a Transfer Completed // interrupt --> handle_channel_irq() break; -- cgit v1.3.1 From 3c1cb0e08f650931f95647400c1cf1e3abb03486 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 29 Oct 2024 22:48:58 +0700 Subject: correct the fifo_available comparison (words not byte) --- src/portable/synopsys/dwc2/dcd_dwc2.c | 10 ++++----- src/portable/synopsys/dwc2/hcd_dwc2.c | 42 +++++++++++++++++------------------ 2 files changed, 26 insertions(+), 26 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index bcfdb546b..9b5c476e4 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -853,21 +853,21 @@ static void handle_epin_irq(uint8_t rhport) { const uint16_t remain_bytes = epin->dieptsiz_bm.xfer_size; // Packet can not be larger than ep max size - const uint16_t packet_size = tu_min16(remain_bytes, xfer->max_size); + const uint16_t xact_bytes = tu_min16(remain_bytes, xfer->max_size); // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current // EP has to be checked if the buffer can take another WHOLE packet - if (packet_size > ((epin->dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) { + if (xact_bytes > ((epin->dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) { break; } // Push packet to Tx-FIFO if (xfer->ff) { volatile uint32_t* tx_fifo = dwc2->fifo[n]; - tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, packet_size); + tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, xact_bytes); } else { - dfifo_write_packet(dwc2, n, xfer->buffer, packet_size); - xfer->buffer += packet_size; + dfifo_write_packet(dwc2, n, xfer->buffer, xact_bytes); + xfer->buffer += xact_bytes; } } diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index d64a95393..226497b78 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -463,6 +463,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * TU_ASSERT(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; dwc2_channel_char_t* hcchar_bm = &edpt->hcchar_bm; + bool const is_period = edpt_is_periodic(hcchar_bm->ep_type); uint8_t ch_id = channel_alloc(dwc2); TU_ASSERT(ch_id < 16); // all channel are in used @@ -487,7 +488,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * // TODO support split transaction channel->hcsplt = edpt->hcsplt; - hcchar_bm->odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame + if (is_period) { + hcchar_bm->odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame + } hcchar_bm->ep_dir = ep_dir; // control endpoint can switch direction channel->hcchar = (edpt->hcchar & ~HCCHAR_CHENA); // restore hcchar but don't enable yet @@ -508,8 +511,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * channel->hcintmsk = hcintmsk; dwc2->haintmsk |= TU_BIT(ch_id); - bool const is_period = edpt_is_periodic(hcchar_bm->ep_type); - // enable channel for slave mode: // - OUT: it will enable corresponding FIFO channel // - IN : it will write an IN request to the Non-periodic Request Queue, this will have dwc2 trying to send @@ -771,7 +772,8 @@ bool handle_channel_slave_out(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, xfer->result = XFER_RESULT_FAILED; is_notify = true; } else { - // Re-initialize Channel (Do ping protocol for HS) + // Got here due to NAK probably, retry channel (Do ping protocol for HS) + } } else if (hcint & HCINT_ACK) { xfer->err_count = 0; @@ -827,24 +829,22 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; - if (xfer->allocated) { - dwc2_channel_t* channel = &dwc2->channel[ch_id]; - const dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; - if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { - const uint16_t remain_packets = channel->hctsiz_bm.packet_count; - for (uint16_t i = 0; i < remain_packets; i++) { - const uint16_t remain_bytes = (uint16_t) channel->hctsiz_bm.xfer_size; - const uint16_t xact_bytes = tu_min16(remain_bytes, hcchar_bm.ep_size); - - // check if there is enough space in FIFO and RequestQueue. - // Packet's last word written to FIFO will trigger a request queue - if ((xact_bytes > txsts_bm->fifo_available) && (txsts_bm->req_queue_available > 0)) { - return true; - } - - dfifo_write_packet(dwc2, ch_id, xfer->buffer, xact_bytes); - xfer->buffer += xact_bytes; + dwc2_channel_t* channel = &dwc2->channel[ch_id]; + const dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; + if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { + const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + for (uint16_t i = 0; i < remain_packets; i++) { + const uint16_t remain_bytes = (uint16_t) channel->hctsiz_bm.xfer_size; + const uint16_t xact_bytes = tu_min16(remain_bytes, hcchar_bm.ep_size); + + // check if there is enough space in FIFO and RequestQueue. + // Packet's last word written to FIFO will trigger a request queue + if ((xact_bytes > (txsts_bm->fifo_available << 2)) && (txsts_bm->req_queue_available > 0)) { + return true; } + + dfifo_write_packet(dwc2, ch_id, xfer->buffer, xact_bytes); + xfer->buffer += xact_bytes; } } } -- cgit v1.3.1 From 80d8157048170bcf2bbb77499b1496ea3c79c193 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 30 Oct 2024 18:11:41 +0700 Subject: handle out nak slave -> halted -> retry transfer --- src/portable/synopsys/dwc2/hcd_dwc2.c | 217 +++++++++++++++++++++------------- 1 file changed, 133 insertions(+), 84 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 226497b78..e80f8d0ba 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -75,10 +75,13 @@ typedef struct { typedef struct { volatile bool allocated; uint8_t ep_id; // associated edpt - uint8_t result; uint8_t err_count; - uint8_t* buffer; - uint16_t total_bytes; + uint8_t result; + uint16_t xferred_bytes; // bytes that accumulate transferred though USB bus for the whole hcd_edpt_xfer(), which can + // be composed of multiple channel_start_xfer() (retry with NAK/NYET) + uint8_t* buf_start; + uint16_t buf_len; + uint16_t out_fifo_bytes; // bytes written to TX FIFO (may not be transferred on USB bus). } hcd_xfer_t; typedef struct { @@ -125,30 +128,30 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) { return TUSB_INDEX_INVALID_8; } +TU_ATTR_ALWAYS_INLINE static inline uint8_t req_queue_avail(const dwc2_regs_t* dwc2, bool is_period) { + if (is_period) { + return dwc2->hptxsts_bm.req_queue_available; + } else { + return dwc2->hnptxsts_bm.req_queue_available; + } +} + TU_ATTR_ALWAYS_INLINE static inline void channel_dealloc(dwc2_regs_t* dwc2, uint8_t ch_id) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; xfer->allocated = false; dwc2->haintmsk &= ~TU_BIT(ch_id); } -TU_ATTR_ALWAYS_INLINE static inline void channel_disable(dwc2_channel_t* channel) { +TU_ATTR_ALWAYS_INLINE static inline void channel_disable(const dwc2_regs_t* dwc2, dwc2_channel_t* channel, bool is_period) { // disable also require request queue - // request_queue_avail(); + TU_ASSERT(req_queue_avail(dwc2, is_period), ); channel->hcintmsk |= HCINT_HALTED; channel->hcchar |= HCCHAR_CHDIS | HCCHAR_CHENA; // must set both CHDIS and CHENA } -TU_ATTR_ALWAYS_INLINE static inline uint8_t request_queue_avail(const dwc2_regs_t* dwc2, bool is_period) { - if (is_period) { - return dwc2->hptxsts_bm.req_queue_available; - } else { - return dwc2->hnptxsts_bm.req_queue_available; - } -} - // attempt to send IN token to receive data TU_ATTR_ALWAYS_INLINE static inline bool channel_send_in_token(const dwc2_regs_t* dwc2, dwc2_channel_t* channel, bool is_period) { - TU_ASSERT(request_queue_avail(dwc2, is_period)); + TU_ASSERT(req_queue_avail(dwc2, is_period)); channel->hcchar_bm.enable = 1; return true; } @@ -197,6 +200,14 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t edpt_find_opened(uint8_t dev_addr, u return TUSB_INDEX_INVALID_8; } +TU_ATTR_ALWAYS_INLINE static inline uint16_t cal_packet_count(uint16_t len, uint16_t ep_size) { + if (len == 0) { + return 1; + } else { + return tu_div_ceil(len, ep_size); + } +} + TU_ATTR_ALWAYS_INLINE static inline uint8_t cal_next_pid(uint8_t pid, uint8_t packet_count) { if (packet_count & 0x01) { return pid ^ 0x02; // toggle DATA0 and DATA1 @@ -453,57 +464,42 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* return true; } -// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked -bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - const uint8_t ep_num = tu_edpt_number(ep_addr); - const uint8_t ep_dir = tu_edpt_dir(ep_addr); - - uint8_t ep_id = edpt_find_opened(dev_addr, ep_num, ep_dir); - TU_ASSERT(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); - hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; +bool channel_start_xfer(dwc2_regs_t* dwc2, uint8_t ch_id) { + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; dwc2_channel_char_t* hcchar_bm = &edpt->hcchar_bm; + dwc2_channel_t* channel = &dwc2->channel[ch_id]; bool const is_period = edpt_is_periodic(hcchar_bm->ep_type); - uint8_t ch_id = channel_alloc(dwc2); - TU_ASSERT(ch_id < 16); // all channel are in used - hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; - xfer->ep_id = ep_id; + // clear previous state + xfer->out_fifo_bytes = 0; - dwc2_channel_t* channel = &dwc2->channel[ch_id]; - - uint16_t packet_count = tu_div_ceil(buflen, hcchar_bm->ep_size); - if (packet_count == 0) { - packet_count = 1; // zero length packet still count as 1 + // hchar: restore but don't enable yet + if (is_period) { + hcchar_bm->odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame } - channel->hctsiz = (edpt->next_pid << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | buflen; + channel->hcchar = (edpt->hcchar & ~HCCHAR_CHENA); + + // hctsiz: zero length packet still count as 1 + const uint16_t packet_count = cal_packet_count(xfer->buf_len, hcchar_bm->ep_size); + channel->hctsiz = (edpt->next_pid << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | xfer->buf_len; // pre-calculate next PID based on packet count, adjusted in transfer complete interrupt if short packet - if (ep_num == 0) { + if (hcchar_bm->ep_num == 0) { edpt->next_pid = HCTSIZ_PID_DATA1; // control data and status stage always start with DATA1 } else { edpt->next_pid = cal_next_pid(edpt->next_pid, packet_count); } - // TODO support split transaction + // split: TODO support later channel->hcsplt = edpt->hcsplt; - if (is_period) { - hcchar_bm->odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame - } - hcchar_bm->ep_dir = ep_dir; // control endpoint can switch direction - channel->hcchar = (edpt->hcchar & ~HCCHAR_CHENA); // restore hcchar but don't enable yet - - xfer->buffer = buffer; - xfer->total_bytes = buflen; - xfer->result = XFER_RESULT_INVALID; - if (dma_host_enabled(dwc2)) { - channel->hcdma = (uint32_t) buffer; + // channel->hcdma = (uint32_t) buffer; TU_ASSERT(false); // not yet supported } else { uint32_t hcintmsk = HCINT_NAK | HCINT_XACT_ERR | HCINT_STALL | HCINT_XFER_COMPLETE | HCINT_DATATOGGLE_ERR; - if (ep_dir == TUSB_DIR_IN) { + if (hcchar_bm->ep_dir == TUSB_DIR_IN) { hcintmsk |= HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR; } else { hcintmsk |= HCINT_NYET; @@ -516,11 +512,11 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * // - IN : it will write an IN request to the Non-periodic Request Queue, this will have dwc2 trying to send // IN Token. If we got NAK, we have to re-enable the channel again in the interrupt. Due to the way usbh stack only // call hcd_edpt_xfer() once, we will need to manage de-allocate/re-allocate IN channel dynamically. - if (ep_dir == TUSB_DIR_IN) { + if (hcchar_bm->ep_dir == TUSB_DIR_IN) { channel_send_in_token(dwc2, channel, is_period); } else { - channel->hcchar |= HCCHAR_CHENA; - if (buflen > 0) { + channel->hcchar_bm.enable = 1; + if (xfer->buf_len > 0) { // To prevent conflict with other channel, we will enable periodic/non-periodic FIFO empty interrupt accordingly // And write packet in the interrupt handler dwc2->gintmsk |= (is_period ? GINTSTS_PTX_FIFO_EMPTY : GINTSTS_NPTX_FIFO_EMPTY); @@ -531,6 +527,29 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * return true; } +// Submit a transfer, when complete hcd_event_xfer_complete() must be invoked +bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + const uint8_t ep_num = tu_edpt_number(ep_addr); + const uint8_t ep_dir = tu_edpt_dir(ep_addr); + + uint8_t ep_id = edpt_find_opened(dev_addr, ep_num, ep_dir); + TU_ASSERT(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); + hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; + + uint8_t ch_id = channel_alloc(dwc2); + TU_ASSERT(ch_id < 16); // all channel are in used + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + xfer->ep_id = ep_id; + + edpt->hcchar_bm.ep_dir = ep_dir; // control endpoint can switch direction + xfer->buf_start = buffer; + xfer->buf_len = buflen; + xfer->result = XFER_RESULT_INVALID; + + return channel_start_xfer(dwc2, ch_id); +} + // Abort a queued transfer. Note: it can only abort transfer that has not been started // Return true if a queued transfer is aborted, false if there is no transfer to abort bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { @@ -547,7 +566,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { const uint8_t ch_id = channel_find_enabled(dwc2, dev_addr, ep_num, ep_dir); if (ch_id < 16) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; - channel_disable(channel); + channel_disable(dwc2, channel, edpt_is_periodic(channel->hcchar_bm.ep_type)); } // hcd_int_enable(rhport); @@ -597,16 +616,16 @@ static void handle_rxflvl_irq(uint8_t rhport) { const uint16_t byte_count = grxstsp_bm.byte_count; hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; - dfifo_read_packet(dwc2, xfer->buffer, byte_count); - xfer->buffer += byte_count; + dfifo_read_packet(dwc2, xfer->buf_start + xfer->xferred_bytes, byte_count); + xfer->xferred_bytes += byte_count; const uint16_t remain_bytes = (uint16_t) channel->hctsiz_bm.xfer_size; const uint16_t remain_packets = channel->hctsiz_bm.packet_count; if (byte_count < channel->hcchar_bm.ep_size) { // short packet, minus remaining bytes - xfer->total_bytes -= remain_bytes; + xfer->xferred_bytes -= remain_bytes; - // update PID since we got short packet + // update PID based on remain packets count TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX,); hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; // update PID edpt->next_pid = cal_next_pid(edpt->next_pid, remain_packets); @@ -703,7 +722,7 @@ TU_ATTR_ALWAYS_INLINE static inline void handle_hprt_irq(uint8_t rhport, bool in dwc2->hprt = hprt; // clear interrupt } -bool handle_channel_slave_in(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { +bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; @@ -711,10 +730,10 @@ bool handle_channel_slave_in(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, u if (hcint & HCINT_XFER_COMPLETE) { xfer->result = XFER_RESULT_SUCCESS; - channel_disable(channel); + channel_disable(dwc2, channel, is_period); channel->hcintmsk &= ~HCINT_ACK; } else if (hcint & (HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_STALL)) { - channel_disable(channel); + channel_disable(dwc2, channel, is_period); if (hcint & HCINT_XACT_ERR) { xfer->err_count++; channel->hcintmsk |= HCINT_ACK; @@ -742,45 +761,73 @@ bool handle_channel_slave_in(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, u return is_done; } -bool handle_channel_slave_out(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { +bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { (void) is_period; hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; - bool is_notify = false; + bool is_done = false; if (hcint & HCINT_XFER_COMPLETE) { - is_notify = true; + is_done = true; xfer->result = XFER_RESULT_SUCCESS; channel->hcintmsk &= ~HCINT_ACK; + TU_LOG1("xferred = %u, remain = %u, out_fifo = %u\n", + xfer->xferred_bytes, xfer->buf_len, xfer->out_fifo_bytes); } else if (hcint & HCINT_STALL) { xfer->result = XFER_RESULT_STALLED; - channel_disable(channel); + channel_disable(dwc2, channel, is_period); } else if (hcint & (HCINT_NAK | HCINT_XACT_ERR | HCINT_NYET)) { - channel_disable(channel); + TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); + hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; + edpt->next_pid = channel->hctsiz_bm.pid; // save PID + + /* Rewind buffer pointer and total bytes to retry later + * Must use the hctsiz.pktcnt field to determine how much data has been transferred. This field reflects the number + * of packets that have been transferred via the USB. This is always an integral number of packets if the transfer + * was halted before its normal completion. (Can't use the hctsiz.xfersize field because that reflects the number of + * bytes transferred via the AHB, not the USB). + */ + const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + const uint16_t total_packets = cal_packet_count(xfer->buf_len, channel->hcchar_bm.ep_size); + const uint16_t actual_bytes = (total_packets - remain_packets) * channel->hcchar_bm.ep_size; + xfer->xferred_bytes += actual_bytes; + xfer->buf_start += actual_bytes; + xfer->buf_len -= actual_bytes; + xfer->out_fifo_bytes = 0; + TU_LOG1("xferred = %u, remain = %u, out_fifo = %u, this actual = %u\n", + xfer->xferred_bytes, xfer->buf_len, xfer->out_fifo_bytes, actual_bytes); + + channel_disable(dwc2, channel, is_period); if (hcint & HCINT_XACT_ERR) { xfer->err_count++; channel->hcintmsk |= HCINT_ACK; } else { + // NAK/NYET disable channel to flush all posted request and try again xfer->err_count = 0; } } else if (hcint & HCINT_HALTED) { channel->hcintmsk &= ~HCINT_HALTED; if (xfer->result != XFER_RESULT_INVALID) { - is_notify = true; + is_done = true; } else if (channel->hcchar_bm.err_multi_count == HCD_XFER_ERROR_MAX) { xfer->result = XFER_RESULT_FAILED; - is_notify = true; + is_done = true; } else { - // Got here due to NAK probably, retry channel (Do ping protocol for HS) - + // Got here due to NAK or NYET (need to do PING for HS) -> Retry transfer + TU_ASSERT(channel_start_xfer(dwc2, ch_id)); } } else if (hcint & HCINT_ACK) { xfer->err_count = 0; channel->hcintmsk &= ~HCINT_ACK; } - return is_notify; + if (is_done) { + xfer->xferred_bytes += xfer->out_fifo_bytes; + xfer->out_fifo_bytes = 0; + } + + return is_done; } void handle_channel_irq(uint8_t rhport, bool in_isr) { @@ -798,25 +845,26 @@ void handle_channel_irq(uint8_t rhport, bool in_isr) { uint32_t hcint = channel->hcint; hcint &= channel->hcintmsk; - if (is_dma) { + channel->hcint = hcint; // clear all interrupt flags + if (is_dma) { + // NOTE For DMA This is flow for core with OUT NAK enhancement from v2.71a } else { bool is_done; if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { - is_done = handle_channel_slave_out(dwc2, ch_id, is_period, hcint); + is_done = handle_channel_out_slave(dwc2, ch_id, is_period, hcint); } else { - is_done = handle_channel_slave_in(dwc2, ch_id, is_period, hcint); + is_done = handle_channel_in_slave(dwc2, ch_id, is_period, hcint); } if (is_done) { const uint8_t ep_addr = tu_edpt_addr(hcchar_bm.ep_num, hcchar_bm.ep_dir); - hcd_event_xfer_complete(hcchar_bm.dev_addr, ep_addr, xfer->total_bytes, xfer->result, in_isr); + hcd_event_xfer_complete(hcchar_bm.dev_addr, ep_addr, xfer->xferred_bytes, xfer->result, in_isr); channel_dealloc(dwc2, ch_id); } } - channel->hcint = hcint; // clear all interrupt flags } } } @@ -828,14 +876,14 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { - hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; - const dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; - if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { + // skip writing to FIFO if channel is expecting halted. + if (!(channel->hcintmsk & HCINT_HALTED) && (channel->hcchar_bm.ep_dir == TUSB_DIR_OUT)) { + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; const uint16_t remain_packets = channel->hctsiz_bm.packet_count; for (uint16_t i = 0; i < remain_packets; i++) { const uint16_t remain_bytes = (uint16_t) channel->hctsiz_bm.xfer_size; - const uint16_t xact_bytes = tu_min16(remain_bytes, hcchar_bm.ep_size); + const uint16_t xact_bytes = tu_min16(remain_bytes, channel->hcchar_bm.ep_size); // check if there is enough space in FIFO and RequestQueue. // Packet's last word written to FIFO will trigger a request queue @@ -843,8 +891,8 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { return true; } - dfifo_write_packet(dwc2, ch_id, xfer->buffer, xact_bytes); - xfer->buffer += xact_bytes; + dfifo_write_packet(dwc2, ch_id, xfer->buf_start + xfer->out_fifo_bytes, xact_bytes); + xfer->out_fifo_bytes += xact_bytes; } } } @@ -896,11 +944,6 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { dwc2->gintmsk |= GINTMSK_RXFLVLM; } - if (int_status & GINTSTS_HCINT) { - // Host Channel interrupt: source is cleared in HCINT register - handle_channel_irq(rhport, in_isr); - } - if (int_status & GINTSTS_NPTX_FIFO_EMPTY) { // NPTX FIFO empty interrupt, this is read-only and cleared by hardware when FIFO is written const bool more_isr = handle_txfifo_empty(dwc2, false); @@ -909,6 +952,12 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { dwc2->gintmsk &= ~GINTSTS_NPTX_FIFO_EMPTY; } } + + if (int_status & GINTSTS_HCINT) { + // Host Channel interrupt: source is cleared in HCINT register + // must bee handled after TX FIFO empty + handle_channel_irq(rhport, in_isr); + } } #endif -- cgit v1.3.1 From 92e7ac6c237bdba001660894d6be4008480ad7ba Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 31 Oct 2024 10:50:09 +0700 Subject: fix bulk out and txfifo_empty(), should not rely on hcchar_bm.ep_size for OUT. msc explorer seems to work well. --- src/portable/synopsys/dwc2/hcd_dwc2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index e80f8d0ba..432aac1ea 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -882,12 +882,12 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; const uint16_t remain_packets = channel->hctsiz_bm.packet_count; for (uint16_t i = 0; i < remain_packets; i++) { - const uint16_t remain_bytes = (uint16_t) channel->hctsiz_bm.xfer_size; + const uint16_t remain_bytes = xfer->buf_len - xfer->out_fifo_bytes; const uint16_t xact_bytes = tu_min16(remain_bytes, channel->hcchar_bm.ep_size); - // check if there is enough space in FIFO and RequestQueue. + // skip if there is not enough space in FIFO and RequestQueue. // Packet's last word written to FIFO will trigger a request queue - if ((xact_bytes > (txsts_bm->fifo_available << 2)) && (txsts_bm->req_queue_available > 0)) { + if ((xact_bytes > (txsts_bm->fifo_available << 2)) || (txsts_bm->req_queue_available == 0)) { return true; } -- cgit v1.3.1 From 9afa64014c662eb549bfcb605b0828ca5aeb26be Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 31 Oct 2024 21:37:57 +0700 Subject: testing hcd with dma, work well after enumeration. --- examples/host/cdc_msc_hid/only.txt | 1 + src/portable/synopsys/dwc2/hcd_dwc2.c | 130 +++++++++++++++++++++++++++------- 2 files changed, 107 insertions(+), 24 deletions(-) (limited to 'src/portable') diff --git a/examples/host/cdc_msc_hid/only.txt b/examples/host/cdc_msc_hid/only.txt index fee10f9e2..9b3d6994e 100644 --- a/examples/host/cdc_msc_hid/only.txt +++ b/examples/host/cdc_msc_hid/only.txt @@ -12,3 +12,4 @@ mcu:MSP432E4 mcu:RX65X mcu:RAXXX mcu:MAX3421 +mcu:STM32F7 diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 432aac1ea..3b2721869 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -114,7 +114,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc return CFG_TUH_DWC2_DMA && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; } -// Find a free channel for new transfer +// Allocate a channel for new transfer TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) { const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { @@ -152,7 +152,7 @@ TU_ATTR_ALWAYS_INLINE static inline void channel_disable(const dwc2_regs_t* dwc2 // attempt to send IN token to receive data TU_ATTR_ALWAYS_INLINE static inline bool channel_send_in_token(const dwc2_regs_t* dwc2, dwc2_channel_t* channel, bool is_period) { TU_ASSERT(req_queue_avail(dwc2, is_period)); - channel->hcchar_bm.enable = 1; + channel->hcchar |= HCCHAR_CHENA; return true; } @@ -494,9 +494,20 @@ bool channel_start_xfer(dwc2_regs_t* dwc2, uint8_t ch_id) { // split: TODO support later channel->hcsplt = edpt->hcsplt; + channel->hcint = 0xFFFFFFFF; // clear all interrupts + if (dma_host_enabled(dwc2)) { - // channel->hcdma = (uint32_t) buffer; - TU_ASSERT(false); // not yet supported + uint32_t hcintmsk = HCINT_HALTED; + channel->hcintmsk = hcintmsk; + dwc2->haintmsk |= TU_BIT(ch_id); + + channel->hcdma = (uint32_t) xfer->buf_start; + + if (hcchar_bm->ep_dir == TUSB_DIR_IN) { + channel_send_in_token(dwc2, channel, is_period); + } else { + channel->hcchar |= HCCHAR_CHENA; + } } else { uint32_t hcintmsk = HCINT_NAK | HCINT_XACT_ERR | HCINT_STALL | HCINT_XFER_COMPLETE | HCINT_DATATOGGLE_ERR; if (hcchar_bm->ep_dir == TUSB_DIR_IN) { @@ -515,7 +526,7 @@ bool channel_start_xfer(dwc2_regs_t* dwc2, uint8_t ch_id) { if (hcchar_bm->ep_dir == TUSB_DIR_IN) { channel_send_in_token(dwc2, channel, is_period); } else { - channel->hcchar_bm.enable = 1; + channel->hcchar |= HCCHAR_CHENA; if (xfer->buf_len > 0) { // To prevent conflict with other channel, we will enable periodic/non-periodic FIFO empty interrupt accordingly // And write packet in the interrupt handler @@ -541,12 +552,15 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * TU_ASSERT(ch_id < 16); // all channel are in used hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; xfer->ep_id = ep_id; - - edpt->hcchar_bm.ep_dir = ep_dir; // control endpoint can switch direction xfer->buf_start = buffer; xfer->buf_len = buflen; xfer->result = XFER_RESULT_INVALID; + if (ep_num == 0) { + // update ep_dir since control endpoint can switch direction + edpt->hcchar_bm.ep_dir = ep_dir; + } + return channel_start_xfer(dwc2, ch_id); } @@ -725,7 +739,6 @@ TU_ATTR_ALWAYS_INLINE static inline void handle_hprt_irq(uint8_t rhport, bool in bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; - bool is_done = false; if (hcint & HCINT_XFER_COMPLETE) { @@ -765,15 +778,12 @@ bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, (void) is_period; hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; - bool is_done = false; if (hcint & HCINT_XFER_COMPLETE) { is_done = true; xfer->result = XFER_RESULT_SUCCESS; channel->hcintmsk &= ~HCINT_ACK; - TU_LOG1("xferred = %u, remain = %u, out_fifo = %u\n", - xfer->xferred_bytes, xfer->buf_len, xfer->out_fifo_bytes); } else if (hcint & HCINT_STALL) { xfer->result = XFER_RESULT_STALLED; channel_disable(dwc2, channel, is_period); @@ -795,8 +805,6 @@ bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, xfer->buf_start += actual_bytes; xfer->buf_len -= actual_bytes; xfer->out_fifo_bytes = 0; - TU_LOG1("xferred = %u, remain = %u, out_fifo = %u, this actual = %u\n", - xfer->xferred_bytes, xfer->buf_len, xfer->out_fifo_bytes, actual_bytes); channel_disable(dwc2, channel, is_period); if (hcint & HCINT_XACT_ERR) { @@ -830,6 +838,79 @@ bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, return is_done; } +bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { + (void) is_period; + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + dwc2_channel_t* channel = &dwc2->channel[ch_id]; + bool is_done = false; + + if (hcint & HCINT_HALTED) { + if (hcint & (HCINT_XFER_COMPLETE | HCINT_STALL | HCINT_BABBLE_ERR)) { + is_done = true; + xfer->err_count = 0; + if (hcint & HCINT_STALL) { + xfer->result = XFER_RESULT_STALLED; + } else if (hcint & HCINT_BABBLE_ERR) { + xfer->result = XFER_RESULT_FAILED; + } else { + xfer->result = XFER_RESULT_SUCCESS; + } + channel->hcintmsk &= ~HCINT_ACK; + } else if (hcint & HCINT_XACT_ERR) { + xfer->err_count++; + if (xfer->err_count >= HCD_XFER_ERROR_MAX) { + is_done = true; + xfer->result = XFER_RESULT_FAILED; + } else { + channel->hcintmsk |= HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR; + // re-init channel + TU_ASSERT(false); + } + } + } else if (hcint & (HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR)) { + xfer->err_count = 0; + channel->hcintmsk &= ~(HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR); + } + + return is_done; +} + +bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { + (void) is_period; + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + dwc2_channel_t* channel = &dwc2->channel[ch_id]; + bool is_done = false; + + if (hcint & HCINT_HALTED) { + if (hcint & (HCINT_XFER_COMPLETE | HCINT_STALL)) { + is_done = true; + xfer->result = (hcint & HCINT_STALL) ? XFER_RESULT_STALLED : XFER_RESULT_SUCCESS; + xfer->err_count = 0; + channel->hcintmsk &= ~HCINT_ACK; + } else if (hcint & HCINT_XACT_ERR) { + if (hcint & (HCINT_NAK | HCINT_NYET | HCINT_ACK)) { + xfer->err_count = 0; + // re-init channel, re-wind buffer pointer + TU_ASSERT(false); + } else { + xfer->err_count++; + if (xfer->err_count >= HCD_XFER_ERROR_MAX) { + xfer->result = XFER_RESULT_FAILED; + is_done = true; + } else { + // re-init channel, re-wind buffer pointer + TU_ASSERT(false); + } + } + } + } else if (hcint & HCINT_ACK) { + xfer->err_count = 0; + channel->hcintmsk &= ~HCINT_ACK; + } + + return is_done; +} + void handle_channel_irq(uint8_t rhport, bool in_isr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); const bool is_dma = dma_host_enabled(dwc2); @@ -843,28 +924,29 @@ void handle_channel_irq(uint8_t rhport, bool in_isr) { const bool is_period = edpt_is_periodic(hcchar_bm.ep_type); uint32_t hcint = channel->hcint; - hcint &= channel->hcintmsk; - - channel->hcint = hcint; // clear all interrupt flags + channel->hcint = (hcint & channel->hcintmsk); // clear enabled interrupts + bool is_done; if (is_dma) { // NOTE For DMA This is flow for core with OUT NAK enhancement from v2.71a + if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { + is_done = handle_channel_out_dma(dwc2, ch_id, is_period, hcint); + } else { + is_done = handle_channel_in_dma(dwc2, ch_id, is_period, hcint); + } } else { - bool is_done; - if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { is_done = handle_channel_out_slave(dwc2, ch_id, is_period, hcint); } else { is_done = handle_channel_in_slave(dwc2, ch_id, is_period, hcint); } - - if (is_done) { - const uint8_t ep_addr = tu_edpt_addr(hcchar_bm.ep_num, hcchar_bm.ep_dir); - hcd_event_xfer_complete(hcchar_bm.dev_addr, ep_addr, xfer->xferred_bytes, xfer->result, in_isr); - channel_dealloc(dwc2, ch_id); - } } + if (is_done) { + const uint8_t ep_addr = tu_edpt_addr(hcchar_bm.ep_num, hcchar_bm.ep_dir); + hcd_event_xfer_complete(hcchar_bm.dev_addr, ep_addr, xfer->xferred_bytes, xfer->result, in_isr); + channel_dealloc(dwc2, ch_id); + } } } } -- cgit v1.3.1 From f7f80e844ce7d3a38554609a11b8c16bb383ec21 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 31 Oct 2024 23:00:19 +0700 Subject: do ping for slave out when nak/nyet --- src/portable/synopsys/dwc2/dwc2_type.h | 1 + src/portable/synopsys/dwc2/hcd_dwc2.c | 21 +++++++++++++++++---- 2 files changed, 18 insertions(+), 4 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 342a4cb2d..89561a5e6 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -434,6 +434,7 @@ typedef struct TU_ATTR_PACKED { uint32_t xfer_size : 19; // 0..18 Transfer size in bytes uint32_t packet_count : 10; // 19..28 Number of packets uint32_t pid : 2; // 29..30 Packet ID + uint32_t do_ping : 1; // 31 Do PING } dwc2_channel_tsize_t; TU_VERIFY_STATIC(sizeof(dwc2_channel_tsize_t) == 4, "incorrect size"); diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 3b2721869..a1666b8d0 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -67,16 +67,21 @@ typedef struct { dwc2_channel_split_t hcsplt_bm; }; + uint8_t is_hs_dev; uint8_t next_pid; - // uint8_t resv[3]; + // uint8_t resv[2]; } hcd_endpoint_t; // Additional info for each channel when it is active typedef struct { volatile bool allocated; uint8_t ep_id; // associated edpt - uint8_t err_count; + union TU_ATTR_PACKED { + uint8_t err_count : 7; + uint8_t do_ping : 1; + }; uint8_t result; + uint16_t xferred_bytes; // bytes that accumulate transferred though USB bus for the whole hcd_edpt_xfer(), which can // be composed of multiple channel_start_xfer() (retry with NAK/NYET) uint8_t* buf_start; @@ -180,6 +185,7 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t edpt_alloc(void) { for (uint32_t i = 0; i < CFG_TUH_DWC2_ENDPOINT_MAX; i++) { hcd_endpoint_t* edpt = &_hcd_data.edpt[i]; if (edpt->hcchar_bm.enable == 0) { + tu_memclr(edpt, sizeof(hcd_endpoint_t)); edpt->hcchar_bm.enable = 1; return i; } @@ -460,6 +466,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* hcsplt_bm->split_en = 0; edpt->next_pid = HCTSIZ_PID_DATA0; + edpt->is_hs_dev = (devtree_info.speed == TUSB_SPEED_HIGH) ? 1 : 0; return true; } @@ -482,7 +489,12 @@ bool channel_start_xfer(dwc2_regs_t* dwc2, uint8_t ch_id) { // hctsiz: zero length packet still count as 1 const uint16_t packet_count = cal_packet_count(xfer->buf_len, hcchar_bm->ep_size); - channel->hctsiz = (edpt->next_pid << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | xfer->buf_len; + uint32_t hctsiz = (edpt->next_pid << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | xfer->buf_len; + if (xfer->do_ping && edpt->is_hs_dev && edpt->next_pid != HCTSIZ_PID_SETUP && hcchar_bm->ep_dir == TUSB_DIR_OUT) { + hctsiz |= HCTSIZ_DOPING; + xfer->do_ping = 0; + } + channel->hctsiz = hctsiz; // pre-calculate next PID based on packet count, adjusted in transfer complete interrupt if short packet if (hcchar_bm->ep_num == 0) { @@ -822,7 +834,8 @@ bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, xfer->result = XFER_RESULT_FAILED; is_done = true; } else { - // Got here due to NAK or NYET (need to do PING for HS) -> Retry transfer + // Got here due to NAK or NYET -> Retry transfer with do PING (for highspeed) + xfer->do_ping = 1; TU_ASSERT(channel_start_xfer(dwc2, ch_id)); } } else if (hcint & HCINT_ACK) { -- cgit v1.3.1 From 4c8ce9733aafa96c8810be3b291ff1afea6888b7 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 1 Nov 2024 16:55:12 +0700 Subject: dma host work well with bulk/control --- src/portable/synopsys/dwc2/hcd_dwc2.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index a1666b8d0..c35252a8d 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -861,6 +861,8 @@ bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uin if (hcint & (HCINT_XFER_COMPLETE | HCINT_STALL | HCINT_BABBLE_ERR)) { is_done = true; xfer->err_count = 0; + const uint16_t remain_bytes = (uint16_t) channel->hctsiz_bm.xfer_size; + xfer->xferred_bytes += (xfer->buf_len - remain_bytes); if (hcint & HCINT_STALL) { xfer->result = XFER_RESULT_STALLED; } else if (hcint & HCINT_BABBLE_ERR) { @@ -897,8 +899,19 @@ bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, ui if (hcint & HCINT_HALTED) { if (hcint & (HCINT_XFER_COMPLETE | HCINT_STALL)) { is_done = true; - xfer->result = (hcint & HCINT_STALL) ? XFER_RESULT_STALLED : XFER_RESULT_SUCCESS; xfer->err_count = 0; + if (hcint & HCINT_XFER_COMPLETE) { + xfer->result = XFER_RESULT_SUCCESS; + xfer->xferred_bytes += xfer->buf_len; + } else { + xfer->result = XFER_RESULT_STALLED; + const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + const uint16_t total_packets = cal_packet_count(xfer->buf_len, channel->hcchar_bm.ep_size); + const uint16_t actual_bytes = (total_packets - remain_packets) * channel->hcchar_bm.ep_size; + xfer->xferred_bytes += actual_bytes; + xfer->buf_start += actual_bytes; + xfer->buf_len -= actual_bytes; + } channel->hcintmsk &= ~HCINT_ACK; } else if (hcint & HCINT_XACT_ERR) { if (hcint & (HCINT_NAK | HCINT_NYET | HCINT_ACK)) { -- cgit v1.3.1 From b7ff10f59c48024e65341a494c51c471d4e8337e Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 1 Nov 2024 17:54:10 +0700 Subject: rename and add both CFG_TUH_DWC2_SLAVE_ENABLE/CFG_TUH_DWC2_DMA_ENABLE better out dma handle --- src/portable/synopsys/dwc2/dcd_dwc2.c | 10 +- src/portable/synopsys/dwc2/dwc2_common.c | 9 +- src/portable/synopsys/dwc2/dwc2_common.h | 2 +- src/portable/synopsys/dwc2/hcd_dwc2.c | 232 ++++++++++++++++--------------- src/tusb_option.h | 10 +- 5 files changed, 141 insertions(+), 122 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 9b5c476e4..4cf725bfe 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -412,8 +412,14 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Core Initialization const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE); - const bool is_dma = dma_device_enabled(dwc2); - TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma)); + TU_ASSERT(dwc2_core_init(rhport, is_highspeed)); + + if (dma_device_enabled(dwc2)) { + // DMA seems to be only settable after a core reset, and not possible to switch on-the-fly + dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2; + } else { + dwc2->gintmsk |= GINTSTS_RXFLVL; + } // Device Initialization dcd_disconnect(rhport); diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index 66dc59b11..a3c7e80cb 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -194,7 +194,7 @@ bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role) { * In addition, UTMI+/ULPI can be shared to run at fullspeed mode with 48Mhz * */ -bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) { +bool dwc2_core_init(uint8_t rhport, bool is_highspeed) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Check Synopsys ID register, failed if controller clock/power is not enabled @@ -235,13 +235,6 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) { dwc2->gintmsk = 0; - if (is_dma) { - // DMA seems to be only settable after a core reset, and not possible to switch on-the-fly - dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2; - } else { - dwc2->gintmsk |= GINTMSK_RXFLVLM; - } - return true; } diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h index 18b93894f..3f7f23c3a 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.h +++ b/src/portable/synopsys/dwc2/dwc2_common.h @@ -73,7 +73,7 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { } bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role); -bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma); +bool dwc2_core_init(uint8_t rhport, bool is_highspeed); void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr); //--------------------------------------------------------------------+ diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index c35252a8d..02f6fa54a 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -83,7 +83,7 @@ typedef struct { uint8_t result; uint16_t xferred_bytes; // bytes that accumulate transferred though USB bus for the whole hcd_edpt_xfer(), which can - // be composed of multiple channel_start_xfer() (retry with NAK/NYET) + // be composed of multiple channel_xfer_start() (retry with NAK/NYET) uint8_t* buf_start; uint16_t buf_len; uint16_t out_fifo_bytes; // bytes written to TX FIFO (may not be transferred on USB bus). @@ -116,7 +116,7 @@ TU_ATTR_ALWAYS_INLINE static inline tusb_speed_t convert_hprt_speed(uint32_t hpr TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc2) { (void) dwc2; // Internal DMA only - return CFG_TUH_DWC2_DMA && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; + return CFG_TUH_DWC2_DMA_ENABLE && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; } // Allocate a channel for new transfer @@ -321,8 +321,14 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Core Initialization const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_HOST); - const bool is_dma = dma_host_enabled(dwc2); - TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma)); + TU_ASSERT(dwc2_core_init(rhport, is_highspeed)); + + if (dma_host_enabled(dwc2)) { + // DMA seems to be only settable after a core reset, and not possible to switch on-the-fly + dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2; + } else { + dwc2->gintmsk |= GINTSTS_RXFLVL; + } //------------- 3.1 Host Initialization -------------// @@ -471,7 +477,29 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* return true; } -bool channel_start_xfer(dwc2_regs_t* dwc2, uint8_t ch_id) { +// clean up channel after part of transfer is done but the whole urb is not complete +static void channel_xfer_cleanup(dwc2_regs_t* dwc2, uint8_t ch_id) { + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + dwc2_channel_t* channel = &dwc2->channel[ch_id]; + TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX, ); + hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; + + edpt->next_pid = channel->hctsiz_bm.pid; // save PID + + /* Must use the hctsiz.pktcnt field to determine how much data has been transferred. This field reflects the number + * of packets that have been transferred via the USB. This is always an integral number of packets if the transfer + * was halted before its normal completion. (Can't use the hctsiz.xfersize field because that reflects the number of + * bytes transferred via the AHB, not the USB). */ + const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + const uint16_t total_packets = cal_packet_count(xfer->buf_len, channel->hcchar_bm.ep_size); + const uint16_t actual_bytes = (total_packets - remain_packets) * channel->hcchar_bm.ep_size; + xfer->xferred_bytes += actual_bytes; + xfer->buf_start += actual_bytes; + xfer->buf_len -= actual_bytes; + xfer->out_fifo_bytes = 0; +} + +static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; dwc2_channel_char_t* hcchar_bm = &edpt->hcchar_bm; @@ -573,7 +601,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * edpt->hcchar_bm.ep_dir = ep_dir; } - return channel_start_xfer(dwc2, ch_id); + return channel_xfer_start(dwc2, ch_id); } // Abort a queued transfer. Note: it can only abort transfer that has not been started @@ -627,7 +655,7 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { //-------------------------------------------------------------------- // HCD Event Handler //-------------------------------------------------------------------- - +#if CFG_TUH_DWC2_SLAVE_ENABLE static void handle_rxflvl_irq(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); @@ -683,72 +711,7 @@ static void handle_rxflvl_irq(uint8_t rhport) { } } -/* Handle Host Port interrupt, possible source are: - - Connection Detection - - Enable Change - - Over Current Change -*/ -TU_ATTR_ALWAYS_INLINE static inline void handle_hprt_irq(uint8_t rhport, bool in_isr) { - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint32_t hprt = dwc2->hprt & ~HPRT_W1C_MASK; - const dwc2_hprt_t hprt_bm = dwc2->hprt_bm; - - if (dwc2->hprt & HPRT_CONN_DETECT) { - // Port Connect Detect - hprt |= HPRT_CONN_DETECT; - - if (hprt_bm.conn_status) { - hcd_event_device_attach(rhport, in_isr); - } else { - hcd_event_device_remove(rhport, in_isr); - } - } - - if (dwc2->hprt & HPRT_ENABLE_CHANGE) { - // Port enable change - hprt |= HPRT_ENABLE_CHANGE; - - if (hprt_bm.enable) { - // Port enable - // Config HCFG FS/LS clock and HFIR for SOF interval according to link speed (value is in PHY clock unit) - const tusb_speed_t speed = convert_hprt_speed(hprt_bm.speed); - uint32_t hcfg = dwc2->hcfg & ~HCFG_FSLS_PHYCLK_SEL; - - const dwc2_gusbcfg_t gusbcfg_bm = dwc2->gusbcfg_bm; - uint32_t clock = 60; - if (gusbcfg_bm.phy_sel) { - // dedicated FS is 48Mhz - clock = 48; - hcfg |= HCFG_FSLS_PHYCLK_SEL_48MHZ; - } else { - // UTMI+ or ULPI - if (gusbcfg_bm.ulpi_utmi_sel) { - clock = 60; // ULPI 8-bit is 60Mhz - } else if (gusbcfg_bm.phy_if16) { - clock = 30; // UTMI+ 16-bit is 30Mhz - } else { - clock = 60; // UTMI+ 8-bit is 60Mhz - } - hcfg |= HCFG_FSLS_PHYCLK_SEL_30_60MHZ; - } - - dwc2->hcfg = hcfg; - - uint32_t hfir = dwc2->hfir & ~HFIR_FRIVL_Msk; - if (speed == TUSB_SPEED_HIGH) { - hfir |= 125*clock; - } else { - hfir |= 1000*clock; - } - - dwc2->hfir = hfir; - } - } - - dwc2->hprt = hprt; // clear interrupt -} - -bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { +static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; bool is_done = false; @@ -786,7 +749,7 @@ bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, u return is_done; } -bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { +static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { (void) is_period; hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; @@ -800,24 +763,8 @@ bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, xfer->result = XFER_RESULT_STALLED; channel_disable(dwc2, channel, is_period); } else if (hcint & (HCINT_NAK | HCINT_XACT_ERR | HCINT_NYET)) { - TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); - hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; - edpt->next_pid = channel->hctsiz_bm.pid; // save PID - - /* Rewind buffer pointer and total bytes to retry later - * Must use the hctsiz.pktcnt field to determine how much data has been transferred. This field reflects the number - * of packets that have been transferred via the USB. This is always an integral number of packets if the transfer - * was halted before its normal completion. (Can't use the hctsiz.xfersize field because that reflects the number of - * bytes transferred via the AHB, not the USB). - */ - const uint16_t remain_packets = channel->hctsiz_bm.packet_count; - const uint16_t total_packets = cal_packet_count(xfer->buf_len, channel->hcchar_bm.ep_size); - const uint16_t actual_bytes = (total_packets - remain_packets) * channel->hcchar_bm.ep_size; - xfer->xferred_bytes += actual_bytes; - xfer->buf_start += actual_bytes; - xfer->buf_len -= actual_bytes; - xfer->out_fifo_bytes = 0; - + // clean up transfer so far, disable and start again later + channel_xfer_cleanup(dwc2, ch_id); channel_disable(dwc2, channel, is_period); if (hcint & HCINT_XACT_ERR) { xfer->err_count++; @@ -836,7 +783,7 @@ bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, } else { // Got here due to NAK or NYET -> Retry transfer with do PING (for highspeed) xfer->do_ping = 1; - TU_ASSERT(channel_start_xfer(dwc2, ch_id)); + TU_ASSERT(channel_xfer_start(dwc2, ch_id)); } } else if (hcint & HCINT_ACK) { xfer->err_count = 0; @@ -850,8 +797,10 @@ bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, return is_done; } +#endif -bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { +#if CFG_TUH_DWC2_DMA_ENABLE +static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { (void) is_period; hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; @@ -890,7 +839,7 @@ bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uin return is_done; } -bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { +static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { (void) is_period; hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; @@ -905,27 +854,24 @@ bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, ui xfer->xferred_bytes += xfer->buf_len; } else { xfer->result = XFER_RESULT_STALLED; - const uint16_t remain_packets = channel->hctsiz_bm.packet_count; - const uint16_t total_packets = cal_packet_count(xfer->buf_len, channel->hcchar_bm.ep_size); - const uint16_t actual_bytes = (total_packets - remain_packets) * channel->hcchar_bm.ep_size; - xfer->xferred_bytes += actual_bytes; - xfer->buf_start += actual_bytes; - xfer->buf_len -= actual_bytes; + channel_xfer_cleanup(dwc2, ch_id); } channel->hcintmsk &= ~HCINT_ACK; } else if (hcint & HCINT_XACT_ERR) { if (hcint & (HCINT_NAK | HCINT_NYET | HCINT_ACK)) { xfer->err_count = 0; - // re-init channel, re-wind buffer pointer - TU_ASSERT(false); + // clean up transfer so far and start again + channel_xfer_cleanup(dwc2, ch_id); + channel_xfer_start(dwc2, ch_id); } else { xfer->err_count++; if (xfer->err_count >= HCD_XFER_ERROR_MAX) { xfer->result = XFER_RESULT_FAILED; is_done = true; } else { - // re-init channel, re-wind buffer pointer - TU_ASSERT(false); + // clean up transfer so far and start again + channel_xfer_cleanup(dwc2, ch_id); + channel_xfer_start(dwc2, ch_id); } } } @@ -936,8 +882,9 @@ bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, ui return is_done; } +#endif -void handle_channel_irq(uint8_t rhport, bool in_isr) { +static void handle_channel_irq(uint8_t rhport, bool in_isr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); const bool is_dma = dma_host_enabled(dwc2); const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); @@ -978,7 +925,7 @@ void handle_channel_irq(uint8_t rhport, bool in_isr) { } // return true if there is still pending data and need more ISR -bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { +static bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { // Use period txsts for both p/np to get request queue space available (1-bit difference, it is small enough) volatile dwc2_hptxsts_t* txsts_bm = (volatile dwc2_hptxsts_t*) (is_periodic ? &dwc2->hptxsts : &dwc2->hnptxsts); @@ -1008,6 +955,71 @@ bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { return false; // all data written } +/* Handle Host Port interrupt, possible source are: + - Connection Detection + - Enable Change + - Over Current Change +*/ +static void handle_hprt_irq(uint8_t rhport, bool in_isr) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + uint32_t hprt = dwc2->hprt & ~HPRT_W1C_MASK; + const dwc2_hprt_t hprt_bm = dwc2->hprt_bm; + + if (dwc2->hprt & HPRT_CONN_DETECT) { + // Port Connect Detect + hprt |= HPRT_CONN_DETECT; + + if (hprt_bm.conn_status) { + hcd_event_device_attach(rhport, in_isr); + } else { + hcd_event_device_remove(rhport, in_isr); + } + } + + if (dwc2->hprt & HPRT_ENABLE_CHANGE) { + // Port enable change + hprt |= HPRT_ENABLE_CHANGE; + + if (hprt_bm.enable) { + // Port enable + // Config HCFG FS/LS clock and HFIR for SOF interval according to link speed (value is in PHY clock unit) + const tusb_speed_t speed = convert_hprt_speed(hprt_bm.speed); + uint32_t hcfg = dwc2->hcfg & ~HCFG_FSLS_PHYCLK_SEL; + + const dwc2_gusbcfg_t gusbcfg_bm = dwc2->gusbcfg_bm; + uint32_t clock = 60; + if (gusbcfg_bm.phy_sel) { + // dedicated FS is 48Mhz + clock = 48; + hcfg |= HCFG_FSLS_PHYCLK_SEL_48MHZ; + } else { + // UTMI+ or ULPI + if (gusbcfg_bm.ulpi_utmi_sel) { + clock = 60; // ULPI 8-bit is 60Mhz + } else if (gusbcfg_bm.phy_if16) { + clock = 30; // UTMI+ 16-bit is 30Mhz + } else { + clock = 60; // UTMI+ 8-bit is 60Mhz + } + hcfg |= HCFG_FSLS_PHYCLK_SEL_30_60MHZ; + } + + dwc2->hcfg = hcfg; + + uint32_t hfir = dwc2->hfir & ~HFIR_FRIVL_Msk; + if (speed == TUSB_SPEED_HIGH) { + hfir |= 125*clock; + } else { + hfir |= 1000*clock; + } + + dwc2->hfir = hfir; + } + } + + dwc2->hprt = hprt; // clear interrupt +} + /* Interrupt Hierarchy HCINTn HPRT | | @@ -1040,17 +1052,19 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { handle_hprt_irq(rhport, in_isr); } +#if CFG_TUH_DWC2_SLAVE_ENABLE // RxFIFO non-empty interrupt handling, must be handled before HCINT if (int_status & GINTSTS_RXFLVL) { // RXFLVL bit is read-only - dwc2->gintmsk &= ~GINTMSK_RXFLVLM; // disable RXFLVL interrupt while reading + dwc2->gintmsk &= ~GINTSTS_RXFLVL; // disable RXFLVL interrupt while reading do { handle_rxflvl_irq(rhport); // read all packets } while(dwc2->gintsts & GINTSTS_RXFLVL); - dwc2->gintmsk |= GINTMSK_RXFLVLM; + dwc2->gintmsk |= GINTSTS_RXFLVL; } +#endif if (int_status & GINTSTS_NPTX_FIFO_EMPTY) { // NPTX FIFO empty interrupt, this is read-only and cleared by hardware when FIFO is written diff --git a/src/tusb_option.h b/src/tusb_option.h index f3a8bb724..b193d9c09 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -254,8 +254,14 @@ #define CFG_TUD_DWC2_DMA 0 #endif -#ifndef CFG_TUH_DWC2_DMA - #define CFG_TUH_DWC2_DMA 1 +// Enable DWC2 Slave mode for host +#ifndef CFG_TUH_DWC2_SLAVE_ENABLE + #define CFG_TUH_DWC2_SLAVE_ENABLE 1 +#endif + +// Enable DWC2 DMA for host +#ifndef CFG_TUH_DWC2_DMA_ENABLE + #define CFG_TUH_DWC2_DMA_ENABLE 1 #endif // Enable PIO-USB software host controller -- cgit v1.3.1 From b1182de8726db4080a8b1b8b4b57e1667eb81956 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 1 Nov 2024 19:04:32 +0700 Subject: clean up is_period --- src/portable/synopsys/dwc2/hcd_dwc2.c | 97 ++++++++++++++++++++--------------- 1 file changed, 55 insertions(+), 42 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 02f6fa54a..960a78ff3 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -66,16 +66,15 @@ typedef struct { uint32_t hcsplt; dwc2_channel_split_t hcsplt_bm; }; - - uint8_t is_hs_dev; uint8_t next_pid; - // uint8_t resv[2]; + uint16_t frame_interval; + uint16_t frame_countdown; } hcd_endpoint_t; // Additional info for each channel when it is active typedef struct { volatile bool allocated; - uint8_t ep_id; // associated edpt + uint8_t ep_id; union TU_ATTR_PACKED { uint8_t err_count : 7; uint8_t do_ping : 1; @@ -84,8 +83,8 @@ typedef struct { uint16_t xferred_bytes; // bytes that accumulate transferred though USB bus for the whole hcd_edpt_xfer(), which can // be composed of multiple channel_xfer_start() (retry with NAK/NYET) - uint8_t* buf_start; uint16_t buf_len; + uint8_t* buf_start; uint16_t out_fifo_bytes; // bytes written to TX FIFO (may not be transferred on USB bus). } hcd_xfer_t; @@ -133,6 +132,11 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) { return TUSB_INDEX_INVALID_8; } +// Check if is periodic (interrupt/isochronous) +TU_ATTR_ALWAYS_INLINE static inline bool edpt_is_periodic(uint8_t ep_type) { + return ep_type == HCCHAR_EPTYPE_INTERRUPT || ep_type == HCCHAR_EPTYPE_ISOCHRONOUS; +} + TU_ATTR_ALWAYS_INLINE static inline uint8_t req_queue_avail(const dwc2_regs_t* dwc2, bool is_period) { if (is_period) { return dwc2->hptxsts_bm.req_queue_available; @@ -147,16 +151,17 @@ TU_ATTR_ALWAYS_INLINE static inline void channel_dealloc(dwc2_regs_t* dwc2, uint dwc2->haintmsk &= ~TU_BIT(ch_id); } -TU_ATTR_ALWAYS_INLINE static inline void channel_disable(const dwc2_regs_t* dwc2, dwc2_channel_t* channel, bool is_period) { +TU_ATTR_ALWAYS_INLINE static inline bool channel_disable(const dwc2_regs_t* dwc2, dwc2_channel_t* channel) { // disable also require request queue - TU_ASSERT(req_queue_avail(dwc2, is_period), ); + TU_ASSERT(req_queue_avail(dwc2, edpt_is_periodic(channel->hcchar_bm.ep_type))); channel->hcintmsk |= HCINT_HALTED; channel->hcchar |= HCCHAR_CHDIS | HCCHAR_CHENA; // must set both CHDIS and CHENA + return true; } // attempt to send IN token to receive data -TU_ATTR_ALWAYS_INLINE static inline bool channel_send_in_token(const dwc2_regs_t* dwc2, dwc2_channel_t* channel, bool is_period) { - TU_ASSERT(req_queue_avail(dwc2, is_period)); +TU_ATTR_ALWAYS_INLINE static inline bool channel_send_in_token(const dwc2_regs_t* dwc2, dwc2_channel_t* channel) { + TU_ASSERT(req_queue_avail(dwc2, edpt_is_periodic(channel->hcchar_bm.ep_type))); channel->hcchar |= HCCHAR_CHENA; return true; } @@ -175,10 +180,6 @@ TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_find_enabled(dwc2_regs_t* dw return TUSB_INDEX_INVALID_8; } -// Check if is periodic (interrupt/isochronous) -TU_ATTR_ALWAYS_INLINE static inline bool edpt_is_periodic(uint8_t ep_type) { - return ep_type == HCCHAR_EPTYPE_INTERRUPT || ep_type == HCCHAR_EPTYPE_ISOCHRONOUS; -} // Allocate a new endpoint TU_ATTR_ALWAYS_INLINE static inline uint8_t edpt_alloc(void) { @@ -472,7 +473,15 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* hcsplt_bm->split_en = 0; edpt->next_pid = HCTSIZ_PID_DATA0; - edpt->is_hs_dev = (devtree_info.speed == TUSB_SPEED_HIGH) ? 1 : 0; + if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) { + edpt->frame_interval = 1 << (desc_ep->bInterval - 1); + } else if (desc_ep->bmAttributes.xfer == TUSB_XFER_INTERRUPT) { + if (devtree_info.speed == TUSB_SPEED_HIGH) { + edpt->frame_interval = 1 << (desc_ep->bInterval - 1); + } else { + edpt->frame_interval = desc_ep->bInterval; + } + } return true; } @@ -518,8 +527,12 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { // hctsiz: zero length packet still count as 1 const uint16_t packet_count = cal_packet_count(xfer->buf_len, hcchar_bm->ep_size); uint32_t hctsiz = (edpt->next_pid << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | xfer->buf_len; - if (xfer->do_ping && edpt->is_hs_dev && edpt->next_pid != HCTSIZ_PID_SETUP && hcchar_bm->ep_dir == TUSB_DIR_OUT) { - hctsiz |= HCTSIZ_DOPING; + if (xfer->do_ping && edpt->next_pid != HCTSIZ_PID_SETUP && hcchar_bm->ep_dir == TUSB_DIR_OUT) { + hcd_devtree_info_t devtree_info; + hcd_devtree_get_info(hcchar_bm->dev_addr, &devtree_info); + if (devtree_info.speed == TUSB_SPEED_HIGH) { + hctsiz |= HCTSIZ_DOPING; + } xfer->do_ping = 0; } channel->hctsiz = hctsiz; @@ -534,7 +547,7 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { // split: TODO support later channel->hcsplt = edpt->hcsplt; - channel->hcint = 0xFFFFFFFF; // clear all interrupts + channel->hcint = 0xFFFFFFFF; // clear all channel interrupts if (dma_host_enabled(dwc2)) { uint32_t hcintmsk = HCINT_HALTED; @@ -544,7 +557,7 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { channel->hcdma = (uint32_t) xfer->buf_start; if (hcchar_bm->ep_dir == TUSB_DIR_IN) { - channel_send_in_token(dwc2, channel, is_period); + channel_send_in_token(dwc2, channel); } else { channel->hcchar |= HCCHAR_CHENA; } @@ -564,7 +577,7 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { // IN Token. If we got NAK, we have to re-enable the channel again in the interrupt. Due to the way usbh stack only // call hcd_edpt_xfer() once, we will need to manage de-allocate/re-allocate IN channel dynamically. if (hcchar_bm->ep_dir == TUSB_DIR_IN) { - channel_send_in_token(dwc2, channel, is_period); + channel_send_in_token(dwc2, channel); } else { channel->hcchar |= HCCHAR_CHENA; if (xfer->buf_len > 0) { @@ -612,7 +625,6 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { const uint8_t ep_dir = tu_edpt_dir(ep_addr); const uint8_t ep_id = edpt_find_opened(dev_addr, ep_num, ep_dir); TU_VERIFY(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); - //hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; // hcd_int_disable(rhport); @@ -620,7 +632,7 @@ bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { const uint8_t ch_id = channel_find_enabled(dwc2, dev_addr, ep_num, ep_dir); if (ch_id < 16) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; - channel_disable(dwc2, channel, edpt_is_periodic(channel->hcchar_bm.ep_type)); + channel_disable(dwc2, channel); } // hcd_int_enable(rhport); @@ -685,9 +697,7 @@ static void handle_rxflvl_irq(uint8_t rhport) { edpt->next_pid = cal_next_pid(edpt->next_pid, remain_packets); } else { if (remain_packets) { - // still more packet to send - bool const is_period = edpt_is_periodic(channel->hcchar_bm.ep_type); - channel_send_in_token(dwc2, channel, is_period); + channel_send_in_token(dwc2, channel); // still more packet to send } } break; @@ -711,17 +721,17 @@ static void handle_rxflvl_irq(uint8_t rhport) { } } -static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { +static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcint) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; bool is_done = false; if (hcint & HCINT_XFER_COMPLETE) { xfer->result = XFER_RESULT_SUCCESS; - channel_disable(dwc2, channel, is_period); + channel_disable(dwc2, channel); channel->hcintmsk &= ~HCINT_ACK; } else if (hcint & (HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_STALL)) { - channel_disable(dwc2, channel, is_period); + channel_disable(dwc2, channel); if (hcint & HCINT_XACT_ERR) { xfer->err_count++; channel->hcintmsk |= HCINT_ACK; @@ -743,14 +753,13 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_pe xfer->err_count = 0; } else if (hcint & HCINT_NAK) { // NAK received, re-enable channel if request queue is available - channel_send_in_token(dwc2, channel, is_period); + channel_send_in_token(dwc2, channel); } return is_done; } -static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { - (void) is_period; +static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcint) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; bool is_done = false; @@ -761,11 +770,11 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_p channel->hcintmsk &= ~HCINT_ACK; } else if (hcint & HCINT_STALL) { xfer->result = XFER_RESULT_STALLED; - channel_disable(dwc2, channel, is_period); + channel_disable(dwc2, channel); } else if (hcint & (HCINT_NAK | HCINT_XACT_ERR | HCINT_NYET)) { // clean up transfer so far, disable and start again later channel_xfer_cleanup(dwc2, ch_id); - channel_disable(dwc2, channel, is_period); + channel_disable(dwc2, channel); if (hcint & HCINT_XACT_ERR) { xfer->err_count++; channel->hcintmsk |= HCINT_ACK; @@ -800,8 +809,7 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_p #endif #if CFG_TUH_DWC2_DMA_ENABLE -static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { - (void) is_period; +static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcint) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; bool is_done = false; @@ -834,13 +842,16 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_peri } else if (hcint & (HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR)) { xfer->err_count = 0; channel->hcintmsk &= ~(HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR); + // if (hcint & (HCINT_NAK | HCINT_DATATOGGLE_ERR)) { + // TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX,); + // hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; + // } } return is_done; } -static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, bool is_period, uint32_t hcint) { - (void) is_period; +static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcint) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; bool is_done = false; @@ -894,25 +905,27 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; - const bool is_period = edpt_is_periodic(hcchar_bm.ep_type); uint32_t hcint = channel->hcint; channel->hcint = (hcint & channel->hcintmsk); // clear enabled interrupts bool is_done; if (is_dma) { - // NOTE For DMA This is flow for core with OUT NAK enhancement from v2.71a + #if CFG_TUH_DWC2_DMA_ENABLE if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { - is_done = handle_channel_out_dma(dwc2, ch_id, is_period, hcint); + is_done = handle_channel_out_dma(dwc2, ch_id, hcint); } else { - is_done = handle_channel_in_dma(dwc2, ch_id, is_period, hcint); + is_done = handle_channel_in_dma(dwc2, ch_id, hcint); } + #endif } else { + #if CFG_TUH_DWC2_SLAVE_ENABLE if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { - is_done = handle_channel_out_slave(dwc2, ch_id, is_period, hcint); + is_done = handle_channel_out_slave(dwc2, ch_id, hcint); } else { - is_done = handle_channel_in_slave(dwc2, ch_id, is_period, hcint); + is_done = handle_channel_in_slave(dwc2, ch_id, hcint); } + #endif } if (is_done) { -- cgit v1.3.1 From 4f288c030ad92f9859cbc6b78ed86d06609c2ea5 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 1 Nov 2024 20:58:29 +0700 Subject: move buffer and buflen to hcd_endpoint_t to support periodic endpoint --- src/portable/synopsys/dwc2/dwc2_common.c | 12 +-- src/portable/synopsys/dwc2/hcd_dwc2.c | 175 +++++++++++++++++++------------ 2 files changed, 109 insertions(+), 78 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index a3c7e80cb..4d62cf3c6 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -224,15 +224,9 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed) { dfifo_flush_tx(dwc2, 0x10); // all tx fifo dfifo_flush_rx(dwc2); - // Clear all pending interrupts - uint32_t int_mask; - - int_mask = dwc2->gintsts; - dwc2->gintsts |= int_mask; - - int_mask = dwc2->gotgint; - dwc2->gotgint |= int_mask; - + // Clear pending and disable all interrupts + dwc2->gintsts = 0xFFFFFFFFU; + dwc2->gotgint = 0xFFFFFFFFU; dwc2->gintmsk = 0; return true; diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 960a78ff3..c44ea436a 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -66,9 +66,13 @@ typedef struct { uint32_t hcsplt; dwc2_channel_split_t hcsplt_bm; }; + uint8_t next_pid; uint16_t frame_interval; uint16_t frame_countdown; + + uint8_t* buffer; + uint16_t buflen; } hcd_endpoint_t; // Additional info for each channel when it is active @@ -83,8 +87,6 @@ typedef struct { uint16_t xferred_bytes; // bytes that accumulate transferred though USB bus for the whole hcd_edpt_xfer(), which can // be composed of multiple channel_xfer_start() (retry with NAK/NYET) - uint16_t buf_len; - uint8_t* buf_start; uint16_t out_fifo_bytes; // bytes written to TX FIFO (may not be transferred on USB bus). } hcd_xfer_t; @@ -490,7 +492,6 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* static void channel_xfer_cleanup(dwc2_regs_t* dwc2, uint8_t ch_id) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; - TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX, ); hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; edpt->next_pid = channel->hctsiz_bm.pid; // save PID @@ -500,12 +501,12 @@ static void channel_xfer_cleanup(dwc2_regs_t* dwc2, uint8_t ch_id) { * was halted before its normal completion. (Can't use the hctsiz.xfersize field because that reflects the number of * bytes transferred via the AHB, not the USB). */ const uint16_t remain_packets = channel->hctsiz_bm.packet_count; - const uint16_t total_packets = cal_packet_count(xfer->buf_len, channel->hcchar_bm.ep_size); + const uint16_t total_packets = cal_packet_count(edpt->buflen, channel->hcchar_bm.ep_size); const uint16_t actual_bytes = (total_packets - remain_packets) * channel->hcchar_bm.ep_size; xfer->xferred_bytes += actual_bytes; - xfer->buf_start += actual_bytes; - xfer->buf_len -= actual_bytes; xfer->out_fifo_bytes = 0; + edpt->buffer += actual_bytes; + edpt->buflen -= actual_bytes; } static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { @@ -525,8 +526,8 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { channel->hcchar = (edpt->hcchar & ~HCCHAR_CHENA); // hctsiz: zero length packet still count as 1 - const uint16_t packet_count = cal_packet_count(xfer->buf_len, hcchar_bm->ep_size); - uint32_t hctsiz = (edpt->next_pid << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | xfer->buf_len; + const uint16_t packet_count = cal_packet_count(edpt->buflen, hcchar_bm->ep_size); + uint32_t hctsiz = (edpt->next_pid << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | edpt->buflen; if (xfer->do_ping && edpt->next_pid != HCTSIZ_PID_SETUP && hcchar_bm->ep_dir == TUSB_DIR_OUT) { hcd_devtree_info_t devtree_info; hcd_devtree_get_info(hcchar_bm->dev_addr, &devtree_info); @@ -547,14 +548,14 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { // split: TODO support later channel->hcsplt = edpt->hcsplt; - channel->hcint = 0xFFFFFFFF; // clear all channel interrupts + channel->hcint = 0xFFFFFFFFU; // clear all channel interrupts if (dma_host_enabled(dwc2)) { uint32_t hcintmsk = HCINT_HALTED; channel->hcintmsk = hcintmsk; dwc2->haintmsk |= TU_BIT(ch_id); - channel->hcdma = (uint32_t) xfer->buf_start; + channel->hcdma = (uint32_t) edpt->buffer; if (hcchar_bm->ep_dir == TUSB_DIR_IN) { channel_send_in_token(dwc2, channel); @@ -580,7 +581,7 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { channel_send_in_token(dwc2, channel); } else { channel->hcchar |= HCCHAR_CHENA; - if (xfer->buf_len > 0) { + if (edpt->buflen > 0) { // To prevent conflict with other channel, we will enable periodic/non-periodic FIFO empty interrupt accordingly // And write packet in the interrupt handler dwc2->gintmsk |= (is_period ? GINTSTS_PTX_FIFO_EMPTY : GINTSTS_NPTX_FIFO_EMPTY); @@ -605,9 +606,9 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * TU_ASSERT(ch_id < 16); // all channel are in used hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; xfer->ep_id = ep_id; - xfer->buf_start = buffer; - xfer->buf_len = buflen; xfer->result = XFER_RESULT_INVALID; + edpt->buffer = buffer; + edpt->buflen = buflen; if (ep_num == 0) { // update ep_dir since control endpoint can switch direction @@ -681,8 +682,10 @@ static void handle_rxflvl_irq(uint8_t rhport) { // In packet received const uint16_t byte_count = grxstsp_bm.byte_count; hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX,); + hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; - dfifo_read_packet(dwc2, xfer->buf_start + xfer->xferred_bytes, byte_count); + dfifo_read_packet(dwc2, edpt->buffer + xfer->xferred_bytes, byte_count); xfer->xferred_bytes += byte_count; const uint16_t remain_bytes = (uint16_t) channel->hctsiz_bm.xfer_size; @@ -692,8 +695,6 @@ static void handle_rxflvl_irq(uint8_t rhport) { xfer->xferred_bytes -= remain_bytes; // update PID based on remain packets count - TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX,); - hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; // update PID edpt->next_pid = cal_next_pid(edpt->next_pid, remain_packets); } else { if (remain_packets) { @@ -721,6 +722,40 @@ static void handle_rxflvl_irq(uint8_t rhport) { } } +// return true if there is still pending data and need more ISR +static bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { + // Use period txsts for both p/np to get request queue space available (1-bit difference, it is small enough) + volatile dwc2_hptxsts_t* txsts_bm = (volatile dwc2_hptxsts_t*) (is_periodic ? &dwc2->hptxsts : &dwc2->hnptxsts); + + const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); + for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { + dwc2_channel_t* channel = &dwc2->channel[ch_id]; + // skip writing to FIFO if channel is expecting halted. + if (!(channel->hcintmsk & HCINT_HALTED) && (channel->hcchar_bm.ep_dir == TUSB_DIR_OUT)) { + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); + hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; + + const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + for (uint16_t i = 0; i < remain_packets; i++) { + const uint16_t remain_bytes = edpt->buflen - xfer->out_fifo_bytes; + const uint16_t xact_bytes = tu_min16(remain_bytes, channel->hcchar_bm.ep_size); + + // skip if there is not enough space in FIFO and RequestQueue. + // Packet's last word written to FIFO will trigger a request queue + if ((xact_bytes > (txsts_bm->fifo_available << 2)) || (txsts_bm->req_queue_available == 0)) { + return true; + } + + dfifo_write_packet(dwc2, ch_id, edpt->buffer + xfer->out_fifo_bytes, xact_bytes); + xfer->out_fifo_bytes += xact_bytes; + } + } + } + + return false; // all data written +} + static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcint) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; @@ -812,6 +847,8 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcint) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; + hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; + bool is_done = false; if (hcint & HCINT_HALTED) { @@ -819,7 +856,7 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci is_done = true; xfer->err_count = 0; const uint16_t remain_bytes = (uint16_t) channel->hctsiz_bm.xfer_size; - xfer->xferred_bytes += (xfer->buf_len - remain_bytes); + xfer->xferred_bytes += (edpt->buflen - remain_bytes); if (hcint & HCINT_STALL) { xfer->result = XFER_RESULT_STALLED; } else if (hcint & HCINT_BABBLE_ERR) { @@ -838,14 +875,23 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci // re-init channel TU_ASSERT(false); } + } else if (hcint & (HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR)) { + xfer->err_count = 0; + channel->hcintmsk &= ~(HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR); + if ((hcint & (HCINT_NAK | HCINT_DATATOGGLE_ERR))) { + edpt->next_pid = channel->hctsiz_bm.pid; // save PID + + if (edpt_is_periodic(channel->hcchar_bm.ep_type)){ + // for periodic, de-allocate channel, enable SOF set frame counter for later transfer + channel_dealloc(dwc2, ch_id); + edpt->frame_countdown = edpt->frame_interval; + dwc2->gintmsk |= GINTSTS_SOF; + } else { + // for control/bulk: try again immediately + TU_ASSERT(false); + } + } } - } else if (hcint & (HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR)) { - xfer->err_count = 0; - channel->hcintmsk &= ~(HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR); - // if (hcint & (HCINT_NAK | HCINT_DATATOGGLE_ERR)) { - // TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX,); - // hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; - // } } return is_done; @@ -854,6 +900,8 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcint) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; + hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; + bool is_done = false; if (hcint & HCINT_HALTED) { @@ -862,7 +910,7 @@ static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hc xfer->err_count = 0; if (hcint & HCINT_XFER_COMPLETE) { xfer->result = XFER_RESULT_SUCCESS; - xfer->xferred_bytes += xfer->buf_len; + xfer->xferred_bytes += edpt->buflen; } else { xfer->result = XFER_RESULT_STALLED; channel_xfer_cleanup(dwc2, ch_id); @@ -904,6 +952,7 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) { if (tu_bit_test(dwc2->haint, ch_id)) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX,); dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; uint32_t hcint = channel->hcint; @@ -937,35 +986,21 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) { } } -// return true if there is still pending data and need more ISR -static bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { - // Use period txsts for both p/np to get request queue space available (1-bit difference, it is small enough) - volatile dwc2_hptxsts_t* txsts_bm = (volatile dwc2_hptxsts_t*) (is_periodic ? &dwc2->hptxsts : &dwc2->hnptxsts); - - const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); - for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { - dwc2_channel_t* channel = &dwc2->channel[ch_id]; - // skip writing to FIFO if channel is expecting halted. - if (!(channel->hcintmsk & HCINT_HALTED) && (channel->hcchar_bm.ep_dir == TUSB_DIR_OUT)) { - hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; - const uint16_t remain_packets = channel->hctsiz_bm.packet_count; - for (uint16_t i = 0; i < remain_packets; i++) { - const uint16_t remain_bytes = xfer->buf_len - xfer->out_fifo_bytes; - const uint16_t xact_bytes = tu_min16(remain_bytes, channel->hcchar_bm.ep_size); - - // skip if there is not enough space in FIFO and RequestQueue. - // Packet's last word written to FIFO will trigger a request queue - if ((xact_bytes > (txsts_bm->fifo_available << 2)) || (txsts_bm->req_queue_available == 0)) { - return true; - } - - dfifo_write_packet(dwc2, ch_id, xfer->buf_start + xfer->out_fifo_bytes, xact_bytes); - xfer->out_fifo_bytes += xact_bytes; - } - } - } - - return false; // all data written +// SOF is enabled for scheduled periodic transfer +static void handle_sof_irq(uint8_t rhport, bool in_isr) { + (void) in_isr; + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + (void) dwc2; + // for(uint8_t ep_id; ep_id < CFG_TUH_DWC2_ENDPOINT_MAX; ep_id++) { + // hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; + // if (edpt->hcchar_bm.enable && edpt_is_periodic(edpt->hcchar_bm.ep_type) && edpt->frame_countdown > 0) { + // + // edpt->frame_countdown--; + // if (edpt->frame_countdown == 0) { + // channel_xfer_start(dwc2, ep_id); + // } + // } + // } } /* Handle Host Port interrupt, possible source are: @@ -1034,22 +1069,20 @@ static void handle_hprt_irq(uint8_t rhport, bool in_isr) { } /* Interrupt Hierarchy - HCINTn HPRT - | | - HAINT.CHn | - | | - GINTSTS : HCInt PrtInt NPTxFEmp PTxFEmpp RXFLVL - - + HCINTn HPRT + | | + HAINT.CHn | + | | + GINTSTS : HCInt | PrtInt | NPTxFEmp | PTxFEmpp | RXFLVL | SOF */ void hcd_int_handler(uint8_t rhport, bool in_isr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - const uint32_t int_mask = dwc2->gintmsk; - const uint32_t int_status = dwc2->gintsts & int_mask; + const uint32_t gintmsk = dwc2->gintmsk; + const uint32_t gintsts = dwc2->gintsts & gintmsk; // TU_LOG1_HEX(int_status); - if (int_status & GINTSTS_CONIDSTSCHNG) { + if (gintsts & GINTSTS_CONIDSTSCHNG) { // Connector ID status change dwc2->gintsts = GINTSTS_CONIDSTSCHNG; @@ -1059,7 +1092,11 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { // TODO wait for SRP if OTG } - if (int_status & GINTSTS_HPRTINT) { + if (gintsts & GINTSTS_SOF) { + handle_sof_irq(rhport, in_isr); + } + + if (gintsts & GINTSTS_HPRTINT) { // Host port interrupt: source is cleared in HPRT register // TU_LOG1_HEX(dwc2->hprt); handle_hprt_irq(rhport, in_isr); @@ -1067,7 +1104,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { #if CFG_TUH_DWC2_SLAVE_ENABLE // RxFIFO non-empty interrupt handling, must be handled before HCINT - if (int_status & GINTSTS_RXFLVL) { + if (gintsts & GINTSTS_RXFLVL) { // RXFLVL bit is read-only dwc2->gintmsk &= ~GINTSTS_RXFLVL; // disable RXFLVL interrupt while reading @@ -1077,9 +1114,8 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { dwc2->gintmsk |= GINTSTS_RXFLVL; } -#endif - if (int_status & GINTSTS_NPTX_FIFO_EMPTY) { + if (gintsts & GINTSTS_NPTX_FIFO_EMPTY) { // NPTX FIFO empty interrupt, this is read-only and cleared by hardware when FIFO is written const bool more_isr = handle_txfifo_empty(dwc2, false); if (!more_isr) { @@ -1087,8 +1123,9 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { dwc2->gintmsk &= ~GINTSTS_NPTX_FIFO_EMPTY; } } +#endif - if (int_status & GINTSTS_HCINT) { + if (gintsts & GINTSTS_HCINT) { // Host Channel interrupt: source is cleared in HCINT register // must bee handled after TX FIFO empty handle_channel_irq(rhport, in_isr); -- cgit v1.3.1 From c96e04159e3420f156a29bb1de899a379086ff4a Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 1 Nov 2024 21:31:01 +0700 Subject: implement periodic endpoint using sof --- src/portable/synopsys/dwc2/hcd_dwc2.c | 61 ++++++++++++++++++++++------------- 1 file changed, 38 insertions(+), 23 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index c44ea436a..b6509ad4e 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -69,7 +69,7 @@ typedef struct { uint8_t next_pid; uint16_t frame_interval; - uint16_t frame_countdown; + uint16_t frame_countdown; // count down to make a transfer for periodic endpoint (from interval) uint8_t* buffer; uint16_t buflen; @@ -592,6 +592,17 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { return true; } +// kick-off transfer with an endpoint +static bool edpt_xfer_kickoff(dwc2_regs_t* dwc2, uint8_t ep_id) { + uint8_t ch_id = channel_alloc(dwc2); + TU_ASSERT(ch_id < 16); // all channel are in used + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + xfer->ep_id = ep_id; + xfer->result = XFER_RESULT_INVALID; + + return channel_xfer_start(dwc2, ch_id); +} + // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); @@ -602,11 +613,6 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * TU_ASSERT(ep_id < CFG_TUH_DWC2_ENDPOINT_MAX); hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; - uint8_t ch_id = channel_alloc(dwc2); - TU_ASSERT(ch_id < 16); // all channel are in used - hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; - xfer->ep_id = ep_id; - xfer->result = XFER_RESULT_INVALID; edpt->buffer = buffer; edpt->buflen = buflen; @@ -615,7 +621,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * edpt->hcchar_bm.ep_dir = ep_dir; } - return channel_xfer_start(dwc2, ch_id); + return edpt_xfer_kickoff(dwc2, ep_id); } // Abort a queued transfer. Note: it can only abort transfer that has not been started @@ -880,7 +886,6 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci channel->hcintmsk &= ~(HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR); if ((hcint & (HCINT_NAK | HCINT_DATATOGGLE_ERR))) { edpt->next_pid = channel->hctsiz_bm.pid; // save PID - if (edpt_is_periodic(channel->hcchar_bm.ep_type)){ // for periodic, de-allocate channel, enable SOF set frame counter for later transfer channel_dealloc(dwc2, ch_id); @@ -987,20 +992,27 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) { } // SOF is enabled for scheduled periodic transfer -static void handle_sof_irq(uint8_t rhport, bool in_isr) { +static bool handle_sof_irq(uint8_t rhport, bool in_isr) { (void) in_isr; dwc2_regs_t* dwc2 = DWC2_REG(rhport); - (void) dwc2; - // for(uint8_t ep_id; ep_id < CFG_TUH_DWC2_ENDPOINT_MAX; ep_id++) { - // hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; - // if (edpt->hcchar_bm.enable && edpt_is_periodic(edpt->hcchar_bm.ep_type) && edpt->frame_countdown > 0) { - // - // edpt->frame_countdown--; - // if (edpt->frame_countdown == 0) { - // channel_xfer_start(dwc2, ep_id); - // } - // } - // } + + bool more_isr = false; + + for(uint8_t ep_id = 0; ep_id < CFG_TUH_DWC2_ENDPOINT_MAX; ep_id++) { + hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; + if (edpt->hcchar_bm.enable && edpt_is_periodic(edpt->hcchar_bm.ep_type) && edpt->frame_countdown > 0) { + edpt->frame_countdown--; + if (edpt->frame_countdown == 0) { + if (!edpt_xfer_kickoff(dwc2, ep_id)) { + edpt->frame_countdown = 1; // failed to start (out of channel), try again next frame + } + } + + more_isr = true; + } + } + + return more_isr; } /* Handle Host Port interrupt, possible source are: @@ -1093,7 +1105,10 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { } if (gintsts & GINTSTS_SOF) { - handle_sof_irq(rhport, in_isr); + const bool more_sof = handle_sof_irq(rhport, in_isr); + if (!more_sof) { + dwc2->gintmsk &= ~GINTSTS_SOF; + } } if (gintsts & GINTSTS_HPRTINT) { @@ -1117,8 +1132,8 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { if (gintsts & GINTSTS_NPTX_FIFO_EMPTY) { // NPTX FIFO empty interrupt, this is read-only and cleared by hardware when FIFO is written - const bool more_isr = handle_txfifo_empty(dwc2, false); - if (!more_isr) { + const bool more_nptxfe = handle_txfifo_empty(dwc2, false); + if (!more_nptxfe) { // no more pending packet, disable interrupt dwc2->gintmsk &= ~GINTSTS_NPTX_FIFO_EMPTY; } -- cgit v1.3.1 From a0f75e5b6742c5365bbcea079dab75242230fe60 Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 2 Nov 2024 00:20:40 +0700 Subject: fix slave in nak & ack order --- src/portable/synopsys/dwc2/hcd_dwc2.c | 109 ++++++++++++++++++++-------------- 1 file changed, 63 insertions(+), 46 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index b6509ad4e..42a5b9fbd 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -87,7 +87,7 @@ typedef struct { uint16_t xferred_bytes; // bytes that accumulate transferred though USB bus for the whole hcd_edpt_xfer(), which can // be composed of multiple channel_xfer_start() (retry with NAK/NYET) - uint16_t out_fifo_bytes; // bytes written to TX FIFO (may not be transferred on USB bus). + uint16_t txfifo_bytes; // bytes written to TX FIFO (may not be transferred on USB bus). } hcd_xfer_t; typedef struct { @@ -489,22 +489,29 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* } // clean up channel after part of transfer is done but the whole urb is not complete -static void channel_xfer_cleanup(dwc2_regs_t* dwc2, uint8_t ch_id) { +static void channel_xfer_wrapup(dwc2_regs_t* dwc2, uint8_t ch_id) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; edpt->next_pid = channel->hctsiz_bm.pid; // save PID - /* Must use the hctsiz.pktcnt field to determine how much data has been transferred. This field reflects the number - * of packets that have been transferred via the USB. This is always an integral number of packets if the transfer - * was halted before its normal completion. (Can't use the hctsiz.xfersize field because that reflects the number of - * bytes transferred via the AHB, not the USB). */ - const uint16_t remain_packets = channel->hctsiz_bm.packet_count; - const uint16_t total_packets = cal_packet_count(edpt->buflen, channel->hcchar_bm.ep_size); - const uint16_t actual_bytes = (total_packets - remain_packets) * channel->hcchar_bm.ep_size; + /* Since hctsiz.xfersize field reflects the number of bytes transferred via the AHB, not the USB) + * For IN: we can use hctsiz.xfersize as remaining bytes. + * For OUT: Must use the hctsiz.pktcnt field to determine how much data has been transferred. This field reflects the + * number of packets that have been transferred via the USB. This is always an integral number of packets if the + * transfer was halted before its normal completion. + */ + uint16_t actual_bytes; + if (channel->hcchar_bm.ep_dir == TUSB_DIR_IN) { + actual_bytes = edpt->buflen - channel->hctsiz_bm.xfer_size; + } else { + const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + const uint16_t total_packets = cal_packet_count(edpt->buflen, channel->hcchar_bm.ep_size); + actual_bytes = (total_packets - remain_packets) * channel->hcchar_bm.ep_size; + } + xfer->txfifo_bytes = 0; xfer->xferred_bytes += actual_bytes; - xfer->out_fifo_bytes = 0; edpt->buffer += actual_bytes; edpt->buflen -= actual_bytes; } @@ -517,7 +524,7 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { bool const is_period = edpt_is_periodic(hcchar_bm->ep_type); // clear previous state - xfer->out_fifo_bytes = 0; + xfer->txfifo_bytes = 0; // hchar: restore but don't enable yet if (is_period) { @@ -691,19 +698,15 @@ static void handle_rxflvl_irq(uint8_t rhport) { TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX,); hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; - dfifo_read_packet(dwc2, edpt->buffer + xfer->xferred_bytes, byte_count); - xfer->xferred_bytes += byte_count; - - const uint16_t remain_bytes = (uint16_t) channel->hctsiz_bm.xfer_size; - const uint16_t remain_packets = channel->hctsiz_bm.packet_count; - if (byte_count < channel->hcchar_bm.ep_size) { - // short packet, minus remaining bytes - xfer->xferred_bytes -= remain_bytes; + if (byte_count) { + dfifo_read_packet(dwc2, edpt->buffer + xfer->xferred_bytes, byte_count); + xfer->xferred_bytes += byte_count; - // update PID based on remain packets count - edpt->next_pid = cal_next_pid(edpt->next_pid, remain_packets); - } else { - if (remain_packets) { + const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + if (byte_count < edpt->hcchar_bm.ep_size) { + // short packet: update PID based on remain packets count + edpt->next_pid = cal_next_pid(edpt->next_pid, remain_packets); + } if (remain_packets) { channel_send_in_token(dwc2, channel); // still more packet to send } } @@ -744,7 +747,7 @@ static bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { const uint16_t remain_packets = channel->hctsiz_bm.packet_count; for (uint16_t i = 0; i < remain_packets; i++) { - const uint16_t remain_bytes = edpt->buflen - xfer->out_fifo_bytes; + const uint16_t remain_bytes = edpt->buflen - xfer->txfifo_bytes; const uint16_t xact_bytes = tu_min16(remain_bytes, channel->hcchar_bm.ep_size); // skip if there is not enough space in FIFO and RequestQueue. @@ -753,8 +756,8 @@ static bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { return true; } - dfifo_write_packet(dwc2, ch_id, edpt->buffer + xfer->out_fifo_bytes, xact_bytes); - xfer->out_fifo_bytes += xact_bytes; + dfifo_write_packet(dwc2, ch_id, edpt->buffer + xfer->txfifo_bytes, xact_bytes); + xfer->txfifo_bytes += xact_bytes; } } } @@ -772,11 +775,15 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h channel_disable(dwc2, channel); channel->hcintmsk &= ~HCINT_ACK; } else if (hcint & (HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_STALL)) { - channel_disable(dwc2, channel); - if (hcint & HCINT_XACT_ERR) { + if (hcint & HCINT_STALL) { + xfer->result = XFER_RESULT_STALLED; + } else if (hcint & HCINT_BABBLE_ERR) { + xfer->result = XFER_RESULT_FAILED; + } else if (hcint & HCINT_XACT_ERR) { xfer->err_count++; channel->hcintmsk |= HCINT_ACK; } + channel_disable(dwc2, channel); } else if (hcint & HCINT_HALTED) { channel->hcintmsk &= ~HCINT_HALTED; if (xfer->result != XFER_RESULT_INVALID) { @@ -786,15 +793,17 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h is_done = true; } else { // Re-initialize Channel + TU_ASSERT(false); } - } else if (hcint & HCINT_ACK) { - xfer->err_count = 0; - channel->hcintmsk &= ~HCINT_ACK; } else if (hcint & HCINT_DATATOGGLE_ERR) { xfer->err_count = 0; + TU_ASSERT(false); } else if (hcint & HCINT_NAK) { // NAK received, re-enable channel if request queue is available channel_send_in_token(dwc2, channel); + } else if (hcint & HCINT_ACK) { + xfer->err_count = 0; + channel->hcintmsk &= ~HCINT_ACK; } return is_done; @@ -814,7 +823,7 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t channel_disable(dwc2, channel); } else if (hcint & (HCINT_NAK | HCINT_XACT_ERR | HCINT_NYET)) { // clean up transfer so far, disable and start again later - channel_xfer_cleanup(dwc2, ch_id); + channel_xfer_wrapup(dwc2, ch_id); channel_disable(dwc2, channel); if (hcint & HCINT_XACT_ERR) { xfer->err_count++; @@ -841,8 +850,8 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t } if (is_done) { - xfer->xferred_bytes += xfer->out_fifo_bytes; - xfer->out_fifo_bytes = 0; + xfer->xferred_bytes += xfer->txfifo_bytes; + xfer->txfifo_bytes = 0; } return is_done; @@ -878,8 +887,16 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci xfer->result = XFER_RESULT_FAILED; } else { channel->hcintmsk |= HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR; - // re-init channel - TU_ASSERT(false); + edpt->next_pid = channel->hctsiz_bm.pid; // save PID + if (edpt_is_periodic(channel->hcchar_bm.ep_type)){ + // for periodic, de-allocate channel, enable SOF set frame counter for later transfer + channel_dealloc(dwc2, ch_id); + edpt->frame_countdown = edpt->frame_interval; + dwc2->gintmsk |= GINTSTS_SOF; + } else { + // for control/bulk: try again immediately + TU_ASSERT(false); + } } } else if (hcint & (HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR)) { xfer->err_count = 0; @@ -918,14 +935,14 @@ static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hc xfer->xferred_bytes += edpt->buflen; } else { xfer->result = XFER_RESULT_STALLED; - channel_xfer_cleanup(dwc2, ch_id); + channel_xfer_wrapup(dwc2, ch_id); } channel->hcintmsk &= ~HCINT_ACK; } else if (hcint & HCINT_XACT_ERR) { if (hcint & (HCINT_NAK | HCINT_NYET | HCINT_ACK)) { xfer->err_count = 0; // clean up transfer so far and start again - channel_xfer_cleanup(dwc2, ch_id); + channel_xfer_wrapup(dwc2, ch_id); channel_xfer_start(dwc2, ch_id); } else { xfer->err_count++; @@ -934,7 +951,7 @@ static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hc is_done = true; } else { // clean up transfer so far and start again - channel_xfer_cleanup(dwc2, ch_id); + channel_xfer_wrapup(dwc2, ch_id); channel_xfer_start(dwc2, ch_id); } } @@ -961,7 +978,7 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) { dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; uint32_t hcint = channel->hcint; - channel->hcint = (hcint & channel->hcintmsk); // clear enabled interrupts + channel->hcint = hcint; bool is_done; if (is_dma) { @@ -1117,6 +1134,12 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { handle_hprt_irq(rhport, in_isr); } + if (gintsts & GINTSTS_HCINT) { + // Host Channel interrupt: source is cleared in HCINT register + // must be handled after TX FIFO empty + handle_channel_irq(rhport, in_isr); + } + #if CFG_TUH_DWC2_SLAVE_ENABLE // RxFIFO non-empty interrupt handling, must be handled before HCINT if (gintsts & GINTSTS_RXFLVL) { @@ -1139,12 +1162,6 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { } } #endif - - if (gintsts & GINTSTS_HCINT) { - // Host Channel interrupt: source is cleared in HCINT register - // must bee handled after TX FIFO empty - handle_channel_irq(rhport, in_isr); - } } #endif -- cgit v1.3.1 From 56f53a61329f3a3a492530e364f543f3a419297f Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 2 Nov 2024 12:45:32 +0100 Subject: Replace cache clean/invalidate by MPU config. --- hw/bsp/imxrt/family.c | 450 +++++++++++++++++++++++++++--- hw/bsp/imxrt/family.cmake | 1 + hw/bsp/imxrt/family.mk | 3 +- src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 43 +-- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 43 --- 5 files changed, 425 insertions(+), 115 deletions(-) (limited to 'src/portable') diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index 6087ee37d..d3a228f0f 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -24,30 +24,43 @@ * This file is part of the TinyUSB stack. */ -#include "bsp/board_api.h" +#include "board.h" #include "board/clock_config.h" #include "board/pin_mux.h" -#include "board.h" +#include "bsp/board_api.h" // Suppress warning caused by mcu driver #ifdef __GNUC__ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wunused-parameter" + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wunused-parameter" #endif +#include "fsl_clock.h" #include "fsl_device_registers.h" #include "fsl_gpio.h" #include "fsl_iomuxc.h" -#include "fsl_clock.h" #include "fsl_lpuart.h" #include "fsl_ocotp.h" #ifdef __GNUC__ -#pragma GCC diagnostic pop + #pragma GCC diagnostic pop #endif +/* --- Note about USB buffer RAM --- +For M7 core it's recommanded to put USB buffer in DTCM for better performance (flexspi_nor linker default) +Otherwise you have to put the buffer in a non-cacheable section by configurate MPU manually or using BOARD_ConfigMPU(): +- Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) +- (IAR only) Change __NCACHE_REGION_SIZE in linker script to cover the size of non-cacheable section, multiple of 2^N + +For secondary M4 core, the USB controller doesn't support transfer from DTCM so OCRAM must be used: +- __NCACHE_REGION_SIZE is defined by the linker script by default +- Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) +*/ + +static void BOARD_ConfigMPU(void); + // needed by fsl_flexspi_nor_boot -TU_ATTR_USED const uint8_t dcd_data[] = { 0x00 }; +TU_ATTR_USED const uint8_t dcd_data[] = {0x00}; //--------------------------------------------------------------------+ // @@ -59,20 +72,20 @@ TU_ATTR_USED const uint8_t dcd_data[] = { 0x00 }; #endif static void init_usb_phy(uint8_t usb_id) { - USBPHY_Type* usb_phy; + USBPHY_Type *usb_phy; if (usb_id == 0) { usb_phy = USBPHY1; CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M, BOARD_XTAL0_CLK_HZ); } - #ifdef USBPHY2 +#ifdef USBPHY2 else if (usb_id == 1) { usb_phy = USBPHY2; CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ); CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M, BOARD_XTAL0_CLK_HZ); } - #endif +#endif else { return; } @@ -91,13 +104,8 @@ static void init_usb_phy(uint8_t usb_id) { usb_phy->TX = phytx; } -void board_init(void) -{ - // make sure the dcache is on. -#if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT - if (SCB_CCR_DC_Msk != (SCB_CCR_DC_Msk & SCB->CCR)) SCB_EnableDCache(); -#endif - +void board_init(void) { + BOARD_ConfigMPU(); BOARD_InitPins(); BOARD_BootClockRUN(); SystemCoreClockUpdate(); @@ -113,9 +121,9 @@ void board_init(void) #elif CFG_TUSB_OS == OPT_OS_FREERTOS // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) NVIC_SetPriority(USB_OTG1_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); -#ifdef USBPHY2 + #ifdef USBPHY2 NVIC_SetPriority(USB_OTG2_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); -#endif + #endif #endif board_led_write(true); @@ -127,19 +135,397 @@ void board_init(void) uart_config.enableTx = true; uart_config.enableRx = true; - if ( kStatus_Success != LPUART_Init(UART_PORT, &uart_config, UART_CLK_ROOT) ) { + if (kStatus_Success != LPUART_Init(UART_PORT, &uart_config, UART_CLK_ROOT)) { // failed to init uart, probably baudrate is not supported // TU_BREAKPOINT(); } //------------- USB -------------// // Note: RT105x RT106x and later have dual USB controllers. - init_usb_phy(0); // USB0 + init_usb_phy(0);// USB0 #ifdef USBPHY2 - init_usb_phy(1); // USB1 + init_usb_phy(1);// USB1 #endif } +/* MPU configuration. */ +#if __CORTEX_M == 7 +static void BOARD_ConfigMPU(void) { + #if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RW_m_ncache$$Base[]; + /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */ + extern uint32_t Image$$RW_m_ncache_unused$$Base[]; + extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[]; + uint32_t nonCacheStart = (uint32_t) Image$$RW_m_ncache$$Base; + uint32_t size = ((uint32_t) Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? 0 : ((uint32_t) Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart); + #elif defined(__MCUXPRESSO) + #if defined(__USE_SHMEM) + extern uint32_t __base_rpmsg_sh_mem; + extern uint32_t __top_rpmsg_sh_mem; + uint32_t nonCacheStart = (uint32_t) (&__base_rpmsg_sh_mem); + uint32_t size = (uint32_t) (&__top_rpmsg_sh_mem) - nonCacheStart; + #else + extern uint32_t __base_NCACHE_REGION; + extern uint32_t __top_NCACHE_REGION; + uint32_t nonCacheStart = (uint32_t) (&__base_NCACHE_REGION); + uint32_t size = (uint32_t) (&__top_NCACHE_REGION) - nonCacheStart; + #endif + #elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = (uint32_t) __NCACHE_REGION_START; + uint32_t size = (uint32_t) __NCACHE_REGION_SIZE; + #endif + volatile uint32_t i = 0; + + #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT + /* Disable I cache and D cache */ + if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR)) { + SCB_DisableICache(); + } + #endif + #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT + if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR)) { + SCB_DisableDCache(); + } + #endif + + /* Disable MPU */ + ARM_MPU_Disable(); + + /* MPU configure: + * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, + * SubRegionDisable, Size) + * API in mpu_armv7.h. + * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches + * disabled. + * param AccessPermission Data access permissions, allows you to configure read/write access for User and + * Privileged mode. + * Use MACROS defined in mpu_armv7.h: + * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO + * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes. + * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache + * 0 x 0 0 Strongly Ordered shareable + * 0 x 0 1 Device shareable + * 0 0 1 0 Normal not shareable Outer and inner write + * through no write allocate + * 0 0 1 1 Normal not shareable Outer and inner write + * back no write allocate + * 0 1 1 0 Normal shareable Outer and inner write + * through no write allocate + * 0 1 1 1 Normal shareable Outer and inner write + * back no write allocate + * 1 0 0 0 Normal not shareable outer and inner + * noncache + * 1 1 0 0 Normal shareable outer and inner + * noncache + * 1 0 1 1 Normal not shareable outer and inner write + * back write/read acllocate + * 1 1 1 1 Normal shareable outer and inner write + * back write/read acllocate + * 2 x 0 0 Device not shareable + * Above are normal use settings, if your want to see more details or want to config different inner/outer cache + * policy. + * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide + * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled. + * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in + * mpu_armv7.h. + */ + + /* + * Add default region to deny access to whole address space to workaround speculative prefetch. + * Refer to Arm errata 1013783-B for more details. + * + */ + /* Region 0 setting: Instruction access disabled, No data access permission. */ + MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB); + + /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB); + + /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */ + MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB); + + /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB); + + #if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH + /* Region 6 setting: Memory with Normal type, not shareable, write through */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Region 7 setting: Memory with Normal type, not shareable, write trough */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB); + #else + /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(7, 0x20300000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB); + #endif + + #if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1) + /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back. */ + MPU->RBAR = ARM_MPU_RBAR(8, 0x30000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB); + #endif + + #ifdef USE_SDRAM + #if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH + /* Region 9 setting: Memory with Normal type, not shareable, write trough */ + MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB); + #else + /* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */ + MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64MB); + #endif + #endif + + while ((size >> i) > 0x1U) { + i++; + } + + if (i != 0) { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(nonCacheStart % size)); + assert(size == (uint32_t) (1 << i)); + assert(i >= 5); + + /* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1); + } + + /* Region 11 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_16MB); + + /* Region 12 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(12, 0x41000000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); + + /* Region 13 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(13, 0x41400000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Region 14 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(14, 0x41800000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB); + + /* Region 15 setting: Memory with Device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(15, 0x42000000); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); + + /* Enable I cache and D cache */ + #if defined(__DCACHE_PRESENT) && __DCACHE_PRESENT + SCB_EnableDCache(); + #endif + #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT + SCB_EnableICache(); + #endif +} +#elif __CORTEX_M == 4 +void BOARD_ConfigMPU(void) { + #if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RW_m_ncache$$Base[]; + /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */ + extern uint32_t Image$$RW_m_ncache_unused$$Base[]; + extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[]; + uint32_t nonCacheStart = (uint32_t) Image$$RW_m_ncache$$Base; + uint32_t nonCacheSize = ((uint32_t) Image$$RW_m_ncache_unused$$Base == nonCacheStart) ? 0 : ((uint32_t) Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart); + #elif defined(__MCUXPRESSO) + extern uint32_t __base_NCACHE_REGION; + extern uint32_t __top_NCACHE_REGION; + uint32_t nonCacheStart = (uint32_t) (&__base_NCACHE_REGION); + uint32_t nonCacheSize = (uint32_t) (&__top_NCACHE_REGION) - nonCacheStart; + #elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __NCACHE_REGION_START[]; + extern uint32_t __NCACHE_REGION_SIZE[]; + uint32_t nonCacheStart = (uint32_t) __NCACHE_REGION_START; + uint32_t nonCacheSize = (uint32_t) __NCACHE_REGION_SIZE; + #endif + #if defined(__USE_SHMEM) + #if defined(__CC_ARM) || defined(__ARMCC_VERSION) + extern uint32_t Image$$RPMSG_SH_MEM$$Base[]; + /* RPMSG_SH_MEM_unused is a auxiliary region which is used to get the whole size of RPMSG_SH_MEM section */ + extern uint32_t Image$$RPMSG_SH_MEM_unused$$Base[]; + extern uint32_t Image$$RPMSG_SH_MEM_unused$$ZI$$Limit[]; + uint32_t rpmsgShmemStart = (uint32_t) Image$$RPMSG_SH_MEM$$Base; + uint32_t rpmsgShmemSize = (uint32_t) Image$$RPMSG_SH_MEM_unused$$ZI$$Limit - rpmsgShmemStart; + #elif defined(__MCUXPRESSO) + extern uint32_t __base_rpmsg_sh_mem; + extern uint32_t __top_rpmsg_sh_mem; + uint32_t rpmsgShmemStart = (uint32_t) (&__base_rpmsg_sh_mem); + uint32_t rpmsgShmemSize = (uint32_t) (&__top_rpmsg_sh_mem) - rpmsgShmemStart; + #elif defined(__ICCARM__) || defined(__GNUC__) + extern uint32_t __RPMSG_SH_MEM_START[]; + extern uint32_t __RPMSG_SH_MEM_SIZE[]; + uint32_t rpmsgShmemStart = (uint32_t) __RPMSG_SH_MEM_START; + uint32_t rpmsgShmemSize = (uint32_t) __RPMSG_SH_MEM_SIZE; + #endif + #endif + uint32_t i = 0; + + /* Only config non-cacheable region on system bus */ + assert(nonCacheStart >= 0x20000000); + + /* Disable code bus cache */ + if (LMEM_PCCCR_ENCACHE_MASK == (LMEM_PCCCR_ENCACHE_MASK & LMEM->PCCCR)) { + /* Enable the processor code bus to push all modified lines. */ + LMEM->PCCCR |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK | LMEM_PCCCR_GO_MASK; + /* Wait until the cache command completes. */ + while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PCCCR &= ~(LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK); + /* Now disable the cache. */ + LMEM->PCCCR &= ~LMEM_PCCCR_ENCACHE_MASK; + } + + /* Disable system bus cache */ + if (LMEM_PSCCR_ENCACHE_MASK == (LMEM_PSCCR_ENCACHE_MASK & LMEM->PSCCR)) { + /* Enable the processor system bus to push all modified lines. */ + LMEM->PSCCR |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK | LMEM_PSCCR_GO_MASK; + /* Wait until the cache command completes. */ + while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PSCCR &= ~(LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK); + /* Now disable the cache. */ + LMEM->PSCCR &= ~LMEM_PSCCR_ENCACHE_MASK; + } + + /* Disable MPU */ + ARM_MPU_Disable(); + + #if defined(CACHE_MODE_WRITE_THROUGH) && CACHE_MODE_WRITE_THROUGH + /* Region 0 setting: Memory with Normal type, not shareable, write trough */ + MPU->RBAR = ARM_MPU_RBAR(0, 0x20200000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_1MB); + + /* Region 1 setting: Memory with Normal type, not shareable, write through */ + MPU->RBAR = ARM_MPU_RBAR(1, 0x20300000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_512KB); + + /* Region 2 setting: Memory with Normal type, not shareable, write through */ + MPU->RBAR = ARM_MPU_RBAR(2, 0x80000000U); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 0, 0, ARM_MPU_REGION_SIZE_64MB); + + while ((nonCacheSize >> i) > 0x1U) { + i++; + } + + if (i != 0) { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(nonCacheStart % nonCacheSize)); + assert(nonCacheSize == (uint32_t) (1 << i)); + assert(i >= 5); + + /* Region 3 setting: Memory with device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(3, nonCacheStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1); + } + + #if defined(__USE_SHMEM) + i = 0; + + while ((rpmsgShmemSize >> i) > 0x1U) { + i++; + } + + if (i != 0) { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(rpmsgShmemStart % rpmsgShmemSize)); + assert(rpmsgShmemSize == (uint32_t) (1 << i)); + assert(i >= 5); + + /* Region 4 setting: Memory with device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(4, rpmsgShmemStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1); + } + #endif + #else + while ((nonCacheSize >> i) > 0x1U) { + i++; + } + + if (i != 0) { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(nonCacheStart % nonCacheSize)); + assert(nonCacheSize == (uint32_t) (1 << i)); + assert(i >= 5); + + /* Region 0 setting: Memory with device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(0, nonCacheStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1); + } + + #if defined(__USE_SHMEM) + i = 0; + + while ((rpmsgShmemSize >> i) > 0x1U) { + i++; + } + + if (i != 0) { + /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */ + assert(!(rpmsgShmemStart % rpmsgShmemSize)); + assert(rpmsgShmemSize == (uint32_t) (1 << i)); + assert(i >= 5); + + /* Region 1 setting: Memory with device type, not shareable, non-cacheable */ + MPU->RBAR = ARM_MPU_RBAR(1, rpmsgShmemStart); + MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, i - 1); + } + #endif + #endif + + /* Enable MPU */ + ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk); + + /* Enables the processor system bus to invalidate all lines in both ways. + and Initiate the processor system bus cache command. */ + LMEM->PSCCR |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_GO_MASK; + /* Wait until the cache command completes */ + while ((LMEM->PSCCR & LMEM_PSCCR_GO_MASK) != 0U) { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PSCCR &= ~(LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK); + /* Now enable the system bus cache. */ + LMEM->PSCCR |= LMEM_PSCCR_ENCACHE_MASK; + + /* Enables the processor code bus to invalidate all lines in both ways. + and Initiate the processor code bus code cache command. */ + LMEM->PCCCR |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_GO_MASK; + /* Wait until the cache command completes. */ + while ((LMEM->PCCCR & LMEM_PCCCR_GO_MASK) != 0U) { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + LMEM->PCCCR &= ~(LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK); + /* Now enable the code bus cache. */ + LMEM->PCCCR |= LMEM_PCCCR_ENCACHE_MASK; +} +#endif + //--------------------------------------------------------------------+ // USB Interrupt Handler //--------------------------------------------------------------------+ @@ -166,18 +552,18 @@ uint32_t board_button_read(void) { size_t board_get_unique_id(uint8_t id[], size_t max_len) { (void) max_len; - #if FSL_FEATURE_OCOTP_HAS_TIMING_CTRL +#if FSL_FEATURE_OCOTP_HAS_TIMING_CTRL OCOTP_Init(OCOTP, CLOCK_GetFreq(kCLOCK_IpgClk)); - #else +#else OCOTP_Init(OCOTP, 0u); - #endif +#endif // Reads shadow registers 0x01 - 0x04 (Configuration and Manufacturing Info) // into 8 bit wide destination, avoiding punning. for (int i = 0; i < 4; ++i) { uint32_t wr = OCOTP_ReadFuseShadowRegister(OCOTP, i + 1); for (int j = 0; j < 4; j++) { - id[i*4+j] = wr & 0xff; + id[i * 4 + j] = wr & 0xff; wr >>= 8; } } @@ -186,7 +572,7 @@ size_t board_get_unique_id(uint8_t id[], size_t max_len) { return 16; } -int board_uart_read(uint8_t* buf, int len) { +int board_uart_read(uint8_t *buf, int len) { int count = 0; while (count < len) { @@ -209,8 +595,8 @@ int board_uart_read(uint8_t* buf, int len) { return count; } -int board_uart_write(void const * buf, int len) { - LPUART_WriteBlocking(UART_PORT, (uint8_t const*)buf, len); +int board_uart_write(void const *buf, int len) { + LPUART_WriteBlocking(UART_PORT, (uint8_t const *) buf, len); return len; } @@ -236,10 +622,10 @@ TU_ATTR_UNUSED void _start(void) { while (1) {} } -#ifdef __clang__ -void _exit (int __status) { + #ifdef __clang__ +void _exit(int __status) { while (1) {} } -#endif + #endif #endif diff --git a/hw/bsp/imxrt/family.cmake b/hw/bsp/imxrt/family.cmake index d917e9777..436d6e6a3 100644 --- a/hw/bsp/imxrt/family.cmake +++ b/hw/bsp/imxrt/family.cmake @@ -64,6 +64,7 @@ function(add_board_target BOARD_TARGET) XIP_EXTERNAL_FLASH=1 XIP_BOOT_HEADER_ENABLE=1 __STARTUP_CLEAR_BSS + CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) ) target_include_directories(${BOARD_TARGET} PUBLIC ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} diff --git a/hw/bsp/imxrt/family.mk b/hw/bsp/imxrt/family.mk index f00afb6a4..45c3ad31d 100644 --- a/hw/bsp/imxrt/family.mk +++ b/hw/bsp/imxrt/family.mk @@ -14,7 +14,8 @@ CFLAGS += \ -D__STARTUP_CLEAR_BSS \ -DXIP_EXTERNAL_FLASH=1 \ -DXIP_BOOT_HEADER_ENABLE=1 \ - -DCFG_TUSB_MCU=OPT_MCU_MIMXRT1XXX + -DCFG_TUSB_MCU=OPT_MCU_MIMXRT1XXX \ + -DCFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) \ ifdef BOARD_TUD_RHPORT CFLAGS += -DBOARD_TUD_RHPORT=$(BOARD_TUD_RHPORT) diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h index c59c107ff..201936e53 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h +++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h @@ -56,46 +56,11 @@ static const ci_hs_controller_t _ci_controller[] = #define CI_HS_REG(_port) ((ci_hs_regs_t*) _ci_controller[_port].reg_base) //------------- DCD -------------// -#define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum) -#define CI_DCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum) +#define CI_DCD_INT_ENABLE(_p) NVIC_EnableIRQ ((IRQn_Type)_ci_controller[_p].irqnum) +#define CI_DCD_INT_DISABLE(_p) NVIC_DisableIRQ((IRQn_Type)_ci_controller[_p].irqnum) //------------- HCD -------------// -#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ (_ci_controller[_p].irqnum) -#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ(_ci_controller[_p].irqnum) - -//------------- DCache -------------// -TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uintptr_t addr) { - return !(0x20000000 <= addr && addr < 0x20100000); -} - -TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean(void const* addr, uint32_t data_size) { - const uintptr_t addr32 = (uintptr_t) addr; - if (imxrt_is_cache_mem(addr32)) { - TU_ASSERT(tu_is_aligned32(addr32)); - SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size); - } - return true; -} - -TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_invalidate(void const* addr, uint32_t data_size) { - const uintptr_t addr32 = (uintptr_t) addr; - if (imxrt_is_cache_mem(addr32)) { - // Invalidating does not push cached changes back to RAM so we need to be - // *very* careful when we do it. If we're not aligned, then we risk resetting - // values back to their RAM state. - TU_ASSERT(tu_is_aligned32(addr32)); - SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size); - } - return true; -} - -TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean_invalidate(void const* addr, uint32_t data_size) { - const uintptr_t addr32 = (uintptr_t) addr; - if (imxrt_is_cache_mem(addr32)) { - TU_ASSERT(tu_is_aligned32(addr32)); - SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size); - } - return true; -} +#define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ ((IRQn_Type)_ci_controller[_p].irqnum) +#define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ((IRQn_Type)_ci_controller[_p].irqnum) #endif diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index 430a0aad1..76b78cb57 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -33,19 +33,6 @@ #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX #include "ci_hs_imxrt.h" - - void dcd_dcache_clean(void const* addr, uint32_t data_size) { - imxrt_dcache_clean(addr, data_size); - } - - void dcd_dcache_invalidate(void const* addr, uint32_t data_size) { - imxrt_dcache_invalidate(addr, data_size); - } - - void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { - imxrt_dcache_clean_invalidate(addr, data_size); - } - #else #if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) @@ -57,18 +44,6 @@ #else #error "Unsupported MCUs" #endif - - TU_ATTR_WEAK void dcd_dcache_clean(void const* addr, uint32_t data_size) { - (void) addr; (void) data_size; - } - - TU_ATTR_WEAK void dcd_dcache_invalidate(void const* addr, uint32_t data_size) { - (void) addr; (void) data_size; - } - - TU_ATTR_WEAK void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { - (void) addr; (void) data_size; - } #endif //--------------------------------------------------------------------+ @@ -230,8 +205,6 @@ static void bus_reset(uint8_t rhport) _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID; _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only - - dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); } bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { @@ -257,8 +230,6 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED; #endif - dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); - dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment dcd_reg->USBSTS = dcd_reg->USBSTS; dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_SUSPEND; @@ -325,10 +296,6 @@ void dcd_sof_enable(uint8_t rhport, bool en) static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes) { - // Force the CPU to flush the buffer. We increase the size by 31 because the call aligns the - // address to 32-byte boundaries. Buffer must be word aligned - dcd_dcache_clean_invalidate((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes + 31); - tu_memclr(p_qtd, sizeof(dcd_qtd_t)); p_qtd->next = QTD_NEXT_INVALID; @@ -402,8 +369,6 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) p_qhd->qtd_overlay.next = QTD_NEXT_INVALID; - dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); - // Enable EP Control uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET; @@ -461,9 +426,6 @@ static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir) p_qhd->qtd_overlay.halted = false; // clear any previous error p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd - // flush cache - dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); - if ( epnum == 0 ) { // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism @@ -539,8 +501,6 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 page++; } } - - dcd_dcache_clean_invalidate((uint32_t*) tu_align((uint32_t) fifo_info.ptr_wrap, 4), total_bytes - fifo_info.len_wrap + 31); } else { @@ -652,9 +612,6 @@ void dcd_int_handler(uint8_t rhport) if (int_status & INTR_USB) { - // Make sure we read the latest version of _dcd_data. - dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); - uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE; dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge -- cgit v1.3.1 From 5d6d905cb063f7a4f13cf0c8160dbf6371e70e4c Mon Sep 17 00:00:00 2001 From: hathach Date: Sat, 2 Nov 2024 20:20:27 +0700 Subject: got interrupt in working with slave --- src/portable/synopsys/dwc2/hcd_dwc2.c | 71 +++++++++++++++++++++++------------ 1 file changed, 46 insertions(+), 25 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 42a5b9fbd..8bfba442b 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -80,8 +80,9 @@ typedef struct { volatile bool allocated; uint8_t ep_id; union TU_ATTR_PACKED { - uint8_t err_count : 7; + uint8_t err_count : 6; uint8_t do_ping : 1; + uint8_t sof_schedule : 1; }; uint8_t result; @@ -681,6 +682,31 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { //-------------------------------------------------------------------- // HCD Event Handler //-------------------------------------------------------------------- +static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcint) { + hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; + dwc2_channel_t* channel = &dwc2->channel[ch_id]; + hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; + + if (edpt_is_periodic(channel->hcchar_bm.ep_type)){ + // for periodic, de-allocate channel, enable SOF set frame counter for later transfer + edpt->next_pid = channel->hctsiz_bm.pid; // save PID + edpt->frame_countdown = edpt->frame_interval; + dwc2->gintmsk |= GINTSTS_SOF; + + if (hcint & HCINT_HALTED) { + // already halted, de-allocate channel (called from DMA isr) + channel_dealloc(dwc2, ch_id); + } else { + // disable channel first if not halted (called slave isr) + xfer->sof_schedule = 1; + channel_disable(dwc2, channel); + } + } else { + // for control/bulk: try again immediately + channel_send_in_token(dwc2, channel); + } +} + #if CFG_TUH_DWC2_SLAVE_ENABLE static void handle_rxflvl_irq(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); @@ -770,6 +796,8 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h dwc2_channel_t* channel = &dwc2->channel[ch_id]; bool is_done = false; +// TU_LOG1("ch%u: ep = %u, hcint = 0x%04lX\r\n", ch_id, channel->hcchar_bm.ep_num, hcint); + if (hcint & HCINT_XFER_COMPLETE) { xfer->result = XFER_RESULT_SUCCESS; channel_disable(dwc2, channel); @@ -786,21 +814,23 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h channel_disable(dwc2, channel); } else if (hcint & HCINT_HALTED) { channel->hcintmsk &= ~HCINT_HALTED; - if (xfer->result != XFER_RESULT_INVALID) { + if (xfer->sof_schedule) { + // de-allocate channel but does not complete xfer, we schedule it in the SOF interrupt + channel_dealloc(dwc2, ch_id); + } else if (xfer->result != XFER_RESULT_INVALID) { is_done = true; } else if (channel->hcchar_bm.err_multi_count == HCD_XFER_ERROR_MAX) { xfer->result = XFER_RESULT_FAILED; is_done = true; } else { - // Re-initialize Channel - TU_ASSERT(false); + channel_xfer_in_retry(dwc2, ch_id, hcint); } } else if (hcint & HCINT_DATATOGGLE_ERR) { xfer->err_count = 0; TU_ASSERT(false); } else if (hcint & HCINT_NAK) { // NAK received, re-enable channel if request queue is available - channel_send_in_token(dwc2, channel); + channel_xfer_in_retry(dwc2, ch_id, hcint); } else if (hcint & HCINT_ACK) { xfer->err_count = 0; channel->hcintmsk &= ~HCINT_ACK; @@ -887,31 +917,13 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci xfer->result = XFER_RESULT_FAILED; } else { channel->hcintmsk |= HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR; - edpt->next_pid = channel->hctsiz_bm.pid; // save PID - if (edpt_is_periodic(channel->hcchar_bm.ep_type)){ - // for periodic, de-allocate channel, enable SOF set frame counter for later transfer - channel_dealloc(dwc2, ch_id); - edpt->frame_countdown = edpt->frame_interval; - dwc2->gintmsk |= GINTSTS_SOF; - } else { - // for control/bulk: try again immediately - TU_ASSERT(false); - } + channel_xfer_in_retry(dwc2, ch_id, hcint); } } else if (hcint & (HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR)) { xfer->err_count = 0; channel->hcintmsk &= ~(HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR); if ((hcint & (HCINT_NAK | HCINT_DATATOGGLE_ERR))) { - edpt->next_pid = channel->hctsiz_bm.pid; // save PID - if (edpt_is_periodic(channel->hcchar_bm.ep_type)){ - // for periodic, de-allocate channel, enable SOF set frame counter for later transfer - channel_dealloc(dwc2, ch_id); - edpt->frame_countdown = edpt->frame_interval; - dwc2->gintmsk |= GINTSTS_SOF; - } else { - // for control/bulk: try again immediately - TU_ASSERT(false); - } + channel_xfer_in_retry(dwc2, ch_id, hcint); } } } @@ -1161,6 +1173,15 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { dwc2->gintmsk &= ~GINTSTS_NPTX_FIFO_EMPTY; } } + + if (gintsts & GINTSTS_PTX_FIFO_EMPTY) { + // PTX FIFO empty interrupt, this is read-only and cleared by hardware when FIFO is written + const bool more_ptxfe = handle_txfifo_empty(dwc2, true); + if (!more_ptxfe) { + // no more pending packet, disable interrupt + dwc2->gintmsk &= ~GINTSTS_PTX_FIFO_EMPTY; + } + } #endif } -- cgit v1.3.1 From 29262f3e24326c1a7c06137824e44ffaa6301094 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 4 Nov 2024 17:22:25 +0700 Subject: improve port0_enable(), properly configure hcfg and hfir according to port speed. Enable low power UTMI+ phy mode for ls/fs device. --- src/portable/synopsys/dwc2/dwc2_type.h | 4 ++ src/portable/synopsys/dwc2/hcd_dwc2.c | 115 +++++++++++++++++---------------- 2 files changed, 63 insertions(+), 56 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 89561a5e6..a88a2d389 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -730,6 +730,7 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define HCFG_FSLS_PHYCLK_SEL HCFG_FSLS_PHYCLK_SEL_Msk // FS/LS PHY clock select #define HCFG_FSLS_PHYCLK_SEL_30_60MHZ (0x0UL << HCFG_FSLS_PHYCLK_SEL_Pos) // 0x00000000 #define HCFG_FSLS_PHYCLK_SEL_48MHZ (0x1UL << HCFG_FSLS_PHYCLK_SEL_Pos) // 0x00000001 +#define HCFG_FSLS_PHYCLK_SEL_6MHZ (0x2UL << HCFG_FSLS_PHYCLK_SEL_Pos) // 0x00000002 #define HCFG_FSLS_ONLY_Pos (2U) #define HCFG_FSLS_ONLY_Msk (0x1UL << HCFG_FSLS_ONLY_Pos) // 0x00000004 @@ -848,6 +849,9 @@ TU_VERIFY_STATIC(offsetof(dwc2_regs_t, fifo ) == 0x1000, "incorrect size"); #define HFIR_FRIVL_Pos (0U) #define HFIR_FRIVL_Msk (0xFFFFUL << HFIR_FRIVL_Pos) // 0x0000FFFF #define HFIR_FRIVL HFIR_FRIVL_Msk // Frame interval +#define HFIR_RELOAD_CTRL_Pos (16U) // available since v2.92a +#define HFIR_RELOAD_CTRL_Msk (0x1UL << HFIR_RELOAD_CTRL_Pos) +#define HFIR_RELOAD_CTRL HFIR_RELOAD_CTRL_Msk /******************** Bit definition for HFNUM register ********************/ #define HFNUM_FRNUM_Pos (0U) diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 8bfba442b..b2ca86a36 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -45,7 +45,7 @@ TU_VERIFY_STATIC(CFG_TUH_DWC2_ENDPOINT_MAX <= 255, "currently only use 8-bit for index"); enum { - HPRT_W1C_MASK = HPRT_CONN_DETECT | HPRT_ENABLE | HPRT_ENABLE_CHANGE | HPRT_OVER_CURRENT_CHANGE + HPRT_W1_MASK = HPRT_CONN_DETECT | HPRT_ENABLE | HPRT_ENABLE_CHANGE | HPRT_OVER_CURRENT_CHANGE | HPRT_SUSPEND }; enum { @@ -79,7 +79,7 @@ typedef struct { typedef struct { volatile bool allocated; uint8_t ep_id; - union TU_ATTR_PACKED { + struct TU_ATTR_PACKED { uint8_t err_count : 6; uint8_t do_ping : 1; uint8_t sof_schedule : 1; @@ -336,26 +336,13 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { //------------- 3.1 Host Initialization -------------// - // FS/LS PHY Clock Select - uint32_t hcfg = dwc2->hcfg; - if (is_highspeed) { - hcfg &= ~HCFG_FSLS_ONLY; - } else { - hcfg &= ~HCFG_FSLS_ONLY; // since we are using FS PHY - hcfg &= ~HCFG_FSLS_PHYCLK_SEL; - - if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI && - dwc2->ghwcfg2_bm.fs_phy_type == GHWCFG2_FSPHY_DEDICATED) { - // dedicated FS PHY with 48 mhz - hcfg |= HCFG_FSLS_PHYCLK_SEL_48MHZ; - } else { - // shared HS PHY running at full speed - hcfg |= HCFG_FSLS_PHYCLK_SEL_30_60MHZ; - } - } - dwc2->hcfg = hcfg; + // work at max supported speed + dwc2->hcfg &= ~HCFG_FSLS_ONLY; // Enable HFIR reload + if (dwc2->gsnpsid >= DWC2_CORE_REV_2_92a) { + dwc2->hfir |= HFIR_RELOAD_CTRL; + } // force host mode and wait for mode switch dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FDMOD) | GUSBCFG_FHMOD; @@ -364,7 +351,7 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // configure fixed-allocated fifo scheme dfifo_host_init(rhport); - dwc2->hprt = HPRT_W1C_MASK; // clear all write-1-clear bits + dwc2->hprt = HPRT_W1_MASK; // clear all write-1-clear bits dwc2->hprt = HPRT_POWER; // turn on VBUS // Enable required interrupts @@ -408,7 +395,7 @@ bool hcd_port_connect_status(uint8_t rhport) { // Some port would require hcd_port_reset_end() to be invoked after 10ms to complete the reset sequence. void hcd_port_reset(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint32_t hprt = dwc2->hprt & ~HPRT_W1C_MASK; + uint32_t hprt = dwc2->hprt & ~HPRT_W1_MASK; hprt |= HPRT_RESET; dwc2->hprt = hprt; } @@ -416,7 +403,7 @@ void hcd_port_reset(uint8_t rhport) { // Complete bus reset sequence, may be required by some controllers void hcd_port_reset_end(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint32_t hprt = dwc2->hprt & ~HPRT_W1C_MASK; // skip w1c bits + uint32_t hprt = dwc2->hprt & ~HPRT_W1_MASK; // skip w1c bits hprt &= ~HPRT_RESET; dwc2->hprt = hprt; } @@ -1044,6 +1031,50 @@ static bool handle_sof_irq(uint8_t rhport, bool in_isr) { return more_isr; } +// Config HCFG FS/LS clock and HFIR for SOF interval according to link speed (value is in PHY clock unit) +static void port0_enable(dwc2_regs_t* dwc2, tusb_speed_t speed) { + uint32_t hcfg = dwc2->hcfg & ~HCFG_FSLS_PHYCLK_SEL; + + const dwc2_gusbcfg_t gusbcfg_bm = dwc2->gusbcfg_bm; + uint32_t phy_clock; + + if (gusbcfg_bm.phy_sel) { + phy_clock = 48; // dedicated FS is 48Mhz + if (speed == TUSB_SPEED_LOW) { + hcfg |= HCFG_FSLS_PHYCLK_SEL_6MHZ; + } else { + hcfg |= HCFG_FSLS_PHYCLK_SEL_48MHZ; + } + } else { + if (gusbcfg_bm.ulpi_utmi_sel) { + phy_clock = 60; // ULPI 8-bit is 60Mhz + } else { + // UTMI+ 16-bit is 30Mhz, 8-bit is 60Mhz + phy_clock = gusbcfg_bm.phy_if16 ? 30 : 60; + + // Enable UTMI+ low power mode 48Mhz external clock if not highspeed + if (speed == TUSB_SPEED_HIGH) { + dwc2->gusbcfg &= ~GUSBCFG_PHYLPCS; + } else { + dwc2->gusbcfg |= GUSBCFG_PHYLPCS; + // may need to reset port + } + } + hcfg |= HCFG_FSLS_PHYCLK_SEL_30_60MHZ; + } + + dwc2->hcfg = hcfg; + + uint32_t hfir = dwc2->hfir & ~HFIR_FRIVL_Msk; + if (speed == TUSB_SPEED_HIGH) { + hfir |= 125*phy_clock; + } else { + hfir |= 1000*phy_clock; + } + + dwc2->hfir = hfir; +} + /* Handle Host Port interrupt, possible source are: - Connection Detection - Enable Change @@ -1051,7 +1082,7 @@ static bool handle_sof_irq(uint8_t rhport, bool in_isr) { */ static void handle_hprt_irq(uint8_t rhport, bool in_isr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint32_t hprt = dwc2->hprt & ~HPRT_W1C_MASK; + uint32_t hprt = dwc2->hprt & ~HPRT_W1_MASK; const dwc2_hprt_t hprt_bm = dwc2->hprt_bm; if (dwc2->hprt & HPRT_CONN_DETECT) { @@ -1071,38 +1102,10 @@ static void handle_hprt_irq(uint8_t rhport, bool in_isr) { if (hprt_bm.enable) { // Port enable - // Config HCFG FS/LS clock and HFIR for SOF interval according to link speed (value is in PHY clock unit) const tusb_speed_t speed = convert_hprt_speed(hprt_bm.speed); - uint32_t hcfg = dwc2->hcfg & ~HCFG_FSLS_PHYCLK_SEL; - - const dwc2_gusbcfg_t gusbcfg_bm = dwc2->gusbcfg_bm; - uint32_t clock = 60; - if (gusbcfg_bm.phy_sel) { - // dedicated FS is 48Mhz - clock = 48; - hcfg |= HCFG_FSLS_PHYCLK_SEL_48MHZ; - } else { - // UTMI+ or ULPI - if (gusbcfg_bm.ulpi_utmi_sel) { - clock = 60; // ULPI 8-bit is 60Mhz - } else if (gusbcfg_bm.phy_if16) { - clock = 30; // UTMI+ 16-bit is 30Mhz - } else { - clock = 60; // UTMI+ 8-bit is 60Mhz - } - hcfg |= HCFG_FSLS_PHYCLK_SEL_30_60MHZ; - } - - dwc2->hcfg = hcfg; - - uint32_t hfir = dwc2->hfir & ~HFIR_FRIVL_Msk; - if (speed == TUSB_SPEED_HIGH) { - hfir |= 125*clock; - } else { - hfir |= 1000*clock; - } - - dwc2->hfir = hfir; + port0_enable(dwc2, speed); + } else { + // TU_ASSERT(false, ); } } @@ -1121,7 +1124,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { const uint32_t gintmsk = dwc2->gintmsk; const uint32_t gintsts = dwc2->gintsts & gintmsk; - // TU_LOG1_HEX(int_status); + // TU_LOG1_HEX(gintsts); if (gintsts & GINTSTS_CONIDSTSCHNG) { // Connector ID status change -- cgit v1.3.1 From 372db1e19a28458110b250a3149b585f8dabbfff Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 5 Nov 2024 10:37:39 +0700 Subject: implement split transaction, got control working --- src/portable/synopsys/dwc2/hcd_dwc2.c | 89 +++++++++++++++++++++++++---------- 1 file changed, 65 insertions(+), 24 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index b2ca86a36..3527f682e 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -432,8 +432,8 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { // Open an endpoint bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* desc_ep) { - (void) rhport; - //dwc2_regs_t* dwc2 = DWC2_REG(rhport); + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + const tusb_speed_t rh_speed = convert_hprt_speed(dwc2->hprt_bm.speed); hcd_devtree_info_t devtree_info; hcd_devtree_get_info(dev_addr, &devtree_info); @@ -460,7 +460,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* hcsplt_bm->hub_addr = devtree_info.hub_addr; hcsplt_bm->xact_pos = 0; hcsplt_bm->split_compl = 0; - hcsplt_bm->split_en = 0; + hcsplt_bm->split_en = (rh_speed == TUSB_SPEED_HIGH && devtree_info.speed != TUSB_SPEED_HIGH) ? 1 : 0; edpt->next_pid = HCTSIZ_PID_DATA0; if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) { @@ -477,7 +477,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* } // clean up channel after part of transfer is done but the whole urb is not complete -static void channel_xfer_wrapup(dwc2_regs_t* dwc2, uint8_t ch_id) { +static void channel_xfer_out_wrapup(dwc2_regs_t* dwc2, uint8_t ch_id) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; @@ -490,14 +490,10 @@ static void channel_xfer_wrapup(dwc2_regs_t* dwc2, uint8_t ch_id) { * number of packets that have been transferred via the USB. This is always an integral number of packets if the * transfer was halted before its normal completion. */ - uint16_t actual_bytes; - if (channel->hcchar_bm.ep_dir == TUSB_DIR_IN) { - actual_bytes = edpt->buflen - channel->hctsiz_bm.xfer_size; - } else { - const uint16_t remain_packets = channel->hctsiz_bm.packet_count; - const uint16_t total_packets = cal_packet_count(edpt->buflen, channel->hcchar_bm.ep_size); - actual_bytes = (total_packets - remain_packets) * channel->hcchar_bm.ep_size; - } + const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + const uint16_t total_packets = cal_packet_count(edpt->buflen, channel->hcchar_bm.ep_size); + const uint16_t actual_bytes = (total_packets - remain_packets) * channel->hcchar_bm.ep_size; + xfer->txfifo_bytes = 0; xfer->xferred_bytes += actual_bytes; edpt->buffer += actual_bytes; @@ -540,9 +536,7 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { edpt->next_pid = cal_next_pid(edpt->next_pid, packet_count); } - // split: TODO support later channel->hcsplt = edpt->hcsplt; - channel->hcint = 0xFFFFFFFFU; // clear all channel interrupts if (dma_host_enabled(dwc2)) { @@ -690,6 +684,9 @@ static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci } } else { // for control/bulk: try again immediately + if (channel->hcsplt_bm.split_en) { + channel->hcsplt_bm.split_compl = 0; // retry with start split + } channel_send_in_token(dwc2, channel); } } @@ -840,7 +837,7 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t channel_disable(dwc2, channel); } else if (hcint & (HCINT_NAK | HCINT_XACT_ERR | HCINT_NYET)) { // clean up transfer so far, disable and start again later - channel_xfer_wrapup(dwc2, ch_id); + channel_xfer_out_wrapup(dwc2, ch_id); channel_disable(dwc2, channel); if (hcint & HCINT_XACT_ERR) { xfer->err_count++; @@ -883,19 +880,33 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci bool is_done = false; + // TU_LOG1("in hcint = %02lX\r\n", hcint); + if (hcint & HCINT_HALTED) { if (hcint & (HCINT_XFER_COMPLETE | HCINT_STALL | HCINT_BABBLE_ERR)) { - is_done = true; - xfer->err_count = 0; const uint16_t remain_bytes = (uint16_t) channel->hctsiz_bm.xfer_size; - xfer->xferred_bytes += (edpt->buflen - remain_bytes); + const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + const uint16_t actual_len = edpt->buflen - remain_bytes; + xfer->xferred_bytes += actual_len; + + is_done = true; + if (hcint & HCINT_STALL) { xfer->result = XFER_RESULT_STALLED; } else if (hcint & HCINT_BABBLE_ERR) { xfer->result = XFER_RESULT_FAILED; + } else if (channel->hcsplt_bm.split_en && remain_packets && actual_len == edpt->hcchar_bm.ep_size) { + // Split can only complete 1 transaction (up to 1 packet) at a time, schedule more + is_done = false; + edpt->buffer += actual_len; + edpt->buflen -= actual_len; + + channel_xfer_in_retry(dwc2, ch_id, hcint); } else { xfer->result = XFER_RESULT_SUCCESS; } + + xfer->err_count = 0; channel->hcintmsk &= ~HCINT_ACK; } else if (hcint & HCINT_XACT_ERR) { xfer->err_count++; @@ -906,12 +917,27 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci channel->hcintmsk |= HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR; channel_xfer_in_retry(dwc2, ch_id, hcint); } - } else if (hcint & (HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR)) { + } else if (hcint & (HCINT_NAK | HCINT_DATATOGGLE_ERR)) { xfer->err_count = 0; - channel->hcintmsk &= ~(HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR); + channel->hcintmsk &= ~(HCINT_NAK | HCINT_DATATOGGLE_ERR); if ((hcint & (HCINT_NAK | HCINT_DATATOGGLE_ERR))) { channel_xfer_in_retry(dwc2, ch_id, hcint); } + } else if (hcint & HCINT_ACK) { + xfer->err_count = 0; + channel->hcintmsk &= ~HCINT_ACK; + + if (channel->hcsplt_bm.split_en && !channel->hcsplt_bm.split_compl) { + // start split is ACK --> do complete split + channel->hcsplt_bm.split_compl = 1; + channel_send_in_token(dwc2, channel); + } + } else if (hcint & HCINT_NYET) { + if (channel->hcsplt_bm.split_en && channel->hcsplt_bm.split_compl) { + // split not yet mean hub has no data, retry complete split + channel->hcsplt_bm.split_compl = 1; + channel_send_in_token(dwc2, channel); + } } } @@ -925,6 +951,8 @@ static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hc bool is_done = false; + // TU_LOG1("out hcint = %02lX\r\n", hcint); + if (hcint & HCINT_HALTED) { if (hcint & (HCINT_XFER_COMPLETE | HCINT_STALL)) { is_done = true; @@ -934,14 +962,14 @@ static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hc xfer->xferred_bytes += edpt->buflen; } else { xfer->result = XFER_RESULT_STALLED; - channel_xfer_wrapup(dwc2, ch_id); + channel_xfer_out_wrapup(dwc2, ch_id); } channel->hcintmsk &= ~HCINT_ACK; } else if (hcint & HCINT_XACT_ERR) { if (hcint & (HCINT_NAK | HCINT_NYET | HCINT_ACK)) { xfer->err_count = 0; // clean up transfer so far and start again - channel_xfer_wrapup(dwc2, ch_id); + channel_xfer_out_wrapup(dwc2, ch_id); channel_xfer_start(dwc2, ch_id); } else { xfer->err_count++; @@ -950,10 +978,23 @@ static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hc is_done = true; } else { // clean up transfer so far and start again - channel_xfer_wrapup(dwc2, ch_id); + channel_xfer_out_wrapup(dwc2, ch_id); channel_xfer_start(dwc2, ch_id); } } + } else if (hcint & HCINT_ACK) { + xfer->err_count = 0; + if (channel->hcsplt_bm.split_en && !channel->hcsplt_bm.split_compl) { + // start split is ACK --> do complete split + channel->hcsplt_bm.split_compl = 1; + channel->hcchar |= HCCHAR_CHENA; + } + } else if (hcint & HCINT_NYET) { + if (channel->hcsplt_bm.split_en && channel->hcsplt_bm.split_compl) { + // split not yet mean hub has no data, retry complete split + channel->hcsplt_bm.split_compl = 1; + channel->hcchar |= HCCHAR_CHENA; + } } } else if (hcint & HCINT_ACK) { xfer->err_count = 0; @@ -969,7 +1010,7 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) { const bool is_dma = dma_host_enabled(dwc2); const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); - for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { // + for (uint8_t ch_id = 0; ch_id < max_channel; ch_id++) { if (tu_bit_test(dwc2->haint, ch_id)) { dwc2_channel_t* channel = &dwc2->channel[ch_id]; hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; -- cgit v1.3.1 From fbc193647a69c749c43b6ea69733f144000c8a89 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 5 Nov 2024 16:26:56 +0700 Subject: split interrupt work with fs mouse --- src/portable/synopsys/dwc2/hcd_dwc2.c | 115 ++++++++++++++++++++++------------ 1 file changed, 74 insertions(+), 41 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 3527f682e..fa8269132 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -52,6 +52,10 @@ enum { HCD_XFER_ERROR_MAX = 3 }; +enum { + HCD_XFER_PERIOD_SPLIT_NYET_MAX = 3 +}; + //-------------------------------------------------------------------- // //-------------------------------------------------------------------- @@ -67,9 +71,12 @@ typedef struct { dwc2_channel_split_t hcsplt_bm; }; - uint8_t next_pid; - uint16_t frame_interval; - uint16_t frame_countdown; // count down to make a transfer for periodic endpoint (from interval) + struct TU_ATTR_PACKED { + uint32_t uframe_interval : 18; // micro-frame interval + uint32_t next_pid : 2; + }; + + uint32_t uframe_countdown; // micro-frame count down to transfer for periodic, only need 18-bit uint8_t* buffer; uint16_t buflen; @@ -80,7 +87,8 @@ typedef struct { volatile bool allocated; uint8_t ep_id; struct TU_ATTR_PACKED { - uint8_t err_count : 6; + uint8_t err_count : 3; + uint8_t period_split_nyet_count : 3; uint8_t do_ping : 1; uint8_t sof_schedule : 1; }; @@ -101,9 +109,9 @@ hcd_data_t _hcd_data; //-------------------------------------------------------------------- // //-------------------------------------------------------------------- -TU_ATTR_ALWAYS_INLINE static inline tusb_speed_t convert_hprt_speed(uint32_t hprt_speed) { +TU_ATTR_ALWAYS_INLINE static inline tusb_speed_t hprt_speed_get(dwc2_regs_t* dwc2) { tusb_speed_t speed; - switch(hprt_speed) { + switch(dwc2->hprt_bm.speed) { case HPRT_SPEED_HIGH: speed = TUSB_SPEED_HIGH; break; case HPRT_SPEED_FULL: speed = TUSB_SPEED_FULL; break; case HPRT_SPEED_LOW : speed = TUSB_SPEED_LOW ; break; @@ -411,7 +419,7 @@ void hcd_port_reset_end(uint8_t rhport) { // Get port link speed tusb_speed_t hcd_port_speed_get(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - const tusb_speed_t speed = convert_hprt_speed(dwc2->hprt_bm.speed); + const tusb_speed_t speed = hprt_speed_get(dwc2); return speed; } @@ -433,7 +441,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { // Open an endpoint bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* desc_ep) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - const tusb_speed_t rh_speed = convert_hprt_speed(dwc2->hprt_bm.speed); + const tusb_speed_t rh_speed = hprt_speed_get(dwc2); hcd_devtree_info_t devtree_info; hcd_devtree_get_info(dev_addr, &devtree_info); @@ -464,12 +472,15 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* edpt->next_pid = HCTSIZ_PID_DATA0; if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) { - edpt->frame_interval = 1 << (desc_ep->bInterval - 1); + edpt->uframe_interval = 1 << (desc_ep->bInterval - 1); + if (devtree_info.speed == TUSB_SPEED_FULL) { + edpt->uframe_interval <<= 3; + } } else if (desc_ep->bmAttributes.xfer == TUSB_XFER_INTERRUPT) { if (devtree_info.speed == TUSB_SPEED_HIGH) { - edpt->frame_interval = 1 << (desc_ep->bInterval - 1); + edpt->uframe_interval = 1 << (desc_ep->bInterval - 1); } else { - edpt->frame_interval = desc_ep->bInterval; + edpt->uframe_interval = desc_ep->bInterval << 3; } } @@ -669,9 +680,22 @@ static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; if (edpt_is_periodic(channel->hcchar_bm.ep_type)){ + // retry immediately for periodic split nyet if haven't reach max retry + if (channel->hcsplt_bm.split_en && channel->hcsplt_bm.split_compl && (hcint & HCINT_NYET)) { + xfer->period_split_nyet_count++; + if (xfer->period_split_nyet_count < HCD_XFER_PERIOD_SPLIT_NYET_MAX) { + channel->hcchar_bm.odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame + channel_send_in_token(dwc2, channel); + return; + } else { + // too many NYET, de-allocate channel with below code + xfer->period_split_nyet_count = 0; + } + } + // for periodic, de-allocate channel, enable SOF set frame counter for later transfer edpt->next_pid = channel->hctsiz_bm.pid; // save PID - edpt->frame_countdown = edpt->frame_interval; + edpt->uframe_countdown = edpt->uframe_interval; dwc2->gintmsk |= GINTSTS_SOF; if (hcint & HCINT_HALTED) { @@ -683,10 +707,7 @@ static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci channel_disable(dwc2, channel); } } else { - // for control/bulk: try again immediately - if (channel->hcsplt_bm.split_en) { - channel->hcsplt_bm.split_compl = 0; // retry with start split - } + // for control/bulk: retry immediately channel_send_in_token(dwc2, channel); } } @@ -901,6 +922,7 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci edpt->buffer += actual_len; edpt->buflen -= actual_len; + channel->hcsplt_bm.split_compl = 0; channel_xfer_in_retry(dwc2, ch_id, hcint); } else { xfer->result = XFER_RESULT_SUCCESS; @@ -915,29 +937,37 @@ static bool handle_channel_in_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci xfer->result = XFER_RESULT_FAILED; } else { channel->hcintmsk |= HCINT_ACK | HCINT_NAK | HCINT_DATATOGGLE_ERR; + channel->hcsplt_bm.split_compl = 0; channel_xfer_in_retry(dwc2, ch_id, hcint); } - } else if (hcint & (HCINT_NAK | HCINT_DATATOGGLE_ERR)) { - xfer->err_count = 0; - channel->hcintmsk &= ~(HCINT_NAK | HCINT_DATATOGGLE_ERR); - if ((hcint & (HCINT_NAK | HCINT_DATATOGGLE_ERR))) { + } else if (hcint & HCINT_NYET) { + // Must handle nyet before nak or ack. Could get a nyet at the same time as either of those on a BULK/CONTROL + // OUT that started with a PING. The nyet takes precedence. + if (channel->hcsplt_bm.split_en) { + // split not yet mean hub has no data, retry complete split + channel->hcsplt_bm.split_compl = 1; channel_xfer_in_retry(dwc2, ch_id, hcint); } } else if (hcint & HCINT_ACK) { xfer->err_count = 0; channel->hcintmsk &= ~HCINT_ACK; - - if (channel->hcsplt_bm.split_en && !channel->hcsplt_bm.split_compl) { + if (channel->hcsplt_bm.split_en) { // start split is ACK --> do complete split + // TODO: for ISO must use xact_pos to plan complete split based on microframe (up to 187.5 bytes/uframe) channel->hcsplt_bm.split_compl = 1; + if (edpt_is_periodic(channel->hcchar_bm.ep_type)) { + channel->hcchar_bm.odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame + } channel_send_in_token(dwc2, channel); } - } else if (hcint & HCINT_NYET) { - if (channel->hcsplt_bm.split_en && channel->hcsplt_bm.split_compl) { - // split not yet mean hub has no data, retry complete split - channel->hcsplt_bm.split_compl = 1; - channel_send_in_token(dwc2, channel); - } + } else if (hcint & (HCINT_NAK | HCINT_DATATOGGLE_ERR)) { + xfer->err_count = 0; + channel->hcintmsk &= ~(HCINT_NAK | HCINT_DATATOGGLE_ERR); + channel->hcsplt_bm.split_compl = 0; // restart with start-split + channel_xfer_in_retry(dwc2, ch_id, hcint); + } else if (hcint & HCINT_FARME_OVERRUN) { + // retry start-split in next binterval + channel_xfer_in_retry(dwc2, ch_id, hcint); } } @@ -982,6 +1012,12 @@ static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hc channel_xfer_start(dwc2, ch_id); } } + } else if (hcint & HCINT_NYET) { + if (channel->hcsplt_bm.split_en && channel->hcsplt_bm.split_compl) { + // split not yet mean hub has no data, retry complete split + channel->hcsplt_bm.split_compl = 1; + channel->hcchar |= HCCHAR_CHENA; + } } else if (hcint & HCINT_ACK) { xfer->err_count = 0; if (channel->hcsplt_bm.split_en && !channel->hcsplt_bm.split_compl) { @@ -989,12 +1025,6 @@ static bool handle_channel_out_dma(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hc channel->hcsplt_bm.split_compl = 1; channel->hcchar |= HCCHAR_CHENA; } - } else if (hcint & HCINT_NYET) { - if (channel->hcsplt_bm.split_en && channel->hcsplt_bm.split_compl) { - // split not yet mean hub has no data, retry complete split - channel->hcsplt_bm.split_compl = 1; - channel->hcchar |= HCCHAR_CHENA; - } } } else if (hcint & HCINT_ACK) { xfer->err_count = 0; @@ -1055,13 +1085,16 @@ static bool handle_sof_irq(uint8_t rhport, bool in_isr) { bool more_isr = false; + // If highspeed then SOF is 125us, else 1ms + const uint32_t ucount = (hprt_speed_get(dwc2) == TUSB_SPEED_HIGH ? 1 : 8); + for(uint8_t ep_id = 0; ep_id < CFG_TUH_DWC2_ENDPOINT_MAX; ep_id++) { hcd_endpoint_t* edpt = &_hcd_data.edpt[ep_id]; - if (edpt->hcchar_bm.enable && edpt_is_periodic(edpt->hcchar_bm.ep_type) && edpt->frame_countdown > 0) { - edpt->frame_countdown--; - if (edpt->frame_countdown == 0) { + if (edpt->hcchar_bm.enable && edpt_is_periodic(edpt->hcchar_bm.ep_type) && edpt->uframe_countdown > 0) { + edpt->uframe_countdown -= tu_min32(ucount, edpt->uframe_countdown); + if (edpt->uframe_countdown == 0) { if (!edpt_xfer_kickoff(dwc2, ep_id)) { - edpt->frame_countdown = 1; // failed to start (out of channel), try again next frame + edpt->uframe_countdown = ucount; // failed to start, try again next frame } } @@ -1073,7 +1106,8 @@ static bool handle_sof_irq(uint8_t rhport, bool in_isr) { } // Config HCFG FS/LS clock and HFIR for SOF interval according to link speed (value is in PHY clock unit) -static void port0_enable(dwc2_regs_t* dwc2, tusb_speed_t speed) { +static void port0_enable(dwc2_regs_t* dwc2) { + const tusb_speed_t speed = hprt_speed_get(dwc2); uint32_t hcfg = dwc2->hcfg & ~HCFG_FSLS_PHYCLK_SEL; const dwc2_gusbcfg_t gusbcfg_bm = dwc2->gusbcfg_bm; @@ -1143,8 +1177,7 @@ static void handle_hprt_irq(uint8_t rhport, bool in_isr) { if (hprt_bm.enable) { // Port enable - const tusb_speed_t speed = convert_hprt_speed(hprt_bm.speed); - port0_enable(dwc2, speed); + port0_enable(dwc2); } else { // TU_ASSERT(false, ); } -- cgit v1.3.1 From fe79a93594c6ec994443e61317ea6bcc9fdf36b4 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 6 Nov 2024 12:09:32 +0700 Subject: implement split for slave, got mouse working --- src/portable/synopsys/dwc2/dwc2_type.h | 9 ++ src/portable/synopsys/dwc2/hcd_dwc2.c | 176 +++++++++++++++++++++++---------- src/tusb_option.h | 2 +- 3 files changed, 136 insertions(+), 51 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index a88a2d389..dfd61bc32 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -438,6 +438,12 @@ typedef struct TU_ATTR_PACKED { } dwc2_channel_tsize_t; TU_VERIFY_STATIC(sizeof(dwc2_channel_tsize_t) == 4, "incorrect size"); +typedef struct TU_ATTR_PACKED { + uint32_t num : 16; // 0..15 Frame number + uint32_t remainning : 16; // 16..31 Frame remaining +} dwc2_hfnum_t; +TU_VERIFY_STATIC(sizeof(dwc2_hfnum_t) == 4, "incorrect size"); + // Host Channel typedef struct { union { @@ -592,7 +598,10 @@ typedef struct { //------------ Host -------------// volatile uint32_t hcfg; // 400 Host Configuration volatile uint32_t hfir; // 404 Host Frame Interval + union { volatile uint32_t hfnum; // 408 Host Frame Number / Frame Remaining + volatile dwc2_hfnum_t hfnum_bm; + }; uint32_t reserved40c; // 40C union { volatile uint32_t hptxsts; // 410 Host Periodic TX FIFO / Queue Status diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index fa8269132..aabe1c062 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -73,7 +73,10 @@ typedef struct { struct TU_ATTR_PACKED { uint32_t uframe_interval : 18; // micro-frame interval + uint32_t speed : 2; uint32_t next_pid : 2; + uint32_t do_ping : 1; + // uint32_t : 9; }; uint32_t uframe_countdown; // micro-frame count down to transfer for periodic, only need 18-bit @@ -89,14 +92,14 @@ typedef struct { struct TU_ATTR_PACKED { uint8_t err_count : 3; uint8_t period_split_nyet_count : 3; - uint8_t do_ping : 1; - uint8_t sof_schedule : 1; + uint8_t halted_nyet : 1; + uint8_t halted_sof_schedule : 1; }; uint8_t result; uint16_t xferred_bytes; // bytes that accumulate transferred though USB bus for the whole hcd_edpt_xfer(), which can // be composed of multiple channel_xfer_start() (retry with NAK/NYET) - uint16_t txfifo_bytes; // bytes written to TX FIFO (may not be transferred on USB bus). + uint16_t fifo_bytes; // bytes written/read from/to FIFO (may not be transferred on USB bus). } hcd_xfer_t; typedef struct { @@ -470,6 +473,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* hcsplt_bm->split_compl = 0; hcsplt_bm->split_en = (rh_speed == TUSB_SPEED_HIGH && devtree_info.speed != TUSB_SPEED_HIGH) ? 1 : 0; + edpt->speed = devtree_info.speed; edpt->next_pid = HCTSIZ_PID_DATA0; if (desc_ep->bmAttributes.xfer == TUSB_XFER_ISOCHRONOUS) { edpt->uframe_interval = 1 << (desc_ep->bInterval - 1); @@ -505,7 +509,7 @@ static void channel_xfer_out_wrapup(dwc2_regs_t* dwc2, uint8_t ch_id) { const uint16_t total_packets = cal_packet_count(edpt->buflen, channel->hcchar_bm.ep_size); const uint16_t actual_bytes = (total_packets - remain_packets) * channel->hcchar_bm.ep_size; - xfer->txfifo_bytes = 0; + xfer->fifo_bytes = 0; xfer->xferred_bytes += actual_bytes; edpt->buffer += actual_bytes; edpt->buflen -= actual_bytes; @@ -519,7 +523,7 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { bool const is_period = edpt_is_periodic(hcchar_bm->ep_type); // clear previous state - xfer->txfifo_bytes = 0; + xfer->fifo_bytes = 0; // hchar: restore but don't enable yet if (is_period) { @@ -530,15 +534,12 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { // hctsiz: zero length packet still count as 1 const uint16_t packet_count = cal_packet_count(edpt->buflen, hcchar_bm->ep_size); uint32_t hctsiz = (edpt->next_pid << HCTSIZ_PID_Pos) | (packet_count << HCTSIZ_PKTCNT_Pos) | edpt->buflen; - if (xfer->do_ping && edpt->next_pid != HCTSIZ_PID_SETUP && hcchar_bm->ep_dir == TUSB_DIR_OUT) { - hcd_devtree_info_t devtree_info; - hcd_devtree_get_info(hcchar_bm->dev_addr, &devtree_info); - if (devtree_info.speed == TUSB_SPEED_HIGH) { - hctsiz |= HCTSIZ_DOPING; - } - xfer->do_ping = 0; + if (edpt->do_ping && edpt->speed == TUSB_SPEED_HIGH && + edpt->next_pid != HCTSIZ_PID_SETUP && hcchar_bm->ep_dir == TUSB_DIR_OUT) { + hctsiz |= HCTSIZ_DOPING; } channel->hctsiz = hctsiz; + edpt->do_ping = 0; // pre-calculate next PID based on packet count, adjusted in transfer complete interrupt if short packet if (hcchar_bm->ep_num == 0) { @@ -565,9 +566,12 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { } else { uint32_t hcintmsk = HCINT_NAK | HCINT_XACT_ERR | HCINT_STALL | HCINT_XFER_COMPLETE | HCINT_DATATOGGLE_ERR; if (hcchar_bm->ep_dir == TUSB_DIR_IN) { - hcintmsk |= HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR; + hcintmsk |= HCINT_BABBLE_ERR | HCINT_DATATOGGLE_ERR | HCINT_ACK; } else { hcintmsk |= HCINT_NYET; + if (edpt->hcsplt_bm.split_en) { + hcintmsk |= HCINT_ACK; + } } channel->hcintmsk = hcintmsk; dwc2->haintmsk |= TU_BIT(ch_id); @@ -680,9 +684,10 @@ static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; if (edpt_is_periodic(channel->hcchar_bm.ep_type)){ - // retry immediately for periodic split nyet if haven't reach max retry - if (channel->hcsplt_bm.split_en && channel->hcsplt_bm.split_compl && (hcint & HCINT_NYET)) { + // retry immediately for periodic split NYET if we haven't reach max retry + if (channel->hcsplt_bm.split_en && channel->hcsplt_bm.split_compl && (hcint & HCINT_NYET || xfer->halted_nyet)) { xfer->period_split_nyet_count++; + xfer->halted_nyet = 0; if (xfer->period_split_nyet_count < HCD_XFER_PERIOD_SPLIT_NYET_MAX) { channel->hcchar_bm.odd_frame = 1 - (dwc2->hfnum & 1); // transfer on next frame channel_send_in_token(dwc2, channel); @@ -703,7 +708,7 @@ static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci channel_dealloc(dwc2, ch_id); } else { // disable channel first if not halted (called slave isr) - xfer->sof_schedule = 1; + xfer->halted_sof_schedule = 1; channel_disable(dwc2, channel); } } else { @@ -712,6 +717,24 @@ static void channel_xfer_in_retry(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hci } } +#if CFG_TUSB_DEBUG +TU_ATTR_ALWAYS_INLINE static inline void print_hcint(uint32_t hcint) { + const char* str[] = { + "XFRC", "HALTED", "AHBERR", "STALL", + "NAK", "ACK", "NYET", "XERR", + "BBLERR", "FRMOR", "DTERR", "BNA", + "XCSERR", "DESC_LST" + }; + + for(uint32_t i=0; i<14; i++) { + if (hcint & TU_BIT(i)) { + TU_LOG1("%s ", str[i]); + } + } + TU_LOG1("\r\n"); +} +#endif + #if CFG_TUH_DWC2_SLAVE_ENABLE static void handle_rxflvl_irq(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); @@ -719,11 +742,11 @@ static void handle_rxflvl_irq(uint8_t rhport) { // Pop control word off FIFO const dwc2_grxstsp_t grxstsp_bm = dwc2->grxstsp_bm; const uint8_t ch_id = grxstsp_bm.ep_ch_num; - dwc2_channel_t* channel = &dwc2->channel[ch_id]; + // dwc2_channel_t* channel = &dwc2->channel[ch_id]; switch (grxstsp_bm.packet_status) { case GRXSTS_PKTSTS_RX_DATA: { - // In packet received + // In packet received, pop this entry --> ACK interrupt const uint16_t byte_count = grxstsp_bm.byte_count; hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX,); @@ -732,14 +755,7 @@ static void handle_rxflvl_irq(uint8_t rhport) { if (byte_count) { dfifo_read_packet(dwc2, edpt->buffer + xfer->xferred_bytes, byte_count); xfer->xferred_bytes += byte_count; - - const uint16_t remain_packets = channel->hctsiz_bm.packet_count; - if (byte_count < edpt->hcchar_bm.ep_size) { - // short packet: update PID based on remain packets count - edpt->next_pid = cal_next_pid(edpt->next_pid, remain_packets); - } if (remain_packets) { - channel_send_in_token(dwc2, channel); // still more packet to send - } + xfer->fifo_bytes = byte_count; } break; } @@ -778,7 +794,7 @@ static bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { const uint16_t remain_packets = channel->hctsiz_bm.packet_count; for (uint16_t i = 0; i < remain_packets; i++) { - const uint16_t remain_bytes = edpt->buflen - xfer->txfifo_bytes; + const uint16_t remain_bytes = edpt->buflen - xfer->fifo_bytes; const uint16_t xact_bytes = tu_min16(remain_bytes, channel->hcchar_bm.ep_size); // skip if there is not enough space in FIFO and RequestQueue. @@ -787,26 +803,41 @@ static bool handle_txfifo_empty(dwc2_regs_t* dwc2, bool is_periodic) { return true; } - dfifo_write_packet(dwc2, ch_id, edpt->buffer + xfer->txfifo_bytes, xact_bytes); - xfer->txfifo_bytes += xact_bytes; + dfifo_write_packet(dwc2, ch_id, edpt->buffer + xfer->fifo_bytes, xact_bytes); + xfer->fifo_bytes += xact_bytes; } } } - return false; // all data written + return false; // no channel has pending data } static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcint) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; + hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; bool is_done = false; -// TU_LOG1("ch%u: ep = %u, hcint = 0x%04lX\r\n", ch_id, channel->hcchar_bm.ep_num, hcint); + // if (channel->hcsplt_bm.split_en) { + // if (edpt->hcchar_bm.ep_num == 1) { + // TU_LOG1("Frame %u, ch %u: ep %u, hcint 0x%04lX ", dwc2->hfnum_bm.num, ch_id, channel->hcchar_bm.ep_num, hcint); + // print_hcint(hcint); + // } if (hcint & HCINT_XFER_COMPLETE) { - xfer->result = XFER_RESULT_SUCCESS; + if (edpt->hcchar_bm.ep_num != 0) { + edpt->next_pid = channel->hctsiz_bm.pid; // save pid (already toggled) + } + + const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + if (channel->hcsplt_bm.split_en && remain_packets && xfer->fifo_bytes == edpt->hcchar_bm.ep_size) { + // Split can only complete 1 transaction (up to 1 packet) at a time, schedule more + channel->hcsplt_bm.split_compl = 0; + } else { + xfer->result = XFER_RESULT_SUCCESS; + } + channel_disable(dwc2, channel); - channel->hcintmsk &= ~HCINT_ACK; } else if (hcint & (HCINT_XACT_ERR | HCINT_BABBLE_ERR | HCINT_STALL)) { if (hcint & HCINT_STALL) { xfer->result = XFER_RESULT_STALLED; @@ -816,37 +847,66 @@ static bool handle_channel_in_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t h xfer->err_count++; channel->hcintmsk |= HCINT_ACK; } + + channel_disable(dwc2, channel); + } else if (hcint & HCINT_NYET) { + // restart complete split + channel->hcsplt_bm.split_compl = 1; + xfer->halted_nyet = 1; + channel_disable(dwc2, channel); + } else if (hcint & HCINT_NAK) { + // NAK received, re-enable channel if request queue is available + if (channel->hcsplt_bm.split_en) { + channel->hcsplt_bm.split_compl = 0; // restart with start-split + } + channel_disable(dwc2, channel); + } else if (hcint & HCINT_ACK) { + xfer->err_count = 0; + + if (channel->hcsplt_bm.split_en) { + if (!channel->hcsplt_bm.split_compl) { + // start split is ACK --> do complete split + channel->hcintmsk |= HCINT_NYET; + channel->hcsplt_bm.split_compl = 1; + channel_send_in_token(dwc2, channel); + } else { + // do nothing for complete split with DATA, this will trigger XferComplete and handled there + } + } else { + // ACK with data + const uint16_t remain_packets = channel->hctsiz_bm.packet_count; + if (remain_packets) { + // still more packet to receive, also reset to start split + channel->hcsplt_bm.split_compl = 0; + channel_send_in_token(dwc2, channel); + } + } } else if (hcint & HCINT_HALTED) { channel->hcintmsk &= ~HCINT_HALTED; - if (xfer->sof_schedule) { + if (xfer->halted_sof_schedule) { // de-allocate channel but does not complete xfer, we schedule it in the SOF interrupt channel_dealloc(dwc2, ch_id); } else if (xfer->result != XFER_RESULT_INVALID) { is_done = true; - } else if (channel->hcchar_bm.err_multi_count == HCD_XFER_ERROR_MAX) { + } else if (xfer->err_count == HCD_XFER_ERROR_MAX) { xfer->result = XFER_RESULT_FAILED; is_done = true; } else { + // got here due to NAK or NYET channel_xfer_in_retry(dwc2, ch_id, hcint); } } else if (hcint & HCINT_DATATOGGLE_ERR) { xfer->err_count = 0; TU_ASSERT(false); - } else if (hcint & HCINT_NAK) { - // NAK received, re-enable channel if request queue is available - channel_xfer_in_retry(dwc2, ch_id, hcint); - } else if (hcint & HCINT_ACK) { - xfer->err_count = 0; - channel->hcintmsk &= ~HCINT_ACK; } - return is_done; } static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t hcint) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; dwc2_channel_t* channel = &dwc2->channel[ch_id]; + hcd_endpoint_t* edpt = &_hcd_data.edpt[xfer->ep_id]; bool is_done = false; if (hcint & HCINT_XFER_COMPLETE) { @@ -856,7 +916,18 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t } else if (hcint & HCINT_STALL) { xfer->result = XFER_RESULT_STALLED; channel_disable(dwc2, channel); - } else if (hcint & (HCINT_NAK | HCINT_XACT_ERR | HCINT_NYET)) { + } else if (hcint & HCINT_NYET) { + xfer->err_count = 0; + if (channel->hcsplt_bm.split_en) { + // retry complete split + channel->hcsplt_bm.split_compl = 1; + channel->hcchar |= HCCHAR_CHENA; + } else { + edpt->do_ping = 1; + channel_xfer_out_wrapup(dwc2, ch_id); + channel_disable(dwc2, channel); + } + } else if (hcint & (HCINT_NAK | HCINT_XACT_ERR)) { // clean up transfer so far, disable and start again later channel_xfer_out_wrapup(dwc2, ch_id); channel_disable(dwc2, channel); @@ -864,29 +935,34 @@ static bool handle_channel_out_slave(dwc2_regs_t* dwc2, uint8_t ch_id, uint32_t xfer->err_count++; channel->hcintmsk |= HCINT_ACK; } else { - // NAK/NYET disable channel to flush all posted request and try again + // NAK disable channel to flush all posted request and try again + edpt->do_ping = 1; xfer->err_count = 0; } } else if (hcint & HCINT_HALTED) { channel->hcintmsk &= ~HCINT_HALTED; if (xfer->result != XFER_RESULT_INVALID) { is_done = true; - } else if (channel->hcchar_bm.err_multi_count == HCD_XFER_ERROR_MAX) { + } else if (xfer->err_count == HCD_XFER_ERROR_MAX) { xfer->result = XFER_RESULT_FAILED; is_done = true; } else { - // Got here due to NAK or NYET -> Retry transfer with do PING (for highspeed) - xfer->do_ping = 1; + // Got here due to NAK or NYET TU_ASSERT(channel_xfer_start(dwc2, ch_id)); } } else if (hcint & HCINT_ACK) { xfer->err_count = 0; channel->hcintmsk &= ~HCINT_ACK; + if (channel->hcsplt_bm.split_en && !channel->hcsplt_bm.split_compl) { + // start split is ACK --> do complete split + channel->hcsplt_bm.split_compl = 1; + channel->hcchar |= HCCHAR_CHENA; + } } if (is_done) { - xfer->xferred_bytes += xfer->txfifo_bytes; - xfer->txfifo_bytes = 0; + xfer->xferred_bytes += xfer->fifo_bytes; + xfer->fifo_bytes = 0; } return is_done; @@ -1230,7 +1306,7 @@ void hcd_int_handler(uint8_t rhport, bool in_isr) { } #if CFG_TUH_DWC2_SLAVE_ENABLE - // RxFIFO non-empty interrupt handling, must be handled before HCINT + // RxFIFO non-empty interrupt handling if (gintsts & GINTSTS_RXFLVL) { // RXFLVL bit is read-only dwc2->gintmsk &= ~GINTSTS_RXFLVL; // disable RXFLVL interrupt while reading diff --git a/src/tusb_option.h b/src/tusb_option.h index b193d9c09..688976e55 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -261,7 +261,7 @@ // Enable DWC2 DMA for host #ifndef CFG_TUH_DWC2_DMA_ENABLE - #define CFG_TUH_DWC2_DMA_ENABLE 1 + #define CFG_TUH_DWC2_DMA_ENABLE 0 #endif // Enable PIO-USB software host controller -- cgit v1.3.1 From ab8160a29bcfdc451b68c68598cdb5f9d212f395 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 7 Nov 2024 16:37:33 +0700 Subject: hcd work with esp32p4 in slave mode but have issue with DMA mode. In slave it enumerate device but has issue with msc bulk in --- docs/reference/supported.rst | 24 ++++++++------- examples/host/cdc_msc_hid_freertos/only.txt | 1 + hw/bsp/espressif/boards/family.c | 6 ++++ .../components/tinyusb_src/CMakeLists.txt | 7 +++-- hw/bsp/espressif/family.cmake | 17 +++++++++-- src/portable/synopsys/dwc2/dwc2_esp32.h | 34 ++++++++++++++++------ 6 files changed, 63 insertions(+), 26 deletions(-) (limited to 'src/portable') diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index b871490dc..da2431415 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -21,11 +21,13 @@ Supported MCUs +--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ | Dialog | DA1469x | âś” | âś– | âś– | da146xx | | +--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ -| Espressif | ESP32 S2, S3 | âś” | | âś– | dwc2 or esp32sx | | -+--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ +| Espressif | S2, S3 | âś” | âś” | âś– | dwc2 or esp32sx | | +| ESP32 +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| | P4 | âś” | âś” | âś” | dwc2 | | ++--------------+----+------------------------+--------+------+-----------+------------------------+-------------------+ | GigaDevice | GD32VF103 | âś” | | âś– | dwc2 | | +--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ -| Infineon | XMC4500 | âś” | | âś– | dwc2 | | +| Infineon | XMC4500 | âś” | âś” | âś– | dwc2 | | +--------------+-----+-----------------------+--------+------+-----------+------------------------+-------------------+ | MicroChip | SAM | D11, D21, L21, L22 | âś” | | âś– | samd | | | | +-----------------------+--------+------+-----------+------------------------+-------------------+ @@ -89,31 +91,31 @@ Supported MCUs | +----+------------------------+--------+------+-----------+------------------------+-------------------+ | | F1 | 102, 103 | âś” | âś– | âś– | stm32_fsdev | | | | +------------------------+--------+------+-----------+------------------------+-------------------+ -| | | 105, 107 | âś” | | âś– | dwc2 | | +| | | 105, 107 | âś” | âś” | âś– | dwc2 | | | +----+------------------------+--------+------+-----------+------------------------+-------------------+ -| | F2, F4, F7, H7 | âś” | | âś” | dwc2 | | +| | F2, F4, F7, H7 | âś” | âś” | âś” | dwc2 | | | +-----------------------------+--------+------+-----------+------------------------+-------------------+ | | F3 | âś” | âś– | âś– | stm32_fsdev | | | +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | G0, H5 | âś” | | âś– | stm32_fsdev | | +| | G0, H5 | âś” | âś– | âś– | stm32_fsdev | | | +-----------------------------+--------+------+-----------+------------------------+-------------------+ | | G4 | âś” | âś– | âś– | stm32_fsdev | | | +-----------------------------+--------+------+-----------+------------------------+-------------------+ | | L0, L1 | âś” | âś– | âś– | stm32_fsdev | | -| +-----------------------------+--------+------+-----------+------------------------+-------------------+ +| +----+------------------------+--------+------+-----------+------------------------+-------------------+ | | L4 | 4x2, 4x3 | âś” | âś– | âś– | stm32_fsdev | | | | +------------------------+--------+------+-----------+------------------------+-------------------+ -| | | 4x5, 4x6 | âś” | | âś– | dwc2 | | +| | | 4x5, 4x6 | âś” | âś” | âś– | dwc2 | | | +----+------------------------+--------+------+-----------+------------------------+-------------------+ -| | L4+ | âś” | | âś– | dwc2 | | +| | L4+ | âś” | âś” | âś– | dwc2 | | | +-----------------------------+--------+------+-----------+------------------------+-------------------+ | | L5 | âś” | âś– | âś– | stm32_fsdev | | | +----+------------------------+--------+------+-----------+------------------------+-------------------+ | | U5 | 535, 545 | âś” | | âś– | stm32_fsdev | | | | +------------------------+--------+------+-----------+------------------------+-------------------+ -| | | 575, 585 | âś” | | âś– | dwc2 | | +| | | 575, 585 | âś” | âś” | âś– | dwc2 | | | | +------------------------+--------+------+-----------+------------------------+-------------------+ -| | | 59x,5Ax,5Fx,5Gx | âś” | | âś” | dwc2 | | +| | | 59x,5Ax,5Fx,5Gx | âś” | âś” | âś” | dwc2 | | | +----+------------------------+--------+------+-----------+------------------------+-------------------+ | | WBx5 | âś” | âś– | âś– | stm32_fsdev | | +--------------+-----------------------------+--------+------+-----------+------------------------+-------------------+ diff --git a/examples/host/cdc_msc_hid_freertos/only.txt b/examples/host/cdc_msc_hid_freertos/only.txt index 472745301..e3ae25260 100644 --- a/examples/host/cdc_msc_hid_freertos/only.txt +++ b/examples/host/cdc_msc_hid_freertos/only.txt @@ -1,3 +1,4 @@ +mcu:ESP32P4 mcu:LPC175X_6X mcu:LPC177X_8X mcu:LPC18XX diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index a1b4334b2..7f4535d49 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -175,7 +175,13 @@ bool usb_init(void) { usb_phy_config_t phy_conf = { .controller = USB_PHY_CTRL_OTG, .target = USB_PHY_TARGET_INT, + + // maybe we can use USB_OTG_MODE_DEFAULT and switch using dwc2 driver +#if CFG_TUD_ENABLED .otg_mode = USB_OTG_MODE_DEVICE, +#elif CFG_TUH_ENABLED + .otg_mode = USB_OTG_MODE_HOST, +#endif }; // OTG IOs config diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt index ae94a0ea4..e2250c4ca 100644 --- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt +++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt @@ -9,9 +9,10 @@ string(TOUPPER OPT_MCU_${target} tusb_mcu) list(APPEND compile_definitions CFG_TUSB_MCU=${tusb_mcu} CFG_TUSB_OS=OPT_OS_FREERTOS - # EXAMPLE port selection: port0 is fullspeed, port1 is highspeed - BOARD_TUD_RHPORT=${TUD_PORT} - BOARD_TUD_MAX_SPEED=$ + BOARD_TUD_RHPORT=${RHPORT_DEVICE} + BOARD_TUD_MAX_SPEED=${RHPORT_DEVICE_SPEED} + BOARD_TUH_RHPORT=${RHPORT_HOST} + BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} ) list(APPEND srcs diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake index ada082c76..aaa611fac 100644 --- a/hw/bsp/espressif/family.cmake +++ b/hw/bsp/espressif/family.cmake @@ -5,14 +5,25 @@ include("${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake") string(TOUPPER ${IDF_TARGET} FAMILY_MCUS) # Device port default to Port1 for P4 (highspeed), Port0 for others (fullspeed) -if (NOT DEFINED TUD_PORT) +set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) + +if (NOT DEFINED RHPORT_DEVICE) if (IDF_TARGET STREQUAL "esp32p4") - set(TUD_PORT 1) + set(RHPORT_DEVICE 1) + set(RHPORT_HOST 1) else () - set(TUD_PORT 0) + set(RHPORT_DEVICE 0) + set(RHPORT_HOST 0) endif () endif() +if (NOT DEFINED RHPORT_DEVICE_SPEED) + list(GET RHPORT_SPEED ${RHPORT_DEVICE} RHPORT_DEVICE_SPEED) +endif () +if (NOT DEFINED RHPORT_HOST_SPEED) + list(GET RHPORT_SPEED ${RHPORT_HOST} RHPORT_HOST_SPEED) +endif () + # Add example src and bsp directories set(EXTRA_COMPONENT_DIRS "src" "${CMAKE_CURRENT_LIST_DIR}/boards" "${CMAKE_CURRENT_LIST_DIR}/components") diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index c8c5bffd0..a86587786 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -60,21 +60,37 @@ static const dwc2_controller_t _dwc2_controller[] = { }; #endif +//--------------------------------------------------------------------+ +// +//--------------------------------------------------------------------+ static intr_handle_t usb_ih[TU_ARRAY_SIZE(_dwc2_controller)]; -static void dcd_int_handler_wrap(void* arg) { - const uint8_t rhport = (uint8_t)(uintptr_t) arg; - dcd_int_handler(rhport); +static void dwc2_int_handler_wrap(void* arg) { + const uint8_t rhport = tu_u16_low((uint16_t)(uintptr_t)arg); + const tusb_role_t role = (tusb_role_t) tu_u16_high((uint16_t)(uintptr_t)arg); +#if CFG_TUD_ENABLED + if (role == TUSB_ROLE_DEVICE) { + dcd_int_handler(rhport); + } +#endif +#if CFG_TUH_ENABLED + if (role == TUSB_ROLE_HOST) { + hcd_int_handler(rhport, true); + } +#endif } -TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_enable(uint8_t rhport) { - esp_intr_alloc(_dwc2_controller[rhport].irqnum, ESP_INTR_FLAG_LOWMED, - dcd_int_handler_wrap, (void*)(uintptr_t) rhport, &usb_ih[rhport]); +TU_ATTR_ALWAYS_INLINE static inline void dwc2_int_set(uint8_t rhport, tusb_role_t role, bool enabled) { + if (enabled) { + esp_intr_alloc(_dwc2_controller[rhport].irqnum, ESP_INTR_FLAG_LOWMED, + dwc2_int_handler_wrap, (void*)(uintptr_t)tu_u16(role, rhport), &usb_ih[rhport]); + } else { + esp_intr_free(usb_ih[rhport]); + } } -TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcd_int_disable(uint8_t rhport) { - esp_intr_free(usb_ih[rhport]); -} +#define dwc2_dcd_int_enable(_rhport) dwc2_int_set(_rhport, TUSB_ROLE_DEVICE, true) +#define dwc2_dcd_int_disable(_rhport) dwc2_int_set(_rhport, TUSB_ROLE_DEVICE, false) TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { vTaskDelay(pdMS_TO_TICKS(1)); -- cgit v1.3.1 From 5d00488907e5591f35772769a917cf6c3ff97181 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 8 Nov 2024 17:23:43 +0700 Subject: get hcd work esp32p4 but only in slave mode. In DMA channel's HCDMA is increased but data transfer over USB is not correct. --- hw/bsp/espressif/boards/family.c | 2 ++ hw/bsp/espressif/family.cmake | 8 +++++++- src/common/tusb_mcu.h | 3 +++ src/portable/synopsys/dwc2/dwc2_esp32.h | 5 +++-- src/portable/synopsys/dwc2/dwc2_type.h | 9 +++++++++ src/tusb_option.h | 13 ++++++++++--- 6 files changed, 34 insertions(+), 6 deletions(-) (limited to 'src/portable') diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index 7f4535d49..0b1e8badb 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -179,8 +179,10 @@ bool usb_init(void) { // maybe we can use USB_OTG_MODE_DEFAULT and switch using dwc2 driver #if CFG_TUD_ENABLED .otg_mode = USB_OTG_MODE_DEVICE, + .otg_speed = BOARD_TUD_RHPORT ? USB_PHY_SPEED_HIGH : USB_PHY_SPEED_FULL, #elif CFG_TUH_ENABLED .otg_mode = USB_OTG_MODE_HOST, + .otg_speed= BOARD_TUH_RHPORT ? USB_PHY_SPEED_HIGH : USB_PHY_SPEED_FULL, #endif }; diff --git a/hw/bsp/espressif/family.cmake b/hw/bsp/espressif/family.cmake index aaa611fac..daa12cdb4 100644 --- a/hw/bsp/espressif/family.cmake +++ b/hw/bsp/espressif/family.cmake @@ -10,9 +10,15 @@ set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) if (NOT DEFINED RHPORT_DEVICE) if (IDF_TARGET STREQUAL "esp32p4") set(RHPORT_DEVICE 1) - set(RHPORT_HOST 1) else () set(RHPORT_DEVICE 0) + endif () +endif() + +if (NOT DEFINED RHPORT_HOST) + if (IDF_TARGET STREQUAL "esp32p4") + set(RHPORT_HOST 1) + else () set(RHPORT_HOST 0) endif () endif() diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index c77afecad..41f552d33 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -169,6 +169,7 @@ defined (STM32F107xB) || defined (STM32F107xC) #define TUP_USBIP_DWC2 #define TUP_USBIP_DWC2_STM32 + #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0 #define TUP_DCD_ENDPOINT_MAX 4 #elif defined(STM32F102x6) || defined(STM32F102xB) || \ @@ -343,12 +344,14 @@ #define TUP_USBIP_DWC2 #define TUP_USBIP_DWC2_ESP32 #define TUP_DCD_ENDPOINT_MAX 7 // only 5 TX FIFO for endpoint IN + #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0 // TODO currently have issue with buffer DMA with espressif #elif TU_CHECK_MCU(OPT_MCU_ESP32P4) #define TUP_USBIP_DWC2 #define TUP_USBIP_DWC2_ESP32 #define TUP_RHPORT_HIGHSPEED 1 // port0 FS, port1 HS #define TUP_DCD_ENDPOINT_MAX 16 // FS 7 ep, HS 16 ep + #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0 // TODO currently have issue with buffer DMA with espressif #elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2) #if (CFG_TUD_ENABLED || !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)) diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index a86587786..42ab4b80f 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -100,14 +100,15 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_remote_wakeup_delay(void) { TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { (void)dwc2; (void)hs_phy_type; - // nothing to do + // maybe usb_utmi_hal_init() + } // MCU specific PHY update, it is called AFTER init() and core reset TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { (void)dwc2; (void)hs_phy_type; - // nothing to do + // maybe usb_utmi_hal_disable() } #ifdef __cplusplus diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index dfd61bc32..1247f19a3 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -541,13 +541,22 @@ typedef struct { volatile uint32_t gotgctl; // 000 OTG Control and Status volatile dwc2_gotgctl_t gotgctl_bm; }; + union { volatile uint32_t gotgint; // 004 OTG Interrupt + volatile dwc2_gotgint_t gotgint_bm; + }; + union { volatile uint32_t gahbcfg; // 008 AHB Configuration + volatile dwc2_gahbcfg_t gahbcfg_bm; + }; union { volatile uint32_t gusbcfg; // 00c USB Configuration volatile dwc2_gusbcfg_t gusbcfg_bm; }; + union { volatile uint32_t grstctl; // 010 Reset + volatile dwc2_grstctl_t grstctl_bm; + }; volatile uint32_t gintsts; // 014 Interrupt volatile uint32_t gintmsk; // 018 Interrupt Mask volatile uint32_t grxstsr; // 01c Receive Status Debug Read diff --git a/src/tusb_option.h b/src/tusb_option.h index b193d9c09..e9b6a5806 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -241,6 +241,8 @@ #include "tusb_config.h" #endif +#include "common/tusb_mcu.h" + //--------------------------------------------------------------------+ // USBIP //--------------------------------------------------------------------+ @@ -256,12 +258,18 @@ // Enable DWC2 Slave mode for host #ifndef CFG_TUH_DWC2_SLAVE_ENABLE - #define CFG_TUH_DWC2_SLAVE_ENABLE 1 + #ifndef CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT + #define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT 1 + #endif + #define CFG_TUH_DWC2_SLAVE_ENABLE CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT #endif // Enable DWC2 DMA for host #ifndef CFG_TUH_DWC2_DMA_ENABLE - #define CFG_TUH_DWC2_DMA_ENABLE 1 + #ifndef CFG_TUH_DWC2_DMA_ENABLE_DEFAULT + #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 1 + #endif + #define CFG_TUH_DWC2_DMA_ENABLE CFG_TUH_DWC2_DMA_ENABLE_DEFAULT #endif // Enable PIO-USB software host controller @@ -278,7 +286,6 @@ #define CFG_TUH_MAX3421 0 #endif -#include "common/tusb_mcu.h" //-------------------------------------------------------------------- // RootHub Mode detection -- cgit v1.3.1 From c8d104fb47882e7f4cb3cc00758cf240d66baec8 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 8 Nov 2024 21:55:23 +0700 Subject: fix warnings --- src/portable/synopsys/dwc2/dcd_dwc2.c | 2 +- src/portable/synopsys/dwc2/hcd_dwc2.c | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 4cf725bfe..fe67de8dc 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -856,7 +856,7 @@ static void handle_epin_irq(uint8_t rhport) { // Process every single packet (only whole packets can be written to fifo) for (uint16_t i = 0; i < remain_packets; i++) { - const uint16_t remain_bytes = epin->dieptsiz_bm.xfer_size; + const uint16_t remain_bytes = (uint16_t) epin->dieptsiz_bm.xfer_size; // Packet can not be larger than ep max size const uint16_t xact_bytes = tu_min16(remain_bytes, xfer->max_size); diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index aabe1c062..f9fc5ca8e 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -742,7 +742,6 @@ static void handle_rxflvl_irq(uint8_t rhport) { // Pop control word off FIFO const dwc2_grxstsp_t grxstsp_bm = dwc2->grxstsp_bm; const uint8_t ch_id = grxstsp_bm.ep_ch_num; - // dwc2_channel_t* channel = &dwc2->channel[ch_id]; switch (grxstsp_bm.packet_status) { case GRXSTS_PKTSTS_RX_DATA: { -- cgit v1.3.1 From 57c8c223e5f873e8075eb807844140004c74472d Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 11 Nov 2024 16:42:08 +0700 Subject: correctly test dwc2 dma device for s3, disable for p4 (cache issue) and f407 fs (slave only) --- .../components/tinyusb_src/CMakeLists.txt | 5 + src/portable/synopsys/dwc2/dwc2_info.md | 116 ++++++++++----------- src/portable/synopsys/dwc2/dwc2_info.py | 6 +- test/hil/tinyusb.json | 6 -- 4 files changed, 66 insertions(+), 67 deletions(-) (limited to 'src/portable') diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt index e2250c4ca..900f620fd 100644 --- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt +++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt @@ -60,6 +60,11 @@ if (DEFINED LOG) endif () endif() +if(DEFINED CFLAGS_CLI) + list(APPEND compile_definitions ${CFLAGS_CLI}) +endif() + + idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${tusb_src} REQUIRES src diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index 78c2c50f8..dec021f59 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -1,58 +1,58 @@ -| | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/767 FS | ST F723/L4P5 FS | ST F723 HS | ST F769 | ST H743/H750 | ST L476 FS | ST U5A5 HS | GD32VF103 | XMC4500 | -|:---------------------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:-------------|:------------|:-------------| -| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | -| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | -| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | -| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | -| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | -| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | -| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | DMA internal | -| - single_point | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | hub | n/a | -| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | -| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | n/a | Dedicated | -| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | -| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 0 | 13 | -| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nptx_q_depth | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | 8 | -| - ptx_q_depth | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | 8 | -| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | -| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | -| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | -| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | -| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | -| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | -| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | -| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 0 | 634 | -| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | -| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8 bit | 8/16 bit | -| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 0 | 6 | -| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | -| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | +| | BCM2711 (Pi4) | EFM32GG | ESP32-S2/S3 | ESP32-P4 | ST F207/F407/411/429 FS | ST F407/429 HS | ST F412/76x FS | ST F723/L4P5 FS | ST F723 HS | ST F76x HS | ST H743/H750 | ST L476 FS | ST U5A5 HS | XMC4500 | GD32VF103 | +|:---------------------------|:----------------|:-------------|:--------------|:-------------|:--------------------------|:-----------------|:-----------------|:------------------|:-------------|:-------------|:---------------|:-------------|:-------------|:-------------|:------------| +| GUID | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002100 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00AEC000 | 0x00001000 | +| GSNPSID | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x4F54292A | 0x00000000 | +| - specs version | 2.80a | 3.30a | 4.00a | 4.00a | 2.81a | 2.81a | 3.20a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 2.92a | 0.00W | +| GHWCFG1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| GHWCFG2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x215FFFD0 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229FE190 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x228F5930 | 0x00000000 | +| - op_mode | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | HNP SRP | noHNP noSRP | HNP SRP | HNP SRP | +| - arch | DMA internal | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | Slave only | Slave only | DMA internal | DMA internal | DMA internal | Slave only | DMA internal | DMA internal | Slave only | +| - single_point | hub | hub | n/a | hub | n/a | hub | n/a | n/a | hub | hub | hub | n/a | hub | n/a | hub | +| - hs_phy_type | UTMI+ | n/a | n/a | UTMI+/ULPI | n/a | ULPI | n/a | n/a | UTMI+/ULPI | ULPI | ULPI | n/a | UTMI+ | n/a | n/a | +| - fs_phy_type | Dedicated | Dedicated | Dedicated | Shared ULPI | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | Dedicated | n/a | Dedicated | n/a | +| - num_dev_ep | 7 | 6 | 6 | 15 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | +| - num_host_ch | 7 | 13 | 7 | 15 | 7 | 11 | 11 | 11 | 15 | 15 | 15 | 11 | 15 | 13 | 0 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - mul_proc_intrpt | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nptx_q_depth | 8 | 8 | 4 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | +| - ptx_q_depth | 8 | 8 | 8 | 4 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 2 | +| - token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| GHWCFG3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x03805EB5 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x03EED2E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x027A01E5 | 0x00000000 | +| - xfer_size_width | 8 | 8 | 5 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 5 | 0 | +| - packet_size_width | 6 | 6 | 3 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - i2c_enable | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | +| - vendor_ctrl_itf | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | +| - optional_feature_removed | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - dfifo_depth | 4080 | 498 | 200 | 896 | 512 | 1012 | 512 | 512 | 1006 | 1006 | 952 | 512 | 952 | 634 | 0 | +| GHWCFG4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0xDFF1A030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x23F00030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0xDBF08030 | 0x00000000 | +| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - partial_powerdown | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - extended_hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved8 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - enhanced_lpm_support1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - service_interval_flow | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - ipg_isoc_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - acg_support | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - enhanced_lpm_support | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - phy_data_width | 8 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8/16 bit | 8 bit | 8/16 bit | 8/16 bit | 8 bit | 8 bit | 8 bit | 8/16 bit | 8 bit | 8/16 bit | 8 bit | +| - ctrl_ep_num | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - vbus_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - a_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - b_valid_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - session_end_filter | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | +| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | +| - num_dev_in_eps | 7 | 6 | 4 | 7 | 3 | 5 | 5 | 5 | 8 | 8 | 8 | 5 | 8 | 6 | 0 | +| - dma_desc_enable | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | +| - dma_desc_dynamic | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 5884cd455..25edcf22d 100755 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -15,15 +15,15 @@ dwc2_reg_value = { 'ESP32-P4': [0, 0x4F54400A, 0, 0x215FFFD0, 0x03805EB5, 0xDFF1A030], 'ST F207/F407/411/429 FS': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x020001E8, 0x0FF08030], 'ST F407/429 HS': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x03F403E8, 0x17F00030], - 'ST F412/767 FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], + 'ST F412/76x FS': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], 'ST F723/L4P5 FS': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], 'ST F723 HS': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x03EED2E8, 0x23F00030], - 'ST F769': [0x2100, 0x4F54320A, 0, 0x229FE190, 0x03EED2E8, 0x23F00030], + 'ST F76x HS': [0x2100, 0x4F54320A, 0, 0x229FE190, 0x03EED2E8, 0x23F00030], 'ST H743/H750': [0x2300, 0x4F54330A, 0, 0x229FE190, 0x03B8D2E8, 0xE3F00030], 'ST L476 FS': [0x2000, 0x4F54310A, 0, 0x229ED520, 0x0200D1E8, 0x17F08030], 'ST U5A5 HS': [0x5000, 0x4F54411A, 0, 0x228FE052, 0x03B882E8, 0xE2103E30], + 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030], 'GD32VF103': [0x1000, 0, 0, 0, 0, 0], - 'XMC4500': [0xAEC000, 0x4F54292A, 0, 0x228F5930, 0x027A01E5, 0xDBF08030] } # Combine dwc2_info with dwc2_reg_list diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json index c92224e26..f5a3f109e 100644 --- a/test/hil/tinyusb.json +++ b/test/hil/tinyusb.json @@ -3,9 +3,6 @@ { "name": "espressif_p4_function_ev", "uid": "6055F9F98715", - "build" : { - "flags_on": ["", "CFG_TUD_DWC2_DMA"] - }, "tests": { "only": ["device/cdc_msc_freertos", "device/hid_composite_freertos"] }, @@ -98,9 +95,6 @@ { "name": "stm32f407disco", "uid": "30001A000647313332353735", - "build" : { - "flags_on": ["", "CFG_TUD_DWC2_DMA"] - }, "flasher": "jlink", "flasher_sn": "000773661813", "flasher_args": "-device stm32f407vg" -- cgit v1.3.1 From aeae2966a2afa669068e54eef7c4dd2dceffaa0d Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 13 Nov 2024 13:08:30 +0700 Subject: hil add stm32f723disco, add test flags for device/host/dual --- examples/device/cdc_msc/CMakeLists.txt | 2 +- examples/host/device_info/src/main.c | 20 +-- hw/bsp/stm32f7/boards/stm32f723disco/board.cmake | 6 +- hw/bsp/stm32f7/boards/stm32f723disco/board.mk | 5 +- hw/bsp/stm32f7/family.c | 29 +++-- src/portable/synopsys/dwc2/hcd_dwc2.c | 6 +- test/hil/hil_test.py | 147 ++++++++++++++++------- test/hil/tinyusb.json | 69 +++++++++-- 8 files changed, 200 insertions(+), 84 deletions(-) (limited to 'src/portable') diff --git a/examples/device/cdc_msc/CMakeLists.txt b/examples/device/cdc_msc/CMakeLists.txt index 9415f8c68..c2f9cb095 100644 --- a/examples/device/cdc_msc/CMakeLists.txt +++ b/examples/device/cdc_msc/CMakeLists.txt @@ -1,5 +1,5 @@ cmake_minimum_required(VERSION 3.17) -set_property(GLOBAL PROPERTY USE_FOLDERS ON) +#set_property(GLOBAL PROPERTY USE_FOLDERS ON) include(${CMAKE_CURRENT_SOURCE_DIR}/../../../hw/bsp/family_support.cmake) diff --git a/examples/host/device_info/src/main.c b/examples/host/device_info/src/main.c index 8e0185878..70304e449 100644 --- a/examples/host/device_info/src/main.c +++ b/examples/host/device_info/src/main.c @@ -56,8 +56,12 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTYPES //--------------------------------------------------------------------+ - -static uint32_t blink_interval_ms = 1000; +enum { + BLINK_NOT_MOUNTED = 250, + BLINK_MOUNTED = 1000, + BLINK_SUSPENDED = 2500, +}; +static uint32_t blink_interval_ms = BLINK_NOT_MOUNTED; void led_blinking_task(void* param); static void print_utf16(uint16_t* temp_buf, size_t buf_len); @@ -102,6 +106,8 @@ int main(void) { // Invoked when device is mounted (configured) void tuh_mount_cb(uint8_t daddr) { + blink_interval_ms = BLINK_MOUNTED; + // Get Device Descriptor tusb_desc_device_t desc_device; uint8_t xfer_result = tuh_descriptor_get_device_sync(daddr, &desc_device, 18); @@ -161,6 +167,7 @@ void tuh_mount_cb(uint8_t daddr) { // Invoked when device is unmounted (bus reset/unplugged) void tuh_umount_cb(uint8_t daddr) { + blink_interval_ms = BLINK_NOT_MOUNTED; printf("Device removed, address = %d\r\n", daddr); } @@ -227,15 +234,8 @@ void led_blinking_task(void* param) { while (1) { #if CFG_TUSB_OS == OPT_OS_FREERTOS - if (blink_interval_ms == 0) { - vTaskSuspend(NULL); - } else { - vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS); - } + vTaskDelay(blink_interval_ms / portTICK_PERIOD_MS); #else - if (blink_interval_ms == 0) { - return; - } if (board_millis() - start_ms < blink_interval_ms) { return; // not enough time } diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake b/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake index 5655c217e..eb3ed407b 100644 --- a/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake +++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.cmake @@ -5,12 +5,12 @@ set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32F723xE_FLASH.ld) set(RHPORT_SPEED OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED) -# device default to PORT 1 High Speed +# For Hardware test: device default to PORT 0, Host to port 1 if (NOT DEFINED RHPORT_DEVICE) - set(RHPORT_DEVICE 1) + set(RHPORT_DEVICE 0) endif() if (NOT DEFINED RHPORT_HOST) - set(RHPORT_HOST 0) + set(RHPORT_HOST 1) endif() function(update_board TARGET) diff --git a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk index eb6799eb0..9b8e7a969 100644 --- a/hw/bsp/stm32f7/boards/stm32f723disco/board.mk +++ b/hw/bsp/stm32f7/boards/stm32f723disco/board.mk @@ -1,8 +1,9 @@ MCU_VARIANT = stm32f723xx +# For Hardware test: device default to PORT 0, Host to port 1 RHPORT_SPEED = OPT_MODE_FULL_SPEED OPT_MODE_HIGH_SPEED -RHPORT_DEVICE ?= 1 -RHPORT_HOST ?= 0 +RHPORT_DEVICE ?= 0 +RHPORT_HOST ?= 1 CFLAGS += \ -DSTM32F723xx \ diff --git a/hw/bsp/stm32f7/family.c b/hw/bsp/stm32f7/family.c index 61beac47e..527fbfe5c 100644 --- a/hw/bsp/stm32f7/family.c +++ b/hw/bsp/stm32f7/family.c @@ -37,6 +37,25 @@ typedef struct { #include "board.h" +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ + +#ifdef UART_DEV +UART_HandleTypeDef UartHandle = { + .Instance = UART_DEV, + .Init = { + .BaudRate = CFG_BOARD_UART_BAUDRATE, + .WordLength = UART_WORDLENGTH_8B, + .StopBits = UART_STOPBITS_1, + .Parity = UART_PARITY_NONE, + .HwFlowCtl = UART_HWCONTROL_NONE, + .Mode = UART_MODE_TX_RX, + .OverSampling = UART_OVERSAMPLING_16, + } +}; +#endif + //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ @@ -54,8 +73,6 @@ void OTG_HS_IRQHandler(void) { // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -UART_HandleTypeDef UartHandle; - void board_init(void) { board_clock_init(); @@ -89,14 +106,6 @@ void board_init(void) { #endif #ifdef UART_DEV - UartHandle.Instance = UART_DEV; - UartHandle.Init.BaudRate = CFG_BOARD_UART_BAUDRATE; - UartHandle.Init.WordLength = UART_WORDLENGTH_8B; - UartHandle.Init.StopBits = UART_STOPBITS_1; - UartHandle.Init.Parity = UART_PARITY_NONE; - UartHandle.Init.HwFlowCtl = UART_HWCONTROL_NONE; - UartHandle.Init.Mode = UART_MODE_TX_RX; - UartHandle.Init.OverSampling = UART_OVERSAMPLING_16; HAL_UART_Init(&UartHandle); #endif diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index f9fc5ca8e..53583426f 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -1181,8 +1181,7 @@ static bool handle_sof_irq(uint8_t rhport, bool in_isr) { } // Config HCFG FS/LS clock and HFIR for SOF interval according to link speed (value is in PHY clock unit) -static void port0_enable(dwc2_regs_t* dwc2) { - const tusb_speed_t speed = hprt_speed_get(dwc2); +static void port0_enable(dwc2_regs_t* dwc2, tusb_speed_t speed) { uint32_t hcfg = dwc2->hcfg & ~HCFG_FSLS_PHYCLK_SEL; const dwc2_gusbcfg_t gusbcfg_bm = dwc2->gusbcfg_bm; @@ -1252,7 +1251,8 @@ static void handle_hprt_irq(uint8_t rhport, bool in_isr) { if (hprt_bm.enable) { // Port enable - port0_enable(dwc2); + const tusb_speed_t speed = hprt_speed_get(dwc2); + port0_enable(dwc2, speed); } else { // TU_ASSERT(false, ); } diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py index 91fe6b67c..b395c28a4 100755 --- a/test/hil/hil_test.py +++ b/test/hil/hil_test.py @@ -46,6 +46,26 @@ STATUS_SKIPPED = "\033[33mSkipped\033[0m" verbose = False +WCH_RISCV_CONTENT = """ +adapter driver wlinke +adapter speed 6000 +transport select sdi + +wlink_set_address 0x00000000 +set _CHIPNAME wch_riscv +sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1 +set _FLASHNAME $_CHIPNAME.flash + +flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0 + +echo "Ready for Remote Connections" +""" + # ------------------------------------------------------------- # Path # ------------------------------------------------------------- @@ -147,49 +167,60 @@ def flash_jlink(board, firmware): return ret -def flash_stlink(board, firmware): - ret = run_cmd(f'STM32_Programmer_CLI --connect port=swd sn={board["flasher_sn"]} --write {firmware}.elf --go') +def reset_jlink(board): + script = ['halt', 'r', 'go', 'exit'] + f_jlink = f'{board["name"]}_reset.jlink' + if not os.path.exists(f_jlink): + with open(f_jlink, 'w') as f: + f.writelines(f'{s}\n' for s in script) + ret = run_cmd(f'JLinkExe -USB {board["flasher_sn"]} {board["flasher_args"]} -if swd -JTAGConf -1,-1 -speed auto -NoGui 1 -ExitOnError 1 -CommandFile {f_jlink}') return ret +def flash_stlink(board, firmware): + return run_cmd(f'STM32_Programmer_CLI --connect port=swd sn={board["flasher_sn"]} --write {firmware}.elf --go') + + +def reset_stlink(board): + return run_cmd(f'STM32_Programmer_CLI --connect port=swd sn={board["flasher_sn"]} --rst --go') + def flash_stflash(board, firmware): ret = run_cmd(f'st-flash --serial {board["flasher_sn"]} write {firmware}.bin 0x8000000') return ret +def reset_stflash(board): + return subprocess.CompletedProcess(args=['dummy'], returncode=0) + + def flash_openocd(board, firmware): ret = run_cmd(f'openocd -c "adapter serial {board["flasher_sn"]}" {board["flasher_args"]} -c "program {firmware}.elf reset exit"') return ret -def flash_openocd_wch(board, firmware): - # Content of the wch-riscv.cfg file - cfg_content = """ -adapter driver wlinke -adapter speed 6000 -transport select sdi +def reset_openocd(board): + ret = run_cmd(f'openocd -c "adapter serial {board["flasher_sn"]}" {board["flasher_args"]} -c "reset exit"') + return ret -wlink_set_address 0x00000000 -set _CHIPNAME wch_riscv -sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001 -set _TARGETNAME $_CHIPNAME.cpu +def flash_openocd_wch(board, firmware): + f_wch = f"wch-riscv_{board['uid']}.cfg" + if not os.path.exists(f_wch): + with open(f_wch, 'w') as file: + file.write(WCH_RISCV_CONTENT) -target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME -$_TARGETNAME.0 configure -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1 -set _FLASHNAME $_CHIPNAME.flash + ret = run_cmd(f'openocd_wch -c "adapter serial {board["flasher_sn"]}" -f {f_wch} ' + f'-c "program {firmware}.elf reset exit"') + return ret -flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0 -echo "Ready for Remote Connections" -""" +def reset_openocd_wch(board): f_wch = f"wch-riscv_{board['uid']}.cfg" if not os.path.exists(f_wch): with open(f_wch, 'w') as file: - file.write(cfg_content) + file.write(WCH_RISCV_CONTENT) - ret = run_cmd(f'openocd_wch -c "adapter serial {board["flasher_sn"]}" -f {f_wch} ' - f'-c "program {firmware}.elf reset exit"') + ret = run_cmd(f'openocd_wch -c "adapter serial {board["flasher_sn"]}" -f {f_wch} -c "program reset exit"') return ret @@ -198,12 +229,25 @@ def flash_openocd_adi(board, firmware): f'{board["flasher_args"]} -c "program {firmware}.elf reset exit"') return ret + +def reset_openocd_adi(board): + ret = run_cmd(f'{OPENCOD_ADI_PATH}/src/openocd -c "adapter serial {board["flasher_sn"]}" -s {OPENCOD_ADI_PATH}/tcl ' + f'{board["flasher_args"]} -c "program reset exit"') + return ret + + def flash_wlink_rs(board, firmware): # wlink use index for probe selection and lacking usb serial support ret = run_cmd(f'wlink flash {firmware}.elf') return ret +def reset_wlink_rs(board): + # wlink use index for probe selection and lacking usb serial support + ret = run_cmd(f'wlink reset') + return ret + + def flash_esptool(board, firmware): port = get_serial_dev(board["flasher_sn"], None, None, 0) fw_dir = os.path.dirname(f'{firmware}.bin') @@ -213,28 +257,39 @@ def flash_esptool(board, firmware): flash_args = f.read().strip().replace('\n', ' ') command = (f'esptool.py --chip {idf_target} -p {port} {board["flasher_args"]} ' f'--before=default_reset --after=hard_reset write_flash {flash_args}') - # command = f'echo abc' ret = run_cmd(command, cwd=fw_dir) return ret +def reset_esptool(board): + return subprocess.CompletedProcess(args=['dummy'], returncode=0) + + def flash_uniflash(board, firmware): ret = run_cmd(f'dslite.sh {board["flasher_args"]} -f {firmware}.hex') return ret +def reset_uniflash(board): + return subprocess.CompletedProcess(args=['dummy'], returncode=0) + + # ------------------------------------------------------------- # Tests: dual # ------------------------------------------------------------- def test_dual_host_info_to_device_cdc(board): uid = board['uid'] declared_devs = [f'{d["vid_pid"]}_{d["serial"]}' for d in board['tests']['dev_attached']] - port = get_serial_dev(uid, 'TinyUSB', "TinyUSB_Device", 0) ser = open_serial_dev(port) - # read from serial, first line should contain vid/pid and serial + + # read from cdc, first line should contain vid/pid and serial data = ser.read(1000) + ser.close() + if len(data) == 0: + assert False, 'No data from device' lines = data.decode('utf-8').splitlines() + enum_dev_sn = [] for l in lines: vid_pid_sn = re.search(r'ID ([0-9a-fA-F]+):([0-9a-fA-F]+) SN (\w+)', l) @@ -243,12 +298,8 @@ def test_dual_host_info_to_device_cdc(board): enum_dev_sn.append(f'{vid_pid_sn.group(1)}_{vid_pid_sn.group(2)}_{vid_pid_sn.group(3)}') if set(declared_devs) != set(enum_dev_sn): - # for pico/pico2 make this test optional - failed_msg = f'Enumerated devices {enum_dev_sn} not match with declared {declared_devs}' - if 'raspberry_pi_pico' in board['name']: - print(f'\r\n {failed_msg} {STATUS_FAILED} ', end='') - else: - assert False, failed_msg + failed_msg = f'Expected {declared_devs}, Enumerated {enum_dev_sn}' + assert False, failed_msg return 0 @@ -256,12 +307,17 @@ def test_dual_host_info_to_device_cdc(board): # Tests: host # ------------------------------------------------------------- def test_host_device_info(board): - uid = board['uid'] declared_devs = [f'{d["vid_pid"]}_{d["serial"]}' for d in board['tests']['dev_attached']] port = get_serial_dev(board["flasher_sn"], None, None, 0) ser = open_serial_dev(port) + + # reset device since we can miss the first line + ret = globals()[f'reset_{board["flasher"].lower()}'](board) + assert ret.returncode == 0, 'Failed to reset device' + data = ser.read(1000) + ser.close() if len(data) == 0: assert False, 'No data from device' @@ -274,12 +330,8 @@ def test_host_device_info(board): enum_dev_sn.append(f'{vid_pid_sn.group(1)}_{vid_pid_sn.group(2)}_{vid_pid_sn.group(3)}') if set(declared_devs) != set(enum_dev_sn): - # for pico/pico2 make this test optional - failed_msg = f'Enumerated devices {enum_dev_sn} not match with declared {declared_devs}' - if 'raspberry_pi_pico' in board['name']: - print(f'\r\n {failed_msg} {STATUS_FAILED} ', end='') - else: - assert False, failed_msg + failed_msg = f'Expected {declared_devs}, Enumerated {enum_dev_sn}' + assert False, failed_msg return 0 @@ -323,7 +375,8 @@ def test_device_cdc_msc(board): str = b"test_str" ser.write(str) ser.flush() - assert ser.read(len(str)) == str, 'CDC wrong data' + rd_str = ser.read(len(str)) + assert rd_str == str, f'CDC wrong data: expected: {str} was {rd_str}' # Block test data = read_disk_file(uid,0,'README.TXT') @@ -430,10 +483,14 @@ device_tests = [ 'device/hid_boot_interface', ] -host_tests = [ +dual_tests = [ 'dual/host_info_to_device_cdc', ] +host_test = [ + 'host/device_info', +] + def test_board(board): name = board['name'] @@ -444,8 +501,12 @@ def test_board(board): if 'tests' in board: board_tests = board['tests'] - if 'dev_attached' in board_tests: - test_list += host_tests + if 'device' in board_tests and board_tests['device'] == True: + test_list += list(device_tests) + if 'dual' in board_tests and board_tests['dual'] == True: + test_list += dual_tests + if 'host' in board_tests and board_tests['host'] == True: + test_list += host_test if 'only' in board_tests: test_list = board_tests['only'] if 'skip' in board_tests: @@ -455,7 +516,7 @@ def test_board(board): print(f'{name:25} {skip:30} ... Skip') # board_test is added last to disable board's usb - #test_list.append('device/board_test') + test_list.append('device/board_test') err_count = 0 flags_on_list = [""] @@ -473,7 +534,7 @@ def test_board(board): fw_name = f'{fw_dir}/{os.path.basename(test)}' print(f'{name+f1_str:40} {test:30} ... ', end='') - if not os.path.exists(fw_dir): + if not os.path.exists(fw_dir) or not (os.path.exists(f'{fw_name}.elf') or os.path.exists(f'{fw_name}.bin')): print('Skip (no binary)') continue diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json index 2d61981f2..f3ef9dcf7 100644 --- a/test/hil/tinyusb.json +++ b/test/hil/tinyusb.json @@ -27,6 +27,9 @@ { "name": "feather_nrf52840_express", "uid": "1F0479CD0F764471", + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "jlink", "flasher_sn": "000682804350", "flasher_args": "-device nrf52840_xxaa" @@ -34,6 +37,9 @@ { "name": "max32666fthr", "uid": "0C81464124010B20FF0A08CC2C", + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "openocd_adi", "flasher_sn": "E6614C311B597D32", "flasher_args": "-f interface/cmsis-dap.cfg -f target/max32665.cfg" @@ -41,16 +47,20 @@ { "name": "metro_m4_express", "uid": "9995AD485337433231202020FF100A34", - "flasher": "jlink", - "flasher_sn": "123456", - "flasher_args": "-device ATSAMD51J19", "tests": { + "device": true, "host": false, "dual": true, "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002130"}] - } + }, + "flasher": "jlink", + "flasher_sn": "123456", + "flasher_args": "-device ATSAMD51J19" }, { "name": "lpcxpresso11u37", "uid": "17121919", + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "jlink", "flasher_sn": "000724441579", "flasher_args": "-device LPC11U37/401" @@ -59,6 +69,7 @@ "name": "ra4m1_ek", "uid": "152E163038303131393346E46F26574B", "tests": { + "device": true, "host": false, "dual": false, "skip": ["device/cdc_msc", "device/cdc_msc_freertos"] }, "comment": "MSC is slow to enumerated #2602", @@ -69,22 +80,24 @@ { "name": "raspberry_pi_pico", "uid": "E6614C311B764A37", - "flasher": "openocd", - "flasher_sn": "E6614103E72C1D2F", - "flasher_args": "-f interface/cmsis-dap.cfg -f target/rp2040.cfg -c \"adapter speed 5000\"", "tests": { + "device": true, "host": false, "dual": false, "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002470"}] - } + }, + "flasher": "openocd", + "flasher_sn": "E6614103E72C1D2F", + "flasher_args": "-f interface/cmsis-dap.cfg -f target/rp2040.cfg -c \"adapter speed 5000\"" }, { "name": "raspberry_pi_pico2", "uid": "560AE75E1C7152C9", - "flasher": "openocd", - "flasher_sn": "E6633861A3978538", - "flasher_args": "-f interface/cmsis-dap.cfg -f target/rp2350.cfg -c \"adapter speed 5000\"", "tests": { + "device": true, "host": false, "dual": false, "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "533D004242"}] - } + }, + "flasher": "openocd", + "flasher_sn": "E6633861A3978538", + "flasher_args": "-f interface/cmsis-dap.cfg -f target/rp2350.cfg -c \"adapter speed 5000\"" }, { "name": "stm32f072disco", @@ -93,12 +106,29 @@ "flasher_sn": "779541626", "flasher_args": "-device stm32f072rb" }, + { + "name": "stm32f723disco", + "uid": "460029001951373031313335", + "build" : { + "flags_on": ["", "CFG_TUD_DWC2_DMA"] + }, + "tests": { + "device": true, "host": true, "dual": false, + "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2003414"}] + }, + "flasher": "jlink", + "flasher_sn": "000776606156", + "flasher_args": "-device stm32f723ie" + }, { "name": "stm32h743nucleo", "uid": "110018000951383432343236", "build" : { "flags_on": ["", "CFG_TUD_DWC2_DMA"] }, + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "stlink", "flasher_sn": "004C00343137510F39383538", "flasher_args": "" @@ -106,6 +136,9 @@ { "name": "stm32g0b1nucleo", "uid": "4D0038000450434E37343120", + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "openocd", "flasher_sn": "066FFF495087534867063844", "flasher_args": "-f interface/stlink.cfg -f target/stm32g0x.cfg" @@ -118,6 +151,9 @@ "build" : { "flags_on": ["", "CFG_TUD_DWC2_DMA"] }, + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "jlink", "flasher_sn": "000778170924", "flasher_args": "-device stm32f769ni" @@ -125,6 +161,9 @@ { "name": "mimxrt1015_evk", "uid": "DC28F865D2111D228D00B0543A70463C", + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "jlink", "flasher_sn": "000726284213", "flasher_args": "-device MIMXRT1015DAF5A" @@ -132,6 +171,9 @@ { "name": "nanoch32v203", "uid": "CDAB277B0FBC03E339E339E3", + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "openocd_wch", "flasher_sn": "EBCA8F0670AF", "flasher_args": "" @@ -139,6 +181,9 @@ { "name": "stm32f407disco", "uid": "30001A000647313332353735", + "tests": { + "device": true, "host": false, "dual": false + }, "flasher": "jlink", "flasher_sn": "000773661813", "flasher_args": "-device stm32f407vg" -- cgit v1.3.1 From daef846aa73dc2b8edf5e072832833a6ae68b42a Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 14 Nov 2024 13:26:11 +0700 Subject: rename CFG_TUD_DWC2_DMA to CFG_TUD_DWC2_DMA_ENABLE --- src/common/tusb_mcu.h | 2 +- src/portable/synopsys/dwc2/dcd_dwc2.c | 4 +--- src/tusb_option.h | 4 ++-- test/hil/tinyusb.json | 8 ++++---- 4 files changed, 8 insertions(+), 10 deletions(-) (limited to 'src/portable') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 41f552d33..0a039eadf 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -538,7 +538,7 @@ #define TUP_DCD_EDPT_ISO_ALLOC #endif -#if defined(TUP_USBIP_DWC2) // && CFG_TUD_DWC2_DMA == 0 +#if defined(TUP_USBIP_DWC2) // && CFG_TUD_DWC2_DMA_ENABLE == 0 #define TUP_MEM_CONST_ADDR #endif diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index fe67de8dc..80287305a 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -71,7 +71,7 @@ static bool _sof_en; TU_ATTR_ALWAYS_INLINE static inline bool dma_device_enabled(const dwc2_regs_t* dwc2) { (void) dwc2; // Internal DMA only - return CFG_TUD_DWC2_DMA && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; + return CFG_TUD_DWC2_DMA_ENABLE && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; } static void dma_setup_prepare(uint8_t rhport) { @@ -897,8 +897,6 @@ static void handle_epin_irq(uint8_t rhport) { Note: when OTG_MULTI_PROC_INTRPT = 1, Device Each endpoint interrupt deachint/deachmsk/diepeachmsk/doepeachmsk are combined to generate dedicated interrupt line for each endpoint. */ - - void dcd_int_handler(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); diff --git a/src/tusb_option.h b/src/tusb_option.h index e9b6a5806..6257a87ba 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -252,8 +252,8 @@ // (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable. // For example, on Cortex-M7 the MPU region can be configured as normal // non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0. -#ifndef CFG_TUD_DWC2_DMA - #define CFG_TUD_DWC2_DMA 0 +#ifndef CFG_TUD_DWC2_DMA_ENABLE + #define CFG_TUD_DWC2_DMA_ENABLE 0 #endif // Enable DWC2 Slave mode for host diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json index c15daf1d9..b6c9b540a 100644 --- a/test/hil/tinyusb.json +++ b/test/hil/tinyusb.json @@ -17,7 +17,7 @@ "name": "espressif_s3_devkitm", "uid": "84F703C084E4", "build" : { - "flags_on": ["", "CFG_TUD_DWC2_DMA"] + "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE"] }, "tests": { "only": ["device/cdc_msc_freertos", "device/hid_composite_freertos"] @@ -130,7 +130,7 @@ "name": "stm32f723disco", "uid": "460029001951373031313335", "build" : { - "flags_on": ["", "CFG_TUD_DWC2_DMA"] + "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE"] }, "tests": { "device": true, "host": true, "dual": false, @@ -146,7 +146,7 @@ "name": "stm32h743nucleo", "uid": "110018000951383432343236", "build" : { - "flags_on": ["", "CFG_TUD_DWC2_DMA"] + "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE"] }, "tests": { "device": true, "host": false, "dual": false @@ -175,7 +175,7 @@ "name": "stm32f769disco", "uid": "21002F000F51363531383437", "build" : { - "flags_on": ["", "CFG_TUD_DWC2_DMA"] + "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE"] }, "tests": { "device": true, "host": false, "dual": false -- cgit v1.3.1 From a68c53fb8e3cdf58a95a92b6e079105d194e2c0d Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 14 Nov 2024 17:34:14 +0700 Subject: clean up, add typdef for dwc2 type for device --- src/portable/synopsys/dwc2/dcd_dwc2.c | 192 +++++++++++++++---------------- src/portable/synopsys/dwc2/dwc2_common.c | 9 +- src/portable/synopsys/dwc2/dwc2_common.h | 2 +- src/portable/synopsys/dwc2/dwc2_type.h | 173 ++++++++++++++++++++++------ src/portable/synopsys/dwc2/hcd_dwc2.c | 10 +- 5 files changed, 243 insertions(+), 143 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 80287305a..ae6377a49 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -37,6 +37,12 @@ #include "device/dcd.h" #include "dwc2_common.h" +#if TU_CHECK_MCU(OPT_MCU_GD32VF103) + #define DWC2_EP_COUNT(_dwc2) DWC2_EP_MAX +#else + #define DWC2_EP_COUNT(_dwc2) ((_dwc2)->ghwcfg2_bm.num_dev_ep) +#endif + //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ @@ -282,58 +288,6 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { } } -// Start of Bus Reset -static void bus_reset(uint8_t rhport) { - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint8_t const ep_count = _dwc2_controller[rhport].ep_count; - - tu_memclr(xfer_status, sizeof(xfer_status)); - - _sof_en = false; - _allocated_ep_in_count = 1; - - // 1. NAK for all OUT endpoints - for (uint8_t n = 0; n < ep_count; n++) { - dwc2->epout[n].doepctl |= DOEPCTL_SNAK; - } - - // 2. Disable all IN endpoints - for (uint8_t n = 0; n < ep_count; n++) { - if (dwc2->epin[n].diepctl & DIEPCTL_EPENA) { - dwc2->epin[n].diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS; - } - } - - dfifo_flush_tx(dwc2, 0x10); // all tx fifo - dfifo_flush_rx(dwc2); - - // 3. Set up interrupt mask for EP0 - dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos); - dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM; - dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM; - - // 4. Set up DFIFO - dfifo_device_init(rhport); - - // 5. Reset device address - dwc2->dcfg &= ~DCFG_DAD_Msk; - - // Fixed both control EP0 size to 64 bytes - dwc2->epin[0].diepctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos); - dwc2->epout[0].doepctl &= ~(0x03 << DOEPCTL_MPSIZ_Pos); - - xfer_status[0][TUSB_DIR_OUT].max_size = 64; - xfer_status[0][TUSB_DIR_IN].max_size = 64; - - if(dma_device_enabled(dwc2)) { - dma_setup_prepare(rhport); - } else { - dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); - } - - dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT; -} - static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, uint16_t total_bytes) { (void) rhport; @@ -412,18 +366,10 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Core Initialization const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE); - TU_ASSERT(dwc2_core_init(rhport, is_highspeed)); - - if (dma_device_enabled(dwc2)) { - // DMA seems to be only settable after a core reset, and not possible to switch on-the-fly - dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2; - } else { - dwc2->gintmsk |= GINTSTS_RXFLVL; - } - - // Device Initialization - dcd_disconnect(rhport); + const bool is_dma = dma_device_enabled(dwc2); + TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma)); + //------------- 7.1 Device Initialization -------------// // Set device max speed uint32_t dcfg = dwc2->dcfg & ~DCFG_DSPD_Msk; if (is_highspeed) { @@ -434,20 +380,21 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { if (dwc2->ghwcfg2_bm.hs_phy_type == GHWCFG2_HSPHY_ULPI) { dcfg |= DCFG_XCVRDLY; } - }else { + } else { dcfg |= DCFG_DSPD_FS << DCFG_DSPD_Pos; } + + dcfg |= DCFG_NZLSOHSK; // send STALL back and discard if host send non-zlp during control status dwc2->dcfg = dcfg; + dcd_disconnect(rhport); + // Force device mode dwc2->gusbcfg = (dwc2->gusbcfg & ~GUSBCFG_FHMOD) | GUSBCFG_FDMOD; // Clear A override, force B Valid dwc2->gotgctl = (dwc2->gotgctl & ~GOTGCTL_AVALOEN) | GOTGCTL_BVALOEN | GOTGCTL_BVALOVAL; - // If USB host misbehaves during status portion of control xfer (non zero-length packet), send STALL back and discard - dwc2->dcfg |= DCFG_NZLSOHSK; - // Enable required interrupts dwc2->gintmsk |= GINTMSK_OTGINT | GINTMSK_USBSUSPM | GINTMSK_USBRST | GINTMSK_ENUMDNEM | GINTMSK_WUIM; @@ -677,6 +624,57 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { // Interrupt Handler //-------------------------------------------------------------------- +// 7.4.1 Initialization on USB Reset +static void handle_bus_reset(uint8_t rhport) { + dwc2_regs_t *dwc2 = DWC2_REG(rhport); + const uint8_t ep_count = DWC2_EP_COUNT(dwc2); + + tu_memclr(xfer_status, sizeof(xfer_status)); + + _sof_en = false; + _allocated_ep_in_count = 1; + + // 1. NAK for all OUT endpoints + for (uint8_t n = 0; n < ep_count; n++) { + dwc2->epout[n].doepctl |= DOEPCTL_SNAK; + } + + // Disable all IN endpoints + for (uint8_t n = 0; n < ep_count; n++) { + if (dwc2->epin[n].diepctl & DIEPCTL_EPENA) { + dwc2->epin[n].diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS; + } + } + + // 2. Set up interrupt mask for EP0 + dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos); + dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM; + dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM; + + // 4. Set up DFIFO + dfifo_flush_tx(dwc2, 0x10); // all tx fifo + dfifo_flush_rx(dwc2); + dfifo_device_init(rhport); + + // 5. Reset device address + dwc2->dcfg_bm.address = 0; + + // Fixed both control EP0 size to 64 bytes + dwc2->epin[0].ctl &= ~(0x03 << DIEPCTL_MPSIZ_Pos); + dwc2->epout[0].ctl &= ~(0x03 << DOEPCTL_MPSIZ_Pos); + + xfer_status[0][TUSB_DIR_OUT].max_size = 64; + xfer_status[0][TUSB_DIR_IN].max_size = 64; + + if(dma_device_enabled(dwc2)) { + dma_setup_prepare(rhport); + } else { + dwc2->epout[0].doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); + } + + dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT; +} + // Process shared receive FIFO, this interrupt is only used in Slave mode static void handle_rxflvl_irq(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); @@ -686,7 +684,7 @@ static void handle_rxflvl_irq(uint8_t rhport) { const dwc2_grxstsp_t grxstsp_bm = dwc2->grxstsp_bm; const uint8_t epnum = grxstsp_bm.ep_ch_num; const uint16_t byte_count = grxstsp_bm.byte_count; - dwc2_epout_t* epout = &dwc2->epout[epnum]; + dwc2_dep_t* epout = &dwc2->epout[epnum]; switch (grxstsp_bm.packet_status) { // Global OUT NAK: do nothing @@ -724,7 +722,7 @@ static void handle_rxflvl_irq(uint8_t rhport) { // short packet, minus remaining bytes (xfer_size) if (byte_count < xfer->max_size) { - xfer->total_len -= epout->doeptsiz_bm.xfer_size; + xfer->total_len -= epout->tsiz_bm.xfer_size; if (epnum == 0) { xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; ep0_pending[TUSB_DIR_OUT] = 0; @@ -753,7 +751,7 @@ static void handle_epout_irq(uint8_t rhport) { // OEPINT will be cleared when DAINT's out bits are cleared. for (uint8_t epnum = 0; epnum < ep_count; epnum++) { if (dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + epnum)) { - dwc2_epout_t* epout = &dwc2->epout[epnum]; + dwc2_dep_t* epout = &dwc2->epout[epnum]; const uint32_t doepint = epout->doepint; TU_ASSERT((epout->doepint & DOEPINT_AHBERR) == 0, ); @@ -829,7 +827,7 @@ static void handle_epin_irq(uint8_t rhport) { if (dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + n)) { // IN XFER complete (entire xfer). xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_IN); - dwc2_epin_t* epin = &dwc2->epin[n]; + dwc2_dep_t* epin = &dwc2->epin[n]; if (epin->diepint & DIEPINT_XFRC) { epin->diepint = DIEPINT_XFRC; @@ -852,11 +850,11 @@ static void handle_epin_irq(uint8_t rhport) { // It will only be cleared by hardware when written bytes is more than // - 64 bytes or // - Half/Empty of TX FIFO size (configured by GAHBCFG.TXFELVL) - const uint16_t remain_packets = epin->dieptsiz_bm.packet_count; + const uint16_t remain_packets = epin->tsiz_bm.packet_count; // Process every single packet (only whole packets can be written to fifo) for (uint16_t i = 0; i < remain_packets; i++) { - const uint16_t remain_bytes = (uint16_t) epin->dieptsiz_bm.xfer_size; + const uint16_t remain_bytes = (uint16_t) epin->tsiz_bm.xfer_size; // Packet can not be larger than ep max size const uint16_t xact_bytes = tu_min16(remain_bytes, xfer->max_size); @@ -878,7 +876,7 @@ static void handle_epin_irq(uint8_t rhport) { } // Turn off TXFE if all bytes are written. - if (epin->dieptsiz_bm.xfer_size == 0) { + if (epin->tsiz_bm.xfer_size == 0) { dwc2->diepempmsk &= ~(1 << n); } } @@ -887,12 +885,13 @@ static void handle_epin_irq(uint8_t rhport) { } /* Interrupt Hierarchy - - DxEPINTn - | - DAINT.xEPn - | - GINTSTS: xEPInt + DIEPINT DIEPINT + \ / + \ / + DAINT + / \ + / \ + GINTSTS: OEPInt IEPInt | USBReset | EnumDone | USBSusp | WkUpInt | OTGInt | SOF | RXFLVL Note: when OTG_MULTI_PROC_INTRPT = 1, Device Each endpoint interrupt deachint/deachmsk/diepeachmsk/doepeachmsk are combined to generate dedicated interrupt line for each endpoint. @@ -901,46 +900,45 @@ void dcd_int_handler(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint32_t const int_mask = dwc2->gintmsk; - uint32_t const int_status = dwc2->gintsts & int_mask; + uint32_t const gintsts = dwc2->gintsts & int_mask; - if (int_status & GINTSTS_USBRST) { + if (gintsts & GINTSTS_USBRST) { // USBRST is start of reset. dwc2->gintsts = GINTSTS_USBRST; - bus_reset(rhport); + handle_bus_reset(rhport); } - if (int_status & GINTSTS_ENUMDNE) { + if (gintsts & GINTSTS_ENUMDNE) { // ENUMDNE is the end of reset where speed of the link is detected dwc2->gintsts = GINTSTS_ENUMDNE; tusb_speed_t speed; - switch ((dwc2->dsts & DSTS_ENUMSPD_Msk) >> DSTS_ENUMSPD_Pos) { - case DSTS_ENUMSPD_HS: + switch (dwc2->dsts_bm.enum_speed) { + case DCFG_SPEED_HIGH: speed = TUSB_SPEED_HIGH; break; - case DSTS_ENUMSPD_LS: + case DCFG_SPEED_LOW: speed = TUSB_SPEED_LOW; break; - case DSTS_ENUMSPD_FS_HSPHY: - case DSTS_ENUMSPD_FS: + case DCFG_SPEED_FULL_30_60MHZ: + case DCFG_SPEED_FULL_48MHZ: default: speed = TUSB_SPEED_FULL; break; } // TODO must update GUSBCFG_TRDT according to link speed - dcd_event_bus_reset(rhport, speed, true); } - if (int_status & GINTSTS_USBSUSP) { + if (gintsts & GINTSTS_USBSUSP) { dwc2->gintsts = GINTSTS_USBSUSP; dcd_event_bus_signal(rhport, DCD_EVENT_SUSPEND, true); } - if (int_status & GINTSTS_WKUINT) { + if (gintsts & GINTSTS_WKUINT) { dwc2->gintsts = GINTSTS_WKUINT; dcd_event_bus_signal(rhport, DCD_EVENT_RESUME, true); } @@ -948,7 +946,7 @@ void dcd_int_handler(uint8_t rhport) { // TODO check GINTSTS_DISCINT for disconnect detection // if(int_status & GINTSTS_DISCINT) - if (int_status & GINTSTS_OTGINT) { + if (gintsts & GINTSTS_OTGINT) { // OTG INT bit is read-only uint32_t const otg_int = dwc2->gotgint; @@ -959,7 +957,7 @@ void dcd_int_handler(uint8_t rhport) { dwc2->gotgint = otg_int; } - if(int_status & GINTSTS_SOF) { + if(gintsts & GINTSTS_SOF) { dwc2->gintsts = GINTSTS_SOF; const uint32_t frame = (dwc2->dsts & DSTS_FNSOF) >> DSTS_FNSOF_Pos; @@ -972,7 +970,7 @@ void dcd_int_handler(uint8_t rhport) { } // RxFIFO non-empty interrupt handling. - if (int_status & GINTSTS_RXFLVL) { + if (gintsts & GINTSTS_RXFLVL) { // RXFLVL bit is read-only dwc2->gintmsk &= ~GINTMSK_RXFLVLM; // disable RXFLVL interrupt while reading @@ -984,13 +982,13 @@ void dcd_int_handler(uint8_t rhport) { } // OUT endpoint interrupt handling. - if (int_status & GINTSTS_OEPINT) { + if (gintsts & GINTSTS_OEPINT) { // OEPINT is read-only, clear using DOEPINTn handle_epout_irq(rhport); } // IN endpoint interrupt handling. - if (int_status & GINTSTS_IEPINT) { + if (gintsts & GINTSTS_IEPINT) { // IEPINT bit read-only, clear using DIEPINTn handle_epin_irq(rhport); } diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index 4d62cf3c6..ef155c8f7 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -194,7 +194,7 @@ bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role) { * In addition, UTMI+/ULPI can be shared to run at fullspeed mode with 48Mhz * */ -bool dwc2_core_init(uint8_t rhport, bool is_highspeed) { +bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); // Check Synopsys ID register, failed if controller clock/power is not enabled @@ -229,6 +229,13 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed) { dwc2->gotgint = 0xFFFFFFFFU; dwc2->gintmsk = 0; + if (is_dma) { + // DMA seems to be only settable after a core reset, and not possible to switch on-the-fly + dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2; + } else { + dwc2->gintmsk |= GINTSTS_RXFLVL; + } + return true; } diff --git a/src/portable/synopsys/dwc2/dwc2_common.h b/src/portable/synopsys/dwc2/dwc2_common.h index 3f7f23c3a..18b93894f 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.h +++ b/src/portable/synopsys/dwc2/dwc2_common.h @@ -73,7 +73,7 @@ TU_ATTR_ALWAYS_INLINE static inline dwc2_regs_t* DWC2_REG(uint8_t rhport) { } bool dwc2_core_is_highspeed(dwc2_regs_t* dwc2, tusb_role_t role); -bool dwc2_core_init(uint8_t rhport, bool is_highspeed); +bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma); void dwc2_core_handle_common_irq(uint8_t rhport, bool in_isr); //--------------------------------------------------------------------+ diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 1247f19a3..01e10ee00 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -171,6 +171,13 @@ enum { HCCHAR_EPTYPE_INTERRUPT = 3 }; +enum { + DCFG_SPEED_HIGH = 0, // Highspeed with 30/60 Mhz + DCFG_SPEED_FULL_30_60MHZ = 1, // Fullspeed with UTMI+/ULPI 30/60 Mhz + DCFG_SPEED_LOW = 2, // Lowspeed with FS PHY at 6 Mhz + DCFG_SPEED_FULL_48MHZ = 3, // Fullspeed with dedicated FS PHY at 48 Mhz +}; + //-------------------------------------------------------------------- // Common Register Bitfield //-------------------------------------------------------------------- @@ -469,47 +476,126 @@ typedef struct { // Device Register Bitfield //-------------------------------------------------------------------- typedef struct TU_ATTR_PACKED { - uint32_t xfer_size : 19; // 0..18 Transfer size in bytes - uint32_t packet_count : 10; // 19..28 Number of packets - uint32_t mc_pid : 2; // 29..30 IN: Multi Count, OUT: PID -} dwc2_ep_tsize_t; -TU_VERIFY_STATIC(sizeof(dwc2_ep_tsize_t) == 4, "incorrect size"); + uint32_t speed : 2; // 0..1 Speed + uint32_t nzsts_out_handshake : 1; // 2 Non-zero-length status OUT handshake + uint32_t en_32khz_suspsend : 1; // 3 Enable 32-kHz SUSPEND mode + uint32_t address : 7; // 4..10 Device address + uint32_t period_frame_interval : 2; // 11..12 Periodic frame interval + uint32_t en_out_nak : 1; // 13 Enable Device OUT NAK + uint32_t xcvr_delay : 1; // 14 Transceiver delay + uint32_t erratic_int_mask : 1; // 15 Erratic interrupt mask + uint32_t rsv16 : 1; // 16 Reserved + uint32_t ipg_iso_support : 1; // 17 Interpacket gap ISO support + uint32_t epin_mismatch_count : 5; // 18..22 EP IN mismatch count + uint32_t dma_desc : 1; // 23 Enable scatter/gatter DMA descriptor + uint32_t period_schedule_interval : 2; // 24..25 Periodic schedule interval for scatter/gatter DMA + uint32_t resume_valid : 6; // 26..31 Resume valid period +} dwc2_dcfg_t; +TU_VERIFY_STATIC(sizeof(dwc2_dcfg_t) == 4, "incorrect size"); -// Endpoint IN -typedef struct { - volatile uint32_t diepctl; // 900 + 20*ep Device IN Endpoint Control - uint32_t reserved04; // 904 - volatile uint32_t diepint; // 908 + 20*ep Device IN Endpoint Interrupt - uint32_t reserved0c; // 90C - union { - volatile uint32_t dieptsiz; // 910 + 20*ep Device IN Endpoint Transfer Size - volatile dwc2_ep_tsize_t dieptsiz_bm; - }; - volatile uint32_t diepdma; // 914 + 20*ep Device IN Endpoint DMA Address - volatile uint32_t dtxfsts; // 918 + 20*ep Device IN Endpoint Tx FIFO Status - uint32_t reserved1c; // 91C -} dwc2_epin_t; +typedef struct TU_ATTR_PACKED { + uint32_t remote_wakeup_signal : 1; // 0 Remote wakeup signal + uint32_t soft_disconnet : 1; // 1 Soft disconnect + uint32_t gnp_in_nak_status : 1; // 2 Global non-periodic NAK IN status + uint32_t gout_nak_status : 1; // 3 Global OUT NAK status + uint32_t test_control : 3; // 4..6 Test control + uint32_t set_gnp_in_nak : 1; // 7 Set global non-periodic IN NAK + uint32_t clear_gnp_in_nak : 1; // 8 Clear global non-periodic IN NAK + uint32_t set_gout_nak : 1; // 9 Set global OUT NAK + uint32_t clear_gout_nak : 1; // 10 Clear global OUT NAK + uint32_t poweron_prog_done : 1; // 11 Power-on programming done + uint32_t rsv12 : 1; // 12 Reserved + uint32_t global_multi_count : 2; // 13..14 Global multi-count + uint32_t ignore_frame_number : 1; // 15 Ignore frame number + uint32_t nak_on_babble : 1; // 16 NAK on babble + uint32_t en_cont_on_bna : 1; // 17 Enable continue on BNA + uint32_t deep_sleep_besl_reject : 1 ; // 18 Deep sleep BESL reject + uint32_t service_interval : 1; // 19 Service interval for ISO IN endpoint + uint32_t rsv20_31 : 12; // 20..31 Reserved +} dwc2_dctl_t; +TU_VERIFY_STATIC(sizeof(dwc2_dctl_t) == 4, "incorrect size"); -// Endpoint OUT -typedef struct { - volatile uint32_t doepctl; // B00 + 20*ep Device OUT Endpoint Control - uint32_t reserved04; // B04 - volatile uint32_t doepint; // B08 + 20*ep Device OUT Endpoint Interrupt - uint32_t reserved0c; // B0C - union { - volatile uint32_t doeptsiz; // B10 + 20*ep Device OUT Endpoint Transfer Size - volatile dwc2_ep_tsize_t doeptsiz_bm; - }; - volatile uint32_t doepdma; // B14 + 20*ep Device OUT Endpoint DMA Address - uint32_t reserved18[2]; // B18..B1C -} dwc2_epout_t; +typedef struct TU_ATTR_PACKED { + uint32_t suspend_status : 1; // 0 Suspend status + uint32_t enum_speed : 2; // 1..2 Enumerated speed + uint32_t erratic_err : 1; // 3 Erratic error + uint32_t rsv4_7 : 4; // 4..7 Reserved + uint32_t frame_number : 14; // 8..21 Frame/MicroFrame number + uint32_t line_status : 2; // 22..23 Line status + uint32_t rsv24_31 : 8; // 24..31 Reserved +} dwc2_dsts_t; +TU_VERIFY_STATIC(sizeof(dwc2_dsts_t) == 4, "incorrect size"); + +typedef struct TU_ATTR_PACKED { + uint32_t xfer_complete : 1; // 0 Transfer complete + uint32_t disabled : 1; // 1 Endpoint disabled + uint32_t ahb_err : 1; // 2 AHB error + uint32_t timeout : 1; // 3 Timeout + uint32_t in_rx_txfe : 1; // 4 IN token received when TxFIFO is empty + uint32_t in_rx_ep_mismatch : 1; // 5 IN token received with EP mismatch + uint32_t in_ep_nak_effective : 1; // 6 IN endpoint NAK effective + uint32_t rsv7 : 1; // 7 Reserved + uint32_t txfifo_underrun : 1; // 8 Tx FIFO underrun + uint32_t bna : 1; // 9 Buffer not available + uint32_t rsv10_12 : 3; // 10..12 Reserved + uint32_t nak : 1; // 13 NAK + uint32_t rsv14_31 : 18; // 14..31 Reserved +} dwc2_diepint_t; +TU_VERIFY_STATIC(sizeof(dwc2_diepint_t) == 4, "incorrect size"); + +typedef struct TU_ATTR_PACKED { + uint32_t mps : 11; // 0..10 Maximum packet size, EP0 only use 2 bit + uint32_t next_ep : 4; // 11..14 Next endpoint number + uint32_t active : 1; // 15 Active + const uint32_t dpid_iso_odd : 1; // 16 DATA0/DATA1 for bulk/interrupt, odd frame for isochronous + const uint32_t nak_status : 1; // 17 NAK status + uint32_t type : 2; // 18..19 Endpoint type + uint32_t rsv20 : 1; // 20 Reserved + uint32_t stall : 1; // 21 Stall + uint32_t tx_fifo_num : 4; // 22..25 Tx FIFO number (IN) + uint32_t clear_nak : 1; // 26 Clear NAK + uint32_t set_nak : 1; // 27 Set NAK + uint32_t set_data0_iso_even : 1; // 28 Set DATA0 if bulk/interrupt, even frame for isochronous + uint32_t set_data1_iso_odd : 1; // 29 Set DATA1 if bulk/interrupt, odd frame for isochronous + uint32_t disable : 1; // 30 Disable + uint32_t enable : 1; // 31 Enable +} dwc2_depctl_t; +TU_VERIFY_STATIC(sizeof(dwc2_depctl_t) == 4, "incorrect size"); -// Universal Endpoint +typedef struct TU_ATTR_PACKED { + uint32_t xfer_complete : 1; // 0 Transfer complete + uint32_t disabled : 1; // 1 Endpoint disabled + uint32_t ahb_err : 1; // 2 AHB error + uint32_t setup_phase_done : 1; // 3 Setup phase done + uint32_t out_rx_ep_disabled : 1; // 4 OUT token received when endpoint disabled + uint32_t status_phase_rx : 1; // 5 Status phase received + uint32_t setup_b2b : 1; // 6 Setup packet back-to-back + uint32_t rsv7 : 1; // 7 Reserved + uint32_t out_packet_err : 1; // 8 OUT packet error + uint32_t bna : 1; // 9 Buffer not available + uint32_t rsv10_11 : 2; // 10..11 Reserved + uint32_t babble_err : 1; // 12 Babble error + uint32_t nak : 1; // 13 NAK + uint32_t nyet : 1; // 14 NYET + uint32_t rsv15_31 : 16; // 15..31 Reserved +} dwc2_doepint_t; +TU_VERIFY_STATIC(sizeof(dwc2_doepint_t) == 4, "incorrect size"); + +typedef struct TU_ATTR_PACKED { + uint32_t xfer_size : 19; // 0..18 Transfer size in bytes + uint32_t packet_count : 10; // 19..28 Number of packets + uint32_t mc_pid : 2; // 29..30 IN: Multi Count, OUT: PID +} dwc2_ep_tsize_t; +TU_VERIFY_STATIC(sizeof(dwc2_ep_tsize_t) == 4, "incorrect size"); + +// Device IN/OUT Endpoint typedef struct { union { volatile uint32_t diepctl; volatile uint32_t doepctl; + volatile uint32_t ctl; + volatile dwc2_depctl_t ctrl_bm; }; uint32_t rsv04; union { @@ -520,7 +606,7 @@ typedef struct { union { volatile uint32_t dieptsiz; volatile uint32_t doeptsiz; - volatile dwc2_ep_tsize_t deptsiz_bm; + volatile dwc2_ep_tsize_t tsiz_bm; }; union { volatile uint32_t diepdma; @@ -631,12 +717,27 @@ typedef struct { uint32_t reserved700[64]; // 700..7FF //------------- Device -----------// + union { volatile uint32_t dcfg; // 800 Device Configuration + volatile dwc2_dcfg_t dcfg_bm; + }; + union { volatile uint32_t dctl; // 804 Device Control + volatile dwc2_dctl_t dctl_bm; + }; + union { volatile uint32_t dsts; // 808 Device Status (RO) + volatile dwc2_dsts_t dsts_bm; + }; uint32_t reserved80c; // 80C + union { volatile uint32_t diepmsk; // 810 Device IN Endpoint Interrupt Mask + volatile dwc2_diepint_t diepmsk_bm; + }; + union { volatile uint32_t doepmsk; // 814 Device OUT Endpoint Interrupt Mask + volatile dwc2_doepint_t doepmsk_bm; + }; volatile uint32_t daint; // 818 Device All Endpoints Interrupt volatile uint32_t daintmsk; // 81C Device All Endpoints Interrupt Mask volatile uint32_t dtknqr1; // 820 Device IN token sequence learning queue read1 @@ -658,8 +759,8 @@ typedef struct { union { dwc2_dep_t ep[2][16]; // 0: IN, 1 OUT struct { - dwc2_epin_t epin[16]; // 900..AFF IN Endpoints - dwc2_epout_t epout[16]; // B00..CFF OUT Endpoints + dwc2_dep_t epin[16]; // 900..AFF IN Endpoints + dwc2_dep_t epout[16]; // B00..CFF OUT Endpoints }; }; uint32_t reservedd00[64]; // D00..DFF diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 53583426f..550778876 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -336,14 +336,8 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Core Initialization const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_HOST); - TU_ASSERT(dwc2_core_init(rhport, is_highspeed)); - - if (dma_host_enabled(dwc2)) { - // DMA seems to be only settable after a core reset, and not possible to switch on-the-fly - dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2; - } else { - dwc2->gintmsk |= GINTSTS_RXFLVL; - } + const bool is_dma = dma_host_enabled(dwc2); + TU_ASSERT(dwc2_core_init(rhport, is_highspeed, is_dma)); //------------- 3.1 Host Initialization -------------// -- cgit v1.3.1 From a780071d20d26ee308acda0e84096563f4f47f41 Mon Sep 17 00:00:00 2001 From: Chintalagiri Shashank Date: Fri, 8 Nov 2024 18:13:54 +0530 Subject: Add support for STM32H7RSxx --- src/common/tusb_mcu.h | 7 +++++++ src/portable/synopsys/dwc2/dwc2_stm32.h | 8 ++++++++ src/tusb_option.h | 1 + 3 files changed, 16 insertions(+) (limited to 'src/portable') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 41f552d33..0264da89e 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -299,6 +299,13 @@ #define TUP_USBIP_FSDEV_STM32 #define TUP_DCD_ENDPOINT_MAX 8 +#elif TU_CHECK_MCU(OPT_MCU_STM32H7RS) + #define TUP_USBIP_DWC2 + #define TUP_USBIP_DWC2_STM32 + + // FS has 6, HS has 9 + #define TUP_DCD_ENDPOINT_MAX 9 + //--------------------------------------------------------------------+ // Sony //--------------------------------------------------------------------+ diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index 8719c4820..c11c1eb05 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -69,6 +69,14 @@ extern "C" { #define OTG_FS_IRQn OTG_HS_IRQn #endif +#elif CFG_TUSB_MCU == OPT_MCU_STM32H7RS + #include "stm32h7rsxx.h" + #define EP_MAX_FS 6 + #define EP_FIFO_SIZE_FS 1280 + + #define EP_MAX_HS 9 + #define EP_FIFO_SIZE_HS 4096 + #elif CFG_TUSB_MCU == OPT_MCU_STM32F7 #include "stm32f7xx.h" #define EP_MAX_FS 6 diff --git a/src/tusb_option.h b/src/tusb_option.h index e9b6a5806..8bc30e940 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -92,6 +92,7 @@ #define OPT_MCU_STM32L5 314 ///< ST L5 #define OPT_MCU_STM32H5 315 ///< ST H5 #define OPT_MCU_STM32U0 316 ///< ST U0 +#define OPT_MCU_STM32H7RS 317 ///< ST F7RS // Sony #define OPT_MCU_CXD56 400 ///< SONY CXD56 -- cgit v1.3.1 From db7670a3bcd502193d138041c20d401bc3f59001 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 18 Nov 2024 11:35:46 +0700 Subject: separate handle out dma and slave separate edpt_schedule_packets into epout/epin xfer --- src/portable/synopsys/dwc2/dcd_dwc2.c | 357 ++++++++++++++++++++------------- src/portable/synopsys/dwc2/dwc2_type.h | 41 ++-- src/portable/synopsys/dwc2/hcd_dwc2.c | 4 +- 3 files changed, 243 insertions(+), 159 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index ae6377a49..6ca1433a6 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -288,72 +288,118 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { } } -static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, - uint16_t total_bytes) { - (void) rhport; +static inline void iso_set_odd_even(dwc2_regs_t* dwc2, dwc2_depctl_t* depctl_bm) { + // Take odd/even bit from frame counter. + const uint32_t odd_now = (dwc2->dsts_bm.frame_number & 1u); + if (odd_now) { + depctl_bm->set_data0_iso_even = 1; + } else { + depctl_bm->set_data1_iso_odd = 1; + } +} - dwc2_regs_t* dwc2 = DWC2_REG(rhport); +static void epout_xfer(dwc2_regs_t* dwc2, const uint8_t epnum, const uint16_t num_packets, uint16_t total_bytes) { + const uint8_t dir = TUSB_DIR_OUT; xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir); + dwc2_dep_t* dep = &dwc2->epout[epnum]; // EP0 is limited to one packet each xfer // We use multiple transaction of xfer->max_size length to get a whole transfer done - if (epnum == 0) { - total_bytes = tu_min16(ep0_pending[dir], xfer->max_size); - ep0_pending[dir] -= total_bytes; + // if (epnum == 0) { + // total_bytes = tu_min16(ep0_pending[dir], xfer->max_size); + // ep0_pending[dir] -= total_bytes; + // } + + // transfer size: A full OUT transfer (multiple packets, possibly) triggers XFRC. + union { + uint32_t value; + dwc2_ep_tsize_t bm; + } deptsiz; + deptsiz.value = 0; + deptsiz.bm.xfer_size = total_bytes; + deptsiz.bm.packet_count = num_packets; + + dep->tsiz = deptsiz.value; + + // control + union { + dwc2_depctl_t bm; + uint32_t value; + } depctl; + depctl.value = dep->ctl; + + if (depctl.bm.type == DEPCTL_EPTYPE_ISOCHRONOUS && xfer->interval == 1) { + iso_set_odd_even(dwc2, &depctl.bm); + } + + if(dma_device_enabled(dwc2)) { + dep->doepdma = (uintptr_t) xfer->buffer; } - // IN and OUT endpoint xfers are interrupt-driven, we just schedule them here. - const uint8_t is_epout = 1 - dir; - dwc2_dep_t* dep = &dwc2->ep[is_epout][epnum]; + depctl.bm.clear_nak = 1; + depctl.bm.enable = 1; - if (dir == TUSB_DIR_IN) { - // A full IN transfer (multiple packets, possibly) triggers XFRC. - dep->dieptsiz = (num_packets << DIEPTSIZ_PKTCNT_Pos) | - ((total_bytes << DIEPTSIZ_XFRSIZ_Pos) & DIEPTSIZ_XFRSIZ_Msk); - - if(dma_device_enabled(dwc2)) { - dep->diepdma = (uintptr_t)xfer->buffer; - - // For ISO endpoint set correct odd/even bit for next frame. - if ((dep->diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { - // Take odd/even bit from frame counter. - uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); - dep->diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); - } + dep->doepctl = depctl.value; +} - dep->diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; - } else { - dep->diepctl |= DIEPCTL_EPENA | DIEPCTL_CNAK; +static void epin_xfer(dwc2_regs_t* dwc2, const uint8_t epnum, const uint16_t num_packets, uint16_t total_bytes) { + const uint8_t dir = TUSB_DIR_IN; + xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir); + dwc2_dep_t* dep = &dwc2->epin[epnum]; + + // A full IN transfer (multiple packets, possibly) triggers XFRC. + union { + uint32_t value; + dwc2_ep_tsize_t bm; + } deptsiz; + deptsiz.value = 0; + deptsiz.bm.xfer_size = total_bytes; + deptsiz.bm.packet_count = num_packets; + + dep->tsiz = deptsiz.value; + + // control + union { + dwc2_depctl_t bm; + uint32_t value; + } depctl; + depctl.value = dep->ctl; + + depctl.bm.clear_nak = 1; + depctl.bm.enable = 1; + if (depctl.bm.type == DEPCTL_EPTYPE_ISOCHRONOUS && xfer->interval == 1) { + iso_set_odd_even(dwc2, &depctl.bm); + } - // For ISO endpoint set correct odd/even bit for next frame. - if ((dep->diepctl & DIEPCTL_EPTYP) == DIEPCTL_EPTYP_0 && (XFER_CTL_BASE(epnum, dir))->interval == 1) { - // Take odd/even bit from frame counter. - uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); - dep->diepctl |= (odd_frame_now ? DIEPCTL_SD0PID_SEVNFRM_Msk : DIEPCTL_SODDFRM_Msk); - } - // Enable fifo empty interrupt only if there are something to put in the fifo. - if (total_bytes != 0) { - dwc2->diepempmsk |= (1 << epnum); - } - } + if(dma_device_enabled(dwc2)) { + dep->diepdma = (uintptr_t)xfer->buffer; + dep->diepctl = depctl.value; } else { - // A full OUT transfer (multiple packets, possibly) triggers XFRC. - dep->doeptsiz &= ~(DOEPTSIZ_PKTCNT_Msk | DOEPTSIZ_XFRSIZ); - dep->doeptsiz |= (num_packets << DOEPTSIZ_PKTCNT_Pos) | - ((total_bytes << DOEPTSIZ_XFRSIZ_Pos) & DOEPTSIZ_XFRSIZ_Msk); - - if ((dep->doepctl & DOEPCTL_EPTYP) == DOEPCTL_EPTYP_0 && - XFER_CTL_BASE(epnum, dir)->interval == 1) { - // Take odd/even bit from frame counter. - uint32_t const odd_frame_now = (dwc2->dsts & (1u << DSTS_FNSOF_Pos)); - dep->doepctl |= (odd_frame_now ? DOEPCTL_SD0PID_SEVNFRM_Msk : DOEPCTL_SODDFRM_Msk); - } + dep->diepctl = depctl.value; - if(dma_device_enabled(dwc2)) { - dep->doepdma = (uintptr_t)xfer->buffer; + // Enable fifo empty interrupt only if there are something to put in the fifo. + if (total_bytes != 0) { + dwc2->diepempmsk |= (1 << epnum); } + } +} + +static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, + uint16_t total_bytes) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir); + + // EP0 is limited to one packet each xfer + // We use multiple transaction of xfer->max_size length to get a whole transfer done + if (epnum == 0) { + total_bytes = tu_min16(ep0_pending[dir], xfer->max_size); + ep0_pending[dir] -= total_bytes; + } - dep->doepctl |= DOEPCTL_EPENA | DOEPCTL_CNAK; + if (dir == TUSB_DIR_IN) { + epin_xfer(dwc2, epnum, num_packets, total_bytes); + } else { + epout_xfer(dwc2, epnum, num_packets, total_bytes); } } @@ -683,135 +729,164 @@ static void handle_rxflvl_irq(uint8_t rhport) { // Pop control word off FIFO const dwc2_grxstsp_t grxstsp_bm = dwc2->grxstsp_bm; const uint8_t epnum = grxstsp_bm.ep_ch_num; - const uint16_t byte_count = grxstsp_bm.byte_count; + dwc2_dep_t* epout = &dwc2->epout[epnum]; switch (grxstsp_bm.packet_status) { - // Global OUT NAK: do nothing - case GRXSTS_PKTSTS_GLOBALOUTNAK: + case GRXSTS_PKTSTS_GLOBAL_OUT_NAK: + // Global OUT NAK: do nothing break; - case GRXSTS_PKTSTS_SETUPRX: + case GRXSTS_PKTSTS_SETUP_RX: // Setup packet received - // We can receive up to three setup packets in succession, but only the last one is valid. + // We can receive up to three setup packets in succession, but only the last one is valid. _setup_packet[0] = (*rx_fifo); _setup_packet[1] = (*rx_fifo); break; - case GRXSTS_PKTSTS_SETUPDONE: + case GRXSTS_PKTSTS_SETUP_DONE: // Setup packet done: // After popping this out, dwc2 asserts a DOEPINT_SETUP interrupt which is handled by handle_epout_irq() epout->doeptsiz |= (3 << DOEPTSIZ_STUPCNT_Pos); break; - case GRXSTS_PKTSTS_OUTRX: { + case GRXSTS_PKTSTS_RX_DATA: { // Out packet received + const uint16_t byte_count = grxstsp_bm.byte_count; xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - // Read packet off RxFIFO - if (xfer->ff) { - // Ring buffer - tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, byte_count); - } else { - // Linear buffer - dfifo_read_packet(dwc2, xfer->buffer, byte_count); - - // Increment pointer to xfer data - xfer->buffer += byte_count; - } + if (byte_count) { + // Read packet off RxFIFO + if (xfer->ff) { + tu_fifo_write_n_const_addr_full_words(xfer->ff, (const void*) (uintptr_t) rx_fifo, byte_count); + } else { + dfifo_read_packet(dwc2, xfer->buffer, byte_count); + xfer->buffer += byte_count; + } - // short packet, minus remaining bytes (xfer_size) - if (byte_count < xfer->max_size) { - xfer->total_len -= epout->tsiz_bm.xfer_size; - if (epnum == 0) { - xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; - ep0_pending[TUSB_DIR_OUT] = 0; + // short packet, minus remaining bytes (xfer_size) + if (byte_count < xfer->max_size) { + xfer->total_len -= epout->tsiz_bm.xfer_size; + if (epnum == 0) { + xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; + ep0_pending[TUSB_DIR_OUT] = 0; + } } } break; } - case GRXSTS_PKTSTS_OUTDONE: - /* Out packet done - After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed interrupt on - the specified OUT endpoint which will be handled by handle_epout_irq() */ + case GRXSTS_PKTSTS_RX_COMPLETE: + // Out packet done + // After this entry is popped from the receive FIFO, dwc2 asserts a Transfer Completed interrupt on + // the specified OUT endpoint which will be handled by handle_epout_irq() break; - default: - TU_BREAKPOINT(); - break; + default: break; } } -static void handle_epout_irq(uint8_t rhport) { - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint8_t const ep_count = _dwc2_controller[rhport].ep_count; +static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) { + // dwc2_regs_t* dwc2 = DWC2_REG(rhport); - // DAINT for a given EP clears when DOEPINTx is cleared. - // OEPINT will be cleared when DAINT's out bits are cleared. - for (uint8_t epnum = 0; epnum < ep_count; epnum++) { - if (dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + epnum)) { - dwc2_dep_t* epout = &dwc2->epout[epnum]; - const uint32_t doepint = epout->doepint; - TU_ASSERT((epout->doepint & DOEPINT_AHBERR) == 0, ); + if (doepint_bm.setup_phase_done) { + dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); + return; + } - // Setup and/or STPKTRX/STSPHSRX (from 3.00a) can be set along with XFRC, and also set independently. - if (dwc2->gsnpsid >= DWC2_CORE_REV_3_00a) { - if (doepint & DOEPINT_STSPHSRX) { - // Status phase received for control write: In token received from Host - epout->doepint = DOEPINT_STSPHSRX; - } + // Normal OUT transfer complete + if (doepint_bm.xfer_complete) { + // only handle data skip if it is setup or status related + // Note: even though (xfer_complete + status_phase_rx) is for buffered DMA only, for STM32L47x (dwc2 v3.00a) they + // can is set when GRXSTS_PKTSTS_SETUP_RX is popped therefore they can bet set before/together with setup_phase_done + if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) { + xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - if (doepint & DOEPINT_STPKTRX) { - // New setup packet received, but wait for Setup done, since we can receive up to 3 setup consecutively - epout->doepint = DOEPINT_STPKTRX; - } + // EP0 can only handle one packet + if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { + // Schedule another packet to be received. + edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + } else { + dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); } + } + } +} + +static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + + if (doepint_bm.setup_phase_done) { + dma_setup_prepare(rhport); + dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); + return; + } + + // OUT XFER complete + if (doepint_bm.xfer_complete) { + // only handle data skip if it is setup or status related + // Normal OUT transfer complete + if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) { + if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { + // EP0 can only handle one packet Schedule another packet to be received. + edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + } else { + dwc2_dep_t* epout = &dwc2->epout[epnum]; + xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - if (doepint & DOEPINT_SETUP) { - epout->doepint = DOEPINT_SETUP; + // determine actual received bytes + const uint16_t remain = epout->tsiz_bm.xfer_size; + xfer->total_len -= remain; - if(dma_device_enabled(dwc2)) { + // this is ZLP, so prepare EP0 for next setup + if(epnum == 0 && xfer->total_len == 0) { dma_setup_prepare(rhport); } - dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); + dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); } + } + } +} - // OUT XFER complete - if (doepint & DOEPINT_XFRC) { - epout->doepint = DOEPINT_XFRC; - - // only handle data skip if it is setup or status related - // Normal OUT transfer complete - if (!(doepint & (DOEPINT_SETUP | DOEPINT_STPKTRX | DOEPINT_STSPHSRX))) { - xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - - if(dma_device_enabled(dwc2)) { - if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { - // EP0 can only handle one packet Schedule another packet to be received. - edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); - } else { - // Fix packet length - uint16_t remain = (epout->doeptsiz & DOEPTSIZ_XFRSIZ_Msk) >> DOEPTSIZ_XFRSIZ_Pos; - xfer->total_len -= remain; - // this is ZLP, so prepare EP0 for next setup - if(epnum == 0 && xfer->total_len == 0) { - dma_setup_prepare(rhport); - } - - dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); - } - } else { - // EP0 can only handle one packet - if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { - // Schedule another packet to be received. - edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); - } else { - dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); - } - } - } +#if 0 +TU_ATTR_ALWAYS_INLINE static inline void print_doepint(uint32_t doepint) { + const char* str[] = { + "XFRC", "DIS", "AHBERR", "SETUP_DONE", + "ORXED", "STATUS_RX", "SETUP_B2B", "RSV7", + "OPERR", "BNA", "RSV10", "ISODROP", + "BBLERR", "NAK", "NYET", "SETUP_RX" + }; + + for(uint32_t i=0; idaint & TU_BIT(DAINT_OEPINT_Pos + epnum)) { + dwc2_dep_t* epout = &dwc2->epout[epnum]; + const uint32_t doepint = epout->doepint; + const dwc2_doepint_t doepint_bm = epout->doepint_bm; + + epout->doepint = doepint; // Clear interrupt + + // print_doepint(doepint); + if (is_dma) { + handle_epout_dma(rhport, epnum, doepint_bm); + } else { + handle_epout_slave(rhport, epnum, doepint_bm); } } } diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index 01e10ee00..b67771a4d 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -149,17 +149,12 @@ enum { }; enum { - GRXSTS_PKTSTS_GLOBALOUTNAK = 1, - GRXSTS_PKTSTS_OUTRX = 2, - GRXSTS_PKTSTS_OUTDONE = 3, - GRXSTS_PKTSTS_SETUPDONE = 4, - GRXSTS_PKTSTS_SETUPRX = 6 -}; - -enum { - GRXSTS_PKTSTS_RX_DATA = 2, - GRXSTS_PKTSTS_RX_COMPLETE = 3, + GRXSTS_PKTSTS_GLOBAL_OUT_NAK = 1, + GRXSTS_PKTSTS_RX_DATA = 2, + GRXSTS_PKTSTS_RX_COMPLETE = 3, + GRXSTS_PKTSTS_SETUP_DONE = 4, GRXSTS_PKTSTS_HOST_DATATOGGLE_ERR = 5, + GRXSTS_PKTSTS_SETUP_RX = 6, GRXSTS_PKTSTS_HOST_CHANNEL_HALTED = 7 }; @@ -178,6 +173,14 @@ enum { DCFG_SPEED_FULL_48MHZ = 3, // Fullspeed with dedicated FS PHY at 48 Mhz }; +// Same as TUSB_XFER_* +enum { + DEPCTL_EPTYPE_CONTROL = 0, + DEPCTL_EPTYPE_ISOCHRONOUS = 1, + DEPCTL_EPTYPE_BULK = 2, + DEPCTL_EPTYPE_INTERRUPT = 3 +}; + //-------------------------------------------------------------------- // Common Register Bitfield //-------------------------------------------------------------------- @@ -507,11 +510,11 @@ typedef struct TU_ATTR_PACKED { uint32_t rsv12 : 1; // 12 Reserved uint32_t global_multi_count : 2; // 13..14 Global multi-count uint32_t ignore_frame_number : 1; // 15 Ignore frame number - uint32_t nak_on_babble : 1; // 16 NAK on babble + uint32_t nak_on_babble : 1; // 16 NAK on babble uint32_t en_cont_on_bna : 1; // 17 Enable continue on BNA - uint32_t deep_sleep_besl_reject : 1 ; // 18 Deep sleep BESL reject + uint32_t deep_sleep_besl_reject : 1; // 18 Deep sleep BESL reject uint32_t service_interval : 1; // 19 Service interval for ISO IN endpoint - uint32_t rsv20_31 : 12; // 20..31 Reserved + uint32_t rsv20_31 :12; // 20..31 Reserved } dwc2_dctl_t; TU_VERIFY_STATIC(sizeof(dwc2_dctl_t) == 4, "incorrect size"); @@ -573,11 +576,13 @@ typedef struct TU_ATTR_PACKED { uint32_t rsv7 : 1; // 7 Reserved uint32_t out_packet_err : 1; // 8 OUT packet error uint32_t bna : 1; // 9 Buffer not available - uint32_t rsv10_11 : 2; // 10..11 Reserved + uint32_t rsv10 : 1; // 10 Reserved + uint32_t iso_packet_drop : 1; // 11 Isochronous OUT packet drop status uint32_t babble_err : 1; // 12 Babble error uint32_t nak : 1; // 13 NAK uint32_t nyet : 1; // 14 NYET - uint32_t rsv15_31 : 16; // 15..31 Reserved + uint32_t setup_packet_rx : 1; // 15 Setup packet received (Buffer DMA Mode only) + uint32_t rsv16_31 :15; // 16..31 Reserved } dwc2_doepint_t; TU_VERIFY_STATIC(sizeof(dwc2_doepint_t) == 4, "incorrect size"); @@ -595,17 +600,21 @@ typedef struct { volatile uint32_t doepctl; volatile uint32_t ctl; - volatile dwc2_depctl_t ctrl_bm; + volatile dwc2_depctl_t ctl_bm; }; uint32_t rsv04; union { volatile uint32_t diepint; + volatile dwc2_diepint_t diepint_bm; + volatile uint32_t doepint; + volatile dwc2_doepint_t doepint_bm; }; uint32_t rsv0c; union { volatile uint32_t dieptsiz; volatile uint32_t doeptsiz; + volatile uint32_t tsiz; volatile dwc2_ep_tsize_t tsiz_bm; }; union { diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 550778876..8e0162ed6 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -1116,8 +1116,8 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) { TU_ASSERT(xfer->ep_id < CFG_TUH_DWC2_ENDPOINT_MAX,); dwc2_channel_char_t hcchar_bm = channel->hcchar_bm; - uint32_t hcint = channel->hcint; - channel->hcint = hcint; + const uint32_t hcint = channel->hcint; + channel->hcint = hcint; // clear interrupt bool is_done; if (is_dma) { -- cgit v1.3.1 From a2ab783db7928bbfe1f0ddf1be25660a50184ecb Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 18 Nov 2024 12:39:00 +0700 Subject: seperate handle_epin_dma/slave --- src/portable/synopsys/dwc2/dcd_dwc2.c | 147 +++++++++++++++++++-------------- src/portable/synopsys/dwc2/dwc2_type.h | 15 ++-- 2 files changed, 94 insertions(+), 68 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 6ca1433a6..706661706 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -629,12 +629,9 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t xfer->ff = ff; xfer->total_len = total_bytes; - uint16_t num_packets = (total_bytes / xfer->max_size); - uint16_t const short_packet_size = total_bytes % xfer->max_size; - - // Zero-size packet is special case. - if (short_packet_size > 0 || (total_bytes == 0)) { - num_packets++; + uint16_t num_packets = tu_div_ceil(total_bytes, xfer->max_size); + if (num_packets == 0) { + num_packets = 1; // zero length packet still count as 1 } // Schedule packets to be sent within interrupt @@ -839,6 +836,7 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi xfer->total_len -= remain; // this is ZLP, so prepare EP0 for next setup + // TODO use status phase rx if(epnum == 0 && xfer->total_len == 0) { dma_setup_prepare(rhport); } @@ -877,10 +875,10 @@ static void handle_epout_irq(uint8_t rhport) { for (uint8_t epnum = 0; epnum < ep_count; epnum++) { if (dwc2->daint & TU_BIT(DAINT_OEPINT_Pos + epnum)) { dwc2_dep_t* epout = &dwc2->epout[epnum]; - const uint32_t doepint = epout->doepint; + const uint32_t doepint = epout->intr; const dwc2_doepint_t doepint_bm = epout->doepint_bm; - epout->doepint = doepint; // Clear interrupt + epout->intr = doepint; // Clear interrupt // print_doepint(doepint); if (is_dma) { @@ -892,68 +890,91 @@ static void handle_epout_irq(uint8_t rhport) { } } +static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepint_bm) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN); + + if (diepint_bm.xfer_complete) { + if ((epnum == 0) && ep0_pending[TUSB_DIR_IN]) { + // EP0 can only handle one packet. Schedule another packet to be transmitted. + edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); + } else { + dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); + } + } + + // TX FIFO empty bit is read-only. It will only be cleared by hardware when written bytes is more than + // - 64 bytes or + // - Half/Empty of TX FIFO size (configured by GAHBCFG.TXFELVL) + if (diepint_bm.txfifo_empty && (dwc2->diepempmsk & (1 << epnum))) { + dwc2_dep_t* epin = &dwc2->epin[epnum]; + const uint16_t remain_packets = epin->tsiz_bm.packet_count; + + // Process every single packet (only whole packets can be written to fifo) + for (uint16_t i = 0; i < remain_packets; i++) { + const uint16_t remain_bytes = (uint16_t) epin->tsiz_bm.xfer_size; + const uint16_t xact_bytes = tu_min16(remain_bytes, xfer->max_size); + + // Check if dtxfsts has enough space available + if (xact_bytes > ((epin->dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) { + break; + } + + // Push packet to Tx-FIFO + if (xfer->ff) { + volatile uint32_t* tx_fifo = dwc2->fifo[epnum]; + tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*)(uintptr_t)tx_fifo, xact_bytes); + } else { + dfifo_write_packet(dwc2, epnum, xfer->buffer, xact_bytes); + xfer->buffer += xact_bytes; + } + } + + // Turn off TXFE if all bytes are written. + if (epin->tsiz_bm.xfer_size == 0) { + dwc2->diepempmsk &= ~(1 << epnum); + } + } +} + +static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepint_bm) { + // dwc2_regs_t* dwc2 = DWC2_REG(rhport); + // dwc2_dep_t* epin = &dwc2->epin[epnum]; + xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN); + + if (diepint_bm.xfer_complete) { + if ((epnum == 0) && ep0_pending[TUSB_DIR_IN]) { + // EP0 can only handle one packet. Schedule another packet to be transmitted. + edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); + } else { + if(epnum == 0) { + dma_setup_prepare(rhport); + } + dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); + } + } +} + static void handle_epin_irq(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - const uint8_t ep_count = _dwc2_controller[rhport].ep_count; + const bool is_dma = dma_device_enabled(dwc2); + const uint8_t ep_count = DWC2_EP_COUNT(dwc2); // DAINT for a given EP clears when DIEPINTx is cleared. // IEPINT will be cleared when DAINT's out bits are cleared. - for (uint8_t n = 0; n < ep_count; n++) { - if (dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + n)) { - // IN XFER complete (entire xfer). - xfer_ctl_t* xfer = XFER_CTL_BASE(n, TUSB_DIR_IN); - dwc2_dep_t* epin = &dwc2->epin[n]; - - if (epin->diepint & DIEPINT_XFRC) { - epin->diepint = DIEPINT_XFRC; - - // EP0 can only handle one packet - if ((n == 0) && ep0_pending[TUSB_DIR_IN]) { - // Schedule another packet to be transmitted. - edpt_schedule_packets(rhport, n, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); - } else { - if((n == 0) && dma_device_enabled(dwc2)) { - dma_setup_prepare(rhport); - } - dcd_event_xfer_complete(rhport, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); - } - } + for (uint8_t epnum = 0; epnum < ep_count; epnum++) { + if (dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + epnum)) { + dwc2_dep_t* epin = &dwc2->epin[epnum]; + const uint32_t diepint = epin->intr; + const dwc2_diepint_t diepint_bm = epin->diepint_bm; - // XFER FIFO empty - if ((epin->diepint & DIEPINT_TXFE) && (dwc2->diepempmsk & (1 << n))) { - // diepint's TXFE bit is read-only, software cannot clear it. - // It will only be cleared by hardware when written bytes is more than - // - 64 bytes or - // - Half/Empty of TX FIFO size (configured by GAHBCFG.TXFELVL) - const uint16_t remain_packets = epin->tsiz_bm.packet_count; - - // Process every single packet (only whole packets can be written to fifo) - for (uint16_t i = 0; i < remain_packets; i++) { - const uint16_t remain_bytes = (uint16_t) epin->tsiz_bm.xfer_size; - - // Packet can not be larger than ep max size - const uint16_t xact_bytes = tu_min16(remain_bytes, xfer->max_size); - - // It's only possible to write full packets into FIFO. Therefore DTXFSTS register of current - // EP has to be checked if the buffer can take another WHOLE packet - if (xact_bytes > ((epin->dtxfsts & DTXFSTS_INEPTFSAV_Msk) << 2)) { - break; - } + epin->intr = diepint; // Clear interrupt - // Push packet to Tx-FIFO - if (xfer->ff) { - volatile uint32_t* tx_fifo = dwc2->fifo[n]; - tu_fifo_read_n_const_addr_full_words(xfer->ff, (void*) (uintptr_t) tx_fifo, xact_bytes); - } else { - dfifo_write_packet(dwc2, n, xfer->buffer, xact_bytes); - xfer->buffer += xact_bytes; - } - } - - // Turn off TXFE if all bytes are written. - if (epin->tsiz_bm.xfer_size == 0) { - dwc2->diepempmsk &= ~(1 << n); - } + // print_doepint(doepint); + if (is_dma) { + handle_epin_dma(rhport, epnum, diepint_bm); + } else { + handle_epin_slave(rhport, epnum, diepint_bm); } } } diff --git a/src/portable/synopsys/dwc2/dwc2_type.h b/src/portable/synopsys/dwc2/dwc2_type.h index b67771a4d..812096759 100644 --- a/src/portable/synopsys/dwc2/dwc2_type.h +++ b/src/portable/synopsys/dwc2/dwc2_type.h @@ -537,12 +537,15 @@ typedef struct TU_ATTR_PACKED { uint32_t in_rx_txfe : 1; // 4 IN token received when TxFIFO is empty uint32_t in_rx_ep_mismatch : 1; // 5 IN token received with EP mismatch uint32_t in_ep_nak_effective : 1; // 6 IN endpoint NAK effective - uint32_t rsv7 : 1; // 7 Reserved - uint32_t txfifo_underrun : 1; // 8 Tx FIFO underrun + uint32_t txfifo_empty : 1; // 7 TX FIFO empty + uint32_t txfifo_underrun : 1; // 8 Tx FIFO under run uint32_t bna : 1; // 9 Buffer not available - uint32_t rsv10_12 : 3; // 10..12 Reserved + uint32_t rsv10 : 1; // 10 Reserved + uint32_t iso_packet_drop : 1; // 11 Isochronous OUT packet drop status + uint32_t babble_err : 1; // 12 Babble error uint32_t nak : 1; // 13 NAK - uint32_t rsv14_31 : 18; // 14..31 Reserved + uint32_t nyet : 1; // 14 NYET + uint32_t rsv14_31 :17; // 15..31 Reserved } dwc2_diepint_t; TU_VERIFY_STATIC(sizeof(dwc2_diepint_t) == 4, "incorrect size"); @@ -582,7 +585,7 @@ typedef struct TU_ATTR_PACKED { uint32_t nak : 1; // 13 NAK uint32_t nyet : 1; // 14 NYET uint32_t setup_packet_rx : 1; // 15 Setup packet received (Buffer DMA Mode only) - uint32_t rsv16_31 :15; // 16..31 Reserved + uint32_t rsv16_31 :16; // 16..31 Reserved } dwc2_doepint_t; TU_VERIFY_STATIC(sizeof(dwc2_doepint_t) == 4, "incorrect size"); @@ -604,6 +607,8 @@ typedef struct { }; uint32_t rsv04; union { + volatile uint32_t intr; + volatile uint32_t diepint; volatile dwc2_diepint_t diepint_bm; -- cgit v1.3.1 From dab600bea2bb5ff426e69f10aafa6332f7c8507e Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 18 Nov 2024 15:13:00 +0700 Subject: merge back and improve edpt_schedule_packets --- src/portable/synopsys/dwc2/dcd_dwc2.c | 144 ++++++++++------------------------ 1 file changed, 40 insertions(+), 104 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 706661706..2ca4dc88d 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -288,66 +288,29 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { } } -static inline void iso_set_odd_even(dwc2_regs_t* dwc2, dwc2_depctl_t* depctl_bm) { - // Take odd/even bit from frame counter. - const uint32_t odd_now = (dwc2->dsts_bm.frame_number & 1u); - if (odd_now) { - depctl_bm->set_data0_iso_even = 1; - } else { - depctl_bm->set_data1_iso_odd = 1; - } -} - -static void epout_xfer(dwc2_regs_t* dwc2, const uint8_t epnum, const uint16_t num_packets, uint16_t total_bytes) { - const uint8_t dir = TUSB_DIR_OUT; +static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir); - dwc2_dep_t* dep = &dwc2->epout[epnum]; - - // EP0 is limited to one packet each xfer - // We use multiple transaction of xfer->max_size length to get a whole transfer done - // if (epnum == 0) { - // total_bytes = tu_min16(ep0_pending[dir], xfer->max_size); - // ep0_pending[dir] -= total_bytes; - // } - - // transfer size: A full OUT transfer (multiple packets, possibly) triggers XFRC. - union { - uint32_t value; - dwc2_ep_tsize_t bm; - } deptsiz; - deptsiz.value = 0; - deptsiz.bm.xfer_size = total_bytes; - deptsiz.bm.packet_count = num_packets; + const uint8_t is_epout = dir ? 0 : 1; + dwc2_dep_t* dep = &dwc2->ep[is_epout][epnum]; - dep->tsiz = deptsiz.value; + uint16_t num_packets; + uint16_t total_bytes; - // control - union { - dwc2_depctl_t bm; - uint32_t value; - } depctl; - depctl.value = dep->ctl; - - if (depctl.bm.type == DEPCTL_EPTYPE_ISOCHRONOUS && xfer->interval == 1) { - iso_set_odd_even(dwc2, &depctl.bm); - } - - if(dma_device_enabled(dwc2)) { - dep->doepdma = (uintptr_t) xfer->buffer; + // EP0 is limited to one packet per xfer + if (epnum == 0) { + total_bytes = tu_min16(ep0_pending[dir], xfer->max_size); + ep0_pending[dir] -= total_bytes; + num_packets = 1; + } else { + total_bytes = xfer->total_len; + num_packets = tu_div_ceil(total_bytes, xfer->max_size); + if (num_packets == 0) { + num_packets = 1; // zero length packet still count as 1 + } } - depctl.bm.clear_nak = 1; - depctl.bm.enable = 1; - - dep->doepctl = depctl.value; -} - -static void epin_xfer(dwc2_regs_t* dwc2, const uint8_t epnum, const uint16_t num_packets, uint16_t total_bytes) { - const uint8_t dir = TUSB_DIR_IN; - xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir); - dwc2_dep_t* dep = &dwc2->epin[epnum]; - - // A full IN transfer (multiple packets, possibly) triggers XFRC. + // transfer size: A full OUT transfer (multiple packets, possibly) triggers XFRC. union { uint32_t value; dwc2_ep_tsize_t bm; @@ -368,38 +331,24 @@ static void epin_xfer(dwc2_regs_t* dwc2, const uint8_t epnum, const uint16_t num depctl.bm.clear_nak = 1; depctl.bm.enable = 1; if (depctl.bm.type == DEPCTL_EPTYPE_ISOCHRONOUS && xfer->interval == 1) { - iso_set_odd_even(dwc2, &depctl.bm); - } - - if(dma_device_enabled(dwc2)) { - dep->diepdma = (uintptr_t)xfer->buffer; - dep->diepctl = depctl.value; - } else { - dep->diepctl = depctl.value; - - // Enable fifo empty interrupt only if there are something to put in the fifo. - if (total_bytes != 0) { - dwc2->diepempmsk |= (1 << epnum); + const uint32_t odd_now = (dwc2->dsts_bm.frame_number & 1u); + if (odd_now) { + depctl.bm.set_data0_iso_even = 1; + } else { + depctl.bm.set_data1_iso_odd = 1; } } -} - -static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir, uint16_t const num_packets, - uint16_t total_bytes) { - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir); - // EP0 is limited to one packet each xfer - // We use multiple transaction of xfer->max_size length to get a whole transfer done - if (epnum == 0) { - total_bytes = tu_min16(ep0_pending[dir], xfer->max_size); - ep0_pending[dir] -= total_bytes; + const bool is_dma = dma_device_enabled(dwc2); + if(is_dma) { + dep->diepdma = (uintptr_t) xfer->buffer; } - if (dir == TUSB_DIR_IN) { - epin_xfer(dwc2, epnum, num_packets, total_bytes); - } else { - epout_xfer(dwc2, epnum, num_packets, total_bytes); + dep->diepctl = depctl.value; // enable endpoint + + // Slave: enable tx fifo empty interrupt only if there is data. Note must after depctl enable + if (!is_dma && dir == TUSB_DIR_IN && total_bytes != 0) { + dwc2->diepempmsk |= (1 << epnum); } } @@ -597,19 +546,11 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to // EP0 can only handle one packet if (epnum == 0) { ep0_pending[dir] = total_bytes; - - // Schedule the first transaction for EP0 transfer - edpt_schedule_packets(rhport, epnum, dir, 1, ep0_pending[dir]); - } else { - uint16_t num_packets = tu_div_ceil(total_bytes, xfer->max_size); - if (num_packets == 0) { - num_packets = 1; // zero length packet still count as 1 - } - - // Schedule packets to be sent within interrupt - edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); } + // Schedule packets to be sent within interrupt + edpt_schedule_packets(rhport, epnum, dir); + return true; } @@ -629,13 +570,8 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t xfer->ff = ff; xfer->total_len = total_bytes; - uint16_t num_packets = tu_div_ceil(total_bytes, xfer->max_size); - if (num_packets == 0) { - num_packets = 1; // zero length packet still count as 1 - } - // Schedule packets to be sent within interrupt - edpt_schedule_packets(rhport, epnum, dir, num_packets, total_bytes); + edpt_schedule_packets(rhport, epnum, dir); return true; } @@ -802,7 +738,7 @@ static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doe // EP0 can only handle one packet if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { // Schedule another packet to be received. - edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT); } else { dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); } @@ -826,7 +762,7 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) { if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { // EP0 can only handle one packet Schedule another packet to be received. - edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT, 1, ep0_pending[TUSB_DIR_OUT]); + edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT); } else { dwc2_dep_t* epout = &dwc2->epout[epnum]; xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); @@ -892,12 +828,13 @@ static void handle_epout_irq(uint8_t rhport) { static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepint_bm) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); + dwc2_dep_t* epin = &dwc2->epin[epnum]; xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN); if (diepint_bm.xfer_complete) { if ((epnum == 0) && ep0_pending[TUSB_DIR_IN]) { // EP0 can only handle one packet. Schedule another packet to be transmitted. - edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); + edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN); } else { dcd_event_xfer_complete(rhport, epnum | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true); } @@ -907,7 +844,6 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep // - 64 bytes or // - Half/Empty of TX FIFO size (configured by GAHBCFG.TXFELVL) if (diepint_bm.txfifo_empty && (dwc2->diepempmsk & (1 << epnum))) { - dwc2_dep_t* epin = &dwc2->epin[epnum]; const uint16_t remain_packets = epin->tsiz_bm.packet_count; // Process every single packet (only whole packets can be written to fifo) @@ -945,7 +881,7 @@ static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepin if (diepint_bm.xfer_complete) { if ((epnum == 0) && ep0_pending[TUSB_DIR_IN]) { // EP0 can only handle one packet. Schedule another packet to be transmitted. - edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN, 1, ep0_pending[TUSB_DIR_IN]); + edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN); } else { if(epnum == 0) { dma_setup_prepare(rhport); -- cgit v1.3.1 From d37707d6dd6147511cfaa10f21bdc4e28f2cdf69 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 18 Nov 2024 23:00:16 +0700 Subject: move handle ep slave/dma wihtin compiler macro --- hw/bsp/family_support.cmake | 5 + src/portable/synopsys/dwc2/dcd_dwc2.c | 262 ++++++++++++++++++---------------- 2 files changed, 141 insertions(+), 126 deletions(-) (limited to 'src/portable') diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index aa5e037d1..57fa63261 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -289,6 +289,11 @@ function(family_add_tinyusb TARGET OPT_MCU RTOS) ) endif () + # compile define from command line + if(DEFINED CFLAGS_CLI) + target_compile_options(${TARGET}-tinyusb PUBLIC ${CFLAGS_CLI}) + endif() + endfunction() # Add bin/hex output diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 2ca4dc88d..b1cb8c3ea 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -217,24 +217,32 @@ static void dfifo_device_init(uint8_t rhport) { //-------------------------------------------------------------------- static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint8_t const epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); + const uint8_t epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); + const uint8_t dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, dir); xfer->max_size = tu_edpt_packet_size(p_endpoint_desc); xfer->interval = p_endpoint_desc->bInterval; - // USBAEP, EPTYP, SD0PID_SEVNFRM, MPSIZ are the same for IN and OUT endpoints. - uint32_t epctl = (1 << DOEPCTL_USBAEP_Pos) | - (p_endpoint_desc->bmAttributes.xfer << DOEPCTL_EPTYP_Pos) | - (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? DOEPCTL_SD0PID_SEVNFRM : 0) | - (xfer->max_size << DOEPCTL_MPSIZ_Pos); + // Endpoint control + union { + uint32_t value; + dwc2_depctl_t bm; + } depctl; + depctl.value = 0; + + depctl.bm.mps = xfer->max_size; + depctl.bm.active = 1; + depctl.bm.type = p_endpoint_desc->bmAttributes.xfer; + if (p_endpoint_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS) { + depctl.bm.set_data0_iso_even = 1; + } if (dir == TUSB_DIR_IN) { - epctl |= (epnum << DIEPCTL_TXFNUM_Pos); + depctl.bm.tx_fifo_num = epnum; } dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum]; - dep->ctl = epctl; + dep->ctl = depctl.value; dwc2->daintmsk |= TU_BIT(epnum + DAINT_SHIFT(dir)); } @@ -288,7 +296,7 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { } } -static void edpt_schedule_packets(uint8_t rhport, uint8_t const epnum, uint8_t const dir) { +static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uint8_t dir) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir); const uint8_t is_epout = dir ? 0 : 1; @@ -571,6 +579,7 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t xfer->total_len = total_bytes; // Schedule packets to be sent within interrupt + // TODO xfer fifo may only available for slave mode edpt_schedule_packets(rhport, epnum, dir); return true; @@ -654,6 +663,48 @@ static void handle_bus_reset(uint8_t rhport) { dwc2->gintmsk |= GINTMSK_OEPINT | GINTMSK_IEPINT; } +static void handle_enum_done(uint8_t rhport) { + dwc2_regs_t *dwc2 = DWC2_REG(rhport); + tusb_speed_t speed; + switch (dwc2->dsts_bm.enum_speed) { + case DCFG_SPEED_HIGH: + speed = TUSB_SPEED_HIGH; + break; + + case DCFG_SPEED_LOW: + speed = TUSB_SPEED_LOW; + break; + + case DCFG_SPEED_FULL_30_60MHZ: + case DCFG_SPEED_FULL_48MHZ: + default: + speed = TUSB_SPEED_FULL; + break; + } + + // TODO must update GUSBCFG_TRDT according to link speed + dcd_event_bus_reset(rhport, speed, true); +} + +#if 0 +TU_ATTR_ALWAYS_INLINE static inline void print_doepint(uint32_t doepint) { + const char* str[] = { + "XFRC", "DIS", "AHBERR", "SETUP_DONE", + "ORXED", "STATUS_RX", "SETUP_B2B", "RSV7", + "OPERR", "BNA", "RSV10", "ISODROP", + "BBLERR", "NAK", "NYET", "SETUP_RX" + }; + + for(uint32_t i=0; itotal_len, XFER_RESULT_SUCCESS, true); - } - } - } -} - -static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) { - dwc2_regs_t* dwc2 = DWC2_REG(rhport); - - if (doepint_bm.setup_phase_done) { - dma_setup_prepare(rhport); - dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); - return; - } - - // OUT XFER complete - if (doepint_bm.xfer_complete) { - // only handle data skip if it is setup or status related - // Normal OUT transfer complete - if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) { if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { - // EP0 can only handle one packet Schedule another packet to be received. + // EP0 can only handle one packet, Schedule another packet to be received. edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT); } else { - dwc2_dep_t* epout = &dwc2->epout[epnum]; - xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - - // determine actual received bytes - const uint16_t remain = epout->tsiz_bm.xfer_size; - xfer->total_len -= remain; - - // this is ZLP, so prepare EP0 for next setup - // TODO use status phase rx - if(epnum == 0 && xfer->total_len == 0) { - dma_setup_prepare(rhport); - } - dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); } } } } -#if 0 -TU_ATTR_ALWAYS_INLINE static inline void print_doepint(uint32_t doepint) { - const char* str[] = { - "XFRC", "DIS", "AHBERR", "SETUP_DONE", - "ORXED", "STATUS_RX", "SETUP_B2B", "RSV7", - "OPERR", "BNA", "RSV10", "ISODROP", - "BBLERR", "NAK", "NYET", "SETUP_RX" - }; - - for(uint32_t i=0; idaint & TU_BIT(DAINT_OEPINT_Pos + epnum)) { - dwc2_dep_t* epout = &dwc2->epout[epnum]; - const uint32_t doepint = epout->intr; - const dwc2_doepint_t doepint_bm = epout->doepint_bm; - - epout->intr = doepint; // Clear interrupt - - // print_doepint(doepint); - if (is_dma) { - handle_epout_dma(rhport, epnum, doepint_bm); - } else { - handle_epout_slave(rhport, epnum, doepint_bm); - } - } - } -} - static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepint_bm) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); dwc2_dep_t* epin = &dwc2->epin[epnum]; @@ -872,6 +842,45 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep } } } +#endif + +#if CFG_TUD_DWC2_DMA_ENABLE +static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) { + dwc2_regs_t* dwc2 = DWC2_REG(rhport); + + if (doepint_bm.setup_phase_done) { + dma_setup_prepare(rhport); + dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); + return; + } + + // OUT XFER complete + if (doepint_bm.xfer_complete) { + // only handle data skip if it is setup or status related + // Normal OUT transfer complete + if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) { + if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { + // EP0 can only handle one packet Schedule another packet to be received. + edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT); + } else { + dwc2_dep_t* epout = &dwc2->epout[epnum]; + xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); + + // determine actual received bytes + const uint16_t remain = epout->tsiz_bm.xfer_size; + xfer->total_len -= remain; + + // this is ZLP, so prepare EP0 for next setup + // TODO use status phase rx + if(epnum == 0 && xfer->total_len == 0) { + dma_setup_prepare(rhport); + } + + dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); + } + } + } +} static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepint_bm) { // dwc2_regs_t* dwc2 = DWC2_REG(rhport); @@ -890,27 +899,45 @@ static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepin } } } +#endif -static void handle_epin_irq(uint8_t rhport) { +static void handle_ep_irq(uint8_t rhport, uint8_t dir) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); const bool is_dma = dma_device_enabled(dwc2); const uint8_t ep_count = DWC2_EP_COUNT(dwc2); + const uint8_t daint_offset = (dir == TUSB_DIR_IN) ? DAINT_IEPINT_Pos : DAINT_OEPINT_Pos; - // DAINT for a given EP clears when DIEPINTx is cleared. - // IEPINT will be cleared when DAINT's out bits are cleared. + // DAINT for a given EP clears when DEPINTx is cleared. + // EPINT will be cleared when DAINT bits are cleared. for (uint8_t epnum = 0; epnum < ep_count; epnum++) { - if (dwc2->daint & TU_BIT(DAINT_IEPINT_Pos + epnum)) { - dwc2_dep_t* epin = &dwc2->epin[epnum]; - const uint32_t diepint = epin->intr; - const dwc2_diepint_t diepint_bm = epin->diepint_bm; + if (dwc2->daint & TU_BIT(daint_offset + epnum)) { + dwc2_dep_t* epout = &dwc2->ep[1-dir][epnum]; + union { + uint32_t value; + dwc2_diepint_t diepint_bm; + dwc2_doepint_t doepint_bm; + } intr; + intr.value = epout->intr; - epin->intr = diepint; // Clear interrupt + epout->intr = intr.value; // Clear interrupt // print_doepint(doepint); if (is_dma) { - handle_epin_dma(rhport, epnum, diepint_bm); + #if CFG_TUD_DWC2_DMA_ENABLE + if (dir == TUSB_DIR_IN) { + handle_epin_dma(rhport, epnum, intr.diepint_bm); + } else { + handle_epout_dma(rhport, epnum, intr.doepint_bm); + } + #endif } else { - handle_epin_slave(rhport, epnum, diepint_bm); + #if CFG_TUD_DWC2_SLAVE_ENABLE + if (dir == TUSB_DIR_IN) { + handle_epin_slave(rhport, epnum, intr.diepint_bm); + } else { + handle_epout_slave(rhport, epnum, intr.doepint_bm); + } + #endif } } } @@ -931,8 +958,8 @@ static void handle_epin_irq(uint8_t rhport) { void dcd_int_handler(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); - uint32_t const int_mask = dwc2->gintmsk; - uint32_t const gintsts = dwc2->gintsts & int_mask; + const uint32_t gintmask = dwc2->gintmsk; + const uint32_t gintsts = dwc2->gintsts & gintmask; if (gintsts & GINTSTS_USBRST) { // USBRST is start of reset. @@ -943,26 +970,7 @@ void dcd_int_handler(uint8_t rhport) { if (gintsts & GINTSTS_ENUMDNE) { // ENUMDNE is the end of reset where speed of the link is detected dwc2->gintsts = GINTSTS_ENUMDNE; - - tusb_speed_t speed; - switch (dwc2->dsts_bm.enum_speed) { - case DCFG_SPEED_HIGH: - speed = TUSB_SPEED_HIGH; - break; - - case DCFG_SPEED_LOW: - speed = TUSB_SPEED_LOW; - break; - - case DCFG_SPEED_FULL_30_60MHZ: - case DCFG_SPEED_FULL_48MHZ: - default: - speed = TUSB_SPEED_FULL; - break; - } - - // TODO must update GUSBCFG_TRDT according to link speed - dcd_event_bus_reset(rhport, speed, true); + handle_enum_done(rhport); } if (gintsts & GINTSTS_USBSUSP) { @@ -1001,6 +1009,7 @@ void dcd_int_handler(uint8_t rhport) { dcd_event_sof(rhport, frame, true); } +#if CFG_TUD_DWC2_SLAVE_ENABLE // RxFIFO non-empty interrupt handling. if (gintsts & GINTSTS_RXFLVL) { // RXFLVL bit is read-only @@ -1012,17 +1021,18 @@ void dcd_int_handler(uint8_t rhport) { dwc2->gintmsk |= GINTMSK_RXFLVLM; } +#endif // OUT endpoint interrupt handling. if (gintsts & GINTSTS_OEPINT) { // OEPINT is read-only, clear using DOEPINTn - handle_epout_irq(rhport); + handle_ep_irq(rhport, TUSB_DIR_OUT); } // IN endpoint interrupt handling. if (gintsts & GINTSTS_IEPINT) { // IEPINT bit read-only, clear using DIEPINTn - handle_epin_irq(rhport); + handle_ep_irq(rhport, TUSB_DIR_IN); } // // Check for Incomplete isochronous IN transfer -- cgit v1.3.1 From 6d4a60d8ac4c0b3e6add8843216e99122b186ee4 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 18 Nov 2024 23:07:05 +0700 Subject: clean up --- src/portable/synopsys/dwc2/dcd_dwc2.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index b1cb8c3ea..c42ec4a8d 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -241,7 +241,7 @@ static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoin depctl.bm.tx_fifo_num = epnum; } - dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum]; + dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum]; dep->ctl = depctl.value; dwc2->daintmsk |= TU_BIT(epnum + DAINT_SHIFT(dir)); } @@ -252,7 +252,7 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); const uint8_t epnum = tu_edpt_number(ep_addr); const uint8_t dir = tu_edpt_dir(ep_addr); - dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum]; + dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum]; if (dir == TUSB_DIR_IN) { // Only disable currently enabled non-control endpoint @@ -299,8 +299,7 @@ static void edpt_disable(uint8_t rhport, uint8_t ep_addr, bool stall) { static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uint8_t dir) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); xfer_ctl_t* const xfer = XFER_CTL_BASE(epnum, dir); - const uint8_t is_epout = dir ? 0 : 1; - dwc2_dep_t* dep = &dwc2->ep[is_epout][epnum]; + dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum]; uint16_t num_packets; uint16_t total_bytes; @@ -601,7 +600,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); - dwc2_dep_t* dep = &dwc2->ep[1 - dir][epnum]; + dwc2_dep_t* dep = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][epnum]; // Clear stall and reset data toggle dep->ctl &= ~EPCTL_STALL;; @@ -906,12 +905,13 @@ static void handle_ep_irq(uint8_t rhport, uint8_t dir) { const bool is_dma = dma_device_enabled(dwc2); const uint8_t ep_count = DWC2_EP_COUNT(dwc2); const uint8_t daint_offset = (dir == TUSB_DIR_IN) ? DAINT_IEPINT_Pos : DAINT_OEPINT_Pos; + dwc2_dep_t* ep_base = &dwc2->ep[dir == TUSB_DIR_IN ? 0 : 1][0]; // DAINT for a given EP clears when DEPINTx is cleared. // EPINT will be cleared when DAINT bits are cleared. for (uint8_t epnum = 0; epnum < ep_count; epnum++) { if (dwc2->daint & TU_BIT(daint_offset + epnum)) { - dwc2_dep_t* epout = &dwc2->ep[1-dir][epnum]; + dwc2_dep_t* epout = &ep_base[epnum]; union { uint32_t value; dwc2_diepint_t diepint_bm; -- cgit v1.3.1 From 3fe7e612c8df25dd66802c6da2183101eed2f83c Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 18 Nov 2024 23:38:25 +0700 Subject: remove commented code --- src/portable/synopsys/dwc2/dcd_dwc2.c | 11 ----------- 1 file changed, 11 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index c42ec4a8d..2b3ef096f 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -770,8 +770,6 @@ static void handle_rxflvl_irq(uint8_t rhport) { } static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) { - // dwc2_regs_t* dwc2 = DWC2_REG(rhport); - if (doepint_bm.setup_phase_done) { dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); return; @@ -882,8 +880,6 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi } static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepint_bm) { - // dwc2_regs_t* dwc2 = DWC2_REG(rhport); - // dwc2_dep_t* epin = &dwc2->epin[epnum]; xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN); if (diepint_bm.xfer_complete) { @@ -921,7 +917,6 @@ static void handle_ep_irq(uint8_t rhport, uint8_t dir) { epout->intr = intr.value; // Clear interrupt - // print_doepint(doepint); if (is_dma) { #if CFG_TUD_DWC2_DMA_ENABLE if (dir == TUSB_DIR_IN) { @@ -1034,12 +1029,6 @@ void dcd_int_handler(uint8_t rhport) { // IEPINT bit read-only, clear using DIEPINTn handle_ep_irq(rhport, TUSB_DIR_IN); } - - // // Check for Incomplete isochronous IN transfer - // if(int_status & GINTSTS_IISOIXFR) { - // printf(" IISOIXFR!\r\n"); - //// TU_LOG(DWC2_DEBUG, " IISOIXFR!\r\n"); - // } } #if CFG_TUD_TEST_MODE -- cgit v1.3.1 From b8d31a59eec6b27b900a6d51d602a6d6f47ac4d4 Mon Sep 17 00:00:00 2001 From: Roman Leonov Date: Tue, 19 Nov 2024 11:28:04 +0100 Subject: feature(dcd_dwc2): Added cache synchronization --- src/portable/synopsys/dwc2/dcd_dwc2.c | 27 ++++++++++++++++++++++++++- src/portable/synopsys/dwc2/dwc2_esp32.h | 27 +++++++++++++++++++++++++++ 2 files changed, 53 insertions(+), 1 deletion(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 2b3ef096f..1addd28f9 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -47,7 +47,20 @@ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ +#ifdef DWC2_MEM_CACHE_LINE_SIZE +CFG_TUD_MEM_SECTION struct { + union { + uint32_t data[2]; + uint8_t buffer[DWC2_MEM_CACHE_LINE_SIZE]; + }; +} _cache_aligned_setup_packet; + +#define _setup_packet _cache_aligned_setup_packet.data +#define _sizeof_setup_packet() DWC2_MEM_CACHE_LINE_SIZE +#else static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2]; +#define _sizeof_setup_packet() sizeof(_setup_packet) +#endif // DWC2_MEM_CACHE_LINE_SIZE typedef struct { uint8_t* buffer; @@ -348,6 +361,11 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin const bool is_dma = dma_device_enabled(dwc2); if(is_dma) { + if (dir == TUSB_DIR_IN && total_bytes != 0) { + // CACHE HINT + // The xfer->buffer has new data for Host, move it to memory for DMA to transfer it + dcd_dcache_clean(xfer->buffer, total_bytes); + } dep->diepdma = (uintptr_t) xfer->buffer; } @@ -847,6 +865,11 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi if (doepint_bm.setup_phase_done) { dma_setup_prepare(rhport); + // CACHE HINT + // When cache is enabled, _setup_packet must have cache line size alignment + // and there should be no valuable data in memory after. + // Thus, specific struct is used as a buffer for setup packet data + dcd_dcache_invalidate((uint8_t*) _setup_packet, _sizeof_setup_packet()); dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); return; } @@ -872,7 +895,9 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi if(epnum == 0 && xfer->total_len == 0) { dma_setup_prepare(rhport); } - + // CACHE HINT + // Some data has been received by DMA, fetch the data from memory to cache + dcd_dcache_invalidate(xfer->buffer, xfer->total_len); dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); } } diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index 42ab4b80f..c7f1f78e9 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -39,6 +39,14 @@ #include "soc/periph_defs.h" #include "soc/usb_wrap_struct.h" +#if (CFG_TUD_DWC2_DMA_ENABLE && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE) +#include "sdkconfig.h" +#include "esp_cache.h" +#include "esp_log.h" + +#define DWC2_MEM_CACHE_LINE_SIZE CONFIG_CACHE_L1_CACHE_LINE_SIZE +#endif // SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE + #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) #define DWC2_FS_REG_BASE 0x60080000UL #define DWC2_EP_MAX 7 @@ -111,6 +119,25 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint // maybe usb_utmi_hal_disable() } +#if (CFG_TUD_DWC2_DMA_ENABLE && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE) +void dcd_dcache_clean(void const* addr, uint32_t data_size) { + int flags = ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED; + if (addr != NULL && data_size) { + esp_err_t ret = esp_cache_msync((void *) addr, data_size, flags); + assert(ret == ESP_OK); + } +} + +void dcd_dcache_invalidate(void const* addr, uint32_t data_size) { + int flags = ESP_CACHE_MSYNC_FLAG_DIR_M2C; + if (addr != NULL && data_size) { + data_size = (data_size < DWC2_MEM_CACHE_LINE_SIZE)? DWC2_MEM_CACHE_LINE_SIZE : data_size; + esp_err_t ret = esp_cache_msync((void *) addr, data_size, flags); + assert(ret == ESP_OK); + } +} +#endif // CFG_TUD_DWC2_DMA_ENABLE && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE + #ifdef __cplusplus } #endif -- cgit v1.3.1 From 43a45f29cd14bad681be3bb3928ea7e0453cc886 Mon Sep 17 00:00:00 2001 From: Roman Leonov Date: Tue, 19 Nov 2024 11:28:04 +0100 Subject: feature(dcd_dwc2): Added cache synchronization --- src/portable/synopsys/dwc2/dcd_dwc2.c | 27 +-------------------------- src/portable/synopsys/dwc2/dwc2_esp32.h | 27 --------------------------- 2 files changed, 1 insertion(+), 53 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 1addd28f9..2b3ef096f 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -47,20 +47,7 @@ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -#ifdef DWC2_MEM_CACHE_LINE_SIZE -CFG_TUD_MEM_SECTION struct { - union { - uint32_t data[2]; - uint8_t buffer[DWC2_MEM_CACHE_LINE_SIZE]; - }; -} _cache_aligned_setup_packet; - -#define _setup_packet _cache_aligned_setup_packet.data -#define _sizeof_setup_packet() DWC2_MEM_CACHE_LINE_SIZE -#else static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2]; -#define _sizeof_setup_packet() sizeof(_setup_packet) -#endif // DWC2_MEM_CACHE_LINE_SIZE typedef struct { uint8_t* buffer; @@ -361,11 +348,6 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin const bool is_dma = dma_device_enabled(dwc2); if(is_dma) { - if (dir == TUSB_DIR_IN && total_bytes != 0) { - // CACHE HINT - // The xfer->buffer has new data for Host, move it to memory for DMA to transfer it - dcd_dcache_clean(xfer->buffer, total_bytes); - } dep->diepdma = (uintptr_t) xfer->buffer; } @@ -865,11 +847,6 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi if (doepint_bm.setup_phase_done) { dma_setup_prepare(rhport); - // CACHE HINT - // When cache is enabled, _setup_packet must have cache line size alignment - // and there should be no valuable data in memory after. - // Thus, specific struct is used as a buffer for setup packet data - dcd_dcache_invalidate((uint8_t*) _setup_packet, _sizeof_setup_packet()); dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); return; } @@ -895,9 +872,7 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi if(epnum == 0 && xfer->total_len == 0) { dma_setup_prepare(rhport); } - // CACHE HINT - // Some data has been received by DMA, fetch the data from memory to cache - dcd_dcache_invalidate(xfer->buffer, xfer->total_len); + dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); } } diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index c7f1f78e9..42ab4b80f 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -39,14 +39,6 @@ #include "soc/periph_defs.h" #include "soc/usb_wrap_struct.h" -#if (CFG_TUD_DWC2_DMA_ENABLE && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE) -#include "sdkconfig.h" -#include "esp_cache.h" -#include "esp_log.h" - -#define DWC2_MEM_CACHE_LINE_SIZE CONFIG_CACHE_L1_CACHE_LINE_SIZE -#endif // SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE - #if TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3) #define DWC2_FS_REG_BASE 0x60080000UL #define DWC2_EP_MAX 7 @@ -119,25 +111,6 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint // maybe usb_utmi_hal_disable() } -#if (CFG_TUD_DWC2_DMA_ENABLE && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE) -void dcd_dcache_clean(void const* addr, uint32_t data_size) { - int flags = ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED; - if (addr != NULL && data_size) { - esp_err_t ret = esp_cache_msync((void *) addr, data_size, flags); - assert(ret == ESP_OK); - } -} - -void dcd_dcache_invalidate(void const* addr, uint32_t data_size) { - int flags = ESP_CACHE_MSYNC_FLAG_DIR_M2C; - if (addr != NULL && data_size) { - data_size = (data_size < DWC2_MEM_CACHE_LINE_SIZE)? DWC2_MEM_CACHE_LINE_SIZE : data_size; - esp_err_t ret = esp_cache_msync((void *) addr, data_size, flags); - assert(ret == ESP_OK); - } -} -#endif // CFG_TUD_DWC2_DMA_ENABLE && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE - #ifdef __cplusplus } #endif -- cgit v1.3.1 From 4da5de707b53389c8fe35f6b448f3d1bfe7c91e8 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 20 Nov 2024 18:03:42 +0700 Subject: have p4 dma somewhat working but having issue with buffer that does not occupy the whole cache line --- .../components/tinyusb_src/CMakeLists.txt | 8 ++++ src/device/dcd.h | 6 +-- src/device/usbd.c | 20 +++++++--- src/portable/synopsys/dwc2/dcd_dwc2.c | 42 ++++++++++++++++----- src/portable/synopsys/dwc2/dwc2_common.c | 2 + src/portable/synopsys/dwc2/dwc2_esp32.h | 44 ++++++++++++++++++++++ 6 files changed, 104 insertions(+), 18 deletions(-) (limited to 'src/portable') diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt index 900f620fd..9f55c8d5a 100644 --- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt +++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt @@ -15,6 +15,13 @@ list(APPEND compile_definitions BOARD_TUH_MAX_SPEED=${RHPORT_HOST_SPEED} ) +if (target STREQUAL esp32p4) + # P4 change alignment to 64 (DCache line size) for possible DMA configuration + list(APPEND compile_definitions + CFG_TUSB_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\) + ) +endif () + list(APPEND srcs # common ${tusb_src}/tusb.c @@ -68,6 +75,7 @@ endif() idf_component_register(SRCS ${srcs} INCLUDE_DIRS ${tusb_src} REQUIRES src + PRIV_REQUIRES esp_mm ) target_compile_definitions(${COMPONENT_LIB} PUBLIC ${compile_definitions}) diff --git a/src/device/dcd.h b/src/device/dcd.h index d01f82e01..0ecdec4ed 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -93,15 +93,15 @@ typedef struct TU_ATTR_ALIGNED(4) { // clean/flush data cache: write cache -> memory. // Required before an DMA TX transfer to make sure data is in memory -void dcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +void dcd_dcache_clean(const void* addr, uint32_t data_size); // invalidate data cache: mark cache as invalid, next read will read from memory // Required BOTH before and after an DMA RX transfer -void dcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +void dcd_dcache_invalidate(const void* addr, uint32_t data_size); // clean and invalidate data cache // Required before an DMA transfer where memory is both read/write by DMA -void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size); //--------------------------------------------------------------------+ // Controller API diff --git a/src/device/usbd.c b/src/device/usbd.c index a730b745b..f485b6872 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -46,9 +46,7 @@ // Weak stubs: invoked if no strong implementation is available //--------------------------------------------------------------------+ TU_ATTR_WEAK void tud_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_isr) { - (void) rhport; - (void) eventid; - (void) in_isr; + (void) rhport; (void) eventid; (void) in_isr; } TU_ATTR_WEAK void tud_sof_cb(uint32_t frame_count) { @@ -82,9 +80,7 @@ TU_ATTR_WEAK void tud_resume_cb(void) { } TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const* request) { - (void) rhport; - (void) stage; - (void) request; + (void) rhport; (void) stage; (void) request; return false; } @@ -101,6 +97,18 @@ TU_ATTR_WEAK void dcd_disconnect(uint8_t rhport) { (void) rhport; } +TU_ATTR_WEAK void dcd_dcache_clean(const void* addr, uint32_t data_size) { + (void) addr; (void) data_size; +} + +TU_ATTR_WEAK void dcd_dcache_invalidate(const void* addr, uint32_t data_size) { + (void) addr; (void) data_size; +} + +TU_ATTR_WEAK void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) { + (void) addr; (void) data_size; +} + //--------------------------------------------------------------------+ // Device Data //--------------------------------------------------------------------+ diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 2b3ef096f..a4ebacfcb 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -46,8 +46,7 @@ //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ - -static CFG_TUD_MEM_SECTION TU_ATTR_ALIGNED(4) uint32_t _setup_packet[2]; +static CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN uint32_t _setup_packet[2]; typedef struct { uint8_t* buffer; @@ -73,6 +72,25 @@ static bool _sof_en; //-------------------------------------------------------------------- // DMA //-------------------------------------------------------------------- +#if DWC2_ENABLE_MEM_CACHE +void dcd_dcache_clean(const void* addr, uint32_t data_size) { + if (addr && data_size) { + dwc2_dcache_clean(addr, data_size); + } +} + +void dcd_dcache_invalidate(const void* addr, uint32_t data_size) { + if (addr && data_size) { + dwc2_dcache_invalidate(addr, data_size); + } +} + +void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) { + if (addr && data_size) { + dwc2_dcache_clean_invalidate(addr, data_size); + } +} +#endif TU_ATTR_ALWAYS_INLINE static inline bool dma_device_enabled(const dwc2_regs_t* dwc2) { (void) dwc2; @@ -180,7 +198,7 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { // Check if free space is available TU_ASSERT(_dfifo_top >= fifo_size + dwc2->grxfsiz); _dfifo_top -= fifo_size; - TU_LOG(DWC2_DEBUG, " TX FIFO %u: allocated %u words at offset %u\r\n", epnum, fifo_size, _dfifo_top); + // TU_LOG(DWC2_DEBUG, " TX FIFO %u: allocated %u words at offset %u\r\n", epnum, fifo_size, _dfifo_top); // Both TXFD and TXSA are in unit of 32-bit words. if (epnum == 0) { @@ -348,14 +366,18 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin const bool is_dma = dma_device_enabled(dwc2); if(is_dma) { + if (dir == TUSB_DIR_IN && total_bytes != 0) { + dcd_dcache_clean(xfer->buffer, total_bytes); + } dep->diepdma = (uintptr_t) xfer->buffer; - } - - dep->diepctl = depctl.value; // enable endpoint + dep->diepctl = depctl.value; // enable endpoint + } else { + dep->diepctl = depctl.value; // enable endpoint - // Slave: enable tx fifo empty interrupt only if there is data. Note must after depctl enable - if (!is_dma && dir == TUSB_DIR_IN && total_bytes != 0) { - dwc2->diepempmsk |= (1 << epnum); + // Enable tx fifo empty interrupt only if there is data. Note must after depctl enable + if (dir == TUSB_DIR_IN && total_bytes != 0) { + dwc2->diepempmsk |= (1 << epnum); + } } } @@ -847,6 +869,7 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi if (doepint_bm.setup_phase_done) { dma_setup_prepare(rhport); + dcd_dcache_invalidate(_setup_packet, 8); dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); return; } @@ -873,6 +896,7 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi dma_setup_prepare(rhport); } + dcd_dcache_invalidate(xfer->buffer, xfer->total_len); dcd_event_xfer_complete(rhport, epnum, xfer->total_len, XFER_RESULT_SUCCESS, true); } } diff --git a/src/portable/synopsys/dwc2/dwc2_common.c b/src/portable/synopsys/dwc2/dwc2_common.c index ef155c8f7..f80ae9acb 100644 --- a/src/portable/synopsys/dwc2/dwc2_common.c +++ b/src/portable/synopsys/dwc2/dwc2_common.c @@ -229,6 +229,8 @@ bool dwc2_core_init(uint8_t rhport, bool is_highspeed, bool is_dma) { dwc2->gotgint = 0xFFFFFFFFU; dwc2->gintmsk = 0; + TU_LOG(DWC2_COMMON_DEBUG, "DMA = %u\r\n", is_dma); + if (is_dma) { // DMA seems to be only settable after a core reset, and not possible to switch on-the-fly dwc2->gahbcfg |= GAHBCFG_DMAEN | GAHBCFG_HBSTLEN_2; diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index 42ab4b80f..24ff80bce 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -111,6 +111,50 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint // maybe usb_utmi_hal_disable() } +//--------------------------------------------------------------------+ +// Data Cache +//--------------------------------------------------------------------+ +#if defined(SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE) && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE +#include "sdkconfig.h" +#include "hal/cache_hal.h" +#include "esp_cache.h" +#include "esp_log.h" + +#define DWC2_MEM_CACHE_LINE_SIZE CONFIG_CACHE_L1_CACHE_LINE_SIZE +#define DWC2_ENABLE_MEM_CACHE 1 + +TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) { + if (size & (CONFIG_CACHE_L1_CACHE_LINE_SIZE-1)) { + size = (size & ~(CONFIG_CACHE_L1_CACHE_LINE_SIZE-1)) + CONFIG_CACHE_L1_CACHE_LINE_SIZE; + } + return size; +} + +TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_clean(const void* addr, uint32_t data_size) { + // round up to cache line size + const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M; + data_size = round_up_to_cache_line_size(data_size); + //ESP_EARLY_LOGI("ESP32_DWC", "dcache clean, addr 0x%"PRIx32", size %d (%s)", (uintptr_t)addr, data_size); + assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag)); +} + +TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_invalidate(const void* addr, uint32_t data_size) { + const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_M2C; + data_size = round_up_to_cache_line_size(data_size); + //ESP_EARLY_LOGI("ESP32_DWC", "dcache invalidate, addr 0x%"PRIx32", size %d (%s)", (uintptr_t)addr, data_size); + assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag)); +} + +TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_clean_invalidate(const void* addr, uint32_t data_size) { + const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_DIR_M2C; + data_size = round_up_to_cache_line_size(data_size); + //ESP_EARLY_LOGI("ESP32_DWC", "dcache clean_invalidate, addr 0x%"PRIx32", size %d (%s)", (uintptr_t)addr, data_size); + assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag)); +} + +#endif // SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE + + #ifdef __cplusplus } #endif -- cgit v1.3.1 From b3b8bd88cb7e40063de6b54e7f7741c19550d0ab Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 20 Nov 2024 21:30:29 +0700 Subject: add CFG_TUD_MEM_DCACHE_ENABLE, CFG_TUD_MEM_DCACHE_LINE_SIZE option --- src/common/tusb_mcu.h | 12 ++++++++++++ src/portable/synopsys/dwc2/dcd_dwc2.c | 2 +- src/portable/synopsys/dwc2/dwc2_esp32.h | 17 +++++++---------- src/tusb_option.h | 14 ++++++++++++++ 4 files changed, 34 insertions(+), 11 deletions(-) (limited to 'src/portable') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 3ee04b608..dfa6c7151 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -361,6 +361,18 @@ #define TUP_USBIP_DWC2_ESP32 #define TUP_RHPORT_HIGHSPEED 1 // port0 FS, port1 HS #define TUP_DCD_ENDPOINT_MAX 16 // FS 7 ep, HS 16 ep + + #if defined(CFG_TUD_DWC2_DMA_ENABLE) && CFG_TUD_DWC2_DMA_ENABLE == 1 + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1 + #endif + + #if defined(CFG_TUH_DWC2_DMA_ENABLE) && CFG_TUH_DWC2_DMA_ENABLE == 1 + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1 + #endif + + #define CFG_TUD_MEM_DCACHE_LINE_SIZE 64 + #define CFG_TUH_MEM_DCACHE_LINE_SIZE 64 + #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0 // TODO currently have issue with buffer DMA with espressif #elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2) diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index a4ebacfcb..18b7fd024 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -72,7 +72,7 @@ static bool _sof_en; //-------------------------------------------------------------------- // DMA //-------------------------------------------------------------------- -#if DWC2_ENABLE_MEM_CACHE +#if CFG_TUD_MEM_DCACHE_ENABLE void dcd_dcache_clean(const void* addr, uint32_t data_size) { if (addr && data_size) { dwc2_dcache_clean(addr, data_size); diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index 24ff80bce..84a8360c5 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -114,14 +114,15 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint //--------------------------------------------------------------------+ // Data Cache //--------------------------------------------------------------------+ +#if CFG_TUD_DWC2_DMA_ENABLE || CFG_TUH_DWC2_DMA_ENABLE #if defined(SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE) && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE -#include "sdkconfig.h" #include "hal/cache_hal.h" #include "esp_cache.h" -#include "esp_log.h" -#define DWC2_MEM_CACHE_LINE_SIZE CONFIG_CACHE_L1_CACHE_LINE_SIZE -#define DWC2_ENABLE_MEM_CACHE 1 +#if CFG_TUD_MEM_DCACHE_LINE_SIZE != CONFIG_CACHE_L1_CACHE_LINE_SIZE || \ + CFG_TUH_MEM_DCACHE_LINE_SIZE != CONFIG_CACHE_L1_CACHE_LINE_SIZE +#error "CFG_TUD/TUH_MEM_DCACHE_LINE_SIZE must match CONFIG_CACHE_L1_CACHE_LINE_SIZE" +#endif TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) { if (size & (CONFIG_CACHE_L1_CACHE_LINE_SIZE-1)) { @@ -131,29 +132,25 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_ } TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_clean(const void* addr, uint32_t data_size) { - // round up to cache line size const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M; data_size = round_up_to_cache_line_size(data_size); - //ESP_EARLY_LOGI("ESP32_DWC", "dcache clean, addr 0x%"PRIx32", size %d (%s)", (uintptr_t)addr, data_size); assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag)); } TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_invalidate(const void* addr, uint32_t data_size) { const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_M2C; data_size = round_up_to_cache_line_size(data_size); - //ESP_EARLY_LOGI("ESP32_DWC", "dcache invalidate, addr 0x%"PRIx32", size %d (%s)", (uintptr_t)addr, data_size); assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag)); } TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_clean_invalidate(const void* addr, uint32_t data_size) { const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_DIR_M2C; data_size = round_up_to_cache_line_size(data_size); - //ESP_EARLY_LOGI("ESP32_DWC", "dcache clean_invalidate, addr 0x%"PRIx32", size %d (%s)", (uintptr_t)addr, data_size); assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag)); } -#endif // SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE - +#endif +#endif #ifdef __cplusplus } diff --git a/src/tusb_option.h b/src/tusb_option.h index 51017221d..500d74903 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -266,6 +266,7 @@ #ifndef CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT #define CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT 1 #endif + #define CFG_TUH_DWC2_SLAVE_ENABLE CFG_TUH_DWC2_SLAVE_ENABLE_DEFAULT #endif @@ -274,6 +275,7 @@ #ifndef CFG_TUH_DWC2_DMA_ENABLE_DEFAULT #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 1 #endif + #define CFG_TUH_DWC2_DMA_ENABLE CFG_TUH_DWC2_DMA_ENABLE_DEFAULT #endif @@ -422,6 +424,18 @@ #define CFG_TUD_MEM_ALIGN CFG_TUSB_MEM_ALIGN #endif +#ifndef CFG_TUD_MEM_DCACHE_ENABLE + #ifndef CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT + #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 0 + #endif + + #define CFG_TUD_MEM_DCACHE_ENABLE CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT +#endif + +#ifndef CFG_TUD_MEM_DCACHE_LINE_SIZE + #define CFG_TUD_MEM_DCACHE_LINE_SIZE 32 +#endif + #ifndef CFG_TUD_ENDPOINT0_SIZE #define CFG_TUD_ENDPOINT0_SIZE 64 #endif -- cgit v1.3.1 From c61b55b191ffcc25c1feb1a693b6d9d5d704025f Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 20 Nov 2024 22:04:55 +0700 Subject: dcd wrap data to dcd_data_t, add padding for setup_packet to match cache line size --- src/portable/synopsys/dwc2/dcd_dwc2.c | 103 +++++++++++++++++++--------------- 1 file changed, 57 insertions(+), 46 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 18b7fd024..363c77761 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -46,8 +46,6 @@ //--------------------------------------------------------------------+ // MACRO TYPEDEF CONSTANT ENUM //--------------------------------------------------------------------+ -static CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN uint32_t _setup_packet[2]; - typedef struct { uint8_t* buffer; tu_fifo_t* ff; @@ -59,15 +57,26 @@ typedef struct { static xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir]) -// EP0 transfers are limited to 1 packet - larger sizes has to be split -static uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type -static uint16_t _dfifo_top; // top free location in DFIFO in words +typedef struct { + CFG_TUD_MEM_ALIGN union { + uint32_t setup_packet[2]; +#if CFG_TUD_MEM_DCACHE_ENABLE + uint8_t setup_packet_cache_padding[CFG_TUD_MEM_DCACHE_LINE_SIZE]; +#endif + }; + + // EP0 transfers are limited to 1 packet - larger sizes has to be split + uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type + uint16_t dfifo_top; // top free location in DFIFO in words -// Number of IN endpoints active -static uint8_t _allocated_ep_in_count; + // Number of IN endpoints active + uint8_t allocated_epin_count; -// SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by -static bool _sof_en; + // SOF enabling flag - required for SOF to not get disabled in ISR when SOF was enabled by + bool sof_en; +} dcd_data_t; + +CFG_TUD_MEM_SECTION static dcd_data_t _dcd_data; //-------------------------------------------------------------------- // DMA @@ -109,7 +118,7 @@ static void dma_setup_prepare(uint8_t rhport) { // Receive only 1 packet dwc2->epout[0].doeptsiz = (1 << DOEPTSIZ_STUPCNT_Pos) | (1 << DOEPTSIZ_PKTCNT_Pos) | (8 << DOEPTSIZ_XFRSIZ_Pos); - dwc2->epout[0].doepdma = (uintptr_t)_setup_packet; + dwc2->epout[0].doepdma = (uintptr_t) _dcd_data.setup_packet; dwc2->epout[0].doepctl |= DOEPCTL_EPENA | DOEPCTL_USBAEP; } @@ -167,27 +176,27 @@ TU_ATTR_ALWAYS_INLINE static inline uint16_t calc_device_grxfsiz(uint16_t larges static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); const dwc2_controller_t* dwc2_controller = &_dwc2_controller[rhport]; - uint8_t const ep_count = dwc2_controller->ep_count; - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); + const uint8_t ep_count = dwc2_controller->ep_count; + const uint8_t epnum = tu_edpt_number(ep_addr); + const uint8_t dir = tu_edpt_dir(ep_addr); TU_ASSERT(epnum < ep_count); uint16_t fifo_size = tu_div_ceil(packet_size, 4); if (dir == TUSB_DIR_OUT) { // Calculate required size of RX FIFO - uint16_t const new_sz = calc_device_grxfsiz(4 * fifo_size, ep_count); + const uint16_t new_sz = calc_device_grxfsiz(4 * fifo_size, ep_count); // If size_rx needs to be extended check if there is enough free space if (dwc2->grxfsiz < new_sz) { - TU_ASSERT(new_sz <= _dfifo_top); + TU_ASSERT(new_sz <= _dcd_data.dfifo_top); dwc2->grxfsiz = new_sz; // Enlarge RX FIFO } } else { // Check IN endpoints concurrently active limit if(_dwc2_controller->ep_in_count) { - TU_ASSERT(_allocated_ep_in_count < _dwc2_controller->ep_in_count); - _allocated_ep_in_count++; + TU_ASSERT(_dcd_data.allocated_epin_count < _dwc2_controller->ep_in_count); + _dcd_data.allocated_epin_count++; } // If The TXFELVL is configured as half empty, the fifo must be twice the max_size. @@ -196,16 +205,16 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { } // Check if free space is available - TU_ASSERT(_dfifo_top >= fifo_size + dwc2->grxfsiz); - _dfifo_top -= fifo_size; - // TU_LOG(DWC2_DEBUG, " TX FIFO %u: allocated %u words at offset %u\r\n", epnum, fifo_size, _dfifo_top); + TU_ASSERT(_dcd_data.dfifo_top >= fifo_size + dwc2->grxfsiz); + _dcd_data.dfifo_top -= fifo_size; + // TU_LOG(DWC2_DEBUG, " TX FIFO %u: allocated %u words at offset %u\r\n", epnum, fifo_size, dfifo_top); // Both TXFD and TXSA are in unit of 32-bit words. if (epnum == 0) { - dwc2->dieptxf0 = (fifo_size << DIEPTXF0_TX0FD_Pos) | _dfifo_top; + dwc2->dieptxf0 = (fifo_size << DIEPTXF0_TX0FD_Pos) | _dcd_data.dfifo_top; } else { // DIEPTXF starts at FIFO #1. - dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | _dfifo_top; + dwc2->dieptxf[epnum - 1] = (fifo_size << DIEPTXF_INEPTXFD_Pos) | _dcd_data.dfifo_top; } } @@ -219,11 +228,11 @@ static void dfifo_device_init(uint8_t rhport) { // Scatter/Gather DMA mode is not yet supported. Buffer DMA only need 1 words per endpoint direction const bool is_dma = dma_device_enabled(dwc2); - _dfifo_top = dwc2_controller->ep_fifo_size/4; + _dcd_data.dfifo_top = dwc2_controller->ep_fifo_size/4; if (is_dma) { - _dfifo_top -= 2 * dwc2_controller->ep_count; + _dcd_data.dfifo_top -= 2 * dwc2_controller->ep_count; } - dwc2->gdfifocfg = (_dfifo_top << GDFIFOCFG_EPINFOBASE_SHIFT) | _dfifo_top; + dwc2->gdfifocfg = (_dcd_data.dfifo_top << GDFIFOCFG_EPINFOBASE_SHIFT) | _dcd_data.dfifo_top; // Allocate FIFO for EP0 IN dfifo_alloc(rhport, 0x80, CFG_TUD_ENDPOINT0_SIZE); @@ -233,7 +242,7 @@ static void dfifo_device_init(uint8_t rhport) { //-------------------------------------------------------------------- // Endpoint //-------------------------------------------------------------------- -static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) { +static void edpt_activate(uint8_t rhport, const tusb_desc_endpoint_t* p_endpoint_desc) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); const uint8_t epnum = tu_edpt_number(p_endpoint_desc->bEndpointAddress); const uint8_t dir = tu_edpt_dir(p_endpoint_desc->bEndpointAddress); @@ -324,8 +333,8 @@ static void edpt_schedule_packets(uint8_t rhport, const uint8_t epnum, const uin // EP0 is limited to one packet per xfer if (epnum == 0) { - total_bytes = tu_min16(ep0_pending[dir], xfer->max_size); - ep0_pending[dir] -= total_bytes; + total_bytes = tu_min16(_dcd_data.ep0_pending[dir], xfer->max_size); + _dcd_data.ep0_pending[dir] -= total_bytes; num_packets = 1; } else { total_bytes = xfer->total_len; @@ -388,6 +397,8 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { (void) rh_init; dwc2_regs_t* dwc2 = DWC2_REG(rhport); + tu_memclr(&_dcd_data, sizeof(_dcd_data)); + // Core Initialization const bool is_highspeed = dwc2_core_is_highspeed(dwc2, TUSB_ROLE_DEVICE); const bool is_dma = dma_device_enabled(dwc2); @@ -505,7 +516,7 @@ void dcd_sof_enable(uint8_t rhport, bool en) { (void) rhport; dwc2_regs_t* dwc2 = DWC2_REG(rhport); - _sof_en = en; + _dcd_data.sof_en = en; if (en) { dwc2->gintsts = GINTSTS_SOF; @@ -530,7 +541,7 @@ void dcd_edpt_close_all(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const ep_count = _dwc2_controller[rhport].ep_count; - _allocated_ep_in_count = 1; + _dcd_data.allocated_epin_count = 1; // Disable non-control interrupt dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); @@ -574,7 +585,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t* buffer, uint16_t to // EP0 can only handle one packet if (epnum == 0) { - ep0_pending[dir] = total_bytes; + _dcd_data.ep0_pending[dir] = total_bytes; } // Schedule packets to be sent within interrupt @@ -640,8 +651,8 @@ static void handle_bus_reset(uint8_t rhport) { tu_memclr(xfer_status, sizeof(xfer_status)); - _sof_en = false; - _allocated_ep_in_count = 1; + _dcd_data.sof_en = false; + _dcd_data.allocated_epin_count = 1; // 1. NAK for all OUT endpoints for (uint8_t n = 0; n < ep_count; n++) { @@ -745,8 +756,8 @@ static void handle_rxflvl_irq(uint8_t rhport) { case GRXSTS_PKTSTS_SETUP_RX: // Setup packet received // We can receive up to three setup packets in succession, but only the last one is valid. - _setup_packet[0] = (*rx_fifo); - _setup_packet[1] = (*rx_fifo); + _dcd_data.setup_packet[0] = (*rx_fifo); + _dcd_data.setup_packet[1] = (*rx_fifo); break; case GRXSTS_PKTSTS_SETUP_DONE: @@ -773,8 +784,8 @@ static void handle_rxflvl_irq(uint8_t rhport) { if (byte_count < xfer->max_size) { xfer->total_len -= epout->tsiz_bm.xfer_size; if (epnum == 0) { - xfer->total_len -= ep0_pending[TUSB_DIR_OUT]; - ep0_pending[TUSB_DIR_OUT] = 0; + xfer->total_len -= _dcd_data.ep0_pending[TUSB_DIR_OUT]; + _dcd_data.ep0_pending[TUSB_DIR_OUT] = 0; } } } @@ -793,7 +804,7 @@ static void handle_rxflvl_irq(uint8_t rhport) { static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) { if (doepint_bm.setup_phase_done) { - dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); + dcd_event_setup_received(rhport, (uint8_t*) _dcd_data.setup_packet, true); return; } @@ -805,7 +816,7 @@ static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doe if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) { xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT); - if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { + if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_OUT]) { // EP0 can only handle one packet, Schedule another packet to be received. edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT); } else { @@ -821,7 +832,7 @@ static void handle_epin_slave(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diep xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN); if (diepint_bm.xfer_complete) { - if ((epnum == 0) && ep0_pending[TUSB_DIR_IN]) { + if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_IN]) { // EP0 can only handle one packet. Schedule another packet to be transmitted. edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN); } else { @@ -869,8 +880,8 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi if (doepint_bm.setup_phase_done) { dma_setup_prepare(rhport); - dcd_dcache_invalidate(_setup_packet, 8); - dcd_event_setup_received(rhport, (uint8_t*) _setup_packet, true); + dcd_dcache_invalidate(_dcd_data.setup_packet, 8); + dcd_event_setup_received(rhport, (uint8_t*) _dcd_data.setup_packet, true); return; } @@ -879,7 +890,7 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi // only handle data skip if it is setup or status related // Normal OUT transfer complete if (!doepint_bm.status_phase_rx && !doepint_bm.setup_packet_rx) { - if ((epnum == 0) && ep0_pending[TUSB_DIR_OUT]) { + if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_OUT]) { // EP0 can only handle one packet Schedule another packet to be received. edpt_schedule_packets(rhport, epnum, TUSB_DIR_OUT); } else { @@ -907,7 +918,7 @@ static void handle_epin_dma(uint8_t rhport, uint8_t epnum, dwc2_diepint_t diepin xfer_ctl_t* xfer = XFER_CTL_BASE(epnum, TUSB_DIR_IN); if (diepint_bm.xfer_complete) { - if ((epnum == 0) && ep0_pending[TUSB_DIR_IN]) { + if ((epnum == 0) && _dcd_data.ep0_pending[TUSB_DIR_IN]) { // EP0 can only handle one packet. Schedule another packet to be transmitted. edpt_schedule_packets(rhport, epnum, TUSB_DIR_IN); } else { @@ -1007,7 +1018,7 @@ void dcd_int_handler(uint8_t rhport) { if (gintsts & GINTSTS_OTGINT) { // OTG INT bit is read-only - uint32_t const otg_int = dwc2->gotgint; + const uint32_t otg_int = dwc2->gotgint; if (otg_int & GOTGINT_SEDET) { dcd_event_bus_signal(rhport, DCD_EVENT_UNPLUGGED, true); @@ -1021,7 +1032,7 @@ void dcd_int_handler(uint8_t rhport) { const uint32_t frame = (dwc2->dsts & DSTS_FNSOF) >> DSTS_FNSOF_Pos; // Disable SOF interrupt if SOF was not explicitly enabled since SOF was used for remote wakeup detection - if (!_sof_en) { + if (!_dcd_data.sof_en) { dwc2->gintmsk &= ~GINTMSK_SOFM; } -- cgit v1.3.1 From fa523a5682d8dc91cc1c7a63475623743e37ac83 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 21 Nov 2024 10:15:30 +0700 Subject: make sure usb buffer occupies whole cache line when DCACHE is enabled for msc,cdc,hid HIL enable device DMA for p4 --- .../boards/espressif_p4_function_ev/board.h | 4 +- src/class/cdc/cdc_device.c | 10 +- src/class/hid/hid_device.c | 15 ++- src/class/msc/msc_device.c | 125 +++++++++------------ src/common/tusb_common.h | 3 + src/common/tusb_compiler.h | 5 +- src/device/usbd_control.c | 29 ++--- src/portable/synopsys/dwc2/dcd_dwc2.c | 8 +- src/tusb_option.h | 6 +- test/hil/tinyusb.json | 3 + 10 files changed, 105 insertions(+), 103 deletions(-) (limited to 'src/portable') diff --git a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h index 0022f0d2d..c4f73c72e 100644 --- a/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h +++ b/hw/bsp/espressif/boards/espressif_p4_function_ev/board.h @@ -8,7 +8,7 @@ * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: + * furnished to do so, subject to the following conditions:aaaaa * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. @@ -33,7 +33,7 @@ // #define NEOPIXEL_PIN 48 -#define BUTTON_PIN 0 +#define BUTTON_PIN 35 #define BUTTON_STATE_ACTIVE 0 // For CI hardware test, to test both device and host on the same HS port with help of diff --git a/src/class/cdc/cdc_device.c b/src/class/cdc/cdc_device.c index ebc408f5a..3e856383e 100644 --- a/src/class/cdc/cdc_device.c +++ b/src/class/cdc/cdc_device.c @@ -69,8 +69,14 @@ typedef struct { OSAL_MUTEX_DEF(tx_ff_mutex); // Endpoint Transfer buffer - CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE]; - CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE]; + union { + CFG_TUD_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; + union { + CFG_TUD_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; } cdcd_interface_t; #define ITF_MEM_RESET_SIZE offsetof(cdcd_interface_t, wanted_char) diff --git a/src/class/hid/hid_device.c b/src/class/hid/hid_device.c index ef6c7f3af..257af86e0 100644 --- a/src/class/hid/hid_device.c +++ b/src/class/hid/hid_device.c @@ -53,9 +53,18 @@ typedef struct { // Note: HID descriptor may be not available from application after enumeration tusb_hid_descriptor_hid_t const *hid_descriptor; - uint8_t ctrl_buf[CFG_TUD_HID_EP_BUFSIZE]; - CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_HID_EP_BUFSIZE]; - CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_HID_EP_BUFSIZE]; + union { + CFG_TUD_MEM_ALIGN uint8_t ctrl_buf[CFG_TUD_HID_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; + union { + CFG_TUD_MEM_ALIGN uint8_t epin_buf[CFG_TUD_HID_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; + union { + CFG_TUD_MEM_ALIGN uint8_t epout_buf[CFG_TUD_HID_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; } hidd_interface_t; CFG_TUD_MEM_SECTION tu_static hidd_interface_t _hidd_itf[CFG_TUD_HID]; diff --git a/src/class/msc/msc_device.c b/src/class/msc/msc_device.c index 447560b4d..af035bcf3 100644 --- a/src/class/msc/msc_device.c +++ b/src/class/msc/msc_device.c @@ -44,8 +44,7 @@ //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ -enum -{ +enum { MSC_STAGE_CMD = 0, MSC_STAGE_DATA, MSC_STAGE_STATUS, @@ -53,11 +52,19 @@ enum MSC_STAGE_NEED_RESET, }; -typedef struct -{ - // TODO optimize alignment - CFG_TUSB_MEM_ALIGN msc_cbw_t cbw; - CFG_TUSB_MEM_ALIGN msc_csw_t csw; +typedef struct { + union { + CFG_TUD_MEM_ALIGN msc_cbw_t cbw; + TUD_DCACHE_PADDING; + }; + union { + CFG_TUD_MEM_ALIGN msc_csw_t csw; + TUD_DCACHE_PADDING; + }; + union { + CFG_TUD_MEM_ALIGN uint8_t ep_buf[CFG_TUD_MSC_EP_BUFSIZE]; + TUD_DCACHE_PADDING; + }; uint8_t itf_num; uint8_t ep_in; @@ -74,8 +81,7 @@ typedef struct uint8_t add_sense_qualifier; }mscd_interface_t; -CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static mscd_interface_t _mscd_itf; -CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN tu_static uint8_t _mscd_buf[CFG_TUD_MSC_EP_BUFSIZE]; +CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN static mscd_interface_t _mscd_itf; //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION @@ -86,13 +92,11 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc); static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc); static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint32_t xferred_bytes); -TU_ATTR_ALWAYS_INLINE static inline bool is_data_in(uint8_t dir) -{ +TU_ATTR_ALWAYS_INLINE static inline bool is_data_in(uint8_t dir) { return tu_bit_test(dir, 7); } -static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc) -{ +static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc) { // Data residue is always = host expect - actual transferred p_msc->csw.data_residue = p_msc->cbw.total_bytes - p_msc->xferred_len; @@ -100,14 +104,12 @@ static inline bool send_csw(uint8_t rhport, mscd_interface_t* p_msc) return usbd_edpt_xfer(rhport, p_msc->ep_in , (uint8_t*) &p_msc->csw, sizeof(msc_csw_t)); } -static inline bool prepare_cbw(uint8_t rhport, mscd_interface_t* p_msc) -{ +static inline bool prepare_cbw(uint8_t rhport, mscd_interface_t* p_msc) { p_msc->stage = MSC_STAGE_CMD; return usbd_edpt_xfer(rhport, p_msc->ep_out, (uint8_t*) &p_msc->cbw, sizeof(msc_cbw_t)); } -static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status) -{ +static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status) { msc_cbw_t const * p_cbw = &p_msc->cbw; msc_csw_t * p_csw = &p_msc->csw; @@ -116,24 +118,21 @@ static void fail_scsi_op(uint8_t rhport, mscd_interface_t* p_msc, uint8_t status p_msc->stage = MSC_STAGE_STATUS; // failed but sense key is not set: default to Illegal Request - if ( p_msc->sense_key == 0 ) tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); + if (p_msc->sense_key == 0) { + tud_msc_set_sense(p_cbw->lun, SCSI_SENSE_ILLEGAL_REQUEST, 0x20, 0x00); + } // If there is data stage and not yet complete, stall it - if ( p_cbw->total_bytes && p_csw->data_residue ) - { - if ( is_data_in(p_cbw->dir) ) - { + if (p_cbw->total_bytes && p_csw->data_residue) { + if (is_data_in(p_cbw->dir)) { usbd_edpt_stall(rhport, p_msc->ep_in); - } - else - { + } else { usbd_edpt_stall(rhport, p_msc->ep_out); } } } -static inline uint32_t rdwr10_get_lba(uint8_t const command[]) -{ +static inline uint32_t rdwr10_get_lba(uint8_t const command[]) { // use offsetof to avoid pointer to the odd/unaligned address uint32_t const lba = tu_unaligned_read32(command + offsetof(scsi_write10_t, lba)); @@ -141,14 +140,12 @@ static inline uint32_t rdwr10_get_lba(uint8_t const command[]) return tu_ntohl(lba); } -static inline uint16_t rdwr10_get_blockcount(msc_cbw_t const* cbw) -{ +static inline uint16_t rdwr10_get_blockcount(msc_cbw_t const* cbw) { uint16_t const block_count = tu_unaligned_read16(cbw->command + offsetof(scsi_write10_t, block_count)); return tu_ntohs(block_count); } -static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) -{ +static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) { // first extract block count in the command uint16_t const block_count = rdwr10_get_blockcount(cbw); @@ -158,40 +155,28 @@ static inline uint16_t rdwr10_get_blocksize(msc_cbw_t const* cbw) return (uint16_t) (cbw->total_bytes / block_count); } -uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) -{ +uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) { uint8_t status = MSC_CSW_STATUS_PASSED; uint16_t const block_count = rdwr10_get_blockcount(cbw); - if ( cbw->total_bytes == 0 ) - { - if ( block_count ) - { + if (cbw->total_bytes == 0) { + if (block_count) { TU_LOG_DRV(" SCSI case 2 (Hn < Di) or case 3 (Hn < Do) \r\n"); status = MSC_CSW_STATUS_PHASE_ERROR; - }else - { + } else { // no data transfer, only exist in complaint test suite } - }else - { - if ( SCSI_CMD_READ_10 == cbw->command[0] && !is_data_in(cbw->dir) ) - { + } else { + if (SCSI_CMD_READ_10 == cbw->command[0] && !is_data_in(cbw->dir)) { TU_LOG_DRV(" SCSI case 10 (Ho <> Di)\r\n"); status = MSC_CSW_STATUS_PHASE_ERROR; - } - else if ( SCSI_CMD_WRITE_10 == cbw->command[0] && is_data_in(cbw->dir) ) - { + } else if (SCSI_CMD_WRITE_10 == cbw->command[0] && is_data_in(cbw->dir)) { TU_LOG_DRV(" SCSI case 8 (Hi <> Do)\r\n"); status = MSC_CSW_STATUS_PHASE_ERROR; - } - else if ( 0 == block_count ) - { + } else if (0 == block_count) { TU_LOG_DRV(" SCSI case 4 Hi > Dn (READ10) or case 9 Ho > Dn (WRITE10) \r\n"); - status = MSC_CSW_STATUS_FAILED; - } - else if ( cbw->total_bytes / block_count == 0 ) - { + status = MSC_CSW_STATUS_FAILED; + } else if (cbw->total_bytes / block_count == 0) { TU_LOG_DRV(" Computed block size = 0. SCSI case 7 Hi < Di (READ10) or case 13 Ho < Do (WRIT10)\r\n"); status = MSC_CSW_STATUS_PHASE_ERROR; } @@ -205,8 +190,7 @@ uint8_t rdwr10_validate_cmd(msc_cbw_t const* cbw) //--------------------------------------------------------------------+ #if CFG_TUSB_DEBUG >= CFG_TUD_MSC_LOG_LEVEL -TU_ATTR_UNUSED tu_static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = -{ +TU_ATTR_UNUSED tu_static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = { { .key = SCSI_CMD_TEST_UNIT_READY , .data = "Test Unit Ready" }, { .key = SCSI_CMD_INQUIRY , .data = "Inquiry" }, { .key = SCSI_CMD_MODE_SELECT_6 , .data = "Mode_Select 6" }, @@ -220,8 +204,7 @@ TU_ATTR_UNUSED tu_static tu_lookup_entry_t const _msc_scsi_cmd_lookup[] = { .key = SCSI_CMD_WRITE_10 , .data = "Write10" } }; -TU_ATTR_UNUSED tu_static tu_lookup_table_t const _msc_scsi_cmd_table = -{ +TU_ATTR_UNUSED tu_static tu_lookup_table_t const _msc_scsi_cmd_table = { .count = TU_ARRAY_SIZE(_msc_scsi_cmd_lookup), .items = _msc_scsi_cmd_lookup }; @@ -462,7 +445,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // 2. IN & Zero: Process if is built-in, else Invoke app callback. Skip DATA if zero length if ( (p_cbw->total_bytes > 0 ) && !is_data_in(p_cbw->dir) ) { - if (p_cbw->total_bytes > sizeof(_mscd_buf)) + if (p_cbw->total_bytes > CFG_TUD_MSC_EP_BUFSIZE) { TU_LOG_DRV(" SCSI reject non READ10/WRITE10 with large data\r\n"); fail_scsi_op(rhport, p_msc, MSC_CSW_STATUS_FAILED); @@ -470,17 +453,17 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t { // Didn't check for case 9 (Ho > Dn), which requires examining scsi command first // but it is OK to just receive data then responded with failed status - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, (uint16_t) p_msc->total_len) ); + TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, p_msc->ep_buf, (uint16_t) p_msc->total_len) ); } }else { // First process if it is a built-in commands - int32_t resplen = proc_builtin_scsi(p_cbw->lun, p_cbw->command, _mscd_buf, sizeof(_mscd_buf)); + int32_t resplen = proc_builtin_scsi(p_cbw->lun, p_cbw->command, p_msc->ep_buf, CFG_TUD_MSC_EP_BUFSIZE); // Invoke user callback if not built-in if ( (resplen < 0) && (p_msc->sense_key == 0) ) { - resplen = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, (uint16_t) p_msc->total_len); + resplen = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, p_msc->ep_buf, (uint16_t) p_msc->total_len); } if ( resplen < 0 ) @@ -513,7 +496,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t { // cannot return more than host expect p_msc->total_len = tu_min32((uint32_t) resplen, p_cbw->total_bytes); - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_buf, (uint16_t) p_msc->total_len) ); + TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, p_msc->ep_buf, (uint16_t) p_msc->total_len) ); } } } @@ -522,7 +505,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t case MSC_STAGE_DATA: TU_LOG_DRV(" SCSI Data [Lun%u]\r\n", p_cbw->lun); - //TU_LOG_MEM(MSC_DEBUG, _mscd_buf, xferred_bytes, 2); + //TU_LOG_MEM(MSC_DEBUG, p_msc->ep_buf, xferred_bytes, 2); if (SCSI_CMD_READ_10 == p_cbw->command[0]) { @@ -548,7 +531,7 @@ bool mscd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t // OUT transfer, invoke callback if needed if ( !is_data_in(p_cbw->dir) ) { - int32_t cb_result = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, _mscd_buf, (uint16_t) p_msc->total_len); + int32_t cb_result = tud_msc_scsi_cb(p_cbw->lun, p_cbw->command, p_msc->ep_buf, (uint16_t) p_msc->total_len); if ( cb_result < 0 ) { @@ -861,11 +844,11 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) uint32_t const lba = rdwr10_get_lba(p_cbw->command) + (p_msc->xferred_len / block_sz); // remaining bytes capped at class buffer - int32_t nbytes = (int32_t) tu_min32(sizeof(_mscd_buf), p_cbw->total_bytes-p_msc->xferred_len); + int32_t nbytes = (int32_t) tu_min32(CFG_TUD_MSC_EP_BUFSIZE, p_cbw->total_bytes-p_msc->xferred_len); // Application can consume smaller bytes uint32_t const offset = p_msc->xferred_len % block_sz; - nbytes = tud_msc_read10_cb(p_cbw->lun, lba, offset, _mscd_buf, (uint32_t) nbytes); + nbytes = tud_msc_read10_cb(p_cbw->lun, lba, offset, p_msc->ep_buf, (uint32_t) nbytes); if ( nbytes < 0 ) { @@ -884,7 +867,7 @@ static void proc_read10_cmd(uint8_t rhport, mscd_interface_t* p_msc) } else { - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, _mscd_buf, (uint16_t) nbytes), ); + TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_in, p_msc->ep_buf, (uint16_t) nbytes), ); } } @@ -908,10 +891,10 @@ static void proc_write10_cmd(uint8_t rhport, mscd_interface_t* p_msc) } // remaining bytes capped at class buffer - uint16_t nbytes = (uint16_t) tu_min32(sizeof(_mscd_buf), p_cbw->total_bytes-p_msc->xferred_len); + uint16_t nbytes = (uint16_t) tu_min32(CFG_TUD_MSC_EP_BUFSIZE, p_cbw->total_bytes-p_msc->xferred_len); // Write10 callback will be called later when usb transfer complete - TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, _mscd_buf, nbytes), ); + TU_ASSERT( usbd_edpt_xfer(rhport, p_msc->ep_out, p_msc->ep_buf, nbytes), ); } // process new data arrived from WRITE10 @@ -927,7 +910,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 // Invoke callback to consume new data uint32_t const offset = p_msc->xferred_len % block_sz; - int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, offset, _mscd_buf, xferred_bytes); + int32_t nbytes = tud_msc_write10_cb(p_cbw->lun, lba, offset, p_msc->ep_buf, xferred_bytes); if ( nbytes < 0 ) { @@ -950,7 +933,7 @@ static void proc_write10_new_data(uint8_t rhport, mscd_interface_t* p_msc, uint3 if ( nbytes > 0 ) { p_msc->xferred_len += (uint16_t) nbytes; - memmove(_mscd_buf, _mscd_buf+nbytes, left_over); + memmove(p_msc->ep_buf, p_msc->ep_buf+nbytes, left_over); } // simulate an transfer complete with adjusted parameters --> callback will be invoked with adjusted parameter diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 59cc0fb48..416bad296 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -58,6 +58,9 @@ // Generate a mask with bit from high (31) to low (0) set, e.g TU_GENMASK(3, 0) = 0b1111 #define TU_GENMASK(h, l) ( (UINT32_MAX << (l)) & (UINT32_MAX >> (31 - (h))) ) +// DCache padding for variable to occupy full cache line +#define TUD_DCACHE_PADDING uint8_t TU_XSTRCAT(dcache_padding_, _TU_COUNTER_)[CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1] + //--------------------------------------------------------------------+ // Includes //--------------------------------------------------------------------+ diff --git a/src/common/tusb_compiler.h b/src/common/tusb_compiler.h index 646c22b29..9b33a6f61 100644 --- a/src/common/tusb_compiler.h +++ b/src/common/tusb_compiler.h @@ -136,7 +136,7 @@ #define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name))) #define TU_ATTR_PACKED __attribute__ ((packed)) #define TU_ATTR_WEAK __attribute__ ((weak)) - // #define TU_ATTR_WEAK_ALIAS(f) __attribute__ ((weak, alias(#f)) + // #define TU_ATTR_WEAK_ALIAS(f) __attribute__ ((weak, alias(#f))) #ifndef TU_ATTR_ALWAYS_INLINE // allow to override for debug #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline)) #endif @@ -189,6 +189,7 @@ #define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name))) #define TU_ATTR_PACKED __attribute__ ((packed)) #define TU_ATTR_WEAK __attribute__ ((weak)) + // #define TU_ATTR_WEAK_ALIAS(f) __attribute__ ((weak, alias(#f))) #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline)) #define TU_ATTR_DEPRECATED(mess) __attribute__ ((deprecated(mess))) // warn if function with this attribute is used #define TU_ATTR_UNUSED __attribute__ ((unused)) // Function/Variable is meant to be possibly unused @@ -216,6 +217,7 @@ #define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name))) #define TU_ATTR_PACKED __attribute__ ((packed)) #define TU_ATTR_WEAK __attribute__ ((weak)) + // #define TU_ATTR_WEAK_ALIAS(f) __attribute__ ((weak, alias(#f))) #ifndef TU_ATTR_ALWAYS_INLINE // allow to override for debug #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline)) #endif @@ -244,6 +246,7 @@ #define TU_ATTR_SECTION(sec_name) #define TU_ATTR_PACKED #define TU_ATTR_WEAK + // #define TU_ATTR_WEAK_ALIAS(f) #define TU_ATTR_ALWAYS_INLINE #define TU_ATTR_DEPRECATED(mess) #define TU_ATTR_UNUSED diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index b1fd357aa..59c66eb1e 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -54,6 +54,10 @@ enum { }; typedef struct { + union { + CFG_TUD_MEM_ALIGN uint8_t ep_buf[CFG_TUD_ENDPOINT0_SIZE]; + TUD_DCACHE_PADDING; + }; tusb_control_request_t request; uint8_t* buffer; uint16_t data_len; @@ -61,17 +65,14 @@ typedef struct { usbd_control_xfer_cb_t complete_cb; } usbd_control_xfer_t; -tu_static usbd_control_xfer_t _ctrl_xfer; - -CFG_TUD_MEM_SECTION CFG_TUSB_MEM_ALIGN -tu_static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE]; +CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN static usbd_control_xfer_t _ctrl_xfer; //--------------------------------------------------------------------+ // Application API //--------------------------------------------------------------------+ // Queue ZLP status transaction -static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t const* request) { +static inline bool status_stage_xact(uint8_t rhport, tusb_control_request_t const* request) { // Opposite to endpoint in Data Phase uint8_t const ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN; return usbd_edpt_xfer(rhport, ep_addr, NULL, 0); @@ -84,13 +85,13 @@ bool tud_control_status(uint8_t rhport, tusb_control_request_t const* request) { _ctrl_xfer.total_xferred = 0; _ctrl_xfer.data_len = 0; - return _status_stage_xact(rhport, request); + return status_stage_xact(rhport, request); } // Queue a transaction in Data Stage // Each transaction has up to Endpoint0's max packet size. // This function can also transfer an zero-length packet -static bool _data_stage_xact(uint8_t rhport) { +static bool data_stage_xact(uint8_t rhport) { uint16_t const xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred, CFG_TUD_ENDPOINT0_SIZE); @@ -99,11 +100,11 @@ static bool _data_stage_xact(uint8_t rhport) { if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN) { ep_addr = EDPT_CTRL_IN; if (xact_len) { - TU_VERIFY(0 == tu_memcpy_s(_usbd_ctrl_buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len)); + TU_VERIFY(0 == tu_memcpy_s(_ctrl_xfer.ep_buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len)); } } - return usbd_edpt_xfer(rhport, ep_addr, xact_len ? _usbd_ctrl_buf : NULL, xact_len); + return usbd_edpt_xfer(rhport, ep_addr, xact_len ? _ctrl_xfer.ep_buf : NULL, xact_len); } // Transmit data to/from the control endpoint. @@ -122,10 +123,10 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const* request, voi // TU_LOG2(" Control total data length is %u bytes\r\n", _ctrl_xfer.data_len); // Data stage - TU_ASSERT(_data_stage_xact(rhport)); + TU_ASSERT(data_stage_xact(rhport)); } else { // Status stage - TU_ASSERT(_status_stage_xact(rhport, request)); + TU_ASSERT(status_stage_xact(rhport, request)); } return true; @@ -179,7 +180,7 @@ bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT) { TU_VERIFY(_ctrl_xfer.buffer); - memcpy(_ctrl_xfer.buffer, _usbd_ctrl_buf, xferred_bytes); + memcpy(_ctrl_xfer.buffer, _ctrl_xfer.ep_buf, xferred_bytes); TU_LOG_MEM(CFG_TUD_LOG_LEVEL, _usbd_ctrl_buf, xferred_bytes, 2); } @@ -205,7 +206,7 @@ bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, if (is_ok) { // Send status - TU_ASSERT(_status_stage_xact(rhport, &_ctrl_xfer.request)); + TU_ASSERT(status_stage_xact(rhport, &_ctrl_xfer.request)); } else { // Stall both IN and OUT control endpoint dcd_edpt_stall(rhport, EDPT_CTRL_OUT); @@ -213,7 +214,7 @@ bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, } } else { // More data to transfer - TU_ASSERT(_data_stage_xact(rhport)); + TU_ASSERT(data_stage_xact(rhport)); } return true; diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 363c77761..f2eb80e12 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -58,11 +58,9 @@ static xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir]) typedef struct { - CFG_TUD_MEM_ALIGN union { - uint32_t setup_packet[2]; -#if CFG_TUD_MEM_DCACHE_ENABLE - uint8_t setup_packet_cache_padding[CFG_TUD_MEM_DCACHE_LINE_SIZE]; -#endif + union { + CFG_TUD_MEM_ALIGN uint32_t setup_packet[2]; + TUD_DCACHE_PADDING; }; // EP0 transfers are limited to 1 packet - larger sizes has to be split diff --git a/src/tusb_option.h b/src/tusb_option.h index 500d74903..1c8e8aff4 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -252,11 +252,7 @@ #define CFG_TUD_DWC2_SLAVE_ENABLE 1 #endif -// DWC2 controller: use DMA for data transfer -// For processors with data cache enabled, USB endpoint buffer region -// (defined by CFG_TUSB_MEM_SECTION) must be declared as non-cacheable. -// For example, on Cortex-M7 the MPU region can be configured as normal -// non-cacheable, with RASR register value: TEX=1 C=0 B=0 S=0. +// Enable DWC2 DMA for device #ifndef CFG_TUD_DWC2_DMA_ENABLE #define CFG_TUD_DWC2_DMA_ENABLE 0 #endif diff --git a/test/hil/tinyusb.json b/test/hil/tinyusb.json index b6c9b540a..8b4ef6d3a 100644 --- a/test/hil/tinyusb.json +++ b/test/hil/tinyusb.json @@ -3,6 +3,9 @@ { "name": "espressif_p4_function_ev", "uid": "6055F9F98715", + "build" : { + "flags_on": ["", "CFG_TUD_DWC2_DMA_ENABLE"] + }, "tests": { "only": ["device/cdc_msc_freertos", "device/hid_composite_freertos", "host/device_info"], "dev_attached": [{"vid_pid": "1a86_55d4", "serial": "52D2002427"}] -- cgit v1.3.1 From 85e54b0fc3b53e3a690698bc5cf85581e6eaa69d Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 21 Nov 2024 19:18:52 +0700 Subject: use TUD_EPBUF_DEF to declare buffer memory for midi --- src/class/midi/midi_device.c | 151 ++++++++++++++++------------------ src/common/tusb_common.h | 5 +- src/common/tusb_types.h | 10 +++ src/device/usbd_control.c | 40 ++++----- src/portable/synopsys/dwc2/dcd_dwc2.c | 31 ++++--- 5 files changed, 115 insertions(+), 122 deletions(-) (limited to 'src/portable') diff --git a/src/class/midi/midi_device.c b/src/class/midi/midi_device.c index 7e30e5ea4..5be4cb993 100644 --- a/src/class/midi/midi_device.c +++ b/src/class/midi/midi_device.c @@ -68,40 +68,36 @@ typedef struct { osal_mutex_def_t rx_ff_mutex; osal_mutex_def_t tx_ff_mutex; #endif - - // Endpoint Transfer buffer - union { - CFG_TUD_MEM_ALIGN uint8_t epout_buf[CFG_TUD_MIDI_EP_BUFSIZE]; - TUD_DCACHE_PADDING; - }; - union { - CFG_TUD_MEM_ALIGN uint8_t epin_buf[CFG_TUD_MIDI_EP_BUFSIZE]; - TUD_DCACHE_PADDING; - }; } midid_interface_t; #define ITF_MEM_RESET_SIZE offsetof(midid_interface_t, rx_ff) +// Endpoint Transfer buffer +CFG_TUD_MEM_SECTION static struct { + TUD_EPBUF_DEF(epin, CFG_TUD_MIDI_EP_BUFSIZE); + TUD_EPBUF_DEF(epout, CFG_TUD_MIDI_EP_BUFSIZE); +} _midid_epbuf[CFG_TUD_MIDI]; + //--------------------------------------------------------------------+ // INTERNAL OBJECT & FUNCTION DECLARATION //--------------------------------------------------------------------+ -CFG_TUD_MEM_SECTION midid_interface_t _midid_itf[CFG_TUD_MIDI]; +static midid_interface_t _midid_itf[CFG_TUD_MIDI]; bool tud_midi_n_mounted (uint8_t itf) { midid_interface_t* midi = &_midid_itf[itf]; return midi->ep_in && midi->ep_out; } -static void _prep_out_transaction (midid_interface_t* p_midi) -{ - uint8_t const rhport = 0; +static void _prep_out_transaction(uint8_t idx) { + const uint8_t rhport = 0; + midid_interface_t* p_midi = &_midid_itf[idx]; uint16_t available = tu_fifo_remaining(&p_midi->rx_ff); // Prepare for incoming data but only allow what we can store in the ring buffer. // TODO Actually we can still carry out the transfer, keeping count of received bytes // and slowly move it to the FIFO when read(). // This pre-check reduces endpoint claiming - TU_VERIFY(available >= sizeof(p_midi->epout_buf), ); + TU_VERIFY(available >= sizeof(_midid_epbuf[idx].epout), ); // claim endpoint TU_VERIFY(usbd_edpt_claim(rhport, p_midi->ep_out), ); @@ -109,8 +105,8 @@ static void _prep_out_transaction (midid_interface_t* p_midi) // fifo can be changed before endpoint is claimed available = tu_fifo_remaining(&p_midi->rx_ff); - if ( available >= sizeof(p_midi->epout_buf) ) { - usbd_edpt_xfer(rhport, p_midi->ep_out, p_midi->epout_buf, sizeof(p_midi->epout_buf)); + if ( available >= CFG_TUD_MIDI_EP_BUFSIZE ) { + usbd_edpt_xfer(rhport, p_midi->ep_out, _midid_epbuf[idx].epout, CFG_TUD_MIDI_EP_BUFSIZE); }else { // Release endpoint since we don't make any transfer @@ -126,7 +122,7 @@ uint32_t tud_midi_n_available(uint8_t itf, uint8_t cable_num) (void) cable_num; midid_interface_t* midi = &_midid_itf[itf]; - midid_stream_t const* stream = &midi->stream_read; + const midid_stream_t* stream = &midi->stream_read; // when using with packet API stream total & index are both zero return tu_fifo_count(&midi->rx_ff) + (uint8_t) (stream->total - stream->index); @@ -207,8 +203,8 @@ bool tud_midi_n_packet_read (uint8_t itf, uint8_t packet[4]) midid_interface_t* midi = &_midid_itf[itf]; TU_VERIFY(midi->ep_out); - uint32_t const num_read = tu_fifo_read_n(&midi->rx_ff, packet, 4); - _prep_out_transaction(midi); + const uint32_t num_read = tu_fifo_read_n(&midi->rx_ff, packet, 4); + _prep_out_transaction(itf); return (num_read == 4); } @@ -216,31 +212,31 @@ bool tud_midi_n_packet_read (uint8_t itf, uint8_t packet[4]) // WRITE API //--------------------------------------------------------------------+ -static uint32_t write_flush(midid_interface_t* midi) -{ - // No data to send - if ( !tu_fifo_count(&midi->tx_ff) ) return 0; +static uint32_t write_flush(uint8_t idx) { + midid_interface_t* midi = &_midid_itf[idx]; - uint8_t const rhport = 0; + if (!tu_fifo_count(&midi->tx_ff)) { + return 0; // No data to send + } + + const uint8_t rhport = 0; // skip if previous transfer not complete TU_VERIFY( usbd_edpt_claim(rhport, midi->ep_in), 0 ); - uint16_t count = tu_fifo_read_n(&midi->tx_ff, midi->epin_buf, CFG_TUD_MIDI_EP_BUFSIZE); + uint16_t count = tu_fifo_read_n(&midi->tx_ff, _midid_epbuf[idx].epin, CFG_TUD_MIDI_EP_BUFSIZE); - if (count) - { - TU_ASSERT( usbd_edpt_xfer(rhport, midi->ep_in, midi->epin_buf, count), 0 ); + if (count) { + TU_ASSERT( usbd_edpt_xfer(rhport, midi->ep_in, _midid_epbuf[idx].epin, count), 0 ); return count; - }else - { + }else { // Release endpoint since we don't make any transfer usbd_edpt_release(rhport, midi->ep_in); return 0; } } -uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const* buffer, uint32_t bufsize) +uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, const uint8_t* buffer, uint32_t bufsize) { midid_interface_t* midi = &_midid_itf[itf]; TU_VERIFY(midi->ep_in, 0); @@ -250,14 +246,13 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const* uint32_t i = 0; while ( (i < bufsize) && (tu_fifo_remaining(&midi->tx_ff) >= 4) ) { - uint8_t const data = buffer[i]; + const uint8_t data = buffer[i]; i++; if ( stream->index == 0 ) { //------------- New event packet -------------// - - uint8_t const msg = data >> 4; + const uint8_t msg = data >> 4; stream->index = 2; stream->buffer[1] = data; @@ -342,9 +337,11 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const* if ( stream->index == stream->total ) { // zeroes unused bytes - for(uint8_t idx = stream->total; idx < 4; idx++) stream->buffer[idx] = 0; + for (uint8_t idx = stream->total; idx < 4; idx++) { + stream->buffer[idx] = 0; + } - uint16_t const count = tu_fifo_write_n(&midi->tx_ff, stream->buffer, 4); + const uint16_t count = tu_fifo_write_n(&midi->tx_ff, stream->buffer, 4); // complete current event packet, reset stream stream->index = stream->total = 0; @@ -354,20 +351,21 @@ uint32_t tud_midi_n_stream_write(uint8_t itf, uint8_t cable_num, uint8_t const* } } - write_flush(midi); + write_flush(itf); return i; } -bool tud_midi_n_packet_write (uint8_t itf, uint8_t const packet[4]) -{ +bool tud_midi_n_packet_write (uint8_t itf, const uint8_t packet[4]) { midid_interface_t* midi = &_midid_itf[itf]; TU_VERIFY(midi->ep_in); - if (tu_fifo_remaining(&midi->tx_ff) < 4) return false; + if (tu_fifo_remaining(&midi->tx_ff) < 4) { + return false; + } tu_fifo_write_n(&midi->tx_ff, packet, 4); - write_flush(midi); + write_flush(itf); return true; } @@ -431,7 +429,7 @@ void midid_reset(uint8_t rhport) } } -uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint16_t max_len) +uint16_t midid_open(uint8_t rhport, const tusb_desc_interface_t* desc_itf, uint16_t max_len) { // 1st Interface is Audio Control v1 TU_VERIFY(TUSB_CLASS_AUDIO == desc_itf->bInterfaceClass && @@ -439,7 +437,7 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol, 0); uint16_t drv_len = tu_desc_len(desc_itf); - uint8_t const * p_desc = tu_desc_next(desc_itf); + const uint8_t* p_desc = tu_desc_next(desc_itf); // Skip Class Specific descriptors while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len ) @@ -450,7 +448,7 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint // 2nd Interface is MIDI Streaming TU_VERIFY(TUSB_DESC_INTERFACE == tu_desc_type(p_desc), 0); - tusb_desc_interface_t const * desc_midi = (tusb_desc_interface_t const *) p_desc; + const tusb_desc_interface_t* desc_midi = (const tusb_desc_interface_t*) p_desc; TU_VERIFY(TUSB_CLASS_AUDIO == desc_midi->bInterfaceClass && AUDIO_SUBCLASS_MIDI_STREAMING == desc_midi->bInterfaceSubClass && @@ -458,11 +456,10 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint // Find available interface midid_interface_t * p_midi = NULL; - for(uint8_t i=0; ibEndpointAddress; + TU_ASSERT(usbd_edpt_open(rhport, (const tusb_desc_endpoint_t*) p_desc), 0); + uint8_t ep_addr = ((const tusb_desc_endpoint_t*) p_desc)->bEndpointAddress; if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) { @@ -503,7 +500,7 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint } // Prepare for incoming data - _prep_out_transaction(p_midi); + _prep_out_transaction(idx); return drv_len; } @@ -511,14 +508,9 @@ uint16_t midid_open(uint8_t rhport, tusb_desc_interface_t const * desc_itf, uint // Invoked when a control transfer occurred on an interface of this class // Driver response accordingly to the request and the transfer stage (setup/data/ack) // return false to stall control endpoint (e.g unsupported request) -bool midid_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request) -{ - (void) rhport; - (void) stage; - (void) request; - - // driver doesn't support any request yet - return false; +bool midid_control_xfer_cb(uint8_t rhport, uint8_t stage, const tusb_control_request_t* request) { + (void) rhport; (void) stage; (void) request; + return false; // driver doesn't support any request yet } bool midid_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes) @@ -526,40 +518,37 @@ bool midid_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32 (void) result; (void) rhport; - uint8_t itf; + uint8_t idx; midid_interface_t* p_midi; // Identify which interface to use - for (itf = 0; itf < CFG_TUD_MIDI; itf++) - { - p_midi = &_midid_itf[itf]; - if ( ( ep_addr == p_midi->ep_out ) || ( ep_addr == p_midi->ep_in ) ) break; + for (idx = 0; idx < CFG_TUD_MIDI; idx++) { + p_midi = &_midid_itf[idx]; + if ((ep_addr == p_midi->ep_out) || (ep_addr == p_midi->ep_in)) { + break; + } } - TU_ASSERT(itf < CFG_TUD_MIDI); + TU_ASSERT(idx < CFG_TUD_MIDI); // receive new data - if ( ep_addr == p_midi->ep_out ) - { - tu_fifo_write_n(&p_midi->rx_ff, p_midi->epout_buf, (uint16_t) xferred_bytes); + if (ep_addr == p_midi->ep_out) { + tu_fifo_write_n(&p_midi->rx_ff, _midid_epbuf[idx].epout, (uint16_t)xferred_bytes); // invoke receive callback if available - if (tud_midi_rx_cb) tud_midi_rx_cb(itf); + if (tud_midi_rx_cb) { + tud_midi_rx_cb(idx); + } // prepare for next // TODO for now ep_out is not used by public API therefore there is no race condition, // and does not need to claim like ep_in - _prep_out_transaction(p_midi); - } - else if ( ep_addr == p_midi->ep_in ) - { - if (0 == write_flush(p_midi)) - { + _prep_out_transaction(idx); + } else if (ep_addr == p_midi->ep_in) { + if (0 == write_flush(idx)) { // If there is no data left, a ZLP should be sent if // xferred_bytes is multiple of EP size and not zero - if ( !tu_fifo_count(&p_midi->tx_ff) && xferred_bytes && (0 == (xferred_bytes % CFG_TUD_MIDI_EP_BUFSIZE)) ) - { - if ( usbd_edpt_claim(rhport, p_midi->ep_in) ) - { + if (!tu_fifo_count(&p_midi->tx_ff) && xferred_bytes && (0 == (xferred_bytes % CFG_TUD_MIDI_EP_BUFSIZE))) { + if (usbd_edpt_claim(rhport, p_midi->ep_in)) { usbd_edpt_xfer(rhport, p_midi->ep_in, NULL, 0); } } diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index 416bad296..d05032d00 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -58,9 +58,6 @@ // Generate a mask with bit from high (31) to low (0) set, e.g TU_GENMASK(3, 0) = 0b1111 #define TU_GENMASK(h, l) ( (UINT32_MAX << (l)) & (UINT32_MAX >> (31 - (h))) ) -// DCache padding for variable to occupy full cache line -#define TUD_DCACHE_PADDING uint8_t TU_XSTRCAT(dcache_padding_, _TU_COUNTER_)[CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1] - //--------------------------------------------------------------------+ // Includes //--------------------------------------------------------------------+ @@ -179,7 +176,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool tu_is_aligned32(uint32_t value) { retur TU_ATTR_ALWAYS_INLINE static inline bool tu_is_aligned64(uint64_t value) { return (value & 0x3FUL) == 0; } //------------- Mathematics -------------// -TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_div_ceil(uint32_t v, uint32_t d) { return (v + d -1)/d; } +TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_div_ceil(uint32_t v, uint32_t d) { return TU_DIV_CEIL(v, d); } // log2 of a value is its MSB's position // TODO use clz TODO remove diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index d045a3c8f..d0a5c866f 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -35,6 +35,16 @@ extern "C" { #endif +// DCache padding for variable to occupy full cache line +#define TUD_DCACHE_PADDING uint8_t TU_XSTRCAT(dcache_padding_, _TU_COUNTER_)[CFG_TUD_MEM_DCACHE_ENABLE ? CFG_TUD_MEM_DCACHE_LINE_SIZE : 1] + +#define TUD_EPBUF_DEF(_name, _size) \ + union { \ + CFG_TUD_MEM_ALIGN uint8_t _name[_size]; \ + uint8_t _name##_dcache_padding[CFG_TUD_MEM_DCACHE_ENABLE ? (TU_DIV_CEIL(_size, CFG_TUD_MEM_DCACHE_LINE_SIZE) * CFG_TUD_MEM_DCACHE_LINE_SIZE) : 1]; \ + }; + + /*------------------------------------------------------------------*/ /* CONSTANTS *------------------------------------------------------------------*/ diff --git a/src/device/usbd_control.c b/src/device/usbd_control.c index 59c66eb1e..80a2a2cc1 100644 --- a/src/device/usbd_control.c +++ b/src/device/usbd_control.c @@ -35,7 +35,7 @@ //--------------------------------------------------------------------+ // Callback weak stubs (called if application does not provide) //--------------------------------------------------------------------+ -TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const* request) { +TU_ATTR_WEAK void dcd_edpt0_status_complete(uint8_t rhport, const tusb_control_request_t* request) { (void) rhport; (void) request; } @@ -54,10 +54,6 @@ enum { }; typedef struct { - union { - CFG_TUD_MEM_ALIGN uint8_t ep_buf[CFG_TUD_ENDPOINT0_SIZE]; - TUD_DCACHE_PADDING; - }; tusb_control_request_t request; uint8_t* buffer; uint16_t data_len; @@ -65,21 +61,25 @@ typedef struct { usbd_control_xfer_cb_t complete_cb; } usbd_control_xfer_t; -CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN static usbd_control_xfer_t _ctrl_xfer; +static usbd_control_xfer_t _ctrl_xfer; + +CFG_TUD_MEM_SECTION static struct { + TUD_EPBUF_DEF(buf, CFG_TUD_ENDPOINT0_SIZE); +} _ctrl_epbuf; //--------------------------------------------------------------------+ // Application API //--------------------------------------------------------------------+ // Queue ZLP status transaction -static inline bool status_stage_xact(uint8_t rhport, tusb_control_request_t const* request) { +static inline bool status_stage_xact(uint8_t rhport, const tusb_control_request_t* request) { // Opposite to endpoint in Data Phase - uint8_t const ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN; + const uint8_t ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN; return usbd_edpt_xfer(rhport, ep_addr, NULL, 0); } // Status phase -bool tud_control_status(uint8_t rhport, tusb_control_request_t const* request) { +bool tud_control_status(uint8_t rhport, const tusb_control_request_t* request) { _ctrl_xfer.request = (*request); _ctrl_xfer.buffer = NULL; _ctrl_xfer.total_xferred = 0; @@ -92,24 +92,22 @@ bool tud_control_status(uint8_t rhport, tusb_control_request_t const* request) { // Each transaction has up to Endpoint0's max packet size. // This function can also transfer an zero-length packet static bool data_stage_xact(uint8_t rhport) { - uint16_t const xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred, - CFG_TUD_ENDPOINT0_SIZE); - + const uint16_t xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred, CFG_TUD_ENDPOINT0_SIZE); uint8_t ep_addr = EDPT_CTRL_OUT; if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN) { ep_addr = EDPT_CTRL_IN; if (xact_len) { - TU_VERIFY(0 == tu_memcpy_s(_ctrl_xfer.ep_buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len)); + TU_VERIFY(0 == tu_memcpy_s(_ctrl_epbuf.buf, CFG_TUD_ENDPOINT0_SIZE, _ctrl_xfer.buffer, xact_len)); } } - return usbd_edpt_xfer(rhport, ep_addr, xact_len ? _ctrl_xfer.ep_buf : NULL, xact_len); + return usbd_edpt_xfer(rhport, ep_addr, xact_len ? _ctrl_epbuf.buf : NULL, xact_len); } // Transmit data to/from the control endpoint. // If the request's wLength is zero, a status packet is sent instead. -bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const* request, void* buffer, uint16_t len) { +bool tud_control_xfer(uint8_t rhport, const tusb_control_request_t* request, void* buffer, uint16_t len) { _ctrl_xfer.request = (*request); _ctrl_xfer.buffer = (uint8_t*) buffer; _ctrl_xfer.total_xferred = 0U; @@ -119,13 +117,8 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const* request, voi if (_ctrl_xfer.data_len > 0U) { TU_ASSERT(buffer); } - -// TU_LOG2(" Control total data length is %u bytes\r\n", _ctrl_xfer.data_len); - - // Data stage TU_ASSERT(data_stage_xact(rhport)); } else { - // Status stage TU_ASSERT(status_stage_xact(rhport, request)); } @@ -136,7 +129,7 @@ bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const* request, voi // USBD API //--------------------------------------------------------------------+ void usbd_control_reset(void); -void usbd_control_set_request(tusb_control_request_t const* request); +void usbd_control_set_request(const tusb_control_request_t* request); void usbd_control_set_complete_callback(usbd_control_xfer_cb_t fp); bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes); @@ -150,7 +143,7 @@ void usbd_control_set_complete_callback(usbd_control_xfer_cb_t fp) { } // for dcd_set_address where DCD is responsible for status response -void usbd_control_set_request(tusb_control_request_t const* request) { +void usbd_control_set_request(const tusb_control_request_t* request) { _ctrl_xfer.request = (*request); _ctrl_xfer.buffer = NULL; _ctrl_xfer.total_xferred = 0; @@ -180,7 +173,7 @@ bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, if (_ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT) { TU_VERIFY(_ctrl_xfer.buffer); - memcpy(_ctrl_xfer.buffer, _ctrl_xfer.ep_buf, xferred_bytes); + memcpy(_ctrl_xfer.buffer, _ctrl_epbuf.buf, xferred_bytes); TU_LOG_MEM(CFG_TUD_LOG_LEVEL, _usbd_ctrl_buf, xferred_bytes, 2); } @@ -205,7 +198,6 @@ bool usbd_control_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, } if (is_ok) { - // Send status TU_ASSERT(status_stage_xact(rhport, &_ctrl_xfer.request)); } else { // Stall both IN and OUT control endpoint diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index f2eb80e12..6c7b94778 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -31,6 +31,10 @@ #if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2) +#if !CFG_TUD_DWC2_SLAVE_ENABLE && !CFG_TUH_DWC2_DMA_ENABLE +#error DWC2 require either CFG_TUD_DWC2_SLAVE_ENABLE or CFG_TUH_DWC2_DMA_ENABLE to be enabled +#endif + // Debug level for DWC2 #define DWC2_DEBUG 2 @@ -58,11 +62,6 @@ static xfer_ctl_t xfer_status[DWC2_EP_MAX][2]; #define XFER_CTL_BASE(_ep, _dir) (&xfer_status[_ep][_dir]) typedef struct { - union { - CFG_TUD_MEM_ALIGN uint32_t setup_packet[2]; - TUD_DCACHE_PADDING; - }; - // EP0 transfers are limited to 1 packet - larger sizes has to be split uint16_t ep0_pending[2]; // Index determines direction as tusb_dir_t type uint16_t dfifo_top; // top free location in DFIFO in words @@ -74,7 +73,11 @@ typedef struct { bool sof_en; } dcd_data_t; -CFG_TUD_MEM_SECTION static dcd_data_t _dcd_data; +static dcd_data_t _dcd_data; + +CFG_TUD_MEM_SECTION static struct { + TUD_EPBUF_DEF(setup_packet, 8); +} _dcd_usbbuf; //-------------------------------------------------------------------- // DMA @@ -116,7 +119,7 @@ static void dma_setup_prepare(uint8_t rhport) { // Receive only 1 packet dwc2->epout[0].doeptsiz = (1 << DOEPTSIZ_STUPCNT_Pos) | (1 << DOEPTSIZ_PKTCNT_Pos) | (8 << DOEPTSIZ_XFRSIZ_Pos); - dwc2->epout[0].doepdma = (uintptr_t) _dcd_data.setup_packet; + dwc2->epout[0].doepdma = (uintptr_t) _dcd_usbbuf.setup_packet; dwc2->epout[0].doepctl |= DOEPCTL_EPENA | DOEPCTL_USBAEP; } @@ -751,12 +754,14 @@ static void handle_rxflvl_irq(uint8_t rhport) { // Global OUT NAK: do nothing break; - case GRXSTS_PKTSTS_SETUP_RX: + case GRXSTS_PKTSTS_SETUP_RX: { // Setup packet received + uint32_t* setup = (uint32_t*)(uintptr_t) _dcd_usbbuf.setup_packet; // We can receive up to three setup packets in succession, but only the last one is valid. - _dcd_data.setup_packet[0] = (*rx_fifo); - _dcd_data.setup_packet[1] = (*rx_fifo); + setup[0] = (*rx_fifo); + setup[1] = (*rx_fifo); break; + } case GRXSTS_PKTSTS_SETUP_DONE: // Setup packet done: @@ -802,7 +807,7 @@ static void handle_rxflvl_irq(uint8_t rhport) { static void handle_epout_slave(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepint_bm) { if (doepint_bm.setup_phase_done) { - dcd_event_setup_received(rhport, (uint8_t*) _dcd_data.setup_packet, true); + dcd_event_setup_received(rhport, _dcd_usbbuf.setup_packet, true); return; } @@ -878,8 +883,8 @@ static void handle_epout_dma(uint8_t rhport, uint8_t epnum, dwc2_doepint_t doepi if (doepint_bm.setup_phase_done) { dma_setup_prepare(rhport); - dcd_dcache_invalidate(_dcd_data.setup_packet, 8); - dcd_event_setup_received(rhport, (uint8_t*) _dcd_data.setup_packet, true); + dcd_dcache_invalidate(_dcd_usbbuf.setup_packet, 8); + dcd_event_setup_received(rhport, _dcd_usbbuf.setup_packet, true); return; } -- cgit v1.3.1 From 1533e693ee9884c934540fb3a41d97c92e51c2ee Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 22 Nov 2024 15:45:08 +0700 Subject: TUD_EPBUF_TYPE_DEF ncm_device --- src/class/net/ncm_device.c | 21 +++++++++++++++------ src/common/tusb_mcu.h | 4 ++-- src/common/tusb_types.h | 3 ++- src/portable/synopsys/dwc2/dwc2_esp32.h | 1 - src/tusb_option.h | 22 +++++++++++++++++++++- 5 files changed, 40 insertions(+), 11 deletions(-) (limited to 'src/portable') diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c index 1516c329a..6e657abdb 100644 --- a/src/class/net/ncm_device.c +++ b/src/class/net/ncm_device.c @@ -89,7 +89,6 @@ typedef struct { uint8_t rhport; // storage of \a rhport because some callbacks are done without it // recv handling - CFG_TUSB_MEM_ALIGN recv_ntb_t recv_ntb[RECV_NTB_N]; // actual recv NTBs recv_ntb_t *recv_free_ntb[RECV_NTB_N]; // free list of recv NTBs recv_ntb_t *recv_ready_ntb[RECV_NTB_N]; // NTBs waiting for transmission to glue logic recv_ntb_t *recv_tinyusb_ntb; // buffer for the running transfer TinyUSB -> driver @@ -97,7 +96,6 @@ typedef struct { uint16_t recv_glue_ntb_datagram_ndx; // index into \a recv_glue_ntb_datagram // xmit handling - CFG_TUSB_MEM_ALIGN xmit_ntb_t xmit_ntb[XMIT_NTB_N]; // actual xmit NTBs xmit_ntb_t *xmit_free_ntb[XMIT_NTB_N]; // free list of xmit NTBs xmit_ntb_t *xmit_ready_ntb[XMIT_NTB_N]; // NTBs waiting for transmission to TinyUSB xmit_ntb_t *xmit_tinyusb_ntb; // buffer for the running transfer driver -> TinyUSB @@ -118,7 +116,18 @@ typedef struct { bool tud_network_recv_renew_process_again; // tud_network_recv_renew() should process again } ncm_interface_t; -CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN tu_static ncm_interface_t ncm_interface; +typedef struct { + struct { + TUD_EPBUF_TYPE_DEF(ntb, recv_ntb_t); + } recv[RECV_NTB_N]; + + struct { + TUD_EPBUF_TYPE_DEF(ntb, xmit_ntb_t); + } xmit[XMIT_NTB_N]; +} ncm_epbuf_t; + +static ncm_interface_t ncm_interface; +CFG_TUD_MEM_SECTION static ncm_epbuf_t ncm_epbuf; /** * This is the NTB parameter structure @@ -126,7 +135,7 @@ CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN tu_static ncm_interface_t ncm_interface; * \attention * We are lucky, that byte order is correct */ -CFG_TUD_MEM_SECTION CFG_TUD_MEM_ALIGN tu_static const ntb_parameters_t ntb_parameters = { +TU_ATTR_ALIGNED(4) static const ntb_parameters_t ntb_parameters = { .wLength = sizeof(ntb_parameters_t), .bmNtbFormatsSupported = 0x01,// 16-bit NTB supported .dwNtbInMaxSize = CFG_TUD_NCM_IN_NTB_MAX_SIZE, @@ -743,10 +752,10 @@ void netd_init(void) { memset(&ncm_interface, 0, sizeof(ncm_interface)); for (int i = 0; i < XMIT_NTB_N; ++i) { - ncm_interface.xmit_free_ntb[i] = ncm_interface.xmit_ntb + i; + ncm_interface.xmit_free_ntb[i] = &ncm_epbuf.xmit[i].ntb; } for (int i = 0; i < RECV_NTB_N; ++i) { - ncm_interface.recv_free_ntb[i] = ncm_interface.recv_ntb + i; + ncm_interface.recv_free_ntb[i] = &ncm_epbuf.recv[i].ntb; } } // netd_init diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index f6f90c592..622c8fc21 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -373,8 +373,8 @@ #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1 #endif - #define CFG_TUD_MEM_DCACHE_LINE_SIZE 64 - #define CFG_TUH_MEM_DCACHE_LINE_SIZE 64 + #define CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT 64 + #define CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT 64 #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0 // TODO currently have issue with buffer DMA with espressif diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index c726add84..e5660861d 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -35,16 +35,17 @@ extern "C" { #endif -// DCache padding for variable to occupy full cache line #define TUD_EPBUF_DCACHE_SIZE(_size) \ (CFG_TUD_MEM_DCACHE_ENABLE ? (TU_DIV_CEIL(_size, CFG_TUD_MEM_DCACHE_LINE_SIZE) * CFG_TUD_MEM_DCACHE_LINE_SIZE) : (_size)) +// Declare an endpoint buffer with uint8_t[size] #define TUD_EPBUF_DEF(_name, _size) \ union { \ CFG_TUD_MEM_ALIGN uint8_t _name[_size]; \ uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(_size)]; \ }; +// Declare an endpoint buffer with a type #define TUD_EPBUF_TYPE_DEF(_name, _type) \ union { \ CFG_TUD_MEM_ALIGN _type _name; \ diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index 84a8360c5..6220716d3 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -116,7 +116,6 @@ TU_ATTR_ALWAYS_INLINE static inline void dwc2_phy_update(dwc2_regs_t* dwc2, uint //--------------------------------------------------------------------+ #if CFG_TUD_DWC2_DMA_ENABLE || CFG_TUH_DWC2_DMA_ENABLE #if defined(SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE) && SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE -#include "hal/cache_hal.h" #include "esp_cache.h" #if CFG_TUD_MEM_DCACHE_LINE_SIZE != CONFIG_CACHE_L1_CACHE_LINE_SIZE || \ diff --git a/src/tusb_option.h b/src/tusb_option.h index 68fd90de9..2f07b8da6 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -433,7 +433,11 @@ #endif #ifndef CFG_TUD_MEM_DCACHE_LINE_SIZE - #define CFG_TUD_MEM_DCACHE_LINE_SIZE 32 + #ifndef CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT + #define CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT 32 + #endif + + #define CFG_TUD_MEM_DCACHE_LINE_SIZE CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT #endif #ifndef CFG_TUD_ENDPOINT0_SIZE @@ -543,6 +547,22 @@ #define CFG_TUH_MEM_ALIGN CFG_TUSB_MEM_ALIGN #endif +#ifndef CFG_TUH_MEM_DCACHE_ENABLE + #ifndef CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 0 + #endif + + #define CFG_TUH_MEM_DCACHE_ENABLE CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT +#endif + +#ifndef CFG_TUH_MEM_DCACHE_LINE_SIZE + #ifndef CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT + #define CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT 32 + #endif + + #define CFG_TUH_MEM_DCACHE_LINE_SIZE CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT +#endif + //------------- CLASS -------------// #ifndef CFG_TUH_HUB -- cgit v1.3.1 From 833eb7d22d641b2c2b1dd701f86d823f67b12d6d Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 25 Nov 2024 19:11:19 +0700 Subject: change dcd_dcache_*() API return type from void to bool --- src/common/tusb_mcu.h | 10 +++------- src/common/tusb_types.h | 24 ++++++++++++++++++++++-- src/device/dcd.h | 6 +++--- src/device/usbd.c | 9 ++++++--- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 30 ++++++++---------------------- src/portable/synopsys/dwc2/dcd_dwc2.c | 21 +++++++++------------ src/portable/synopsys/dwc2/dwc2_esp32.h | 12 ++++++------ src/tusb_option.h | 20 ++++++++++---------- 8 files changed, 67 insertions(+), 65 deletions(-) (limited to 'src/portable') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 622c8fc21..22d652913 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -364,19 +364,15 @@ #define TUP_DCD_ENDPOINT_MAX 16 // FS 7 ep, HS 16 ep #define CFG_TUSB_OS_INC_PATH_DEFAULT freertos/ + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 64 #if defined(CFG_TUD_DWC2_DMA_ENABLE) && CFG_TUD_DWC2_DMA_ENABLE == 1 #define CFG_TUD_MEM_DCACHE_ENABLE_DEFAULT 1 #endif - #if defined(CFG_TUH_DWC2_DMA_ENABLE) && CFG_TUH_DWC2_DMA_ENABLE == 1 - #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 1 - #endif - - #define CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT 64 - #define CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT 64 + #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0 + #define CFG_TUH_MEM_DCACHE_ENABLE_DEFAULT 0 - #define CFG_TUH_DWC2_DMA_ENABLE_DEFAULT 0 // TODO currently have issue with buffer DMA with espressif #elif TU_CHECK_MCU(OPT_MCU_ESP32, OPT_MCU_ESP32C2, OPT_MCU_ESP32C3, OPT_MCU_ESP32C6, OPT_MCU_ESP32H2) #if (CFG_TUD_ENABLED || !(defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421)) diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index e5660861d..89c65ced1 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -35,8 +35,9 @@ extern "C" { #endif -#define TUD_EPBUF_DCACHE_SIZE(_size) \ - (CFG_TUD_MEM_DCACHE_ENABLE ? (TU_DIV_CEIL(_size, CFG_TUD_MEM_DCACHE_LINE_SIZE) * CFG_TUD_MEM_DCACHE_LINE_SIZE) : (_size)) +//------------- Device DCache declaration -------------// +#define TUD_EPBUF_DCACHE_SIZE(_size) (CFG_TUD_MEM_DCACHE_ENABLE ? \ + (TU_DIV_CEIL(_size, CFG_TUD_MEM_DCACHE_LINE_SIZE) * CFG_TUD_MEM_DCACHE_LINE_SIZE) : (_size)) // Declare an endpoint buffer with uint8_t[size] #define TUD_EPBUF_DEF(_name, _size) \ @@ -52,6 +53,25 @@ uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \ }; +//------------- Host DCache declaration -------------// +#define TUH_EPBUF_DCACHE_SIZE(_size) (CFG_TUH_MEM_DCACHE_ENABLE ? \ + (TU_DIV_CEIL(_size, CFG_TUH_MEM_DCACHE_LINE_SIZE) * CFG_TUH_MEM_DCACHE_LINE_SIZE) : (_size)) + +// Declare an endpoint buffer with uint8_t[size] +#define TUH_EPBUF_DEF(_name, _size) \ + union { \ + CFG_TUH_MEM_ALIGN uint8_t _name[_size]; \ + uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(_size)]; \ + }; + +// Declare an endpoint buffer with a type +#define TUH_EPBUF_TYPE_DEF(_name, _type) \ + union { \ + CFG_TUH_MEM_ALIGN _type _name; \ + uint8_t _name##_dcache_padding[TUH_EPBUF_DCACHE_SIZE(sizeof(_type))]; \ + }; + + /*------------------------------------------------------------------*/ /* CONSTANTS *------------------------------------------------------------------*/ diff --git a/src/device/dcd.h b/src/device/dcd.h index 0ecdec4ed..789552d47 100644 --- a/src/device/dcd.h +++ b/src/device/dcd.h @@ -93,15 +93,15 @@ typedef struct TU_ATTR_ALIGNED(4) { // clean/flush data cache: write cache -> memory. // Required before an DMA TX transfer to make sure data is in memory -void dcd_dcache_clean(const void* addr, uint32_t data_size); +bool dcd_dcache_clean(const void* addr, uint32_t data_size); // invalidate data cache: mark cache as invalid, next read will read from memory // Required BOTH before and after an DMA RX transfer -void dcd_dcache_invalidate(const void* addr, uint32_t data_size); +bool dcd_dcache_invalidate(const void* addr, uint32_t data_size); // clean and invalidate data cache // Required before an DMA transfer where memory is both read/write by DMA -void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size); +bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size); //--------------------------------------------------------------------+ // Controller API diff --git a/src/device/usbd.c b/src/device/usbd.c index f485b6872..2a6081673 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -97,16 +97,19 @@ TU_ATTR_WEAK void dcd_disconnect(uint8_t rhport) { (void) rhport; } -TU_ATTR_WEAK void dcd_dcache_clean(const void* addr, uint32_t data_size) { +TU_ATTR_WEAK bool dcd_dcache_clean(const void* addr, uint32_t data_size) { (void) addr; (void) data_size; + return true; } -TU_ATTR_WEAK void dcd_dcache_invalidate(const void* addr, uint32_t data_size) { +TU_ATTR_WEAK bool dcd_dcache_invalidate(const void* addr, uint32_t data_size) { (void) addr; (void) data_size; + return true; } -TU_ATTR_WEAK void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) { +TU_ATTR_WEAK bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) { (void) addr; (void) data_size; + return true; } //--------------------------------------------------------------------+ diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index 430a0aad1..d9f7ca8ea 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -34,43 +34,29 @@ #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX #include "ci_hs_imxrt.h" - void dcd_dcache_clean(void const* addr, uint32_t data_size) { - imxrt_dcache_clean(addr, data_size); + bool dcd_dcache_clean(void const* addr, uint32_t data_size) { + return imxrt_dcache_clean(addr, data_size); } - void dcd_dcache_invalidate(void const* addr, uint32_t data_size) { - imxrt_dcache_invalidate(addr, data_size); + bool dcd_dcache_invalidate(void const* addr, uint32_t data_size) { + return imxrt_dcache_invalidate(addr, data_size); } - void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { - imxrt_dcache_clean_invalidate(addr, data_size); + bool dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { + return imxrt_dcache_clean_invalidate(addr, data_size); } -#else - -#if TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) +#elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) #include "ci_hs_lpc18_43.h" #elif TU_CHECK_MCU(OPT_MCU_MCXN9) // MCX N9 only port 1 use this controller #include "ci_hs_mcx.h" + #else #error "Unsupported MCUs" #endif - TU_ATTR_WEAK void dcd_dcache_clean(void const* addr, uint32_t data_size) { - (void) addr; (void) data_size; - } - - TU_ATTR_WEAK void dcd_dcache_invalidate(void const* addr, uint32_t data_size) { - (void) addr; (void) data_size; - } - - TU_ATTR_WEAK void dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { - (void) addr; (void) data_size; - } -#endif - //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 6c7b94778..8a9d06bc2 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -83,22 +83,19 @@ CFG_TUD_MEM_SECTION static struct { // DMA //-------------------------------------------------------------------- #if CFG_TUD_MEM_DCACHE_ENABLE -void dcd_dcache_clean(const void* addr, uint32_t data_size) { - if (addr && data_size) { - dwc2_dcache_clean(addr, data_size); - } +bool dcd_dcache_clean(const void* addr, uint32_t data_size) { + TU_VERIFY(addr && data_size); + return dwc2_dcache_clean(addr, data_size); } -void dcd_dcache_invalidate(const void* addr, uint32_t data_size) { - if (addr && data_size) { - dwc2_dcache_invalidate(addr, data_size); - } +bool dcd_dcache_invalidate(const void* addr, uint32_t data_size) { + TU_VERIFY(addr && data_size); + return dwc2_dcache_invalidate(addr, data_size); } -void dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) { - if (addr && data_size) { - dwc2_dcache_clean_invalidate(addr, data_size); - } +bool dcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) { + TU_VERIFY(addr && data_size); + return dwc2_dcache_clean_invalidate(addr, data_size); } #endif diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index 6220716d3..ddbfd0d10 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -130,22 +130,22 @@ TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_ return size; } -TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_clean(const void* addr, uint32_t data_size) { +TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean(const void* addr, uint32_t data_size) { const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M; data_size = round_up_to_cache_line_size(data_size); - assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag)); + return ESP_OK == esp_cache_msync((void*)addr, data_size, flag); } -TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_invalidate(const void* addr, uint32_t data_size) { +TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_invalidate(const void* addr, uint32_t data_size) { const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_M2C; data_size = round_up_to_cache_line_size(data_size); - assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag)); + return ESP_OK == esp_cache_msync((void*)addr, data_size, flag); } -TU_ATTR_ALWAYS_INLINE static inline void dwc2_dcache_clean_invalidate(const void* addr, uint32_t data_size) { +TU_ATTR_ALWAYS_INLINE static inline bool dwc2_dcache_clean_invalidate(const void* addr, uint32_t data_size) { const int flag = ESP_CACHE_MSYNC_FLAG_TYPE_DATA | ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_DIR_M2C; data_size = round_up_to_cache_line_size(data_size); - assert(ESP_OK == esp_cache_msync((void*)addr, data_size, flag)); + return ESP_OK == esp_cache_msync((void*)addr, data_size, flag); } #endif diff --git a/src/tusb_option.h b/src/tusb_option.h index 2f07b8da6..d8b9feb16 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -397,6 +397,14 @@ #define CFG_TUSB_MEM_ALIGN TU_ATTR_ALIGNED(4) #endif +#ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE + #ifndef CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT 32 + #endif + + #define CFG_TUSB_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE_DEFAULT +#endif + // OS selection #ifndef CFG_TUSB_OS #define CFG_TUSB_OS OPT_OS_NONE @@ -433,11 +441,7 @@ #endif #ifndef CFG_TUD_MEM_DCACHE_LINE_SIZE - #ifndef CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT - #define CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT 32 - #endif - - #define CFG_TUD_MEM_DCACHE_LINE_SIZE CFG_TUD_MEM_DCACHE_LINE_SIZE_DEFAULT + #define CFG_TUD_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE #endif #ifndef CFG_TUD_ENDPOINT0_SIZE @@ -556,11 +560,7 @@ #endif #ifndef CFG_TUH_MEM_DCACHE_LINE_SIZE - #ifndef CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT - #define CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT 32 - #endif - - #define CFG_TUH_MEM_DCACHE_LINE_SIZE CFG_TUH_MEM_DCACHE_LINE_SIZE_DEFAULT + #define CFG_TUH_MEM_DCACHE_LINE_SIZE CFG_TUSB_MEM_DCACHE_LINE_SIZE #endif //------------- CLASS -------------// -- cgit v1.3.1 From be25aa31f6720e0efe96e8656f46adf0ccbbce50 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 26 Nov 2024 10:20:38 +0700 Subject: hcd dwc2 add dcache support, usbh correctly use cache line size with TUH_EPBUF_DEF --- .../components/tinyusb_src/CMakeLists.txt | 3 +- src/host/hcd.h | 6 +- src/host/usbh.c | 72 ++++++++++++++-------- src/portable/synopsys/dwc2/dcd_dwc2.c | 2 +- src/portable/synopsys/dwc2/hcd_dwc2.c | 28 ++++++++- 5 files changed, 78 insertions(+), 33 deletions(-) (limited to 'src/portable') diff --git a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt index 9f55c8d5a..95fb2e440 100644 --- a/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt +++ b/hw/bsp/espressif/components/tinyusb_src/CMakeLists.txt @@ -18,7 +18,8 @@ list(APPEND compile_definitions if (target STREQUAL esp32p4) # P4 change alignment to 64 (DCache line size) for possible DMA configuration list(APPEND compile_definitions - CFG_TUSB_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\) + CFG_TUD_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\) + CFG_TUH_MEM_ALIGN=__attribute__\(\(aligned\(64\)\)\) ) endif () diff --git a/src/host/hcd.h b/src/host/hcd.h index 6518e6fd2..56b6fdb5d 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -103,15 +103,15 @@ typedef struct { // clean/flush data cache: write cache -> memory. // Required before an DMA TX transfer to make sure data is in memory -bool hcd_dcache_clean(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_clean(void const* addr, uint32_t data_size); // invalidate data cache: mark cache as invalid, next read will read from memory // Required BOTH before and after an DMA RX transfer -bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_invalidate(void const* addr, uint32_t data_size); // clean and invalidate data cache // Required before an DMA transfer where memory is both read/write by DMA -bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) TU_ATTR_WEAK; +bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size); //--------------------------------------------------------------------+ // Controller API diff --git a/src/host/usbh.c b/src/host/usbh.c index b0a2b2160..f2683e235 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -65,6 +65,21 @@ TU_ATTR_WEAK void tuh_event_hook_cb(uint8_t rhport, uint32_t eventid, bool in_is (void) in_isr; } +TU_ATTR_WEAK bool hcd_dcache_clean(const void* addr, uint32_t data_size) { + (void) addr; (void) data_size; + return false; +} + +TU_ATTR_WEAK bool hcd_dcache_invalidate(const void* addr, uint32_t data_size) { + (void) addr; (void) data_size; + return false; +} + +TU_ATTR_WEAK bool hcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) { + (void) addr; (void) data_size; + return false; +} + //--------------------------------------------------------------------+ // USBH-HCD common data structure //--------------------------------------------------------------------+ @@ -249,14 +264,10 @@ static usbh_device_t _usbh_devices[TOTAL_DEVICES]; OSAL_QUEUE_DEF(usbh_int_set, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t); static osal_queue_t _usbh_q; -CFG_TUH_MEM_SECTION CFG_TUH_MEM_ALIGN -static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE]; - // Control transfers: since most controllers do not support multiple control transfers // on multiple devices concurrently and control transfers are not used much except for // enumeration, we will only execute control transfers one at a time. -CFG_TUH_MEM_SECTION struct { - CFG_TUH_MEM_ALIGN tusb_control_request_t request; +static struct { uint8_t* buffer; tuh_xfer_cb_t complete_cb; uintptr_t user_data; @@ -264,7 +275,14 @@ CFG_TUH_MEM_SECTION struct { uint8_t daddr; volatile uint8_t stage; volatile uint16_t actual_len; -}_ctrl_xfer; +} _ctrl_xfer; + +typedef struct { + TUH_EPBUF_TYPE_DEF(request, tusb_control_request_t); + TUH_EPBUF_DEF(ctrl, CFG_TUH_ENUMERATION_BUFSIZE); +} usbh_epbuf_t; + +CFG_TUH_MEM_SECTION static usbh_epbuf_t _usbh_epbuf; //------------- Helper Function -------------// @@ -475,7 +493,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { switch (event.event_id) { case HCD_EVENT_DEVICE_ATTACH: - // due to the shared _usbh_ctrl_buf, we must complete enumerating one device before enumerating another one. + // due to the shared control buffer, we must complete enumerating one device before enumerating another one. // TODO better to have an separated queue for newly attached devices if (_dev0.enumerating) { // Some device can cause multiple duplicated attach events @@ -622,10 +640,10 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { _ctrl_xfer.daddr = daddr; _ctrl_xfer.actual_len = 0; - _ctrl_xfer.request = (*xfer->setup); _ctrl_xfer.buffer = xfer->buffer; _ctrl_xfer.complete_cb = xfer->complete_cb; _ctrl_xfer.user_data = xfer->user_data; + _usbh_epbuf.request = (*xfer->setup); } (void) osal_mutex_unlock(_usbh_mutex); @@ -639,7 +657,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { TU_LOG_BUF_USBH(xfer->setup, 8); if (xfer->complete_cb) { - TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_ctrl_xfer.request) ); + TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t const*) &_usbh_epbuf.request) ); }else { // blocking if complete callback is not provided // change callback to internal blocking, and result as user argument @@ -649,7 +667,7 @@ bool tuh_control_xfer (tuh_xfer_t* xfer) { _ctrl_xfer.user_data = (uintptr_t) &result; _ctrl_xfer.complete_cb = _control_blocking_complete_cb; - TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_ctrl_xfer.request) ); + TU_ASSERT( hcd_setup_send(rhport, daddr, (uint8_t*) &_usbh_epbuf.request) ); while (result == XFER_RESULT_INVALID) { // Note: this can be called within an callback ie. part of tuh_task() @@ -681,7 +699,7 @@ static void _control_xfer_complete(uint8_t daddr, xfer_result_t result) { TU_LOG_USBH("\r\n"); // duplicate xfer since user can execute control transfer within callback - tusb_control_request_t const request = _ctrl_xfer.request; + tusb_control_request_t const request = _usbh_epbuf.request; tuh_xfer_t xfer_temp = { .daddr = daddr, .ep_addr = 0, @@ -704,7 +722,7 @@ static bool usbh_control_xfer_cb (uint8_t daddr, uint8_t ep_addr, xfer_result_t (void) ep_addr; const uint8_t rhport = usbh_get_rhport(daddr); - tusb_control_request_t const * request = &_ctrl_xfer.request; + tusb_control_request_t const * request = &_usbh_epbuf.request; if (XFER_RESULT_SUCCESS != result) { TU_LOG_USBH("[%u:%u] Control %s, xferred_bytes = %" PRIu32 "\r\n", rhport, daddr, result == XFER_RESULT_STALLED ? "STALLED" : "FAILED", xferred_bytes); @@ -817,7 +835,7 @@ uint8_t usbh_get_rhport(uint8_t dev_addr) { } uint8_t *usbh_get_enum_buf(void) { - return _usbh_ctrl_buf; + return _usbh_epbuf.ctrl; } void usbh_int_set(bool enabled) { @@ -1279,7 +1297,7 @@ static void process_removing_device(uint8_t rhport, uint8_t hub_addr, uint8_t hu // Enumeration Process // is a lengthy process with a series of control transfer to configure // newly attached device. -// NOTE: due to the shared _usbh_ctrl_buf, we must complete enumerating +// NOTE: due to the shared control buffer, we must complete enumerating // one device before enumerating another one. //--------------------------------------------------------------------+ @@ -1347,7 +1365,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { case ENUM_HUB_CLEAR_RESET_1: { hub_port_status_response_t port_status; - memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t)); + memcpy(&port_status, _usbh_epbuf.ctrl, sizeof(hub_port_status_response_t)); if (!port_status.status.connection) { // device unplugged while delaying, nothing else to do @@ -1368,13 +1386,13 @@ static void process_enumeration(tuh_xfer_t* xfer) { case ENUM_HUB_GET_STATUS_2: tusb_time_delay_ms_api(ENUM_RESET_DELAY_MS); - TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, + TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_epbuf.ctrl, process_enumeration, ENUM_HUB_CLEAR_RESET_2),); break; case ENUM_HUB_CLEAR_RESET_2: { hub_port_status_response_t port_status; - memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t)); + memcpy(&port_status, _usbh_epbuf.ctrl, sizeof(hub_port_status_response_t)); // Acknowledge Port Reset Change if Reset Successful if (port_status.change.reset) { @@ -1392,7 +1410,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { // Get first 8 bytes of device descriptor for Control Endpoint size TU_LOG_USBH("Get 8 byte of Device Descriptor\r\n"); - TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_ctrl_buf, 8, + TU_ASSERT(tuh_descriptor_get_device(addr0, _usbh_epbuf.ctrl, 8, process_enumeration, ENUM_SET_ADDR),); break; } @@ -1443,13 +1461,13 @@ static void process_enumeration(tuh_xfer_t* xfer) { // Get full device descriptor TU_LOG_USBH("Get Device Descriptor\r\n"); - TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_ctrl_buf, sizeof(tusb_desc_device_t), + TU_ASSERT(tuh_descriptor_get_device(new_addr, _usbh_epbuf.ctrl, sizeof(tusb_desc_device_t), process_enumeration, ENUM_GET_9BYTE_CONFIG_DESC),); break; } case ENUM_GET_9BYTE_CONFIG_DESC: { - tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf; + tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_epbuf.ctrl; usbh_device_t* dev = get_device(daddr); TU_ASSERT(dev,); @@ -1459,18 +1477,18 @@ static void process_enumeration(tuh_xfer_t* xfer) { dev->i_product = desc_device->iProduct; dev->i_serial = desc_device->iSerialNumber; - // if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_ctrl_buf); + // if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_epbuf.ctrl); // Get 9-byte for total length uint8_t const config_idx = CONFIG_NUM - 1; TU_LOG_USBH("Get Configuration[0] Descriptor (9 bytes)\r\n"); - TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, 9, + TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, 9, process_enumeration, ENUM_GET_FULL_CONFIG_DESC),); break; } case ENUM_GET_FULL_CONFIG_DESC: { - uint8_t const* desc_config = _usbh_ctrl_buf; + uint8_t const* desc_config = _usbh_epbuf.ctrl; // Use offsetof to avoid pointer to the odd/misaligned address uint16_t const total_len = tu_le16toh( @@ -1482,7 +1500,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { // Get full configuration descriptor uint8_t const config_idx = CONFIG_NUM - 1; TU_LOG_USBH("Get Configuration[0] Descriptor\r\n"); - TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_ctrl_buf, total_len, + TU_ASSERT(tuh_descriptor_get_configuration(daddr, config_idx, _usbh_epbuf.ctrl, total_len, process_enumeration, ENUM_SET_CONFIG),); break; } @@ -1500,7 +1518,7 @@ static void process_enumeration(tuh_xfer_t* xfer) { // Parse configuration & set up drivers // driver_open() must not make any usb transfer - TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_ctrl_buf),); + TU_ASSERT(_parse_configuration_descriptor(daddr, (tusb_desc_configuration_t*) _usbh_epbuf.ctrl),); // Start the Set Configuration process for interfaces (itf = TUSB_INDEX_INVALID_8) // Since driver can perform control transfer within its set_config, this is done asynchronously. @@ -1561,7 +1579,7 @@ static bool enum_new_device(hcd_event_t* event) { tusb_time_delay_ms_api(ENUM_DEBOUNCING_DELAY_MS); // ENUM_HUB_GET_STATUS - TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, + TU_ASSERT(hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_epbuf.ctrl, process_enumeration, ENUM_HUB_CLEAR_RESET_1)); } #endif // hub @@ -1589,7 +1607,7 @@ static uint8_t get_new_address(bool is_hub) { } static bool enum_request_set_addr(void) { - tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf; + tusb_desc_device_t const* desc_device = (tusb_desc_device_t const*) _usbh_epbuf.ctrl; // Get new address uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB); diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 8a9d06bc2..04108499d 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -31,7 +31,7 @@ #if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2) -#if !CFG_TUD_DWC2_SLAVE_ENABLE && !CFG_TUH_DWC2_DMA_ENABLE +#if !(CFG_TUD_DWC2_SLAVE_ENABLE || CFG_TUH_DWC2_DMA_ENABLE) #error DWC2 require either CFG_TUD_DWC2_SLAVE_ENABLE or CFG_TUH_DWC2_DMA_ENABLE to be enabled #endif diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index 8e0162ed6..ebbb6200a 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -28,6 +28,10 @@ #if CFG_TUH_ENABLED && defined(TUP_USBIP_DWC2) +#if !(CFG_TUH_DWC2_SLAVE_ENABLE || CFG_TUH_DWC2_DMA_ENABLE) +#error DWC2 require either CFG_TUH_DWC2_SLAVE_ENABLE or CFG_TUH_DWC2_DMA_ENABLE to be enabled +#endif + // Debug level for DWC2 #define DWC2_DEBUG 2 @@ -132,6 +136,23 @@ TU_ATTR_ALWAYS_INLINE static inline bool dma_host_enabled(const dwc2_regs_t* dwc return CFG_TUH_DWC2_DMA_ENABLE && dwc2->ghwcfg2_bm.arch == GHWCFG2_ARCH_INTERNAL_DMA; } +#if CFG_TUH_MEM_DCACHE_ENABLE +bool hcd_dcache_clean(const void* addr, uint32_t data_size) { + TU_VERIFY(addr && data_size); + return dwc2_dcache_clean(addr, data_size); +} + +bool hcd_dcache_invalidate(const void* addr, uint32_t data_size) { + TU_VERIFY(addr && data_size); + return dwc2_dcache_invalidate(addr, data_size); +} + +bool hcd_dcache_clean_invalidate(const void* addr, uint32_t data_size) { + TU_VERIFY(addr && data_size); + return dwc2_dcache_clean_invalidate(addr, data_size); +} +#endif + // Allocate a channel for new transfer TU_ATTR_ALWAYS_INLINE static inline uint8_t channel_alloc(dwc2_regs_t* dwc2) { const uint8_t max_channel = DWC2_CHANNEL_COUNT(dwc2); @@ -555,6 +576,7 @@ static bool channel_xfer_start(dwc2_regs_t* dwc2, uint8_t ch_id) { if (hcchar_bm->ep_dir == TUSB_DIR_IN) { channel_send_in_token(dwc2, channel); } else { + hcd_dcache_clean(edpt->buffer, edpt->buflen); channel->hcchar |= HCCHAR_CHENA; } } else { @@ -1119,13 +1141,17 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) { const uint32_t hcint = channel->hcint; channel->hcint = hcint; // clear interrupt - bool is_done; + bool is_done = false; if (is_dma) { #if CFG_TUH_DWC2_DMA_ENABLE if (hcchar_bm.ep_dir == TUSB_DIR_OUT) { is_done = handle_channel_out_dma(dwc2, ch_id, hcint); } else { is_done = handle_channel_in_dma(dwc2, ch_id, hcint); + if (is_done && (channel->hcdma > xfer->xferred_bytes)) { + // hcdma is increased by word --> need to align4 + hcd_dcache_invalidate((void*) tu_align4(channel->hcdma - xfer->xferred_bytes), xfer->xferred_bytes); + } } #endif } else { -- cgit v1.3.1 From ae7cdcd0705aedbae2ac4d6eb051aa0d359fe3b5 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 27 Nov 2024 12:18:54 +0700 Subject: fix typo --- src/portable/synopsys/dwc2/dcd_dwc2.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 04108499d..63d2e5bb1 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -31,8 +31,8 @@ #if CFG_TUD_ENABLED && defined(TUP_USBIP_DWC2) -#if !(CFG_TUD_DWC2_SLAVE_ENABLE || CFG_TUH_DWC2_DMA_ENABLE) -#error DWC2 require either CFG_TUD_DWC2_SLAVE_ENABLE or CFG_TUH_DWC2_DMA_ENABLE to be enabled +#if !(CFG_TUD_DWC2_SLAVE_ENABLE || CFG_TUD_DWC2_DMA_ENABLE) +#error DWC2 require either CFG_TUD_DWC2_SLAVE_ENABLE or CFG_TUD_DWC2_DMA_ENABLE to be enabled #endif // Debug level for DWC2 @@ -615,10 +615,6 @@ bool dcd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t* ff, uint16_t return true; } -void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { - edpt_disable(rhport, ep_addr, false); -} - void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); edpt_disable(rhport, ep_addr, true); -- cgit v1.3.1 From dbc2c8d9720593ce4b0bbd0c96b3b91f81ce15bb Mon Sep 17 00:00:00 2001 From: Ha Thach Date: Wed, 27 Nov 2024 18:28:12 +0700 Subject: Fix missing protoype warning, change TUD_EPBUF_TYPE_DEF order (#2889) * change TUD_EPBUF_TYPE_DEF order * add and fix -Wmissing-prototypes warnings for cmake (skip make) --- .github/workflows/build.yml | 5 +++ .idea/cmake.xml | 8 ++--- examples/build_system/make/toolchain/gcc_common.mk | 1 + hw/bsp/board.c | 19 +++++----- src/CMakeLists.txt | 1 + src/class/audio/audio_device.c | 2 +- src/class/bth/bth_device.c | 2 +- src/class/net/ncm_device.c | 8 ++--- src/class/usbtmc/usbtmc_device.c | 2 +- src/class/video/video_device.h | 2 ++ src/common/tusb_types.h | 2 +- src/portable/dialog/da146xx/dcd_da146xx.c | 1 + src/portable/microchip/samd/dcd_samd.c | 2 +- src/portable/microchip/samg/dcd_samg.c | 40 ++++++++-------------- src/portable/nordic/nrf5x/dcd_nrf5x.c | 3 +- src/portable/nxp/khci/hcd_khci.c | 2 +- src/portable/nxp/lpc17_40/hcd_lpc17_40.c | 1 + src/portable/renesas/rusb2/rusb2_common.c | 1 + 18 files changed, 54 insertions(+), 48 deletions(-) (limited to 'src/portable') diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml index 8d5bcbc67..283b72061 100644 --- a/.github/workflows/build.yml +++ b/.github/workflows/build.yml @@ -118,6 +118,8 @@ jobs: runs-on: [self-hosted, Linux, X64, hifiphile] env: BUILD_ARGS: ${{ join(fromJSON(needs.set-matrix.outputs.json)['arm-iar'], ' ') }} + IAR_LMS_CLOUD_URL: https://license.cloud.iar.com + IAR_LMS_BEARER_TOKEN: ${{ secrets.IAR_LMS_BEARER_TOKEN }} steps: - name: Clean workspace run: | @@ -125,6 +127,9 @@ jobs: rm -rf "${{ github.workspace }}" mkdir -p "${{ github.workspace }}" + - name: Toolchain version + run: iccarm --version + - name: Checkout TinyUSB uses: actions/checkout@v4 diff --git a/.idea/cmake.xml b/.idea/cmake.xml index aa15374b9..25a8513ca 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -61,7 +61,7 @@ - + @@ -83,7 +83,7 @@ - + @@ -100,7 +100,7 @@ - + @@ -108,7 +108,7 @@ - + diff --git a/examples/build_system/make/toolchain/gcc_common.mk b/examples/build_system/make/toolchain/gcc_common.mk index 6986d8bba..0cbb6774d 100644 --- a/examples/build_system/make/toolchain/gcc_common.mk +++ b/examples/build_system/make/toolchain/gcc_common.mk @@ -31,6 +31,7 @@ CFLAGS += \ -Wreturn-type \ -Wredundant-decls \ +# -Wmissing-prototypes \ # conversion is too strict for most mcu driver, may be disable sign/int/arith-conversion # -Wconversion diff --git a/hw/bsp/board.c b/hw/bsp/board.c index e3a4be461..5bcdb7f15 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -39,6 +39,9 @@ #define sys_read _read #endif +int sys_write(int fhdl, const char *buf, size_t count) TU_ATTR_USED; +int sys_read(int fhdl, char *buf, size_t count) TU_ATTR_USED; + #if defined(LOGGER_RTT) // Logging with RTT @@ -46,13 +49,13 @@ #if !(defined __SES_ARM) && !(defined __SES_RISCV) && !(defined __CROSSWORKS_ARM) #include "SEGGER_RTT.h" -TU_ATTR_USED int sys_write(int fhdl, const char *buf, size_t count) { +int sys_write(int fhdl, const char *buf, size_t count) { (void) fhdl; SEGGER_RTT_Write(0, (const char *) buf, (int) count); return (int) count; } -TU_ATTR_USED int sys_read(int fhdl, char *buf, size_t count) { +int sys_read(int fhdl, char *buf, size_t count) { (void) fhdl; int rd = (int) SEGGER_RTT_Read(0, buf, count); return (rd > 0) ? rd : -1; @@ -64,7 +67,7 @@ TU_ATTR_USED int sys_read(int fhdl, char *buf, size_t count) { // Logging with SWO for ARM Cortex #include "board_mcu.h" -TU_ATTR_USED int sys_write (int fhdl, const char *buf, size_t count) { +int sys_write (int fhdl, const char *buf, size_t count) { (void) fhdl; uint8_t const* buf8 = (uint8_t const*) buf; @@ -75,7 +78,7 @@ TU_ATTR_USED int sys_write (int fhdl, const char *buf, size_t count) { return (int) count; } -TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) { +int sys_read (int fhdl, char *buf, size_t count) { (void) fhdl; (void) buf; (void) count; @@ -85,12 +88,12 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) { #else // Default logging with on-board UART -TU_ATTR_USED int sys_write (int fhdl, const char *buf, size_t count) { +int sys_write (int fhdl, const char *buf, size_t count) { (void) fhdl; return board_uart_write(buf, (int) count); } -TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) { +int sys_read (int fhdl, char *buf, size_t count) { (void) fhdl; int rd = board_uart_read((uint8_t*) buf, (int) count); return (rd > 0) ? rd : -1; @@ -98,12 +101,12 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) { #endif -//TU_ATTR_USED int _close(int fhdl) { +//int _close(int fhdl) { // (void) fhdl; // return 0; //} -//TU_ATTR_USED int _fstat(int file, struct stat *st) { +//int _fstat(int file, struct stat *st) { // memset(st, 0, sizeof(*st)); // st->st_mode = S_IFCHR; //} diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 272962332..cf6878389 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -67,6 +67,7 @@ function(add_tinyusb TARGET) -Wunused-function -Wreturn-type -Wredundant-decls + -Wmissing-prototypes ) elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 66430feab..cd4183cc3 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -490,13 +490,13 @@ TU_ATTR_WEAK bool tud_audio_feedback_format_correction_cb(uint8_t func_id) { (void) func_id; return CFG_TUD_AUDIO_ENABLE_FEEDBACK_FORMAT_CORRECTION; } -#endif TU_ATTR_WEAK TU_ATTR_FAST_FUNC void tud_audio_feedback_interval_isr(uint8_t func_id, uint32_t frame_number, uint8_t interval_shift) { (void) func_id; (void) frame_number; (void) interval_shift; } +#endif #if CFG_TUD_AUDIO_ENABLE_INTERRUPT_EP TU_ATTR_WEAK void tud_audio_int_done_cb(uint8_t rhport) { diff --git a/src/class/bth/bth_device.c b/src/class/bth/bth_device.c index 5e533cf35..45cbf2d98 100755 --- a/src/class/bth/bth_device.c +++ b/src/class/bth/bth_device.c @@ -52,7 +52,7 @@ typedef struct { typedef struct { TUD_EPBUF_DEF(epout_buf, CFG_TUD_BTH_DATA_EPSIZE); - TUD_EPBUF_TYPE_DEF(hci_cmd, bt_hci_cmd_t); + TUD_EPBUF_TYPE_DEF(bt_hci_cmd_t, hci_cmd); } btd_epbuf_t; //--------------------------------------------------------------------+ diff --git a/src/class/net/ncm_device.c b/src/class/net/ncm_device.c index c97c66a4e..4e6088340 100644 --- a/src/class/net/ncm_device.c +++ b/src/class/net/ncm_device.c @@ -118,14 +118,14 @@ typedef struct { typedef struct { struct { - TUD_EPBUF_TYPE_DEF(ntb, recv_ntb_t); + TUD_EPBUF_TYPE_DEF(recv_ntb_t, ntb); } recv[RECV_NTB_N]; struct { - TUD_EPBUF_TYPE_DEF(ntb, xmit_ntb_t); + TUD_EPBUF_TYPE_DEF(xmit_ntb_t, ntb); } xmit[XMIT_NTB_N]; - TUD_EPBUF_TYPE_DEF(epnotif, ncm_notify_t); + TUD_EPBUF_TYPE_DEF(ncm_notify_t, epnotif); } ncm_epbuf_t; static ncm_interface_t ncm_interface; @@ -748,7 +748,7 @@ void tud_network_recv_renew(void) { /** * Same as tud_network_recv_renew() but knows \a rhport */ -void tud_network_recv_renew_r(uint8_t rhport) { +static void tud_network_recv_renew_r(uint8_t rhport) { TU_LOG_DRV("tud_network_recv_renew_r(%d)\n", rhport); ncm_interface.rhport = rhport; diff --git a/src/class/usbtmc/usbtmc_device.c b/src/class/usbtmc/usbtmc_device.c index 37634c38e..abde9679f 100644 --- a/src/class/usbtmc/usbtmc_device.c +++ b/src/class/usbtmc/usbtmc_device.c @@ -180,7 +180,7 @@ osal_mutex_t usbtmcLock; #define criticalEnter() do { (void) osal_mutex_lock(usbtmcLock,OSAL_TIMEOUT_WAIT_FOREVER); } while (0) #define criticalLeave() do { (void) osal_mutex_unlock(usbtmcLock); } while (0) -bool atomicChangeState(usbtmcd_state_enum expectedState, usbtmcd_state_enum newState) +static bool atomicChangeState(usbtmcd_state_enum expectedState, usbtmcd_state_enum newState) { bool ret = true; criticalEnter(); diff --git a/src/class/video/video_device.h b/src/class/video/video_device.h index 92930c013..648a221d5 100644 --- a/src/class/video/video_device.h +++ b/src/class/video/video_device.h @@ -40,6 +40,8 @@ extern "C" { // CFG_TUD_VIDEO > 1 //--------------------------------------------------------------------+ +bool tud_video_n_connected(uint_fast8_t ctl_idx); + /** Return true if streaming * * @param[in] ctl_idx Destination control interface index diff --git a/src/common/tusb_types.h b/src/common/tusb_types.h index 533c1bcea..9e4d9380c 100644 --- a/src/common/tusb_types.h +++ b/src/common/tusb_types.h @@ -47,7 +47,7 @@ } // Declare an endpoint buffer with a type -#define TUD_EPBUF_TYPE_DEF(_name, _type) \ +#define TUD_EPBUF_TYPE_DEF(_type, _name) \ union { \ CFG_TUD_MEM_ALIGN _type _name; \ uint8_t _name##_dcache_padding[TUD_EPBUF_DCACHE_SIZE(sizeof(_type))]; \ diff --git a/src/portable/dialog/da146xx/dcd_da146xx.c b/src/portable/dialog/da146xx/dcd_da146xx.c index 887f59588..56ecb7575 100644 --- a/src/portable/dialog/da146xx/dcd_da146xx.c +++ b/src/portable/dialog/da146xx/dcd_da146xx.c @@ -896,6 +896,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool is_in_isr(void) return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0; } +void tusb_vbus_changed(bool present); void tusb_vbus_changed(bool present) { if (present && !_dcd.vbus_present) diff --git a/src/portable/microchip/samd/dcd_samd.c b/src/portable/microchip/samd/dcd_samd.c index 0c96f6ac4..357aa1549 100644 --- a/src/portable/microchip/samd/dcd_samd.c +++ b/src/portable/microchip/samd/dcd_samd.c @@ -335,7 +335,7 @@ void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr) //--------------------------------------------------------------------+ // Interrupt Handler //--------------------------------------------------------------------+ -void maybe_transfer_complete(void) { +static void maybe_transfer_complete(void) { uint32_t epints = USB->DEVICE.EPINTSMRY.reg; for (uint8_t epnum = 0; epnum < USB_EPT_NUM; epnum++) { diff --git a/src/portable/microchip/samg/dcd_samg.c b/src/portable/microchip/samg/dcd_samg.c index c88b31514..a5c768839 100644 --- a/src/portable/microchip/samg/dcd_samg.c +++ b/src/portable/microchip/samg/dcd_samg.c @@ -52,37 +52,31 @@ typedef struct // Endpoint 0-5, each can only be either OUT or In xfer_desc_t _dcd_xfer[EP_COUNT]; -void xfer_epsize_set(xfer_desc_t* xfer, uint16_t epsize) -{ +TU_ATTR_ALWAYS_INLINE static inline void xfer_epsize_set(xfer_desc_t* xfer, uint16_t epsize) { xfer->epsize = epsize; } -void xfer_begin(xfer_desc_t* xfer, uint8_t * buffer, uint16_t total_bytes) -{ +TU_ATTR_ALWAYS_INLINE static inline void xfer_begin(xfer_desc_t* xfer, uint8_t * buffer, uint16_t total_bytes) { xfer->buffer = buffer; // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API xfer->total_len = total_bytes; xfer->actual_len = 0; } -void xfer_end(xfer_desc_t* xfer) -{ +TU_ATTR_ALWAYS_INLINE static inline void xfer_end(xfer_desc_t* xfer) { xfer->buffer = NULL; // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API xfer->total_len = 0; xfer->actual_len = 0; } -uint16_t xfer_packet_len(xfer_desc_t* xfer) -{ +TU_ATTR_ALWAYS_INLINE static inline uint16_t xfer_packet_len(xfer_desc_t* xfer) { // also cover zero-length packet return tu_min16(xfer->total_len - xfer->actual_len, xfer->epsize); } -void xfer_packet_done(xfer_desc_t* xfer) -{ +TU_ATTR_ALWAYS_INLINE static inline void xfer_packet_done(xfer_desc_t* xfer) { uint16_t const xact_len = xfer_packet_len(xfer); - xfer->buffer += xact_len; xfer->actual_len += xact_len; } @@ -90,19 +84,15 @@ void xfer_packet_done(xfer_desc_t* xfer) //------------- Transaction helpers -------------// // Write data to EP FIFO, return number of written bytes -static void xact_ep_write(uint8_t epnum, uint8_t* buffer, uint16_t xact_len) -{ - for(uint16_t i=0; iUDP_FDR[epnum] = (uint32_t) buffer[i]; } } // Read data from EP FIFO -static void xact_ep_read(uint8_t epnum, uint8_t* buffer, uint16_t xact_len) -{ - for(uint16_t i=0; iUDP_FDR[epnum]; } } @@ -112,24 +102,24 @@ static void xact_ep_read(uint8_t epnum, uint8_t* buffer, uint16_t xact_len) #define CSR_NO_EFFECT_1_ALL (UDP_CSR_RX_DATA_BK0 | UDP_CSR_RX_DATA_BK1 | UDP_CSR_STALLSENT | UDP_CSR_RXSETUP | UDP_CSR_TXCOMP) // Per Specs: CSR need synchronization each write -static inline void csr_write(uint8_t epnum, uint32_t value) -{ +TU_ATTR_ALWAYS_INLINE static inline void csr_write(uint8_t epnum, uint32_t value) { uint32_t const csr = value; UDP->UDP_CSR[epnum] = csr; volatile uint32_t nop_count; - for (nop_count = 0; nop_count < 20; nop_count ++) __NOP(); + for (nop_count = 0; nop_count < 20; nop_count ++) { + __NOP(); + } } // Per Specs: CSR need synchronization each write -static inline void csr_set(uint8_t epnum, uint32_t mask) +TU_ATTR_ALWAYS_INLINE static inline void csr_set(uint8_t epnum, uint32_t mask) { csr_write(epnum, UDP->UDP_CSR[epnum] | CSR_NO_EFFECT_1_ALL | mask); } // Per Specs: CSR need synchronization each write -static inline void csr_clear(uint8_t epnum, uint32_t mask) -{ +TU_ATTR_ALWAYS_INLINE static inline void csr_clear(uint8_t epnum, uint32_t mask) { csr_write(epnum, (UDP->UDP_CSR[epnum] | CSR_NO_EFFECT_1_ALL) & ~mask); } diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index 3f53ee26e..5bfedae17 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -530,7 +530,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { /*------------------------------------------------------------------*/ /* Interrupt Handler *------------------------------------------------------------------*/ -void bus_reset(void) { +static void bus_reset(void) { // 6.35.6 USB controller automatically disabled all endpoints (except control) NRF_USBD->EPOUTEN = 1UL; NRF_USBD->EPINEN = 1UL; @@ -901,6 +901,7 @@ static void hfclk_disable(void) { // Therefore this function must be called to handle USB power event by // - nrfx_power_usbevt_init() : if Softdevice is not used or enabled // - SoftDevice SOC event : if SD is used and enabled +void tusb_hal_nrf_power_event(uint32_t event); void tusb_hal_nrf_power_event(uint32_t event) { // Value is chosen to be as same as NRFX_POWER_USB_EVT_* in nrfx_power.h enum { diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c index f5ca73c18..056dbf40b 100644 --- a/src/portable/nxp/khci/hcd_khci.c +++ b/src/portable/nxp/khci/hcd_khci.c @@ -140,7 +140,7 @@ typedef struct CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(512) static hcd_data_t _hcd; //CFG_TUH_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t _rx_buf[1024]; -int find_pipe(uint8_t dev_addr, uint8_t ep_addr) +static int find_pipe(uint8_t dev_addr, uint8_t ep_addr) { /* Find the target pipe */ int num; diff --git a/src/portable/nxp/lpc17_40/hcd_lpc17_40.c b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c index 372dcf51f..090d1ba69 100644 --- a/src/portable/nxp/lpc17_40/hcd_lpc17_40.c +++ b/src/portable/nxp/lpc17_40/hcd_lpc17_40.c @@ -30,6 +30,7 @@ (CFG_TUSB_MCU == OPT_MCU_LPC175X_6X || CFG_TUSB_MCU == OPT_MCU_LPC177X_8X || CFG_TUSB_MCU == OPT_MCU_LPC40XX) #include "chip.h" +#include "host/hcd.h" void hcd_int_enable(uint8_t rhport) { diff --git a/src/portable/renesas/rusb2/rusb2_common.c b/src/portable/renesas/rusb2/rusb2_common.c index 850060777..72e65736b 100644 --- a/src/portable/renesas/rusb2/rusb2_common.c +++ b/src/portable/renesas/rusb2/rusb2_common.c @@ -45,6 +45,7 @@ rusb2_controller_t rusb2_controller[] = { }; // Application API for setting IRQ number. May throw warnings for missing prototypes. +void tusb_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum); void tusb_rusb2_set_irqnum(uint8_t rhport, int32_t irqnum) { rusb2_controller[rhport].irqnum = irqnum; } -- cgit v1.3.1 From 568c785da10e35eb8d5298a4cf63854cbf9dbfd4 Mon Sep 17 00:00:00 2001 From: "David (Pololu)" Date: Tue, 8 Oct 2024 12:30:44 -0700 Subject: Add support for the STM32C0 and the NUCLEO-C071RB. --- README.rst | 2 +- docs/reference/supported.rst | 2 +- hw/bsp/board_mcu.h | 3 + .../boards/stm32c071nucleo/STM32C071RBTX_FLASH.ld | 187 ++++++++++++++ hw/bsp/stm32c0/boards/stm32c071nucleo/board.cmake | 10 + hw/bsp/stm32c0/boards/stm32c071nucleo/board.h | 58 +++++ hw/bsp/stm32c0/boards/stm32c071nucleo/board.mk | 13 + hw/bsp/stm32c0/family.c | 199 +++++++++++++++ hw/bsp/stm32c0/family.cmake | 118 +++++++++ hw/bsp/stm32c0/family.mk | 52 ++++ hw/bsp/stm32c0/stm32c0xx_hal_conf.h | 284 +++++++++++++++++++++ src/common/tusb_mcu.h | 5 + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 1 + src/portable/st/stm32_fsdev/fsdev_stm32.h | 16 ++ src/tusb_option.h | 1 + tools/get_deps.py | 18 +- 16 files changed, 961 insertions(+), 8 deletions(-) create mode 100644 hw/bsp/stm32c0/boards/stm32c071nucleo/STM32C071RBTX_FLASH.ld create mode 100644 hw/bsp/stm32c0/boards/stm32c071nucleo/board.cmake create mode 100644 hw/bsp/stm32c0/boards/stm32c071nucleo/board.h create mode 100644 hw/bsp/stm32c0/boards/stm32c071nucleo/board.mk create mode 100644 hw/bsp/stm32c0/family.c create mode 100644 hw/bsp/stm32c0/family.cmake create mode 100644 hw/bsp/stm32c0/family.mk create mode 100644 hw/bsp/stm32c0/stm32c0xx_hal_conf.h (limited to 'src/portable') diff --git a/README.rst b/README.rst index 502115c25..db36cad3b 100644 --- a/README.rst +++ b/README.rst @@ -153,7 +153,7 @@ Following CPUs are supported, check out `Supported Devices`_ for comprehensive l +--------------+------------------------------------------------------------+ | Sony | CXD56 | +--------------+------------------------------------------------------------+ -| ST STM32 | F0, F1, F2, F3, F4, F7, G0, G4, H5, H7, | +| ST STM32 | C0, F0, F1, F2, F3, F4, F7, G0, G4, H5, H7, | | | | | | L0, L1, L4, L4+, L5, U5, WB | +--------------+------------------------------------------------------------+ diff --git a/docs/reference/supported.rst b/docs/reference/supported.rst index da2431415..cbd6c4786 100644 --- a/docs/reference/supported.rst +++ b/docs/reference/supported.rst @@ -97,7 +97,7 @@ Supported MCUs | +-----------------------------+--------+------+-----------+------------------------+-------------------+ | | F3 | âś” | âś– | âś– | stm32_fsdev | | | +-----------------------------+--------+------+-----------+------------------------+-------------------+ -| | G0, H5 | âś” | âś– | âś– | stm32_fsdev | | +| | C0, G0, H5 | âś” | | âś– | stm32_fsdev | | | +-----------------------------+--------+------+-----------+------------------------+-------------------+ | | G4 | âś” | âś– | âś– | stm32_fsdev | | | +-----------------------------+--------+------+-----------+------------------------+-------------------+ diff --git a/hw/bsp/board_mcu.h b/hw/bsp/board_mcu.h index d3a33cf36..e720cd747 100644 --- a/hw/bsp/board_mcu.h +++ b/hw/bsp/board_mcu.h @@ -107,6 +107,9 @@ #elif CFG_TUSB_MCU == OPT_MCU_STM32G0 #include "stm32g0xx.h" +#elif CFG_TUSB_MCU == OPT_MCU_STM32C0 + #include "stm32c0xx.h" + #elif CFG_TUSB_MCU == OPT_MCU_CXD56 // no header needed diff --git a/hw/bsp/stm32c0/boards/stm32c071nucleo/STM32C071RBTX_FLASH.ld b/hw/bsp/stm32c0/boards/stm32c071nucleo/STM32C071RBTX_FLASH.ld new file mode 100644 index 000000000..bd2968889 --- /dev/null +++ b/hw/bsp/stm32c0/boards/stm32c071nucleo/STM32C071RBTX_FLASH.ld @@ -0,0 +1,187 @@ +/* +****************************************************************************** +** +** @file : LinkerScript.ld +** +** @author : Auto-generated by STM32CubeIDE +** +** Abstract : Linker script for NUCLEO-C071RB Board embedding STM32C071RBTx Device from stm32c0 series +** 128KBytes FLASH +** 24KBytes RAM +** +** Set heap size, stack size and stack location according +** to application requirements. +** +** Set memory bank area and size if external memory is used +** +** Target : STMicroelectronics STM32 +** +** Distribution: The file is distributed as is, without any warranty +** of any kind. +** +****************************************************************************** +** @attention +** +** Copyright (c) 2024 STMicroelectronics. +** All rights reserved. +** +** This software is licensed under terms that can be found in the LICENSE file +** in the root directory of this software component. +** If no LICENSE file comes with this software, it is provided AS-IS. +** +****************************************************************************** +*/ + +/* Entry Point */ +ENTRY(Reset_Handler) + +/* Highest address of the user mode stack */ +_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ + +_Min_Heap_Size = 0x200; /* required amount of heap */ +_Min_Stack_Size = 0x400; /* required amount of stack */ + +/* Memories definition */ +MEMORY +{ + RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 24K + FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 128K +} + +/* Sections */ +SECTIONS +{ + /* The startup code into "FLASH" Rom type memory */ + .isr_vector : + { + . = ALIGN(4); + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + } >FLASH + + /* The program code and other data into "FLASH" Rom type memory */ + .text : + { + . = ALIGN(4); + *(.text) /* .text sections (code) */ + *(.text*) /* .text* sections (code) */ + *(.glue_7) /* glue arm to thumb code */ + *(.glue_7t) /* glue thumb to arm code */ + *(.eh_frame) + + KEEP (*(.init)) + KEEP (*(.fini)) + + . = ALIGN(4); + _etext = .; /* define a global symbols at end of code */ + } >FLASH + + /* Constant data into "FLASH" Rom type memory */ + .rodata : + { + . = ALIGN(4); + *(.rodata) /* .rodata sections (constants, strings, etc.) */ + *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ + . = ALIGN(4); + } >FLASH + + .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) + . = ALIGN(4); + } >FLASH + + .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + __exidx_start = .; + *(.ARM.exidx*) + __exidx_end = .; + . = ALIGN(4); + } >FLASH + + .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array*)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array*)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */ + { + . = ALIGN(4); + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array*)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + /* Used by the startup to initialize data */ + _sidata = LOADADDR(.data); + + /* Initialized data sections into "RAM" Ram type memory */ + .data : + { + . = ALIGN(4); + _sdata = .; /* create a global symbol at data start */ + *(.data) /* .data sections */ + *(.data*) /* .data* sections */ + *(.RamFunc) /* .RamFunc sections */ + *(.RamFunc*) /* .RamFunc* sections */ + + . = ALIGN(4); + _edata = .; /* define a global symbol at data end */ + + } >RAM AT> FLASH + + /* Uninitialized data section into "RAM" Ram type memory */ + . = ALIGN(4); + .bss : + { + /* This is used by the startup in order to initialize the .bss section */ + _sbss = .; /* define a global symbol at bss start */ + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + + . = ALIGN(4); + _ebss = .; /* define a global symbol at bss end */ + __bss_end__ = _ebss; + } >RAM + + /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ + ._user_heap_stack : + { + . = ALIGN(8); + PROVIDE ( end = . ); + PROVIDE ( _end = . ); + . = . + _Min_Heap_Size; + . = . + _Min_Stack_Size; + . = ALIGN(8); + } >RAM + + /* Remove information from the compiler libraries */ + /DISCARD/ : + { + libc.a ( * ) + libm.a ( * ) + libgcc.a ( * ) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } +} diff --git a/hw/bsp/stm32c0/boards/stm32c071nucleo/board.cmake b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.cmake new file mode 100644 index 000000000..2a319a73c --- /dev/null +++ b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.cmake @@ -0,0 +1,10 @@ +set(MCU_VARIANT stm32c071xx) +set(JLINK_DEVICE stm32c071rb) + +set(LD_FILE_GNU ${CMAKE_CURRENT_LIST_DIR}/STM32C071RBTx_FLASH.ld) + +function(update_board TARGET) + target_compile_definitions(${TARGET} PUBLIC + STM32C071xx + ) +endfunction() diff --git a/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h new file mode 100644 index 000000000..f08762736 --- /dev/null +++ b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.h @@ -0,0 +1,58 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2020, Ha Thach (tinyusb.org) + * Copyright (c) 2023, HiFiPhile + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#ifndef BOARD_H_ +#define BOARD_H_ + +// Green LED +#define GREEN_LED_PORT GPIOA +#define GREEN_LED_PIN GPIO_PIN_5 +#define GREEN_LED_STATE_ON 1 + +// Blue LED +#define BLUE_LED_PORT GPIOC +#define BLUE_LED_PIN GPIO_PIN_9 +#define BLUE_LED_STATE_ON 0 + +// Generic LED +#define LED_PORT GREEN_LED_PORT +#define LED_PIN GREEN_LED_PIN +#define LED_STATE_ON GREEN_LED_STATE_ON + +// Button +#define BUTTON_PORT GPIOC +#define BUTTON_PIN GPIO_PIN_13 +#define BUTTON_STATE_ACTIVE 0 + +// Enable UART serial communication with the ST-Link +#define UART_DEV USART2 +#define UART_GPIO_PORT GPIOA +#define UART_GPIO_AF GPIO_AF1_USART2 +#define UART_TX_PIN GPIO_PIN_2 +#define UART_RX_PIN GPIO_PIN_3 + +#endif /* BOARD_H_ */ diff --git a/hw/bsp/stm32c0/boards/stm32c071nucleo/board.mk b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.mk new file mode 100644 index 000000000..67a9b59a8 --- /dev/null +++ b/hw/bsp/stm32c0/boards/stm32c071nucleo/board.mk @@ -0,0 +1,13 @@ +CFLAGS += \ + -DSTM32C071xx + +# GCC +SRC_S_GCC += $(ST_CMSIS)/Source/Templates/gcc/startup_stm32c071xx.s +LD_FILE_GCC = $(BOARD_PATH)/STM32C071RBTx_FLASH.ld + +# IAR +SRC_S_IAR += $(ST_CMSIS)/Source/Templates/iar/startup_stm32c071xx.s +LD_FILE_IAR = $(ST_CMSIS)/Source/Templates/iar/linker/stm32c071xx_flash.icf + +# For flash-jlink target +JLINK_DEVICE = stm32c071rb diff --git a/hw/bsp/stm32c0/family.c b/hw/bsp/stm32c0/family.c new file mode 100644 index 000000000..dba6a8af1 --- /dev/null +++ b/hw/bsp/stm32c0/family.c @@ -0,0 +1,199 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2019 Ha Thach (tinyusb.org) + * Copyright (c) 2023 HiFiPhile + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "stm32c0xx_hal.h" +#include "bsp/board_api.h" +#include "board.h" + +//--------------------------------------------------------------------+ +// Forward USB interrupt events to TinyUSB IRQ Handler +//--------------------------------------------------------------------+ +void USB_DRD_FS_IRQHandler(void) { + tud_int_handler(0); +} + +// Startup code generated by STM32CubeIDE uses USB_IRQHandler, while +// stm32c071xx.s from cmsis_device_c0 uses USB_DRD_FS_IRQHandler. +void USB_IRQHandler(void) { + USB_DRD_FS_IRQHandler(); +} + +//--------------------------------------------------------------------+ +// MACRO TYPEDEF CONSTANT ENUM +//--------------------------------------------------------------------+ +UART_HandleTypeDef UartHandle; + +void board_init(void) { + HAL_Init(); + + // Enable the HSIUSB48 48 MHz oscillator. + RCC->CR |= RCC_CR_HSIUSB48ON; + + // Wait for HSIUSB48 to be ready. + while (!(RCC->CR & RCC_CR_HSIUSB48RDY)) { } + + // Change the SYSCLK source to HSIUSB48. + RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_SYSCLKSOURCE_HSIUSB48; + + // Wait for the SYSCLK source to change. + while ((RCC->CFGR & RCC_CFGR_SWS) >> RCC_CFGR_SWS_Pos != RCC_SYSCLKSOURCE_HSIUSB48) { } + + // Disable HSI48 to save power. + RCC->CR &= ~RCC_CR_HSION; + + // Enable peripheral clocks. + RCC->APBENR1 = RCC_APBENR1_USBEN | RCC_APBENR1_CRSEN | RCC_APBENR1_USART2EN; + RCC->APBENR2 = RCC_APBENR2_USART1EN; + + // Enable all GPIO clocks. + RCC->IOPENR = 0x2F; + + // Turn on CRS to make the HSIUSB48 clock more precise when USB is connected. + CRS->CR |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN; + +#if CFG_TUSB_OS == OPT_OS_NONE + // 1ms tick timer + SysTick_Config(SystemCoreClock / 1000); +#elif CFG_TUSB_OS == OPT_OS_FREERTOS + // Explicitly disable systick to prevent its ISR runs before scheduler start + SysTick->CTRL &= ~1U; + + // If freeRTOS is used, IRQ priority is limit by max syscall ( smaller is higher ) + NVIC_SetPriority(USB_DRD_FS_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY); +#endif + + // LED + { + GPIO_InitTypeDef gpio_init = { 0 }; + gpio_init.Pin = LED_PIN; + gpio_init.Mode = GPIO_MODE_OUTPUT_PP; + HAL_GPIO_Init(LED_PORT, &gpio_init); + board_led_write(false); + } + + // Button + { + GPIO_InitTypeDef gpio_init = { 0 }; + gpio_init.Pin = BUTTON_PIN; + gpio_init.Mode = GPIO_MODE_INPUT; + gpio_init.Pull = BUTTON_STATE_ACTIVE ? GPIO_PULLDOWN : GPIO_PULLUP; + HAL_GPIO_Init(BUTTON_PORT, &gpio_init); + } + +#ifdef UART_DEV + // UART + { + GPIO_InitTypeDef gpio_init = { 0 }; + gpio_init.Pin = UART_TX_PIN | UART_RX_PIN; + gpio_init.Mode = GPIO_MODE_AF_PP; + gpio_init.Pull = GPIO_PULLUP; + gpio_init.Speed = GPIO_SPEED_FREQ_HIGH; + gpio_init.Alternate = UART_GPIO_AF; + HAL_GPIO_Init(UART_GPIO_PORT, &gpio_init); + } + + UartHandle = (UART_HandleTypeDef){ + .Instance = UART_DEV, + .Init.BaudRate = CFG_BOARD_UART_BAUDRATE, + .Init.WordLength = UART_WORDLENGTH_8B, + .Init.StopBits = UART_STOPBITS_1, + .Init.Parity = UART_PARITY_NONE, + .Init.HwFlowCtl = UART_HWCONTROL_NONE, + .Init.Mode = UART_MODE_TX_RX, + .Init.OverSampling = UART_OVERSAMPLING_16, + .AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT + }; + HAL_UART_Init(&UartHandle); +#endif +} + +//--------------------------------------------------------------------+ +// Board porting API +//--------------------------------------------------------------------+ + +void board_led_write(bool state) { + GPIO_PinState pin_state = (GPIO_PinState)(state ? LED_STATE_ON : (1 - LED_STATE_ON)); + HAL_GPIO_WritePin(LED_PORT, LED_PIN, pin_state); +} + +uint32_t board_button_read(void) { + return BUTTON_STATE_ACTIVE == HAL_GPIO_ReadPin(BUTTON_PORT, BUTTON_PIN); +} + +size_t board_get_unique_id(uint8_t id[], size_t max_len) { + (void) max_len; + volatile uint32_t * stm32_uuid = (volatile uint32_t *) UID_BASE; + uint32_t* id32 = (uint32_t*) (uintptr_t) id; + uint8_t const len = 12; + + id32[0] = stm32_uuid[0]; + id32[1] = stm32_uuid[1]; + id32[2] = stm32_uuid[2]; + + return len; +} + +int board_uart_read(uint8_t *buf, int len) { + (void) buf; + (void) len; + return 0; +} + +int board_uart_write(void const *buf, int len) { +#ifdef UART_DEV + HAL_UART_Transmit(&UartHandle, (uint8_t*)(uintptr_t) buf, len, 0xffff); + return len; +#else + (void) buf; + (void) len; + (void) UartHandle; + return 0; +#endif +} + +#if CFG_TUSB_OS == OPT_OS_NONE +volatile uint32_t system_ticks = 0; + +void SysTick_Handler(void) { + system_ticks++; + HAL_IncTick(); +} + +uint32_t board_millis(void) { + return system_ticks; +} +#endif + +void HardFault_Handler(void) { + __asm("BKPT #0\n"); +} + +// Required by __libc_init_array in startup code if we are compiling using +// -nostdlib/-nostartfiles. +void _init(void) { + +} diff --git a/hw/bsp/stm32c0/family.cmake b/hw/bsp/stm32c0/family.cmake new file mode 100644 index 000000000..ebfb532c7 --- /dev/null +++ b/hw/bsp/stm32c0/family.cmake @@ -0,0 +1,118 @@ +include_guard() + +set(ST_FAMILY c0) +set(ST_PREFIX stm32${ST_FAMILY}xx) + +set(ST_HAL_DRIVER ${TOP}/hw/mcu/st/stm32${ST_FAMILY}xx_hal_driver) +set(ST_CMSIS ${TOP}/hw/mcu/st/cmsis_device_${ST_FAMILY}) +set(CMSIS_5 ${TOP}/lib/CMSIS_5) + +# include board specific +include(${CMAKE_CURRENT_LIST_DIR}/boards/${BOARD}/board.cmake) + +# toolchain set up +set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus CACHE INTERNAL "System Processor") +set(CMAKE_TOOLCHAIN_FILE ${TOP}/examples/build_system/cmake/toolchain/arm_${TOOLCHAIN}.cmake) + +set(FAMILY_MCUS STM32C0 CACHE INTERNAL "") +set(OPENOCD_OPTION "-f interface/stlink.cfg -f target/stm32c0x.cfg") + +#------------------------------------ +# BOARD_TARGET +#------------------------------------ +# only need to be built ONCE for all examples +function(add_board_target BOARD_TARGET) + if (TARGET ${BOARD_TARGET}) + return() + endif () + + # Startup & Linker script + set(STARTUP_FILE_GNU ${ST_CMSIS}/Source/Templates/gcc/startup_${MCU_VARIANT}.s) + set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) + set(STARTUP_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/startup_${MCU_VARIANT}.s) + + set(LD_FILE_Clang ${LD_FILE_GNU}) + set(LD_FILE_IAR ${ST_CMSIS}/Source/Templates/iar/linker/${MCU_VARIANT}_flash.icf) + + add_library(${BOARD_TARGET} STATIC + ${ST_CMSIS}/Source/Templates/system_${ST_PREFIX}.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_cortex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_pwr_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_rcc_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_gpio.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_uart_ex.c + ${ST_HAL_DRIVER}/Src/${ST_PREFIX}_hal_dma.c + ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} + ) + target_include_directories(${BOARD_TARGET} PUBLIC + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMSIS_5}/CMSIS/Core/Include + ${ST_CMSIS}/Include + ${ST_HAL_DRIVER}/Inc + ) +# target_compile_options(${BOARD_TARGET} PUBLIC) +# target_compile_definitions(${BOARD_TARGET} PUBLIC) + + update_board(${BOARD_TARGET}) + + if (CMAKE_C_COMPILER_ID STREQUAL "GNU") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_GNU}" + -nostartfiles + --specs=nosys.specs --specs=nano.specs + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--script=${LD_FILE_Clang}" + ) + elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") + target_link_options(${BOARD_TARGET} PUBLIC + "LINKER:--config=${LD_FILE_IAR}" + ) + endif () +endfunction() + + +#------------------------------------ +# Functions +#------------------------------------ +function(family_configure_example TARGET RTOS) + family_configure_common(${TARGET} ${RTOS}) + + # Board target + add_board_target(board_${BOARD}) + + #---------- Port Specific ---------- + # These files are built for each example since it depends on example's tusb_config.h + target_sources(${TARGET} PUBLIC + # BSP + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/family.c + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../board.c + ) + target_include_directories(${TARGET} PUBLIC + # family, hw, board + ${CMAKE_CURRENT_FUNCTION_LIST_DIR} + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/../../ + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/boards/${BOARD} + ) + + # Add TinyUSB target and port source + family_add_tinyusb(${TARGET} OPT_MCU_STM32C0 ${RTOS}) + target_sources(${TARGET}-tinyusb PUBLIC + ${TOP}/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c + ${TOP}/src/portable/st/typec/typec_stm32.c + ) + target_link_libraries(${TARGET}-tinyusb PUBLIC board_${BOARD}) + + # Link dependencies + target_link_libraries(${TARGET} PUBLIC board_${BOARD} ${TARGET}-tinyusb) + + # Flashing + family_flash_jlink(${TARGET}) + family_flash_stlink(${TARGET}) + #family_flash_openocd(${TARGET}) +endfunction() diff --git a/hw/bsp/stm32c0/family.mk b/hw/bsp/stm32c0/family.mk new file mode 100644 index 000000000..2380d76c3 --- /dev/null +++ b/hw/bsp/stm32c0/family.mk @@ -0,0 +1,52 @@ +ST_FAMILY = c0 +DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver + +ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY) +ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver + +include $(TOP)/$(BOARD_PATH)/board.mk +CPU_CORE ?= cortex-m0plus + +# -------------- +# Compiler Flags +# -------------- +CFLAGS += \ + -DCFG_TUSB_MCU=OPT_MCU_STM32C0 + +# GCC Flags +CFLAGS_GCC += \ + -flto \ + +# suppress warning caused by vendor mcu driver +CFLAGS_GCC += -Wno-error=cast-align -Wno-error=unused-parameter + +LDFLAGS_GCC += \ + -nostdlib -nostartfiles \ + --specs=nosys.specs --specs=nano.specs + +# ----------------- +# Sources & Include +# ----------------- + +SRC_C += \ + src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ + $(ST_CMSIS)/Source/Templates/system_stm32$(ST_FAMILY)xx.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_cortex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_pwr_ex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_rcc_ex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_uart_ex.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_gpio.c \ + $(ST_HAL_DRIVER)/Src/stm32$(ST_FAMILY)xx_hal_dma.c + +INC += \ + $(TOP)/$(BOARD_PATH) \ + $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ + $(TOP)/$(ST_CMSIS)/Include \ + $(TOP)/$(ST_HAL_DRIVER)/Inc + +# flash target using on-board stlink +flash: flash-stlink diff --git a/hw/bsp/stm32c0/stm32c0xx_hal_conf.h b/hw/bsp/stm32c0/stm32c0xx_hal_conf.h new file mode 100644 index 000000000..678b6ee0d --- /dev/null +++ b/hw/bsp/stm32c0/stm32c0xx_hal_conf.h @@ -0,0 +1,284 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file stm32c0xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration template file. + * This file should be copied to the application folder and renamed + * to stm32c0xx_hal_conf.h. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32C0xx_HAL_CONF_H +#define STM32C0xx_HAL_CONF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#define HAL_MODULE_ENABLED +/* #define HAL_ADC_MODULE_ENABLED */ +/* #define HAL_CRC_MODULE_ENABLED */ +/* #define HAL_CRYP_MODULE_ENABLED */ +/* #define HAL_I2C_MODULE_ENABLED */ +/* #define HAL_I2S_MODULE_ENABLED */ +/* #define HAL_IWDG_MODULE_ENABLED */ +/* #define HAL_IRDA_MODULE_ENABLED */ +/* #define HAL_PCD_MODULE_ENABLED */ +/* #define HAL_HCD_MODULE_ENABLED */ +/* #define HAL_RNG_MODULE_ENABLED */ +/* #define HAL_RTC_MODULE_ENABLED */ +/* #define HAL_SMARTCARD_MODULE_ENABLED */ +/* #define HAL_SMBUS_MODULE_ENABLED */ +/* #define HAL_SPI_MODULE_ENABLED */ +/* #define HAL_TIM_MODULE_ENABLED */ +/* #define HAL_USART_MODULE_ENABLED */ +/* #define HAL_WWDG_MODULE_ENABLED */ +#define HAL_GPIO_MODULE_ENABLED +#define HAL_EXTI_MODULE_ENABLED +#define HAL_DMA_MODULE_ENABLED +#define HAL_RCC_MODULE_ENABLED +#define HAL_FLASH_MODULE_ENABLED +#define HAL_PWR_MODULE_ENABLED +#define HAL_CORTEX_MODULE_ENABLED +#define HAL_UART_MODULE_ENABLED + +/* ########################## Register Callbacks selection ############################## */ +/** + * @brief Set below the peripheral configuration to "1U" to add the support + * of HAL callback registration/unregistration feature for the HAL + * driver(s). This allows user application to provide specific callback + * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting + * the default weak callback functions (see each stm32c0xx_hal_ppp.h file + * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef + * for each PPP peripheral). + */ +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Oscillator Values adaptation ####################*/ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) +#define HSE_STARTUP_TIMEOUT (100UL) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) +#define HSI_VALUE (48000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) +#define LSI_VALUE (32000UL) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz +The real value may vary depending on the variations +in voltage and temperature.*/ +#if !defined (LSI_STARTUP_TIME) +#define LSI_STARTUP_TIME 130UL /*!< Time out for LSI start up, in ms */ +#endif /* LSI_STARTUP_TIME */ +/** + * @brief External Low Speed oscillator (LSE) value. + * This value is used by the UART, RTC HAL module to compute the system frequency + */ +#if !defined (LSE_VALUE) +#define LSE_VALUE (32768UL) /*!< Value of the External oscillator in Hz*/ +#endif /* LSE_VALUE */ + +#if !defined (LSE_STARTUP_TIMEOUT) +#define LSE_STARTUP_TIMEOUT (5000UL) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S1 peripheral + * This value is used by the RCC HAL module to compute the I2S1 clock source + * frequency. + */ +#if !defined (EXTERNAL_I2S1_CLOCK_VALUE) +#define EXTERNAL_I2S1_CLOCK_VALUE (12288000UL) /*!< Value of the I2S1 External clock source in Hz*/ +#endif /* EXTERNAL_I2S1_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY 3U /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 0U +#define INSTRUCTION_CACHE_ENABLE 1U + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1U */ + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include modules header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32c0xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32c0xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32c0xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32c0xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32c0xx_hal_adc.h" + #include "stm32c0xx_hal_adc_ex.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32c0xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED +#include "stm32c0xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32c0xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32c0xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32c0xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32c0xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32c0xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32c0xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32c0xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32c0xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32c0xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32c0xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32c0xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32c0xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32c0xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32c0xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32c0xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32c0xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for functions parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +void assert_failed(uint8_t *file, uint32_t line); +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32C0xx_HAL_CONF_H */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index d43e5f2ba..0c64c041c 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -238,6 +238,11 @@ #define TUP_USBIP_FSDEV_STM32 #define TUP_DCD_ENDPOINT_MAX 8 +#elif TU_CHECK_MCU(OPT_MCU_STM32C0) + #define TUP_USBIP_FSDEV + #define TUP_USBIP_FSDEV_STM32 + #define TUP_DCD_ENDPOINT_MAX 8 + #elif TU_CHECK_MCU(OPT_MCU_STM32L0, OPT_MCU_STM32L1) #define TUP_USBIP_FSDEV #define TUP_USBIP_FSDEV_STM32 diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index d921429e2..ef58957bb 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -40,6 +40,7 @@ * F102, F103 512 byte buffer; no internal D+ pull-up (maybe many more changes?) * F302xB/C, F303xB/C, F373 512 byte buffer; no internal D+ pull-up * F302x6/8, F302xD/E2, F303xD/E 1024 byte buffer; no internal D+ pull-up + * C0 2048 byte buffer; 32-bit bus; host mode * G0 2048 byte buffer; 32-bit bus; host mode * G4 1024 byte buffer * H5 2048 byte buffer; 32-bit bus; host mode diff --git a/src/portable/st/stm32_fsdev/fsdev_stm32.h b/src/portable/st/stm32_fsdev/fsdev_stm32.h index 03ea4c67e..ccf31e035 100644 --- a/src/portable/st/stm32_fsdev/fsdev_stm32.h +++ b/src/portable/st/stm32_fsdev/fsdev_stm32.h @@ -104,6 +104,20 @@ #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY #define USB_CNTR_FSUSP USB_CNTR_SUSPEN +#elif CFG_TUSB_MCU == OPT_MCU_STM32C0 + #include "stm32c0xx.h" + #define FSDEV_PMA_SIZE (2048u) + #define USB USB_DRD_FS + #define USB_EP_CTR_RX USB_CHEP_VTRX + #define USB_EP_CTR_TX USB_CHEP_VTTX + #define USB_EPREG_MASK USB_CHEP_REG_MASK + #define USB_CNTR_FRES USB_CNTR_USBRST + #define USB_CNTR_RESUME USB_CNTR_L2RES + #define USB_ISTR_EP_ID USB_ISTR_IDN + #define USB_EPADDR_FIELD USB_CHEP_ADDR + #define USB_CNTR_LPMODE USB_CNTR_SUSPRDY + #define USB_CNTR_FSUSP USB_CNTR_SUSPEN + #elif CFG_TUSB_MCU == OPT_MCU_STM32H5 #include "stm32h5xx.h" #define FSDEV_PMA_SIZE (2048u) @@ -260,6 +274,8 @@ static const IRQn_Type fsdev_irq[] = { #else USB_UCPD1_2_IRQn, #endif + #elif CFG_TUSB_MCU == OPT_MCU_STM32C0 + USB_DRD_FS_IRQn, #elif TU_CHECK_MCU(OPT_MCU_STM32G4, OPT_MCU_STM32L1) USB_HP_IRQn, USB_LP_IRQn, diff --git a/src/tusb_option.h b/src/tusb_option.h index 42994cb03..dca1e4109 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -93,6 +93,7 @@ #define OPT_MCU_STM32H5 315 ///< ST H5 #define OPT_MCU_STM32U0 316 ///< ST U0 #define OPT_MCU_STM32H7RS 317 ///< ST F7RS +#define OPT_MCU_STM32C0 318 ///< ST C0 // Sony #define OPT_MCU_CXD56 400 ///< SONY CXD56 diff --git a/tools/get_deps.py b/tools/get_deps.py index 6d0ef9d0c..58709414c 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -73,6 +73,9 @@ deps_optional = { 'hw/mcu/sony/cxd56/spresense-exported-sdk': ['https://github.com/sonydevworld/spresense-exported-sdk.git', '2ec2a1538362696118dc3fdf56f33dacaf8f4067', 'spresense'], + 'hw/mcu/st/cmsis_device_c0': ['https://github.com/STMicroelectronics/cmsis_device_c0.git', + 'fb56b1b70c73b74eacda2a4bcc36886444364ab3', + 'stm32c0'], 'hw/mcu/st/cmsis_device_f0': ['https://github.com/STMicroelectronics/cmsis_device_f0.git', '2fc25ee22264bc27034358be0bd400b893ef837e', 'stm32f0'], @@ -124,6 +127,9 @@ deps_optional = { 'hw/mcu/st/stm32-mfxstm32l152': ['https://github.com/STMicroelectronics/stm32-mfxstm32l152.git', '7f4389efee9c6a655b55e5df3fceef5586b35f9b', 'stm32h7'], + 'hw/mcu/st/stm32c0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32c0xx_hal_driver.git', + '41253e2f1d7ae4a4d0c379cf63f5bcf71fcf8eb3', + 'stm32c0'], 'hw/mcu/st/stm32f0xx_hal_driver': ['https://github.com/STMicroelectronics/stm32f0xx_hal_driver.git', '0e95cd88657030f640a11e690a8a5186c7712ea5', 'stm32f0'], @@ -189,12 +195,12 @@ deps_optional = { 'ch32f20x'], 'lib/CMSIS_5': ['https://github.com/ARM-software/CMSIS_5.git', '20285262657d1b482d132d20d755c8c330d55c1f', - 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x' - 'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43' - 'stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5' - 'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb' - 'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg' - 'tm4c'], + 'imxrt kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx mm32 msp432e4 nrf ra saml2x ' + 'lpc11 lpc13 lpc15 lpc17 lpc18 lpc40 lpc43 ' + 'stm32c0 stm32f0 stm32f1 stm32f2 stm32f3 stm32f4 stm32f7 stm32g0 stm32g4 stm32h5 ' + 'stm32h7 stm32l0 stm32l1 stm32l4 stm32l5 stm32u5 stm32wb ' + 'sam3x samd11 samd21 samd51 samd5x_e5x same5x same7x saml2x samg ' + 'tm4c '], 'lib/sct_neopixel': ['https://github.com/gsteiert/sct_neopixel.git', 'e73e04ca63495672d955f9268e003cffe168fcd8', 'lpc55'], -- cgit v1.3.1 From 7f61a5a43b4637afc323f6e63cc59330f1b1e5a6 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 28 Nov 2024 15:56:47 +0700 Subject: made change per reviews, remove dcd_edpt_close(), rename and move thing around --- src/common/tusb_common.h | 1 + src/portable/raspberrypi/rp2040/dcd_rp2040.c | 167 +++++++++------------------ 2 files changed, 55 insertions(+), 113 deletions(-) (limited to 'src/portable') diff --git a/src/common/tusb_common.h b/src/common/tusb_common.h index d05032d00..74cac965d 100644 --- a/src/common/tusb_common.h +++ b/src/common/tusb_common.h @@ -177,6 +177,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool tu_is_aligned64(uint64_t value) { retur //------------- Mathematics -------------// TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_div_ceil(uint32_t v, uint32_t d) { return TU_DIV_CEIL(v, d); } +TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_round_up(uint32_t v, uint32_t f) { return tu_div_ceil(v, f) * f; } // log2 of a value is its MSB's position // TODO use clz TODO remove diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index bb0a2f3fb..af08b549d 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -46,11 +46,8 @@ /*------------------------------------------------------------------*/ /* Low level controller *------------------------------------------------------------------*/ -static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type); -static void hw_set_endpoint_control_reg(struct hw_endpoint* ep, uint dpram_offset); - // Init these in dcd_init -static uint8_t* next_buffer_ptr = NULL; +static uint8_t* next_buffer_ptr; // USB_MAX_ENDPOINTS Endpoints, direction TUSB_DIR_OUT for out and TUSB_DIR_IN for in. static struct hw_endpoint hw_endpoints[USB_MAX_ENDPOINTS][2]; @@ -70,115 +67,28 @@ TU_ATTR_ALWAYS_INLINE static inline struct hw_endpoint* hw_endpoint_get_by_addr( // Allocate from the USB buffer space (max 3840 bytes) static void hw_endpoint_alloc(struct hw_endpoint* ep, size_t size) { - static uint8_t *end; - // determine buffer end - if (end == NULL){ - end = &usb_dpram->epx_data[0] + 0xF00; - } - // determine first next_buffer_ptr if necessary - if (next_buffer_ptr == NULL){ - next_buffer_ptr = &usb_dpram->epx_data[0]; - } - // assign buffer - ep->hw_data_buf = next_buffer_ptr; - next_buffer_ptr += size; - - hard_assert(next_buffer_ptr < end); - - pico_info(" Allocated %d bytes (0x%p)\r\n", size, ep->hw_data_buf); -} + // round up size to multiple of 64 + size = tu_round_up(ep->wMaxPacketSize, 64); -// allocate endpoint and fill endpoint control registers -static void hw_endpoint_alloc_and_control(struct hw_endpoint* ep, uint8_t transfer_type) { - // size must be multiple of 64 - uint size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u; // double buffered Bulk endpoint - if (transfer_type == TUSB_XFER_BULK) { + if (ep->transfer_type == TUSB_XFER_BULK) { size *= 2u; } - ep->transfer_type = transfer_type; - hw_endpoint_alloc(ep, size); - uint dpram_offset = hw_data_offset(ep->hw_data_buf); - pico_info(" Allocated %d bytes at offset 0x%x (0x%p)\r\n", size, dpram_offset, ep->hw_data_buf); + // assign buffer + ep->hw_data_buf = next_buffer_ptr; + next_buffer_ptr += size; - hw_set_endpoint_control_reg(ep, dpram_offset); + hard_assert(next_buffer_ptr < usb_dpram->epx_data + sizeof(usb_dpram->epx_data)); + pico_info(" Allocated %d bytes (0x%p)\r\n", size, ep->hw_data_buf); } -static void hw_set_endpoint_control_reg(struct hw_endpoint* ep, uint dpram_offset) { - // Fill in endpoint control register with buffer offset - uint32_t const reg = EP_CTRL_ENABLE_BITS | ((uint) ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset; +// Enable endpoint +TU_ATTR_ALWAYS_INLINE static inline void hw_endpoint_enable(struct hw_endpoint* ep) { + uint32_t const reg = EP_CTRL_ENABLE_BITS | ((uint) ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | hw_data_offset(ep->hw_data_buf); *ep->endpoint_control = reg; } -// New API: Allocate packet buffer used by ISO endpoints -// Some MCU need manual packet buffer allocation, we allocate the largest size to avoid clustering -bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { - (void) rhport; - assert(rhport == 0); - struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); - // size must be multiple of 64 - uint16_t size = (uint16_t)tu_div_ceil(largest_packet_size, 64) * 64u; - ep->wMaxPacketSize = size; - hw_endpoint_alloc(ep, size); - return true; -} - -// New API: Configure and enable an ISO endpoint according to descriptor -bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { - (void) rhport; - assert(rhport == 0); - const uint8_t ep_addr = ep_desc->bEndpointAddress; - const uint16_t mps = ep_desc->wMaxPacketSize; - uint16_t size = (uint16_t)tu_div_ceil(mps, 64) * 64u; - - // init w/o allocate - hw_endpoint_init(ep_addr, size, TUSB_XFER_ISOCHRONOUS); - - // Fill in endpoint control register with buffer offset - struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); - uint dpram_offset = hw_data_offset(ep->hw_data_buf); - hw_set_endpoint_control_reg(ep, dpram_offset); - return true; -} - -static void hw_endpoint_close(uint8_t ep_addr) { - struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); - // Clear hardware registers and then zero the struct - // Clears endpoint enable - *ep->endpoint_control = 0; - // Clears buffer available, etc - *ep->buffer_control = 0; - // Clear any endpoint state - memset(ep, 0, sizeof(struct hw_endpoint)); - - // Reclaim buffer space if all endpoints are closed - bool reclaim_buffers = true; - for (uint8_t i = 1; i < USB_MAX_ENDPOINTS; i++) { - if (hw_endpoint_get_by_num(i, TUSB_DIR_OUT)->hw_data_buf != NULL || - hw_endpoint_get_by_num(i, TUSB_DIR_IN)->hw_data_buf != NULL) { - reclaim_buffers = false; - break; - } - } - if (reclaim_buffers) { - next_buffer_ptr = &usb_dpram->epx_data[0]; - } -} - -// Legacy init called by dcd_init (which does allocation) -static void hw_endpoint_init_and_alloc(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type) { - struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); - uint16_t size = (uint16_t) tu_div_ceil(wMaxPacketSize, 64) * 64u; - // size must be multiple of 64 - hw_endpoint_init(ep_addr, size, transfer_type); - const uint8_t num = tu_edpt_number(ep_addr); - if (num != 0) { - // alloc a buffer and fill in endpoint control register - hw_endpoint_alloc_and_control(ep, transfer_type); - } -} - // main processing for dcd_edpt_iso_activate static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type) { struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); @@ -221,6 +131,18 @@ static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t t } } +// Init, allocate buffer and enable endpoint +static void hw_endpoint_open(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type) { + struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); + hw_endpoint_init(ep_addr, wMaxPacketSize, transfer_type); + const uint8_t num = tu_edpt_number(ep_addr); + if (num != 0) { + // EP0 is already enabled + hw_endpoint_alloc(ep, ep->wMaxPacketSize); + hw_endpoint_enable(ep); + } +} + static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t* buffer, uint16_t total_bytes) { struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); hw_endpoint_xfer_start(ep, buffer, total_bytes); @@ -446,8 +368,8 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // Init control endpoints tu_memclr(hw_endpoints[0], 2 * sizeof(hw_endpoint_t)); - hw_endpoint_init_and_alloc(0x0, 64, TUSB_XFER_CONTROL); - hw_endpoint_init_and_alloc(0x80, 64, TUSB_XFER_CONTROL); + hw_endpoint_open(0x0, 64, TUSB_XFER_CONTROL); + hw_endpoint_open(0x80, 64, TUSB_XFER_CONTROL); // Init non-control endpoints reset_non_control_endpoints(); @@ -552,9 +474,34 @@ void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const* req } } -bool dcd_edpt_open(__unused uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) { - assert(rhport == 0); - hw_endpoint_init_and_alloc(desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt), desc_edpt->bmAttributes.xfer); +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const* desc_edpt) { + (void) rhport; + const uint8_t xfer_type = desc_edpt->bmAttributes.xfer; + TU_VERIFY(xfer_type != TUSB_XFER_ISOCHRONOUS); + hw_endpoint_open(desc_edpt->bEndpointAddress, tu_edpt_packet_size(desc_edpt), xfer_type); + return true; +} + +// New API: Allocate packet buffer used by ISO endpoints +// Some MCU need manual packet buffer allocation, we allocate the largest size to avoid clustering +bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet_size) { + (void) rhport; + struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); + hw_endpoint_init(ep_addr, largest_packet_size, TUSB_XFER_ISOCHRONOUS); + hw_endpoint_alloc(ep, largest_packet_size); + return true; +} + +// New API: Configure and enable an ISO endpoint according to descriptor +bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { + (void) rhport; + const uint8_t ep_addr = ep_desc->bEndpointAddress; + // Fill in endpoint control register with buffer offset + struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); + TU_ASSERT(ep->hw_data_buf != NULL); // must be inited and buffer allocated + ep->wMaxPacketSize = ep_desc->wMaxPacketSize; + + hw_endpoint_enable(ep); return true; } @@ -599,12 +546,6 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { } } -void dcd_edpt_close(uint8_t rhport, uint8_t ep_addr) { - (void) rhport; - pico_trace("dcd_edpt_close %02x\r\n", ep_addr); - hw_endpoint_close(ep_addr); -} - void __tusb_irq_path_func(dcd_int_handler)(uint8_t rhport) { (void) rhport; dcd_rp2040_irq(); -- cgit v1.3.1 From 741fdaaee7b346815546a8e5be2cae9dd015d64a Mon Sep 17 00:00:00 2001 From: Roman Leonov Date: Thu, 28 Nov 2024 11:58:20 +0100 Subject: fix(dcd_dwc2): Reset allocated_epin_count on bus reset and close all ep --- src/portable/synopsys/dwc2/dcd_dwc2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 63d2e5bb1..91c006e01 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -539,7 +539,7 @@ void dcd_edpt_close_all(uint8_t rhport) { dwc2_regs_t* dwc2 = DWC2_REG(rhport); uint8_t const ep_count = _dwc2_controller[rhport].ep_count; - _dcd_data.allocated_epin_count = 1; + _dcd_data.allocated_epin_count = 0; // Disable non-control interrupt dwc2->daintmsk = (1 << DAINTMSK_OEPM_Pos) | (1 << DAINTMSK_IEPM_Pos); @@ -646,7 +646,7 @@ static void handle_bus_reset(uint8_t rhport) { tu_memclr(xfer_status, sizeof(xfer_status)); _dcd_data.sof_en = false; - _dcd_data.allocated_epin_count = 1; + _dcd_data.allocated_epin_count = 0; // 1. NAK for all OUT endpoints for (uint8_t n = 0; n < ep_count; n++) { -- cgit v1.3.1 From 239443c197c34f0f51a4ff7839b25985ccbb48ad Mon Sep 17 00:00:00 2001 From: Roman Leonov Date: Thu, 28 Nov 2024 12:59:13 +0100 Subject: fix(dcd_dwc2): Correct usage of dwc2_controller --- src/portable/synopsys/dwc2/dcd_dwc2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index 91c006e01..bde48ef57 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -192,8 +192,8 @@ static bool dfifo_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t packet_size) { } } else { // Check IN endpoints concurrently active limit - if(_dwc2_controller->ep_in_count) { - TU_ASSERT(_dcd_data.allocated_epin_count < _dwc2_controller->ep_in_count); + if(dwc2_controller->ep_in_count) { + TU_ASSERT(_dcd_data.allocated_epin_count < dwc2_controller->ep_in_count); _dcd_data.allocated_epin_count++; } -- cgit v1.3.1 From 3351c366ab8298c342b2802c28d65a67f4078d56 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 30 Nov 2024 20:48:09 +0100 Subject: Restore DCache clean/invalidate. Signed-off-by: HiFiPhile --- src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 52 +++++++++++++++++++++++++++++++ src/portable/chipidea/ci_hs/dcd_ci_hs.c | 29 ++++++++++------- 2 files changed, 69 insertions(+), 12 deletions(-) (limited to 'src/portable') diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h index 201936e53..c53556f79 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h +++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h @@ -63,4 +63,56 @@ static const ci_hs_controller_t _ci_controller[] = #define CI_HCD_INT_ENABLE(_p) NVIC_EnableIRQ ((IRQn_Type)_ci_controller[_p].irqnum) #define CI_HCD_INT_DISABLE(_p) NVIC_DisableIRQ((IRQn_Type)_ci_controller[_p].irqnum) +//------------- DCache -------------// +#if CFG_TUD_MEM_DCACHE_ENABLE || CFG_TUH_MEM_DCACHE_ENABLE +#if __CORTEX_M == 7 +TU_ATTR_ALWAYS_INLINE static inline uint32_t round_up_to_cache_line_size(uint32_t size) { + if (size & (CFG_TUD_MEM_DCACHE_LINE_SIZE-1)) { + size = (size & ~(CFG_TUD_MEM_DCACHE_LINE_SIZE-1)) + CFG_TUD_MEM_DCACHE_LINE_SIZE; + } + return size; +} + +TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uintptr_t addr) { + return !(0x20000000 <= addr && addr < 0x20100000); +} + +bool dcd_dcache_clean(void const* addr, uint32_t data_size) { + const uintptr_t addr32 = (uintptr_t) addr; + if (imxrt_is_cache_mem(addr32)) { + TU_ASSERT(tu_is_aligned32(addr32)); + data_size = round_up_to_cache_line_size(data_size); + SCB_CleanDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size); + } + return true; +} + +bool dcd_dcache_invalidate(void const* addr, uint32_t data_size) { + const uintptr_t addr32 = (uintptr_t) addr; + if (imxrt_is_cache_mem(addr32)) { + // Invalidating does not push cached changes back to RAM so we need to be + // *very* careful when we do it. If we're not aligned, then we risk resetting + // values back to their RAM state. + TU_ASSERT(tu_is_aligned32(addr32)); + data_size = round_up_to_cache_line_size(data_size); + SCB_InvalidateDCache_by_Addr((void*) addr32, (int32_t) data_size); + } + return true; +} + +bool dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { + const uintptr_t addr32 = (uintptr_t) addr; + if (imxrt_is_cache_mem(addr32)) { + TU_ASSERT(tu_is_aligned32(addr32)); + data_size = round_up_to_cache_line_size(data_size); + SCB_CleanInvalidateDCache_by_Addr((uint32_t *) addr32, (int32_t) data_size); + } + return true; +} + +#elif __CORTEX_M == 4 +#error "Secondary M4 core's cache controller is not supported yet." +#endif +#endif + #endif diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index 6d6a74524..bacc1b99d 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -34,18 +34,6 @@ #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX #include "ci_hs_imxrt.h" - bool dcd_dcache_clean(void const* addr, uint32_t data_size) { - return imxrt_dcache_clean(addr, data_size); - } - - bool dcd_dcache_invalidate(void const* addr, uint32_t data_size) { - return imxrt_dcache_invalidate(addr, data_size); - } - - bool dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { - return imxrt_dcache_clean_invalidate(addr, data_size); - } - #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) #include "ci_hs_lpc18_43.h" @@ -216,6 +204,8 @@ static void bus_reset(uint8_t rhport) _dcd_data.qhd[0][0].qtd_overlay.next = _dcd_data.qhd[0][1].qtd_overlay.next = QTD_NEXT_INVALID; _dcd_data.qhd[0][0].int_on_setup = 1; // OUT only + + dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); } bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { @@ -241,6 +231,8 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dcd_reg->PORTSC1 = PORTSC1_FORCE_FULL_SPEED; #endif + dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); + dcd_reg->ENDPTLISTADDR = (uint32_t) _dcd_data.qhd; // Endpoint List Address has to be 2K alignment dcd_reg->USBSTS = dcd_reg->USBSTS; dcd_reg->USBINTR = INTR_USB | INTR_ERROR | INTR_PORT_CHANGE | INTR_SUSPEND; @@ -307,6 +299,8 @@ void dcd_sof_enable(uint8_t rhport, bool en) static void qtd_init(dcd_qtd_t* p_qtd, void * data_ptr, uint16_t total_bytes) { + dcd_dcache_clean_invalidate((uint32_t*) tu_align((uint32_t) data_ptr, 4), total_bytes); + tu_memclr(p_qtd, sizeof(dcd_qtd_t)); p_qtd->next = QTD_NEXT_INVALID; @@ -380,6 +374,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoint_desc) p_qhd->qtd_overlay.next = QTD_NEXT_INVALID; + dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); + // Enable EP Control uint32_t const epctrl = (p_endpoint_desc->bmAttributes.xfer << ENDPTCTRL_TYPE_POS) | ENDPTCTRL_ENABLE | ENDPTCTRL_TOGGLE_RESET; @@ -437,6 +433,9 @@ static void qhd_start_xfer(uint8_t rhport, uint8_t epnum, uint8_t dir) p_qhd->qtd_overlay.halted = false; // clear any previous error p_qhd->qtd_overlay.next = (uint32_t) p_qtd; // link qtd to qhd + // flush cache + dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); + if ( epnum == 0 ) { // follows UM 24.10.8.1.1 Setup packet handling using setup lockout mechanism @@ -466,7 +465,9 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t return true; } +#if !CFG_TUD_MEM_DCACHE_ENABLE // fifo has to be aligned to 4k boundary +// It's imcompatible with dcache enabled transfer, since neither address nor size is aligned to cache line bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) { uint8_t const epnum = tu_edpt_number(ep_addr); @@ -526,6 +527,7 @@ bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16 return true; } +#endif //--------------------------------------------------------------------+ // ISR @@ -623,6 +625,9 @@ void dcd_int_handler(uint8_t rhport) if (int_status & INTR_USB) { + // Make sure we read the latest version of _dcd_data. + dcd_dcache_clean_invalidate(&_dcd_data, sizeof(dcd_data_t)); + uint32_t const edpt_complete = dcd_reg->ENDPTCOMPLETE; dcd_reg->ENDPTCOMPLETE = edpt_complete; // acknowledge -- cgit v1.3.1 From 0bca377d5210833ac259db6ed9d7d96c724f3e6e Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 30 Nov 2024 21:57:47 +0100 Subject: Fix typo. Signed-off-by: HiFiPhile --- src/class/audio/audio_device.c | 8 ++++---- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) (limited to 'src/portable') diff --git a/src/class/audio/audio_device.c b/src/class/audio/audio_device.c index 2add741a8..425da4483 100644 --- a/src/class/audio/audio_device.c +++ b/src/class/audio/audio_device.c @@ -81,7 +81,7 @@ // Only STM32 and dcd_transdimension use non-linear buffer for now // dwc2 except esp32sx (since it may use dcd_esp32sx) -// Ring buffer is imcompatible with dcache, since neither address nor size is aligned to cache line +// Ring buffer is incompatible with dcache, since neither address nor size is aligned to cache line #if (defined(TUP_USBIP_DWC2) && !TU_CHECK_MCU(OPT_MCU_ESP32S2, OPT_MCU_ESP32S3)) || \ defined(TUP_USBIP_FSDEV) || \ CFG_TUSB_MCU == OPT_MCU_RX63X || \ @@ -179,13 +179,13 @@ tu_static OUT_SW_BUF_MEM_ATTR struct { #if CFG_FIFO_MUTEX #if CFG_TUD_AUDIO_FUNC_1_EP_OUT_SW_BUF_SZ > 0 - tu_static osal_mutex_def_t ep_out_ff_mutex_wr_1; + tu_static osal_mutex_def_t ep_out_ff_mutex_rd_1; #endif #if CFG_TUD_AUDIO > 1 && CFG_TUD_AUDIO_FUNC_2_EP_OUT_SW_BUF_SZ > 0 - tu_static osal_mutex_def_t ep_out_ff_mutex_wr_2; + tu_static osal_mutex_def_t ep_out_ff_mutex_rd_2; #endif #if CFG_TUD_AUDIO > 2 && CFG_TUD_AUDIO_FUNC_3_EP_OUT_SW_BUF_SZ > 0 - tu_static osal_mutex_def_t ep_out_ff_mutex_wr_3; + tu_static osal_mutex_def_t ep_out_ff_mutex_rd_3; #endif #endif #endif // CFG_TUD_AUDIO_ENABLE_EP_OUT && !CFG_TUD_AUDIO_ENABLE_DECODING diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index bacc1b99d..331fbfe80 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -467,7 +467,7 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t t #if !CFG_TUD_MEM_DCACHE_ENABLE // fifo has to be aligned to 4k boundary -// It's imcompatible with dcache enabled transfer, since neither address nor size is aligned to cache line +// It's incompatible with dcache enabled transfer, since neither address nor size is aligned to cache line bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) { uint8_t const epnum = tu_edpt_number(ep_addr); -- cgit v1.3.1 From 0d9a24c416cce6fc7201d9201dc131ec2b2110c3 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sat, 30 Nov 2024 23:18:22 +0100 Subject: Fix HCD build. Signed-off-by: HiFiPhile --- src/portable/chipidea/ci_hs/ci_hs_imxrt.h | 6 +++--- src/portable/chipidea/ci_hs/dcd_ci_hs.c | 14 ++++++++++++++ src/portable/chipidea/ci_hs/hcd_ci_hs.c | 2 ++ 3 files changed, 19 insertions(+), 3 deletions(-) (limited to 'src/portable') diff --git a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h index c53556f79..75d1d55b8 100644 --- a/src/portable/chipidea/ci_hs/ci_hs_imxrt.h +++ b/src/portable/chipidea/ci_hs/ci_hs_imxrt.h @@ -77,7 +77,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool imxrt_is_cache_mem(uintptr_t addr) { return !(0x20000000 <= addr && addr < 0x20100000); } -bool dcd_dcache_clean(void const* addr, uint32_t data_size) { +TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean(void const* addr, uint32_t data_size) { const uintptr_t addr32 = (uintptr_t) addr; if (imxrt_is_cache_mem(addr32)) { TU_ASSERT(tu_is_aligned32(addr32)); @@ -87,7 +87,7 @@ bool dcd_dcache_clean(void const* addr, uint32_t data_size) { return true; } -bool dcd_dcache_invalidate(void const* addr, uint32_t data_size) { +TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_invalidate(void const* addr, uint32_t data_size) { const uintptr_t addr32 = (uintptr_t) addr; if (imxrt_is_cache_mem(addr32)) { // Invalidating does not push cached changes back to RAM so we need to be @@ -100,7 +100,7 @@ bool dcd_dcache_invalidate(void const* addr, uint32_t data_size) { return true; } -bool dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { +TU_ATTR_ALWAYS_INLINE static inline bool imxrt_dcache_clean_invalidate(void const* addr, uint32_t data_size) { const uintptr_t addr32 = (uintptr_t) addr; if (imxrt_is_cache_mem(addr32)) { TU_ASSERT(tu_is_aligned32(addr32)); diff --git a/src/portable/chipidea/ci_hs/dcd_ci_hs.c b/src/portable/chipidea/ci_hs/dcd_ci_hs.c index 331fbfe80..a716dc24c 100644 --- a/src/portable/chipidea/ci_hs/dcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/dcd_ci_hs.c @@ -34,6 +34,20 @@ #if CFG_TUSB_MCU == OPT_MCU_MIMXRT1XXX #include "ci_hs_imxrt.h" +#if CFG_TUD_MEM_DCACHE_ENABLE +bool dcd_dcache_clean(void const* addr, uint32_t data_size) { + return imxrt_dcache_clean(addr, data_size); +} + +bool dcd_dcache_invalidate(void const* addr, uint32_t data_size) { + return imxrt_dcache_invalidate(addr, data_size); +} + +bool dcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { + return imxrt_dcache_clean_invalidate(addr, data_size); +} +#endif + #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) #include "ci_hs_lpc18_43.h" diff --git a/src/portable/chipidea/ci_hs/hcd_ci_hs.c b/src/portable/chipidea/ci_hs/hcd_ci_hs.c index 14f8acb45..c4c342a70 100644 --- a/src/portable/chipidea/ci_hs/hcd_ci_hs.c +++ b/src/portable/chipidea/ci_hs/hcd_ci_hs.c @@ -42,6 +42,7 @@ #include "ci_hs_imxrt.h" +#if CFG_TUH_MEM_DCACHE_ENABLE bool hcd_dcache_clean(void const* addr, uint32_t data_size) { return imxrt_dcache_clean(addr, data_size); } @@ -53,6 +54,7 @@ bool hcd_dcache_invalidate(void const* addr, uint32_t data_size) { bool hcd_dcache_clean_invalidate(void const* addr, uint32_t data_size) { return imxrt_dcache_clean_invalidate(addr, data_size); } +#endif #elif TU_CHECK_MCU(OPT_MCU_LPC18XX, OPT_MCU_LPC43XX) -- cgit v1.3.1 From 3653c23240046a99d8b846b65d875589f0edcd16 Mon Sep 17 00:00:00 2001 From: Scott Shawcroft Date: Mon, 2 Dec 2024 12:32:39 -0800 Subject: Disable DWC HCD interrupt with MAX3421 enabled hcd_int_handler isn't found otherwise. --- src/portable/synopsys/dwc2/dwc2_esp32.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dwc2_esp32.h b/src/portable/synopsys/dwc2/dwc2_esp32.h index ddbfd0d10..3309760ff 100644 --- a/src/portable/synopsys/dwc2/dwc2_esp32.h +++ b/src/portable/synopsys/dwc2/dwc2_esp32.h @@ -73,7 +73,7 @@ static void dwc2_int_handler_wrap(void* arg) { dcd_int_handler(rhport); } #endif -#if CFG_TUH_ENABLED +#if CFG_TUH_ENABLED && !CFG_TUH_MAX3421 if (role == TUSB_ROLE_HOST) { hcd_int_handler(rhport, true); } -- cgit v1.3.1 From d502a0c481b7e0e742e2997f0d3fb5ef9f4eb9d4 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 11 Dec 2024 15:02:02 +0700 Subject: fix correct DWC2_EP_COUNT --- src/portable/synopsys/dwc2/dcd_dwc2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/dcd_dwc2.c b/src/portable/synopsys/dwc2/dcd_dwc2.c index bde48ef57..c461d9a79 100644 --- a/src/portable/synopsys/dwc2/dcd_dwc2.c +++ b/src/portable/synopsys/dwc2/dcd_dwc2.c @@ -44,7 +44,7 @@ #if TU_CHECK_MCU(OPT_MCU_GD32VF103) #define DWC2_EP_COUNT(_dwc2) DWC2_EP_MAX #else - #define DWC2_EP_COUNT(_dwc2) ((_dwc2)->ghwcfg2_bm.num_dev_ep) + #define DWC2_EP_COUNT(_dwc2) ((_dwc2)->ghwcfg2_bm.num_dev_ep + 1) #endif //--------------------------------------------------------------------+ -- cgit v1.3.1 From 80224770316966e4339d414c60aea6a5020caa16 Mon Sep 17 00:00:00 2001 From: Reimu NotMoe Date: Fri, 27 Dec 2024 00:36:31 +0800 Subject: dcd_pic: add readme --- src/portable/microchip/pic/README.md | 51 ++++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) create mode 100644 src/portable/microchip/pic/README.md (limited to 'src/portable') diff --git a/src/portable/microchip/pic/README.md b/src/portable/microchip/pic/README.md new file mode 100644 index 000000000..7ba6a4a96 --- /dev/null +++ b/src/portable/microchip/pic/README.md @@ -0,0 +1,51 @@ +# Microchip PIC Chipidea FS Driver + +This driver adds support for Microchip PIC microcontrollers with full-speed Chipidea USB peripheral to the TinyUSB stack. It supports the following families: + +- PIC32MX (untested) +- PIC32MM +- PIC32MK (untested) +- PIC24FJ +- PIC24EP (untested) +- dsPIC33EP (untested) + +Currently only the device mode is supported. + + +## Important Notes + +### Handling of shared VBUS & GPIO pin + +Some PICs have the USB VBUS pin bonded with a GPIO pin in the chip package. This driver does **NOT** handle the potential conflict between the VBUS and GPIO functionalities. + +Developers must ensure that the GPIO pin is tristated when the VBUS pin is managed by the USB peripheral in order to prevent damaging the chip. + +This design choice allows developers the flexibility to use the GPIO functionality for controlling VBUS in device mode if desired. + + +## TODO + +### Handle USB remote wakeup timing correctly + +The Chipidea FS IP doesn't handle the RESUME signal automatically and it must be managed in software. It needs to be asserted for exactly 10ms, and this is impossible to do without per-device support due to BSP differences. For now, a simple for-based loop is used. + +### 8-bit PIC support + +The 8-bit PICs also uses the Chipidea FS IP. Technically it's possible to support them as well. + +Possible difficulties: +- Memory size constraints (1KB/8KB ballpark) +- A third BDT layout (now we have two) +- Different compiler-specific directives +- Compiler bugs if you use SDCC + + +## Author +[ReimuNotMoe](https://github.com/ReimuNotMoe) at SudoMaker, Ltd. + + +## Credits + +This driver is based on: +- Microchip's USB driver (usb_device.c) +- TinyUSB's NXP KHCI driver (dcd_khci.c) -- cgit v1.3.1 From 99e6b32a7da695f16a2fed93c59bfa0d5a1952dc Mon Sep 17 00:00:00 2001 From: Reimu NotMoe Date: Fri, 27 Dec 2024 00:36:42 +0800 Subject: dcd_pic: change license header and credit people accordingly --- src/portable/microchip/pic/dcd_pic.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'src/portable') diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c index d40c4794a..461c65259 100644 --- a/src/portable/microchip/pic/dcd_pic.c +++ b/src/portable/microchip/pic/dcd_pic.c @@ -1,8 +1,11 @@ /* * The MIT License (MIT) * - * Copyright (c) 2020 Koji Kitayama - * Copyright (c) 2022 Reimu NotMoe + * Copyright (c) 2022-2024 SudoMaker, Ltd. + * Author: Mike Yang (Reimu NotMoe) + * + * Based on usb_device.c - Copyright (c) 2015 Microchip Technology Inc. + * Based on dcd_khci.c - Copyright (c) 2020 Koji Kitayama * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal -- cgit v1.3.1 From 8907a817a2a782423bf8d6db2136147b6e334225 Mon Sep 17 00:00:00 2001 From: Reimu NotMoe Date: Fri, 27 Dec 2024 00:50:32 +0800 Subject: dcd_pic: handle bus resume correctly --- src/portable/microchip/pic/dcd_pic.c | 58 ++++++++++++++++++++++++++++++------ 1 file changed, 49 insertions(+), 9 deletions(-) (limited to 'src/portable') diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c index 461c65259..0dac18523 100644 --- a/src/portable/microchip/pic/dcd_pic.c +++ b/src/portable/microchip/pic/dcd_pic.c @@ -741,8 +741,11 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) //--------------------------------------------------------------------+ void dcd_int_handler(uint8_t rhport) { - uint32_t is = U1IR; - uint32_t msk = U1IE; + uint32_t is, msk; + + // Part 1 - "USB interrupts" + is = U1IR; + msk = U1IE; U1IR = is & ~msk; is &= msk; @@ -750,7 +753,7 @@ void dcd_int_handler(uint8_t rhport) if (is & _U1IR_UERRIF_MASK) { uint32_t es = U1EIR; U1EIR = es; - U1IR = is; /* discard any pending events */ + U1IR = is; /* discard any pending events */ } if (is & _U1IR_URSTIF_MASK) { @@ -761,29 +764,66 @@ void dcd_int_handler(uint8_t rhport) if (is & _U1IR_IDLEIF_MASK) { // Note Host usually has extra delay after bus reset (without SOF), which could falsely // detected as Sleep event. Though usbd has debouncing logic so we are good + + /* + * NOTE: Do not clear U1OTGIRbits.ACTVIF here! + * Reason: + * ACTVIF is only generated once an IDLEIF has been generated. + * This is a 1:1 ratio interrupt generation. + * For every IDLEIF, there will be only one ACTVIF regardless of + * the number of subsequent bus transitions. + * + * If the ACTIF is cleared here, a problem could occur when: + * [ IDLE ][bus activity -> + * <--- 3 ms -----> ^ + * ^ ACTVIF=1 + * IDLEIF=1 + * # # # # (#=Program polling flags) + * ^ + * This polling loop will see both + * IDLEIF=1 and ACTVIF=1. + * However, the program services IDLEIF first + * because ACTIVIE=0. + * If this routine clears the only ACTIVIF, + * then it can never get out of the suspend + * mode. + */ + U1OTGIESET = _U1OTGIE_ACTVIE_MASK; U1IR = _U1IR_IDLEIF_MASK; process_bus_sleep(rhport); } - if (is & _U1IR_RESUMEIF_MASK) { - U1IR = _U1IR_RESUMEIF_MASK; - process_bus_resume(rhport); - } - if (is & _U1IR_SOFIF_MASK) { U1IR = _U1IR_SOFIF_MASK; dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); } if (is & _U1IR_STALLIF_MASK) { - U1IR = _U1IR_STALLIF_MASK; process_stall(rhport); + U1IR = _U1IR_STALLIF_MASK; } if (is & _U1IR_TRNIF_MASK) { process_tokdne(rhport); } + // Part 2 - "USB OTG interrupts" + is = U1OTGIR; + msk = U1OTGIE; + + U1OTGIR = is & ~msk; + is &= msk; + + if (is & _U1OTGIR_ACTVIF_MASK) { +#if TU_PIC_INT_SIZE == 4 + U1OTGIECLR = _U1OTGIE_ACTVIE_MASK; +#else + U1OTGIE &= ~_U1OTGIE_ACTVIE_MASK; +#endif + U1OTGIR = _U1OTGIR_ACTVIF_MASK; + process_bus_resume(rhport); + } + intr_clear(rhport); } -- cgit v1.3.1 From f409472998cfba4f6be0534912c1afd48e0d6816 Mon Sep 17 00:00:00 2001 From: Reimu NotMoe Date: Fri, 27 Dec 2024 00:57:22 +0800 Subject: dcd_pic: handle remote wakeup more correctly --- src/portable/microchip/pic/dcd_pic.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) (limited to 'src/portable') diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c index 0dac18523..9ffeb0811 100644 --- a/src/portable/microchip/pic/dcd_pic.c +++ b/src/portable/microchip/pic/dcd_pic.c @@ -532,8 +532,25 @@ void dcd_remote_wakeup(uint8_t rhport) #else U1CONbits.RESUME = 1; #endif - unsigned cnt = 25000000 / 1000; + + // FIXME: Assert RESUME signal correctly, requires device-specific handling + // For now we use a hardcoded cycle-based delay which attempts to delay 10ms + // at the most common CPU frequencies. On PIC32s we assume the loop body + // takes 3 cycles. On 16-bit PICs we assume the XC16 compiler is in use and + // use its `__delay_ms' function. + +#if CFG_TUSB_MCU == OPT_MCU_PIC32MM + uint32_t cnt = 24000000 / 1000 / 3; + while (cnt--) asm volatile("nop"); +#elif CFG_TUSB_MCU == OPT_MCU_PIC32MX + uint32_t cnt = 40000000 / 1000 / 3; while (cnt--) asm volatile("nop"); +#elif CFG_TUSB_MCU == OPT_MCU_PIC32MK + uint32_t cnt = 120000000 / 1000 / 3; + while (cnt--) asm volatile("nop"); +#else + __delay_ms(10); +#endif #if TU_PIC_INT_SIZE == 4 U1CONCLR = _U1CON_RESUME_MASK; -- cgit v1.3.1 From 0192b2a9b0a8a7a300326c27ebd59f15cb34790e Mon Sep 17 00:00:00 2001 From: Reimu NotMoe Date: Fri, 27 Dec 2024 00:59:45 +0800 Subject: dcd_pic: implement dcd_deinit() --- src/portable/microchip/pic/dcd_pic.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src/portable') diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c index 9ffeb0811..04c54059f 100644 --- a/src/portable/microchip/pic/dcd_pic.c +++ b/src/portable/microchip/pic/dcd_pic.c @@ -508,6 +508,19 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { return true; } +bool dcd_deinit(uint8_t rhport) +{ + U1CON = 0; + U1IE = 0; + U1OTGIE = 0; +#if TU_PIC_INT_SIZE == 4 + U1PWRCCLR = _U1PWRC_USUSPEND_MASK | _U1PWRC_USBPWR_MASK; +#else + U1PWRC &= ~(_U1PWRC_USUSPEND_MASK | _U1PWRC_USBPWR_MASK); +#endif + return true; +} + void dcd_int_enable(uint8_t rhport) { intr_enable(rhport); -- cgit v1.3.1 From 6e1140683140eb7bb80dfae0d207a920dec6d12c Mon Sep 17 00:00:00 2001 From: Reimu NotMoe Date: Fri, 27 Dec 2024 01:02:10 +0800 Subject: dcd_pic: handle EP0 timeout/stall correctly --- src/portable/microchip/pic/dcd_pic.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) (limited to 'src/portable') diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c index 04c54059f..4e0bd735e 100644 --- a/src/portable/microchip/pic/dcd_pic.c +++ b/src/portable/microchip/pic/dcd_pic.c @@ -316,12 +316,23 @@ static void prepare_next_setup_packet(uint8_t rhport) { const unsigned out_odd = _dcd.endpoint[0][0].odd; const unsigned in_odd = _dcd.endpoint[0][1].odd; - TU_ASSERT(0 == _dcd.bdt[0][0][out_odd].own, ); + + // Abandon any previous control transfers that might have been using EP0. + // Ordinarily, nothing actually needs abandoning, since the previous control + // transfer would have completed successfully prior to the host sending the + // next SETUP packet. However, in a timeout error case, or after an EP0 + // STALL event, one or more UOWN bits might still be set. If so, we should + // clear the UOWN bits, so the EP0 IN/OUT endpoints are in a known inactive + // state, ready for re-arming by the `dcd_edpt_xfer' function that will be + // called next. _dcd.bdt[0][0][out_odd].data = 0; + _dcd.bdt[0][0][out_odd].own = 0; _dcd.bdt[0][0][out_odd ^ 1].data = 1; _dcd.bdt[0][1][in_odd].data = 1; + _dcd.bdt[0][1][in_odd].own = 0; _dcd.bdt[0][1][in_odd ^ 1].data = 0; + _dcd.bdt[0][1][in_odd ^ 1].own = 0; dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_OUT), _dcd.setup_packet, sizeof(_dcd.setup_packet)); } -- cgit v1.3.1 From a4169114ec6acb07cf8e26a1718e61c0c7af69fa Mon Sep 17 00:00:00 2001 From: Reimu NotMoe Date: Fri, 27 Dec 2024 01:04:29 +0800 Subject: dcd_pic: let the user manage shared GPIO/VBUS pin --- src/portable/microchip/pic/dcd_pic.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/portable') diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c index 4e0bd735e..a4fa0e840 100644 --- a/src/portable/microchip/pic/dcd_pic.c +++ b/src/portable/microchip/pic/dcd_pic.c @@ -489,10 +489,6 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { intr_disable(rhport); intr_clear(rhport); -#if CFG_TUSB_MCU == OPT_MCU_PIC32MM - TRISBbits.TRISB6 = 1; -#endif - tu_memclr(&_dcd, sizeof(_dcd)); #if TU_PIC_INT_SIZE == 4 -- cgit v1.3.1 From 655092d568720188a3a34b9376a7ebcf274dab79 Mon Sep 17 00:00:00 2001 From: Reimu NotMoe Date: Fri, 27 Dec 2024 04:17:26 +0800 Subject: dcd_pic: check USBBUSY bit on PIC32s --- src/portable/microchip/pic/dcd_pic.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/portable') diff --git a/src/portable/microchip/pic/dcd_pic.c b/src/portable/microchip/pic/dcd_pic.c index a4fa0e840..b4a698199 100644 --- a/src/portable/microchip/pic/dcd_pic.c +++ b/src/portable/microchip/pic/dcd_pic.c @@ -492,6 +492,9 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { tu_memclr(&_dcd, sizeof(_dcd)); #if TU_PIC_INT_SIZE == 4 + // The USBBUSY bit is present on PIC32s and we're required to check it + // prior to powering on the USB peripheral (see DS61126F page 27) + while (U1PWRCbits.USBBUSY); U1PWRCSET = _U1PWRC_USBPWR_MASK; #else U1PWRCbits.USBPWR = 1; -- cgit v1.3.1 From b91d5ebb4509d02d108e249197884913698aac1c Mon Sep 17 00:00:00 2001 From: pschatzmann Date: Sat, 4 Jan 2025 22:20:46 +0100 Subject: rp2040 correct dcd_edpt_iso_activate --- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/portable') diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index af08b549d..b91dd38d5 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -496,6 +496,12 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { (void) rhport; const uint8_t ep_addr = ep_desc->bEndpointAddress; + + // init w/o allocate + const uint16_t mps = ep_desc->wMaxPacketSize; + uint16_t size = (uint16_t)tu_div_ceil(mps, 64) * 64u; + hw_endpoint_init(ep_addr, size, TUSB_XFER_ISOCHRONOUS); + // Fill in endpoint control register with buffer offset struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); TU_ASSERT(ep->hw_data_buf != NULL); // must be inited and buffer allocated -- cgit v1.3.1 From 5b32df5abd5667bce7541bed62658750d7f68232 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 20 Jan 2025 22:47:32 +0700 Subject: add s3 undefined speed note for racing issue with reset. fix dcd_event_sof() with frame number --- hw/bsp/espressif/boards/family.c | 12 +++--------- src/portable/nxp/khci/dcd_khci.c | 2 +- 2 files changed, 4 insertions(+), 10 deletions(-) (limited to 'src/portable') diff --git a/hw/bsp/espressif/boards/family.c b/hw/bsp/espressif/boards/family.c index 26e415d94..2f9ecfe4d 100644 --- a/hw/bsp/espressif/boards/family.c +++ b/hw/bsp/espressif/boards/family.c @@ -175,20 +175,14 @@ bool usb_init(void) { // maybe we can use USB_OTG_MODE_DEFAULT and switch using dwc2 driver #if CFG_TUD_ENABLED .otg_mode = USB_OTG_MODE_DEVICE, - .otg_speed = BOARD_TUD_RHPORT ? USB_PHY_SPEED_HIGH : USB_PHY_SPEED_FULL, #elif CFG_TUH_ENABLED .otg_mode = USB_OTG_MODE_HOST, - .otg_speed= BOARD_TUH_RHPORT ? USB_PHY_SPEED_HIGH : USB_PHY_SPEED_FULL, #endif + // https://github.com/hathach/tinyusb/issues/2943#issuecomment-2601888322 + // Set speed to undefined (auto-detect) to avoid timinng/racing issue with S3 with host such as macOS + .otg_speed = USB_PHY_SPEED_UNDEFINED, }; - // OTG IOs config - // const usb_phy_otg_io_conf_t otg_io_conf = USB_PHY_SELF_POWERED_DEVICE(config->vbus_monitor_io); - // if (config->self_powered) { - // phy_conf.otg_io_conf = &otg_io_conf; - // } - // ESP_RETURN_ON_ERROR(usb_new_phy(&phy_conf, &phy_hdl), TAG, "Install USB PHY failed"); - usb_new_phy(&phy_conf, &phy_hdl); return true; diff --git a/src/portable/nxp/khci/dcd_khci.c b/src/portable/nxp/khci/dcd_khci.c index 8398b09bf..3d5e195a9 100644 --- a/src/portable/nxp/khci/dcd_khci.c +++ b/src/portable/nxp/khci/dcd_khci.c @@ -565,7 +565,7 @@ void dcd_int_handler(uint8_t rhport) if (is & USB_ISTAT_SOFTOK_MASK) { KHCI->ISTAT = USB_ISTAT_SOFTOK_MASK; - dcd_event_bus_signal(rhport, DCD_EVENT_SOF, true); + dcd_event_sof(rhport, tu_u16(KHCI->FRMNUMH, KHCI->FRMNUML), true); } if (is & USB_ISTAT_STALL_MASK) { -- cgit v1.3.1 From 31071ccf0e27cc8b77ddb41417665ea82b2b9b35 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 23 Jan 2025 17:10:01 +0700 Subject: kind of work with zephyr with pca10056 with cmake -DBUILD_ZEPHYR --- .idea/cmake.xml | 3 +- .west/config | 2 +- examples/build_system/cmake/toolchain/common.cmake | 4 + examples/device/video_capture/src/main.c | 2 +- examples/host/msc_file_explorer/src/main.c | 6 +- examples/host/msc_file_explorer/src/msc_app.c | 20 +- examples/host/msc_file_explorer/src/msc_app.h | 35 +++ examples/west.yml | 12 - hw/bsp/family_support.cmake | 18 +- hw/bsp/nrf/boards/pca10095/board.cmake | 2 +- hw/bsp/nrf/family.c | 29 +- hw/bsp/nrf/family.cmake | 47 ++-- hw/bsp/nrf/family.mk | 32 +-- hw/bsp/nrf/nrfx_config.h | 46 ---- hw/bsp/nrf/nrfx_config/nrfx_config.h | 46 ++++ hw/bsp/nrf/nrfx_config/nrfx_glue.h | 294 +++++++++++++++++++++ hw/bsp/nrf/nrfx_config/nrfx_log.h | 135 ++++++++++ hw/bsp/nrf/nrfx_glue.h | 294 --------------------- hw/bsp/nrf/nrfx_log.h | 135 ---------- src/portable/nordic/nrf5x/dcd_nrf5x.c | 14 +- 20 files changed, 597 insertions(+), 579 deletions(-) create mode 100644 examples/host/msc_file_explorer/src/msc_app.h delete mode 100644 examples/west.yml delete mode 100644 hw/bsp/nrf/nrfx_config.h create mode 100644 hw/bsp/nrf/nrfx_config/nrfx_config.h create mode 100644 hw/bsp/nrf/nrfx_config/nrfx_glue.h create mode 100644 hw/bsp/nrf/nrfx_config/nrfx_log.h delete mode 100644 hw/bsp/nrf/nrfx_glue.h delete mode 100644 hw/bsp/nrf/nrfx_log.h (limited to 'src/portable') diff --git a/.idea/cmake.xml b/.idea/cmake.xml index e4c189251..b1a987a24 100644 --- a/.idea/cmake.xml +++ b/.idea/cmake.xml @@ -85,7 +85,8 @@ - + + diff --git a/.west/config b/.west/config index 2518007f6..f6f0d7a3d 100644 --- a/.west/config +++ b/.west/config @@ -1,5 +1,5 @@ [manifest] -path = examples +path = lib/zephyr file = west.yml [zephyr] diff --git a/examples/build_system/cmake/toolchain/common.cmake b/examples/build_system/cmake/toolchain/common.cmake index 4c181137b..7fe0aac4b 100644 --- a/examples/build_system/cmake/toolchain/common.cmake +++ b/examples/build_system/cmake/toolchain/common.cmake @@ -1,3 +1,7 @@ +if (BUILD_ZEPHYR) + return() +endif() + include(CMakePrintHelpers) # ---------------------------------------------------------------------------- diff --git a/examples/device/video_capture/src/main.c b/examples/device/video_capture/src/main.c index 8bb924c61..04d4af4e5 100644 --- a/examples/device/video_capture/src/main.c +++ b/examples/device/video_capture/src/main.c @@ -185,7 +185,7 @@ static void fill_color_bar(uint8_t* buffer, unsigned start_position) { #endif -void video_send_frame(void) { +static void video_send_frame(void) { static unsigned start_ms = 0; static unsigned already_sent = 0; diff --git a/examples/host/msc_file_explorer/src/main.c b/examples/host/msc_file_explorer/src/main.c index 9509035b4..8197c3c8d 100644 --- a/examples/host/msc_file_explorer/src/main.c +++ b/examples/host/msc_file_explorer/src/main.c @@ -62,15 +62,13 @@ #include "bsp/board_api.h" #include "tusb.h" +#include "msc_app.h" + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF PROTYPES //--------------------------------------------------------------------+ void led_blinking_task(void); -// from msc_app.c -extern bool msc_app_init(void); -extern void msc_app_task(void); - /*------------- MAIN -------------*/ int main(void) { board_init(); diff --git a/examples/host/msc_file_explorer/src/msc_app.c b/examples/host/msc_file_explorer/src/msc_app.c index 035d74689..226c870ea 100644 --- a/examples/host/msc_file_explorer/src/msc_app.c +++ b/examples/host/msc_file_explorer/src/msc_app.c @@ -67,7 +67,9 @@ bool cli_init(void); bool msc_app_init(void) { - for(size_t i=0; i 0 ) @@ -99,8 +103,7 @@ void msc_app_task(void) // //--------------------------------------------------------------------+ -bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) -{ +static bool inquiry_complete_cb(uint8_t dev_addr, tuh_msc_complete_data_t const * cb_data) { msc_cbw_t const* cbw = cb_data->cbw; msc_csw_t const* csw = cb_data->csw; @@ -294,18 +297,11 @@ void cli_cmd_mkdir(EmbeddedCli *cli, char *args, void *context); void cli_cmd_mv(EmbeddedCli *cli, char *args, void *context); void cli_cmd_rm(EmbeddedCli *cli, char *args, void *context); -void cli_write_char(EmbeddedCli *cli, char c) -{ +static void cli_write_char(EmbeddedCli *cli, char c) { (void) cli; putchar((int) c); } -void cli_cmd_unknown(EmbeddedCli *cli, CliCommand *command) -{ - (void) cli; - printf("%s: command not found\r\n", command->name); -} - bool cli_init(void) { EmbeddedCliConfig *config = embeddedCliDefaultConfig(); diff --git a/examples/host/msc_file_explorer/src/msc_app.h b/examples/host/msc_file_explorer/src/msc_app.h new file mode 100644 index 000000000..3ba03d0dc --- /dev/null +++ b/examples/host/msc_file_explorer/src/msc_app.h @@ -0,0 +1,35 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ +#ifndef MSC_APP_H +#define MSC_APP_H + +#include + +bool msc_app_init(void); +void msc_app_task(void); + + +#endif diff --git a/examples/west.yml b/examples/west.yml deleted file mode 100644 index 4e2160202..000000000 --- a/examples/west.yml +++ /dev/null @@ -1,12 +0,0 @@ -manifest: - remotes: - - name: zephyrproject-rtos - url-base: https://github.com/zephyrproject-rtos - projects: - - name: zephyr - remote: zephyrproject-rtos - revision: v4.0.0 - path: lib/zephyr - import: true - self: - path: . diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index 15baf0294..e32bb1689 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -170,7 +170,7 @@ function(family_add_rtos TARGET RTOS) elseif (RTOS STREQUAL "zephyr") target_compile_definitions(${TARGET} PUBLIC CFG_TUSB_OS=OPT_OS_ZEPHYR) target_include_directories(${TARGET} PUBLIC ${ZEPHYR_BASE}/include) - target_link_libraries(${TARGET} PUBLIC zephyr_interface kernel) +# target_link_libraries(${TARGET} PUBLIC kernel) endif () endfunction() @@ -201,12 +201,9 @@ function(family_configure_common TARGET RTOS) target_compile_definitions(${TARGET} PUBLIC LOGGER_${LOGGER}) # Add segger rtt to example if(LOGGER STREQUAL "RTT" OR LOGGER STREQUAL "rtt") - if (NOT TARGET segger_rtt) - add_library(segger_rtt STATIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c) - target_include_directories(segger_rtt PUBLIC ${TOP}/lib/SEGGER_RTT/RTT) -# target_compile_definitions(segger_rtt PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) - endif() - target_link_libraries(${TARGET} PUBLIC segger_rtt) + target_sources(${TARGET} PUBLIC ${TOP}/lib/SEGGER_RTT/RTT/SEGGER_RTT.c) + target_include_directories(${TARGET} PUBLIC ${TOP}/lib/SEGGER_RTT/RTT) +# target_compile_definitions(${TARGET} PUBLIC SEGGER_RTT_MODE_DEFAULT=SEGGER_RTT_MODE_BLOCK_IF_FIFO_FULL) endif () endif () @@ -239,7 +236,8 @@ function(family_configure_common TARGET RTOS) -Wmissing-prototypes ) target_link_options(${TARGET} PUBLIC "LINKER:-Map=$.map") - if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 AND NO_WARN_RWX_SEGMENTS_SUPPORTED) + if (CMAKE_C_COMPILER_ID STREQUAL "GNU" AND CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 + AND NO_WARN_RWX_SEGMENTS_SUPPORTED AND (NOT BUILD_ZEPHYR)) target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") endif () elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") @@ -255,7 +253,7 @@ function(family_configure_common TARGET RTOS) # endif () endfunction() -# Add tinyusb to target with RTOS +# Add tinyusb to target (TODO remove RTOS) function(family_add_tinyusb TARGET OPT_MCU RTOS) # tinyusb's CMakeList.txt add_subdirectory(${TOP}/src ${CMAKE_CURRENT_BINARY_DIR}/tinyusb) @@ -364,7 +362,7 @@ function(family_add_default_example_warnings TARGET) if (CMAKE_C_COMPILER_ID STREQUAL "GNU") if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0 AND NO_WARN_RWX_SEGMENTS_SUPPORTED) -# target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") + target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") endif() # GCC 10 diff --git a/hw/bsp/nrf/boards/pca10095/board.cmake b/hw/bsp/nrf/boards/pca10095/board.cmake index 95dd30969..6d183dde6 100644 --- a/hw/bsp/nrf/boards/pca10095/board.cmake +++ b/hw/bsp/nrf/boards/pca10095/board.cmake @@ -2,6 +2,6 @@ set(MCU_VARIANT nrf5340_application) function(update_board TARGET) target_sources(${TARGET} PRIVATE - ${NRFX_DIR}/drivers/src/nrfx_usbreg.c + ${NRFX_PATH}/drivers/src/nrfx_usbreg.c ) endfunction() diff --git a/hw/bsp/nrf/family.c b/hw/bsp/nrf/family.c index 2c3413b9e..298ca2302 100644 --- a/hw/bsp/nrf/family.c +++ b/hw/bsp/nrf/family.c @@ -44,10 +44,10 @@ #include "nrfx.h" #include "hal/nrf_gpio.h" -#include "drivers/include/nrfx_gpiote.h" -#include "drivers/include/nrfx_power.h" -#include "drivers/include/nrfx_uarte.h" -#include "drivers/include/nrfx_spim.h" +#include "nrfx_gpiote.h" +#include "nrfx_power.h" +#include "nrfx_uarte.h" +#include "nrfx_spim.h" #ifdef SOFTDEVICE_PRESENT #include "nrf_sdm.h" @@ -67,8 +67,6 @@ #define NRFX_VER 3 #endif -extern void nrfx_isr(const void *irq_handler); - //--------------------------------------------------------------------+ // Forward USB interrupt events to TinyUSB IRQ Handler //--------------------------------------------------------------------+ @@ -148,12 +146,10 @@ void board_init(void) { // irq_enable(USBREGULATOR_IRQn); #endif - // IRQ_CONNECT(CLOCK_POWER_IRQn, 0, nrfx_isr, nrfx_power_irq_handler, 0); - /* USB device controller access from devicetree */ - // #define DT_DRV_COMPAT nordic_nrf_usbd - // IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), nrfx_isr, nrf_usbd_common_irq_handler, 0); - + #define DT_DRV_COMPAT nordic_nrf_usbd + IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), nrfx_isr, USBD_IRQHandler, 0); + irq_enable(DT_INST_IRQN(0)); #endif // UART @@ -187,7 +183,7 @@ void board_init(void) { }; #endif - nrfx_uarte_init(&_uart_id, &uart_cfg, NULL); //uart_handler); + nrfx_uarte_init(&_uart_id, &uart_cfg, NULL); //------------- USB -------------// #if CFG_TUD_ENABLED @@ -231,8 +227,12 @@ void board_init(void) { #endif } - if ( usb_reg & VBUSDETECT_Msk ) tusb_hal_nrf_power_event(USB_EVT_DETECTED); - if ( usb_reg & OUTPUTRDY_Msk ) tusb_hal_nrf_power_event(USB_EVT_READY); + if ( usb_reg & VBUSDETECT_Msk ) { + tusb_hal_nrf_power_event(USB_EVT_DETECTED); + } + if ( usb_reg & OUTPUTRDY_Msk ) { + tusb_hal_nrf_power_event(USB_EVT_READY); + } #endif #if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 @@ -244,7 +244,6 @@ void board_init(void) { //--------------------------------------------------------------------+ // Board porting API //--------------------------------------------------------------------+ - void board_led_write(bool state) { nrf_gpio_pin_write(LED_PIN, state ? LED_STATE_ON : (1 - LED_STATE_ON)); } diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 30561cdf5..1e7a4fe82 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -1,6 +1,6 @@ include_guard() -set(NRFX_DIR ${TOP}/hw/mcu/nordic/nrfx) +set(NRFX_PATH ${TOP}/hw/mcu/nordic/nrfx) set(CMSIS_DIR ${TOP}/lib/CMSIS_5) # include board specific @@ -25,6 +25,10 @@ set(FAMILY_MCUS NRF5X CACHE INTERNAL "") #------------------------------------ # only need to be built ONCE for all examples function(add_board_target BOARD_TARGET) + if (BUILD_ZEPHYR) + return() + endif () + if (TARGET ${BOARD_TARGET}) return() endif () @@ -40,18 +44,18 @@ function(add_board_target BOARD_TARGET) endif () if (NOT DEFINED STARTUP_FILE_${CMAKE_C_COMPILER_ID}) - set(STARTUP_FILE_GNU ${NRFX_DIR}/mdk/gcc_startup_${MCU_VARIANT}.S) + set(STARTUP_FILE_GNU ${NRFX_PATH}/mdk/gcc_startup_${MCU_VARIANT}.S) set(STARTUP_FILE_Clang ${STARTUP_FILE_GNU}) endif () add_library(${BOARD_TARGET} STATIC - ${NRFX_DIR}/helpers/nrfx_flag32_allocator.c - ${NRFX_DIR}/drivers/src/nrfx_gpiote.c - ${NRFX_DIR}/drivers/src/nrfx_power.c - ${NRFX_DIR}/drivers/src/nrfx_spim.c - ${NRFX_DIR}/drivers/src/nrfx_uarte.c - ${NRFX_DIR}/mdk/system_${MCU_VARIANT}.c - ${NRFX_DIR}/soc/nrfx_atomic.c + ${NRFX_PATH}/helpers/nrfx_flag32_allocator.c + ${NRFX_PATH}/drivers/src/nrfx_gpiote.c + ${NRFX_PATH}/drivers/src/nrfx_power.c + ${NRFX_PATH}/drivers/src/nrfx_spim.c + ${NRFX_PATH}/drivers/src/nrfx_uarte.c + ${NRFX_PATH}/mdk/system_${MCU_VARIANT}.c + ${NRFX_PATH}/soc/nrfx_atomic.c ${STARTUP_FILE_${CMAKE_C_COMPILER_ID}} ) string(TOUPPER "${MCU_VARIANT_XXAA}" MCU_VARIANT_XXAA_UPPER) @@ -67,12 +71,10 @@ function(add_board_target BOARD_TARGET) endif () target_include_directories(${BOARD_TARGET} PUBLIC - ${CMAKE_CURRENT_FUNCTION_LIST_DIR} - ${NRFX_DIR} - ${NRFX_DIR}/mdk - ${NRFX_DIR}/hal - ${NRFX_DIR}/drivers/include - ${NRFX_DIR}/drivers/src + ${CMAKE_CURRENT_FUNCTION_LIST_DIR}/nrfx_config + ${NRFX_PATH} + ${NRFX_PATH}/mdk + ${NRFX_PATH}/drivers/include ${CMSIS_DIR}/CMSIS/Core/Include ) @@ -81,14 +83,14 @@ function(add_board_target BOARD_TARGET) if (CMAKE_C_COMPILER_ID STREQUAL "GNU") target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" - -L${NRFX_DIR}/mdk + -L${NRFX_PATH}/mdk --specs=nosys.specs --specs=nano.specs -nostartfiles ) elseif (CMAKE_C_COMPILER_ID STREQUAL "Clang") target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" - -L${NRFX_DIR}/mdk + -L${NRFX_PATH}/mdk ) elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") target_link_options(${BOARD_TARGET} PUBLIC @@ -113,6 +115,9 @@ endfunction() function(family_configure_example TARGET RTOS) # Board target add_board_target(board_${BOARD}) + if (NOT BUILD_ZEPHYR) + target_link_libraries(${TARGET} PUBLIC board_${BOARD}) + endif () family_configure_common(${TARGET} ${RTOS}) @@ -132,16 +137,10 @@ function(family_configure_example TARGET RTOS) # Add TinyUSB target and port source family_add_tinyusb(${TARGET} OPT_MCU_NRF5X ${RTOS}) - target_sources(${TARGET} PUBLIC + target_sources(${TARGET} PRIVATE ${TOP}/src/portable/nordic/nrf5x/dcd_nrf5x.c ) -# if (BUILD_ZEPHYR) -# target_link_libraries(${TARGET} PUBLIC zephyr_interface kernel) -# elseif () - target_link_libraries(${TARGET} PUBLIC board_${BOARD}) -# endif () - # Flashing # family_add_bin_hex(${TARGET}) family_flash_jlink(${TARGET}) diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk index b3c05e6db..f5a3f5c45 100644 --- a/hw/bsp/nrf/family.mk +++ b/hw/bsp/nrf/family.mk @@ -1,6 +1,6 @@ UF2_FAMILY_ID = 0xADA52840 -NRFX_DIR = hw/mcu/nordic/nrfx +NRFX_PATH = hw/mcu/nordic/nrfx include $(TOP)/$(BOARD_PATH)/board.mk @@ -28,31 +28,31 @@ CFLAGS_GCC += \ LDFLAGS_GCC += \ -nostartfiles \ --specs=nosys.specs --specs=nano.specs \ - -L$(TOP)/${NRFX_DIR}/mdk + -L$(TOP)/${NRFX_PATH}/mdk LDFLAGS_CLANG += \ - -L$(TOP)/${NRFX_DIR}/mdk \ + -L$(TOP)/${NRFX_PATH}/mdk \ SRC_C += \ src/portable/nordic/nrf5x/dcd_nrf5x.c \ - ${NRFX_DIR}/helpers/nrfx_flag32_allocator.c \ - ${NRFX_DIR}/drivers/src/nrfx_gpiote.c \ - ${NRFX_DIR}/drivers/src/nrfx_power.c \ - ${NRFX_DIR}/drivers/src/nrfx_spim.c \ - ${NRFX_DIR}/drivers/src/nrfx_uarte.c \ - ${NRFX_DIR}/mdk/system_$(MCU_VARIANT).c \ - ${NRFX_DIR}/soc/nrfx_atomic.c + ${NRFX_PATH}/helpers/nrfx_flag32_allocator.c \ + ${NRFX_PATH}/drivers/src/nrfx_gpiote.c \ + ${NRFX_PATH}/drivers/src/nrfx_power.c \ + ${NRFX_PATH}/drivers/src/nrfx_spim.c \ + ${NRFX_PATH}/drivers/src/nrfx_uarte.c \ + ${NRFX_PATH}/mdk/system_$(MCU_VARIANT).c \ + ${NRFX_PATH}/soc/nrfx_atomic.c INC += \ $(TOP)/$(BOARD_PATH) \ $(TOP)/lib/CMSIS_5/CMSIS/Core/Include \ - $(TOP)/${NRFX_DIR} \ - $(TOP)/${NRFX_DIR}/mdk \ - $(TOP)/${NRFX_DIR}/hal \ - $(TOP)/${NRFX_DIR}/drivers/include \ - $(TOP)/${NRFX_DIR}/drivers/src \ + $(TOP)/${NRFX_PATH} \ + $(TOP)/${NRFX_PATH}/mdk \ + $(TOP)/${NRFX_PATH}/hal \ + $(TOP)/${NRFX_PATH}/drivers/include \ + $(TOP)/${NRFX_PATH}/drivers/src \ -SRC_S += ${NRFX_DIR}/mdk/gcc_startup_$(MCU_VARIANT).S +SRC_S += ${NRFX_PATH}/mdk/gcc_startup_$(MCU_VARIANT).S ASFLAGS += -D__HEAP_SIZE=0 diff --git a/hw/bsp/nrf/nrfx_config.h b/hw/bsp/nrf/nrfx_config.h deleted file mode 100644 index fbec4192b..000000000 --- a/hw/bsp/nrf/nrfx_config.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef NRFX_CONFIG_H__ -#define NRFX_CONFIG_H__ - -#define NRFX_POWER_ENABLED 1 -#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7 - -#define NRFX_CLOCK_ENABLED 0 -#define NRFX_GPIOTE_ENABLED 1 -#define NRFX_GPIOTE0_ENABLED 1 - -#define NRFX_UARTE_ENABLED 1 -#define NRFX_UARTE0_ENABLED 1 - -#define NRFX_SPIM_ENABLED 1 -#define NRFX_SPIM1_ENABLED 1 // use SPI1 since nrf5340 share uart with spi - -#define NRFX_PRS_ENABLED 0 -#define NRFX_USBREG_ENABLED 1 - -#if defined(NRF51) -#include -#elif defined(NRF52805_XXAA) -#include -#elif defined(NRF52810_XXAA) -#include -#elif defined(NRF52811_XXAA) -#include -#elif defined(NRF52820_XXAA) -#include -#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) -#include -#elif defined(NRF52833_XXAA) -#include -#elif defined(NRF52840_XXAA) -#include -#elif defined(NRF5340_XXAA_APPLICATION) -#include -#elif defined(NRF5340_XXAA_NETWORK) - #include -#elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA) - #include -#else - #error "Unknown device." -#endif - -#endif // NRFX_CONFIG_H__ diff --git a/hw/bsp/nrf/nrfx_config/nrfx_config.h b/hw/bsp/nrf/nrfx_config/nrfx_config.h new file mode 100644 index 000000000..fbec4192b --- /dev/null +++ b/hw/bsp/nrf/nrfx_config/nrfx_config.h @@ -0,0 +1,46 @@ +#ifndef NRFX_CONFIG_H__ +#define NRFX_CONFIG_H__ + +#define NRFX_POWER_ENABLED 1 +#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY 7 + +#define NRFX_CLOCK_ENABLED 0 +#define NRFX_GPIOTE_ENABLED 1 +#define NRFX_GPIOTE0_ENABLED 1 + +#define NRFX_UARTE_ENABLED 1 +#define NRFX_UARTE0_ENABLED 1 + +#define NRFX_SPIM_ENABLED 1 +#define NRFX_SPIM1_ENABLED 1 // use SPI1 since nrf5340 share uart with spi + +#define NRFX_PRS_ENABLED 0 +#define NRFX_USBREG_ENABLED 1 + +#if defined(NRF51) +#include +#elif defined(NRF52805_XXAA) +#include +#elif defined(NRF52810_XXAA) +#include +#elif defined(NRF52811_XXAA) +#include +#elif defined(NRF52820_XXAA) +#include +#elif defined(NRF52832_XXAA) || defined (NRF52832_XXAB) +#include +#elif defined(NRF52833_XXAA) +#include +#elif defined(NRF52840_XXAA) +#include +#elif defined(NRF5340_XXAA_APPLICATION) +#include +#elif defined(NRF5340_XXAA_NETWORK) + #include +#elif defined(NRF9120_XXAA) || defined(NRF9160_XXAA) + #include +#else + #error "Unknown device." +#endif + +#endif // NRFX_CONFIG_H__ diff --git a/hw/bsp/nrf/nrfx_config/nrfx_glue.h b/hw/bsp/nrf/nrfx_config/nrfx_glue.h new file mode 100644 index 000000000..bc3b3689b --- /dev/null +++ b/hw/bsp/nrf/nrfx_config/nrfx_glue.h @@ -0,0 +1,294 @@ +/* + * Copyright (c) 2017 - 2024, Nordic Semiconductor ASA + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_GLUE_H__ +#define NRFX_GLUE_H__ + +// THIS IS A TEMPLATE FILE. +// It should be copied to a suitable location within the host environment into +// which nrfx is integrated, and the following macros should be provided with +// appropriate implementations. +// And this comment should be removed from the customized file. + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_glue nrfx_glue.h + * @{ + * @ingroup nrfx + * + * @brief This file contains macros that should be implemented according to + * the needs of the host environment into which @em nrfx is integrated. + */ + +// Uncomment this line to use the standard MDK way of binding IRQ handlers +// at linking time. +#include + +//------------------------------------------------------------------------------ + +/** + * @brief Macro for placing a runtime assertion. + * + * @param expression Expression to be evaluated. + */ +#define NRFX_ASSERT(expression) + +/** + * @brief Macro for placing a compile time assertion. + * + * @param expression Expression to be evaluated. + */ +#define NRFX_STATIC_ASSERT(expression) + +//------------------------------------------------------------------------------ + +/** + * @brief Macro for setting the priority of a specific IRQ. + * + * @param irq_number IRQ number. + * @param priority Priority to be set. + */ +#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) _NRFX_IRQ_PRIORITY_SET(irq_number, priority) +static inline void _NRFX_IRQ_PRIORITY_SET(IRQn_Type irq_number, + uint8_t priority) +{ + NRFX_ASSERT(INTERRUPT_PRIORITY_IS_VALID(priority)); + NVIC_SetPriority(irq_number, priority); +} + +/** + * @brief Macro for enabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_ENABLE(irq_number) _NRFX_IRQ_ENABLE(irq_number) +static inline void _NRFX_IRQ_ENABLE(IRQn_Type irq_number) +{ + NVIC_ClearPendingIRQ(irq_number); + NVIC_EnableIRQ(irq_number); +} + +/** + * @brief Macro for checking if a specific IRQ is enabled. + * + * @param irq_number IRQ number. + * + * @retval true If the IRQ is enabled. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_ENABLED(irq_number) _NRFX_IRQ_IS_ENABLED(irq_number) +static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number) +{ + return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32))); +} + +/** + * @brief Macro for disabling a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_DISABLE(irq_number) _NRFX_IRQ_DISABLE(irq_number) +static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number) +{ + NVIC_DisableIRQ(irq_number); +} + +/** + * @brief Macro for setting a specific IRQ as pending. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_SET(irq_number) _NRFX_IRQ_PENDING_SET(irq_number) +static inline void _NRFX_IRQ_PENDING_SET(IRQn_Type irq_number) +{ + NVIC_SetPendingIRQ(irq_number); +} + +/** + * @brief Macro for clearing the pending status of a specific IRQ. + * + * @param irq_number IRQ number. + */ +#define NRFX_IRQ_PENDING_CLEAR(irq_number) _NRFX_IRQ_PENDING_CLEAR(irq_number) +static inline void _NRFX_IRQ_PENDING_CLEAR(IRQn_Type irq_number) +{ + NVIC_ClearPendingIRQ(irq_number); +} + +/** + * @brief Macro for checking the pending status of a specific IRQ. + * + * @retval true If the IRQ is pending. + * @retval false Otherwise. + */ +#define NRFX_IRQ_IS_PENDING(irq_number) _NRFX_IRQ_IS_PENDING(irq_number) +static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number) +{ + return (NVIC_GetPendingIRQ(irq_number) == 1); +} + +/** @brief Macro for entering into a critical section. */ +#define NRFX_CRITICAL_SECTION_ENTER() + +/** @brief Macro for exiting from a critical section. */ +#define NRFX_CRITICAL_SECTION_EXIT() + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that + * @ref nrfx_coredep_delay_us uses a precise DWT-based solution. + * A compilation error is generated if the DWT unit is not present + * in the SoC used. + */ +#define NRFX_DELAY_DWT_BASED 0 + +/** + * @brief Macro for delaying the code execution for at least the specified time. + * + * @param us_time Number of microseconds to wait. + */ +#include +#define NRFX_DELAY_US(us_time) nrfx_coredep_delay_us(us_time) + +//------------------------------------------------------------------------------ + +/** + * @brief When set to a non-zero value, this macro specifies that the + * @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined + * in a customized way and the default definitions from @c + * should not be used. + */ +#define NRFX_CUSTOM_ERROR_CODES 0 + +//------------------------------------------------------------------------------ + +/** + * @brief Bitmask defining PPI channels reserved to be used outside of nrfx. + */ +#define NRFX_PPI_CHANNELS_USED 0 + +/** + * @brief Bitmask defining PPI groups reserved to be used outside of nrfx. + */ +#define NRFX_PPI_GROUPS_USED 0 + +/** + * @brief Bitmask defining SWI instances reserved to be used outside of nrfx. + */ +#define NRFX_SWI_USED 0 + +/** + * @brief Bitmask defining TIMER instances reserved to be used outside of nrfx. + */ +#define NRFX_TIMERS_USED 0 + +/** @} */ + +//------------------------------------------------------------------------------ + +#include + +/** + * @brief Atomic 32 bit unsigned type. + */ +#define nrfx_atomic_t nrfx_atomic_u32_t + +/** + * @brief Stores value to an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value to store. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_STORE(p_data, value) nrfx_atomic_u32_fetch_store(p_data, value) + +/** + * @brief Performs logical OR operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of OR operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_OR(p_data, value) nrfx_atomic_u32_fetch_or(p_data, value) + +/** + * @brief Performs logical AND operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of AND operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_AND(p_data, value) nrfx_atomic_u32_fetch_and(p_data, value) + +/** + * @brief Performs logical XOR operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of XOR operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_XOR(p_data, value) nrfx_atomic_u32_fetch_xor(p_data, value) + +/** + * @brief Performs logical ADD operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of ADD operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_ADD(p_data, value) nrfx_atomic_u32_fetch_add(p_data, value) + +/** + * @brief Performs logical SUB operation on an atomic object and returns previously stored value. + * + * @param[in] p_data Atomic memory pointer. + * @param[in] value Value of second operand of SUB operation. + * + * @return Old value stored into atomic object. + */ +#define NRFX_ATOMIC_FETCH_SUB(p_data, value) nrfx_atomic_u32_fetch_sub(p_data, value) + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_GLUE_H__ diff --git a/hw/bsp/nrf/nrfx_config/nrfx_log.h b/hw/bsp/nrf/nrfx_config/nrfx_log.h new file mode 100644 index 000000000..3bc1b424e --- /dev/null +++ b/hw/bsp/nrf/nrfx_config/nrfx_log.h @@ -0,0 +1,135 @@ +/* + * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef NRFX_LOG_H__ +#define NRFX_LOG_H__ + +// THIS IS A TEMPLATE FILE. +// It should be copied to a suitable location within the host environment into +// which nrfx is integrated, and the following macros should be provided with +// appropriate implementations. +// And this comment should be removed from the customized file. + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrfx_log nrfx_log.h + * @{ + * @ingroup nrfx + * + * @brief This file contains macros that should be implemented according to + * the needs of the host environment into which @em nrfx is integrated. + */ + +/** + * @brief Macro for logging a message with the severity level ERROR. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_ERROR(format, ...) + +/** + * @brief Macro for logging a message with the severity level WARNING. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_WARNING(format, ...) + +/** + * @brief Macro for logging a message with the severity level INFO. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_INFO(format, ...) + +/** + * @brief Macro for logging a message with the severity level DEBUG. + * + * @param format printf-style format string, optionally followed by arguments + * to be formatted and inserted in the resulting string. + */ +#define NRFX_LOG_DEBUG(format, ...) + + +/** + * @brief Macro for logging a memory dump with the severity level ERROR. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level WARNING. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level INFO. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_INFO(p_memory, length) + +/** + * @brief Macro for logging a memory dump with the severity level DEBUG. + * + * @param[in] p_memory Pointer to the memory region to be dumped. + * @param[in] length Length of the memory region in bytes. + */ +#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length) + + +/** + * @brief Macro for getting the textual representation of a given error code. + * + * @param[in] error_code Error code. + * + * @return String containing the textual representation of the error code. + */ +#define NRFX_LOG_ERROR_STRING_GET(error_code) + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRFX_LOG_H__ diff --git a/hw/bsp/nrf/nrfx_glue.h b/hw/bsp/nrf/nrfx_glue.h deleted file mode 100644 index bc3b3689b..000000000 --- a/hw/bsp/nrf/nrfx_glue.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - * Copyright (c) 2017 - 2024, Nordic Semiconductor ASA - * All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef NRFX_GLUE_H__ -#define NRFX_GLUE_H__ - -// THIS IS A TEMPLATE FILE. -// It should be copied to a suitable location within the host environment into -// which nrfx is integrated, and the following macros should be provided with -// appropriate implementations. -// And this comment should be removed from the customized file. - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_glue nrfx_glue.h - * @{ - * @ingroup nrfx - * - * @brief This file contains macros that should be implemented according to - * the needs of the host environment into which @em nrfx is integrated. - */ - -// Uncomment this line to use the standard MDK way of binding IRQ handlers -// at linking time. -#include - -//------------------------------------------------------------------------------ - -/** - * @brief Macro for placing a runtime assertion. - * - * @param expression Expression to be evaluated. - */ -#define NRFX_ASSERT(expression) - -/** - * @brief Macro for placing a compile time assertion. - * - * @param expression Expression to be evaluated. - */ -#define NRFX_STATIC_ASSERT(expression) - -//------------------------------------------------------------------------------ - -/** - * @brief Macro for setting the priority of a specific IRQ. - * - * @param irq_number IRQ number. - * @param priority Priority to be set. - */ -#define NRFX_IRQ_PRIORITY_SET(irq_number, priority) _NRFX_IRQ_PRIORITY_SET(irq_number, priority) -static inline void _NRFX_IRQ_PRIORITY_SET(IRQn_Type irq_number, - uint8_t priority) -{ - NRFX_ASSERT(INTERRUPT_PRIORITY_IS_VALID(priority)); - NVIC_SetPriority(irq_number, priority); -} - -/** - * @brief Macro for enabling a specific IRQ. - * - * @param irq_number IRQ number. - */ -#define NRFX_IRQ_ENABLE(irq_number) _NRFX_IRQ_ENABLE(irq_number) -static inline void _NRFX_IRQ_ENABLE(IRQn_Type irq_number) -{ - NVIC_ClearPendingIRQ(irq_number); - NVIC_EnableIRQ(irq_number); -} - -/** - * @brief Macro for checking if a specific IRQ is enabled. - * - * @param irq_number IRQ number. - * - * @retval true If the IRQ is enabled. - * @retval false Otherwise. - */ -#define NRFX_IRQ_IS_ENABLED(irq_number) _NRFX_IRQ_IS_ENABLED(irq_number) -static inline bool _NRFX_IRQ_IS_ENABLED(IRQn_Type irq_number) -{ - return 0 != (NVIC->ISER[irq_number / 32] & (1UL << (irq_number % 32))); -} - -/** - * @brief Macro for disabling a specific IRQ. - * - * @param irq_number IRQ number. - */ -#define NRFX_IRQ_DISABLE(irq_number) _NRFX_IRQ_DISABLE(irq_number) -static inline void _NRFX_IRQ_DISABLE(IRQn_Type irq_number) -{ - NVIC_DisableIRQ(irq_number); -} - -/** - * @brief Macro for setting a specific IRQ as pending. - * - * @param irq_number IRQ number. - */ -#define NRFX_IRQ_PENDING_SET(irq_number) _NRFX_IRQ_PENDING_SET(irq_number) -static inline void _NRFX_IRQ_PENDING_SET(IRQn_Type irq_number) -{ - NVIC_SetPendingIRQ(irq_number); -} - -/** - * @brief Macro for clearing the pending status of a specific IRQ. - * - * @param irq_number IRQ number. - */ -#define NRFX_IRQ_PENDING_CLEAR(irq_number) _NRFX_IRQ_PENDING_CLEAR(irq_number) -static inline void _NRFX_IRQ_PENDING_CLEAR(IRQn_Type irq_number) -{ - NVIC_ClearPendingIRQ(irq_number); -} - -/** - * @brief Macro for checking the pending status of a specific IRQ. - * - * @retval true If the IRQ is pending. - * @retval false Otherwise. - */ -#define NRFX_IRQ_IS_PENDING(irq_number) _NRFX_IRQ_IS_PENDING(irq_number) -static inline bool _NRFX_IRQ_IS_PENDING(IRQn_Type irq_number) -{ - return (NVIC_GetPendingIRQ(irq_number) == 1); -} - -/** @brief Macro for entering into a critical section. */ -#define NRFX_CRITICAL_SECTION_ENTER() - -/** @brief Macro for exiting from a critical section. */ -#define NRFX_CRITICAL_SECTION_EXIT() - -//------------------------------------------------------------------------------ - -/** - * @brief When set to a non-zero value, this macro specifies that - * @ref nrfx_coredep_delay_us uses a precise DWT-based solution. - * A compilation error is generated if the DWT unit is not present - * in the SoC used. - */ -#define NRFX_DELAY_DWT_BASED 0 - -/** - * @brief Macro for delaying the code execution for at least the specified time. - * - * @param us_time Number of microseconds to wait. - */ -#include -#define NRFX_DELAY_US(us_time) nrfx_coredep_delay_us(us_time) - -//------------------------------------------------------------------------------ - -/** - * @brief When set to a non-zero value, this macro specifies that the - * @ref nrfx_error_codes and the @ref nrfx_err_t type itself are defined - * in a customized way and the default definitions from @c - * should not be used. - */ -#define NRFX_CUSTOM_ERROR_CODES 0 - -//------------------------------------------------------------------------------ - -/** - * @brief Bitmask defining PPI channels reserved to be used outside of nrfx. - */ -#define NRFX_PPI_CHANNELS_USED 0 - -/** - * @brief Bitmask defining PPI groups reserved to be used outside of nrfx. - */ -#define NRFX_PPI_GROUPS_USED 0 - -/** - * @brief Bitmask defining SWI instances reserved to be used outside of nrfx. - */ -#define NRFX_SWI_USED 0 - -/** - * @brief Bitmask defining TIMER instances reserved to be used outside of nrfx. - */ -#define NRFX_TIMERS_USED 0 - -/** @} */ - -//------------------------------------------------------------------------------ - -#include - -/** - * @brief Atomic 32 bit unsigned type. - */ -#define nrfx_atomic_t nrfx_atomic_u32_t - -/** - * @brief Stores value to an atomic object and returns previously stored value. - * - * @param[in] p_data Atomic memory pointer. - * @param[in] value Value to store. - * - * @return Old value stored into atomic object. - */ -#define NRFX_ATOMIC_FETCH_STORE(p_data, value) nrfx_atomic_u32_fetch_store(p_data, value) - -/** - * @brief Performs logical OR operation on an atomic object and returns previously stored value. - * - * @param[in] p_data Atomic memory pointer. - * @param[in] value Value of second operand of OR operation. - * - * @return Old value stored into atomic object. - */ -#define NRFX_ATOMIC_FETCH_OR(p_data, value) nrfx_atomic_u32_fetch_or(p_data, value) - -/** - * @brief Performs logical AND operation on an atomic object and returns previously stored value. - * - * @param[in] p_data Atomic memory pointer. - * @param[in] value Value of second operand of AND operation. - * - * @return Old value stored into atomic object. - */ -#define NRFX_ATOMIC_FETCH_AND(p_data, value) nrfx_atomic_u32_fetch_and(p_data, value) - -/** - * @brief Performs logical XOR operation on an atomic object and returns previously stored value. - * - * @param[in] p_data Atomic memory pointer. - * @param[in] value Value of second operand of XOR operation. - * - * @return Old value stored into atomic object. - */ -#define NRFX_ATOMIC_FETCH_XOR(p_data, value) nrfx_atomic_u32_fetch_xor(p_data, value) - -/** - * @brief Performs logical ADD operation on an atomic object and returns previously stored value. - * - * @param[in] p_data Atomic memory pointer. - * @param[in] value Value of second operand of ADD operation. - * - * @return Old value stored into atomic object. - */ -#define NRFX_ATOMIC_FETCH_ADD(p_data, value) nrfx_atomic_u32_fetch_add(p_data, value) - -/** - * @brief Performs logical SUB operation on an atomic object and returns previously stored value. - * - * @param[in] p_data Atomic memory pointer. - * @param[in] value Value of second operand of SUB operation. - * - * @return Old value stored into atomic object. - */ -#define NRFX_ATOMIC_FETCH_SUB(p_data, value) nrfx_atomic_u32_fetch_sub(p_data, value) - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_GLUE_H__ diff --git a/hw/bsp/nrf/nrfx_log.h b/hw/bsp/nrf/nrfx_log.h deleted file mode 100644 index 3bc1b424e..000000000 --- a/hw/bsp/nrf/nrfx_log.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - * Copyright (c) 2017 - 2019, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of the copyright holder nor the names of its - * contributors may be used to endorse or promote products derived from this - * software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef NRFX_LOG_H__ -#define NRFX_LOG_H__ - -// THIS IS A TEMPLATE FILE. -// It should be copied to a suitable location within the host environment into -// which nrfx is integrated, and the following macros should be provided with -// appropriate implementations. -// And this comment should be removed from the customized file. - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @defgroup nrfx_log nrfx_log.h - * @{ - * @ingroup nrfx - * - * @brief This file contains macros that should be implemented according to - * the needs of the host environment into which @em nrfx is integrated. - */ - -/** - * @brief Macro for logging a message with the severity level ERROR. - * - * @param format printf-style format string, optionally followed by arguments - * to be formatted and inserted in the resulting string. - */ -#define NRFX_LOG_ERROR(format, ...) - -/** - * @brief Macro for logging a message with the severity level WARNING. - * - * @param format printf-style format string, optionally followed by arguments - * to be formatted and inserted in the resulting string. - */ -#define NRFX_LOG_WARNING(format, ...) - -/** - * @brief Macro for logging a message with the severity level INFO. - * - * @param format printf-style format string, optionally followed by arguments - * to be formatted and inserted in the resulting string. - */ -#define NRFX_LOG_INFO(format, ...) - -/** - * @brief Macro for logging a message with the severity level DEBUG. - * - * @param format printf-style format string, optionally followed by arguments - * to be formatted and inserted in the resulting string. - */ -#define NRFX_LOG_DEBUG(format, ...) - - -/** - * @brief Macro for logging a memory dump with the severity level ERROR. - * - * @param[in] p_memory Pointer to the memory region to be dumped. - * @param[in] length Length of the memory region in bytes. - */ -#define NRFX_LOG_HEXDUMP_ERROR(p_memory, length) - -/** - * @brief Macro for logging a memory dump with the severity level WARNING. - * - * @param[in] p_memory Pointer to the memory region to be dumped. - * @param[in] length Length of the memory region in bytes. - */ -#define NRFX_LOG_HEXDUMP_WARNING(p_memory, length) - -/** - * @brief Macro for logging a memory dump with the severity level INFO. - * - * @param[in] p_memory Pointer to the memory region to be dumped. - * @param[in] length Length of the memory region in bytes. - */ -#define NRFX_LOG_HEXDUMP_INFO(p_memory, length) - -/** - * @brief Macro for logging a memory dump with the severity level DEBUG. - * - * @param[in] p_memory Pointer to the memory region to be dumped. - * @param[in] length Length of the memory region in bytes. - */ -#define NRFX_LOG_HEXDUMP_DEBUG(p_memory, length) - - -/** - * @brief Macro for getting the textual representation of a given error code. - * - * @param[in] error_code Error code. - * - * @return String containing the textual representation of the error code. - */ -#define NRFX_LOG_ERROR_STRING_GET(error_code) - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRFX_LOG_H__ diff --git a/src/portable/nordic/nrf5x/dcd_nrf5x.c b/src/portable/nordic/nrf5x/dcd_nrf5x.c index 5bfedae17..9e5f5117f 100644 --- a/src/portable/nordic/nrf5x/dcd_nrf5x.c +++ b/src/portable/nordic/nrf5x/dcd_nrf5x.c @@ -39,8 +39,8 @@ #endif #include "nrf.h" -#include "nrf_clock.h" -#include "nrfx_usbd_errata.h" +#include "nrfx_clock.h" +#include "nrf_erratas.h" #ifdef __GNUC__ #pragma GCC diagnostic pop @@ -926,7 +926,7 @@ void tusb_hal_nrf_power_event(uint32_t event) { #ifdef NRF52_SERIES // NRF53 does not need this errata // ERRATA 171, 187, 166 - if (nrfx_usbd_errata_187()) { + if (nrf52_errata_187()) { // CRITICAL_REGION_ENTER(); if (*((volatile uint32_t*) (0x4006EC00)) == 0x00000000) { *((volatile uint32_t*) (0x4006EC00)) = 0x00009375; @@ -938,7 +938,7 @@ void tusb_hal_nrf_power_event(uint32_t event) { // CRITICAL_REGION_EXIT(); } - if (nrfx_usbd_errata_171()) { + if (nrf52_errata_171()) { // CRITICAL_REGION_ENTER(); if (*((volatile uint32_t*) (0x4006EC00)) == 0x00000000) { *((volatile uint32_t*) (0x4006EC00)) = 0x00009375; @@ -974,7 +974,7 @@ void tusb_hal_nrf_power_event(uint32_t event) { __DSB(); // for sync #ifdef NRF52_SERIES - if (nrfx_usbd_errata_171()) { + if (nrf52_errata_171()) { // CRITICAL_REGION_ENTER(); if (*((volatile uint32_t*) (0x4006EC00)) == 0x00000000) { *((volatile uint32_t*) (0x4006EC00)) = 0x00009375; @@ -987,7 +987,7 @@ void tusb_hal_nrf_power_event(uint32_t event) { // CRITICAL_REGION_EXIT(); } - if (nrfx_usbd_errata_187()) { + if (nrf52_errata_187()) { // CRITICAL_REGION_ENTER(); if (*((volatile uint32_t*) (0x4006EC00)) == 0x00000000) { *((volatile uint32_t*) (0x4006EC00)) = 0x00009375; @@ -999,7 +999,7 @@ void tusb_hal_nrf_power_event(uint32_t event) { // CRITICAL_REGION_EXIT(); } - if (nrfx_usbd_errata_166()) { + if (nrf52_errata_166()) { *((volatile uint32_t*) (NRF_USBD_BASE + 0x800)) = 0x7E3; *((volatile uint32_t*) (NRF_USBD_BASE + 0x804)) = 0x40; -- cgit v1.3.1 From f7fa4d0edb2eccfe494d1499a6fc4ef3e039309b Mon Sep 17 00:00:00 2001 From: Jannis Konrad Date: Wed, 5 Feb 2025 17:35:02 +0100 Subject: ch32v3 fs: signal bus speed --- src/portable/wch/dcd_ch32_usbfs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/portable') diff --git a/src/portable/wch/dcd_ch32_usbfs.c b/src/portable/wch/dcd_ch32_usbfs.c index 4e8e25a00..d7674b5a3 100644 --- a/src/portable/wch/dcd_ch32_usbfs.c +++ b/src/portable/wch/dcd_ch32_usbfs.c @@ -192,7 +192,8 @@ void dcd_int_handler(uint8_t rhport) { data.xfer[0][TUSB_DIR_OUT].max_size = 64; data.xfer[0][TUSB_DIR_IN].max_size = 64; - dcd_event_bus_signal(rhport, DCD_EVENT_BUS_RESET, true); + //dcd_event_bus_reset(rhport, (USBOTG_FS->BASE_CTRL & USBFS_CTRL_LOW_SPEED) ? 1 : 0, true); + dcd_event_bus_reset(rhport, (USBOTG_FS->UDEV_CTRL & USBFS_UDEV_CTRL_LOW_SPEED) ? 1 : 0, true); USBOTG_FS->DEV_ADDR = 0x00; EP_RX_CTRL(0) = USBFS_EP_R_RES_ACK; -- cgit v1.3.1 From 169d2d7a1fd120d8d0267eaf0a7dcc5e47059100 Mon Sep 17 00:00:00 2001 From: Jannis Konrad Date: Thu, 6 Feb 2025 08:50:25 +0100 Subject: use speed enum --- src/portable/wch/dcd_ch32_usbfs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/portable') diff --git a/src/portable/wch/dcd_ch32_usbfs.c b/src/portable/wch/dcd_ch32_usbfs.c index d7674b5a3..c248ba14e 100644 --- a/src/portable/wch/dcd_ch32_usbfs.c +++ b/src/portable/wch/dcd_ch32_usbfs.c @@ -192,8 +192,8 @@ void dcd_int_handler(uint8_t rhport) { data.xfer[0][TUSB_DIR_OUT].max_size = 64; data.xfer[0][TUSB_DIR_IN].max_size = 64; - //dcd_event_bus_reset(rhport, (USBOTG_FS->BASE_CTRL & USBFS_CTRL_LOW_SPEED) ? 1 : 0, true); - dcd_event_bus_reset(rhport, (USBOTG_FS->UDEV_CTRL & USBFS_UDEV_CTRL_LOW_SPEED) ? 1 : 0, true); + //dcd_event_bus_reset(rhport, (USBOTG_FS->BASE_CTRL & USBFS_CTRL_LOW_SPEED) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL, true); + dcd_event_bus_reset(rhport, (USBOTG_FS->UDEV_CTRL & USBFS_UDEV_CTRL_LOW_SPEED) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL, true); USBOTG_FS->DEV_ADDR = 0x00; EP_RX_CTRL(0) = USBFS_EP_R_RES_ACK; -- cgit v1.3.1 From 93ff3daa116471e41615b85cd7d466cc48bc2148 Mon Sep 17 00:00:00 2001 From: hathach Date: Fri, 28 Feb 2025 16:41:51 +0700 Subject: fix(hcd_rp2040) assert/panic endpoint already active: when a device reset while having on-going control transfer --- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 48 +++++++++++++++------------- src/portable/raspberrypi/rp2040/rp2040_usb.c | 2 +- 2 files changed, 27 insertions(+), 23 deletions(-) (limited to 'src/portable') diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 2c0a3fd49..478c6e789 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -459,28 +459,33 @@ tusb_speed_t hcd_port_speed_get(uint8_t rhport) } // Close all opened endpoint belong to this device -void hcd_device_close(uint8_t rhport, uint8_t dev_addr) -{ +void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { pico_trace("hcd_device_close %d\n", dev_addr); (void) rhport; - if (dev_addr == 0) return; - - for (size_t i = 1; i < TU_ARRAY_SIZE(ep_pool); i++) - { - hw_endpoint_t* ep = &ep_pool[i]; + // reset epx if it is currently active with unplugged device + if (epx.configured && epx.active && epx.dev_addr == dev_addr) { + epx.configured = false; + *epx.endpoint_control = 0; + *epx.buffer_control = 0; + hw_endpoint_reset_transfer(&epx); + } - if (ep->dev_addr == dev_addr && ep->configured) - { - // in case it is an interrupt endpoint, disable it - usb_hw_clear->int_ep_ctrl = (1 << (ep->interrupt_num + 1)); - usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = 0; - - // unconfigure the endpoint - ep->configured = false; - *ep->endpoint_control = 0; - *ep->buffer_control = 0; - hw_endpoint_reset_transfer(ep); + // dev0 only has ep0 + if (dev_addr != 0) { + for (size_t i = 1; i < TU_ARRAY_SIZE(ep_pool); i++) { + hw_endpoint_t *ep = &ep_pool[i]; + if (ep->dev_addr == dev_addr && ep->configured) { + // in case it is an interrupt endpoint, disable it + usb_hw_clear->int_ep_ctrl = (1 << (ep->interrupt_num + 1)); + usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = 0; + + // unconfigure the endpoint + ep->configured = false; + *ep->endpoint_control = 0; + *ep->buffer_control = 0; + hw_endpoint_reset_transfer(ep); + } } } } @@ -557,7 +562,7 @@ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * } // If a normal transfer (non-interrupt) then initiate using - // sie ctrl registers. Otherwise interrupt ep registers should + // sie ctrl registers. Otherwise, interrupt ep registers should // already be configured if ( ep == &epx ) { @@ -597,13 +602,12 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet (void) rhport; // Copy data into setup packet buffer - for ( uint8_t i = 0; i < 8; i++ ) - { + for (uint8_t i = 0; i < 8; i++) { usbh_dpram->setup_packet[i] = setup_packet[i]; } // Configure EP0 struct with setup info for the trans complete - struct hw_endpoint * ep = _hw_endpoint_allocate(0); + struct hw_endpoint * ep = _hw_endpoint_allocate( (uint8_t) TUSB_XFER_CONTROL); TU_ASSERT(ep); // EPX should be inactive diff --git a/src/portable/raspberrypi/rp2040/rp2040_usb.c b/src/portable/raspberrypi/rp2040/rp2040_usb.c index 43f48da39..9d0bd762d 100644 --- a/src/portable/raspberrypi/rp2040/rp2040_usb.c +++ b/src/portable/raspberrypi/rp2040/rp2040_usb.c @@ -110,7 +110,7 @@ void __tusb_irq_path_func(_hw_endpoint_buffer_control_update32)(struct hw_endpoi *ep->buffer_control = value & ~USB_BUF_CTRL_AVAIL; // 4.1.2.5.1 Con-current access: 12 cycles (should be good for 48*12Mhz = 576Mhz) after write to buffer control // Don't need delay in host mode as host is in charge - if ( !is_host_mode()) { + if (!is_host_mode()) { busy_wait_at_least_cycles(12); } } -- cgit v1.3.1 From 102c1991d0abcfba9275830c48706ac34d7734d5 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 5 Mar 2025 22:26:28 +0700 Subject: rp2040: abort transfer if active in iso_activate() add hw_endpoint_abort_xfer() --- src/portable/raspberrypi/rp2040/dcd_rp2040.c | 59 ++++++++++++++++------------ 1 file changed, 33 insertions(+), 26 deletions(-) (limited to 'src/portable') diff --git a/src/portable/raspberrypi/rp2040/dcd_rp2040.c b/src/portable/raspberrypi/rp2040/dcd_rp2040.c index b91dd38d5..358ce84bc 100644 --- a/src/portable/raspberrypi/rp2040/dcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/dcd_rp2040.c @@ -148,6 +148,32 @@ static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t* buffer, uint16_t total_by hw_endpoint_xfer_start(ep, buffer, total_bytes); } +static void hw_endpoint_abort_xfer(struct hw_endpoint* ep) { + // Abort any pending transfer + // Due to Errata RP2040-E2: ABORT flag is only applicable for B2 and later (unusable for B0, B1). + // Which means we are not guaranteed to safely abort pending transfer on B0 and B1. + const uint8_t dir = tu_edpt_dir(ep->ep_addr); + const uint8_t epnum = tu_edpt_number(ep->ep_addr); + const uint32_t abort_mask = TU_BIT((epnum << 1) | (dir ? 0 : 1)); + if (rp2040_chip_version() >= 2) { + usb_hw_set->abort = abort_mask; + while ((usb_hw->abort_done & abort_mask) != abort_mask) {} + } + + uint32_t buf_ctrl = USB_BUF_CTRL_SEL; // reset to buffer 0 + if (ep->next_pid) { + buf_ctrl |= USB_BUF_CTRL_DATA1_PID; + } + + _hw_endpoint_buffer_control_set_value32(ep, buf_ctrl); + hw_endpoint_reset_transfer(ep); + + if (rp2040_chip_version() >= 2) { + usb_hw_clear->abort_done = abort_mask; + usb_hw_clear->abort = abort_mask; + } +} + static void __tusb_irq_path_func(hw_handle_buff_status)(void) { uint32_t remaining_buffers = usb_hw->buf_status; pico_trace("buf_status = 0x%08lx\r\n", remaining_buffers); @@ -178,25 +204,10 @@ TU_ATTR_ALWAYS_INLINE static inline void reset_ep0(void) { // setup transfer. Also clear a stall in case for (uint8_t dir = 0; dir < 2; dir++) { struct hw_endpoint* ep = hw_endpoint_get_by_num(0, dir); + ep->next_pid = 1u; if (ep->active) { - // Abort any pending transfer from a prior control transfer per USB specs - // Due to Errata RP2040-E2: ABORT flag is only applicable for B2 and later (unusable for B0, B1). - // Which means we are not guaranteed to safely abort pending transfer on B0 and B1. - uint32_t const abort_mask = (dir ? USB_EP_ABORT_EP0_IN_BITS : USB_EP_ABORT_EP0_OUT_BITS); - if (rp2040_chip_version() >= 2) { - usb_hw_set->abort = abort_mask; - while ((usb_hw->abort_done & abort_mask) != abort_mask) {} - } - - _hw_endpoint_buffer_control_set_value32(ep, USB_BUF_CTRL_DATA1_PID | USB_BUF_CTRL_SEL); - hw_endpoint_reset_transfer(ep); - - if (rp2040_chip_version() >= 2) { - usb_hw_clear->abort_done = abort_mask; - usb_hw_clear->abort = abort_mask; - } + hw_endpoint_abort_xfer(ep); // Abort any pending transfer per USB specs } - ep->next_pid = 1u; } } @@ -495,18 +506,14 @@ bool dcd_edpt_iso_alloc(uint8_t rhport, uint8_t ep_addr, uint16_t largest_packet // New API: Configure and enable an ISO endpoint according to descriptor bool dcd_edpt_iso_activate(uint8_t rhport, tusb_desc_endpoint_t const * ep_desc) { (void) rhport; - const uint8_t ep_addr = ep_desc->bEndpointAddress; + struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_desc->bEndpointAddress); + TU_ASSERT(ep->hw_data_buf != NULL); // must be inited and allocated previously - // init w/o allocate - const uint16_t mps = ep_desc->wMaxPacketSize; - uint16_t size = (uint16_t)tu_div_ceil(mps, 64) * 64u; - hw_endpoint_init(ep_addr, size, TUSB_XFER_ISOCHRONOUS); + if (ep->active) { + hw_endpoint_abort_xfer(ep); // abort any pending transfer + } - // Fill in endpoint control register with buffer offset - struct hw_endpoint* ep = hw_endpoint_get_by_addr(ep_addr); - TU_ASSERT(ep->hw_data_buf != NULL); // must be inited and buffer allocated ep->wMaxPacketSize = ep_desc->wMaxPacketSize; - hw_endpoint_enable(ep); return true; } -- cgit v1.3.1 From 65e44e0a51272f9d75719d90955f19209dbf1ea2 Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 6 Mar 2025 22:46:21 +0700 Subject: fix(dwc2) host driver conflict with max3421e --- examples/host/bare_api/src/tusb_config.h | 3 ++- examples/host/cdc_msc_hid/src/tusb_config.h | 3 ++- examples/host/cdc_msc_hid_freertos/src/tusb_config.h | 3 ++- examples/host/device_info/src/tusb_config.h | 3 ++- examples/host/hid_controller/src/tusb_config.h | 3 ++- examples/host/msc_file_explorer/src/tusb_config.h | 3 ++- src/portable/synopsys/dwc2/hcd_dwc2.c | 2 +- 7 files changed, 13 insertions(+), 7 deletions(-) (limited to 'src/portable') diff --git a/examples/host/bare_api/src/tusb_config.h b/examples/host/bare_api/src/tusb_config.h index fab233be0..a03675c5f 100644 --- a/examples/host/bare_api/src/tusb_config.h +++ b/examples/host/bare_api/src/tusb_config.h @@ -69,9 +69,10 @@ // Enable Host stack #define CFG_TUH_ENABLED 1 +// #define CFG_TUH_MAX3421 1 // use max3421 as host controller + #if CFG_TUSB_MCU == OPT_MCU_RP2040 // #define CFG_TUH_RPI_PIO_USB 1 // use pio-usb as host controller - // #define CFG_TUH_MAX3421 1 // use max3421 as host controller // host roothub port is 1 if using either pio-usb or max3421 #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421) diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index a59a0ffb9..cc8d6e5c4 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -69,9 +69,10 @@ // Enable Host stack #define CFG_TUH_ENABLED 1 +// #define CFG_TUH_MAX3421 1 // use max3421 as host controller + #if CFG_TUSB_MCU == OPT_MCU_RP2040 // #define CFG_TUH_RPI_PIO_USB 1 // use pio-usb as host controller - // #define CFG_TUH_MAX3421 1 // use max3421 as host controller // host roothub port is 1 if using either pio-usb or max3421 #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421) diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h index 02de4197b..682265f59 100644 --- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h +++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h @@ -74,9 +74,10 @@ // Enable Host stack #define CFG_TUH_ENABLED 1 +// #define CFG_TUH_MAX3421 1 // use max3421 as host controller + #if CFG_TUSB_MCU == OPT_MCU_RP2040 // #define CFG_TUH_RPI_PIO_USB 1 // use pio-usb as host controller - // #define CFG_TUH_MAX3421 1 // use max3421 as host controller // host roothub port is 1 if using either pio-usb or max3421 #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421) diff --git a/examples/host/device_info/src/tusb_config.h b/examples/host/device_info/src/tusb_config.h index 5190b5b1f..db02a97db 100644 --- a/examples/host/device_info/src/tusb_config.h +++ b/examples/host/device_info/src/tusb_config.h @@ -74,9 +74,10 @@ // Enable Host stack #define CFG_TUH_ENABLED 1 +// #define CFG_TUH_MAX3421 1 // use max3421 as host controller + #if CFG_TUSB_MCU == OPT_MCU_RP2040 // #define CFG_TUH_RPI_PIO_USB 1 // use pio-usb as host controller - // #define CFG_TUH_MAX3421 1 // use max3421 as host controller // host roothub port is 1 if using either pio-usb or max3421 #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421) diff --git a/examples/host/hid_controller/src/tusb_config.h b/examples/host/hid_controller/src/tusb_config.h index 3ac591d8f..351fe0178 100644 --- a/examples/host/hid_controller/src/tusb_config.h +++ b/examples/host/hid_controller/src/tusb_config.h @@ -69,9 +69,10 @@ // Enable Host stack #define CFG_TUH_ENABLED 1 +// #define CFG_TUH_MAX3421 1 // use max3421 as host controller + #if CFG_TUSB_MCU == OPT_MCU_RP2040 // #define CFG_TUH_RPI_PIO_USB 1 // use pio-usb as host controller - // #define CFG_TUH_MAX3421 1 // use max3421 as host controller // host roothub port is 1 if using either pio-usb or max3421 #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421) diff --git a/examples/host/msc_file_explorer/src/tusb_config.h b/examples/host/msc_file_explorer/src/tusb_config.h index c798b4383..c1829c300 100644 --- a/examples/host/msc_file_explorer/src/tusb_config.h +++ b/examples/host/msc_file_explorer/src/tusb_config.h @@ -69,9 +69,10 @@ // Enable Host stack #define CFG_TUH_ENABLED 1 +// #define CFG_TUH_MAX3421 1 // use max3421 as host controller + #if CFG_TUSB_MCU == OPT_MCU_RP2040 // #define CFG_TUH_RPI_PIO_USB 1 // use pio-usb as host controller - // #define CFG_TUH_MAX3421 1 // use max3421 as host controller // host roothub port is 1 if using either pio-usb or max3421 #if (defined(CFG_TUH_RPI_PIO_USB) && CFG_TUH_RPI_PIO_USB) || (defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421) diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index ebbb6200a..b13479b02 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -26,7 +26,7 @@ #include "tusb_option.h" -#if CFG_TUH_ENABLED && defined(TUP_USBIP_DWC2) +#if CFG_TUH_ENABLED && defined(TUP_USBIP_DWC2) && !CFG_TUH_MAX3421 #if !(CFG_TUH_DWC2_SLAVE_ENABLE || CFG_TUH_DWC2_DMA_ENABLE) #error DWC2 require either CFG_TUH_DWC2_SLAVE_ENABLE or CFG_TUH_DWC2_DMA_ENABLE to be enabled -- cgit v1.3.1 From 585bcbfcdd5e24e25dd8d42b51446824b8143602 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sun, 16 Mar 2025 00:07:15 +0100 Subject: Fix 2 IAR warnings. Signed-off-by: HiFiPhile --- src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'src/portable') diff --git a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c index 7d5cfb5b0..7c637ce0c 100644 --- a/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c +++ b/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c @@ -297,7 +297,7 @@ bool dcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { dcd_reg->EPLISTSTART = (uint32_t) _dcd.ep; dcd_reg->DATABUFSTART = tu_align((uint32_t) &_dcd, TU_BIT(22)); // 22-bit alignment - dcd_reg->INTSTAT |= dcd_reg->INTSTAT; // clear all pending interrupt + dcd_reg->INTSTAT = dcd_reg->INTSTAT; // clear all pending interrupt dcd_reg->INTEN = INT_DEVICE_STATUS_MASK; dcd_reg->DEVCMDSTAT |= DEVCMDSTAT_DEVICE_ENABLE_MASK | DEVCMDSTAT_DEVICE_CONNECT_MASK | DEVCMDSTAT_RESET_CHANGE_MASK | DEVCMDSTAT_CONNECT_CHANGE_MASK | DEVCMDSTAT_SUSPEND_CHANGE_MASK; @@ -563,7 +563,8 @@ void dcd_int_handler(uint8_t rhport) uint32_t const cmd_stat = dcd_reg->DEVCMDSTAT; - uint32_t int_status = dcd_reg->INTSTAT & dcd_reg->INTEN; + uint32_t int_status = dcd_reg->INTSTAT; + int_status &= dcd_reg->INTEN; dcd_reg->INTSTAT = int_status; // Acknowledge handled interrupt if (int_status == 0) return; -- cgit v1.3.1 From 65e01fff2e7ab5302baa45bdd81a1d774e269452 Mon Sep 17 00:00:00 2001 From: hathach Date: Tue, 25 Mar 2025 16:15:58 +0700 Subject: add tuh_edpt_close() API, it will abort any pending transfer implement hcd_edpt_close() for pio-usb and max3421e, also move max3421e api into its own header. --- examples/host/bare_api/src/main.c | 254 +++++++++++-------------- src/host/hcd.h | 3 + src/host/usbh.c | 6 + src/host/usbh.h | 7 + src/portable/analog/max3421/hcd_max3421.c | 40 ++-- src/portable/analog/max3421/hcd_max3421.h | 63 ++++++ src/portable/raspberrypi/pio_usb/hcd_pio_usb.c | 5 + tools/get_deps.py | 4 +- 8 files changed, 218 insertions(+), 164 deletions(-) create mode 100644 src/portable/analog/max3421/hcd_max3421.h (limited to 'src/portable') diff --git a/examples/host/bare_api/src/main.c b/examples/host/bare_api/src/main.c index f582f4f5a..0c76ff0c9 100644 --- a/examples/host/bare_api/src/main.c +++ b/examples/host/bare_api/src/main.c @@ -55,16 +55,15 @@ uint8_t* get_hid_buf(uint8_t daddr); void free_hid_buf(uint8_t daddr); /*------------- MAIN -------------*/ -int main(void) -{ +int main(void) { board_init(); printf("TinyUSB Bare API Example\r\n"); // init host stack on configured roothub port tusb_rhport_init_t host_init = { - .role = TUSB_ROLE_HOST, - .speed = TUSB_SPEED_AUTO + .role = TUSB_ROLE_HOST, + .speed = TUSB_SPEED_AUTO }; tusb_init(BOARD_TUH_RHPORT, &host_init); @@ -72,8 +71,7 @@ int main(void) board_init_after_tusb(); } - while (1) - { + while (1) { // tinyusb host task tuh_task(); led_blinking_task(); @@ -85,8 +83,7 @@ int main(void) /*------------- TinyUSB Callbacks -------------*/ // Invoked when device is mounted (configured) -void tuh_mount_cb (uint8_t daddr) -{ +void tuh_mount_cb(uint8_t daddr) { printf("Device attached, address = %d\r\n", daddr); // Get Device Descriptor @@ -95,8 +92,7 @@ void tuh_mount_cb (uint8_t daddr) } /// Invoked when device is unmounted (bus reset/unplugged) -void tuh_umount_cb(uint8_t daddr) -{ +void tuh_umount_cb(uint8_t daddr) { printf("Device removed, address = %d\r\n", daddr); free_hid_buf(daddr); } @@ -104,11 +100,8 @@ void tuh_umount_cb(uint8_t daddr) //--------------------------------------------------------------------+ // Device Descriptor //--------------------------------------------------------------------+ - -void print_device_descriptor(tuh_xfer_t* xfer) -{ - if ( XFER_RESULT_SUCCESS != xfer->result ) - { +void print_device_descriptor(tuh_xfer_t *xfer) { + if (XFER_RESULT_SUCCESS != xfer->result) { printf("Failed to get device descriptor\r\n"); return; } @@ -131,33 +124,29 @@ void print_device_descriptor(tuh_xfer_t* xfer) // Get String descriptor using Sync API uint16_t temp_buf[128]; - printf(" iManufacturer %u " , desc_device.iManufacturer); - if (XFER_RESULT_SUCCESS == tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf)) ) - { + printf(" iManufacturer %u ", desc_device.iManufacturer); + if (XFER_RESULT_SUCCESS == tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) { print_utf16(temp_buf, TU_ARRAY_SIZE(temp_buf)); } printf("\r\n"); - printf(" iProduct %u " , desc_device.iProduct); - if (XFER_RESULT_SUCCESS == tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) - { + printf(" iProduct %u ", desc_device.iProduct); + if (XFER_RESULT_SUCCESS == tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) { print_utf16(temp_buf, TU_ARRAY_SIZE(temp_buf)); } printf("\r\n"); - printf(" iSerialNumber %u " , desc_device.iSerialNumber); - if (XFER_RESULT_SUCCESS == tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) - { + printf(" iSerialNumber %u ", desc_device.iSerialNumber); + if (XFER_RESULT_SUCCESS == tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, temp_buf, sizeof(temp_buf))) { print_utf16(temp_buf, TU_ARRAY_SIZE(temp_buf)); } printf("\r\n"); - printf(" bNumConfigurations %u\r\n" , desc_device.bNumConfigurations); + printf(" bNumConfigurations %u\r\n", desc_device.bNumConfigurations); // Get configuration descriptor with sync API - if (XFER_RESULT_SUCCESS == tuh_descriptor_get_configuration_sync(daddr, 0, temp_buf, sizeof(temp_buf))) - { - parse_config_descriptor(daddr, (tusb_desc_configuration_t*) temp_buf); + if (XFER_RESULT_SUCCESS == tuh_descriptor_get_configuration_sync(daddr, 0, temp_buf, sizeof(temp_buf))) { + parse_config_descriptor(daddr, (tusb_desc_configuration_t *) temp_buf); } } @@ -171,37 +160,33 @@ uint16_t count_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_ void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len); // simple configuration parser to open and listen to HID Endpoint IN -void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg) -{ - uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength); - uint8_t const* p_desc = tu_desc_next(desc_cfg); +void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const *desc_cfg) { + uint8_t const *desc_end = ((uint8_t const *) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength); + uint8_t const *p_desc = tu_desc_next(desc_cfg); // parse each interfaces - while( p_desc < desc_end ) - { + while (p_desc < desc_end) { uint8_t assoc_itf_count = 1; // Class will always starts with Interface Association (if any) and then Interface descriptor - if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) ) - { - tusb_desc_interface_assoc_t const * desc_iad = (tusb_desc_interface_assoc_t const *) p_desc; + if (TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc)) { + tusb_desc_interface_assoc_t const *desc_iad = (tusb_desc_interface_assoc_t const *) p_desc; assoc_itf_count = desc_iad->bInterfaceCount; - p_desc = tu_desc_next(p_desc); // next to Interface + p_desc = tu_desc_next(p_desc);// next to Interface } // must be interface from now - if( TUSB_DESC_INTERFACE != tu_desc_type(p_desc) ) return; - tusb_desc_interface_t const* desc_itf = (tusb_desc_interface_t const*) p_desc; + if (TUSB_DESC_INTERFACE != tu_desc_type(p_desc)) { return; } + tusb_desc_interface_t const *desc_itf = (tusb_desc_interface_t const *) p_desc; - uint16_t const drv_len = count_interface_total_len(desc_itf, assoc_itf_count, (uint16_t) (desc_end-p_desc)); + uint16_t const drv_len = count_interface_total_len(desc_itf, assoc_itf_count, (uint16_t) (desc_end - p_desc)); // probably corrupted descriptor - if(drv_len < sizeof(tusb_desc_interface_t)) return; + if (drv_len < sizeof(tusb_desc_interface_t)) { return; } // only open and listen to HID endpoint IN - if (desc_itf->bInterfaceClass == TUSB_CLASS_HID) - { + if (desc_itf->bInterfaceClass == TUSB_CLASS_HID) { open_hid_interface(dev_addr, desc_itf, drv_len); } @@ -210,25 +195,21 @@ void parse_config_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* } } -uint16_t count_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len) -{ - uint8_t const* p_desc = (uint8_t const*) desc_itf; +uint16_t count_interface_total_len(tusb_desc_interface_t const *desc_itf, uint8_t itf_count, uint16_t max_len) { + uint8_t const *p_desc = (uint8_t const *) desc_itf; uint16_t len = 0; - while (itf_count--) - { + while (itf_count--) { // Next on interface desc len += tu_desc_len(desc_itf); p_desc = tu_desc_next(p_desc); - while (len < max_len) - { + while (len < max_len) { // return on IAD regardless of itf count - if ( tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION ) return len; + if (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION) { return len; } - if ( (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) && - ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0 ) - { + if ((tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) && + ((tusb_desc_interface_t const *) p_desc)->bAlternateSetting == 0) { break; } @@ -246,46 +227,45 @@ uint16_t count_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_ void hid_report_received(tuh_xfer_t* xfer); -void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len) -{ +void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, uint16_t max_len) { // len = interface + hid + n*endpoints uint16_t const drv_len = (uint16_t) (sizeof(tusb_desc_interface_t) + sizeof(tusb_hid_descriptor_hid_t) + desc_itf->bNumEndpoints * sizeof(tusb_desc_endpoint_t)); // corrupted descriptor - if (max_len < drv_len) return; + if (max_len < drv_len) { return; } uint8_t const *p_desc = (uint8_t const *) desc_itf; // HID descriptor p_desc = tu_desc_next(p_desc); tusb_hid_descriptor_hid_t const *desc_hid = (tusb_hid_descriptor_hid_t const *) p_desc; - if(HID_DESC_TYPE_HID != desc_hid->bDescriptorType) return; + if (HID_DESC_TYPE_HID != desc_hid->bDescriptorType) { return; } // Endpoint descriptor p_desc = tu_desc_next(p_desc); - tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc; - - for(int i = 0; i < desc_itf->bNumEndpoints; i++) - { - if (TUSB_DESC_ENDPOINT != desc_ep->bDescriptorType) return; - - if(tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) - { - // skip if failed to open endpoint - if ( ! tuh_edpt_open(daddr, desc_ep) ) return; - - uint8_t* buf = get_hid_buf(daddr); - if (!buf) return; // out of memory - - tuh_xfer_t xfer = - { - .daddr = daddr, - .ep_addr = desc_ep->bEndpointAddress, - .buflen = 64, - .buffer = buf, - .complete_cb = hid_report_received, - .user_data = (uintptr_t) buf, // since buffer is not available in callback, use user data to store the buffer + tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc; + + for (int i = 0; i < desc_itf->bNumEndpoints; i++) { + if (TUSB_DESC_ENDPOINT != desc_ep->bDescriptorType) { return; } + + if (tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN) { + if (!tuh_edpt_open(daddr, desc_ep)) { + return; // skip if failed to open endpoint + } + + uint8_t *buf = get_hid_buf(daddr); + if (!buf) { + return;// out of memory + } + + tuh_xfer_t xfer = { + .daddr = daddr, + .ep_addr = desc_ep->bEndpointAddress, + .buflen = 64, + .buffer = buf, + .complete_cb = hid_report_received, + .user_data = (uintptr_t) buf,// since buffer is not available in callback, use user data to store the buffer }; // submit transfer for this EP @@ -299,18 +279,17 @@ void open_hid_interface(uint8_t daddr, tusb_desc_interface_t const *desc_itf, ui } } -void hid_report_received(tuh_xfer_t* xfer) -{ +void hid_report_received(tuh_xfer_t *xfer) { // Note: not all field in xfer is available for use (i.e filled by tinyusb stack) in callback to save sram // For instance, xfer->buffer is NULL. We have used user_data to store buffer when submitted callback - uint8_t* buf = (uint8_t*) xfer->user_data; + uint8_t *buf = (uint8_t *) xfer->user_data; - if (xfer->result == XFER_RESULT_SUCCESS) - { + if (xfer->result == XFER_RESULT_SUCCESS) { printf("[dev %u: ep %02x] HID Report:", xfer->daddr, xfer->ep_addr); - for(uint32_t i=0; iactual_len; i++) - { - if (i%16 == 0) printf("\r\n "); + for (uint32_t i = 0; i < xfer->actual_len; i++) { + if (i % 16 == 0) { + printf("\r\n "); + } printf("%02X ", buf[i]); } printf("\r\n"); @@ -329,12 +308,9 @@ void hid_report_received(tuh_xfer_t* xfer) //--------------------------------------------------------------------+ // get an buffer from pool -uint8_t* get_hid_buf(uint8_t daddr) -{ - for(size_t i=0; i> 6 & 0x1F)); - *utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F)); - } else { - // TODO: Verify surrogate. - *utf8++ = (uint8_t)(0xE0 | (chr >> 12 & 0x0F)); - *utf8++ = (uint8_t)(0x80 | (chr >> 6 & 0x3F)); - *utf8++ = (uint8_t)(0x80 | (chr >> 0 & 0x3F)); - } - // TODO: Handle UTF-16 code points that take two entries. + // TODO: Check for runover. + (void) utf8_len; + // Get the UTF-16 length out of the data itself. + + for (size_t i = 0; i < utf16_len; i++) { + uint16_t chr = utf16[i]; + if (chr < 0x80) { + *utf8++ = chr & 0xffu; + } else if (chr < 0x800) { + *utf8++ = (uint8_t) (0xC0 | (chr >> 6 & 0x1F)); + *utf8++ = (uint8_t) (0x80 | (chr >> 0 & 0x3F)); + } else { + // TODO: Verify surrogate. + *utf8++ = (uint8_t) (0xE0 | (chr >> 12 & 0x0F)); + *utf8++ = (uint8_t) (0x80 | (chr >> 6 & 0x3F)); + *utf8++ = (uint8_t) (0x80 | (chr >> 0 & 0x3F)); } + // TODO: Handle UTF-16 code points that take two entries. + } } // Count how many bytes a utf-16-le encoded string will take in utf-8. static int _count_utf8_bytes(const uint16_t *buf, size_t len) { - size_t total_bytes = 0; - for (size_t i = 0; i < len; i++) { - uint16_t chr = buf[i]; - if (chr < 0x80) { - total_bytes += 1; - } else if (chr < 0x800) { - total_bytes += 2; - } else { - total_bytes += 3; - } - // TODO: Handle UTF-16 code points that take two entries. + size_t total_bytes = 0; + for (size_t i = 0; i < len; i++) { + uint16_t chr = buf[i]; + if (chr < 0x80) { + total_bytes += 1; + } else if (chr < 0x800) { + total_bytes += 2; + } else { + total_bytes += 3; } - return (int) total_bytes; + // TODO: Handle UTF-16 code points that take two entries. + } + return (int) total_bytes; } static void print_utf16(uint16_t *temp_buf, size_t buf_len) { - if ((temp_buf[0] & 0xff) == 0) return; // empty - size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t); - size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len); - _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len); - ((uint8_t*) temp_buf)[utf8_len] = '\0'; + if ((temp_buf[0] & 0xff) == 0) return;// empty + size_t utf16_len = ((temp_buf[0] & 0xff) - 2) / sizeof(uint16_t); + size_t utf8_len = (size_t) _count_utf8_bytes(temp_buf + 1, utf16_len); + _convert_utf16le_to_utf8(temp_buf + 1, utf16_len, (uint8_t *) temp_buf, sizeof(uint16_t) * buf_len); + ((uint8_t *) temp_buf)[utf8_len] = '\0'; - printf("%s", (char*)temp_buf); + printf("%s", (char *) temp_buf); } diff --git a/src/host/hcd.h b/src/host/hcd.h index 56b6fdb5d..aa9e9cf3b 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -165,6 +165,9 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr); // Open an endpoint bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc); +// Close an endpoint +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr); + // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked bool hcd_edpt_xfer(uint8_t rhport, uint8_t daddr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen); diff --git a/src/host/usbh.c b/src/host/usbh.c index 308916c9b..5925a7be0 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -994,6 +994,12 @@ bool tuh_edpt_open(uint8_t dev_addr, tusb_desc_endpoint_t const* desc_ep) { return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, desc_ep); } +bool tuh_edpt_close(uint8_t daddr, uint8_t ep_addr) { + TU_VERIFY(0 != tu_edpt_number(ep_addr)); // cannot close EP0 + tuh_edpt_abort_xfer(daddr, ep_addr); // abort any pending transfer + return hcd_edpt_close(usbh_get_rhport(daddr), daddr, ep_addr); +} + bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr) { usbh_device_t* dev = get_device(dev_addr); TU_VERIFY(dev); diff --git a/src/host/usbh.h b/src/host/usbh.h index d95bb9b57..4829a8183 100644 --- a/src/host/usbh.h +++ b/src/host/usbh.h @@ -33,6 +33,10 @@ #include "common/tusb_common.h" +#if CFG_TUH_MAX3421 +#include "portable/analog/max3421/hcd_max3421.h" +#endif + //--------------------------------------------------------------------+ // MACRO CONSTANT TYPEDEF //--------------------------------------------------------------------+ @@ -227,6 +231,9 @@ bool tuh_edpt_xfer(tuh_xfer_t* xfer); // Open a non-control endpoint bool tuh_edpt_open(uint8_t daddr, tusb_desc_endpoint_t const * desc_ep); +// Close a non-control endpoint, it will abort any pending transfer +bool tuh_edpt_close(uint8_t daddr, uint8_t ep_addr); + // Abort a queued transfer. Note: it can only abort transfer that has not been started // Return true if a queued transfer is aborted, false if there is no transfer to abort bool tuh_edpt_abort_xfer(uint8_t daddr, uint8_t ep_addr); diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index c5e924266..3fbf950a4 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -252,28 +252,6 @@ static tuh_configure_max3421_t _tuh_cfg = { .pinctl = 0, // default: negative edge interrupt }; -//--------------------------------------------------------------------+ -// API: SPI transfer with MAX3421E -// - spi_cs_api(), spi_xfer_api(), int_api(): must be implemented by application -// - reg_read(), reg_write(): is implemented by this driver, can be used by application -//--------------------------------------------------------------------+ - -// API to control MAX3421 SPI CS -extern void tuh_max3421_spi_cs_api(uint8_t rhport, bool active); - -// API to transfer data with MAX3421 SPI -// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only -extern bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes); - -// API to enable/disable MAX3421 INTR pin interrupt -extern void tuh_max3421_int_api(uint8_t rhport, bool enabled); - -// API to read MAX3421's register. Implemented by TinyUSB -uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr); - -// API to write MAX3421's register. Implemented by TinyUSB -bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr); - //--------------------------------------------------------------------+ // SPI Commands and Helper //--------------------------------------------------------------------+ @@ -632,6 +610,9 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e if (daddr == 0 && ep_num == 0) { ep = &_hcd_data.ep[0]; }else { + if (NULL != find_ep_not_addr0(daddr, ep_num, ep_dir)) { + return false; // endpoint already opened + } ep = allocate_ep(); TU_ASSERT(ep); ep->daddr = daddr; @@ -645,6 +626,21 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e return true; } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; + uint8_t const ep_num = tu_edpt_number(ep_addr); + tusb_dir_t const ep_dir = tu_edpt_dir(ep_addr); + max3421_ep_t * ep = find_ep_not_addr0(daddr, ep_num, ep_dir); + + if (!ep) { + return false; // not opened + } + + tu_memclr(ep, sizeof(max3421_ep_t)); + + return true; +} + /* The microcontroller repeatedly writes the SNDFIFO register R2 to load the FIFO with up to 64 data bytes. * Then the microcontroller writes the SNDBC register, which this does three things: * 1. Tells the MAX3421E SIE (Serial Interface Engine) how many bytes in the FIFO to send. diff --git a/src/portable/analog/max3421/hcd_max3421.h b/src/portable/analog/max3421/hcd_max3421.h new file mode 100644 index 000000000..4631fa21a --- /dev/null +++ b/src/portable/analog/max3421/hcd_max3421.h @@ -0,0 +1,63 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2025 Ha Thach (tinyusb.org) + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ +#ifndef TUSB_HCD_MAX3421_H +#define TUSB_HCD_MAX3421_H + +#ifdef __cplusplus + extern "C" { +#endif + +//--------------------------------------------------------------------+ +// SPI transfer API with MAX3421E are implemented by application +// - spi_cs_api(), spi_xfer_api(), int_api() +//--------------------------------------------------------------------+ + +// API to control MAX3421 SPI CS +extern void tuh_max3421_spi_cs_api(uint8_t rhport, bool active); + +// API to transfer data with MAX3421 SPI +// Either tx_buf or rx_buf can be NULL, which means transfer is write or read only +extern bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint8_t* rx_buf, size_t xfer_bytes); + +// API to enable/disable MAX3421 INTR pin interrupt +extern void tuh_max3421_int_api(uint8_t rhport, bool enabled); + +//--------------------------------------------------------------------+ +// API for read/write MAX3421 registers +// are implemented by this driver, can be used by application +//--------------------------------------------------------------------+ + +// API to read MAX3421's register. Implemented by TinyUSB +uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr); + +// API to write MAX3421's register. Implemented by TinyUSB +bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr); + +#ifdef __cplusplus + } +#endif + +#endif diff --git a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c index 6422afff1..225a44dcf 100644 --- a/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c +++ b/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c @@ -122,6 +122,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const return pio_usb_host_endpoint_open(pio_rhport, dev_addr, (uint8_t const *) desc_ep, need_pre); } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + uint8_t const pio_rhport = RHPORT_PIO(rhport); + return pio_usb_host_endpoint_close(pio_rhport, daddr, ep_addr); +} + bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) { uint8_t const pio_rhport = RHPORT_PIO(rhport); return pio_usb_host_endpoint_transfer(pio_rhport, dev_addr, ep_addr, buffer, buflen); diff --git a/tools/get_deps.py b/tools/get_deps.py index 3f529bd7e..ba9dc23ce 100755 --- a/tools/get_deps.py +++ b/tools/get_deps.py @@ -58,8 +58,8 @@ deps_optional = { 'hw/mcu/nxp/mcux-sdk': ['https://github.com/hathach/mcux-sdk.git', '144f1eb7ea8c06512e12f12b27383601c0272410', 'kinetis_k kinetis_k32l2 kinetis_kl lpc51 lpc54 lpc55 mcx imxrt'], - 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/sekigon-gonnoc/Pico-PIO-USB.git', - '0ca3657d55ea20e7fa4483bbd21ce951bc1d6fa5', + 'hw/mcu/raspberry_pi/Pico-PIO-USB': ['https://github.com/hathach/Pico-PIO-USB.git', + '810653f66adadba3e0e4b4b56d5167ac4f7fdbf7', 'rp2040'], 'hw/mcu/renesas/fsp': ['https://github.com/renesas/fsp.git', 'edcc97d684b6f716728a60d7a6fea049d9870bd6', -- cgit v1.3.1 From 901ce2ad93b39c08e8e6b7e5b3f4dbd0b9df879e Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 26 Mar 2025 21:13:01 +0700 Subject: hcd/ehci: hcd_edpt_open() return false if ep is already opened. implement hcd_edpt_close() --- hw/bsp/imxrt/family.c | 4 +- src/device/usbd.c | 9 +- src/host/usbh.c | 2 +- src/portable/ehci/ehci.c | 259 ++++++++++++++++++++------------------ src/portable/ehci/ehci.h | 314 +++++++++++++++++++++++------------------------ test/hil/hil_test.py | 3 +- 6 files changed, 301 insertions(+), 290 deletions(-) (limited to 'src/portable') diff --git a/hw/bsp/imxrt/family.c b/hw/bsp/imxrt/family.c index 7b89cc76d..7e4734a66 100644 --- a/hw/bsp/imxrt/family.c +++ b/hw/bsp/imxrt/family.c @@ -61,7 +61,7 @@ - Define CFG_TUSB_MEM_SECTION=__attribute__((section("NonCacheable"))) */ -static void BOARD_ConfigMPU(void); +// static void BOARD_ConfigMPU(void); // needed by fsl_flexspi_nor_boot TU_ATTR_USED const uint8_t dcd_data[] = {0x00}; @@ -456,7 +456,7 @@ static void BOARD_ConfigMPU(void) { #elif __CORTEX_M == 4 -void BOARD_ConfigMPU(void) { +static void BOARD_ConfigMPU(void) { #if defined(__CC_ARM) || defined(__ARMCC_VERSION) extern uint32_t Image$$RW_m_ncache$$Base[]; /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */ diff --git a/src/device/usbd.c b/src/device/usbd.c index fb5cec49d..9c381d5e0 100644 --- a/src/device/usbd.c +++ b/src/device/usbd.c @@ -561,8 +561,7 @@ static void usbd_reset(uint8_t rhport) { } bool tud_task_event_ready(void) { - // Skip if stack is not initialized - if (!tud_inited()) return false; + TU_VERIFY(tud_inited()); // Skip if stack is not initialized return !osal_queue_empty(_usbd_q); } @@ -684,7 +683,9 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) { case USBD_EVENT_FUNC_CALL: TU_LOG_USBD("\r\n"); - if (event.func_call.func) event.func_call.func(event.func_call.param); + if (event.func_call.func) { + event.func_call.func(event.func_call.param); + } break; case DCD_EVENT_SOF: @@ -701,7 +702,7 @@ void tud_task_ext(uint32_t timeout_ms, bool in_isr) { #if CFG_TUSB_OS != OPT_OS_NONE && CFG_TUSB_OS != OPT_OS_PICO // return if there is no more events, for application to run other background - if (osal_queue_empty(_usbd_q)) return; + if (osal_queue_empty(_usbd_q)) { return; } #endif } } diff --git a/src/host/usbh.c b/src/host/usbh.c index 5925a7be0..e60db53da 100644 --- a/src/host/usbh.c +++ b/src/host/usbh.c @@ -520,7 +520,7 @@ void tuh_task_ext(uint32_t timeout_ms, bool in_isr) { // Loop until there is no more events in the queue while (1) { hcd_event_t event; - if (!osal_queue_receive(_usbh_q, &event, timeout_ms)) return; + if (!osal_queue_receive(_usbh_q, &event, timeout_ms)) { return; } switch (event.event_id) { case HCD_EVENT_DEVICE_ATTACH: diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 01bbf62bf..292a352fb 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -62,8 +62,7 @@ #define QHD_MAX (CFG_TUH_DEVICE_MAX*CFG_TUH_ENDPOINT_MAX + CFG_TUH_HUB) #define QTD_MAX QHD_MAX -typedef struct -{ +typedef struct { ehci_link_t period_framelist[FRAMELIST_SIZE]; // TODO only implement 1 ms & 2 ms & 4 ms, 8 ms (framelist) @@ -139,6 +138,12 @@ static ehci_qhd_t* qhd_get_from_addr (uint8_t dev_addr, uint8_t ep_addr); static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc); static void qhd_attach_qtd(ehci_qhd_t *qhd, ehci_qtd_t *qtd); static void qhd_remove_qtd(ehci_qhd_t *qhd); +TU_ATTR_ALWAYS_INLINE static inline bool qhd_is_periodic(ehci_qhd_t const *qhd) { + return qhd->int_smask != 0; +} +TU_ATTR_ALWAYS_INLINE static inline uint8_t qhd_ep_addr(ehci_qhd_t const *qhd) { + return tu_edpt_addr(qhd->ep_number, qhd->pid); +} TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_control(uint8_t dev_addr); TU_ATTR_ALWAYS_INLINE static inline ehci_qtd_t* qtd_find_free (void); @@ -146,9 +151,10 @@ static void qtd_init (ehci_qtd_t* qtd, void const* buffer, uint16_t total_bytes) TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_get_period_head(uint8_t rhport, uint32_t interval_ms); TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* list_get_async_head(uint8_t rhport); -TU_ATTR_ALWAYS_INLINE static inline void list_insert (ehci_link_t *current, ehci_link_t *new, uint8_t new_type); TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_next (ehci_link_t const *p_link); -static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr); +TU_ATTR_ALWAYS_INLINE static inline void list_insert (ehci_link_t *current, ehci_link_t *entry, uint8_t type); +TU_ATTR_ALWAYS_INLINE static inline void list_remove(ehci_link_t* head, ehci_link_t* prev, ehci_qhd_t* qhd); +static void list_remove_qhd_by_addr(ehci_link_t *list_head, uint8_t dev_addr, uint8_t ep_addr); static void ehci_disable_schedule(ehci_registers_t* regs, bool is_period) { // maybe have a timeout for status @@ -175,15 +181,12 @@ static void ehci_enable_schedule(ehci_registers_t* regs, bool is_period) { //--------------------------------------------------------------------+ // HCD API //--------------------------------------------------------------------+ - -uint32_t hcd_frame_number(uint8_t rhport) -{ +uint32_t hcd_frame_number(uint8_t rhport) { (void) rhport; return (ehci_data.uframe_number + ehci_data.regs->frame_index) >> 3; } -void hcd_port_reset(uint8_t rhport) -{ +void hcd_port_reset(uint8_t rhport) { (void) rhport; ehci_registers_t* regs = ehci_data.regs; @@ -204,8 +207,7 @@ void hcd_port_reset(uint8_t rhport) regs->portsc = portsc; } -void hcd_port_reset_end(uint8_t rhport) -{ +void hcd_port_reset_end(uint8_t rhport) { (void) rhport; ehci_registers_t* regs = ehci_data.regs; @@ -221,32 +223,29 @@ void hcd_port_reset_end(uint8_t rhport) regs->portsc = portsc; } -bool hcd_port_connect_status(uint8_t rhport) -{ +bool hcd_port_connect_status(uint8_t rhport) { (void) rhport; return ehci_data.regs->portsc_bm.current_connect_status; } -tusb_speed_t hcd_port_speed_get(uint8_t rhport) -{ +tusb_speed_t hcd_port_speed_get(uint8_t rhport) { (void) rhport; return (tusb_speed_t) ehci_data.regs->portsc_bm.nxp_port_speed; // NXP specific port speed } // Close all opened endpoint belong to this device -void hcd_device_close(uint8_t rhport, uint8_t daddr) -{ +void hcd_device_close(uint8_t rhport, uint8_t daddr) { // skip dev0 if (daddr == 0) { return; } - // Remove from async list - list_remove_qhd_by_daddr((ehci_link_t *) list_get_async_head(rhport), daddr); + // Remove from async list all endpoints of this device + list_remove_qhd_by_addr((ehci_link_t *) list_get_async_head(rhport), daddr, TUSB_INDEX_INVALID_8); - // Remove from all interval period list - for(uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) { - list_remove_qhd_by_daddr((ehci_link_t *) &ehci_data.period_head_arr[i], daddr); + // Remove from all interval period list of this device + for (uint8_t i = 0; i < TU_ARRAY_SIZE(ehci_data.period_head_arr); i++) { + list_remove_qhd_by_addr((ehci_link_t *) &ehci_data.period_head_arr[i], daddr, TUSB_INDEX_INVALID_8); } // Async doorbell (EHCI 4.8.2 for operational details) @@ -358,12 +357,10 @@ bool ehci_init(uint8_t rhport, uint32_t capability_reg, uint32_t operatial_reg) } #if 0 -static void ehci_stop(uint8_t rhport) -{ +static void ehci_stop(uint8_t rhport) { (void) rhport; ehci_registers_t* regs = ehci_data.regs; - regs->command_bm.run_stop = 0; // USB Spec: controller has to stop within 16 uframe = 2 frames @@ -375,41 +372,44 @@ static void ehci_stop(uint8_t rhport) // Endpoint API //--------------------------------------------------------------------+ -bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) -{ - (void) rhport; - +bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { // TODO not support ISO yet TU_ASSERT (ep_desc->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS); //------------- Prepare Queue Head -------------// - ehci_qhd_t *p_qhd = (ep_desc->bEndpointAddress == 0) ? qhd_control(dev_addr) : qhd_find_free(); + ehci_qhd_t *p_qhd; + if (ep_desc->bEndpointAddress == 0) { + p_qhd = qhd_control(dev_addr); + } else { + TU_VERIFY(NULL == qhd_get_from_addr(dev_addr, ep_desc->bEndpointAddress)); // ep not opened yet + p_qhd = qhd_find_free(); + } TU_ASSERT(p_qhd); - qhd_init(p_qhd, dev_addr, ep_desc); - // control of dev0 is always present as async head - if ( dev_addr == 0 ) return true; + // control of dev0 always exists as async head + if (dev_addr == 0) { + return true; + } // Insert to list ehci_link_t * list_head = NULL; - - switch (ep_desc->bmAttributes.xfer) - { + switch (ep_desc->bmAttributes.xfer) { case TUSB_XFER_CONTROL: case TUSB_XFER_BULK: - list_head = (ehci_link_t*) list_get_async_head(rhport); - break; + list_head = (ehci_link_t *) list_get_async_head(rhport); + break; case TUSB_XFER_INTERRUPT: list_head = list_get_period_head(rhport, p_qhd->interval_ms); - break; + break; case TUSB_XFER_ISOCHRONOUS: // TODO iso is not supported - break; + break; - default: break; + default: + break; } TU_ASSERT(list_head); @@ -421,8 +421,23 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const return true; } -bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) -{ +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + ehci_qhd_t* qhd = qhd_get_from_addr(daddr, ep_addr); + TU_VERIFY(qhd != NULL); + + ehci_link_t * list_head; + if (qhd_is_periodic(qhd)) { + // interrupt endpoint + list_head = list_get_period_head(rhport, qhd->interval_ms);; + } else { + list_head = (ehci_link_t *) list_get_async_head(rhport); + } + + list_remove_qhd_by_addr(list_head, daddr, ep_addr); + return true; +} + +bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { (void) rhport; ehci_qhd_t* qhd = &ehci_data.control[dev_addr].qhd; @@ -444,14 +459,14 @@ bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet return true; } -bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) -{ +bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { (void) rhport; uint8_t const epnum = tu_edpt_number(ep_addr); uint8_t const dir = tu_edpt_dir(ep_addr); ehci_qhd_t* qhd = qhd_get_from_addr(dev_addr, ep_addr); + TU_VERIFY(qhd != NULL); ehci_qtd_t* qtd; if (epnum == 0) { @@ -540,8 +555,7 @@ bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { // This isr mean it is safe to modify previously removed queue head from async list. // In tinyusb, queue head is only removed when device is unplugged. TU_ATTR_ALWAYS_INLINE static inline -void async_advance_isr(uint8_t rhport) -{ +void async_advance_isr(uint8_t rhport) { (void) rhport; ehci_qhd_t *qhd_pool = ehci_data.qhd_pool; @@ -612,8 +626,7 @@ void qhd_xfer_complete_isr(ehci_qhd_t * qhd) { } TU_ATTR_ALWAYS_INLINE static inline -void proccess_async_xfer_isr(ehci_qhd_t * const list_head) -{ +void proccess_async_xfer_isr(ehci_qhd_t * const list_head) { ehci_qhd_t *qhd = list_head; do { @@ -623,8 +636,7 @@ void proccess_async_xfer_isr(ehci_qhd_t * const list_head) } TU_ATTR_ALWAYS_INLINE static inline -void process_period_xfer_isr(uint8_t rhport, uint32_t interval_ms) -{ +void process_period_xfer_isr(uint8_t rhport, uint32_t interval_ms) { uint32_t const period_1ms_addr = (uint32_t) list_get_period_head(rhport, 1u); ehci_link_t next_link = *list_get_period_head(rhport, interval_ms); @@ -726,51 +738,55 @@ TU_ATTR_ALWAYS_INLINE static inline ehci_link_t* list_next(ehci_link_t const *p_ return (ehci_link_t*) tu_align32(p_link->address); } -TU_ATTR_ALWAYS_INLINE static inline void list_insert(ehci_link_t *current, ehci_link_t *new, uint8_t new_type) -{ - new->address = current->address; - current->address = ((uint32_t) new) | (new_type << 1); +TU_ATTR_ALWAYS_INLINE static inline void list_insert(ehci_link_t *current, ehci_link_t *entry, uint8_t type) { + entry->address = current->address; + current->address = ((uint32_t) entry) | (type << 1); +} + +// Remove a queue head from the list. +// Per EHCI 4.8.2 the removed qhd's next is linked to list head (which always reachable by Host Controller) +// TODO support iTD/siTD +TU_ATTR_ALWAYS_INLINE static inline void list_remove(ehci_link_t* head, ehci_link_t* prev, ehci_qhd_t* qhd) { + // TODO deactivate all TD, wait for QHD to inactive before removal + prev->address = qhd->next.address; + + // link the removed qhd's next to list head + qhd->next.address = ((uint32_t) head) | (EHCI_QTYPE_QHD << 1); + + if (qhd_is_periodic(qhd)) { + // period list queue element is guarantee to be free in the next frame (1 ms) + qhd->used = 0; + } else { + // async list use async advance handshake. Mark as removing, will completely re-usable when async advance isr occurs + qhd->removing = 1; + } + + hcd_dcache_clean(qhd, sizeof(ehci_qhd_t)); + hcd_dcache_clean(prev, sizeof(ehci_qhd_t)); } -// Remove all queue head belong to this device address -static void list_remove_qhd_by_daddr(ehci_link_t* list_head, uint8_t dev_addr) { - ehci_link_t* prev = list_head; +// Remove queue head belong to this device address +static void list_remove_qhd_by_addr(ehci_link_t *list_head, uint8_t dev_addr, uint8_t ep_addr) { + ehci_link_t *prev = list_head; while (prev && !prev->terminate) { - ehci_qhd_t* qhd = (ehci_qhd_t*) (uintptr_t) list_next(prev); + ehci_qhd_t *qhd = (ehci_qhd_t *) (uintptr_t) list_next(prev); // done if loop back to head - if ( (uintptr_t) qhd == (uintptr_t) list_head) { + if ((uintptr_t) qhd == (uintptr_t) list_head) { break; } - if ( qhd->dev_addr == dev_addr ) { - // TODO deactivate all TD, wait for QHD to inactive before removal - prev->address = qhd->next.address; - - // EHCI 4.8.2 link the removed qhd's next to async head (which always reachable by Host Controller) - qhd->next.address = ((uint32_t) list_head) | (EHCI_QTYPE_QHD << 1); - - if ( qhd->int_smask ) - { - // period list queue element is guarantee to be free in the next frame (1 ms) - qhd->used = 0; - }else - { - // async list use async advance handshake - // mark as removing, will completely re-usable when async advance isr occurs - qhd->removing = 1; - } - - hcd_dcache_clean(qhd, sizeof(ehci_qhd_t)); - hcd_dcache_clean(prev, sizeof(ehci_qhd_t)); - }else { + // ep_addr is 0xff means all endpoints of this device address + if (qhd->dev_addr == dev_addr && + (ep_addr == TUSB_INDEX_INVALID_8 || qhd_ep_addr(qhd) == ep_addr)) { + list_remove(list_head, prev, qhd); + } else { prev = list_next(prev); } } } - //--------------------------------------------------------------------+ // Queue Header helper //--------------------------------------------------------------------+ @@ -782,8 +798,10 @@ TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t* qhd_control(uint8_t dev_addr) { // Find a free queue head TU_ATTR_ALWAYS_INLINE static inline ehci_qhd_t *qhd_find_free(void) { - for ( uint32_t i = 0; i < QHD_MAX; i++ ) { - if ( !ehci_data.qhd_pool[i].used ) return &ehci_data.qhd_pool[i]; + for (uint32_t i = 0; i < QHD_MAX; i++) { + if (!ehci_data.qhd_pool[i].used) { + return &ehci_data.qhd_pool[i]; + } } return NULL; } @@ -800,10 +818,9 @@ static ehci_qhd_t *qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) { } ehci_qhd_t *qhd_pool = ehci_data.qhd_pool; - - for ( uint32_t i = 0; i < QHD_MAX; i++ ) { - if ( (qhd_pool[i].dev_addr == dev_addr) && - ep_addr == tu_edpt_addr(qhd_pool[i].ep_number, qhd_pool[i].pid) ) { + for (uint32_t i = 0; i < QHD_MAX; i++) { + if ((qhd_pool[i].dev_addr == dev_addr) && + ep_addr == qhd_ep_addr(&qhd_pool[i])) { return &qhd_pool[i]; } } @@ -812,8 +829,7 @@ static ehci_qhd_t *qhd_get_from_addr(uint8_t dev_addr, uint8_t ep_addr) { } // Init queue head with endpoint descriptor -static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) -{ +static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { // address 0 is used as async head, which always on the list --> cannot be cleared (ehci halted otherwise) if (dev_addr != 0) { tu_memclr(p_qhd, sizeof(ehci_qhd_t)); @@ -830,39 +846,43 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c p_qhd->ep_number = tu_edpt_number(ep_desc->bEndpointAddress); p_qhd->ep_speed = devtree_info.speed; p_qhd->data_toggle_control= (xfer_type == TUSB_XFER_CONTROL) ? 1 : 0; - p_qhd->head_list_flag = (dev_addr == 0) ? 1 : 0; // addr0's endpoint is the static asyn list head + p_qhd->head_list_flag = (dev_addr == 0) ? 1 : 0; // addr0's endpoint is the static async list head p_qhd->max_packet_size = tu_edpt_packet_size(ep_desc); p_qhd->fl_ctrl_ep_flag = ((xfer_type == TUSB_XFER_CONTROL) && (p_qhd->ep_speed != TUSB_SPEED_HIGH)) ? 1 : 0; p_qhd->nak_reload = 0; - // Bulk/Control -> smask = cmask = 0 - // TODO Isochronous - if (TUSB_XFER_INTERRUPT == xfer_type) - { - if (TUSB_SPEED_HIGH == p_qhd->ep_speed) - { - TU_ASSERT( interval <= 16, ); - if ( interval < 4) // sub millisecond interval - { - p_qhd->interval_ms = 0; - p_qhd->int_smask = (interval == 1) ? TU_BIN8(11111111) : - (interval == 2) ? TU_BIN8(10101010) : TU_BIN8(01000100); - }else - { - p_qhd->interval_ms = (uint8_t) tu_min16( 1 << (interval-4), 255 ); - p_qhd->int_smask = TU_BIT(interval % 8); + switch (xfer_type) { + case TUSB_XFER_CONTROL: + case TUSB_XFER_BULK: + p_qhd->int_smask = p_qhd->fl_int_cmask = 0; + break; + + case TUSB_XFER_INTERRUPT: + if (TUSB_SPEED_HIGH == p_qhd->ep_speed) { + TU_ASSERT(interval <= 16, ); + if (interval < 4) { + // sub millisecond interval + p_qhd->interval_ms = 0; + p_qhd->int_smask = (interval == 1) ? TU_BIN8(11111111) : + (interval == 2) ? TU_BIN8(10101010): TU_BIN8(01000100); + } else { + p_qhd->interval_ms = (uint8_t) tu_min16(1 << (interval - 4), 255); + p_qhd->int_smask = TU_BIT(interval % 8); + } + } else { + TU_ASSERT(0 != interval, ); + // Full/Low: 4.12.2.1 (EHCI) case 1 schedule start split at 1 us & complete split at 2,3,4 uframes + p_qhd->int_smask = 0x01; + p_qhd->fl_int_cmask = TU_BIN8(11100); + p_qhd->interval_ms = interval; } - }else - { - TU_ASSERT( 0 != interval, ); - // Full/Low: 4.12.2.1 (EHCI) case 1 schedule start split at 1 us & complete split at 2,3,4 uframes - p_qhd->int_smask = 0x01; - p_qhd->fl_int_cmask = TU_BIN8(11100); - p_qhd->interval_ms = interval; - } - }else - { - p_qhd->int_smask = p_qhd->fl_int_cmask = 0; + break; + + case TUSB_XFER_ISOCHRONOUS: + // TODO not support ISO yet + break; + + default: break; } p_qhd->fl_hub_addr = devtree_info.hub_addr; @@ -880,8 +900,7 @@ static void qhd_init(ehci_qhd_t *p_qhd, uint8_t dev_addr, tusb_desc_endpoint_t c p_qhd->qtd_overlay.next.terminate = 1; p_qhd->qtd_overlay.alternate.terminate = 1; - if (TUSB_XFER_BULK == xfer_type && p_qhd->ep_speed == TUSB_SPEED_HIGH && p_qhd->pid == EHCI_PID_OUT) - { + if (TUSB_XFER_BULK == xfer_type && p_qhd->ep_speed == TUSB_SPEED_HIGH && p_qhd->pid == EHCI_PID_OUT) { p_qhd->qtd_overlay.ping_err = 1; // do PING for Highspeed Bulk OUT, EHCI section 4.11 } } diff --git a/src/portable/ehci/ehci.h b/src/portable/ehci/ehci.h index 457adc1d3..87659701b 100644 --- a/src/portable/ehci/ehci.h +++ b/src/portable/ehci/ehci.h @@ -49,15 +49,14 @@ // TODO merge OHCI with EHCI enum { - EHCI_MAX_ITD = 4, + EHCI_MAX_ITD = 4, EHCI_MAX_SITD = 16 }; //--------------------------------------------------------------------+ // EHCI Data Structure //--------------------------------------------------------------------+ -enum -{ +enum { EHCI_QTYPE_ITD = 0 , EHCI_QTYPE_QHD , EHCI_QTYPE_SITD , @@ -65,8 +64,7 @@ enum }; /// EHCI PID -enum -{ +enum { EHCI_PID_OUT = 0 , EHCI_PID_IN , EHCI_PID_SETUP @@ -74,187 +72,182 @@ enum /// Link pointer typedef union { - uint32_t address; - struct { - uint32_t terminate : 1; - uint32_t type : 2; - }; -}ehci_link_t; + uint32_t address; + struct { + uint32_t terminate : 1; + uint32_t type : 2; + }; +} ehci_link_t; TU_VERIFY_STATIC( sizeof(ehci_link_t) == 4, "size is not correct" ); /// Queue Element Transfer Descriptor /// Qtd is used to declare overlay in ehci_qhd_t -> cannot be declared with TU_ATTR_ALIGNED(32) -typedef struct -{ - // Word 0: Next QTD Pointer - ehci_link_t next; - - // Word 1: Alternate Next QTD Pointer (not used) - union{ - ehci_link_t alternate; - struct { - uint32_t : 5; - uint32_t used : 1; - uint32_t : 10; - uint32_t expected_bytes : 16; - }; - }; - - // Word 2: qTQ Token - volatile uint32_t ping_err : 1 ; ///< For Highspeed: 0 Out, 1 Ping. Full/Slow used as error indicator - volatile uint32_t non_hs_split_state : 1 ; ///< Used by HC to track the state of split transaction - volatile uint32_t non_hs_missed_uframe : 1 ; ///< HC misses a complete split transaction - volatile uint32_t xact_err : 1 ; ///< Error (Timeout, CRC, Bad PID ... ) - volatile uint32_t babble_err : 1 ; ///< Babble detected, also set Halted bit to 1 - volatile uint32_t buffer_err : 1 ; ///< Data overrun/underrun error - volatile uint32_t halted : 1 ; ///< Serious error or STALL received - volatile uint32_t active : 1 ; ///< Start transfer, clear by HC when complete - - uint32_t pid : 2 ; ///< 0: OUT, 1: IN, 2 Setup - volatile uint32_t err_count : 2 ; ///< Error Counter of consecutive errors - volatile uint32_t current_page : 3 ; ///< Index into the qTD buffer pointer list - uint32_t int_on_complete : 1 ; ///< Interrupt on complete - volatile uint32_t total_bytes : 15 ; ///< Transfer bytes, decreased during transaction - volatile uint32_t data_toggle : 1 ; ///< Data Toggle bit - - - /// Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page - uint32_t buffer[5]; +typedef struct { + // Word 0 Next QTD Pointer + ehci_link_t next; + + // Word 1 Alternate Next QTD Pointer (not used) + union { + ehci_link_t alternate; + struct { + uint32_t : 5; + uint32_t used : 1; + uint32_t : 10; + uint32_t expected_bytes : 16; + }; + }; + + // Word 2 qTQ Token + volatile uint32_t ping_err : 1; // For Highspeed: 0 Out, 1 Ping. Full/Slow used as error indicator + volatile uint32_t non_hs_split_state : 1; // Used by HC to track the state of split transaction + volatile uint32_t non_hs_missed_uframe : 1; // HC misses a complete split transaction + volatile uint32_t xact_err : 1; // Error (Timeout, CRC, Bad PID ... ) + volatile uint32_t babble_err : 1; // Babble detected, also set Halted bit to 1 + volatile uint32_t buffer_err : 1; // Data overrun/underrun error + volatile uint32_t halted : 1; // Serious error or STALL received + volatile uint32_t active : 1; // Start transfer, clear by HC when complete + + uint32_t pid : 2; // 0: OUT, 1: IN, 2 Setup + volatile uint32_t err_count : 2; // Error Counter of consecutive errors + volatile uint32_t current_page : 3; // Index into the qTD buffer pointer list + uint32_t int_on_complete : 1; // Interrupt on complete + volatile uint32_t total_bytes : 15; // Transfer bytes, decreased during transaction + volatile uint32_t data_toggle : 1; // Data Toggle bit + + // Buffer Page Pointer List, Each element in the list is a 4K page aligned, physical memory address. + // The lower 12 bits in each pointer are reserved (except for the first one) as each memory pointer must reference the start of a 4K page + uint32_t buffer[5]; } ehci_qtd_t; TU_VERIFY_STATIC( sizeof(ehci_qtd_t) == 32, "size is not correct" ); /// Queue Head -typedef struct TU_ATTR_ALIGNED(32) -{ - // Word 0: Next QHD - ehci_link_t next; - - // Word 1: Endpoint Characteristics - uint32_t dev_addr : 7 ; ///< device address - uint32_t fl_inactive_next_xact : 1 ; ///< Only valid for Periodic with Full/Slow speed - uint32_t ep_number : 4 ; ///< EP number - uint32_t ep_speed : 2 ; ///< 0: Full, 1: Low, 2: High - uint32_t data_toggle_control : 1 ; ///< 0: use DT in qHD, 1: use DT in qTD - uint32_t head_list_flag : 1 ; ///< Head of the queue - uint32_t max_packet_size : 11 ; ///< Max packet size - uint32_t fl_ctrl_ep_flag : 1 ; ///< 1 if is Full/Low speed control endpoint - uint32_t nak_reload : 4 ; ///< Used by HC - - // Word 2: Endpoint Capabilities - uint32_t int_smask : 8 ; ///< Interrupt Schedule Mask - uint32_t fl_int_cmask : 8 ; ///< Split Completion Mask for Full/Slow speed - uint32_t fl_hub_addr : 7 ; ///< Hub Address for Full/Slow speed - uint32_t fl_hub_port : 7 ; ///< Hub Port for Full/Slow speed - uint32_t mult : 2 ; ///< Transaction per micro frame - - // Word 3: Current qTD Pointer - volatile uint32_t qtd_addr; - - // Word 4-11: Transfer Overlay - volatile ehci_qtd_t qtd_overlay; - - //--------------------------------------------------------------------+ +typedef struct TU_ATTR_ALIGNED(32) { + // Word 0 Next QHD + ehci_link_t next; + + // Word 1 Endpoint Characteristics + uint32_t dev_addr : 7; // device address + uint32_t fl_inactive_next_xact : 1; // Only valid for Periodic with Full/Slow speed + uint32_t ep_number : 4; // EP number + uint32_t ep_speed : 2; // Full (0), Low (1), High (2) + uint32_t data_toggle_control : 1; // 0 use DT in qHD, 1 use DT in qTD + uint32_t head_list_flag : 1; // Head of the queue + uint32_t max_packet_size : 11; // Max packet size + uint32_t fl_ctrl_ep_flag : 1; // 1 if is Full/Low speed control endpoint + uint32_t nak_reload : 4; // Used by HC + + // Word 2 Endpoint Capabilities + uint32_t int_smask : 8; // Interrupt Schedule Mask + uint32_t fl_int_cmask : 8; // Split Completion Mask for Full/Slow speed + uint32_t fl_hub_addr : 7; // Hub Address for Full/Slow speed + uint32_t fl_hub_port : 7; // Hub Port for Full/Slow speed + uint32_t mult : 2; // Transaction per micro frame + + // Word 3 Current qTD Pointer + volatile uint32_t qtd_addr; + + // Word 4-11 Transfer Overlay + volatile ehci_qtd_t qtd_overlay; + + //--------------------------------------------------------------------+ /// Due to the fact QHD is 32 bytes aligned but occupies only 48 bytes - /// thus there are 16 bytes padding free that we can make use of. + /// thus there are 16 bytes padding free that we can make use of. //--------------------------------------------------------------------+ - uint8_t used; - uint8_t removing; // removed from asyn list, waiting for async advance - uint8_t pid; - uint8_t interval_ms; // polling interval in frames (or millisecond) + uint8_t used; + uint8_t removing;// removed from asyn list, waiting for async advance + uint8_t pid; + uint8_t interval_ms;// polling interval in frames (or millisecond) - uint8_t TU_RESERVED[4]; + uint8_t TU_RESERVED[4]; // Attached TD management, note usbh will only queue 1 TD per QHD. // buffer for dcache invalidate since td's buffer is modified by HC and finding initial buffer address is not trivial uint32_t attached_buffer; - ehci_qtd_t * volatile attached_qtd; + ehci_qtd_t *volatile attached_qtd; } ehci_qhd_t; - TU_VERIFY_STATIC( sizeof(ehci_qhd_t) == 64, "size is not correct" ); /// Highspeed Isochronous Transfer Descriptor (section 3.3) typedef struct TU_ATTR_ALIGNED(32) { - // Word 0: Next Link Pointer - ehci_link_t next; - - // Word 1-8: iTD Transaction Status and Control List - struct { - // iTD Control - volatile uint32_t offset : 12 ; ///< This field is a value that is an offset, expressed in bytes, from the beginning of a buffer. - volatile uint32_t page_select : 3 ; ///< These bits are set by software to indicate which of the buffer page pointers the offset field in this slot should be concatenated to produce the starting memory address for this transaction. The valid range of values for this field is 0 to 6 - uint32_t int_on_complete : 1 ; ///< If this bit is set to a one, it specifies that when this transaction completes, the Host Controller should issue an interrupt at the next interrupt threshold - volatile uint32_t length : 12 ; ///< For an OUT, this field is the number of data bytes the host controller will send during the transaction. The host controller is not required to update this field to reflect the actual number of bytes transferred during the transfer - ///< For an IN, the initial value of the field is the number of bytes the host expects the endpoint to deliver. During the status update, the host controller writes back the number of bytes successfully received. The value in this register is the actual byte count - // iTD Status - volatile uint32_t error : 1 ; ///< Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit may only be set for isochronous IN transactions. - volatile uint32_t babble_err : 1 ; ///< Set to a 1 by the Host Controller during status update when a babble is detected during the transaction - volatile uint32_t buffer_err : 1 ; ///< Set to a 1 by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (underrun). - volatile uint32_t active : 1 ; ///< Set to 1 by software to enable the execution of an isochronous transaction by the Host Controller - } xact[8]; - - // Word 9-15 Buffer Page Pointer List (Plus) - uint32_t BufferPointer[7]; - -// // FIXME: Store meta data into buffer pointer reserved for saving memory -// /*---------- HCD Area ----------*/ -// uint32_t used; -// uint32_t IhdIdx; -// uint32_t reserved[6]; + // Word 0: Next Link Pointer + ehci_link_t next; + + // Word 1-8: iTD Transaction Status and Control List + struct { + // iTD Control + volatile uint32_t offset : 12; // offset in bytes, from the beginning of a buffer. + volatile uint32_t page_select : 3; // buffer page pointers the offset field in this slot should be concatenated to produce the starting memory address for this transaction. The valid range of values for this field is 0 to 6 + uint32_t int_on_complete : 1; // If this bit is set to a one, it specifies that when this transaction completes, the Host Controller should issue an interrupt at the next interrupt threshold + volatile uint32_t length : 12; // For an OUT, this field is the number of data bytes the host controller will send during the transaction. The host controller is not required to update this field to reflect the actual number of bytes transferred during the transfer + // For an IN, the initial value of the field is the number of bytes the host expects the endpoint to deliver. During the status update, the host controller writes back the number of bytes successfully received. The value in this register is the actual byte count + // iTD Status + volatile uint32_t error : 1; // Set to a one by the Host Controller during status update in the case where the host did not receive a valid response from the device (Timeout, CRC, Bad PID, etc.). This bit may only be set for isochronous IN transactions. + volatile uint32_t babble_err : 1; // Set to a 1 by the Host Controller during status update when a babble is detected during the transaction + volatile uint32_t buffer_err : 1; // Set to a 1 by the Host Controller during status update to indicate that the Host Controller is unable to keep up with the reception of incoming data (overrun) or is unable to supply data fast enough during transmission (underrun). + volatile uint32_t active : 1; // Set to 1 by software to enable the execution of an isochronous transaction by the Host Controller + } xact[8]; + + // Word 9-15 Buffer Page Pointer List (Plus) + uint32_t BufferPointer[7]; + + // FIXME: Store meta data into buffer pointer reserved for saving memory + //---------- HCD Area ---------- + // uint32_t used; + // uint32_t IhdIdx; + // uint32_t reserved[6]; } ehci_itd_t; - TU_VERIFY_STATIC( sizeof(ehci_itd_t) == 64, "size is not correct" ); /// Split (Full-Speed) Isochronous Transfer Descriptor -typedef struct TU_ATTR_ALIGNED(32) -{ +typedef struct TU_ATTR_ALIGNED(32) { // Word 0: Next Link Pointer - ehci_link_t next; - - // Word 1: siTD Endpoint Characteristics - uint32_t dev_addr : 7; ///< This field selects the specific device serving as the data source or sink. - uint32_t : 1; ///< reserved - uint32_t ep_number : 4; ///< This 4-bit field selects the particular endpoint number on the device serving as the data source or sink. - uint32_t : 4; ///< This field is reserved and should be set to zero. - uint32_t hub_addr : 7; ///< This field holds the device address of the transaction translators’ hub. - uint32_t : 1; ///< reserved - uint32_t port_number : 7; ///< This field is the port number of the recipient transaction translator. - uint32_t direction : 1; ///< 0 = OUT; 1 = IN. This field encodes whether the full-speed transaction should be an IN or OUT. - - // Word 2: Micro-frame Schedule Control - uint8_t int_smask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute complete-split transactions - uint8_t fl_int_cmask; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute start-split transactions. - uint16_t reserved ; ///< reserved - - // Word 3: siTD Transfer Status and Control - // Status [7:0] TODO identical to qTD Token'status --> refactor later - volatile uint32_t : 1 ; // reserved - volatile uint32_t split_state : 1 ; - volatile uint32_t missed_uframe : 1 ; - volatile uint32_t xact_err : 1 ; - volatile uint32_t babble_err : 1 ; - volatile uint32_t buffer_err : 1 ; - volatile uint32_t error : 1 ; - volatile uint32_t active : 1 ; - // Micro-frame Schedule Control - volatile uint32_t cmask_progress : 8 ; ///< This field is used by the host controller to record which split-completes have been executed. See Section 4.12.3.3.2 for behavioral requirements. - volatile uint32_t total_bytes : 10 ; ///< This field is initialized by software to the total number of bytes expected in this transfer. Maximum value is 1023 - volatile uint32_t : 4 ; ///< reserved - volatile uint32_t page_select : 1 ; ///< Used to indicate which data page pointer should be concatenated with the CurrentOffsetfield to construct a data buffer pointer - uint32_t int_on_complete : 1 ; ///< Do not interrupt when transaction is complete. 1 = Do interrupt when transaction is complete - uint32_t : 0 ; // padding to the end of current storage unit - - /// Word 4-5: Buffer Pointer List - uint32_t buffer[2]; // buffer[1] TP: Transaction Position - T-Count: Transaction Count - - /*---------- Word 6 ----------*/ - ehci_link_t back; - - /// SITD is 32-byte aligned but occupies only 28 --> 4 bytes for storing extra data - uint8_t used; - uint8_t ihd_idx; - uint8_t reserved2[2]; + ehci_link_t next; + + // Word 1: siTD Endpoint Characteristics + uint32_t dev_addr : 7; ///< This field selects the specific device serving as the data source or sink. + uint32_t : 1; ///< reserved + uint32_t ep_number : 4; ///< This 4-bit field selects the particular endpoint number on the device serving as the data source or sink. + uint32_t : 4; ///< This field is reserved and should be set to zero. + uint32_t hub_addr : 7; ///< This field holds the device address of the transaction translators’ hub. + uint32_t : 1; ///< reserved + uint32_t port_number : 7; ///< This field is the port number of the recipient transaction translator. + uint32_t direction : 1; ///< 0 = OUT; 1 = IN. This field encodes whether the full-speed transaction should be an IN or OUT. + + // Word 2: Micro-frame Schedule Control + uint8_t int_smask ; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute complete-split transactions + uint8_t fl_int_cmask; ///< This field (along with the Activeand SplitX-statefields in the Statusbyte) are used to determine during which micro-frames the host controller should execute start-split transactions. + uint16_t reserved ; ///< reserved + + // Word 3: siTD Transfer Status and Control + // Status [7:0] TODO identical to qTD Token'status --> refactor later + volatile uint32_t : 1 ; // reserved + volatile uint32_t split_state : 1 ; + volatile uint32_t missed_uframe : 1 ; + volatile uint32_t xact_err : 1 ; + volatile uint32_t babble_err : 1 ; + volatile uint32_t buffer_err : 1 ; + volatile uint32_t error : 1 ; + volatile uint32_t active : 1 ; + // Micro-frame Schedule Control + volatile uint32_t cmask_progress : 8 ; ///< This field is used by the host controller to record which split-completes have been executed. See Section 4.12.3.3.2 for behavioral requirements. + volatile uint32_t total_bytes : 10 ; ///< This field is initialized by software to the total number of bytes expected in this transfer. Maximum value is 1023 + volatile uint32_t : 4 ; ///< reserved + volatile uint32_t page_select : 1 ; ///< Used to indicate which data page pointer should be concatenated with the CurrentOffsetfield to construct a data buffer pointer + uint32_t int_on_complete : 1 ; ///< Do not interrupt when transaction is complete. 1 = Do interrupt when transaction is complete + uint32_t : 0 ; // padding to the end of current storage unit + + /// Word 4-5: Buffer Pointer List + uint32_t buffer[2]; // buffer[1] TP: Transaction Position - T-Count: Transaction Count + + /*---------- Word 6 ----------*/ + ehci_link_t back; + + /// SITD is 32-byte aligned but occupies only 28 --> 4 bytes for storing extra data + uint8_t used; + uint8_t ihd_idx; + uint8_t reserved2[2]; } ehci_sitd_t; TU_VERIFY_STATIC( sizeof(ehci_sitd_t) == 32, "size is not correct" ); @@ -315,8 +308,7 @@ enum { EHCI_PORTSC_MASK_OVER_CURRENT_CHANGE }; -typedef volatile struct -{ +typedef volatile struct { union { uint32_t command; // 0x00 diff --git a/test/hil/hil_test.py b/test/hil/hil_test.py index 662bb3a1f..8b89de66c 100755 --- a/test/hil/hil_test.py +++ b/test/hil/hil_test.py @@ -340,8 +340,8 @@ def test_host_device_info(board): ser.close() if len(data) == 0: assert False, 'No data from device' - lines = data.decode('utf-8', errors='ignore').splitlines() + enum_dev_sn = [] for l in lines: vid_pid_sn = re.search(r'ID ([0-9a-fA-F]+):([0-9a-fA-F]+) SN (\w+)', l) @@ -353,7 +353,6 @@ def test_host_device_info(board): failed_msg = f'Expected {declared_devs}, Enumerated {enum_dev_sn}' print('\n'.join(lines)) assert False, failed_msg - return 0 -- cgit v1.3.1 From e511d00f34b2832ae32ad0b2418a0878c7c4e7d6 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 26 Mar 2025 22:11:44 +0700 Subject: added hcd_edpt_close() stub for other ports --- src/portable/mentor/musb/hcd_musb.c | 5 +++ src/portable/nxp/khci/hcd_khci.c | 5 +++ src/portable/ohci/ohci.c | 6 +++- src/portable/raspberrypi/rp2040/hcd_rp2040.c | 6 +++- src/portable/renesas/rusb2/hcd_rusb2.c | 5 +++ src/portable/synopsys/dwc2/hcd_dwc2.c | 5 +++ src/portable/template/hcd_template.c | 49 ++++++++-------------------- 7 files changed, 44 insertions(+), 37 deletions(-) (limited to 'src/portable') diff --git a/src/portable/mentor/musb/hcd_musb.c b/src/portable/mentor/musb/hcd_musb.c index 1c0740193..811043d74 100644 --- a/src/portable/mentor/musb/hcd_musb.c +++ b/src/portable/mentor/musb/hcd_musb.c @@ -804,6 +804,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const return true; } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; (void) daddr; (void) ep_addr; + return false; // TODO not implemented yet +} + bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) { (void)rhport; diff --git a/src/portable/nxp/khci/hcd_khci.c b/src/portable/nxp/khci/hcd_khci.c index 056dbf40b..c3c901c5d 100644 --- a/src/portable/nxp/khci/hcd_khci.c +++ b/src/portable/nxp/khci/hcd_khci.c @@ -541,6 +541,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const return true; } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; (void) daddr; (void) ep_addr; + return false; // TODO not implemented yet +} + /* The address of buffer must be aligned to 4 byte boundary. And it must be at least 4 bytes long. * DMA writes data in 4 byte unit */ bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) diff --git a/src/portable/ohci/ohci.c b/src/portable/ohci/ohci.c index ce35eab70..672ad0443 100644 --- a/src/portable/ohci/ohci.c +++ b/src/portable/ohci/ohci.c @@ -451,7 +451,6 @@ static void td_insert_to_ed(ohci_ed_t* p_ed, ohci_gtd_t * p_gtd) //--------------------------------------------------------------------+ // Endpoint API //--------------------------------------------------------------------+ - bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { (void) rhport; @@ -486,6 +485,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const return true; } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; (void) daddr; (void) ep_addr; + return false; // TODO not implemented yet +} + bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { (void) rhport; diff --git a/src/portable/raspberrypi/rp2040/hcd_rp2040.c b/src/portable/raspberrypi/rp2040/hcd_rp2040.c index 478c6e789..cd8c905d5 100644 --- a/src/portable/raspberrypi/rp2040/hcd_rp2040.c +++ b/src/portable/raspberrypi/rp2040/hcd_rp2040.c @@ -514,7 +514,6 @@ void hcd_int_disable(uint8_t rhport) //--------------------------------------------------------------------+ // Endpoint API //--------------------------------------------------------------------+ - bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { (void) rhport; @@ -535,6 +534,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const return true; } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; (void) daddr; (void) ep_addr; + return false; // TODO not implemented yet +} + bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { (void) rhport; diff --git a/src/portable/renesas/rusb2/hcd_rusb2.c b/src/portable/renesas/rusb2/hcd_rusb2.c index 4c81b05be..3e4b36981 100644 --- a/src/portable/renesas/rusb2/hcd_rusb2.c +++ b/src/portable/renesas/rusb2/hcd_rusb2.c @@ -718,6 +718,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const return true; } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; (void) daddr; (void) ep_addr; + return false; // TODO not implemented yet +} + bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t *buffer, uint16_t buflen) { bool r; diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index b13479b02..f0cea529e 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -506,6 +506,11 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, const tusb_desc_endpoint_t* return true; } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; (void) daddr; (void) ep_addr; + return false; // TODO not implemented yet +} + // clean up channel after part of transfer is done but the whole urb is not complete static void channel_xfer_out_wrapup(dwc2_regs_t* dwc2, uint8_t ch_id) { hcd_xfer_t* xfer = &_hcd_data.xfer[ch_id]; diff --git a/src/portable/template/hcd_template.c b/src/portable/template/hcd_template.c index d8bca196f..1202c4ef4 100644 --- a/src/portable/template/hcd_template.c +++ b/src/portable/template/hcd_template.c @@ -36,24 +36,19 @@ // optional hcd configuration, called by tuh_configure() bool hcd_configure(uint8_t rhport, uint32_t cfg_id, const void* cfg_param) { - (void) rhport; - (void) cfg_id; - (void) cfg_param; - + (void) rhport; (void) cfg_id; (void) cfg_param; return false; } // Initialize controller to host mode bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { - (void) rhport; - (void) rh_init; + (void) rhport; (void) rh_init; return false; } // Interrupt Handler void hcd_int_handler(uint8_t rhport, bool in_isr) { - (void) rhport; - (void) in_isr; + (void) rhport; (void) in_isr; } // Enable USB interrupt @@ -69,7 +64,6 @@ void hcd_int_disable(uint8_t rhport) { // Get frame number (1ms) uint32_t hcd_frame_number(uint8_t rhport) { (void) rhport; - return 0; } @@ -80,7 +74,6 @@ uint32_t hcd_frame_number(uint8_t rhport) { // Get the current connect status of roothub port bool hcd_port_connect_status(uint8_t rhport) { (void) rhport; - return false; } @@ -98,14 +91,12 @@ void hcd_port_reset_end(uint8_t rhport) { // Get port link speed tusb_speed_t hcd_port_speed_get(uint8_t rhport) { (void) rhport; - return TUSB_SPEED_FULL; } // HCD closes all opened endpoints belong to this device void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { - (void) rhport; - (void) dev_addr; + (void) rhport; (void) dev_addr; } //--------------------------------------------------------------------+ @@ -114,49 +105,37 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr) { // Open an endpoint bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc) { - (void) rhport; - (void) dev_addr; - (void) ep_desc; - + (void) rhport; (void) dev_addr; (void) ep_desc; return false; } +bool hcd_edpt_close(uint8_t rhport, uint8_t daddr, uint8_t ep_addr) { + (void) rhport; (void) daddr; (void) ep_addr; + return false; // TODO not implemented yet +} + // Submit a transfer, when complete hcd_event_xfer_complete() must be invoked bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen) { - (void) rhport; - (void) dev_addr; - (void) ep_addr; - (void) buffer; - (void) buflen; - + (void) rhport; (void) dev_addr; (void) ep_addr; (void) buffer; (void) buflen; return false; } // Abort a queued transfer. Note: it can only abort transfer that has not been started // Return true if a queued transfer is aborted, false if there is no transfer to abort bool hcd_edpt_abort_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { - (void) rhport; - (void) dev_addr; - (void) ep_addr; - + (void) rhport; (void) dev_addr; (void) ep_addr; return false; } // Submit a special transfer to send 8-byte Setup Packet, when complete hcd_event_xfer_complete() must be invoked bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]) { - (void) rhport; - (void) dev_addr; - (void) setup_packet; - + (void) rhport; (void) dev_addr; (void) setup_packet; return false; } // clear stall, data toggle is also reset to DATA0 bool hcd_edpt_clear_stall(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr) { - (void) rhport; - (void) dev_addr; - (void) ep_addr; - + (void) rhport; (void) dev_addr; (void) ep_addr; return false; } -- cgit v1.3.1 From 4787cd5f546eabad630fc5c22f37f67a076ac37e Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 3 Apr 2025 18:11:33 +0700 Subject: fix(hcd) hcd_edpt_open() return true if endpoint is already opened. --- examples/host/device_info/src/main.c | 31 ++++++++++++++++++++----------- src/host/hcd.h | 1 + src/portable/analog/max3421/hcd_max3421.c | 2 +- src/portable/ehci/ehci.c | 4 +++- 4 files changed, 25 insertions(+), 13 deletions(-) (limited to 'src/portable') diff --git a/examples/host/device_info/src/main.c b/examples/host/device_info/src/main.c index ac4c46a11..e924a137b 100644 --- a/examples/host/device_info/src/main.c +++ b/examples/host/device_info/src/main.c @@ -124,13 +124,18 @@ void tuh_mount_cb(uint8_t daddr) { } printf("Device %u: ID %04x:%04x SN ", daddr, desc.device.idVendor, desc.device.idProduct); - xfer_result = tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, desc.serial, sizeof(desc.serial)); + + xfer_result = XFER_RESULT_FAILED; + if (desc.device.iSerialNumber != 0) { + xfer_result = tuh_descriptor_get_serial_string_sync(daddr, LANGUAGE_ID, desc.serial, sizeof(desc.serial)); + } if (XFER_RESULT_SUCCESS != xfer_result) { uint16_t* serial = (uint16_t*)(uintptr_t) desc.serial; - serial[0] = 'n'; - serial[1] = '/'; - serial[2] = 'a'; - serial[3] = 0; + serial[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * 3 + 2)); + serial[1] = 'n'; + serial[2] = '/'; + serial[3] = 'a'; + serial[4] = 0; } print_utf16((uint16_t*)(uintptr_t) desc.serial, sizeof(desc.serial)/2); printf("\r\n"); @@ -150,16 +155,20 @@ void tuh_mount_cb(uint8_t daddr) { // Get String descriptor using Sync API printf(" iManufacturer %u ", desc.device.iManufacturer); - xfer_result = tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, desc.buf, sizeof(desc.buf)); - if (XFER_RESULT_SUCCESS == xfer_result) { - print_utf16((uint16_t*)(uintptr_t) desc.buf, sizeof(desc.buf)/2); + if (desc.device.iManufacturer != 0) { + xfer_result = tuh_descriptor_get_manufacturer_string_sync(daddr, LANGUAGE_ID, desc.buf, sizeof(desc.buf)); + if (XFER_RESULT_SUCCESS == xfer_result) { + print_utf16((uint16_t*)(uintptr_t) desc.buf, sizeof(desc.buf)/2); + } } printf("\r\n"); printf(" iProduct %u ", desc.device.iProduct); - xfer_result = tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, desc.buf, sizeof(desc.buf)); - if (XFER_RESULT_SUCCESS == xfer_result) { - print_utf16((uint16_t*)(uintptr_t) desc.buf, sizeof(desc.buf)/2); + if (desc.device.iProduct != 0) { + xfer_result = tuh_descriptor_get_product_string_sync(daddr, LANGUAGE_ID, desc.buf, sizeof(desc.buf)); + if (XFER_RESULT_SUCCESS == xfer_result) { + print_utf16((uint16_t*)(uintptr_t) desc.buf, sizeof(desc.buf)/2); + } } printf("\r\n"); diff --git a/src/host/hcd.h b/src/host/hcd.h index aa9e9cf3b..b20d96d54 100644 --- a/src/host/hcd.h +++ b/src/host/hcd.h @@ -163,6 +163,7 @@ void hcd_device_close(uint8_t rhport, uint8_t dev_addr); //--------------------------------------------------------------------+ // Open an endpoint +// return true if successfully opened or endpoint is currently opened bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * ep_desc); // Close an endpoint diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 3fbf950a4..bb33200f2 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -611,7 +611,7 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t daddr, tusb_desc_endpoint_t const * e ep = &_hcd_data.ep[0]; }else { if (NULL != find_ep_not_addr0(daddr, ep_num, ep_dir)) { - return false; // endpoint already opened + return true; // already opened } ep = allocate_ep(); TU_ASSERT(ep); diff --git a/src/portable/ehci/ehci.c b/src/portable/ehci/ehci.c index 292a352fb..7451f69a3 100644 --- a/src/portable/ehci/ehci.c +++ b/src/portable/ehci/ehci.c @@ -381,7 +381,9 @@ bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const if (ep_desc->bEndpointAddress == 0) { p_qhd = qhd_control(dev_addr); } else { - TU_VERIFY(NULL == qhd_get_from_addr(dev_addr, ep_desc->bEndpointAddress)); // ep not opened yet + if (NULL != qhd_get_from_addr(dev_addr, ep_desc->bEndpointAddress)) { + return true; // already opened + } p_qhd = qhd_find_free(); } TU_ASSERT(p_qhd); -- cgit v1.3.1 From 255ccf26ea29eb16be41f7715426c10be69b6e30 Mon Sep 17 00:00:00 2001 From: Maxime Vincent Date: Fri, 4 Apr 2025 14:21:20 +0200 Subject: dwc2/host: clear SOF flag in handle_sof_irq() --- src/portable/synopsys/dwc2/hcd_dwc2.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/portable') diff --git a/src/portable/synopsys/dwc2/hcd_dwc2.c b/src/portable/synopsys/dwc2/hcd_dwc2.c index f0cea529e..7cbef05b7 100644 --- a/src/portable/synopsys/dwc2/hcd_dwc2.c +++ b/src/portable/synopsys/dwc2/hcd_dwc2.c @@ -1182,6 +1182,7 @@ static void handle_channel_irq(uint8_t rhport, bool in_isr) { static bool handle_sof_irq(uint8_t rhport, bool in_isr) { (void) in_isr; dwc2_regs_t* dwc2 = DWC2_REG(rhport); + dwc2->gintsts = GINTSTS_SOF; // Clear the SOF interrupt flag bool more_isr = false; -- cgit v1.3.1