From a3e50242b9239e1fc0c10d15651222fb3ae3f6d1 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 1 Apr 2020 17:07:28 +0700
Subject: add dcd_esp32s2

skip esp32s2_saola for make build since idf use cmake
---
 src/portable/espressif/esp32s2/dcd_esp32s2.c | 749 +++++++++++++++++++++++++++
 1 file changed, 749 insertions(+)
 create mode 100644 src/portable/espressif/esp32s2/dcd_esp32s2.c

(limited to 'src')

diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c
new file mode 100644
index 000000000..e4e8e30fe
--- /dev/null
+++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c
@@ -0,0 +1,749 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2018 Scott Shawcroft, 2019 William D. Jones for Adafruit Industries
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Additions Copyright (c) 2020, Espressif Systems (Shanghai) Co. Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+// Espressif
+#include "driver/periph_ctrl.h"
+#include "freertos/xtensa_api.h"
+#include "esp_intr_alloc.h"
+#include "esp_log.h"
+#include "esp32s2/rom/gpio.h"
+#include "soc/dport_reg.h"
+#include "soc/gpio_sig_map.h"
+#include "soc/usb_periph.h"
+#include "tusb_config.h"
+// TinyUSB
+#include "tusb_option.h"
+//#include "descriptors_control.h"
+#include "device/dcd.h"
+
+
+#define USB_EP_DIRECTIONS 2
+#define USB_MAX_EP_NUM 16
+
+typedef struct {
+    uint8_t *buffer;
+    uint16_t total_len;
+    uint16_t queued_len;
+    uint16_t max_size;
+    bool short_packet;
+} xfer_ctl_t;
+
+static const char *TAG = "TUSB:DCD";
+static intr_handle_t usb_ih;
+static volatile TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
+static uint8_t s_setup_phase = 0; /*  00 - got setup,
+                                    01 - got done setup,
+                                    02 - setup cmd sent*/
+
+#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
+static xfer_ctl_t xfer_status[USB_MAX_EP_NUM][USB_EP_DIRECTIONS];
+
+static inline void readyfor1setup_pkg(int ep_num)
+{
+    USB0.out_ep_reg[ep_num].doeptsiz |= (1 << USB_SUPCNT0_S); // doeptsiz 29:30 will decremented on every setup received
+}
+
+// Setup the control endpoint 0.
+static void bus_reset(void)
+{
+
+    for (int ep_num = 0; ep_num < USB_OUT_EP_NUM; ep_num++) {
+        USB0.out_ep_reg[ep_num].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK
+    }
+
+    USB0.dcfg &= ~USB_DEVADDR_M; // reset address
+
+    // Peripheral FIFO architecture
+    //
+    // --------------- 320 ( 1280 bytes )
+    // | IN FIFO 3  |
+    // --------------- y + x + 16 + GRXFSIZ
+    // | IN FIFO 2  |
+    // --------------- x + 16 + GRXFSIZ
+    // | IN FIFO 1  |
+    // --------------- 16 + GRXFSIZ
+    // | IN FIFO 0  |
+    // --------------- GRXFSIZ
+    // | OUT FIFO   |
+    // | ( Shared ) |
+    // --------------- 0
+    //
+    // FIFO sizes are set up by the following rules (each word 32-bits):
+    // All EP OUT shared a unique OUT FIFO which uses (based on page 1354 of Rev 17 of reference manual):
+    // * 10 locations in hardware for setup packets + setup control words
+    // (up to 3 setup packets).
+    // * 2 locations for OUT endpoint control words.
+    // * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes)
+    // * 1 location for global NAK (not required/used here).
+    //
+    // It is recommended to allocate 2 times the largest packet size, therefore
+    // Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 50
+    USB0.grstctl |= 0x10 << USB_TXFNUM_S; // fifo 0x10,
+    USB0.grstctl |= USB_TXFFLSH_M;        // Flush fifo
+    USB0.grxfsiz = 50;
+
+    USB0.gintmsk = USB_MODEMISMSK_M |
+                   USB_SOFMSK_M |
+                   USB_RXFLVIMSK_M |
+                   USB_ERLYSUSPMSK_M |
+                   USB_USBSUSPMSK_M |
+                   USB_USBRSTMSK_M |
+                   USB_ENUMDONEMSK_M |
+                   USB_IEPINTMSK_M |
+                   USB_OEPINTMSK_M |
+                   USB_RESETDETMSK_M |
+                   USB_DISCONNINTMSK_M;
+
+    USB0.daintmsk |= USB_OUTEPMSK0_M | USB_INEPMSK0_M;
+    USB0.doepmsk |= USB_SETUPMSK_M | USB_XFERCOMPLMSK;
+    USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M;
+
+    USB0.gnptxfsiz = 16 << USB_NPTXFDEP_S; // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
+
+    readyfor1setup_pkg(0);
+}
+
+static void enum_done_processing(void)
+{
+
+    ESP_EARLY_LOGV(TAG, "dcd_int_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then");
+    // On current silicon on the Full Speed core, speed is fixed to Full Speed.
+    // However, keep for debugging and in case Low Speed is ever supported.
+    uint32_t enum_spd = (USB0.dsts >> USB_ENUMSPD_S) & (USB_ENUMSPD_V);
+
+    // Maximum packet size for EP 0 is set for both directions by writing DIEPCTL
+    if (enum_spd == 0x03) { // Full-Speed (PHY on 48 MHz)
+        USB0.in_ep_reg[0].diepctl &= ~USB_D_MPS0_V;    // 64 bytes
+        USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall
+        xfer_status[0][TUSB_DIR_OUT].max_size = 64;
+        xfer_status[0][TUSB_DIR_IN].max_size = 64;
+    } else {
+        USB0.in_ep_reg[0].diepctl |= USB_D_MPS0_V;     // 8 bytes
+        USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall
+        xfer_status[0][TUSB_DIR_OUT].max_size = 8;
+        xfer_status[0][TUSB_DIR_IN].max_size = 8;
+    }
+
+    USB0.gintmsk |= USB_SOFMSK_M; // SOF unmask
+}
+
+
+
+
+/*------------------------------------------------------------------*/
+/* Controller API
+ *------------------------------------------------------------------*/
+void dcd_init(uint8_t rhport)
+{
+    ESP_LOGV(TAG, "DCD init - Start");
+
+    // A. Disconnect
+    ESP_LOGV(TAG, "DCD init - Soft DISCONNECT and Setting up");
+    USB0.dctl |= USB_SFTDISCON_M; // Soft disconnect
+
+    // B. Programming DCFG
+    /* If USB host misbehaves during status portion of control xfer
+    (non zero-length packet), send STALL back and discard. Full speed. */
+    USB0.dcfg |= USB_NZSTSOUTHSHK_M | // NonZero .... STALL
+                 (3 << 0);            // dev speed: fullspeed 1.1 on 48 mhz  // TODO no value in usb_reg.h (IDF-1476)
+
+    USB0.gahbcfg |= USB_NPTXFEMPLVL_M | USB_GLBLLNTRMSK_M; // Global interruptions ON
+    USB0.gusbcfg |= USB_FORCEDEVMODE_M;                    // force devmode
+
+    USB0.gotgctl &= ~(USB_BVALIDOVVAL_M | USB_BVALIDOVEN_M | USB_VBVALIDOVVAL_M); //no overrides
+#ifdef CONFIG_IDF_TARGET_ESP32S2BETA // needed for beta chip only
+    //C. chip 7.2.2 hack
+    ESP_LOGV(TAG, "DCD init - chip ESP32-S2 beta hack");
+    USB0.gotgctl = (0 << USB_BVALIDOVVAL_S); //B override value
+    ets_delay_us(20);
+    USB0.gotgctl = (0 << USB_BVALIDOVVAL_S) | (1 << USB_BVALIDOVEN_S); //B override value & enable
+    ets_delay_us(20);
+#endif
+
+    // C. Setting SNAKs, then connect
+    for (int n = 0; n < USB_OUT_EP_NUM; n++) {
+        USB0.out_ep_reg[n].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK
+    }
+    ESP_LOGV(TAG, "DCD init - Soft CONNECT");
+    USB0.dctl &= ~USB_SFTDISCON_M; // Connect
+
+    // D. Interruption masking
+    USB0.gintmsk = 0;   //mask all
+    USB0.gotgint = ~0U; //clear OTG ints
+    USB0.gintsts = ~0U; //clear pending ints
+    USB0.gintmsk = USB_MODEMISMSK_M |
+                   USB_SOFMSK_M |
+                   USB_RXFLVIMSK_M |
+                   USB_ERLYSUSPMSK_M |
+                   USB_USBSUSPMSK_M |
+                   USB_USBRSTMSK_M |
+                   USB_ENUMDONEMSK_M |
+                   USB_RESETDETMSK_M |
+                   USB_DISCONNINTMSK_M;
+    ets_delay_us(100);
+}
+
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
+{
+    (void)rhport;
+    ESP_LOGV(TAG, "DCD init - Set address : %u", dev_addr);
+    USB0.dcfg |= ((dev_addr & USB_DEVADDR_V) << USB_DEVADDR_S);
+    // Response with status after changing device address
+    dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+}
+
+void dcd_set_config(uint8_t rhport, uint8_t config_num)
+{
+    (void)rhport;
+    (void)config_num;
+    // Nothing to do
+}
+
+void dcd_remote_wakeup(uint8_t rhport)
+{
+    (void)rhport;
+}
+
+/*------------------------------------------------------------------*/
+/* DCD Endpoint port
+ *------------------------------------------------------------------*/
+
+bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
+{
+
+    ESP_LOGV(TAG, "DCD endpoint opened");
+    (void)rhport;
+
+    usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]);
+    usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]);
+
+    uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
+    uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
+
+    // Unsupported endpoint numbers/size.
+    if ((desc_edpt->wMaxPacketSize.size > 64) || (epnum > 3)) {
+        return false;
+    }
+
+    xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
+    xfer->max_size = desc_edpt->wMaxPacketSize.size;
+
+    if (dir == TUSB_DIR_OUT) {
+        out_ep[epnum].doepctl |= USB_USBACTEP0_M |
+                                 desc_edpt->bmAttributes.xfer << USB_EPTYPE0_S |
+                                 desc_edpt->wMaxPacketSize.size << USB_MPS0_S;
+        USB0.daintmsk |= (1 << (16 + epnum));
+    } else {
+        // Peripheral FIFO architecture (Rev18 RM 29.11)
+        //
+        // --------------- 320 ( 1280 bytes )
+        // | IN FIFO 3  |
+        // --------------- y + x + 16 + GRXFSIZ
+        // | IN FIFO 2  |
+        // --------------- x + 16 + GRXFSIZ
+        // | IN FIFO 1  |
+        // --------------- 16 + GRXFSIZ
+        // | IN FIFO 0  |
+        // --------------- GRXFSIZ
+        // | OUT FIFO   |
+        // | ( Shared ) |
+        // --------------- 0
+        //
+        // Since OUT FIFO = 50, FIFO 0 = 16, average of FIFOx = (312-50-16) / 3 = 82 ~ 80
+        in_ep[epnum].diepctl |= USB_D_USBACTEP1_M |
+                                (epnum - 1) << USB_D_TXFNUM1_S |
+                                desc_edpt->bmAttributes.xfer << USB_D_EPTYPE1_S |
+                                (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? (1 << USB_DI_SETD0PID1_S) : 0) |
+                                desc_edpt->wMaxPacketSize.size << 0;
+        USB0.daintmsk |= (1 << (0 + epnum));
+
+        // Both TXFD and TXSA are in unit of 32-bit words
+        uint16_t const fifo_size = 80;
+        uint32_t const fifo_offset = (USB0.grxfsiz & USB_NPTXFDEP_V) + 16 + fifo_size * (epnum - 1);
+        USB0.dieptxf[epnum - 1] = (80 << USB_NPTXFDEP_S) | fifo_offset;
+    }
+    return true;
+}
+
+bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
+{
+
+    (void)rhport;
+
+    uint8_t const epnum = tu_edpt_number(ep_addr);
+    uint8_t const dir = tu_edpt_dir(ep_addr);
+
+    xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
+    xfer->buffer = buffer;
+    xfer->total_len = total_bytes;
+    xfer->queued_len = 0;
+    xfer->short_packet = false;
+
+    uint16_t num_packets = (total_bytes / xfer->max_size);
+    uint8_t short_packet_size = total_bytes % xfer->max_size;
+
+    // Zero-size packet is special case.
+    if (short_packet_size > 0 || (total_bytes == 0)) {
+        num_packets++;
+    }
+
+    ESP_LOGV(TAG, "Transfer <-> EP%i, %s, pkgs: %i, bytes: %i",
+             epnum, ((dir == TUSB_DIR_IN) ? "USB0.HOST (in)" : "HOST->DEV (out)"),
+             num_packets, total_bytes);
+
+    // IN and OUT endpoint xfers are interrupt-driven, we just schedule them
+    // here.
+    if (dir == TUSB_DIR_IN) {
+        // A full IN transfer (multiple packets, possibly) triggers XFRC.
+        int bytes2fifo_left = total_bytes;
+        uint32_t val; // 32 bit val from 4 buff addresses
+
+        USB0.in_ep_reg[epnum].diepint = ~0U; // clear all ints
+        USB0.in_ep_reg[epnum].dieptsiz = (num_packets << USB_D_PKTCNT0_S) | total_bytes;
+        USB0.in_ep_reg[epnum].diepctl |= USB_D_EPENA1_M | USB_D_CNAK1_M; // Enable | CNAK
+        while (bytes2fifo_left > 0) {  // TODO move it to ep_in_handle (IDF-1475)
+            /* ATTENTION! In cases when CFG_TUD_ENDOINT0_SIZE, CFG_TUD_CDC_EPSIZE, CFG_TUD_MIDI_EPSIZE or
+            CFG_TUD_MSC_BUFSIZE < 4 next line can be a cause of an error.*/
+            val = (*(buffer + 3) << 24) |
+                  (*(buffer + 2) << 16) |
+                  (*(buffer + 1) << 8) |
+                  (*(buffer + 0) << 0);
+            ESP_LOGV(TAG, "Transfer 0x%08x -> FIFO%d", val, epnum);
+            USB0.fifo[epnum][0] = val; //copy and next buffer address
+            buffer += 4;
+            bytes2fifo_left -= 4;
+        }
+        // USB0.dtknqr4_fifoemptymsk |= (1 << epnum);
+    } else {
+        // Each complete packet for OUT xfers triggers XFRC.
+        USB0.out_ep_reg[epnum].doeptsiz = USB_PKTCNT0_M |
+                                          ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S);
+        USB0.out_ep_reg[epnum].doepctl |= USB_EPENA0_M | USB_CNAK0_M;
+    }
+    return true;
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+    (void)rhport;
+
+    usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]);
+    usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]);
+
+    uint8_t const epnum = tu_edpt_number(ep_addr);
+    uint8_t const dir = tu_edpt_dir(ep_addr);
+
+    if (dir == TUSB_DIR_IN) {
+        // Only disable currently enabled non-control endpoint
+        if ((epnum == 0) || !(in_ep[epnum].diepctl & USB_D_EPENA1_M)) {
+            in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M);
+        } else {
+            // Stop transmitting packets and NAK IN xfers.
+            in_ep[epnum].diepctl |= USB_DI_SNAK1_M;
+            while ((in_ep[epnum].diepint & USB_DI_SNAK1_M) == 0)
+                ;
+
+            // Disable the endpoint. Note that both SNAK and STALL are set here.
+            in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M |
+                                     USB_D_EPDIS1_M);
+            while ((in_ep[epnum].diepint & USB_D_EPDISBLD0_M) == 0)
+                ;
+            in_ep[epnum].diepint = USB_D_EPDISBLD0_M;
+        }
+
+        // Flush the FIFO, and wait until we have confirmed it cleared.
+        USB0.grstctl |= ((epnum - 1) << USB_TXFNUM_S);
+        USB0.grstctl |= USB_TXFFLSH_M;
+        while ((USB0.grstctl & USB_TXFFLSH_M) != 0)
+            ;
+    } else {
+        // Only disable currently enabled non-control endpoint
+        if ((epnum == 0) || !(out_ep[epnum].doepctl & USB_EPENA0_M)) {
+            out_ep[epnum].doepctl |= USB_STALL0_M;
+        } else {
+            // Asserting GONAK is required to STALL an OUT endpoint.
+            // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
+            // anyway, and it can't be cleared by user code. If this while loop never
+            // finishes, we have bigger problems than just the stack.
+            USB0.dctl |= USB_SGOUTNAK_M;
+            while ((USB0.gintsts & USB_GOUTNAKEFF_M) == 0)
+                ;
+
+            // Ditto here- disable the endpoint. Note that only STALL and not SNAK
+            // is set here.
+            out_ep[epnum].doepctl |= (USB_STALL0_M | USB_EPDIS0_M);
+            while ((out_ep[epnum].doepint & USB_EPDISBLD0_M) == 0)
+                ;
+            out_ep[epnum].doepint = USB_EPDISBLD0_M;
+
+            // Allow other OUT endpoints to keep receiving.
+            USB0.dctl |= USB_CGOUTNAK_M;
+        }
+    }
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+    (void)rhport;
+
+    usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]);
+    usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]);
+
+    uint8_t const epnum = tu_edpt_number(ep_addr);
+    uint8_t const dir = tu_edpt_dir(ep_addr);
+
+    if (dir == TUSB_DIR_IN) {
+        in_ep[epnum].diepctl &= ~USB_D_STALL1_M;
+
+        uint8_t eptype = (in_ep[epnum].diepctl & USB_D_EPTYPE1_M) >> USB_D_EPTYPE1_S;
+        // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt
+        // and bulk endpoints.
+        if (eptype == 2 || eptype == 3) {
+            in_ep[epnum].diepctl |= USB_DI_SETD0PID1_M;
+        }
+    } else {
+        out_ep[epnum].doepctl &= ~USB_STALL1_M;
+
+        uint8_t eptype = (out_ep[epnum].doepctl & USB_EPTYPE1_M) >> USB_EPTYPE1_S;
+        // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt
+        // and bulk endpoints.
+        if (eptype == 2 || eptype == 3) {
+            out_ep[epnum].doepctl |= USB_DO_SETD0PID1_M;
+        }
+    }
+}
+
+/*------------------------------------------------------------------*/
+
+static void receive_packet(xfer_ctl_t *xfer, /* usb_out_endpoint_t * out_ep, */ uint16_t xfer_size)
+{
+    ESP_EARLY_LOGV(TAG, "USB - receive_packet");
+    uint32_t *rx_fifo = USB0.fifo[0];
+
+    // See above TODO
+    // uint16_t remaining = (out_ep->DOEPTSIZ & UsbDOEPTSIZ_XFRSIZ_Msk) >> UsbDOEPTSIZ_XFRSIZ_Pos;
+    // xfer->queued_len = xfer->total_len - remaining;
+
+    uint16_t remaining = xfer->total_len - xfer->queued_len;
+    uint16_t to_recv_size;
+
+    if (remaining <= xfer->max_size) {
+        // Avoid buffer overflow.
+        to_recv_size = (xfer_size > remaining) ? remaining : xfer_size;
+    } else {
+        // Room for full packet, choose recv_size based on what the microcontroller
+        // claims.
+        to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size;
+    }
+
+    uint8_t to_recv_rem = to_recv_size % 4;
+    uint16_t to_recv_size_aligned = to_recv_size - to_recv_rem;
+
+    // Do not assume xfer buffer is aligned.
+    uint8_t *base = (xfer->buffer + xfer->queued_len);
+
+    // This for loop always runs at least once- skip if less than 4 bytes
+    // to collect.
+    if (to_recv_size >= 4) {
+        for (uint16_t i = 0; i < to_recv_size_aligned; i += 4) {
+            uint32_t tmp = (*rx_fifo);
+            base[i] = tmp & 0x000000FF;
+            base[i + 1] = (tmp & 0x0000FF00) >> 8;
+            base[i + 2] = (tmp & 0x00FF0000) >> 16;
+            base[i + 3] = (tmp & 0xFF000000) >> 24;
+        }
+    }
+
+    // Do not read invalid bytes from RX FIFO.
+    if (to_recv_rem != 0) {
+        uint32_t tmp = (*rx_fifo);
+        uint8_t *last_32b_bound = base + to_recv_size_aligned;
+
+        last_32b_bound[0] = tmp & 0x000000FF;
+        if (to_recv_rem > 1) {
+            last_32b_bound[1] = (tmp & 0x0000FF00) >> 8;
+        }
+        if (to_recv_rem > 2) {
+            last_32b_bound[2] = (tmp & 0x00FF0000) >> 16;
+        }
+    }
+
+    xfer->queued_len += xfer_size;
+
+    // Per USB spec, a short OUT packet (including length 0) is always
+    // indicative of the end of a transfer (at least for ctl, bulk, int).
+    xfer->short_packet = (xfer_size < xfer->max_size);
+}
+
+static void transmit_packet(xfer_ctl_t *xfer, volatile usb_in_endpoint_t *in_ep, uint8_t fifo_num)
+{
+
+    ESP_EARLY_LOGV(TAG, "USB - transmit_packet");
+    uint32_t *tx_fifo = USB0.fifo[0];
+
+    uint16_t remaining = (in_ep->dieptsiz & 0x7FFFFU) >> USB_D_XFERSIZE0_S;
+    xfer->queued_len = xfer->total_len - remaining;
+
+    uint16_t to_xfer_size = (remaining > xfer->max_size) ? xfer->max_size : remaining;
+    uint8_t to_xfer_rem = to_xfer_size % 4;
+    uint16_t to_xfer_size_aligned = to_xfer_size - to_xfer_rem;
+
+    // Buffer might not be aligned to 32b, so we need to force alignment
+    // by copying to a temp var.
+    uint8_t *base = (xfer->buffer + xfer->queued_len);
+
+    // This for loop always runs at least once- skip if less than 4 bytes
+    // to send off.
+    if (to_xfer_size >= 4) {
+        for (uint16_t i = 0; i < to_xfer_size_aligned; i += 4) {
+            uint32_t tmp = base[i] | (base[i + 1] << 8) |
+                           (base[i + 2] << 16) | (base[i + 3] << 24);
+            (*tx_fifo) = tmp;
+        }
+    }
+
+    // Do not read beyond end of buffer if not divisible by 4.
+    if (to_xfer_rem != 0) {
+        uint32_t tmp = 0;
+        uint8_t *last_32b_bound = base + to_xfer_size_aligned;
+
+        tmp |= last_32b_bound[0];
+        if (to_xfer_rem > 1) {
+            tmp |= (last_32b_bound[1] << 8);
+        }
+        if (to_xfer_rem > 2) {
+            tmp |= (last_32b_bound[2] << 16);
+        }
+
+        (*tx_fifo) = tmp;
+    }
+}
+
+static void read_rx_fifo(void)
+{
+    // Pop control word off FIFO (completed xfers will have 2 control words,
+    // we only pop one ctl word each interrupt).
+    volatile uint32_t ctl_word = USB0.grxstsp;
+    uint8_t pktsts = (ctl_word & USB_PKTSTS_M) >> USB_PKTSTS_S;
+    uint8_t epnum = (ctl_word & USB_CHNUM_M) >> USB_CHNUM_S;
+    uint16_t bcnt = (ctl_word & USB_BCNT_M) >> USB_BCNT_S;
+    switch (pktsts) {
+    case 0x01: // Global OUT NAK (Interrupt)
+        ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Global OUT NAK");
+        break;
+    case 0x02: { // Out packet recvd
+        ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet");
+        xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
+        receive_packet(xfer, bcnt);
+    }
+    break;
+    case 0x03: // Out packet done (Interrupt)
+        ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet done");
+        break;
+    case 0x04:                // Setup packet done (Interrupt)
+        if (s_setup_phase == 0) { // only if setup is started
+            s_setup_phase = 1;
+            ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 1"); //finished
+            ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet done");
+        }
+
+        break;
+    case 0x06: { // Setup packet recvd
+        s_setup_phase = 0;
+        ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 0"); // new setup process
+        // For some reason, it's possible to get a mismatch between
+        // how many setup packets were received versus the location
+        // of the Setup packet done word. This leads to situations
+        // where stale setup packets are in the RX FIFO that were received
+        // after the core loaded the Setup packet done word. Workaround by
+        // only accepting one setup packet at a time for now.
+        _setup_packet[0] = (USB0.grxstsp);
+        _setup_packet[1] = (USB0.grxstsp);
+        ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet : 0x%08x 0x%08x",
+                       _setup_packet[0], _setup_packet[1]);
+    }
+    break;
+    default: // Invalid, do something here, like breakpoint?
+        break;
+    }
+}
+
+static void handle_epout_ints(void)
+{
+    // GINTSTS will be cleared with DAINT == 0
+    // DAINT for a given EP clears when DOEPINTx is cleared.
+    // DOEPINT will be cleared when DAINT's out bits are cleared.
+    for (int n = 0; n < USB_OUT_EP_NUM; n++) {
+        xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
+        if (USB0.daint & (1 << (16 + n))) {
+            // SETUP packet Setup Phase done.
+            if ((USB0.out_ep_reg[n].doepint & USB_SETUP0_M)) {
+                USB0.out_ep_reg[n].doepint |= USB_STUPPKTRCVD0_M | USB_SETUP0_M; // clear
+                if (s_setup_phase == 1) {                                          // only if setup is done, but not handled
+                    s_setup_phase = 2;
+                    ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 2"); // sending to  a handling queue
+                    ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP OUT - Setup Phase done (irq-s 0x%08x)", USB0.out_ep_reg[n].doepint);
+                    dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true);
+                }
+                readyfor1setup_pkg(0);
+            }
+
+            // OUT XFER complete (single packet).q
+            if (USB0.out_ep_reg[n].doepint & USB_XFERCOMPL0_M) {
+
+                ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP OUT - XFER complete (single packet)");
+                USB0.out_ep_reg[n].doepint = USB_XFERCOMPL0_M;
+
+                // Transfer complete if short packet or total len is transferred
+                if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
+                    xfer->short_packet = false;
+                    dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+                } else {
+                    // Schedule another packet to be received.
+                    USB0.out_ep_reg[n].doeptsiz = USB_PKTCNT0_M |
+                                                  ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S);
+                    USB0.out_ep_reg[n].doepctl |= USB_EPENA0_M | USB_CNAK0_M;
+                }
+            }
+        }
+    }
+}
+
+static void handle_epin_ints(void)
+{
+
+    // GINTSTS will be cleared with DAINT == 0
+    // DAINT for a given EP clears when DIEPINTx is cleared.
+    // IEPINT will be cleared when DAINT's out bits are cleared.
+    for (uint32_t n = 0; n < USB_IN_EP_NUM; n++) {
+        xfer_ctl_t *xfer = &xfer_status[n][TUSB_DIR_IN];
+
+        if (USB0.daint & (1 << (0 + n))) {
+            ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP IN %u", n);
+            // IN XFER complete (entire xfer).
+            if (USB0.in_ep_reg[n].diepint & USB_D_XFERCOMPL0_M) {
+                ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER complete!");
+                USB0.in_ep_reg[n].diepint = USB_D_XFERCOMPL0_M;
+                // USB0.dtknqr4_fifoemptymsk &= ~(1 << n); // Turn off TXFE b/c xfer inactive.
+                dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
+            }
+
+            // XFER FIFO empty
+            if (USB0.in_ep_reg[n].diepint & USB_D_XFERCOMPL0_M) {
+                ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER FIFO empty!");
+                USB0.in_ep_reg[n].diepint = USB_D_TXFEMP0_M;
+                transmit_packet(xfer, &USB0.in_ep_reg[n], n);
+            }
+        }
+    }
+}
+
+
+static void dcd_int_handler(void)
+{
+    uint32_t int_status = USB0.gintsts;
+    uint32_t int_msk = USB0.gintmsk;
+
+    if (int_status & USB_DISCONNINT_M) {
+        ESP_EARLY_LOGV(TAG, "dcd_int_handler - disconnected");
+        USB0.gintsts = USB_DISCONNINT_M;
+    }
+
+    if (int_status & USB_USBRST_M) {
+
+        ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset");
+        USB0.gintsts = USB_USBRST_M;
+        bus_reset();
+    }
+
+    if (int_status & USB_RESETDET_M) {
+        ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset while suspend");
+        USB0.gintsts = USB_RESETDET_M;
+        bus_reset();
+    }
+
+    if (int_status & USB_ENUMDONE_M) {
+        // ENUMDNE detects speed of the link. For full-speed, we
+        // always expect the same value. This interrupt is considered
+        // the end of reset.
+        USB0.gintsts = USB_ENUMDONE_M;
+        enum_done_processing();
+        dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
+    }
+
+    if (int_status & USB_SOF_M) {
+        USB0.gintsts = USB_SOF_M;
+        dcd_event_bus_signal(0, DCD_EVENT_SOF, true); // do nothing actually
+    }
+
+    if ((int_status & USB_RXFLVI_M) & (int_msk & USB_RXFLVIMSK_M)) {
+        ESP_EARLY_LOGV(TAG, "dcd_int_handler - rx!");
+        read_rx_fifo();
+    }
+
+    // OUT endpoint interrupt handling.
+    if (int_status & USB_OEPINT_M) {
+        ESP_EARLY_LOGV(TAG, "dcd_int_handler - OUT endpoint!");
+        handle_epout_ints();
+    }
+
+    // IN endpoint interrupt handling.
+    if (int_status & USB_IEPINT_M) {
+        ESP_EARLY_LOGV(TAG, "dcd_int_handler - IN endpoint!");
+        handle_epin_ints();
+    }
+
+    // Without handling
+    USB0.gintsts |= USB_CURMOD_INT_M |
+                    USB_MODEMIS_M |
+                    USB_OTGINT_M |
+                    USB_NPTXFEMP_M |
+                    USB_GINNAKEFF_M |
+                    USB_GOUTNAKEFF |
+                    USB_ERLYSUSP_M |
+                    USB_USBSUSP_M |
+                    USB_ISOOUTDROP_M |
+                    USB_EOPF_M |
+                    USB_EPMIS_M |
+                    USB_INCOMPISOIN_M |
+                    USB_INCOMPIP_M |
+                    USB_FETSUSP_M |
+                    USB_PTXFEMP_M;
+}
+
+void dcd_int_enable(uint8_t rhport)
+{
+    (void)rhport;
+    esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)dcd_int_handler, NULL, &usb_ih);
+}
+
+void dcd_int_disable(uint8_t rhport)
+{
+    (void)rhport;
+    esp_intr_free(usb_ih);
+}
-- 
cgit v1.3.1


From 1e7c3cf95eb4c1e078a9083277b2abbbda5e19bf Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 3 Apr 2020 17:09:38 +0700
Subject: update dcd esp32s2 fifo allocation to match current dcd synopsys

---
 src/portable/espressif/esp32s2/dcd_esp32s2.c | 116 ++++++++++++++++-----------
 1 file changed, 69 insertions(+), 47 deletions(-)

(limited to 'src')

diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c
index e4e8e30fe..b2593383c 100644
--- a/src/portable/espressif/esp32s2/dcd_esp32s2.c
+++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c
@@ -26,6 +26,10 @@
  * This file is part of the TinyUSB stack.
  */
 
+#include "tusb_option.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 && TUSB_OPT_DEVICE_ENABLED
+
 // Espressif
 #include "driver/periph_ctrl.h"
 #include "freertos/xtensa_api.h"
@@ -35,15 +39,12 @@
 #include "soc/dport_reg.h"
 #include "soc/gpio_sig_map.h"
 #include "soc/usb_periph.h"
-#include "tusb_config.h"
-// TinyUSB
-#include "tusb_option.h"
-//#include "descriptors_control.h"
-#include "device/dcd.h"
 
+#include "device/dcd.h"
 
-#define USB_EP_DIRECTIONS 2
-#define USB_MAX_EP_NUM 16
+// FIFO size in bytes TODO need confirmation from Espressif
+#define EP_MAX            USB_OUT_EP_NUM
+#define EP_FIFO_SIZE      1280
 
 typedef struct {
     uint8_t *buffer;
@@ -61,7 +62,7 @@ static uint8_t s_setup_phase = 0; /*  00 - got setup,
                                     02 - setup cmd sent*/
 
 #define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
-static xfer_ctl_t xfer_status[USB_MAX_EP_NUM][USB_EP_DIRECTIONS];
+static xfer_ctl_t xfer_status[EP_MAX][2];
 
 static inline void readyfor1setup_pkg(int ep_num)
 {
@@ -78,34 +79,37 @@ static void bus_reset(void)
 
     USB0.dcfg &= ~USB_DEVADDR_M; // reset address
 
+    // "USB Data FIFOs" section in reference manual
     // Peripheral FIFO architecture
     //
-    // --------------- 320 ( 1280 bytes )
-    // | IN FIFO 3  |
+    // --------------- 320 or 1024 ( 1280 or 4096 bytes )
+    // | IN FIFO MAX |
+    // ---------------
+    // |    ...      |
     // --------------- y + x + 16 + GRXFSIZ
-    // | IN FIFO 2  |
+    // | IN FIFO 2   |
     // --------------- x + 16 + GRXFSIZ
-    // | IN FIFO 1  |
+    // | IN FIFO 1   |
     // --------------- 16 + GRXFSIZ
-    // | IN FIFO 0  |
+    // | IN FIFO 0   |
     // --------------- GRXFSIZ
-    // | OUT FIFO   |
-    // | ( Shared ) |
+    // | OUT FIFO    |
+    // | ( Shared )  |
     // --------------- 0
     //
-    // FIFO sizes are set up by the following rules (each word 32-bits):
-    // All EP OUT shared a unique OUT FIFO which uses (based on page 1354 of Rev 17 of reference manual):
-    // * 10 locations in hardware for setup packets + setup control words
-    // (up to 3 setup packets).
-    // * 2 locations for OUT endpoint control words.
-    // * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes)
-    // * 1 location for global NAK (not required/used here).
+    // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits):
+    // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN
     //
-    // It is recommended to allocate 2 times the largest packet size, therefore
-    // Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 50
+    // - All EP OUT shared a unique OUT FIFO which uses
+    //   * 10 locations in hardware for setup packets + setup control words (up to 3 setup packets).
+    //   * 2 locations for OUT endpoint control words.
+    //   * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes)
+    //   * 1 location for global NAK (not required/used here).
+    //   * It is recommended to allocate 2 times the largest packet size, therefore
+    //   Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 52
     USB0.grstctl |= 0x10 << USB_TXFNUM_S; // fifo 0x10,
     USB0.grstctl |= USB_TXFFLSH_M;        // Flush fifo
-    USB0.grxfsiz = 50;
+    USB0.grxfsiz = 52;
 
     USB0.gintmsk = USB_MODEMISMSK_M |
                    USB_SOFMSK_M |
@@ -123,7 +127,8 @@ static void bus_reset(void)
     USB0.doepmsk |= USB_SETUPMSK_M | USB_XFERCOMPLMSK;
     USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M;
 
-    USB0.gnptxfsiz = 16 << USB_NPTXFDEP_S; // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
+    // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
+    USB0.gnptxfsiz = (16 << USB_NPTXFDEP_S) | (USB0.grxfsiz & 0x0000ffffUL);
 
     readyfor1setup_pkg(0);
 }
@@ -245,10 +250,8 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
     uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
     uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
 
-    // Unsupported endpoint numbers/size.
-    if ((desc_edpt->wMaxPacketSize.size > 64) || (epnum > 3)) {
-        return false;
-    }
+    TU_ASSERT(desc_edpt->wMaxPacketSize.size <= 64);
+    TU_ASSERT(epnum < EP_MAX);
 
     xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
     xfer->max_size = desc_edpt->wMaxPacketSize.size;
@@ -259,33 +262,44 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
                                  desc_edpt->wMaxPacketSize.size << USB_MPS0_S;
         USB0.daintmsk |= (1 << (16 + epnum));
     } else {
-        // Peripheral FIFO architecture (Rev18 RM 29.11)
+        // "USB Data FIFOs" section in reference manual
+        // Peripheral FIFO architecture
         //
-        // --------------- 320 ( 1280 bytes )
-        // | IN FIFO 3  |
+        // --------------- 320 or 1024 ( 1280 or 4096 bytes )
+        // | IN FIFO MAX |
+        // ---------------
+        // |    ...      |
         // --------------- y + x + 16 + GRXFSIZ
-        // | IN FIFO 2  |
+        // | IN FIFO 2   |
         // --------------- x + 16 + GRXFSIZ
-        // | IN FIFO 1  |
+        // | IN FIFO 1   |
         // --------------- 16 + GRXFSIZ
-        // | IN FIFO 0  |
+        // | IN FIFO 0   |
         // --------------- GRXFSIZ
-        // | OUT FIFO   |
-        // | ( Shared ) |
+        // | OUT FIFO    |
+        // | ( Shared )  |
         // --------------- 0
         //
-        // Since OUT FIFO = 50, FIFO 0 = 16, average of FIFOx = (312-50-16) / 3 = 82 ~ 80
+        // Since OUT FIFO = GRXFSIZ, FIFO 0 = 16, for simplicity, we equally allocated for the rest of endpoints
+        // - Size  : (FIFO_SIZE/4 - GRXFSIZ - 16) / (EP_MAX-1)
+        // - Offset: GRXFSIZ + 16 + Size*(epnum-1)
+        // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
+
         in_ep[epnum].diepctl |= USB_D_USBACTEP1_M |
-                                (epnum - 1) << USB_D_TXFNUM1_S |
+                                epnum << USB_D_TXFNUM1_S |
                                 desc_edpt->bmAttributes.xfer << USB_D_EPTYPE1_S |
                                 (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? (1 << USB_DI_SETD0PID1_S) : 0) |
                                 desc_edpt->wMaxPacketSize.size << 0;
         USB0.daintmsk |= (1 << (0 + epnum));
 
-        // Both TXFD and TXSA are in unit of 32-bit words
-        uint16_t const fifo_size = 80;
-        uint32_t const fifo_offset = (USB0.grxfsiz & USB_NPTXFDEP_V) + 16 + fifo_size * (epnum - 1);
-        USB0.dieptxf[epnum - 1] = (80 << USB_NPTXFDEP_S) | fifo_offset;
+        // Both TXFD and TXSA are in unit of 32-bit words.
+        // IN FIFO 0 was configured during enumeration, hence the "+ 16".
+        uint16_t const allocated_size = (USB0.grxfsiz & 0x0000ffff) + 16;
+        uint16_t const fifo_size = (EP_FIFO_SIZE/4 - allocated_size) / (EP_MAX-1);
+        uint32_t const fifo_offset = allocated_size + fifo_size*(epnum-1);
+
+        // DIEPTXF starts at FIFO #1.
+        USB0.dieptxf[epnum - 1] = (fifo_size << USB_NPTXFDEP_S) | fifo_offset;
     }
     return true;
 }
@@ -320,12 +334,14 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
     // here.
     if (dir == TUSB_DIR_IN) {
         // A full IN transfer (multiple packets, possibly) triggers XFRC.
-        int bytes2fifo_left = total_bytes;
-        uint32_t val; // 32 bit val from 4 buff addresses
-
         USB0.in_ep_reg[epnum].diepint = ~0U; // clear all ints
         USB0.in_ep_reg[epnum].dieptsiz = (num_packets << USB_D_PKTCNT0_S) | total_bytes;
         USB0.in_ep_reg[epnum].diepctl |= USB_D_EPENA1_M | USB_D_CNAK1_M; // Enable | CNAK
+
+#if 1
+        //int bytes2fifo_left = tu_min16(total_bytes, xfer->max_size);
+        int bytes2fifo_left = total_bytes;
+        uint32_t val; // 32 bit val from 4 buff addresses
         while (bytes2fifo_left > 0) {  // TODO move it to ep_in_handle (IDF-1475)
             /* ATTENTION! In cases when CFG_TUD_ENDOINT0_SIZE, CFG_TUD_CDC_EPSIZE, CFG_TUD_MIDI_EPSIZE or
             CFG_TUD_MSC_BUFSIZE < 4 next line can be a cause of an error.*/
@@ -338,7 +354,10 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
             buffer += 4;
             bytes2fifo_left -= 4;
         }
+#else
+//        transmit_packet(xfer, &USB0.in_ep_reg[epnum], epnum);
         // USB0.dtknqr4_fifoemptymsk |= (1 << epnum);
+#endif
     } else {
         // Each complete packet for OUT xfers triggers XFRC.
         USB0.out_ep_reg[epnum].doeptsiz = USB_PKTCNT0_M |
@@ -747,3 +766,6 @@ void dcd_int_disable(uint8_t rhport)
     (void)rhport;
     esp_intr_free(usb_ih);
 }
+
+#endif // OPT_MCU_ESP32S2
+
-- 
cgit v1.3.1


From 050de0ec33752d0a24b53c9e18d82161185d0176 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 Apr 2020 16:32:55 +0700
Subject: fix issue and typo with In token when Fifo empty

fix transmit packet endpoint's fifo
---
 src/portable/espressif/esp32s2/dcd_esp32s2.c | 45 ++++++++--------------------
 1 file changed, 12 insertions(+), 33 deletions(-)

(limited to 'src')

diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c
index b2593383c..3361bde36 100644
--- a/src/portable/espressif/esp32s2/dcd_esp32s2.c
+++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c
@@ -57,9 +57,9 @@ typedef struct {
 static const char *TAG = "TUSB:DCD";
 static intr_handle_t usb_ih;
 static volatile TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
-static uint8_t s_setup_phase = 0; /*  00 - got setup,
-                                    01 - got done setup,
-                                    02 - setup cmd sent*/
+static volatile uint8_t s_setup_phase = 0; /*  00 - got setup,
+                                               01 - got done setup,
+                                               02 - setup cmd sent*/
 
 #define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
 static xfer_ctl_t xfer_status[EP_MAX][2];
@@ -125,7 +125,7 @@ static void bus_reset(void)
 
     USB0.daintmsk |= USB_OUTEPMSK0_M | USB_INEPMSK0_M;
     USB0.doepmsk |= USB_SETUPMSK_M | USB_XFERCOMPLMSK;
-    USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M;
+    USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M /*| USB_INTKNTXFEMPMSK_M*/;
 
     // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
     USB0.gnptxfsiz = (16 << USB_NPTXFDEP_S) | (USB0.grxfsiz & 0x0000ffffUL);
@@ -334,30 +334,9 @@ bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t to
     // here.
     if (dir == TUSB_DIR_IN) {
         // A full IN transfer (multiple packets, possibly) triggers XFRC.
-        USB0.in_ep_reg[epnum].diepint = ~0U; // clear all ints
         USB0.in_ep_reg[epnum].dieptsiz = (num_packets << USB_D_PKTCNT0_S) | total_bytes;
         USB0.in_ep_reg[epnum].diepctl |= USB_D_EPENA1_M | USB_D_CNAK1_M; // Enable | CNAK
-
-#if 1
-        //int bytes2fifo_left = tu_min16(total_bytes, xfer->max_size);
-        int bytes2fifo_left = total_bytes;
-        uint32_t val; // 32 bit val from 4 buff addresses
-        while (bytes2fifo_left > 0) {  // TODO move it to ep_in_handle (IDF-1475)
-            /* ATTENTION! In cases when CFG_TUD_ENDOINT0_SIZE, CFG_TUD_CDC_EPSIZE, CFG_TUD_MIDI_EPSIZE or
-            CFG_TUD_MSC_BUFSIZE < 4 next line can be a cause of an error.*/
-            val = (*(buffer + 3) << 24) |
-                  (*(buffer + 2) << 16) |
-                  (*(buffer + 1) << 8) |
-                  (*(buffer + 0) << 0);
-            ESP_LOGV(TAG, "Transfer 0x%08x -> FIFO%d", val, epnum);
-            USB0.fifo[epnum][0] = val; //copy and next buffer address
-            buffer += 4;
-            bytes2fifo_left -= 4;
-        }
-#else
-//        transmit_packet(xfer, &USB0.in_ep_reg[epnum], epnum);
-        // USB0.dtknqr4_fifoemptymsk |= (1 << epnum);
-#endif
+        USB0.dtknqr4_fifoemptymsk |= (1 << epnum);
     } else {
         // Each complete packet for OUT xfers triggers XFRC.
         USB0.out_ep_reg[epnum].doeptsiz = USB_PKTCNT0_M |
@@ -521,9 +500,8 @@ static void receive_packet(xfer_ctl_t *xfer, /* usb_out_endpoint_t * out_ep, */
 
 static void transmit_packet(xfer_ctl_t *xfer, volatile usb_in_endpoint_t *in_ep, uint8_t fifo_num)
 {
-
     ESP_EARLY_LOGV(TAG, "USB - transmit_packet");
-    uint32_t *tx_fifo = USB0.fifo[0];
+    volatile uint32_t *tx_fifo = USB0.fifo[fifo_num];
 
     uint16_t remaining = (in_ep->dieptsiz & 0x7FFFFU) >> USB_D_XFERSIZE0_S;
     xfer->queued_len = xfer->total_len - remaining;
@@ -567,10 +545,11 @@ static void read_rx_fifo(void)
 {
     // Pop control word off FIFO (completed xfers will have 2 control words,
     // we only pop one ctl word each interrupt).
-    volatile uint32_t ctl_word = USB0.grxstsp;
+    uint32_t ctl_word = USB0.grxstsp;
     uint8_t pktsts = (ctl_word & USB_PKTSTS_M) >> USB_PKTSTS_S;
     uint8_t epnum = (ctl_word & USB_CHNUM_M) >> USB_CHNUM_S;
     uint16_t bcnt = (ctl_word & USB_BCNT_M) >> USB_BCNT_S;
+
     switch (pktsts) {
     case 0x01: // Global OUT NAK (Interrupt)
         ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Global OUT NAK");
@@ -668,12 +647,12 @@ static void handle_epin_ints(void)
             if (USB0.in_ep_reg[n].diepint & USB_D_XFERCOMPL0_M) {
                 ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER complete!");
                 USB0.in_ep_reg[n].diepint = USB_D_XFERCOMPL0_M;
-                // USB0.dtknqr4_fifoemptymsk &= ~(1 << n); // Turn off TXFE b/c xfer inactive.
+                USB0.dtknqr4_fifoemptymsk &= ~(1 << n); // Turn off TXFE b/c xfer inactive.
                 dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
             }
 
             // XFER FIFO empty
-            if (USB0.in_ep_reg[n].diepint & USB_D_XFERCOMPL0_M) {
+            if (USB0.in_ep_reg[n].diepint & USB_D_TXFEMP0_M) {
                 ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER FIFO empty!");
                 USB0.in_ep_reg[n].diepint = USB_D_TXFEMP0_M;
                 transmit_packet(xfer, &USB0.in_ep_reg[n], n);
@@ -685,8 +664,8 @@ static void handle_epin_ints(void)
 
 static void dcd_int_handler(void)
 {
-    uint32_t int_status = USB0.gintsts;
-    uint32_t int_msk = USB0.gintmsk;
+    const uint32_t int_status = USB0.gintsts;
+    const uint32_t int_msk = USB0.gintmsk;
 
     if (int_status & USB_DISCONNINT_M) {
         ESP_EARLY_LOGV(TAG, "dcd_int_handler - disconnected");
-- 
cgit v1.3.1


From c026236824e95d9409136cd48481b69e2cea56dc Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 Apr 2020 16:33:04 +0700
Subject: house keeping

---
 src/device/usbd.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/device/usbd.c b/src/device/usbd.c
index ddd99d7f1..125aa351c 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -421,7 +421,7 @@ void tud_task (void)
         uint8_t const epnum   = tu_edpt_number(ep_addr);
         uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
 
-        TU_LOG2("  Endpoint: 0x%02X, Bytes: %ld\r\n", ep_addr, event.xfer_complete.len);
+        TU_LOG2("  Endpoint: 0x%02X, Bytes: %lu\r\n", ep_addr, event.xfer_complete.len);
 
         _usbd_dev.ep_status[epnum][ep_dir].busy = false;
 
-- 
cgit v1.3.1


From 22a9b05834504471a4446f45e5f8153a8f99d9fa Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 Apr 2020 19:49:25 +0700
Subject: rename dcd_int_handler to dcd_irq_handler for consistency with other
 port

---
 src/portable/espressif/esp32s2/dcd_esp32s2.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

(limited to 'src')

diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c
index 3361bde36..df4cbf445 100644
--- a/src/portable/espressif/esp32s2/dcd_esp32s2.c
+++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c
@@ -136,7 +136,7 @@ static void bus_reset(void)
 static void enum_done_processing(void)
 {
 
-    ESP_EARLY_LOGV(TAG, "dcd_int_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then");
+    ESP_EARLY_LOGV(TAG, "dcd_irq_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then");
     // On current silicon on the Full Speed core, speed is fixed to Full Speed.
     // However, keep for debugging and in case Low Speed is ever supported.
     uint32_t enum_spd = (USB0.dsts >> USB_ENUMSPD_S) & (USB_ENUMSPD_V);
@@ -662,25 +662,25 @@ static void handle_epin_ints(void)
 }
 
 
-static void dcd_int_handler(void)
+void dcd_irq_handler(void)
 {
     const uint32_t int_status = USB0.gintsts;
     const uint32_t int_msk = USB0.gintmsk;
 
     if (int_status & USB_DISCONNINT_M) {
-        ESP_EARLY_LOGV(TAG, "dcd_int_handler - disconnected");
+        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - disconnected");
         USB0.gintsts = USB_DISCONNINT_M;
     }
 
     if (int_status & USB_USBRST_M) {
 
-        ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset");
+        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset");
         USB0.gintsts = USB_USBRST_M;
         bus_reset();
     }
 
     if (int_status & USB_RESETDET_M) {
-        ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset while suspend");
+        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset while suspend");
         USB0.gintsts = USB_RESETDET_M;
         bus_reset();
     }
@@ -700,19 +700,19 @@ static void dcd_int_handler(void)
     }
 
     if ((int_status & USB_RXFLVI_M) & (int_msk & USB_RXFLVIMSK_M)) {
-        ESP_EARLY_LOGV(TAG, "dcd_int_handler - rx!");
+        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - rx!");
         read_rx_fifo();
     }
 
     // OUT endpoint interrupt handling.
     if (int_status & USB_OEPINT_M) {
-        ESP_EARLY_LOGV(TAG, "dcd_int_handler - OUT endpoint!");
+        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - OUT endpoint!");
         handle_epout_ints();
     }
 
     // IN endpoint interrupt handling.
     if (int_status & USB_IEPINT_M) {
-        ESP_EARLY_LOGV(TAG, "dcd_int_handler - IN endpoint!");
+        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - IN endpoint!");
         handle_epin_ints();
     }
 
@@ -737,7 +737,7 @@ static void dcd_int_handler(void)
 void dcd_int_enable(uint8_t rhport)
 {
     (void)rhport;
-    esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)dcd_int_handler, NULL, &usb_ih);
+    esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)dcd_irq_handler, NULL, &usb_ih);
 }
 
 void dcd_int_disable(uint8_t rhport)
-- 
cgit v1.3.1


From 06e87b47a29a0d8c304a08cd1f8bb1ad2168880f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Mon, 6 Apr 2020 21:28:02 +0700
Subject: revert name to dcd_init_handler()

since the function signature is different
---
 src/portable/espressif/esp32s2/dcd_esp32s2.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

(limited to 'src')

diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c
index df4cbf445..3361bde36 100644
--- a/src/portable/espressif/esp32s2/dcd_esp32s2.c
+++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c
@@ -136,7 +136,7 @@ static void bus_reset(void)
 static void enum_done_processing(void)
 {
 
-    ESP_EARLY_LOGV(TAG, "dcd_irq_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then");
+    ESP_EARLY_LOGV(TAG, "dcd_int_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then");
     // On current silicon on the Full Speed core, speed is fixed to Full Speed.
     // However, keep for debugging and in case Low Speed is ever supported.
     uint32_t enum_spd = (USB0.dsts >> USB_ENUMSPD_S) & (USB_ENUMSPD_V);
@@ -662,25 +662,25 @@ static void handle_epin_ints(void)
 }
 
 
-void dcd_irq_handler(void)
+static void dcd_int_handler(void)
 {
     const uint32_t int_status = USB0.gintsts;
     const uint32_t int_msk = USB0.gintmsk;
 
     if (int_status & USB_DISCONNINT_M) {
-        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - disconnected");
+        ESP_EARLY_LOGV(TAG, "dcd_int_handler - disconnected");
         USB0.gintsts = USB_DISCONNINT_M;
     }
 
     if (int_status & USB_USBRST_M) {
 
-        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset");
+        ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset");
         USB0.gintsts = USB_USBRST_M;
         bus_reset();
     }
 
     if (int_status & USB_RESETDET_M) {
-        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset while suspend");
+        ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset while suspend");
         USB0.gintsts = USB_RESETDET_M;
         bus_reset();
     }
@@ -700,19 +700,19 @@ void dcd_irq_handler(void)
     }
 
     if ((int_status & USB_RXFLVI_M) & (int_msk & USB_RXFLVIMSK_M)) {
-        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - rx!");
+        ESP_EARLY_LOGV(TAG, "dcd_int_handler - rx!");
         read_rx_fifo();
     }
 
     // OUT endpoint interrupt handling.
     if (int_status & USB_OEPINT_M) {
-        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - OUT endpoint!");
+        ESP_EARLY_LOGV(TAG, "dcd_int_handler - OUT endpoint!");
         handle_epout_ints();
     }
 
     // IN endpoint interrupt handling.
     if (int_status & USB_IEPINT_M) {
-        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - IN endpoint!");
+        ESP_EARLY_LOGV(TAG, "dcd_int_handler - IN endpoint!");
         handle_epin_ints();
     }
 
@@ -737,7 +737,7 @@ void dcd_irq_handler(void)
 void dcd_int_enable(uint8_t rhport)
 {
     (void)rhport;
-    esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)dcd_irq_handler, NULL, &usb_ih);
+    esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)dcd_int_handler, NULL, &usb_ih);
 }
 
 void dcd_int_disable(uint8_t rhport)
-- 
cgit v1.3.1


From 7b7a78ab2e89a8f147bbe7210923a72560b601d8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 8 Apr 2020 15:29:12 +0700
Subject: disable SOF interrupt since it is not used for now

---
 src/portable/espressif/esp32s2/dcd_esp32s2.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

(limited to 'src')

diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c
index 3361bde36..4cd682e12 100644
--- a/src/portable/espressif/esp32s2/dcd_esp32s2.c
+++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c
@@ -42,6 +42,10 @@
 
 #include "device/dcd.h"
 
+// Since TinyUSB doesn't use SOF for now, and this interrupt too often (1ms interval)
+// We disable SOF for now until needed later on
+#define USE_SOF     0
+
 // FIFO size in bytes TODO need confirmation from Espressif
 #define EP_MAX            USB_OUT_EP_NUM
 #define EP_FIFO_SIZE      1280
@@ -112,7 +116,7 @@ static void bus_reset(void)
     USB0.grxfsiz = 52;
 
     USB0.gintmsk = USB_MODEMISMSK_M |
-                   USB_SOFMSK_M |
+                   /* USB_SOFMSK_M | */
                    USB_RXFLVIMSK_M |
                    USB_ERLYSUSPMSK_M |
                    USB_USBSUSPMSK_M |
@@ -154,7 +158,7 @@ static void enum_done_processing(void)
         xfer_status[0][TUSB_DIR_IN].max_size = 8;
     }
 
-    USB0.gintmsk |= USB_SOFMSK_M; // SOF unmask
+//    USB0.gintmsk |= USB_SOFMSK_M; // SOF unmask
 }
 
 
@@ -202,7 +206,7 @@ void dcd_init(uint8_t rhport)
     USB0.gotgint = ~0U; //clear OTG ints
     USB0.gintsts = ~0U; //clear pending ints
     USB0.gintmsk = USB_MODEMISMSK_M |
-                   USB_SOFMSK_M |
+                   /*USB_SOFMSK_M |*/
                    USB_RXFLVIMSK_M |
                    USB_ERLYSUSPMSK_M |
                    USB_USBSUSPMSK_M |
-- 
cgit v1.3.1


From 880595433ce6b75428dca30b72b41d865a4b89f4 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Wed, 8 Apr 2020 15:41:16 +0700
Subject: use macro for easy enable/disable SOF

---
 src/portable/espressif/esp32s2/dcd_esp32s2.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c
index 4cd682e12..8a11f57b0 100644
--- a/src/portable/espressif/esp32s2/dcd_esp32s2.c
+++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c
@@ -116,7 +116,9 @@ static void bus_reset(void)
     USB0.grxfsiz = 52;
 
     USB0.gintmsk = USB_MODEMISMSK_M |
-                   /* USB_SOFMSK_M | */
+#if USE_SOF
+                   USB_SOFMSK_M |
+#endif
                    USB_RXFLVIMSK_M |
                    USB_ERLYSUSPMSK_M |
                    USB_USBSUSPMSK_M |
@@ -157,8 +159,6 @@ static void enum_done_processing(void)
         xfer_status[0][TUSB_DIR_OUT].max_size = 8;
         xfer_status[0][TUSB_DIR_IN].max_size = 8;
     }
-
-//    USB0.gintmsk |= USB_SOFMSK_M; // SOF unmask
 }
 
 
@@ -206,7 +206,9 @@ void dcd_init(uint8_t rhport)
     USB0.gotgint = ~0U; //clear OTG ints
     USB0.gintsts = ~0U; //clear pending ints
     USB0.gintmsk = USB_MODEMISMSK_M |
-                   /*USB_SOFMSK_M |*/
+#if USE_SOF
+                   USB_SOFMSK_M |
+#endif
                    USB_RXFLVIMSK_M |
                    USB_ERLYSUSPMSK_M |
                    USB_USBSUSPMSK_M |
@@ -698,10 +700,12 @@ static void dcd_int_handler(void)
         dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
     }
 
+#if USE_SOF
     if (int_status & USB_SOF_M) {
         USB0.gintsts = USB_SOF_M;
         dcd_event_bus_signal(0, DCD_EVENT_SOF, true); // do nothing actually
     }
+#endif
 
     if ((int_status & USB_RXFLVI_M) & (int_msk & USB_RXFLVIMSK_M)) {
         ESP_EARLY_LOGV(TAG, "dcd_int_handler - rx!");
-- 
cgit v1.3.1


From 1b3d1b52c9351391f62dea374345c8de7f985b0f Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Apr 2020 13:54:50 +0700
Subject: fix uint32_t format with log

---
 src/device/usbd.c | 2 +-
 src/tusb.c        | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'src')

diff --git a/src/device/usbd.c b/src/device/usbd.c
index 125aa351c..397a681ed 100644
--- a/src/device/usbd.c
+++ b/src/device/usbd.c
@@ -421,7 +421,7 @@ void tud_task (void)
         uint8_t const epnum   = tu_edpt_number(ep_addr);
         uint8_t const ep_dir  = tu_edpt_dir(ep_addr);
 
-        TU_LOG2("  Endpoint: 0x%02X, Bytes: %lu\r\n", ep_addr, event.xfer_complete.len);
+        TU_LOG2("  Endpoint: 0x%02X, Bytes: %u\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
 
         _usbd_dev.ep_status[epnum][ep_dir].busy = false;
 
diff --git a/src/tusb.c b/src/tusb.c
index 8e0022f4d..8f234455f 100644
--- a/src/tusb.c
+++ b/src/tusb.c
@@ -96,9 +96,9 @@ void tu_print_mem(void const *buf, uint16_t count, uint8_t indent)
   char format[] = "%00lX";
   format[2] += 2*size;
 
-  const uint8_t  item_per_line  = 16 / size;
+  const uint8_t item_per_line  = 16 / size;
 
-  for(uint32_t i=0; i<count; i++)
+  for(uint16_t i=0; i<count; i++)
   {
     uint32_t value=0;
 
@@ -115,7 +115,7 @@ void tu_print_mem(void const *buf, uint16_t count, uint8_t indent)
       for(uint8_t s=0; s < indent; s++) tu_printf(" ");
 
       // print offset or absolute address
-      tu_printf("%03lX: ", 16*i/item_per_line);
+      tu_printf("%03X: ", 16*i/item_per_line);
     }
 
     memcpy(&value, buf8, size);
-- 
cgit v1.3.1


From a40d1e800d409dd52d9ea9076771337172ccea28 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Apr 2020 14:04:18 +0700
Subject: try to fix racing condition with setup

---
 src/portable/espressif/esp32s2/dcd_esp32s2.c | 145 +++++++++++++++++----------
 1 file changed, 93 insertions(+), 52 deletions(-)

(limited to 'src')

diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c
index 8a11f57b0..3aebd824e 100644
--- a/src/portable/espressif/esp32s2/dcd_esp32s2.c
+++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c
@@ -60,18 +60,23 @@ typedef struct {
 
 static const char *TAG = "TUSB:DCD";
 static intr_handle_t usb_ih;
-static volatile TU_ATTR_ALIGNED(4) uint32_t _setup_packet[6];
-static volatile uint8_t s_setup_phase = 0; /*  00 - got setup,
-                                               01 - got done setup,
-                                               02 - setup cmd sent*/
+
+
+static uint32_t _setup_packet[2];
 
 #define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
 static xfer_ctl_t xfer_status[EP_MAX][2];
 
+#if 0
+static volatile uint8_t s_setup_phase = 0; /*  00 - got setup,
+                                               01 - got done setup,
+                                               02 - setup cmd sent*/
+
 static inline void readyfor1setup_pkg(int ep_num)
 {
     USB0.out_ep_reg[ep_num].doeptsiz |= (1 << USB_SUPCNT0_S); // doeptsiz 29:30 will decremented on every setup received
 }
+#endif
 
 // Setup the control endpoint 0.
 static void bus_reset(void)
@@ -83,6 +88,10 @@ static void bus_reset(void)
 
     USB0.dcfg &= ~USB_DEVADDR_M; // reset address
 
+    USB0.daintmsk |= USB_OUTEPMSK0_M | USB_INEPMSK0_M;
+    USB0.doepmsk |= USB_SETUPMSK_M | USB_XFERCOMPLMSK;
+    USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M /*| USB_INTKNTXFEMPMSK_M*/;
+
     // "USB Data FIFOs" section in reference manual
     // Peripheral FIFO architecture
     //
@@ -115,28 +124,16 @@ static void bus_reset(void)
     USB0.grstctl |= USB_TXFFLSH_M;        // Flush fifo
     USB0.grxfsiz = 52;
 
-    USB0.gintmsk = USB_MODEMISMSK_M |
-#if USE_SOF
-                   USB_SOFMSK_M |
-#endif
-                   USB_RXFLVIMSK_M |
-                   USB_ERLYSUSPMSK_M |
-                   USB_USBSUSPMSK_M |
-                   USB_USBRSTMSK_M |
-                   USB_ENUMDONEMSK_M |
-                   USB_IEPINTMSK_M |
-                   USB_OEPINTMSK_M |
-                   USB_RESETDETMSK_M |
-                   USB_DISCONNINTMSK_M;
-
-    USB0.daintmsk |= USB_OUTEPMSK0_M | USB_INEPMSK0_M;
-    USB0.doepmsk |= USB_SETUPMSK_M | USB_XFERCOMPLMSK;
-    USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M /*| USB_INTKNTXFEMPMSK_M*/;
-
     // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
     USB0.gnptxfsiz = (16 << USB_NPTXFDEP_S) | (USB0.grxfsiz & 0x0000ffffUL);
 
+#if 0
     readyfor1setup_pkg(0);
+#else
+    USB0.out_ep_reg[0].doeptsiz |= USB_SUPCNT0_M;
+#endif
+
+    USB0.gintmsk |= USB_IEPINTMSK_M | USB_OEPINTMSK_M;
 }
 
 static void enum_done_processing(void)
@@ -162,13 +159,13 @@ static void enum_done_processing(void)
 }
 
 
-
-
 /*------------------------------------------------------------------*/
 /* Controller API
  *------------------------------------------------------------------*/
 void dcd_init(uint8_t rhport)
 {
+    (void)rhport;
+
     ESP_LOGV(TAG, "DCD init - Start");
 
     // A. Disconnect
@@ -198,9 +195,7 @@ void dcd_init(uint8_t rhport)
     for (int n = 0; n < USB_OUT_EP_NUM; n++) {
         USB0.out_ep_reg[n].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK
     }
-    ESP_LOGV(TAG, "DCD init - Soft CONNECT");
-    USB0.dctl &= ~USB_SFTDISCON_M; // Connect
-
+    
     // D. Interruption masking
     USB0.gintmsk = 0;   //mask all
     USB0.gotgint = ~0U; //clear OTG ints
@@ -216,6 +211,10 @@ void dcd_init(uint8_t rhport)
                    USB_ENUMDONEMSK_M |
                    USB_RESETDETMSK_M |
                    USB_DISCONNINTMSK_M;
+
+    ESP_LOGV(TAG, "DCD init - Soft CONNECT");
+    USB0.dctl &= ~USB_SFTDISCON_M; // Connect
+
     ets_delay_us(100);
 }
 
@@ -240,6 +239,18 @@ void dcd_remote_wakeup(uint8_t rhport)
     (void)rhport;
 }
 
+// disconnect by disabling internal pull-up resistor on D+/D-
+void dcd_disconnect(uint8_t rhport)
+{
+  USB0.dctl |= USB_SFTDISCON_M;
+}
+
+// connect by enabling internal pull-up resistor on D+/D-
+void dcd_connect(uint8_t rhport)
+{
+  USB0.dctl &= ~USB_SFTDISCON_M;
+}
+
 /*------------------------------------------------------------------*/
 /* DCD Endpoint port
  *------------------------------------------------------------------*/
@@ -312,7 +323,6 @@ bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
 
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
 {
-
     (void)rhport;
 
     uint8_t const epnum = tu_edpt_number(ep_addr);
@@ -447,7 +457,7 @@ void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 static void receive_packet(xfer_ctl_t *xfer, /* usb_out_endpoint_t * out_ep, */ uint16_t xfer_size)
 {
     ESP_EARLY_LOGV(TAG, "USB - receive_packet");
-    uint32_t *rx_fifo = USB0.fifo[0];
+    volatile uint32_t *rx_fifo = USB0.fifo[0];
 
     // See above TODO
     // uint16_t remaining = (out_ep->DOEPTSIZ & UsbDOEPTSIZ_XFRSIZ_Msk) >> UsbDOEPTSIZ_XFRSIZ_Pos;
@@ -549,35 +559,47 @@ static void transmit_packet(xfer_ctl_t *xfer, volatile usb_in_endpoint_t *in_ep,
 
 static void read_rx_fifo(void)
 {
+    volatile uint32_t *rx_fifo = USB0.fifo[0];
+
     // Pop control word off FIFO (completed xfers will have 2 control words,
     // we only pop one ctl word each interrupt).
-    uint32_t ctl_word = USB0.grxstsp;
-    uint8_t pktsts = (ctl_word & USB_PKTSTS_M) >> USB_PKTSTS_S;
-    uint8_t epnum = (ctl_word & USB_CHNUM_M) >> USB_CHNUM_S;
-    uint16_t bcnt = (ctl_word & USB_BCNT_M) >> USB_BCNT_S;
+    uint32_t const ctl_word = USB0.grxstsp;
+    uint8_t  const pktsts   = (ctl_word & USB_PKTSTS_M) >> USB_PKTSTS_S;
+    uint8_t  const epnum    = (ctl_word & USB_CHNUM_M ) >> USB_CHNUM_S;
+    uint16_t const bcnt     = (ctl_word & USB_BCNT_M  ) >> USB_BCNT_S;
 
     switch (pktsts) {
-    case 0x01: // Global OUT NAK (Interrupt)
+      case 0x01: // Global OUT NAK (Interrupt)
         ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Global OUT NAK");
         break;
-    case 0x02: { // Out packet recvd
+
+      case 0x02: { // Out packet recvd
         ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet");
         xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
         receive_packet(xfer, bcnt);
-    }
-    break;
-    case 0x03: // Out packet done (Interrupt)
+      }
+      break;
+
+      case 0x03: // Out packet done (Interrupt)
         ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet done");
         break;
-    case 0x04:                // Setup packet done (Interrupt)
+
+      case 0x04: // Step 2: Setup transaction completed (Interrupt)
+        // After this event, OEPINT interrupt will occur with SETUP bit set
+#if 0
         if (s_setup_phase == 0) { // only if setup is started
-            s_setup_phase = 1;
-            ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 1"); //finished
-            ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet done");
+          s_setup_phase = 1;
+          ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 1"); //finished
+          ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet done");
         }
+#else
+        USB0.out_ep_reg[epnum].doeptsiz |= USB_SUPCNT0_M;
+#endif
 
         break;
-    case 0x06: { // Setup packet recvd
+
+      case 0x06: { // Step1: Setup data packet received
+#if 0
         s_setup_phase = 0;
         ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 0"); // new setup process
         // For some reason, it's possible to get a mismatch between
@@ -588,11 +610,18 @@ static void read_rx_fifo(void)
         // only accepting one setup packet at a time for now.
         _setup_packet[0] = (USB0.grxstsp);
         _setup_packet[1] = (USB0.grxstsp);
-        ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet : 0x%08x 0x%08x",
-                       _setup_packet[0], _setup_packet[1]);
-    }
-    break;
-    default: // Invalid, do something here, like breakpoint?
+        ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet : 0x%08x 0x%08x", _setup_packet[0], _setup_packet[1]);
+#else
+        // We can receive up to three setup packets in succession, but
+        // only the last one is valid. Therefore we just overwrite it
+        _setup_packet[0] = (*rx_fifo);
+        _setup_packet[1] = (*rx_fifo);
+#endif
+      }
+      break;
+
+      default: // Invalid, do something here, like breakpoint?
+        TU_BREAKPOINT();
         break;
     }
 }
@@ -604,9 +633,11 @@ static void handle_epout_ints(void)
     // DOEPINT will be cleared when DAINT's out bits are cleared.
     for (int n = 0; n < USB_OUT_EP_NUM; n++) {
         xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
+
         if (USB0.daint & (1 << (16 + n))) {
             // SETUP packet Setup Phase done.
             if ((USB0.out_ep_reg[n].doepint & USB_SETUP0_M)) {
+#if 0
                 USB0.out_ep_reg[n].doepint |= USB_STUPPKTRCVD0_M | USB_SETUP0_M; // clear
                 if (s_setup_phase == 1) {                                          // only if setup is done, but not handled
                     s_setup_phase = 2;
@@ -615,6 +646,10 @@ static void handle_epout_ints(void)
                     dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true);
                 }
                 readyfor1setup_pkg(0);
+#else
+                USB0.out_ep_reg[n].doepint = USB_STUPPKTRCVD0_M | USB_SETUP0_M; // clear
+                dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true);
+#endif
             }
 
             // OUT XFER complete (single packet).q
@@ -668,18 +703,21 @@ static void handle_epin_ints(void)
 }
 
 
-static void dcd_int_handler(void)
+static void dcd_int_handler(void* arg)
 {
+    (void) arg;
+
     const uint32_t int_status = USB0.gintsts;
-    const uint32_t int_msk = USB0.gintmsk;
+    //const uint32_t int_msk = USB0.gintmsk;
 
     if (int_status & USB_DISCONNINT_M) {
         ESP_EARLY_LOGV(TAG, "dcd_int_handler - disconnected");
         USB0.gintsts = USB_DISCONNINT_M;
+        dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
     }
 
     if (int_status & USB_USBRST_M) {
-
+        // start of reset
         ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset");
         USB0.gintsts = USB_USBRST_M;
         bus_reset();
@@ -707,9 +745,12 @@ static void dcd_int_handler(void)
     }
 #endif
 
-    if ((int_status & USB_RXFLVI_M) & (int_msk & USB_RXFLVIMSK_M)) {
+    if ((int_status & USB_RXFLVI_M) /*& (int_msk & USB_RXFLVIMSK_M)*/) {
         ESP_EARLY_LOGV(TAG, "dcd_int_handler - rx!");
+        USB0.gintmsk &= ~USB_RXFLVIMSK_M;
         read_rx_fifo();
+        USB0.gintmsk |= USB_RXFLVIMSK_M;
+        USB0.gintsts = USB_RXFLVI_M;
     }
 
     // OUT endpoint interrupt handling.
-- 
cgit v1.3.1


From d122d7de88819b744c192c2b3ab76b2a3d6cfda8 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Apr 2020 14:45:55 +0700
Subject: remove commented code

---
 src/portable/espressif/esp32s2/dcd_esp32s2.c | 57 +++-------------------------
 1 file changed, 6 insertions(+), 51 deletions(-)

(limited to 'src')

diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c
index 3aebd824e..ed01c7877 100644
--- a/src/portable/espressif/esp32s2/dcd_esp32s2.c
+++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c
@@ -67,17 +67,6 @@ static uint32_t _setup_packet[2];
 #define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir]
 static xfer_ctl_t xfer_status[EP_MAX][2];
 
-#if 0
-static volatile uint8_t s_setup_phase = 0; /*  00 - got setup,
-                                               01 - got done setup,
-                                               02 - setup cmd sent*/
-
-static inline void readyfor1setup_pkg(int ep_num)
-{
-    USB0.out_ep_reg[ep_num].doeptsiz |= (1 << USB_SUPCNT0_S); // doeptsiz 29:30 will decremented on every setup received
-}
-#endif
-
 // Setup the control endpoint 0.
 static void bus_reset(void)
 {
@@ -127,11 +116,8 @@ static void bus_reset(void)
     // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
     USB0.gnptxfsiz = (16 << USB_NPTXFDEP_S) | (USB0.grxfsiz & 0x0000ffffUL);
 
-#if 0
-    readyfor1setup_pkg(0);
-#else
+    // Ready to receive SETUP packet
     USB0.out_ep_reg[0].doeptsiz |= USB_SUPCNT0_M;
-#endif
 
     USB0.gintmsk |= USB_IEPINTMSK_M | USB_OEPINTMSK_M;
 }
@@ -559,8 +545,6 @@ static void transmit_packet(xfer_ctl_t *xfer, volatile usb_in_endpoint_t *in_ep,
 
 static void read_rx_fifo(void)
 {
-    volatile uint32_t *rx_fifo = USB0.fifo[0];
-
     // Pop control word off FIFO (completed xfers will have 2 control words,
     // we only pop one ctl word each interrupt).
     uint32_t const ctl_word = USB0.grxstsp;
@@ -586,37 +570,19 @@ static void read_rx_fifo(void)
 
       case 0x04: // Step 2: Setup transaction completed (Interrupt)
         // After this event, OEPINT interrupt will occur with SETUP bit set
-#if 0
-        if (s_setup_phase == 0) { // only if setup is started
-          s_setup_phase = 1;
-          ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 1"); //finished
-          ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet done");
-        }
-#else
+        ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet done");
         USB0.out_ep_reg[epnum].doeptsiz |= USB_SUPCNT0_M;
-#endif
-
         break;
 
       case 0x06: { // Step1: Setup data packet received
-#if 0
-        s_setup_phase = 0;
-        ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 0"); // new setup process
-        // For some reason, it's possible to get a mismatch between
-        // how many setup packets were received versus the location
-        // of the Setup packet done word. This leads to situations
-        // where stale setup packets are in the RX FIFO that were received
-        // after the core loaded the Setup packet done word. Workaround by
-        // only accepting one setup packet at a time for now.
-        _setup_packet[0] = (USB0.grxstsp);
-        _setup_packet[1] = (USB0.grxstsp);
-        ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet : 0x%08x 0x%08x", _setup_packet[0], _setup_packet[1]);
-#else
+        volatile uint32_t *rx_fifo = USB0.fifo[0];
+
         // We can receive up to three setup packets in succession, but
         // only the last one is valid. Therefore we just overwrite it
         _setup_packet[0] = (*rx_fifo);
         _setup_packet[1] = (*rx_fifo);
-#endif
+
+        ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet : 0x%08x 0x%08x", _setup_packet[0], _setup_packet[1]);
       }
       break;
 
@@ -637,19 +603,8 @@ static void handle_epout_ints(void)
         if (USB0.daint & (1 << (16 + n))) {
             // SETUP packet Setup Phase done.
             if ((USB0.out_ep_reg[n].doepint & USB_SETUP0_M)) {
-#if 0
-                USB0.out_ep_reg[n].doepint |= USB_STUPPKTRCVD0_M | USB_SETUP0_M; // clear
-                if (s_setup_phase == 1) {                                          // only if setup is done, but not handled
-                    s_setup_phase = 2;
-                    ESP_EARLY_LOGV(TAG, "TUSB IRQ - setup_phase 2"); // sending to  a handling queue
-                    ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP OUT - Setup Phase done (irq-s 0x%08x)", USB0.out_ep_reg[n].doepint);
-                    dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true);
-                }
-                readyfor1setup_pkg(0);
-#else
                 USB0.out_ep_reg[n].doepint = USB_STUPPKTRCVD0_M | USB_SETUP0_M; // clear
                 dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true);
-#endif
             }
 
             // OUT XFER complete (single packet).q
-- 
cgit v1.3.1


From cec747776dd08452e2cd446262e407c60f4bfd7a Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Apr 2020 14:47:02 +0700
Subject: rename dcd_init_handler to dcd_irq_handler to consistent with other
 ports

---
 src/portable/espressif/esp32s2/dcd_esp32s2.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

(limited to 'src')

diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c
index ed01c7877..27312824e 100644
--- a/src/portable/espressif/esp32s2/dcd_esp32s2.c
+++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c
@@ -125,7 +125,7 @@ static void bus_reset(void)
 static void enum_done_processing(void)
 {
 
-    ESP_EARLY_LOGV(TAG, "dcd_int_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then");
+    ESP_EARLY_LOGV(TAG, "dcd_irq_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then");
     // On current silicon on the Full Speed core, speed is fixed to Full Speed.
     // However, keep for debugging and in case Low Speed is ever supported.
     uint32_t enum_spd = (USB0.dsts >> USB_ENUMSPD_S) & (USB_ENUMSPD_V);
@@ -658,28 +658,28 @@ static void handle_epin_ints(void)
 }
 
 
-static void dcd_int_handler(void* arg)
+void dcd_irq_handler(uint32_t rhport)
 {
-    (void) arg;
+    (void) rhport;
 
     const uint32_t int_status = USB0.gintsts;
     //const uint32_t int_msk = USB0.gintmsk;
 
     if (int_status & USB_DISCONNINT_M) {
-        ESP_EARLY_LOGV(TAG, "dcd_int_handler - disconnected");
+        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - disconnected");
         USB0.gintsts = USB_DISCONNINT_M;
         dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
     }
 
     if (int_status & USB_USBRST_M) {
         // start of reset
-        ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset");
+        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset");
         USB0.gintsts = USB_USBRST_M;
         bus_reset();
     }
 
     if (int_status & USB_RESETDET_M) {
-        ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset while suspend");
+        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset while suspend");
         USB0.gintsts = USB_RESETDET_M;
         bus_reset();
     }
@@ -701,7 +701,7 @@ static void dcd_int_handler(void* arg)
 #endif
 
     if ((int_status & USB_RXFLVI_M) /*& (int_msk & USB_RXFLVIMSK_M)*/) {
-        ESP_EARLY_LOGV(TAG, "dcd_int_handler - rx!");
+        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - rx!");
         USB0.gintmsk &= ~USB_RXFLVIMSK_M;
         read_rx_fifo();
         USB0.gintmsk |= USB_RXFLVIMSK_M;
@@ -710,13 +710,13 @@ static void dcd_int_handler(void* arg)
 
     // OUT endpoint interrupt handling.
     if (int_status & USB_OEPINT_M) {
-        ESP_EARLY_LOGV(TAG, "dcd_int_handler - OUT endpoint!");
+        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - OUT endpoint!");
         handle_epout_ints();
     }
 
     // IN endpoint interrupt handling.
     if (int_status & USB_IEPINT_M) {
-        ESP_EARLY_LOGV(TAG, "dcd_int_handler - IN endpoint!");
+        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - IN endpoint!");
         handle_epin_ints();
     }
 
@@ -741,7 +741,7 @@ static void dcd_int_handler(void* arg)
 void dcd_int_enable(uint8_t rhport)
 {
     (void)rhport;
-    esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)dcd_int_handler, NULL, &usb_ih);
+    esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)dcd_irq_handler, NULL, &usb_ih);
 }
 
 void dcd_int_disable(uint8_t rhport)
-- 
cgit v1.3.1


From 933e3cdfc754c42936e5be7e84bf1c55f77b8bd0 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Apr 2020 15:01:12 +0700
Subject: change indent from 4 -> 2 spaces

---
 src/portable/espressif/esp32s2/dcd_esp32s2.c | 1078 +++++++++++++-------------
 1 file changed, 540 insertions(+), 538 deletions(-)

(limited to 'src')

diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c
index 27312824e..e0a2c2454 100644
--- a/src/portable/espressif/esp32s2/dcd_esp32s2.c
+++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c
@@ -70,78 +70,76 @@ static xfer_ctl_t xfer_status[EP_MAX][2];
 // Setup the control endpoint 0.
 static void bus_reset(void)
 {
-
-    for (int ep_num = 0; ep_num < USB_OUT_EP_NUM; ep_num++) {
-        USB0.out_ep_reg[ep_num].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK
-    }
-
-    USB0.dcfg &= ~USB_DEVADDR_M; // reset address
-
-    USB0.daintmsk |= USB_OUTEPMSK0_M | USB_INEPMSK0_M;
-    USB0.doepmsk |= USB_SETUPMSK_M | USB_XFERCOMPLMSK;
-    USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M /*| USB_INTKNTXFEMPMSK_M*/;
-
-    // "USB Data FIFOs" section in reference manual
-    // Peripheral FIFO architecture
-    //
-    // --------------- 320 or 1024 ( 1280 or 4096 bytes )
-    // | IN FIFO MAX |
-    // ---------------
-    // |    ...      |
-    // --------------- y + x + 16 + GRXFSIZ
-    // | IN FIFO 2   |
-    // --------------- x + 16 + GRXFSIZ
-    // | IN FIFO 1   |
-    // --------------- 16 + GRXFSIZ
-    // | IN FIFO 0   |
-    // --------------- GRXFSIZ
-    // | OUT FIFO    |
-    // | ( Shared )  |
-    // --------------- 0
-    //
-    // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits):
-    // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN
-    //
-    // - All EP OUT shared a unique OUT FIFO which uses
-    //   * 10 locations in hardware for setup packets + setup control words (up to 3 setup packets).
-    //   * 2 locations for OUT endpoint control words.
-    //   * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes)
-    //   * 1 location for global NAK (not required/used here).
-    //   * It is recommended to allocate 2 times the largest packet size, therefore
-    //   Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 52
-    USB0.grstctl |= 0x10 << USB_TXFNUM_S; // fifo 0x10,
-    USB0.grstctl |= USB_TXFFLSH_M;        // Flush fifo
-    USB0.grxfsiz = 52;
-
-    // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
-    USB0.gnptxfsiz = (16 << USB_NPTXFDEP_S) | (USB0.grxfsiz & 0x0000ffffUL);
-
-    // Ready to receive SETUP packet
-    USB0.out_ep_reg[0].doeptsiz |= USB_SUPCNT0_M;
-
-    USB0.gintmsk |= USB_IEPINTMSK_M | USB_OEPINTMSK_M;
+  for (int ep_num = 0; ep_num < USB_OUT_EP_NUM; ep_num++) {
+    USB0.out_ep_reg[ep_num].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK
+  }
+
+  USB0.dcfg &= ~USB_DEVADDR_M; // reset address
+
+  USB0.daintmsk |= USB_OUTEPMSK0_M | USB_INEPMSK0_M;
+  USB0.doepmsk |= USB_SETUPMSK_M | USB_XFERCOMPLMSK;
+  USB0.diepmsk |= USB_TIMEOUTMSK_M | USB_DI_XFERCOMPLMSK_M /*| USB_INTKNTXFEMPMSK_M*/;
+
+  // "USB Data FIFOs" section in reference manual
+  // Peripheral FIFO architecture
+  //
+  // --------------- 320 or 1024 ( 1280 or 4096 bytes )
+  // | IN FIFO MAX |
+  // ---------------
+  // |    ...      |
+  // --------------- y + x + 16 + GRXFSIZ
+  // | IN FIFO 2   |
+  // --------------- x + 16 + GRXFSIZ
+  // | IN FIFO 1   |
+  // --------------- 16 + GRXFSIZ
+  // | IN FIFO 0   |
+  // --------------- GRXFSIZ
+  // | OUT FIFO    |
+  // | ( Shared )  |
+  // --------------- 0
+  //
+  // According to "FIFO RAM allocation" section in RM, FIFO RAM are allocated as follows (each word 32-bits):
+  // - Each EP IN needs at least max packet size, 16 words is sufficient for EP0 IN
+  //
+  // - All EP OUT shared a unique OUT FIFO which uses
+  //   * 10 locations in hardware for setup packets + setup control words (up to 3 setup packets).
+  //   * 2 locations for OUT endpoint control words.
+  //   * 16 for largest packet size of 64 bytes. ( TODO Highspeed is 512 bytes)
+  //   * 1 location for global NAK (not required/used here).
+  //   * It is recommended to allocate 2 times the largest packet size, therefore
+  //   Recommended value = 10 + 1 + 2 x (16+2) = 47 --> Let's make it 52
+  USB0.grstctl |= 0x10 << USB_TXFNUM_S; // fifo 0x10,
+  USB0.grstctl |= USB_TXFFLSH_M;        // Flush fifo
+  USB0.grxfsiz = 52;
+
+  // Control IN uses FIFO 0 with 64 bytes ( 16 32-bit word )
+  USB0.gnptxfsiz = (16 << USB_NPTXFDEP_S) | (USB0.grxfsiz & 0x0000ffffUL);
+
+  // Ready to receive SETUP packet
+  USB0.out_ep_reg[0].doeptsiz |= USB_SUPCNT0_M;
+
+  USB0.gintmsk |= USB_IEPINTMSK_M | USB_OEPINTMSK_M;
 }
 
 static void enum_done_processing(void)
 {
-
-    ESP_EARLY_LOGV(TAG, "dcd_irq_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then");
-    // On current silicon on the Full Speed core, speed is fixed to Full Speed.
-    // However, keep for debugging and in case Low Speed is ever supported.
-    uint32_t enum_spd = (USB0.dsts >> USB_ENUMSPD_S) & (USB_ENUMSPD_V);
-
-    // Maximum packet size for EP 0 is set for both directions by writing DIEPCTL
-    if (enum_spd == 0x03) { // Full-Speed (PHY on 48 MHz)
-        USB0.in_ep_reg[0].diepctl &= ~USB_D_MPS0_V;    // 64 bytes
-        USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall
-        xfer_status[0][TUSB_DIR_OUT].max_size = 64;
-        xfer_status[0][TUSB_DIR_IN].max_size = 64;
-    } else {
-        USB0.in_ep_reg[0].diepctl |= USB_D_MPS0_V;     // 8 bytes
-        USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall
-        xfer_status[0][TUSB_DIR_OUT].max_size = 8;
-        xfer_status[0][TUSB_DIR_IN].max_size = 8;
-    }
+  ESP_EARLY_LOGV(TAG, "dcd_irq_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then");
+  // On current silicon on the Full Speed core, speed is fixed to Full Speed.
+  // However, keep for debugging and in case Low Speed is ever supported.
+  uint32_t enum_spd = (USB0.dsts >> USB_ENUMSPD_S) & (USB_ENUMSPD_V);
+
+  // Maximum packet size for EP 0 is set for both directions by writing DIEPCTL
+  if (enum_spd == 0x03) { // Full-Speed (PHY on 48 MHz)
+    USB0.in_ep_reg[0].diepctl &= ~USB_D_MPS0_V;    // 64 bytes
+    USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall
+    xfer_status[0][TUSB_DIR_OUT].max_size = 64;
+    xfer_status[0][TUSB_DIR_IN].max_size = 64;
+  } else {
+    USB0.in_ep_reg[0].diepctl |= USB_D_MPS0_V;     // 8 bytes
+    USB0.in_ep_reg[0].diepctl &= ~USB_D_STALL0_M; // clear Stall
+    xfer_status[0][TUSB_DIR_OUT].max_size = 8;
+    xfer_status[0][TUSB_DIR_IN].max_size = 8;
+  }
 }
 
 
@@ -150,79 +148,79 @@ static void enum_done_processing(void)
  *------------------------------------------------------------------*/
 void dcd_init(uint8_t rhport)
 {
-    (void)rhport;
+  (void)rhport;
 
-    ESP_LOGV(TAG, "DCD init - Start");
+  ESP_LOGV(TAG, "DCD init - Start");
 
-    // A. Disconnect
-    ESP_LOGV(TAG, "DCD init - Soft DISCONNECT and Setting up");
-    USB0.dctl |= USB_SFTDISCON_M; // Soft disconnect
+  // A. Disconnect
+  ESP_LOGV(TAG, "DCD init - Soft DISCONNECT and Setting up");
+  USB0.dctl |= USB_SFTDISCON_M; // Soft disconnect
 
-    // B. Programming DCFG
-    /* If USB host misbehaves during status portion of control xfer
+  // B. Programming DCFG
+  /* If USB host misbehaves during status portion of control xfer
     (non zero-length packet), send STALL back and discard. Full speed. */
-    USB0.dcfg |= USB_NZSTSOUTHSHK_M | // NonZero .... STALL
-                 (3 << 0);            // dev speed: fullspeed 1.1 on 48 mhz  // TODO no value in usb_reg.h (IDF-1476)
+  USB0.dcfg |= USB_NZSTSOUTHSHK_M | // NonZero .... STALL
+      (3 << 0);            // dev speed: fullspeed 1.1 on 48 mhz  // TODO no value in usb_reg.h (IDF-1476)
 
-    USB0.gahbcfg |= USB_NPTXFEMPLVL_M | USB_GLBLLNTRMSK_M; // Global interruptions ON
-    USB0.gusbcfg |= USB_FORCEDEVMODE_M;                    // force devmode
+  USB0.gahbcfg |= USB_NPTXFEMPLVL_M | USB_GLBLLNTRMSK_M; // Global interruptions ON
+  USB0.gusbcfg |= USB_FORCEDEVMODE_M;                    // force devmode
 
-    USB0.gotgctl &= ~(USB_BVALIDOVVAL_M | USB_BVALIDOVEN_M | USB_VBVALIDOVVAL_M); //no overrides
+  USB0.gotgctl &= ~(USB_BVALIDOVVAL_M | USB_BVALIDOVEN_M | USB_VBVALIDOVVAL_M); //no overrides
 #ifdef CONFIG_IDF_TARGET_ESP32S2BETA // needed for beta chip only
-    //C. chip 7.2.2 hack
-    ESP_LOGV(TAG, "DCD init - chip ESP32-S2 beta hack");
-    USB0.gotgctl = (0 << USB_BVALIDOVVAL_S); //B override value
-    ets_delay_us(20);
-    USB0.gotgctl = (0 << USB_BVALIDOVVAL_S) | (1 << USB_BVALIDOVEN_S); //B override value & enable
-    ets_delay_us(20);
+  //C. chip 7.2.2 hack
+  ESP_LOGV(TAG, "DCD init - chip ESP32-S2 beta hack");
+  USB0.gotgctl = (0 << USB_BVALIDOVVAL_S); //B override value
+  ets_delay_us(20);
+  USB0.gotgctl = (0 << USB_BVALIDOVVAL_S) | (1 << USB_BVALIDOVEN_S); //B override value & enable
+  ets_delay_us(20);
 #endif
 
-    // C. Setting SNAKs, then connect
-    for (int n = 0; n < USB_OUT_EP_NUM; n++) {
-        USB0.out_ep_reg[n].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK
-    }
-    
-    // D. Interruption masking
-    USB0.gintmsk = 0;   //mask all
-    USB0.gotgint = ~0U; //clear OTG ints
-    USB0.gintsts = ~0U; //clear pending ints
-    USB0.gintmsk = USB_MODEMISMSK_M |
-#if USE_SOF
-                   USB_SOFMSK_M |
-#endif
-                   USB_RXFLVIMSK_M |
-                   USB_ERLYSUSPMSK_M |
-                   USB_USBSUSPMSK_M |
-                   USB_USBRSTMSK_M |
-                   USB_ENUMDONEMSK_M |
-                   USB_RESETDETMSK_M |
-                   USB_DISCONNINTMSK_M;
-
-    ESP_LOGV(TAG, "DCD init - Soft CONNECT");
-    USB0.dctl &= ~USB_SFTDISCON_M; // Connect
-
-    ets_delay_us(100);
+  // C. Setting SNAKs, then connect
+  for (int n = 0; n < USB_OUT_EP_NUM; n++) {
+    USB0.out_ep_reg[n].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK
+  }
+
+  // D. Interruption masking
+  USB0.gintmsk = 0;   //mask all
+  USB0.gotgint = ~0U; //clear OTG ints
+  USB0.gintsts = ~0U; //clear pending ints
+  USB0.gintmsk = USB_MODEMISMSK_M  |
+          #if USE_SOF
+                 USB_SOFMSK_M      |
+          #endif
+                 USB_RXFLVIMSK_M   |
+                 USB_ERLYSUSPMSK_M |
+                 USB_USBSUSPMSK_M  |
+                 USB_USBRSTMSK_M   |
+                 USB_ENUMDONEMSK_M |
+                 USB_RESETDETMSK_M |
+                 USB_DISCONNINTMSK_M;
+
+  ESP_LOGV(TAG, "DCD init - Soft CONNECT");
+  USB0.dctl &= ~USB_SFTDISCON_M; // Connect
+
+  ets_delay_us(100);
 }
 
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
 {
-    (void)rhport;
-    ESP_LOGV(TAG, "DCD init - Set address : %u", dev_addr);
-    USB0.dcfg |= ((dev_addr & USB_DEVADDR_V) << USB_DEVADDR_S);
-    // Response with status after changing device address
-    dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
+  (void)rhport;
+  ESP_LOGV(TAG, "DCD init - Set address : %u", dev_addr);
+  USB0.dcfg |= ((dev_addr & USB_DEVADDR_V) << USB_DEVADDR_S);
+  // Response with status after changing device address
+  dcd_edpt_xfer(rhport, tu_edpt_addr(0, TUSB_DIR_IN), NULL, 0);
 }
 
 void dcd_set_config(uint8_t rhport, uint8_t config_num)
 {
-    (void)rhport;
-    (void)config_num;
-    // Nothing to do
+  (void)rhport;
+  (void)config_num;
+  // Nothing to do
 }
 
 void dcd_remote_wakeup(uint8_t rhport)
 {
-    (void)rhport;
+  (void)rhport;
 }
 
 // disconnect by disabling internal pull-up resistor on D+/D-
@@ -243,511 +241,515 @@ void dcd_connect(uint8_t rhport)
 
 bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt)
 {
+  ESP_LOGV(TAG, "DCD endpoint opened");
+  (void)rhport;
 
-    ESP_LOGV(TAG, "DCD endpoint opened");
-    (void)rhport;
+  usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]);
+  usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]);
 
-    usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]);
-    usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]);
+  uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
+  uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
 
-    uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress);
-    uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress);
+  TU_ASSERT(desc_edpt->wMaxPacketSize.size <= 64);
+  TU_ASSERT(epnum < EP_MAX);
 
-    TU_ASSERT(desc_edpt->wMaxPacketSize.size <= 64);
-    TU_ASSERT(epnum < EP_MAX);
+  xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
+  xfer->max_size = desc_edpt->wMaxPacketSize.size;
 
-    xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
-    xfer->max_size = desc_edpt->wMaxPacketSize.size;
-
-    if (dir == TUSB_DIR_OUT) {
-        out_ep[epnum].doepctl |= USB_USBACTEP0_M |
-                                 desc_edpt->bmAttributes.xfer << USB_EPTYPE0_S |
-                                 desc_edpt->wMaxPacketSize.size << USB_MPS0_S;
-        USB0.daintmsk |= (1 << (16 + epnum));
-    } else {
-        // "USB Data FIFOs" section in reference manual
-        // Peripheral FIFO architecture
-        //
-        // --------------- 320 or 1024 ( 1280 or 4096 bytes )
-        // | IN FIFO MAX |
-        // ---------------
-        // |    ...      |
-        // --------------- y + x + 16 + GRXFSIZ
-        // | IN FIFO 2   |
-        // --------------- x + 16 + GRXFSIZ
-        // | IN FIFO 1   |
-        // --------------- 16 + GRXFSIZ
-        // | IN FIFO 0   |
-        // --------------- GRXFSIZ
-        // | OUT FIFO    |
-        // | ( Shared )  |
-        // --------------- 0
-        //
-        // Since OUT FIFO = GRXFSIZ, FIFO 0 = 16, for simplicity, we equally allocated for the rest of endpoints
-        // - Size  : (FIFO_SIZE/4 - GRXFSIZ - 16) / (EP_MAX-1)
-        // - Offset: GRXFSIZ + 16 + Size*(epnum-1)
-        // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
-
-        in_ep[epnum].diepctl |= USB_D_USBACTEP1_M |
-                                epnum << USB_D_TXFNUM1_S |
-                                desc_edpt->bmAttributes.xfer << USB_D_EPTYPE1_S |
-                                (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? (1 << USB_DI_SETD0PID1_S) : 0) |
-                                desc_edpt->wMaxPacketSize.size << 0;
-        USB0.daintmsk |= (1 << (0 + epnum));
-
-        // Both TXFD and TXSA are in unit of 32-bit words.
-        // IN FIFO 0 was configured during enumeration, hence the "+ 16".
-        uint16_t const allocated_size = (USB0.grxfsiz & 0x0000ffff) + 16;
-        uint16_t const fifo_size = (EP_FIFO_SIZE/4 - allocated_size) / (EP_MAX-1);
-        uint32_t const fifo_offset = allocated_size + fifo_size*(epnum-1);
-
-        // DIEPTXF starts at FIFO #1.
-        USB0.dieptxf[epnum - 1] = (fifo_size << USB_NPTXFDEP_S) | fifo_offset;
-    }
-    return true;
+  if (dir == TUSB_DIR_OUT) {
+    out_ep[epnum].doepctl |= USB_USBACTEP0_M |
+        desc_edpt->bmAttributes.xfer << USB_EPTYPE0_S |
+        desc_edpt->wMaxPacketSize.size << USB_MPS0_S;
+    USB0.daintmsk |= (1 << (16 + epnum));
+  } else {
+    // "USB Data FIFOs" section in reference manual
+    // Peripheral FIFO architecture
+    //
+    // --------------- 320 or 1024 ( 1280 or 4096 bytes )
+    // | IN FIFO MAX |
+    // ---------------
+    // |    ...      |
+    // --------------- y + x + 16 + GRXFSIZ
+    // | IN FIFO 2   |
+    // --------------- x + 16 + GRXFSIZ
+    // | IN FIFO 1   |
+    // --------------- 16 + GRXFSIZ
+    // | IN FIFO 0   |
+    // --------------- GRXFSIZ
+    // | OUT FIFO    |
+    // | ( Shared )  |
+    // --------------- 0
+    //
+    // Since OUT FIFO = GRXFSIZ, FIFO 0 = 16, for simplicity, we equally allocated for the rest of endpoints
+    // - Size  : (FIFO_SIZE/4 - GRXFSIZ - 16) / (EP_MAX-1)
+    // - Offset: GRXFSIZ + 16 + Size*(epnum-1)
+    // - IN EP 1 gets FIFO 1, IN EP "n" gets FIFO "n".
+
+    in_ep[epnum].diepctl |= USB_D_USBACTEP1_M |
+        epnum << USB_D_TXFNUM1_S |
+        desc_edpt->bmAttributes.xfer << USB_D_EPTYPE1_S |
+        (desc_edpt->bmAttributes.xfer != TUSB_XFER_ISOCHRONOUS ? (1 << USB_DI_SETD0PID1_S) : 0) |
+        desc_edpt->wMaxPacketSize.size << 0;
+    USB0.daintmsk |= (1 << (0 + epnum));
+
+    // Both TXFD and TXSA are in unit of 32-bit words.
+    // IN FIFO 0 was configured during enumeration, hence the "+ 16".
+    uint16_t const allocated_size = (USB0.grxfsiz & 0x0000ffff) + 16;
+    uint16_t const fifo_size = (EP_FIFO_SIZE/4 - allocated_size) / (EP_MAX-1);
+    uint32_t const fifo_offset = allocated_size + fifo_size*(epnum-1);
+
+    // DIEPTXF starts at FIFO #1.
+    USB0.dieptxf[epnum - 1] = (fifo_size << USB_NPTXFDEP_S) | fifo_offset;
+  }
+  return true;
 }
 
 bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
 {
-    (void)rhport;
-
-    uint8_t const epnum = tu_edpt_number(ep_addr);
-    uint8_t const dir = tu_edpt_dir(ep_addr);
-
-    xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
-    xfer->buffer = buffer;
-    xfer->total_len = total_bytes;
-    xfer->queued_len = 0;
-    xfer->short_packet = false;
-
-    uint16_t num_packets = (total_bytes / xfer->max_size);
-    uint8_t short_packet_size = total_bytes % xfer->max_size;
-
-    // Zero-size packet is special case.
-    if (short_packet_size > 0 || (total_bytes == 0)) {
-        num_packets++;
-    }
-
-    ESP_LOGV(TAG, "Transfer <-> EP%i, %s, pkgs: %i, bytes: %i",
-             epnum, ((dir == TUSB_DIR_IN) ? "USB0.HOST (in)" : "HOST->DEV (out)"),
-             num_packets, total_bytes);
-
-    // IN and OUT endpoint xfers are interrupt-driven, we just schedule them
-    // here.
-    if (dir == TUSB_DIR_IN) {
-        // A full IN transfer (multiple packets, possibly) triggers XFRC.
-        USB0.in_ep_reg[epnum].dieptsiz = (num_packets << USB_D_PKTCNT0_S) | total_bytes;
-        USB0.in_ep_reg[epnum].diepctl |= USB_D_EPENA1_M | USB_D_CNAK1_M; // Enable | CNAK
-        USB0.dtknqr4_fifoemptymsk |= (1 << epnum);
-    } else {
-        // Each complete packet for OUT xfers triggers XFRC.
-        USB0.out_ep_reg[epnum].doeptsiz = USB_PKTCNT0_M |
-                                          ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S);
-        USB0.out_ep_reg[epnum].doepctl |= USB_EPENA0_M | USB_CNAK0_M;
-    }
-    return true;
+  (void)rhport;
+
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
+
+  xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir);
+  xfer->buffer = buffer;
+  xfer->total_len = total_bytes;
+  xfer->queued_len = 0;
+  xfer->short_packet = false;
+
+  uint16_t num_packets = (total_bytes / xfer->max_size);
+  uint8_t short_packet_size = total_bytes % xfer->max_size;
+
+  // Zero-size packet is special case.
+  if (short_packet_size > 0 || (total_bytes == 0)) {
+    num_packets++;
+  }
+
+  ESP_LOGV(TAG, "Transfer <-> EP%i, %s, pkgs: %i, bytes: %i",
+           epnum, ((dir == TUSB_DIR_IN) ? "USB0.HOST (in)" : "HOST->DEV (out)"),
+           num_packets, total_bytes);
+
+  // IN and OUT endpoint xfers are interrupt-driven, we just schedule them
+  // here.
+  if (dir == TUSB_DIR_IN) {
+    // A full IN transfer (multiple packets, possibly) triggers XFRC.
+    USB0.in_ep_reg[epnum].dieptsiz = (num_packets << USB_D_PKTCNT0_S) | total_bytes;
+    USB0.in_ep_reg[epnum].diepctl |= USB_D_EPENA1_M | USB_D_CNAK1_M; // Enable | CNAK
+    USB0.dtknqr4_fifoemptymsk |= (1 << epnum);
+  } else {
+    // Each complete packet for OUT xfers triggers XFRC.
+    USB0.out_ep_reg[epnum].doeptsiz = USB_PKTCNT0_M |
+        ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S);
+    USB0.out_ep_reg[epnum].doepctl |= USB_EPENA0_M | USB_CNAK0_M;
+  }
+  return true;
 }
 
 void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
 {
-    (void)rhport;
+  (void)rhport;
 
-    usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]);
-    usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]);
+  usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]);
+  usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]);
 
-    uint8_t const epnum = tu_edpt_number(ep_addr);
-    uint8_t const dir = tu_edpt_dir(ep_addr);
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-    if (dir == TUSB_DIR_IN) {
-        // Only disable currently enabled non-control endpoint
-        if ((epnum == 0) || !(in_ep[epnum].diepctl & USB_D_EPENA1_M)) {
-            in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M);
-        } else {
-            // Stop transmitting packets and NAK IN xfers.
-            in_ep[epnum].diepctl |= USB_DI_SNAK1_M;
-            while ((in_ep[epnum].diepint & USB_DI_SNAK1_M) == 0)
-                ;
-
-            // Disable the endpoint. Note that both SNAK and STALL are set here.
-            in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M |
-                                     USB_D_EPDIS1_M);
-            while ((in_ep[epnum].diepint & USB_D_EPDISBLD0_M) == 0)
-                ;
-            in_ep[epnum].diepint = USB_D_EPDISBLD0_M;
-        }
+  if (dir == TUSB_DIR_IN) {
+    // Only disable currently enabled non-control endpoint
+    if ((epnum == 0) || !(in_ep[epnum].diepctl & USB_D_EPENA1_M)) {
+      in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M);
+    } else {
+      // Stop transmitting packets and NAK IN xfers.
+      in_ep[epnum].diepctl |= USB_DI_SNAK1_M;
+      while ((in_ep[epnum].diepint & USB_DI_SNAK1_M) == 0)
+        ;
+
+      // Disable the endpoint. Note that both SNAK and STALL are set here.
+      in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M |
+          USB_D_EPDIS1_M);
+      while ((in_ep[epnum].diepint & USB_D_EPDISBLD0_M) == 0)
+        ;
+      in_ep[epnum].diepint = USB_D_EPDISBLD0_M;
+    }
 
-        // Flush the FIFO, and wait until we have confirmed it cleared.
-        USB0.grstctl |= ((epnum - 1) << USB_TXFNUM_S);
-        USB0.grstctl |= USB_TXFFLSH_M;
-        while ((USB0.grstctl & USB_TXFFLSH_M) != 0)
-            ;
+    // Flush the FIFO, and wait until we have confirmed it cleared.
+    USB0.grstctl |= ((epnum - 1) << USB_TXFNUM_S);
+    USB0.grstctl |= USB_TXFFLSH_M;
+    while ((USB0.grstctl & USB_TXFFLSH_M) != 0)
+      ;
+  } else {
+    // Only disable currently enabled non-control endpoint
+    if ((epnum == 0) || !(out_ep[epnum].doepctl & USB_EPENA0_M)) {
+      out_ep[epnum].doepctl |= USB_STALL0_M;
     } else {
-        // Only disable currently enabled non-control endpoint
-        if ((epnum == 0) || !(out_ep[epnum].doepctl & USB_EPENA0_M)) {
-            out_ep[epnum].doepctl |= USB_STALL0_M;
-        } else {
-            // Asserting GONAK is required to STALL an OUT endpoint.
-            // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
-            // anyway, and it can't be cleared by user code. If this while loop never
-            // finishes, we have bigger problems than just the stack.
-            USB0.dctl |= USB_SGOUTNAK_M;
-            while ((USB0.gintsts & USB_GOUTNAKEFF_M) == 0)
-                ;
-
-            // Ditto here- disable the endpoint. Note that only STALL and not SNAK
-            // is set here.
-            out_ep[epnum].doepctl |= (USB_STALL0_M | USB_EPDIS0_M);
-            while ((out_ep[epnum].doepint & USB_EPDISBLD0_M) == 0)
-                ;
-            out_ep[epnum].doepint = USB_EPDISBLD0_M;
-
-            // Allow other OUT endpoints to keep receiving.
-            USB0.dctl |= USB_CGOUTNAK_M;
-        }
+      // Asserting GONAK is required to STALL an OUT endpoint.
+      // Simpler to use polling here, we don't use the "B"OUTNAKEFF interrupt
+      // anyway, and it can't be cleared by user code. If this while loop never
+      // finishes, we have bigger problems than just the stack.
+      USB0.dctl |= USB_SGOUTNAK_M;
+      while ((USB0.gintsts & USB_GOUTNAKEFF_M) == 0)
+        ;
+
+      // Ditto here- disable the endpoint. Note that only STALL and not SNAK
+      // is set here.
+      out_ep[epnum].doepctl |= (USB_STALL0_M | USB_EPDIS0_M);
+      while ((out_ep[epnum].doepint & USB_EPDISBLD0_M) == 0)
+        ;
+      out_ep[epnum].doepint = USB_EPDISBLD0_M;
+
+      // Allow other OUT endpoints to keep receiving.
+      USB0.dctl |= USB_CGOUTNAK_M;
     }
+  }
 }
 
 void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
 {
-    (void)rhport;
-
-    usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]);
-    usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]);
+  (void)rhport;
 
-    uint8_t const epnum = tu_edpt_number(ep_addr);
-    uint8_t const dir = tu_edpt_dir(ep_addr);
+  usb_out_endpoint_t *out_ep = &(USB0.out_ep_reg[0]);
+  usb_in_endpoint_t *in_ep = &(USB0.in_ep_reg[0]);
 
-    if (dir == TUSB_DIR_IN) {
-        in_ep[epnum].diepctl &= ~USB_D_STALL1_M;
+  uint8_t const epnum = tu_edpt_number(ep_addr);
+  uint8_t const dir = tu_edpt_dir(ep_addr);
 
-        uint8_t eptype = (in_ep[epnum].diepctl & USB_D_EPTYPE1_M) >> USB_D_EPTYPE1_S;
-        // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt
-        // and bulk endpoints.
-        if (eptype == 2 || eptype == 3) {
-            in_ep[epnum].diepctl |= USB_DI_SETD0PID1_M;
-        }
-    } else {
-        out_ep[epnum].doepctl &= ~USB_STALL1_M;
+  if (dir == TUSB_DIR_IN) {
+    in_ep[epnum].diepctl &= ~USB_D_STALL1_M;
 
-        uint8_t eptype = (out_ep[epnum].doepctl & USB_EPTYPE1_M) >> USB_EPTYPE1_S;
-        // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt
-        // and bulk endpoints.
-        if (eptype == 2 || eptype == 3) {
-            out_ep[epnum].doepctl |= USB_DO_SETD0PID1_M;
-        }
+    uint8_t eptype = (in_ep[epnum].diepctl & USB_D_EPTYPE1_M) >> USB_D_EPTYPE1_S;
+    // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt
+    // and bulk endpoints.
+    if (eptype == 2 || eptype == 3) {
+      in_ep[epnum].diepctl |= USB_DI_SETD0PID1_M;
+    }
+  } else {
+    out_ep[epnum].doepctl &= ~USB_STALL1_M;
+
+    uint8_t eptype = (out_ep[epnum].doepctl & USB_EPTYPE1_M) >> USB_EPTYPE1_S;
+    // Required by USB spec to reset DATA toggle bit to DATA0 on interrupt
+    // and bulk endpoints.
+    if (eptype == 2 || eptype == 3) {
+      out_ep[epnum].doepctl |= USB_DO_SETD0PID1_M;
     }
+  }
 }
 
 /*------------------------------------------------------------------*/
 
 static void receive_packet(xfer_ctl_t *xfer, /* usb_out_endpoint_t * out_ep, */ uint16_t xfer_size)
 {
-    ESP_EARLY_LOGV(TAG, "USB - receive_packet");
-    volatile uint32_t *rx_fifo = USB0.fifo[0];
-
-    // See above TODO
-    // uint16_t remaining = (out_ep->DOEPTSIZ & UsbDOEPTSIZ_XFRSIZ_Msk) >> UsbDOEPTSIZ_XFRSIZ_Pos;
-    // xfer->queued_len = xfer->total_len - remaining;
-
-    uint16_t remaining = xfer->total_len - xfer->queued_len;
-    uint16_t to_recv_size;
-
-    if (remaining <= xfer->max_size) {
-        // Avoid buffer overflow.
-        to_recv_size = (xfer_size > remaining) ? remaining : xfer_size;
-    } else {
-        // Room for full packet, choose recv_size based on what the microcontroller
-        // claims.
-        to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size;
-    }
-
-    uint8_t to_recv_rem = to_recv_size % 4;
-    uint16_t to_recv_size_aligned = to_recv_size - to_recv_rem;
-
-    // Do not assume xfer buffer is aligned.
-    uint8_t *base = (xfer->buffer + xfer->queued_len);
-
-    // This for loop always runs at least once- skip if less than 4 bytes
-    // to collect.
-    if (to_recv_size >= 4) {
-        for (uint16_t i = 0; i < to_recv_size_aligned; i += 4) {
-            uint32_t tmp = (*rx_fifo);
-            base[i] = tmp & 0x000000FF;
-            base[i + 1] = (tmp & 0x0000FF00) >> 8;
-            base[i + 2] = (tmp & 0x00FF0000) >> 16;
-            base[i + 3] = (tmp & 0xFF000000) >> 24;
-        }
+  ESP_EARLY_LOGV(TAG, "USB - receive_packet");
+  volatile uint32_t *rx_fifo = USB0.fifo[0];
+
+  // See above TODO
+  // uint16_t remaining = (out_ep->DOEPTSIZ & UsbDOEPTSIZ_XFRSIZ_Msk) >> UsbDOEPTSIZ_XFRSIZ_Pos;
+  // xfer->queued_len = xfer->total_len - remaining;
+
+  uint16_t remaining = xfer->total_len - xfer->queued_len;
+  uint16_t to_recv_size;
+
+  if (remaining <= xfer->max_size) {
+    // Avoid buffer overflow.
+    to_recv_size = (xfer_size > remaining) ? remaining : xfer_size;
+  } else {
+    // Room for full packet, choose recv_size based on what the microcontroller
+    // claims.
+    to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size;
+  }
+
+  uint8_t to_recv_rem = to_recv_size % 4;
+  uint16_t to_recv_size_aligned = to_recv_size - to_recv_rem;
+
+  // Do not assume xfer buffer is aligned.
+  uint8_t *base = (xfer->buffer + xfer->queued_len);
+
+  // This for loop always runs at least once- skip if less than 4 bytes
+  // to collect.
+  if (to_recv_size >= 4) {
+    for (uint16_t i = 0; i < to_recv_size_aligned; i += 4) {
+      uint32_t tmp = (*rx_fifo);
+      base[i] = tmp & 0x000000FF;
+      base[i + 1] = (tmp & 0x0000FF00) >> 8;
+      base[i + 2] = (tmp & 0x00FF0000) >> 16;
+      base[i + 3] = (tmp & 0xFF000000) >> 24;
     }
+  }
 
-    // Do not read invalid bytes from RX FIFO.
-    if (to_recv_rem != 0) {
-        uint32_t tmp = (*rx_fifo);
-        uint8_t *last_32b_bound = base + to_recv_size_aligned;
+  // Do not read invalid bytes from RX FIFO.
+  if (to_recv_rem != 0) {
+    uint32_t tmp = (*rx_fifo);
+    uint8_t *last_32b_bound = base + to_recv_size_aligned;
 
-        last_32b_bound[0] = tmp & 0x000000FF;
-        if (to_recv_rem > 1) {
-            last_32b_bound[1] = (tmp & 0x0000FF00) >> 8;
-        }
-        if (to_recv_rem > 2) {
-            last_32b_bound[2] = (tmp & 0x00FF0000) >> 16;
-        }
+    last_32b_bound[0] = tmp & 0x000000FF;
+    if (to_recv_rem > 1) {
+      last_32b_bound[1] = (tmp & 0x0000FF00) >> 8;
     }
+    if (to_recv_rem > 2) {
+      last_32b_bound[2] = (tmp & 0x00FF0000) >> 16;
+    }
+  }
 
-    xfer->queued_len += xfer_size;
+  xfer->queued_len += xfer_size;
 
-    // Per USB spec, a short OUT packet (including length 0) is always
-    // indicative of the end of a transfer (at least for ctl, bulk, int).
-    xfer->short_packet = (xfer_size < xfer->max_size);
+  // Per USB spec, a short OUT packet (including length 0) is always
+  // indicative of the end of a transfer (at least for ctl, bulk, int).
+  xfer->short_packet = (xfer_size < xfer->max_size);
 }
 
 static void transmit_packet(xfer_ctl_t *xfer, volatile usb_in_endpoint_t *in_ep, uint8_t fifo_num)
 {
-    ESP_EARLY_LOGV(TAG, "USB - transmit_packet");
-    volatile uint32_t *tx_fifo = USB0.fifo[fifo_num];
-
-    uint16_t remaining = (in_ep->dieptsiz & 0x7FFFFU) >> USB_D_XFERSIZE0_S;
-    xfer->queued_len = xfer->total_len - remaining;
-
-    uint16_t to_xfer_size = (remaining > xfer->max_size) ? xfer->max_size : remaining;
-    uint8_t to_xfer_rem = to_xfer_size % 4;
-    uint16_t to_xfer_size_aligned = to_xfer_size - to_xfer_rem;
-
-    // Buffer might not be aligned to 32b, so we need to force alignment
-    // by copying to a temp var.
-    uint8_t *base = (xfer->buffer + xfer->queued_len);
-
-    // This for loop always runs at least once- skip if less than 4 bytes
-    // to send off.
-    if (to_xfer_size >= 4) {
-        for (uint16_t i = 0; i < to_xfer_size_aligned; i += 4) {
-            uint32_t tmp = base[i] | (base[i + 1] << 8) |
-                           (base[i + 2] << 16) | (base[i + 3] << 24);
-            (*tx_fifo) = tmp;
-        }
+  ESP_EARLY_LOGV(TAG, "USB - transmit_packet");
+  volatile uint32_t *tx_fifo = USB0.fifo[fifo_num];
+
+  uint16_t remaining = (in_ep->dieptsiz & 0x7FFFFU) >> USB_D_XFERSIZE0_S;
+  xfer->queued_len = xfer->total_len - remaining;
+
+  uint16_t to_xfer_size = (remaining > xfer->max_size) ? xfer->max_size : remaining;
+  uint8_t to_xfer_rem = to_xfer_size % 4;
+  uint16_t to_xfer_size_aligned = to_xfer_size - to_xfer_rem;
+
+  // Buffer might not be aligned to 32b, so we need to force alignment
+  // by copying to a temp var.
+  uint8_t *base = (xfer->buffer + xfer->queued_len);
+
+  // This for loop always runs at least once- skip if less than 4 bytes
+  // to send off.
+  if (to_xfer_size >= 4) {
+    for (uint16_t i = 0; i < to_xfer_size_aligned; i += 4) {
+      uint32_t tmp = base[i] | (base[i + 1] << 8) |
+          (base[i + 2] << 16) | (base[i + 3] << 24);
+      (*tx_fifo) = tmp;
     }
+  }
 
-    // Do not read beyond end of buffer if not divisible by 4.
-    if (to_xfer_rem != 0) {
-        uint32_t tmp = 0;
-        uint8_t *last_32b_bound = base + to_xfer_size_aligned;
+  // Do not read beyond end of buffer if not divisible by 4.
+  if (to_xfer_rem != 0) {
+    uint32_t tmp = 0;
+    uint8_t *last_32b_bound = base + to_xfer_size_aligned;
 
-        tmp |= last_32b_bound[0];
-        if (to_xfer_rem > 1) {
-            tmp |= (last_32b_bound[1] << 8);
-        }
-        if (to_xfer_rem > 2) {
-            tmp |= (last_32b_bound[2] << 16);
-        }
-
-        (*tx_fifo) = tmp;
+    tmp |= last_32b_bound[0];
+    if (to_xfer_rem > 1) {
+      tmp |= (last_32b_bound[1] << 8);
+    }
+    if (to_xfer_rem > 2) {
+      tmp |= (last_32b_bound[2] << 16);
     }
+
+    (*tx_fifo) = tmp;
+  }
 }
 
 static void read_rx_fifo(void)
 {
-    // Pop control word off FIFO (completed xfers will have 2 control words,
-    // we only pop one ctl word each interrupt).
-    uint32_t const ctl_word = USB0.grxstsp;
-    uint8_t  const pktsts   = (ctl_word & USB_PKTSTS_M) >> USB_PKTSTS_S;
-    uint8_t  const epnum    = (ctl_word & USB_CHNUM_M ) >> USB_CHNUM_S;
-    uint16_t const bcnt     = (ctl_word & USB_BCNT_M  ) >> USB_BCNT_S;
-
-    switch (pktsts) {
-      case 0x01: // Global OUT NAK (Interrupt)
-        ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Global OUT NAK");
-        break;
-
-      case 0x02: { // Out packet recvd
-        ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet");
-        xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
-        receive_packet(xfer, bcnt);
-      }
+  // Pop control word off FIFO (completed xfers will have 2 control words,
+  // we only pop one ctl word each interrupt).
+  uint32_t const ctl_word = USB0.grxstsp;
+  uint8_t  const pktsts   = (ctl_word & USB_PKTSTS_M) >> USB_PKTSTS_S;
+  uint8_t  const epnum    = (ctl_word & USB_CHNUM_M ) >> USB_CHNUM_S;
+  uint16_t const bcnt     = (ctl_word & USB_BCNT_M  ) >> USB_BCNT_S;
+
+  switch (pktsts) {
+    case 0x01: // Global OUT NAK (Interrupt)
+      ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Global OUT NAK");
       break;
 
-      case 0x03: // Out packet done (Interrupt)
-        ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet done");
-        break;
+    case 0x02: { // Out packet recvd
+      ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet");
+      xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, TUSB_DIR_OUT);
+      receive_packet(xfer, bcnt);
+    }
+    break;
 
-      case 0x04: // Step 2: Setup transaction completed (Interrupt)
-        // After this event, OEPINT interrupt will occur with SETUP bit set
-        ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet done");
-        USB0.out_ep_reg[epnum].doeptsiz |= USB_SUPCNT0_M;
-        break;
+    case 0x03: // Out packet done (Interrupt)
+      ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX type : Out packet done");
+      break;
 
-      case 0x06: { // Step1: Setup data packet received
-        volatile uint32_t *rx_fifo = USB0.fifo[0];
+    case 0x04: // Step 2: Setup transaction completed (Interrupt)
+      // After this event, OEPINT interrupt will occur with SETUP bit set
+      ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet done");
+      USB0.out_ep_reg[epnum].doeptsiz |= USB_SUPCNT0_M;
+      break;
 
-        // We can receive up to three setup packets in succession, but
-        // only the last one is valid. Therefore we just overwrite it
-        _setup_packet[0] = (*rx_fifo);
-        _setup_packet[1] = (*rx_fifo);
+    case 0x06: { // Step1: Setup data packet received
+      volatile uint32_t *rx_fifo = USB0.fifo[0];
 
-        ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet : 0x%08x 0x%08x", _setup_packet[0], _setup_packet[1]);
-      }
-      break;
+      // We can receive up to three setup packets in succession, but
+      // only the last one is valid. Therefore we just overwrite it
+      _setup_packet[0] = (*rx_fifo);
+      _setup_packet[1] = (*rx_fifo);
 
-      default: // Invalid, do something here, like breakpoint?
-        TU_BREAKPOINT();
-        break;
+      ESP_EARLY_LOGV(TAG, "TUSB IRQ - RX : Setup packet : 0x%08x 0x%08x", _setup_packet[0], _setup_packet[1]);
     }
+    break;
+
+    default: // Invalid, do something here, like breakpoint?
+      TU_BREAKPOINT();
+      break;
+  }
 }
 
 static void handle_epout_ints(void)
 {
-    // GINTSTS will be cleared with DAINT == 0
-    // DAINT for a given EP clears when DOEPINTx is cleared.
-    // DOEPINT will be cleared when DAINT's out bits are cleared.
-    for (int n = 0; n < USB_OUT_EP_NUM; n++) {
-        xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
-
-        if (USB0.daint & (1 << (16 + n))) {
-            // SETUP packet Setup Phase done.
-            if ((USB0.out_ep_reg[n].doepint & USB_SETUP0_M)) {
-                USB0.out_ep_reg[n].doepint = USB_STUPPKTRCVD0_M | USB_SETUP0_M; // clear
-                dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true);
-            }
-
-            // OUT XFER complete (single packet).q
-            if (USB0.out_ep_reg[n].doepint & USB_XFERCOMPL0_M) {
-
-                ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP OUT - XFER complete (single packet)");
-                USB0.out_ep_reg[n].doepint = USB_XFERCOMPL0_M;
-
-                // Transfer complete if short packet or total len is transferred
-                if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
-                    xfer->short_packet = false;
-                    dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true);
-                } else {
-                    // Schedule another packet to be received.
-                    USB0.out_ep_reg[n].doeptsiz = USB_PKTCNT0_M |
-                                                  ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S);
-                    USB0.out_ep_reg[n].doepctl |= USB_EPENA0_M | USB_CNAK0_M;
-                }
-            }
+  // GINTSTS will be cleared with DAINT == 0
+  // DAINT for a given EP clears when DOEPINTx is cleared.
+  // DOEPINT will be cleared when DAINT's out bits are cleared.
+  for (int n = 0; n < USB_OUT_EP_NUM; n++) {
+    xfer_ctl_t *xfer = XFER_CTL_BASE(n, TUSB_DIR_OUT);
+
+    if (USB0.daint & (1 << (16 + n))) {
+      // SETUP packet Setup Phase done.
+      if ((USB0.out_ep_reg[n].doepint & USB_SETUP0_M)) {
+        USB0.out_ep_reg[n].doepint = USB_STUPPKTRCVD0_M | USB_SETUP0_M; // clear
+        dcd_event_setup_received(0, (uint8_t *)&_setup_packet[0], true);
+      }
+
+      // OUT XFER complete (single packet).q
+      if (USB0.out_ep_reg[n].doepint & USB_XFERCOMPL0_M) {
+
+        ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP OUT - XFER complete (single packet)");
+        USB0.out_ep_reg[n].doepint = USB_XFERCOMPL0_M;
+
+        // Transfer complete if short packet or total len is transferred
+        if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) {
+          xfer->short_packet = false;
+          dcd_event_xfer_complete(0, n, xfer->queued_len, XFER_RESULT_SUCCESS, true);
+        } else {
+          // Schedule another packet to be received.
+          USB0.out_ep_reg[n].doeptsiz = USB_PKTCNT0_M |
+              ((xfer->max_size & USB_XFERSIZE0_V) << USB_XFERSIZE0_S);
+          USB0.out_ep_reg[n].doepctl |= USB_EPENA0_M | USB_CNAK0_M;
         }
+      }
     }
+  }
 }
 
 static void handle_epin_ints(void)
 {
+  // GINTSTS will be cleared with DAINT == 0
+  // DAINT for a given EP clears when DIEPINTx is cleared.
+  // IEPINT will be cleared when DAINT's out bits are cleared.
+  for (uint32_t n = 0; n < USB_IN_EP_NUM; n++) {
+    xfer_ctl_t *xfer = &xfer_status[n][TUSB_DIR_IN];
+
+    if (USB0.daint & (1 << (0 + n))) {
+      ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP IN %u", n);
+      // IN XFER complete (entire xfer).
+      if (USB0.in_ep_reg[n].diepint & USB_D_XFERCOMPL0_M) {
+        ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER complete!");
+        USB0.in_ep_reg[n].diepint = USB_D_XFERCOMPL0_M;
+        USB0.dtknqr4_fifoemptymsk &= ~(1 << n); // Turn off TXFE b/c xfer inactive.
+        dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
+      }
 
-    // GINTSTS will be cleared with DAINT == 0
-    // DAINT for a given EP clears when DIEPINTx is cleared.
-    // IEPINT will be cleared when DAINT's out bits are cleared.
-    for (uint32_t n = 0; n < USB_IN_EP_NUM; n++) {
-        xfer_ctl_t *xfer = &xfer_status[n][TUSB_DIR_IN];
-
-        if (USB0.daint & (1 << (0 + n))) {
-            ESP_EARLY_LOGV(TAG, "TUSB IRQ - EP IN %u", n);
-            // IN XFER complete (entire xfer).
-            if (USB0.in_ep_reg[n].diepint & USB_D_XFERCOMPL0_M) {
-                ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER complete!");
-                USB0.in_ep_reg[n].diepint = USB_D_XFERCOMPL0_M;
-                USB0.dtknqr4_fifoemptymsk &= ~(1 << n); // Turn off TXFE b/c xfer inactive.
-                dcd_event_xfer_complete(0, n | TUSB_DIR_IN_MASK, xfer->total_len, XFER_RESULT_SUCCESS, true);
-            }
-
-            // XFER FIFO empty
-            if (USB0.in_ep_reg[n].diepint & USB_D_TXFEMP0_M) {
-                ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER FIFO empty!");
-                USB0.in_ep_reg[n].diepint = USB_D_TXFEMP0_M;
-                transmit_packet(xfer, &USB0.in_ep_reg[n], n);
-            }
-        }
+      // XFER FIFO empty
+      if (USB0.in_ep_reg[n].diepint & USB_D_TXFEMP0_M) {
+        ESP_EARLY_LOGV(TAG, "TUSB IRQ - IN XFER FIFO empty!");
+        USB0.in_ep_reg[n].diepint = USB_D_TXFEMP0_M;
+        transmit_packet(xfer, &USB0.in_ep_reg[n], n);
+      }
     }
+  }
 }
 
 
 void dcd_irq_handler(uint32_t rhport)
 {
-    (void) rhport;
-
-    const uint32_t int_status = USB0.gintsts;
-    //const uint32_t int_msk = USB0.gintmsk;
-
-    if (int_status & USB_DISCONNINT_M) {
-        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - disconnected");
-        USB0.gintsts = USB_DISCONNINT_M;
-        dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
-    }
-
-    if (int_status & USB_USBRST_M) {
-        // start of reset
-        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset");
-        USB0.gintsts = USB_USBRST_M;
-        bus_reset();
-    }
-
-    if (int_status & USB_RESETDET_M) {
-        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset while suspend");
-        USB0.gintsts = USB_RESETDET_M;
-        bus_reset();
-    }
-
-    if (int_status & USB_ENUMDONE_M) {
-        // ENUMDNE detects speed of the link. For full-speed, we
-        // always expect the same value. This interrupt is considered
-        // the end of reset.
-        USB0.gintsts = USB_ENUMDONE_M;
-        enum_done_processing();
-        dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
-    }
+  (void) rhport;
+
+  const uint32_t int_status = USB0.gintsts;
+  //const uint32_t int_msk = USB0.gintmsk;
+
+  if (int_status & USB_DISCONNINT_M) {
+    ESP_EARLY_LOGV(TAG, "dcd_irq_handler - disconnected");
+    USB0.gintsts = USB_DISCONNINT_M;
+    dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
+  }
+
+  if (int_status & USB_USBRST_M) {
+    // start of reset
+    ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset");
+    USB0.gintsts = USB_USBRST_M;
+    bus_reset();
+  }
+
+  if (int_status & USB_RESETDET_M) {
+    ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset while suspend");
+    USB0.gintsts = USB_RESETDET_M;
+    bus_reset();
+  }
+
+  if (int_status & USB_ENUMDONE_M) {
+    // ENUMDNE detects speed of the link. For full-speed, we
+    // always expect the same value. This interrupt is considered
+    // the end of reset.
+    USB0.gintsts = USB_ENUMDONE_M;
+    enum_done_processing();
+    dcd_event_bus_signal(0, DCD_EVENT_BUS_RESET, true);
+  }
 
 #if USE_SOF
-    if (int_status & USB_SOF_M) {
-        USB0.gintsts = USB_SOF_M;
-        dcd_event_bus_signal(0, DCD_EVENT_SOF, true); // do nothing actually
-    }
+  if (int_status & USB_SOF_M) {
+    USB0.gintsts = USB_SOF_M;
+    dcd_event_bus_signal(0, DCD_EVENT_SOF, true); // do nothing actually
+  }
 #endif
 
-    if ((int_status & USB_RXFLVI_M) /*& (int_msk & USB_RXFLVIMSK_M)*/) {
-        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - rx!");
-        USB0.gintmsk &= ~USB_RXFLVIMSK_M;
-        read_rx_fifo();
-        USB0.gintmsk |= USB_RXFLVIMSK_M;
-        USB0.gintsts = USB_RXFLVI_M;
-    }
-
-    // OUT endpoint interrupt handling.
-    if (int_status & USB_OEPINT_M) {
-        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - OUT endpoint!");
-        handle_epout_ints();
-    }
-
-    // IN endpoint interrupt handling.
-    if (int_status & USB_IEPINT_M) {
-        ESP_EARLY_LOGV(TAG, "dcd_irq_handler - IN endpoint!");
-        handle_epin_ints();
-    }
-
-    // Without handling
-    USB0.gintsts |= USB_CURMOD_INT_M |
-                    USB_MODEMIS_M |
-                    USB_OTGINT_M |
-                    USB_NPTXFEMP_M |
-                    USB_GINNAKEFF_M |
-                    USB_GOUTNAKEFF |
-                    USB_ERLYSUSP_M |
-                    USB_USBSUSP_M |
-                    USB_ISOOUTDROP_M |
-                    USB_EOPF_M |
-                    USB_EPMIS_M |
-                    USB_INCOMPISOIN_M |
-                    USB_INCOMPIP_M |
-                    USB_FETSUSP_M |
-                    USB_PTXFEMP_M;
+  if (int_status & USB_RXFLVI_M) {
+    ESP_EARLY_LOGV(TAG, "dcd_irq_handler - rx!");
+
+    // disable RXFLVI interrupt until we read data from FIFO
+    USB0.gintmsk &= ~USB_RXFLVIMSK_M;
+
+    read_rx_fifo();
+
+    // re-enable RXFLVI
+    USB0.gintmsk |= USB_RXFLVIMSK_M;
+
+    USB0.gintsts = USB_RXFLVI_M;
+  }
+
+  // OUT endpoint interrupt handling.
+  if (int_status & USB_OEPINT_M) {
+    ESP_EARLY_LOGV(TAG, "dcd_irq_handler - OUT endpoint!");
+    handle_epout_ints();
+  }
+
+  // IN endpoint interrupt handling.
+  if (int_status & USB_IEPINT_M) {
+    ESP_EARLY_LOGV(TAG, "dcd_irq_handler - IN endpoint!");
+    handle_epin_ints();
+  }
+
+  // Without handling
+  USB0.gintsts |= USB_CURMOD_INT_M  |
+                  USB_MODEMIS_M     |
+                  USB_OTGINT_M      |
+                  USB_NPTXFEMP_M    |
+                  USB_GINNAKEFF_M   |
+                  USB_GOUTNAKEFF    |
+                  USB_ERLYSUSP_M    |
+                  USB_USBSUSP_M     |
+                  USB_ISOOUTDROP_M  |
+                  USB_EOPF_M        |
+                  USB_EPMIS_M       |
+                  USB_INCOMPISOIN_M |
+                  USB_INCOMPIP_M    |
+                  USB_FETSUSP_M     |
+                  USB_PTXFEMP_M;
 }
 
-void dcd_int_enable(uint8_t rhport)
+void dcd_int_enable (uint8_t rhport)
 {
-    (void)rhport;
-    esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t)dcd_irq_handler, NULL, &usb_ih);
+  (void) rhport;
+  esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t) dcd_irq_handler, NULL, &usb_ih);
 }
 
-void dcd_int_disable(uint8_t rhport)
+void dcd_int_disable (uint8_t rhport)
 {
-    (void)rhport;
-    esp_intr_free(usb_ih);
+  (void) rhport;
+  esp_intr_free(usb_ih);
 }
 
 #endif // OPT_MCU_ESP32S2
-- 
cgit v1.3.1


From c0695b4b55ba0a01117d7e9f544735c117fcb14b Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Apr 2020 15:13:12 +0700
Subject: clear USB_RXFLVI_M before read_rx_fifo()

more format clean up
---
 src/portable/espressif/esp32s2/dcd_esp32s2.c | 21 +++++++--------------
 1 file changed, 7 insertions(+), 14 deletions(-)

(limited to 'src')

diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c
index e0a2c2454..d34e1c123 100644
--- a/src/portable/espressif/esp32s2/dcd_esp32s2.c
+++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c
@@ -362,22 +362,18 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
     } else {
       // Stop transmitting packets and NAK IN xfers.
       in_ep[epnum].diepctl |= USB_DI_SNAK1_M;
-      while ((in_ep[epnum].diepint & USB_DI_SNAK1_M) == 0)
-        ;
+      while ((in_ep[epnum].diepint & USB_DI_SNAK1_M) == 0) ;
 
       // Disable the endpoint. Note that both SNAK and STALL are set here.
-      in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M |
-          USB_D_EPDIS1_M);
-      while ((in_ep[epnum].diepint & USB_D_EPDISBLD0_M) == 0)
-        ;
+      in_ep[epnum].diepctl |= (USB_DI_SNAK1_M | USB_D_STALL1_M | USB_D_EPDIS1_M);
+      while ((in_ep[epnum].diepint & USB_D_EPDISBLD0_M) == 0) ;
       in_ep[epnum].diepint = USB_D_EPDISBLD0_M;
     }
 
     // Flush the FIFO, and wait until we have confirmed it cleared.
     USB0.grstctl |= ((epnum - 1) << USB_TXFNUM_S);
     USB0.grstctl |= USB_TXFFLSH_M;
-    while ((USB0.grstctl & USB_TXFFLSH_M) != 0)
-      ;
+    while ((USB0.grstctl & USB_TXFFLSH_M) != 0) ;
   } else {
     // Only disable currently enabled non-control endpoint
     if ((epnum == 0) || !(out_ep[epnum].doepctl & USB_EPENA0_M)) {
@@ -388,14 +384,12 @@ void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
       // anyway, and it can't be cleared by user code. If this while loop never
       // finishes, we have bigger problems than just the stack.
       USB0.dctl |= USB_SGOUTNAK_M;
-      while ((USB0.gintsts & USB_GOUTNAKEFF_M) == 0)
-        ;
+      while ((USB0.gintsts & USB_GOUTNAKEFF_M) == 0) ;
 
       // Ditto here- disable the endpoint. Note that only STALL and not SNAK
       // is set here.
       out_ep[epnum].doepctl |= (USB_STALL0_M | USB_EPDIS0_M);
-      while ((out_ep[epnum].doepint & USB_EPDISBLD0_M) == 0)
-        ;
+      while ((out_ep[epnum].doepint & USB_EPDISBLD0_M) == 0) ;
       out_ep[epnum].doepint = USB_EPDISBLD0_M;
 
       // Allow other OUT endpoints to keep receiving.
@@ -698,6 +692,7 @@ void dcd_irq_handler(uint32_t rhport)
 
   if (int_status & USB_RXFLVI_M) {
     ESP_EARLY_LOGV(TAG, "dcd_irq_handler - rx!");
+    USB0.gintsts = USB_RXFLVI_M;
 
     // disable RXFLVI interrupt until we read data from FIFO
     USB0.gintmsk &= ~USB_RXFLVIMSK_M;
@@ -706,8 +701,6 @@ void dcd_irq_handler(uint32_t rhport)
 
     // re-enable RXFLVI
     USB0.gintmsk |= USB_RXFLVIMSK_M;
-
-    USB0.gintsts = USB_RXFLVI_M;
   }
 
   // OUT endpoint interrupt handling.
-- 
cgit v1.3.1


From 30945ab9f3f7c96725e1cabbe084836b48a113b5 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Apr 2020 15:27:23 +0700
Subject: revert name to dcd_int_handler due to function prototype warning

---
 src/portable/espressif/esp32s2/dcd_esp32s2.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

(limited to 'src')

diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c
index d34e1c123..328ec2fb9 100644
--- a/src/portable/espressif/esp32s2/dcd_esp32s2.c
+++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c
@@ -123,7 +123,7 @@ static void bus_reset(void)
 
 static void enum_done_processing(void)
 {
-  ESP_EARLY_LOGV(TAG, "dcd_irq_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then");
+  ESP_EARLY_LOGV(TAG, "dcd_int_handler - Speed enumeration done! Sending DCD_EVENT_BUS_RESET then");
   // On current silicon on the Full Speed core, speed is fixed to Full Speed.
   // However, keep for debugging and in case Low Speed is ever supported.
   uint32_t enum_spd = (USB0.dsts >> USB_ENUMSPD_S) & (USB_ENUMSPD_V);
@@ -648,28 +648,28 @@ static void handle_epin_ints(void)
 }
 
 
-void dcd_irq_handler(uint32_t rhport)
+static void dcd_int_handler(void* arg)
 {
-  (void) rhport;
+  (void) arg;
 
   const uint32_t int_status = USB0.gintsts;
   //const uint32_t int_msk = USB0.gintmsk;
 
   if (int_status & USB_DISCONNINT_M) {
-    ESP_EARLY_LOGV(TAG, "dcd_irq_handler - disconnected");
+    ESP_EARLY_LOGV(TAG, "dcd_int_handler - disconnected");
     USB0.gintsts = USB_DISCONNINT_M;
     dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
   }
 
   if (int_status & USB_USBRST_M) {
     // start of reset
-    ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset");
+    ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset");
     USB0.gintsts = USB_USBRST_M;
     bus_reset();
   }
 
   if (int_status & USB_RESETDET_M) {
-    ESP_EARLY_LOGV(TAG, "dcd_irq_handler - reset while suspend");
+    ESP_EARLY_LOGV(TAG, "dcd_int_handler - reset while suspend");
     USB0.gintsts = USB_RESETDET_M;
     bus_reset();
   }
@@ -691,7 +691,7 @@ void dcd_irq_handler(uint32_t rhport)
 #endif
 
   if (int_status & USB_RXFLVI_M) {
-    ESP_EARLY_LOGV(TAG, "dcd_irq_handler - rx!");
+    ESP_EARLY_LOGV(TAG, "dcd_int_handler - rx!");
     USB0.gintsts = USB_RXFLVI_M;
 
     // disable RXFLVI interrupt until we read data from FIFO
@@ -705,13 +705,13 @@ void dcd_irq_handler(uint32_t rhport)
 
   // OUT endpoint interrupt handling.
   if (int_status & USB_OEPINT_M) {
-    ESP_EARLY_LOGV(TAG, "dcd_irq_handler - OUT endpoint!");
+    ESP_EARLY_LOGV(TAG, "dcd_int_handler - OUT endpoint!");
     handle_epout_ints();
   }
 
   // IN endpoint interrupt handling.
   if (int_status & USB_IEPINT_M) {
-    ESP_EARLY_LOGV(TAG, "dcd_irq_handler - IN endpoint!");
+    ESP_EARLY_LOGV(TAG, "dcd_int_handler - IN endpoint!");
     handle_epin_ints();
   }
 
@@ -736,7 +736,7 @@ void dcd_irq_handler(uint32_t rhport)
 void dcd_int_enable (uint8_t rhport)
 {
   (void) rhport;
-  esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t) dcd_irq_handler, NULL, &usb_ih);
+  esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LOWMED, (intr_handler_t) dcd_int_handler, NULL, &usb_ih);
 }
 
 void dcd_int_disable (uint8_t rhport)
-- 
cgit v1.3.1


From 978eec73b350ae5a52e47036c0dec163172944fa Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Apr 2020 15:39:59 +0700
Subject: remove 100us delay at the end of dcd_init()

---
 src/portable/espressif/esp32s2/dcd_esp32s2.c | 2 --
 1 file changed, 2 deletions(-)

(limited to 'src')

diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c
index 328ec2fb9..26895c204 100644
--- a/src/portable/espressif/esp32s2/dcd_esp32s2.c
+++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c
@@ -198,8 +198,6 @@ void dcd_init(uint8_t rhport)
 
   ESP_LOGV(TAG, "DCD init - Soft CONNECT");
   USB0.dctl &= ~USB_SFTDISCON_M; // Connect
-
-  ets_delay_us(100);
 }
 
 void dcd_set_address(uint8_t rhport, uint8_t dev_addr)
-- 
cgit v1.3.1


From c545cfc0bc9c4828c4b60515014386f770622166 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Apr 2020 15:42:50 +0700
Subject: Correct dedicated FIFO SRAM size to 1024

add note for up to 5 active IN endpoints (including EP0 IN)
---
 src/portable/espressif/esp32s2/dcd_esp32s2.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c
index 26895c204..099f3af3e 100644
--- a/src/portable/espressif/esp32s2/dcd_esp32s2.c
+++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c
@@ -46,9 +46,13 @@
 // We disable SOF for now until needed later on
 #define USE_SOF     0
 
-// FIFO size in bytes TODO need confirmation from Espressif
+// Max number of bi-directional endpoints including EP0
+// Note: ESP32S2 specs say there are only up to 5 IN active endpoints include EP0
+// We should probably prohibit enabling Endpoint IN > 4 (not done yet)
 #define EP_MAX            USB_OUT_EP_NUM
-#define EP_FIFO_SIZE      1280
+
+// FIFO size in bytes
+#define EP_FIFO_SIZE      1024
 
 typedef struct {
     uint8_t *buffer;
-- 
cgit v1.3.1


From 8953bc9255712cace4eb3e66b1e89961952bb639 Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Apr 2020 20:25:53 +0700
Subject: added comment note for beta chip walkaround

---
 src/portable/espressif/esp32s2/dcd_esp32s2.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c
index 099f3af3e..d1e670358 100644
--- a/src/portable/espressif/esp32s2/dcd_esp32s2.c
+++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c
@@ -170,7 +170,17 @@ void dcd_init(uint8_t rhport)
   USB0.gusbcfg |= USB_FORCEDEVMODE_M;                    // force devmode
 
   USB0.gotgctl &= ~(USB_BVALIDOVVAL_M | USB_BVALIDOVEN_M | USB_VBVALIDOVVAL_M); //no overrides
-#ifdef CONFIG_IDF_TARGET_ESP32S2BETA // needed for beta chip only
+
+#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
+  // needed for beta chip only
+  // there was a bug in the phy logic that made the chip reset as soon as it transmitted anything.
+  // Setting the B override value made it ignore resets (any resets, generated by the faulty logic or not),
+  // which 'fixed' the problem well enough to test usb with it.
+  // Also, do note that the beta silicon run was very small and software support for it is not in mainstream esp-idf,
+  // as such you may consider phasing out support for it alltogether somewhere in the future
+
+  // TODO we could safely remove this later (maybe after 2020)
+
   //C. chip 7.2.2 hack
   ESP_LOGV(TAG, "DCD init - chip ESP32-S2 beta hack");
   USB0.gotgctl = (0 << USB_BVALIDOVVAL_S); //B override value
-- 
cgit v1.3.1


From a37a56acd3ca70e0330d68da866d56faf00e82ce Mon Sep 17 00:00:00 2001
From: hathach <thach@tinyusb.org>
Date: Fri, 10 Apr 2020 23:38:36 +0700
Subject: remove CONFIG_IDF_TARGET_ESP32S2BETA per review

---
 src/portable/espressif/esp32s2/dcd_esp32s2.c | 19 -------------------
 1 file changed, 19 deletions(-)

(limited to 'src')

diff --git a/src/portable/espressif/esp32s2/dcd_esp32s2.c b/src/portable/espressif/esp32s2/dcd_esp32s2.c
index d1e670358..de9ef6b6d 100644
--- a/src/portable/espressif/esp32s2/dcd_esp32s2.c
+++ b/src/portable/espressif/esp32s2/dcd_esp32s2.c
@@ -168,27 +168,8 @@ void dcd_init(uint8_t rhport)
 
   USB0.gahbcfg |= USB_NPTXFEMPLVL_M | USB_GLBLLNTRMSK_M; // Global interruptions ON
   USB0.gusbcfg |= USB_FORCEDEVMODE_M;                    // force devmode
-
   USB0.gotgctl &= ~(USB_BVALIDOVVAL_M | USB_BVALIDOVEN_M | USB_VBVALIDOVVAL_M); //no overrides
 
-#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
-  // needed for beta chip only
-  // there was a bug in the phy logic that made the chip reset as soon as it transmitted anything.
-  // Setting the B override value made it ignore resets (any resets, generated by the faulty logic or not),
-  // which 'fixed' the problem well enough to test usb with it.
-  // Also, do note that the beta silicon run was very small and software support for it is not in mainstream esp-idf,
-  // as such you may consider phasing out support for it alltogether somewhere in the future
-
-  // TODO we could safely remove this later (maybe after 2020)
-
-  //C. chip 7.2.2 hack
-  ESP_LOGV(TAG, "DCD init - chip ESP32-S2 beta hack");
-  USB0.gotgctl = (0 << USB_BVALIDOVVAL_S); //B override value
-  ets_delay_us(20);
-  USB0.gotgctl = (0 << USB_BVALIDOVVAL_S) | (1 << USB_BVALIDOVEN_S); //B override value & enable
-  ets_delay_us(20);
-#endif
-
   // C. Setting SNAKs, then connect
   for (int n = 0; n < USB_OUT_EP_NUM; n++) {
     USB0.out_ep_reg[n].doepctl |= USB_DO_SNAK0_M; // DOEPCTL0_SNAK
-- 
cgit v1.3.1