From 35045e0346f64fe3b19e94c8e9c8d2eb908fc5d6 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Fri, 10 Apr 2026 13:33:13 +0200 Subject: debloat the workaround Signed-off-by: HiFiPhile --- src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c | 2 +- src/portable/st/stm32_fsdev/fsdev_common.h | 37 ----------------- src/portable/st/stm32_fsdev/fsdev_stm32.h | 60 ++++++++++++++++++--------- src/portable/st/stm32_fsdev/hcd_stm32_fsdev.c | 6 +-- 4 files changed, 42 insertions(+), 63 deletions(-) (limited to 'src') diff --git a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c index c8bb0e827..3ef0819bd 100644 --- a/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c @@ -393,7 +393,7 @@ void dcd_int_handler(uint8_t rhport) { const uint32_t ep_reg = ep_read(ep_id); if (ep_reg & U_EP_CTR_RX) { - #ifdef CFG_TUSB_FSDEV_32BIT + #if defined(TUP_USBIP_FSDEV_STM32) && defined(CFG_TUSB_FSDEV_32BIT) fsdev_btable_workaround_delay(false); #endif diff --git a/src/portable/st/stm32_fsdev/fsdev_common.h b/src/portable/st/stm32_fsdev/fsdev_common.h index 95854d63d..140ff1d61 100644 --- a/src/portable/st/stm32_fsdev/fsdev_common.h +++ b/src/portable/st/stm32_fsdev/fsdev_common.h @@ -307,24 +307,6 @@ typedef struct { #error "Unknown USB IP" #endif -#if defined(TUP_USBIP_FSDEV_STM32) && defined(CFG_TUSB_FSDEV_32BIT) - #ifndef CFG_TUSB_FSDEV_BTABLE_FS_DELAY_COUNT - #if defined(FSDEV_STM32_CPU_MHZ) - #define CFG_TUSB_FSDEV_BTABLE_FS_DELAY_COUNT (FSDEV_STM32_CPU_MHZ / 4U) - #else - #error "Define CFG_TUSB_FSDEV_BTABLE_FS_DELAY_COUNT or FSDEV_STM32_CPU_MHZ for STM32 FSDEV 32-bit" - #endif - #endif - - #ifndef CFG_TUSB_FSDEV_BTABLE_LS_DELAY_COUNT - #if defined(FSDEV_STM32_CPU_MHZ) - #define CFG_TUSB_FSDEV_BTABLE_LS_DELAY_COUNT (FSDEV_STM32_CPU_MHZ * 2U) - #else - #error "Define CFG_TUSB_FSDEV_BTABLE_LS_DELAY_COUNT or FSDEV_STM32_CPU_MHZ for STM32 FSDEV 32-bit" - #endif - #endif -#endif - //--------------------------------------------------------------------+ // Endpoint Helper // - CTR is write 0 to clear @@ -467,25 +449,6 @@ uint16_t pma_align_buffer_size(uint16_t size, uint8_t *blsize, uint8_t *num_bloc // Set RX buffer size void btable_set_rx_bufsize(uint32_t ep_id, uint8_t buf_id, uint16_t wCount); -/* STM32 FSDEV PMA Buffer Description Table errata workaround: - * - ES0561 (STM32H503), ES0587 (STM32U535/U545) - * - CTR may trigger before final PMA SRAM accesses complete on OUT transfers. - * - Insert delay before reading PMA count/data. - * - * Low-speed path uses CFG_TUSB_FSDEV_BTABLE_LS_DELAY_COUNT, otherwise full-speed count. - */ -TU_ATTR_ALWAYS_INLINE static inline void fsdev_btable_workaround_delay(bool low_speed) { -#if defined(TUP_USBIP_FSDEV_STM32) && defined(CFG_TUSB_FSDEV_32BIT) - uint32_t cycle_count = low_speed ? CFG_TUSB_FSDEV_BTABLE_LS_DELAY_COUNT : CFG_TUSB_FSDEV_BTABLE_FS_DELAY_COUNT; - volatile uint32_t delay_count = cycle_count; - while (delay_count > 0U) { - delay_count--; - } -#else - (void) low_speed; -#endif -} - #ifdef __cplusplus } #endif diff --git a/src/portable/st/stm32_fsdev/fsdev_stm32.h b/src/portable/st/stm32_fsdev/fsdev_stm32.h index d2a7a6caa..79052b489 100644 --- a/src/portable/st/stm32_fsdev/fsdev_stm32.h +++ b/src/portable/st/stm32_fsdev/fsdev_stm32.h @@ -138,26 +138,6 @@ #error "FSDEV_HAS_SBUF_ISO not defined" #endif -#ifndef FSDEV_STM32_CPU_MHZ - // Max CPU frequency in MHz, used to derive conservative FSDEV PMA delay defaults. - #if CFG_TUSB_MCU == OPT_MCU_STM32H5 - #define FSDEV_STM32_CPU_MHZ 250U - #elif CFG_TUSB_MCU == OPT_MCU_STM32U5 - #define FSDEV_STM32_CPU_MHZ 160U - #elif CFG_TUSB_MCU == OPT_MCU_STM32U3 - #define FSDEV_STM32_CPU_MHZ 96U - #elif CFG_TUSB_MCU == OPT_MCU_STM32U0 - #define FSDEV_STM32_CPU_MHZ 56U - #elif CFG_TUSB_MCU == OPT_MCU_STM32G0 - #define FSDEV_STM32_CPU_MHZ 64U - #elif CFG_TUSB_MCU == OPT_MCU_STM32C0 - #define FSDEV_STM32_CPU_MHZ 48U - #elif defined(CFG_TUSB_FSDEV_32BIT) && \ - (!defined(CFG_TUSB_FSDEV_BTABLE_FS_DELAY_COUNT) || !defined(CFG_TUSB_FSDEV_BTABLE_LS_DELAY_COUNT)) - #error "Define FSDEV_STM32_CPU_MHZ or both CFG_TUSB_FSDEV_BTABLE_{FS,LS}_DELAY_COUNT for this STM32 MCU" - #endif -#endif - #ifndef CFG_TUD_FSDEV_DOUBLE_BUFFERED_ISO_EP // Default configuration for double-buffered isochronous endpoints: // - Enable double buffering on devices with >1KB Packet Memory Area (PMA) @@ -271,6 +251,46 @@ TU_ATTR_ALWAYS_INLINE static inline void fsdev_int_disable(uint8_t rhport) { // CMSIS has a membar after disabling interrupts } +//--------------------------------------------------------------------+ +// STM32 FSDEV PMA Buffer Description Table errata workaround +//--------------------------------------------------------------------+ + +#ifdef CFG_TUSB_FSDEV_32BIT +// ES0561 (STM32H503), ES0587 (STM32U535/U545) +// CTR may trigger before final PMA SRAM accesses complete on OUT transfers. +// Insert delay before reading PMA count/data. +// Max CPU frequency in MHz, used to derive conservative FSDEV PMA delay defaults. +#if CFG_TUSB_MCU == OPT_MCU_STM32H5 + #define FSDEV_STM32_CPU_MHZ 250U +#elif CFG_TUSB_MCU == OPT_MCU_STM32U5 + #define FSDEV_STM32_CPU_MHZ 160U +#elif CFG_TUSB_MCU == OPT_MCU_STM32U3 + #define FSDEV_STM32_CPU_MHZ 96U +#elif CFG_TUSB_MCU == OPT_MCU_STM32U0 + #define FSDEV_STM32_CPU_MHZ 56U +#elif CFG_TUSB_MCU == OPT_MCU_STM32G0 + #define FSDEV_STM32_CPU_MHZ 64U +#elif CFG_TUSB_MCU == OPT_MCU_STM32C0 + #define FSDEV_STM32_CPU_MHZ 48U +#endif + +#ifndef CFG_TUSB_FSDEV_BTABLE_FS_DELAY_COUNT + #define CFG_TUSB_FSDEV_BTABLE_FS_DELAY_COUNT (FSDEV_STM32_CPU_MHZ / 4U) +#endif + +#ifndef CFG_TUSB_FSDEV_BTABLE_LS_DELAY_COUNT + #define CFG_TUSB_FSDEV_BTABLE_LS_DELAY_COUNT (FSDEV_STM32_CPU_MHZ * 2U) +#endif + +TU_ATTR_ALWAYS_INLINE static inline void fsdev_btable_workaround_delay(bool low_speed) { + uint32_t cycle_count = low_speed ? CFG_TUSB_FSDEV_BTABLE_LS_DELAY_COUNT : CFG_TUSB_FSDEV_BTABLE_FS_DELAY_COUNT; + volatile uint32_t delay_count = cycle_count; + while (delay_count > 0U) { + delay_count--; + } +} +#endif + //--------------------------------------------------------------------+ // Connect / Disconnect //--------------------------------------------------------------------+ diff --git a/src/portable/st/stm32_fsdev/hcd_stm32_fsdev.c b/src/portable/st/stm32_fsdev/hcd_stm32_fsdev.c index 18cf302d8..f9201651a 100644 --- a/src/portable/st/stm32_fsdev/hcd_stm32_fsdev.c +++ b/src/portable/st/stm32_fsdev/hcd_stm32_fsdev.c @@ -197,11 +197,7 @@ bool hcd_init(uint8_t rhport, const tusb_rhport_init_t* rh_init) { // If DCON_STAT is already set, the controller sometimes misses the initial connection interrupt if (FSDEV_REG->ISTR & U_ISTR_DCON_STAT) { - // Wait DP/DM stabilize time - volatile uint32_t cycle_count = FSDEV_STM32_CPU_MHZ / 4U; - while (cycle_count > 0U) { - cycle_count--; - } + tusb_time_delay_ms_api(2); port_status_handler(rhport, false); } -- cgit v1.3.1