From ce627f431831e1fbaa3bb7bad35a489b8006b749 Mon Sep 17 00:00:00 2001 From: "denis.krasutski" Date: Fri, 6 Oct 2023 13:04:54 +0300 Subject: feat(ch32f20x): add support of ch32f20x --- src/common/tusb_mcu.h | 4 + src/portable/wch/ch32_usbhs_reg.h | 349 +++++++++++++++++++++++++ src/portable/wch/ch32v307/ch32_usbhs_reg.h | 345 ------------------------- src/portable/wch/ch32v307/dcd_usbhs.c | 391 ----------------------------- src/portable/wch/dcd_ch32_usbhs.c | 391 +++++++++++++++++++++++++++++ src/tusb_option.h | 1 + 6 files changed, 745 insertions(+), 736 deletions(-) create mode 100644 src/portable/wch/ch32_usbhs_reg.h delete mode 100644 src/portable/wch/ch32v307/ch32_usbhs_reg.h delete mode 100644 src/portable/wch/ch32v307/dcd_usbhs.c create mode 100644 src/portable/wch/dcd_ch32_usbhs.c (limited to 'src') diff --git a/src/common/tusb_mcu.h b/src/common/tusb_mcu.h index 8807ff8aa..a72976ae9 100644 --- a/src/common/tusb_mcu.h +++ b/src/common/tusb_mcu.h @@ -383,6 +383,10 @@ #elif TU_CHECK_MCU(OPT_MCU_CH32V307) #define TUP_DCD_ENDPOINT_MAX 16 #define TUP_RHPORT_HIGHSPEED 1 + +#elif TU_CHECK_MCU(OPT_MCU_CH32F20X) + #define TUP_DCD_ENDPOINT_MAX 16 + #define TUP_RHPORT_HIGHSPEED 1 #endif diff --git a/src/portable/wch/ch32_usbhs_reg.h b/src/portable/wch/ch32_usbhs_reg.h new file mode 100644 index 000000000..9b956231f --- /dev/null +++ b/src/portable/wch/ch32_usbhs_reg.h @@ -0,0 +1,349 @@ +#ifndef _USB_CH32_USBHS_REG_H +#define _USB_CH32_USBHS_REG_H + +#if (CFG_TUSB_MCU == OPT_MCU_CH32V307) +#include +#elif (CFG_TUSB_MCU == OPT_MCU_CH32F20X) +#include +#endif + +/******************* GLOBAL ******************/ + +// USB CONTROL +#define USBHS_CONTROL_OFFSET 0x00 +#define USBHS_DMA_EN (1 << 0) +#define USBHS_ALL_CLR (1 << 1) +#define USBHS_FORCE_RST (1 << 2) +#define USBHS_INT_BUSY_EN (1 << 3) +#define USBHS_DEV_PU_EN (1 << 4) +#define USBHS_SPEED_MASK (3 << 5) +#define USBHS_FULL_SPEED (0 << 5) +#define USBHS_HIGH_SPEED (1 << 5) +#define USBHS_LOW_SPEED (2 << 5) +#define USBHS_HOST_MODE (1 << 7) + +// USB_INT_EN +#define USBHS_INT_EN_OFFSET 0x02 +#define USBHS_BUS_RST_EN (1 << 0) +#define USBHS_DETECT_EN (1 << 0) +#define USBHS_TRANSFER_EN (1 << 1) +#define USBHS_SUSPEND_EN (1 << 2) +#define USBHS_SOF_ACT_EN (1 << 3) +#define USBHS_FIFO_OV_EN (1 << 4) +#define USBHS_SETUP_ACT_EN (1 << 5) +#define USBHS_ISO_ACT_EN (1 << 6) +#define USBHS_DEV_NAK_EN (1 << 7) + +// USB DEV AD +#define USBHS_DEV_AD_OFFSET 0x03 +// USB FRAME_NO +#define USBHS_FRAME_NO_OFFSET 0x04 +// USB SUSPEND +#define USBHS_SUSPEND_OFFSET 0x06 +#define USBHS_DEV_REMOTE_WAKEUP (1 << 2) +#define USBHS_LINESTATE_MASK (2 << 4) /* Read Only */ + +// RESERVED0 + +// USB SPEED TYPE +#define USBHS_SPEED_TYPE_OFFSET 0x08 +#define USBSPEED_MASK (0x03) + +// USB_MIS_ST +#define USBHS_MIS_ST_OFFSET 0x09 +#define USBHS_SPLIT_CAN (1 << 0) +#define USBHS_ATTACH (1 << 1) +#define USBHS_SUSPEND (1 << 2) +#define USBHS_BUS_RESET (1 << 3) +#define USBHS_R_FIFO_RDY (1 << 4) +#define USBHS_SIE_FREE (1 << 5) +#define USBHS_SOF_ACT (1 << 6) +#define USBHS_SOF_PRES (1 << 7) + +// INT_FLAG +#define USBHS_INT_FLAG_OFFSET 0x0A +#define USBHS_BUS_RST_FLAG (1 << 0) +#define USBHS_DETECT_FLAG (1 << 0) +#define USBHS_TRANSFER_FLAG (1 << 1) +#define USBHS_SUSPEND_FLAG (1 << 2) +#define USBHS_HST_SOF_FLAG (1 << 3) +#define USBHS_FIFO_OV_FLAG (1 << 4) +#define USBHS_SETUP_FLAG (1 << 5) +#define USBHS_ISO_ACT_FLAG (1 << 6) + +// INT_ST +#define USBHS_INT_ST_OFFSET 0x0B +#define USBHS_DEV_UIS_IS_NAK (1 << 7) +#define USBHS_DEV_UIS_TOG_OK (1 << 6) +#define MASK_UIS_TOKEN (3 << 4) +#define MASK_UIS_ENDP (0x0F) +#define MASK_UIS_H_RES (0x0F) + +#define USBHS_TOGGLE_OK (0x40) +#define USBHS_HOST_RES (0x0f) + +//USB_RX_LEN +#define USBHS_RX_LEN_OFFSET 0x0C +/******************* DEVICE ******************/ + +//UEP_CONFIG +#define USBHS_UEP_CONFIG_OFFSET 0x10 +#define USBHS_EP0_T_EN (1 << 0) +#define USBHS_EP0_R_EN (1 << 16) + +#define USBHS_EP1_T_EN (1 << 1) +#define USBHS_EP1_R_EN (1 << 17) + +#define USBHS_EP2_T_EN (1 << 2) +#define USBHS_EP2_R_EN (1 << 18) + +#define USBHS_EP3_T_EN (1 << 3) +#define USBHS_EP3_R_EN (1 << 19) + +#define USBHS_EP4_T_EN (1 << 4) +#define USBHS_EP4_R_EN (1 << 20) + +#define USBHS_EP5_T_EN (1 << 5) +#define USBHS_EP5_R_EN (1 << 21) + +#define USBHS_EP6_T_EN (1 << 6) +#define USBHS_EP6_R_EN (1 << 22) + +#define USBHS_EP7_T_EN (1 << 7) +#define USBHS_EP7_R_EN (1 << 23) + +#define USBHS_EP8_T_EN (1 << 8) +#define USBHS_EP8_R_EN (1 << 24) + +#define USBHS_EP9_T_EN (1 << 9) +#define USBHS_EP9_R_EN (1 << 25) + +#define USBHS_EP10_T_EN (1 << 10) +#define USBHS_EP10_R_EN (1 << 26) + +#define USBHS_EP11_T_EN (1 << 11) +#define USBHS_EP11_R_EN (1 << 27) + +#define USBHS_EP12_T_EN (1 << 12) +#define USBHS_EP12_R_EN (1 << 28) + +#define USBHS_EP13_T_EN (1 << 13) +#define USBHS_EP13_R_EN (1 << 29) + +#define USBHS_EP14_T_EN (1 << 14) +#define USBHS_EP14_R_EN (1 << 30) + +#define USBHS_EP15_T_EN (1 << 15) +#define USBHS_EP15_R_EN (1 << 31) + +//UEP_TYPE +#define USBHS_UEP_TYPE_OFFSET 0x14 +#define USBHS_EP0_T_TYP (1 << 0) +#define USBHS_EP0_R_TYP (1 << 16) + +#define USBHS_EP1_T_TYP (1 << 1) +#define USBHS_EP1_R_TYP (1 << 17) + +#define USBHS_EP2_T_TYP (1 << 2) +#define USBHS_EP2_R_TYP (1 << 18) + +#define USBHS_EP3_T_TYP (1 << 3) +#define USBHS_EP3_R_TYP (1 << 19) + +#define USBHS_EP4_T_TYP (1 << 4) +#define USBHS_EP4_R_TYP (1 << 20) + +#define USBHS_EP5_T_TYP (1 << 5) +#define USBHS_EP5_R_TYP (1 << 21) + +#define USBHS_EP6_T_TYP (1 << 6) +#define USBHS_EP6_R_TYP (1 << 22) + +#define USBHS_EP7_T_TYP (1 << 7) +#define USBHS_EP7_R_TYP (1 << 23) + +#define USBHS_EP8_T_TYP (1 << 8) +#define USBHS_EP8_R_TYP (1 << 24) + +#define USBHS_EP9_T_TYP (1 << 8) +#define USBHS_EP9_R_TYP (1 << 25) + +#define USBHS_EP10_T_TYP (1 << 10) +#define USBHS_EP10_R_TYP (1 << 26) + +#define USBHS_EP11_T_TYP (1 << 11) +#define USBHS_EP11_R_TYP (1 << 27) + +#define USBHS_EP12_T_TYP (1 << 12) +#define USBHS_EP12_R_TYP (1 << 28) + +#define USBHS_EP13_T_TYP (1 << 13) +#define USBHS_EP13_R_TYP (1 << 29) + +#define USBHS_EP14_T_TYP (1 << 14) +#define USBHS_EP14_R_TYP (1 << 30) + +#define USBHS_EP15_T_TYP (1 << 15) +#define USBHS_EP15_R_TYP (1 << 31) + +/* BUF_MOD UEP1~15 */ +#define USBHS_BUF_MOD_OFFSET 0x18 +#define USBHS_EP0_BUF_MOD (1 << 0) +#define USBHS_EP0_ISO_BUF_MOD (1 << 16) + +#define USBHS_EP1_BUF_MOD (1 << 1) +#define USBHS_EP1_ISO_BUF_MOD (1 << 17) + +#define USBHS_EP2_BUF_MOD (1 << 2) +#define USBHS_EP2_ISO_BUF_MOD (1 << 18) + +#define USBHS_EP3_BUF_MOD (1 << 3) +#define USBHS_EP3_ISO_BUF_MOD (1 << 19) + +#define USBHS_EP4_BUF_MOD (1 << 4) +#define USBHS_EP4_ISO_BUF_MOD (1 << 20) + +#define USBHS_EP5_BUF_MOD (1 << 5) +#define USBHS_EP5_ISO_BUF_MOD (1 << 21) + +#define USBHS_EP6_BUF_MOD (1 << 6) +#define USBHS_EP6_ISO_BUF_MOD (1 << 22) + +#define USBHS_EP7_BUF_MOD (1 << 7) +#define USBHS_EP7_ISO_BUF_MOD (1 << 23) + +#define USBHS_EP8_BUF_MOD (1 << 8) +#define USBHS_EP8_ISO_BUF_MOD (1 << 24) + +#define USBHS_EP9_BUF_MOD (1 << 9) +#define USBHS_EP9_ISO_BUF_MOD (1 << 25) + +#define USBHS_EP10_BUF_MOD (1 << 10) +#define USBHS_EP10_ISO_BUF_MOD (1 << 26) + +#define USBHS_EP11_BUF_MOD (1 << 11) +#define USBHS_EP11_ISO_BUF_MOD (1 << 27) + +#define USBHS_EP12_BUF_MOD (1 << 12) +#define USBHS_EP12_ISO_BUF_MOD (1 << 28) + +#define USBHS_EP13_BUF_MOD (1 << 13) +#define USBHS_EP13_ISO_BUF_MOD (1 << 29) + +#define USBHS_EP14_BUF_MOD (1 << 14) +#define USBHS_EP14_ISO_BUF_MOD (1 << 30) + +#define USBHS_EP15_BUF_MOD (1 << 15) +#define USBHS_EP15_ISO_BUF_MOD (1 << 31) +//USBHS_EPn_T_EN USBHS_EPn_R_EN USBHS_EPn_BUF_MOD Description: Arrange from low to high with UEPn_DMA as the starting address +// 0 0 x The endpoint is disabled and the UEPn_*_DMA buffers are not used. +// 1 0 0 The first address of the receive (OUT) buffer is UEPn_RX_DMA +// 1 0 1 RB_UEPn_RX_TOG[0]=0, use buffer UEPn_RX_DMA RB_UEPn_RX_TOG[0]=1, use buffer UEPn_TX_DMA +// 0 1 0 The first address of the transmit (IN) buffer is UEPn_TX_DMA. +// 0 1 1 RB_UEPn_TX_TOG[0]=0, use buffer UEPn_TX_DMA RB_UEPn_TX_TOG[0]=1, use buffer UEPn_RX_DMA + +/* USB0_DMA */ +#define USBHS_UEP0_DMA_OFFSET(n) (0x1C) // endpoint 0 DMA buffer address + +/* USBX_RX_DMA */ +#define USBHS_UEPx_RX_DMA_OFFSET(n) (0x1C + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_TX_DMA_OFFSET(n) (0x58 + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_MAX_LEN_OFFSET(n) (0x98 + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_T_LEN_OFFSET(n) (0xD8 + 4 * (n)) // endpoint x DMA buffer address +#define USBHS_UEPx_TX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 2) // endpoint x DMA buffer address +#define USBHS_UEPx_RX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 3) // endpoint x DMA buffer address + +// UEPn_T_LEN +#define USBHS_EP_T_LEN_MASK (0x7FF) + +//UEPn_TX_CTRL +#define USBHS_EP_T_RES_MASK (3 << 0) +#define USBHS_EP_T_RES_ACK (0 << 0) +#define USBHS_EP_T_RES_NYET (1 << 0) +#define USBHS_EP_T_RES_NAK (2 << 0) +#define USBHS_EP_T_RES_STALL (3 << 0) + +#define USBHS_EP_T_TOG_MASK (3 << 3) +#define USBHS_EP_T_TOG_0 (0 << 3) +#define USBHS_EP_T_TOG_1 (1 << 3) +#define USBHS_EP_T_TOG_2 (2 << 3) +#define USBHS_EP_T_TOG_M (3 << 3) + +#define USBHS_EP_T_AUTOTOG (1 << 5) + +//UEPn_RX_CTRL +#define USBHS_EP_R_RES_MASK (3 << 0) +#define USBHS_EP_R_RES_ACK (0 << 0) +#define USBHS_EP_R_RES_NYET (1 << 0) +#define USBHS_EP_R_RES_NAK (2 << 0) +#define USBHS_EP_R_RES_STALL (3 << 0) + +#define USBHS_EP_R_TOG_MASK (3 << 3) +#define USBHS_EP_R_TOG_0 (0 << 3) +#define USBHS_EP_R_TOG_1 (1 << 3) +#define USBHS_EP_R_TOG_2 (2 << 3) +#define USBHS_EP_R_TOG_M (3 << 3) + +#define USBHS_EP_R_AUTOTOG (1 << 5) + +#define USBHS_TOG_MATCH (1 << 6) + +/******************* HOST ******************/ +// USB HOST_CTRL +#define USBHS_SEND_BUS_RESET (1 << 0) +#define USBHS_SEND_BUS_SUSPEND (1 << 1) +#define USBHS_SEND_BUS_RESUME (1 << 2) +#define USBHS_REMOTE_WAKE (1 << 3) +#define USBHS_PHY_SUSPENDM (1 << 4) +#define USBHS_UH_SOFT_FREE (1 << 6) +#define USBHS_SEND_SOF_EN (1 << 7) + +//UH_CONFIG +#define USBHS_HOST_TX_EN (1 << 3) +#define USBHS_HOST_RX_EN (1 << 18) + +// HOST_EP_TYPE +#define USBHS_ENDP_TX_ISO (1 << 3) +#define USBHS_ENDP_RX_ISO (1 << (16 + 2)) + +// R32_UH_EP_PID +#define USBHS_HOST_MASK_TOKEN (0x0f) +#define USBHS_HOST_MASK_ENDP (0x0f << 4) + +//R8_UH_RX_CTRL +#define USBHS_EP_R_RES_MASK (3 << 0) +#define USBHS_EP_R_RES_ACK (0 << 0) +#define USBHS_EP_R_RES_NYET (1 << 0) +#define USBHS_EP_R_RES_NAK (2 << 0) +#define USBHS_EP_R_RES_STALL (3 << 0) + +#define USBHS_UH_R_RES_NO (1 << 2) +#define USBHS_UH_R_TOG_1 (1 << 3) +#define USBHS_UH_R_TOG_2 (2 << 3) +#define USBHS_UH_R_TOG_3 (3 << 3) +#define USBHS_UH_R_TOG_AUTO (1 << 5) +#define USBHS_UH_R_DATA_NO (1 << 6) +//R8_UH_TX_CTRL +#define USBHS_UH_T_RES_MASK (3 << 0) +#define USBHS_UH_T_RES_ACK (0 << 0) +#define USBHS_UH_T_RES_NYET (1 << 0) +#define USBHS_UH_T_RES_NAK (2 << 0) +#define USBHS_UH_T_RES_STALL (3 << 0) + +#define USBHS_UH_T_RES_NO (1 << 2) +#define USBHS_UH_T_TOG_1 (1 << 3) +#define USBHS_UH_T_TOG_2 (2 << 3) +#define USBHS_UH_T_TOG_3 (3 << 3) +#define USBHS_UH_T_TOG_AUTO (1 << 5) +#define USBHS_UH_T_DATA_NO (1 << 6) + +// 00: OUT, 01:SOF, 10:IN, 11:SETUP +#define PID_OUT 0 +#define PID_SOF 1 +#define PID_IN 2 +#define PID_SETUP 3 + +#endif diff --git a/src/portable/wch/ch32v307/ch32_usbhs_reg.h b/src/portable/wch/ch32v307/ch32_usbhs_reg.h deleted file mode 100644 index 5a2c1fbc9..000000000 --- a/src/portable/wch/ch32v307/ch32_usbhs_reg.h +++ /dev/null @@ -1,345 +0,0 @@ -#ifndef _USB_CH32_USBHS_REG_H -#define _USB_CH32_USBHS_REG_H - -#include - -/******************* GLOBAL ******************/ - -// USB CONTROL -#define USBHS_CONTROL_OFFSET 0x00 -#define USBHS_DMA_EN (1 << 0) -#define USBHS_ALL_CLR (1 << 1) -#define USBHS_FORCE_RST (1 << 2) -#define USBHS_INT_BUSY_EN (1 << 3) -#define USBHS_DEV_PU_EN (1 << 4) -#define USBHS_SPEED_MASK (3 << 5) -#define USBHS_FULL_SPEED (0 << 5) -#define USBHS_HIGH_SPEED (1 << 5) -#define USBHS_LOW_SPEED (2 << 5) -#define USBHS_HOST_MODE (1 << 7) - -// USB_INT_EN -#define USBHS_INT_EN_OFFSET 0x02 -#define USBHS_BUS_RST_EN (1 << 0) -#define USBHS_DETECT_EN (1 << 0) -#define USBHS_TRANSFER_EN (1 << 1) -#define USBHS_SUSPEND_EN (1 << 2) -#define USBHS_SOF_ACT_EN (1 << 3) -#define USBHS_FIFO_OV_EN (1 << 4) -#define USBHS_SETUP_ACT_EN (1 << 5) -#define USBHS_ISO_ACT_EN (1 << 6) -#define USBHS_DEV_NAK_EN (1 << 7) - -// USB DEV AD -#define USBHS_DEV_AD_OFFSET 0x03 -// USB FRAME_NO -#define USBHS_FRAME_NO_OFFSET 0x04 -// USB SUSPEND -#define USBHS_SUSPEND_OFFSET 0x06 -#define USBHS_DEV_REMOTE_WAKEUP (1 << 2) -#define USBHS_LINESTATE_MASK (2 << 4) /* Read Only */ - -// RESERVED0 - -// USB SPEED TYPE -#define USBHS_SPEED_TYPE_OFFSET 0x08 -#define USBSPEED_MASK (0x03) - -// USB_MIS_ST -#define USBHS_MIS_ST_OFFSET 0x09 -#define USBHS_SPLIT_CAN (1 << 0) -#define USBHS_ATTACH (1 << 1) -#define USBHS_SUSPEND (1 << 2) -#define USBHS_BUS_RESET (1 << 3) -#define USBHS_R_FIFO_RDY (1 << 4) -#define USBHS_SIE_FREE (1 << 5) -#define USBHS_SOF_ACT (1 << 6) -#define USBHS_SOF_PRES (1 << 7) - -// INT_FLAG -#define USBHS_INT_FLAG_OFFSET 0x0A -#define USBHS_BUS_RST_FLAG (1 << 0) -#define USBHS_DETECT_FLAG (1 << 0) -#define USBHS_TRANSFER_FLAG (1 << 1) -#define USBHS_SUSPEND_FLAG (1 << 2) -#define USBHS_HST_SOF_FLAG (1 << 3) -#define USBHS_FIFO_OV_FLAG (1 << 4) -#define USBHS_SETUP_FLAG (1 << 5) -#define USBHS_ISO_ACT_FLAG (1 << 6) - -// INT_ST -#define USBHS_INT_ST_OFFSET 0x0B -#define USBHS_DEV_UIS_IS_NAK (1 << 7) -#define USBHS_DEV_UIS_TOG_OK (1 << 6) -#define MASK_UIS_TOKEN (3 << 4) -#define MASK_UIS_ENDP (0x0F) -#define MASK_UIS_H_RES (0x0F) - -#define USBHS_TOGGLE_OK (0x40) -#define USBHS_HOST_RES (0x0f) - -//USB_RX_LEN -#define USBHS_RX_LEN_OFFSET 0x0C -/******************* DEVICE ******************/ - -//UEP_CONFIG -#define USBHS_UEP_CONFIG_OFFSET 0x10 -#define USBHS_EP0_T_EN (1 << 0) -#define USBHS_EP0_R_EN (1 << 16) - -#define USBHS_EP1_T_EN (1 << 1) -#define USBHS_EP1_R_EN (1 << 17) - -#define USBHS_EP2_T_EN (1 << 2) -#define USBHS_EP2_R_EN (1 << 18) - -#define USBHS_EP3_T_EN (1 << 3) -#define USBHS_EP3_R_EN (1 << 19) - -#define USBHS_EP4_T_EN (1 << 4) -#define USBHS_EP4_R_EN (1 << 20) - -#define USBHS_EP5_T_EN (1 << 5) -#define USBHS_EP5_R_EN (1 << 21) - -#define USBHS_EP6_T_EN (1 << 6) -#define USBHS_EP6_R_EN (1 << 22) - -#define USBHS_EP7_T_EN (1 << 7) -#define USBHS_EP7_R_EN (1 << 23) - -#define USBHS_EP8_T_EN (1 << 8) -#define USBHS_EP8_R_EN (1 << 24) - -#define USBHS_EP9_T_EN (1 << 9) -#define USBHS_EP9_R_EN (1 << 25) - -#define USBHS_EP10_T_EN (1 << 10) -#define USBHS_EP10_R_EN (1 << 26) - -#define USBHS_EP11_T_EN (1 << 11) -#define USBHS_EP11_R_EN (1 << 27) - -#define USBHS_EP12_T_EN (1 << 12) -#define USBHS_EP12_R_EN (1 << 28) - -#define USBHS_EP13_T_EN (1 << 13) -#define USBHS_EP13_R_EN (1 << 29) - -#define USBHS_EP14_T_EN (1 << 14) -#define USBHS_EP14_R_EN (1 << 30) - -#define USBHS_EP15_T_EN (1 << 15) -#define USBHS_EP15_R_EN (1 << 31) - -//UEP_TYPE -#define USBHS_UEP_TYPE_OFFSET 0x14 -#define USBHS_EP0_T_TYP (1 << 0) -#define USBHS_EP0_R_TYP (1 << 16) - -#define USBHS_EP1_T_TYP (1 << 1) -#define USBHS_EP1_R_TYP (1 << 17) - -#define USBHS_EP2_T_TYP (1 << 2) -#define USBHS_EP2_R_TYP (1 << 18) - -#define USBHS_EP3_T_TYP (1 << 3) -#define USBHS_EP3_R_TYP (1 << 19) - -#define USBHS_EP4_T_TYP (1 << 4) -#define USBHS_EP4_R_TYP (1 << 20) - -#define USBHS_EP5_T_TYP (1 << 5) -#define USBHS_EP5_R_TYP (1 << 21) - -#define USBHS_EP6_T_TYP (1 << 6) -#define USBHS_EP6_R_TYP (1 << 22) - -#define USBHS_EP7_T_TYP (1 << 7) -#define USBHS_EP7_R_TYP (1 << 23) - -#define USBHS_EP8_T_TYP (1 << 8) -#define USBHS_EP8_R_TYP (1 << 24) - -#define USBHS_EP9_T_TYP (1 << 8) -#define USBHS_EP9_R_TYP (1 << 25) - -#define USBHS_EP10_T_TYP (1 << 10) -#define USBHS_EP10_R_TYP (1 << 26) - -#define USBHS_EP11_T_TYP (1 << 11) -#define USBHS_EP11_R_TYP (1 << 27) - -#define USBHS_EP12_T_TYP (1 << 12) -#define USBHS_EP12_R_TYP (1 << 28) - -#define USBHS_EP13_T_TYP (1 << 13) -#define USBHS_EP13_R_TYP (1 << 29) - -#define USBHS_EP14_T_TYP (1 << 14) -#define USBHS_EP14_R_TYP (1 << 30) - -#define USBHS_EP15_T_TYP (1 << 15) -#define USBHS_EP15_R_TYP (1 << 31) - -/* BUF_MOD UEP1~15 */ -#define USBHS_BUF_MOD_OFFSET 0x18 -#define USBHS_EP0_BUF_MOD (1 << 0) -#define USBHS_EP0_ISO_BUF_MOD (1 << 16) - -#define USBHS_EP1_BUF_MOD (1 << 1) -#define USBHS_EP1_ISO_BUF_MOD (1 << 17) - -#define USBHS_EP2_BUF_MOD (1 << 2) -#define USBHS_EP2_ISO_BUF_MOD (1 << 18) - -#define USBHS_EP3_BUF_MOD (1 << 3) -#define USBHS_EP3_ISO_BUF_MOD (1 << 19) - -#define USBHS_EP4_BUF_MOD (1 << 4) -#define USBHS_EP4_ISO_BUF_MOD (1 << 20) - -#define USBHS_EP5_BUF_MOD (1 << 5) -#define USBHS_EP5_ISO_BUF_MOD (1 << 21) - -#define USBHS_EP6_BUF_MOD (1 << 6) -#define USBHS_EP6_ISO_BUF_MOD (1 << 22) - -#define USBHS_EP7_BUF_MOD (1 << 7) -#define USBHS_EP7_ISO_BUF_MOD (1 << 23) - -#define USBHS_EP8_BUF_MOD (1 << 8) -#define USBHS_EP8_ISO_BUF_MOD (1 << 24) - -#define USBHS_EP9_BUF_MOD (1 << 9) -#define USBHS_EP9_ISO_BUF_MOD (1 << 25) - -#define USBHS_EP10_BUF_MOD (1 << 10) -#define USBHS_EP10_ISO_BUF_MOD (1 << 26) - -#define USBHS_EP11_BUF_MOD (1 << 11) -#define USBHS_EP11_ISO_BUF_MOD (1 << 27) - -#define USBHS_EP12_BUF_MOD (1 << 12) -#define USBHS_EP12_ISO_BUF_MOD (1 << 28) - -#define USBHS_EP13_BUF_MOD (1 << 13) -#define USBHS_EP13_ISO_BUF_MOD (1 << 29) - -#define USBHS_EP14_BUF_MOD (1 << 14) -#define USBHS_EP14_ISO_BUF_MOD (1 << 30) - -#define USBHS_EP15_BUF_MOD (1 << 15) -#define USBHS_EP15_ISO_BUF_MOD (1 << 31) -//USBHS_EPn_T_EN USBHS_EPn_R_EN USBHS_EPn_BUF_MOD Description: Arrange from low to high with UEPn_DMA as the starting address -// 0 0 x The endpoint is disabled and the UEPn_*_DMA buffers are not used. -// 1 0 0 The first address of the receive (OUT) buffer is UEPn_RX_DMA -// 1 0 1 RB_UEPn_RX_TOG[0]=0, use buffer UEPn_RX_DMA RB_UEPn_RX_TOG[0]=1, use buffer UEPn_TX_DMA -// 0 1 0 The first address of the transmit (IN) buffer is UEPn_TX_DMA. -// 0 1 1 RB_UEPn_TX_TOG[0]=0, use buffer UEPn_TX_DMA RB_UEPn_TX_TOG[0]=1, use buffer UEPn_RX_DMA - -/* USB0_DMA */ -#define USBHS_UEP0_DMA_OFFSET(n) (0x1C) // endpoint 0 DMA buffer address - -/* USBX_RX_DMA */ -#define USBHS_UEPx_RX_DMA_OFFSET(n) (0x1C + 4 * (n)) // endpoint x DMA buffer address - -#define USBHS_UEPx_TX_DMA_OFFSET(n) (0x58 + 4 * (n)) // endpoint x DMA buffer address - -#define USBHS_UEPx_MAX_LEN_OFFSET(n) (0x98 + 4 * (n)) // endpoint x DMA buffer address - -#define USBHS_UEPx_T_LEN_OFFSET(n) (0xD8 + 4 * (n)) // endpoint x DMA buffer address -#define USBHS_UEPx_TX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 2) // endpoint x DMA buffer address -#define USBHS_UEPx_RX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 3) // endpoint x DMA buffer address - -// UEPn_T_LEN -#define USBHS_EP_T_LEN_MASK (0x7FF) - -//UEPn_TX_CTRL -#define USBHS_EP_T_RES_MASK (3 << 0) -#define USBHS_EP_T_RES_ACK (0 << 0) -#define USBHS_EP_T_RES_NYET (1 << 0) -#define USBHS_EP_T_RES_NAK (2 << 0) -#define USBHS_EP_T_RES_STALL (3 << 0) - -#define USBHS_EP_T_TOG_MASK (3 << 3) -#define USBHS_EP_T_TOG_0 (0 << 3) -#define USBHS_EP_T_TOG_1 (1 << 3) -#define USBHS_EP_T_TOG_2 (2 << 3) -#define USBHS_EP_T_TOG_M (3 << 3) - -#define USBHS_EP_T_AUTOTOG (1 << 5) - -//UEPn_RX_CTRL -#define USBHS_EP_R_RES_MASK (3 << 0) -#define USBHS_EP_R_RES_ACK (0 << 0) -#define USBHS_EP_R_RES_NYET (1 << 0) -#define USBHS_EP_R_RES_NAK (2 << 0) -#define USBHS_EP_R_RES_STALL (3 << 0) - -#define USBHS_EP_R_TOG_MASK (3 << 3) -#define USBHS_EP_R_TOG_0 (0 << 3) -#define USBHS_EP_R_TOG_1 (1 << 3) -#define USBHS_EP_R_TOG_2 (2 << 3) -#define USBHS_EP_R_TOG_M (3 << 3) - -#define USBHS_EP_R_AUTOTOG (1 << 5) - -#define USBHS_TOG_MATCH (1 << 6) - -/******************* HOST ******************/ -// USB HOST_CTRL -#define USBHS_SEND_BUS_RESET (1 << 0) -#define USBHS_SEND_BUS_SUSPEND (1 << 1) -#define USBHS_SEND_BUS_RESUME (1 << 2) -#define USBHS_REMOTE_WAKE (1 << 3) -#define USBHS_PHY_SUSPENDM (1 << 4) -#define USBHS_UH_SOFT_FREE (1 << 6) -#define USBHS_SEND_SOF_EN (1 << 7) - -//UH_CONFIG -#define USBHS_HOST_TX_EN (1 << 3) -#define USBHS_HOST_RX_EN (1 << 18) - -// HOST_EP_TYPE -#define USBHS_ENDP_TX_ISO (1 << 3) -#define USBHS_ENDP_RX_ISO (1 << (16 + 2)) - -// R32_UH_EP_PID -#define USBHS_HOST_MASK_TOKEN (0x0f) -#define USBHS_HOST_MASK_ENDP (0x0f << 4) - -//R8_UH_RX_CTRL -#define USBHS_EP_R_RES_MASK (3 << 0) -#define USBHS_EP_R_RES_ACK (0 << 0) -#define USBHS_EP_R_RES_NYET (1 << 0) -#define USBHS_EP_R_RES_NAK (2 << 0) -#define USBHS_EP_R_RES_STALL (3 << 0) - -#define USBHS_UH_R_RES_NO (1 << 2) -#define USBHS_UH_R_TOG_1 (1 << 3) -#define USBHS_UH_R_TOG_2 (2 << 3) -#define USBHS_UH_R_TOG_3 (3 << 3) -#define USBHS_UH_R_TOG_AUTO (1 << 5) -#define USBHS_UH_R_DATA_NO (1 << 6) -//R8_UH_TX_CTRL -#define USBHS_UH_T_RES_MASK (3 << 0) -#define USBHS_UH_T_RES_ACK (0 << 0) -#define USBHS_UH_T_RES_NYET (1 << 0) -#define USBHS_UH_T_RES_NAK (2 << 0) -#define USBHS_UH_T_RES_STALL (3 << 0) - -#define USBHS_UH_T_RES_NO (1 << 2) -#define USBHS_UH_T_TOG_1 (1 << 3) -#define USBHS_UH_T_TOG_2 (2 << 3) -#define USBHS_UH_T_TOG_3 (3 << 3) -#define USBHS_UH_T_TOG_AUTO (1 << 5) -#define USBHS_UH_T_DATA_NO (1 << 6) - -// 00: OUT, 01:SOF, 10:IN, 11:SETUP -#define PID_OUT 0 -#define PID_SOF 1 -#define PID_IN 2 -#define PID_SETUP 3 - -#endif diff --git a/src/portable/wch/ch32v307/dcd_usbhs.c b/src/portable/wch/ch32v307/dcd_usbhs.c deleted file mode 100644 index 3ad011cff..000000000 --- a/src/portable/wch/ch32v307/dcd_usbhs.c +++ /dev/null @@ -1,391 +0,0 @@ -/* - * The MIT License (MIT) - * - * Copyright (c) 2022 Greg Davill - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE - * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - * - * This file is part of the TinyUSB stack. - */ - -#include "tusb_option.h" - -#if CFG_TUD_ENABLED && (CFG_TUSB_MCU == OPT_MCU_CH32V307) -#include "device/dcd.h" - -#include "ch32_usbhs_reg.h" -#include "core_riscv.h" - -// Max number of bi-directional endpoints including EP0 -#define EP_MAX 16 - -typedef struct { - uint8_t *buffer; - // tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API - uint16_t total_len; - uint16_t queued_len; - uint16_t max_size; - bool short_packet; -} xfer_ctl_t; - -#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] -static xfer_ctl_t xfer_status[EP_MAX][2]; - -#define EP_TX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_TX_LEN) + (ep)*2) -#define EP_TX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_TX_CTRL) + (ep)*4) -#define EP_RX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_RX_CTRL) + (ep)*4) -#define EP_RX_MAX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_MAX_LEN) + (ep)*2) - -#define EP_TX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_TX_DMA) + (ep - 1)) -#define EP_RX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_RX_DMA) + (ep - 1)) - -/* Endpoint Buffer */ -TU_ATTR_ALIGNED(4) uint8_t EP0_DatabufHD[64]; // ep0(64) - -volatile uint8_t USBHS_Dev_Endp0_Tog = 0x01; - -void dcd_init(uint8_t rhport) { - (void)rhport; - - memset(&xfer_status, 0, sizeof(xfer_status)); - - USBHSD->HOST_CTRL = 0x00; - USBHSD->HOST_CTRL = USBHS_PHY_SUSPENDM; - - USBHSD->CONTROL = 0; - -#if TUD_OPT_HIGH_SPEED - USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED; -#else - #error OPT_MODE_FULL_SPEED not currently supported on CH32V307 - USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED; -#endif - - USBHSD->INT_EN = 0; - USBHSD->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_DETECT_EN | USBHS_SUSPEND_EN; - - /* ALL endpoint enable */ - USBHSD->ENDP_CONFIG = 0xffffffff; - - USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN; - USBHSD->ENDP_TYPE = 0x00; - USBHSD->BUF_MODE = 0x00; - - USBHSD->UEP0_MAX_LEN = 64; - - USBHSD->UEP0_DMA = (uint32_t)EP0_DatabufHD; - - USBHSD->UEP0_TX_LEN = 0; - USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_NAK; - USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; - - for (int ep = 1; ep < EP_MAX; ep++) { - EP_TX_LEN(ep) = 0; - EP_TX_CTRL(ep) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK; - EP_RX_CTRL(ep) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK; - - EP_RX_MAX_LEN(ep) = 512; - } - - USBHSD->DEV_AD = 0; - USBHSD->CONTROL |= USBHS_DEV_PU_EN; -} - -void dcd_int_enable(uint8_t rhport) { - (void)rhport; - - NVIC_EnableIRQ(USBHS_IRQn); -} - -void dcd_int_disable(uint8_t rhport) { - (void)rhport; - - NVIC_DisableIRQ(USBHS_IRQn); -} - -void dcd_edpt_close_all(uint8_t rhport) { - (void)rhport; -} - -void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { - (void)dev_addr; - - // Response with zlp status - dcd_edpt_xfer(rhport, 0x80, NULL, 0); -} - -void dcd_remote_wakeup(uint8_t rhport) -{ - (void) rhport; -} - -void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) { - (void)rhport; - - if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && - request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && - request->bRequest == TUSB_REQ_SET_ADDRESS) { - USBHSD->DEV_AD = (uint8_t)request->wValue; - } - - EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK; - EP_RX_CTRL(0) = USBHS_EP_R_RES_ACK; -} - -bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) { - (void)rhport; - - uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); - uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); - - TU_ASSERT(epnum < EP_MAX); - - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); - xfer->max_size = tu_edpt_packet_size(desc_edpt); - - if (epnum != 0) { - if (tu_edpt_dir(desc_edpt->bEndpointAddress) == TUSB_DIR_OUT) { - EP_RX_CTRL(epnum) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_ACK; - } else { - EP_TX_LEN(epnum) = 0; - EP_TX_CTRL(epnum) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0; - } - } - - return true; -} - -int usbd_ep_close(const uint8_t ep) { - (void)ep; - - return 0; -} -void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - if (epnum == 0) { - if (dir == TUSB_DIR_OUT) { - USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_STALL; - } else { - USBHSD->UEP0_TX_LEN = 0; - USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_STALL; - } - } else { - if (dir == TUSB_DIR_OUT) { - EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_STALL; - - } else { - EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~USBHS_EP_T_RES_MASK) | USBHS_EP_T_RES_STALL; - } - } -} - -void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { - (void)rhport; - - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - if (epnum == 0) { - if (dir == TUSB_DIR_OUT) { - USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; - } else { - } - } else { - if (dir == TUSB_DIR_OUT) { - EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~(USBHS_EP_R_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_ACK; - - } else { - EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_NAK; - } - } -} - -bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { - (void)rhport; - uint8_t const epnum = tu_edpt_number(ep_addr); - uint8_t const dir = tu_edpt_dir(ep_addr); - - xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); - xfer->buffer = buffer; - // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API - xfer->total_len = total_bytes; - xfer->queued_len = 0; - xfer->short_packet = false; - - // uint16_t num_packets = (total_bytes / xfer->max_size); - uint16_t short_packet_size = total_bytes % (xfer->max_size + 1); - - // Zero-size packet is special case. - if (short_packet_size == 0 || (total_bytes == 0)) { - xfer->short_packet = true; - } - - if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) { - if (!total_bytes) { - xfer->short_packet = true; - if (epnum == 0) { - USBHSD->UEP0_TX_LEN = 0; - USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); - USBHS_Dev_Endp0_Tog ^= 1; - } else { - EP_TX_LEN(epnum) = 0; - EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK; - } - } else { - if (epnum == 0) { - xfer->queued_len += short_packet_size; - memcpy(&EP0_DatabufHD[0], buffer, short_packet_size); - - USBHSD->UEP0_TX_LEN = short_packet_size; - USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); - USBHS_Dev_Endp0_Tog ^= 1; - } else { - xfer->queued_len += short_packet_size; - - EP_TX_DMA_ADDR(epnum) = (uint32_t)buffer; - USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << epnum); - EP_TX_LEN(epnum) = short_packet_size; - EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK; - } - } - } else { /* TUSB_DIR_OUT */ - if (epnum == 0) { - uint32_t read_count = USBHSD->RX_LEN; - read_count = TU_MIN(read_count, total_bytes); - - if ((total_bytes == 8)) { - read_count = 8; - memcpy(buffer, &EP0_DatabufHD[0], 8); - } else { - memcpy(buffer, &EP0_DatabufHD[0], read_count); - } - } else { - EP_RX_DMA_ADDR(epnum) = (uint32_t)xfer->buffer; - USBHSD->ENDP_CONFIG |= (USBHS_EP0_R_EN << epnum); - } - - // usbd_ep_read(ep_addr, buffer, total_bytes, &ret_bytes); - } - return true; -} - - -static void receive_packet(xfer_ctl_t *xfer, uint16_t xfer_size) { - // xfer->queued_len = xfer->total_len - remaining; - - uint16_t remaining = xfer->total_len - xfer->queued_len; - uint16_t to_recv_size; - - if (remaining <= xfer->max_size) { - // Avoid buffer overflow. - to_recv_size = (xfer_size > remaining) ? remaining : xfer_size; - } else { - // Room for full packet, choose recv_size based on what the microcontroller - // claims. - to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size; - } - - if (to_recv_size) { - } - - xfer->queued_len += xfer_size; - - // Per USB spec, a short OUT packet (including length 0) is always - // indicative of the end of a transfer (at least for ctl, bulk, int). - xfer->short_packet = (xfer_size < xfer->max_size); -} - -void dcd_int_handler(uint8_t rhport) { - (void)rhport; - - uint32_t end_num, rx_token; - uint8_t intflag = 0; - - intflag = USBHSD->INT_FG; - - if (intflag & USBHS_TRANSFER_FLAG) { - - end_num = (USBHSD->INT_ST) & MASK_UIS_ENDP; - rx_token = (((USBHSD->INT_ST) & MASK_UIS_TOKEN) >> 4) & 0x03; - - uint8_t endp = end_num | (rx_token == PID_IN ? TUSB_DIR_IN_MASK : 0); - - xfer_ctl_t *xfer = XFER_CTL_BASE(end_num, tu_edpt_dir(endp)); - - if (rx_token == PID_OUT) { - uint16_t rx_len = USBHSD->RX_LEN; - - receive_packet(xfer, rx_len); - - if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) { - xfer->short_packet = false; - - dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true); - } - - if (end_num == 0) { - USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0; - } - - } else if (rx_token == PID_IN) { - if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) { - xfer->short_packet = false; - xfer->total_len = 0; - dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true); - - EP_TX_CTRL(end_num) = (EP_TX_CTRL(end_num) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_NAK; - - if (end_num == 0) { - } - } else { - dcd_edpt_xfer(0, endp, xfer->buffer + xfer->queued_len, xfer->total_len - xfer->queued_len); - } - } - - USBHSD->INT_FG = USBHS_TRANSFER_FLAG; /* Clear flag */ - } else if (intflag & USBHS_SETUP_FLAG) { - USBHS_Dev_Endp0_Tog = 1; - dcd_event_setup_received(0, EP0_DatabufHD, true); - - USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */ - } else if (intflag & USBHS_DETECT_FLAG) { - USBHS_Dev_Endp0_Tog = 1; - - xfer_status[0][TUSB_DIR_OUT].max_size = 64; - xfer_status[0][TUSB_DIR_IN].max_size = 64; - - dcd_event_bus_reset(0, TUSB_SPEED_HIGH, true); - - USBHSD->DEV_AD = 0; - USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0; - - USBHSD->INT_FG = USBHS_DETECT_FLAG; /* Clear flag */ - } else if (intflag & USBHS_SUSPEND_FLAG) { - dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SUSPEND }; - dcd_event_handler(&event, true); - - USBHSD->INT_FG = USBHS_SUSPEND_FLAG; /* Clear flag */ - } -} - -#endif diff --git a/src/portable/wch/dcd_ch32_usbhs.c b/src/portable/wch/dcd_ch32_usbhs.c new file mode 100644 index 000000000..1f1c0b876 --- /dev/null +++ b/src/portable/wch/dcd_ch32_usbhs.c @@ -0,0 +1,391 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2022 Greg Davill + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + * + * This file is part of the TinyUSB stack. + */ + +#include "tusb_option.h" + +#if CFG_TUD_ENABLED && ((CFG_TUSB_MCU == OPT_MCU_CH32V307) || (CFG_TUSB_MCU == OPT_MCU_CH32F20X)) +#include "device/dcd.h" + +#include "ch32_usbhs_reg.h" + + +// Max number of bi-directional endpoints including EP0 +#define EP_MAX 16 + +typedef struct { + uint8_t *buffer; + // tu_fifo_t * ff; // TODO support dcd_edpt_xfer_fifo API + uint16_t total_len; + uint16_t queued_len; + uint16_t max_size; + bool short_packet; +} xfer_ctl_t; + +#define XFER_CTL_BASE(_ep, _dir) &xfer_status[_ep][_dir] +static xfer_ctl_t xfer_status[EP_MAX][2]; + +#define EP_TX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_TX_LEN) + (ep)*2) +#define EP_TX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_TX_CTRL) + (ep)*4) +#define EP_RX_CTRL(ep) *(volatile uint8_t *)((volatile uint8_t *)&(USBHSD->UEP0_RX_CTRL) + (ep)*4) +#define EP_RX_MAX_LEN(ep) *(volatile uint16_t *)((volatile uint16_t *)&(USBHSD->UEP0_MAX_LEN) + (ep)*2) + +#define EP_TX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_TX_DMA) + (ep - 1)) +#define EP_RX_DMA_ADDR(ep) *(volatile uint32_t *)((volatile uint32_t *)&(USBHSD->UEP1_RX_DMA) + (ep - 1)) + +/* Endpoint Buffer */ +TU_ATTR_ALIGNED(4) uint8_t EP0_DatabufHD[64]; // ep0(64) + +volatile uint8_t USBHS_Dev_Endp0_Tog = 0x01; + +void dcd_init(uint8_t rhport) { + (void)rhport; + + memset(&xfer_status, 0, sizeof(xfer_status)); + + USBHSD->HOST_CTRL = 0x00; + USBHSD->HOST_CTRL = USBHS_PHY_SUSPENDM; + + USBHSD->CONTROL = 0; + +#if TUD_OPT_HIGH_SPEED + USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED; +#else + #error OPT_MODE_FULL_SPEED not currently supported on CH32 + USBHSD->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED; +#endif + + USBHSD->INT_EN = 0; + USBHSD->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_DETECT_EN | USBHS_SUSPEND_EN; + + /* ALL endpoint enable */ + USBHSD->ENDP_CONFIG = 0xffffffff; + + USBHSD->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN; + USBHSD->ENDP_TYPE = 0x00; + USBHSD->BUF_MODE = 0x00; + + USBHSD->UEP0_MAX_LEN = 64; + + USBHSD->UEP0_DMA = (uint32_t)EP0_DatabufHD; + + USBHSD->UEP0_TX_LEN = 0; + USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_NAK; + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; + + for (int ep = 1; ep < EP_MAX; ep++) { + EP_TX_LEN(ep) = 0; + EP_TX_CTRL(ep) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK; + EP_RX_CTRL(ep) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK; + + EP_RX_MAX_LEN(ep) = 512; + } + + USBHSD->DEV_AD = 0; + USBHSD->CONTROL |= USBHS_DEV_PU_EN; +} + +void dcd_int_enable(uint8_t rhport) { + (void)rhport; + + NVIC_EnableIRQ(USBHS_IRQn); +} + +void dcd_int_disable(uint8_t rhport) { + (void)rhport; + + NVIC_DisableIRQ(USBHS_IRQn); +} + +void dcd_edpt_close_all(uint8_t rhport) { + (void)rhport; +} + +void dcd_set_address(uint8_t rhport, uint8_t dev_addr) { + (void)dev_addr; + + // Response with zlp status + dcd_edpt_xfer(rhport, 0x80, NULL, 0); +} + +void dcd_remote_wakeup(uint8_t rhport) +{ + (void) rhport; +} + +void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const *request) { + (void)rhport; + + if (request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE && + request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD && + request->bRequest == TUSB_REQ_SET_ADDRESS) { + USBHSD->DEV_AD = (uint8_t)request->wValue; + } + + EP_TX_CTRL(0) = USBHS_EP_T_RES_NAK; + EP_RX_CTRL(0) = USBHS_EP_R_RES_ACK; +} + +bool dcd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const *desc_edpt) { + (void)rhport; + + uint8_t const epnum = tu_edpt_number(desc_edpt->bEndpointAddress); + uint8_t const dir = tu_edpt_dir(desc_edpt->bEndpointAddress); + + TU_ASSERT(epnum < EP_MAX); + + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); + xfer->max_size = tu_edpt_packet_size(desc_edpt); + + if (epnum != 0) { + if (tu_edpt_dir(desc_edpt->bEndpointAddress) == TUSB_DIR_OUT) { + EP_RX_CTRL(epnum) = USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_ACK; + } else { + EP_TX_LEN(epnum) = 0; + EP_TX_CTRL(epnum) = USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0; + } + } + + return true; +} + +int usbd_ep_close(const uint8_t ep) { + (void)ep; + + return 0; +} +void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr) { + (void)rhport; + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if (epnum == 0) { + if (dir == TUSB_DIR_OUT) { + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_STALL; + } else { + USBHSD->UEP0_TX_LEN = 0; + USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_STALL; + } + } else { + if (dir == TUSB_DIR_OUT) { + EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_STALL; + + } else { + EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~USBHS_EP_T_RES_MASK) | USBHS_EP_T_RES_STALL; + } + } +} + +void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr) { + (void)rhport; + + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + if (epnum == 0) { + if (dir == TUSB_DIR_OUT) { + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; + } else { + } + } else { + if (dir == TUSB_DIR_OUT) { + EP_RX_CTRL(epnum) = (EP_RX_CTRL(epnum) & ~(USBHS_EP_R_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_ACK; + + } else { + EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_NAK; + } + } +} + +bool dcd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes) { + (void)rhport; + uint8_t const epnum = tu_edpt_number(ep_addr); + uint8_t const dir = tu_edpt_dir(ep_addr); + + xfer_ctl_t *xfer = XFER_CTL_BASE(epnum, dir); + xfer->buffer = buffer; + // xfer->ff = NULL; // TODO support dcd_edpt_xfer_fifo API + xfer->total_len = total_bytes; + xfer->queued_len = 0; + xfer->short_packet = false; + + // uint16_t num_packets = (total_bytes / xfer->max_size); + uint16_t short_packet_size = total_bytes % (xfer->max_size + 1); + + // Zero-size packet is special case. + if (short_packet_size == 0 || (total_bytes == 0)) { + xfer->short_packet = true; + } + + if (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) { + if (!total_bytes) { + xfer->short_packet = true; + if (epnum == 0) { + USBHSD->UEP0_TX_LEN = 0; + USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); + USBHS_Dev_Endp0_Tog ^= 1; + } else { + EP_TX_LEN(epnum) = 0; + EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK; + } + } else { + if (epnum == 0) { + xfer->queued_len += short_packet_size; + memcpy(&EP0_DatabufHD[0], buffer, short_packet_size); + + USBHSD->UEP0_TX_LEN = short_packet_size; + USBHSD->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | (USBHS_Dev_Endp0_Tog ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); + USBHS_Dev_Endp0_Tog ^= 1; + } else { + xfer->queued_len += short_packet_size; + + EP_TX_DMA_ADDR(epnum) = (uint32_t)buffer; + USBHSD->ENDP_CONFIG |= (USBHS_EP0_T_EN << epnum); + EP_TX_LEN(epnum) = short_packet_size; + EP_TX_CTRL(epnum) = (EP_TX_CTRL(epnum) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_ACK; + } + } + } else { /* TUSB_DIR_OUT */ + if (epnum == 0) { + uint32_t read_count = USBHSD->RX_LEN; + read_count = TU_MIN(read_count, total_bytes); + + if ((total_bytes == 8)) { + read_count = 8; + memcpy(buffer, &EP0_DatabufHD[0], 8); + } else { + memcpy(buffer, &EP0_DatabufHD[0], read_count); + } + } else { + EP_RX_DMA_ADDR(epnum) = (uint32_t)xfer->buffer; + USBHSD->ENDP_CONFIG |= (USBHS_EP0_R_EN << epnum); + } + + // usbd_ep_read(ep_addr, buffer, total_bytes, &ret_bytes); + } + return true; +} + + +static void receive_packet(xfer_ctl_t *xfer, uint16_t xfer_size) { + // xfer->queued_len = xfer->total_len - remaining; + + uint16_t remaining = xfer->total_len - xfer->queued_len; + uint16_t to_recv_size; + + if (remaining <= xfer->max_size) { + // Avoid buffer overflow. + to_recv_size = (xfer_size > remaining) ? remaining : xfer_size; + } else { + // Room for full packet, choose recv_size based on what the microcontroller + // claims. + to_recv_size = (xfer_size > xfer->max_size) ? xfer->max_size : xfer_size; + } + + if (to_recv_size) { + } + + xfer->queued_len += xfer_size; + + // Per USB spec, a short OUT packet (including length 0) is always + // indicative of the end of a transfer (at least for ctl, bulk, int). + xfer->short_packet = (xfer_size < xfer->max_size); +} + +void dcd_int_handler(uint8_t rhport) { + (void)rhport; + + uint32_t end_num, rx_token; + uint8_t intflag = 0; + + intflag = USBHSD->INT_FG; + + if (intflag & USBHS_TRANSFER_FLAG) { + + end_num = (USBHSD->INT_ST) & MASK_UIS_ENDP; + rx_token = (((USBHSD->INT_ST) & MASK_UIS_TOKEN) >> 4) & 0x03; + + uint8_t endp = end_num | (rx_token == PID_IN ? TUSB_DIR_IN_MASK : 0); + + xfer_ctl_t *xfer = XFER_CTL_BASE(end_num, tu_edpt_dir(endp)); + + if (rx_token == PID_OUT) { + uint16_t rx_len = USBHSD->RX_LEN; + + receive_packet(xfer, rx_len); + + if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) { + xfer->short_packet = false; + + dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true); + } + + if (end_num == 0) { + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0; + } + + } else if (rx_token == PID_IN) { + if (xfer->short_packet || (xfer->queued_len == xfer->total_len)) { + xfer->short_packet = false; + xfer->total_len = 0; + dcd_event_xfer_complete(0, endp, xfer->queued_len, XFER_RESULT_SUCCESS, true); + + EP_TX_CTRL(end_num) = (EP_TX_CTRL(end_num) & ~(USBHS_EP_T_RES_MASK)) | USBHS_EP_T_RES_NAK; + + if (end_num == 0) { + } + } else { + dcd_edpt_xfer(0, endp, xfer->buffer + xfer->queued_len, xfer->total_len - xfer->queued_len); + } + } + + USBHSD->INT_FG = USBHS_TRANSFER_FLAG; /* Clear flag */ + } else if (intflag & USBHS_SETUP_FLAG) { + USBHS_Dev_Endp0_Tog = 1; + dcd_event_setup_received(0, EP0_DatabufHD, true); + + USBHSD->INT_FG = USBHS_SETUP_FLAG; /* Clear flag */ + } else if (intflag & USBHS_DETECT_FLAG) { + USBHS_Dev_Endp0_Tog = 1; + + xfer_status[0][TUSB_DIR_OUT].max_size = 64; + xfer_status[0][TUSB_DIR_IN].max_size = 64; + + dcd_event_bus_reset(0, TUSB_SPEED_HIGH, true); + + USBHSD->DEV_AD = 0; + USBHSD->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0; + + USBHSD->INT_FG = USBHS_DETECT_FLAG; /* Clear flag */ + } else if (intflag & USBHS_SUSPEND_FLAG) { + dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SUSPEND }; + dcd_event_handler(&event, true); + + USBHSD->INT_FG = USBHS_SUSPEND_FLAG; /* Clear flag */ + } +} + +#endif diff --git a/src/tusb_option.h b/src/tusb_option.h index a41f5a07e..f4b1a1dd4 100644 --- a/src/tusb_option.h +++ b/src/tusb_option.h @@ -169,6 +169,7 @@ // WCH #define OPT_MCU_CH32V307 2200 ///< WCH CH32V307 +#define OPT_MCU_CH32F20X 2210 ///< WCH CH32F20x // NXP LPC MCX -- cgit v1.3.1 From b5b34e73d6cbce1a1d85999ef92712fb98a73a84 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sun, 19 Nov 2023 16:10:16 +0100 Subject: Add dwc2 info of F429. --- src/portable/synopsys/dwc2/dwc2_info.md | 108 ++++++++++++++++---------------- src/portable/synopsys/dwc2/dwc2_info.py | 2 + 2 files changed, 56 insertions(+), 54 deletions(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index 2d8ab067f..f298f6656 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -1,54 +1,54 @@ -| | BCM2711 (Pi4) | EFM32GG FullSpeed | ESP32-S2 | STM32F407 Fullspeed | STM32F407 Highspeed | STM32F411 Fullspeed | STM32F412 Fullspeed | STM32F723 Fullspeed | STM32F723 HighSpeed | STM32F767 Fullspeed | STM32H743 Highspeed | STM32L476 Fullspeed | STM32U5A5 Highspeed | GD32VF103 Fullspeed | XMC4500 | -|:----------------------------|:----------------|:--------------------|:-----------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:-----------| -| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00001200 | 0x00002000 | 0x00003000 | 0x00003100 | 0x00002000 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | -| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | -| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | -| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229DCD20 | 0x229ED520 | 0x229ED520 | 0x229FE1D0 | 0x229ED520 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | -| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | -| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | -| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | -| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | -| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 3 | 5 | 5 | 8 | 5 | 8 | 5 | 8 | 0 | 6 | -| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 7 | 11 | 11 | 15 | 11 | 15 | 11 | 15 | 0 | 13 | -| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - nperiod_tx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - host_period_tx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | -| - dev_token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | -| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x020001E8 | 0x0200D1E8 | 0x0200D1E8 | 0x03EED2E8 | 0x0200D1E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | -| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | -| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | -| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | -| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | -| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | -| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | -| - total_fifo_size | 4080 | 498 | 200 | 512 | 1012 | 512 | 512 | 512 | 1006 | 512 | 952 | 512 | 952 | 0 | 634 | -| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x0FF08030 | 0x17F08030 | 0x17F08030 | 0x23F00030 | 0x17F08030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | -| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - power_optimized | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - reserved7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | -| - service_interval_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - ipg_isoc_en | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - acg_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - reserved13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | -| - utmi_phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 0 | 2 | -| - dev_ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | -| - iddg_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | -| - vbus_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - a_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - b_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | -| - num_dev_in_eps | 15 | 13 | 9 | 7 | 11 | 7 | 11 | 11 | 1 | 11 | 1 | 11 | 1 | 0 | 13 | -| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | -| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | +| | BCM2711 (Pi4) | EFM32GG FullSpeed | ESP32-S2 | STM32F407 Fullspeed | STM32F407 Highspeed | STM32F411 Fullspeed | STM32F412 Fullspeed | STM32F429 Fullspeed | STM32F429 Highspeed | STM32F723 Fullspeed | STM32F723 HighSpeed | STM32F767 Fullspeed | STM32H743 Highspeed | STM32L476 Fullspeed | STM32U5A5 Highspeed | GD32VF103 Fullspeed | XMC4500 | +|:----------------------------|:----------------|:--------------------|:-----------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:-----------| +| guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00001200 | 0x00002000 | 0x00001200 | 0x00001100 | 0x00003000 | 0x00003100 | 0x00002000 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | +| gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54281A | 0x4F54281A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | +| ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | +| ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229DCD20 | 0x229ED520 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229FE1D0 | 0x229ED520 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | +| - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | +| - arch | 2 | 2 | 2 | 0 | 2 | 0 | 0 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | +| - point2point | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | +| - hs_phy_type | 1 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | 2 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | +| - fs_phy_type | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - num_dev_ep | 7 | 6 | 6 | 3 | 5 | 3 | 5 | 3 | 5 | 5 | 8 | 5 | 8 | 5 | 8 | 0 | 6 | +| - num_host_ch | 7 | 13 | 7 | 7 | 11 | 7 | 11 | 7 | 11 | 11 | 15 | 11 | 15 | 11 | 15 | 0 | 13 | +| - period_channel_support | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - enable_dynamic_fifo | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - mul_cpu_int | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - reserved21 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - nperiod_tx_q_depth | 2 | 2 | 1 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - host_period_tx_q_depth | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 2 | 0 | 2 | +| - dev_token_q_depth | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 8 | +| - otg_enable_ic_usb | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| ghwcfg3 | 0x0FF000E8 | 0x01F204E8 | 0x00C804B5 | 0x020001E8 | 0x03F403E8 | 0x020001E8 | 0x0200D1E8 | 0x020001E8 | 0x03F403E8 | 0x0200D1E8 | 0x03EED2E8 | 0x0200D1E8 | 0x03B8D2E8 | 0x0200D1E8 | 0x03B882E8 | 0x00000000 | 0x027A01E5 | +| - xfer_size_width | 8 | 8 | 5 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 8 | 0 | 5 | +| - packet_size_width | 6 | 6 | 3 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 6 | 0 | 6 | +| - otg_enable | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - i2c_enable | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | +| - vendor_ctrl_itf | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | +| - optional_feature_removed | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - synch_reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - otg_adp_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - otg_enable_hsic | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - battery_charger_support | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | +| - lpm_mode | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | +| - total_fifo_size | 4080 | 498 | 200 | 512 | 1012 | 512 | 512 | 512 | 1012 | 512 | 1006 | 512 | 952 | 512 | 952 | 0 | 634 | +| ghwcfg4 | 0x1FF00020 | 0x1BF08030 | 0xD3F0A030 | 0x0FF08030 | 0x17F00030 | 0x0FF08030 | 0x17F08030 | 0x0FF08030 | 0x17F00030 | 0x17F08030 | 0x23F00030 | 0x17F08030 | 0xE3F00030 | 0x17F08030 | 0xE2103E30 | 0x00000000 | 0xDBF08030 | +| - num_dev_period_in_ep | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - power_optimized | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - ahb_freq_min | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - hibernation | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - reserved7 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | +| - service_interval_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - ipg_isoc_en | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - acg_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - reserved13 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | +| - utmi_phy_data_width | 0 | 2 | 2 | 2 | 0 | 2 | 2 | 2 | 0 | 2 | 0 | 2 | 0 | 2 | 0 | 0 | 2 | +| - dev_ctrl_ep_num | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | +| - iddg_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | +| - vbus_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - a_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - b_valid_filter_enabled | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | +| - num_dev_in_eps | 15 | 13 | 9 | 7 | 11 | 7 | 11 | 7 | 11 | 11 | 1 | 11 | 1 | 11 | 1 | 0 | 13 | +| - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | +| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | \ No newline at end of file diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 0af6c4c77..4bcdb4fe5 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -12,6 +12,8 @@ dwc2_reg_value = { 'STM32F407 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030], 'STM32F411 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030], 'STM32F412 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], + 'STM32F429 Fullspeed': [0x1200, 0x4F54281A, 0, 0x229DCD20, 0x20001E8, 0xFF08030], + 'STM32F429 Highspeed': [0x1100, 0x4F54281A, 0, 0x229ED590, 0x3F403E8, 0x17F00030], 'STM32F723 Fullspeed': [0x3000, 0x4F54330A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], 'STM32F723 HighSpeed': [0x3100, 0x4F54330A, 0, 0x229FE1D0, 0x3EED2E8, 0x23F00030], 'STM32F767 Fullspeed': [0x2000, 0x4F54320A, 0, 0x229ED520, 0x200D1E8, 0x17F08030], -- cgit v1.3.1 From 8af470e06d032d1b9731d817741318883c0b8fa0 Mon Sep 17 00:00:00 2001 From: HiFiPhile Date: Sun, 19 Nov 2023 16:19:11 +0100 Subject: Fix CI --- src/portable/synopsys/dwc2/dwc2_info.md | 2 +- src/portable/synopsys/dwc2/dwc2_info.py | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index f298f6656..d093502b0 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -51,4 +51,4 @@ | - dedicated_fifos | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | | - num_dev_in_eps | 15 | 13 | 9 | 7 | 11 | 7 | 11 | 7 | 11 | 11 | 1 | 11 | 1 | 11 | 1 | 0 | 13 | | - dma_desc_enable | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | -| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | \ No newline at end of file +| - dma_dynamic | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 4bcdb4fe5..03c095655 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -154,6 +154,7 @@ def render_md(): # Write the Markdown table to a file with open('dwc2_info.md', 'w') as md_file: md_file.write(df.to_markdown()) + md_file.write('\n') if __name__ == '__main__': -- cgit v1.3.1 From 1f71625a32a77d5fe243f71f9e8be03c9bbc41d1 Mon Sep 17 00:00:00 2001 From: hathach Date: Mon, 20 Nov 2023 21:31:06 +0700 Subject: add tuh_max3421_reg_read(), tuh_max3421_reg_read() for application usage added max3241 for feather m4 and tested --- hw/bsp/samd51/boards/feather_m4_express/board.h | 17 ++++++ hw/bsp/samd51/family.c | 28 +++++++-- src/portable/analog/max3421/hcd_max3421.c | 78 +++++++++++++++---------- 3 files changed, 86 insertions(+), 37 deletions(-) (limited to 'src') diff --git a/hw/bsp/samd51/boards/feather_m4_express/board.h b/hw/bsp/samd51/boards/feather_m4_express/board.h index 4629643fd..474163c06 100644 --- a/hw/bsp/samd51/boards/feather_m4_express/board.h +++ b/hw/bsp/samd51/boards/feather_m4_express/board.h @@ -31,6 +31,8 @@ extern "C" { #endif +#define _PINNUM(port, pin) ((port)*32 + (pin)) + // LED #define LED_PIN 23 #define LED_STATE_ON 1 @@ -43,6 +45,21 @@ #define UART_TX_PIN (32 + 17) #define UART_RX_PIN (32 + 16) +// SPI for USB host shield +#define MAX3421_SERCOM_ID 1 // SERCOM2 +#define MAX3421_SERCOM_FUNCTION 2 // function C + +#define MAX3421_SCK_PIN _PINNUM(0, 17) +#define MAX3421_MOSI_PIN _PINNUM(1, 23) +#define MAX3421_MISO_PIN _PINNUM(1, 22) +#define MAX3421_TX_PAD 2 // MOSI = PAD_3, SCK = PAD_1 +#define MAX3421_RX_PAD 2 // MISO = PAD_2 + +#define MAX3421_CS_PIN 21 // D11 + +#define MAX3421_INTR_PIN 20 // D10 +#define MAX3421_INTR_EIC_ID 4 // EIC4 + #ifdef __cplusplus } #endif diff --git a/hw/bsp/samd51/family.c b/hw/bsp/samd51/family.c index bca18e1a2..2a2aee982 100644 --- a/hw/bsp/samd51/family.c +++ b/hw/bsp/samd51/family.c @@ -76,12 +76,18 @@ void USB_3_Handler(void) { // Implementation //--------------------------------------------------------------------+ -#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 +#if CFG_TUH_ENABLED && CFG_TUH_MAX3421 + +// API to read MAX3421's register. Implemented by TinyUSB +extern uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr); + +// API to write MAX3421's register. Implemented by TinyUSB +extern bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr); + #define MAX3421_SERCOM TU_XSTRCAT(SERCOM, MAX3421_SERCOM_ID) #define MAX3421_EIC_Handler TU_XSTRCAT3(EIC_, MAX3421_INTR_EIC_ID, _Handler) static void max3421_init(void); - #endif void board_init(void) { @@ -136,11 +142,23 @@ void board_init(void) { gpio_set_pin_function(PIN_PA24, PINMUX_PA24H_USB_DM); gpio_set_pin_function(PIN_PA25, PINMUX_PA25H_USB_DP); -#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 +#if CFG_TUH_ENABLED && CFG_TUH_MAX3421 max3421_init(); #endif } +void board_init_after_tusb(void) { +#if CFG_TUH_ENABLED && CFG_TUH_MAX3421 + // FeatherWing MAX3421E use MAX3421E's GPIO0 for VBUS enable + enum { + IOPINS1_ADDR = 20u << 3, // 0xA0 + }; + + uint8_t rhport = 1; + tuh_max3421_reg_write(rhport, IOPINS1_ADDR, 0x01, false); +#endif +} + //--------------------------------------------------------------------+ // Board porting API //--------------------------------------------------------------------+ @@ -182,7 +200,7 @@ uint32_t board_millis(void) { //--------------------------------------------------------------------+ // API: SPI transfer with MAX3421E, must be implemented by application //--------------------------------------------------------------------+ -#if CFG_TUH_ENABLED && defined(CFG_TUH_MAX3421) && CFG_TUH_MAX3421 +#if CFG_TUH_ENABLED && CFG_TUH_MAX3421 static void max3421_init(void) { //------------- SPI Init -------------// @@ -262,7 +280,7 @@ static void max3421_init(void) { // Enable the SPI module sercom->SPI.CTRLA.bit.ENABLE = 1; - while (sercom->SPI.SYNCBUSY.bit.ENABLE); + while (sercom->SPI.SYNCBUSY.bit.ENABLE) {} //------------- External Interrupt -------------// diff --git a/src/portable/analog/max3421/hcd_max3421.c b/src/portable/analog/max3421/hcd_max3421.c index 65f87f7c6..2abd74d51 100644 --- a/src/portable/analog/max3421/hcd_max3421.c +++ b/src/portable/analog/max3421/hcd_max3421.c @@ -54,6 +54,12 @@ enum { CPUCTL_ADDR = 16u << 3, // 0x80 PINCTL_ADDR = 17u << 3, // 0x88 REVISION_ADDR = 18u << 3, // 0x90 + // 19 is not used + IOPINS1_ADDR = 20u << 3, // 0xA0 + IOPINS2_ADDR = 21u << 3, // 0xA8 + GPINIRQ_ADDR = 22u << 3, // 0xB0 + GPINIEN_ADDR = 23u << 3, // 0xB8 + GPINPOL_ADDR = 24u << 3, // 0xC0 HIRQ_ADDR = 25u << 3, // 0xC8 HIEN_ADDR = 26u << 3, // 0xD0 MODE_ADDR = 27u << 3, // 0xD8 @@ -207,7 +213,9 @@ typedef struct { static max3421_data_t _hcd_data; //--------------------------------------------------------------------+ -// API: SPI transfer with MAX3421E, must be implemented by application +// API: SPI transfer with MAX3421E +// - spi_cs_api(), spi_xfer_api(), int_api(): must be implemented by application +// - reg_read(), reg_write(): is implemented by this driver, can be used by application //--------------------------------------------------------------------+ // API to control MAX3421 SPI CS @@ -220,11 +228,18 @@ extern bool tuh_max3421_spi_xfer_api(uint8_t rhport, uint8_t const* tx_buf, uint // API to enable/disable MAX3421 INTR pin interrupt extern void tuh_max3421_int_api(uint8_t rhport, bool enabled); +// API to read MAX3421's register. Implemented by TinyUSB +uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr); + +// API to write MAX3421's register. Implemented by TinyUSB +bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr); + //--------------------------------------------------------------------+ -// SPI Helper +// SPI Commands and Helper //--------------------------------------------------------------------+ -static void handle_connect_irq(uint8_t rhport, bool in_isr); -static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr); + +#define reg_read tuh_max3421_reg_read +#define reg_write tuh_max3421_reg_write static void max3421_spi_lock(uint8_t rhport, bool in_isr) { // disable interrupt and mutex lock (for pre-emptive RTOS) if not in_isr @@ -248,61 +263,60 @@ static void max3421_spi_unlock(uint8_t rhport, bool in_isr) { } } -static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint16_t len, bool in_isr) { - uint8_t hirq; - reg |= CMDBYTE_WRITE; +uint8_t tuh_max3421_reg_read(uint8_t rhport, uint8_t reg, bool in_isr) { + uint8_t tx_buf[2] = {reg, 0}; + uint8_t rx_buf[2] = {0, 0}; max3421_spi_lock(rhport, in_isr); - - tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); - _hcd_data.hirq = hirq; - tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len); - + bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2); max3421_spi_unlock(rhport, in_isr); + _hcd_data.hirq = rx_buf[0]; + return ret ? rx_buf[1] : 0; } -static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) { - uint8_t hirq; - uint8_t const reg = RCVVFIFO_ADDR; +bool tuh_max3421_reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr) { + uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data}; + uint8_t rx_buf[2] = {0, 0}; max3421_spi_lock(rhport, in_isr); + bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2); + max3421_spi_unlock(rhport, in_isr); - tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); - _hcd_data.hirq = hirq; - tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len); + // HIRQ register since we are in full-duplex mode + _hcd_data.hirq = rx_buf[0]; - max3421_spi_unlock(rhport, in_isr); + return ret; } -static void reg_write(uint8_t rhport, uint8_t reg, uint8_t data, bool in_isr) { - uint8_t tx_buf[2] = {reg | CMDBYTE_WRITE, data}; - uint8_t rx_buf[2] = {0, 0}; +static void fifo_write(uint8_t rhport, uint8_t reg, uint8_t const * buffer, uint16_t len, bool in_isr) { + uint8_t hirq; + reg |= CMDBYTE_WRITE; max3421_spi_lock(rhport, in_isr); - tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2); + tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); + _hcd_data.hirq = hirq; + tuh_max3421_spi_xfer_api(rhport, buffer, NULL, len); max3421_spi_unlock(rhport, in_isr); - // HIRQ register since we are in full-duplex mode - _hcd_data.hirq = rx_buf[0]; } -static uint8_t reg_read(uint8_t rhport, uint8_t reg, bool in_isr) { - uint8_t tx_buf[2] = {reg, 0}; - uint8_t rx_buf[2] = {0, 0}; +static void fifo_read(uint8_t rhport, uint8_t * buffer, uint16_t len, bool in_isr) { + uint8_t hirq; + uint8_t const reg = RCVVFIFO_ADDR; max3421_spi_lock(rhport, in_isr); - bool ret = tuh_max3421_spi_xfer_api(rhport, tx_buf, rx_buf, 2); + tuh_max3421_spi_xfer_api(rhport, ®, &hirq, 1); + _hcd_data.hirq = hirq; + tuh_max3421_spi_xfer_api(rhport, NULL, buffer, len); max3421_spi_unlock(rhport, in_isr); - - _hcd_data.hirq = rx_buf[0]; - return ret ? rx_buf[1] : 0; } +//------------- register write helper -------------// static inline void hirq_write(uint8_t rhport, uint8_t data, bool in_isr) { reg_write(rhport, HIRQ_ADDR, data, in_isr); // HIRQ write 1 is clear -- cgit v1.3.1 From aedc92f2d31af6209b00e8a5d7abbfec02ed979b Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Nov 2023 11:25:55 +0700 Subject: fix typo in cdc line coding enum --- examples/host/cdc_msc_hid/src/tusb_config.h | 2 +- examples/host/cdc_msc_hid_freertos/src/tusb_config.h | 2 +- src/class/cdc/cdc.h | 20 +++++++++++--------- src/class/cdc/cdc_host.h | 2 +- 4 files changed, 14 insertions(+), 12 deletions(-) (limited to 'src') diff --git a/examples/host/cdc_msc_hid/src/tusb_config.h b/examples/host/cdc_msc_hid/src/tusb_config.h index c8e9138e3..a53000a11 100644 --- a/examples/host/cdc_msc_hid/src/tusb_config.h +++ b/examples/host/cdc_msc_hid/src/tusb_config.h @@ -118,7 +118,7 @@ // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t // bit rate = 115200, 1 stop bit, no parity, 8 bit data width -#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } +#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } #ifdef __cplusplus diff --git a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h index 1bed9a9b3..ba23301ed 100644 --- a/examples/host/cdc_msc_hid_freertos/src/tusb_config.h +++ b/examples/host/cdc_msc_hid_freertos/src/tusb_config.h @@ -123,7 +123,7 @@ // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t // bit rate = 115200, 1 stop bit, no parity, 8 bit data width -#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } +#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } #ifdef __cplusplus diff --git a/src/class/cdc/cdc.h b/src/class/cdc/cdc.h index 4658e43af..deec32ae4 100644 --- a/src/class/cdc/cdc.h +++ b/src/class/cdc/cdc.h @@ -182,21 +182,23 @@ typedef enum CDC_REQUEST_MDLM_SEMANTIC_MODEL = 0x60, }cdc_management_request_t; -enum -{ +enum { CDC_CONTROL_LINE_STATE_DTR = 0x01, CDC_CONTROL_LINE_STATE_RTS = 0x02, }; -enum -{ - CDC_LINE_CONDING_STOP_BITS_1 = 0, // 1 bit - CDC_LINE_CONDING_STOP_BITS_1_5 = 1, // 1.5 bits - CDC_LINE_CONDING_STOP_BITS_2 = 2, // 2 bits +enum { + CDC_LINE_CODING_STOP_BITS_1 = 0, // 1 bit + CDC_LINE_CODING_STOP_BITS_1_5 = 1, // 1.5 bits + CDC_LINE_CODING_STOP_BITS_2 = 2, // 2 bits }; -enum -{ +// TODO Backward compatible for typos. Maybe removed in the future release +#define CDC_LINE_CONDING_STOP_BITS_1 CDC_LINE_CODING_STOP_BITS_1 +#define CDC_LINE_CONDING_STOP_BITS_1_5 CDC_LINE_CODING_STOP_BITS_1_5 +#define CDC_LINE_CONDING_STOP_BITS_2 CDC_LINE_CODING_STOP_BITS_2 + +enum { CDC_LINE_CODING_PARITY_NONE = 0, CDC_LINE_CODING_PARITY_ODD = 1, CDC_LINE_CODING_PARITY_EVEN = 2, diff --git a/src/class/cdc/cdc_host.h b/src/class/cdc/cdc_host.h index 19552f1ee..9e5edd94e 100644 --- a/src/class/cdc/cdc_host.h +++ b/src/class/cdc/cdc_host.h @@ -44,7 +44,7 @@ // Set Line Coding on enumeration/mounted, value for cdc_line_coding_t //#ifndef CFG_TUH_CDC_LINE_CODING_ON_ENUM -//#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CONDING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } +//#define CFG_TUH_CDC_LINE_CODING_ON_ENUM { 115200, CDC_LINE_CODING_STOP_BITS_1, CDC_LINE_CODING_PARITY_NONE, 8 } //#endif // RX FIFO size -- cgit v1.3.1 From 025ffa200c5508c23e76316045792af4f7728da5 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Nov 2023 17:36:52 +0700 Subject: add spec version to dwc2 info --- src/portable/synopsys/dwc2/dwc2_info.md | 1 + src/portable/synopsys/dwc2/dwc2_info.py | 14 +- src/portable/synopsys/dwc2/hwcfg_list.md | 777 ------------------------------- 3 files changed, 12 insertions(+), 780 deletions(-) delete mode 100644 src/portable/synopsys/dwc2/hwcfg_list.md (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_info.md b/src/portable/synopsys/dwc2/dwc2_info.md index d093502b0..8690a0755 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.md +++ b/src/portable/synopsys/dwc2/dwc2_info.md @@ -2,6 +2,7 @@ |:----------------------------|:----------------|:--------------------|:-----------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:----------------------|:-----------| | guid | 0x2708A000 | 0x00000000 | 0x00000000 | 0x00001200 | 0x00001100 | 0x00001200 | 0x00002000 | 0x00001200 | 0x00001100 | 0x00003000 | 0x00003100 | 0x00002000 | 0x00002300 | 0x00002000 | 0x00005000 | 0x00001000 | 0x00AEC000 | | gsnpsid | 0x4F54280A | 0x4F54330A | 0x4F54400A | 0x4F54281A | 0x4F54281A | 0x4F54281A | 0x4F54320A | 0x4F54281A | 0x4F54281A | 0x4F54330A | 0x4F54330A | 0x4F54320A | 0x4F54330A | 0x4F54310A | 0x4F54411A | 0x00000000 | 0x4F54292A | +| - specs version | 2.80a | 3.30a | 4.00a | 2.81a | 2.81a | 2.81a | 3.20a | 2.81a | 2.81a | 3.30a | 3.30a | 3.20a | 3.30a | 3.10a | 4.11a | 0.00W | 2.92a | | ghwcfg1 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | 0x00000000 | | ghwcfg2 | 0x228DDD50 | 0x228F5910 | 0x224DD930 | 0x229DCD20 | 0x229ED590 | 0x229DCD20 | 0x229ED520 | 0x229DCD20 | 0x229ED590 | 0x229ED520 | 0x229FE1D0 | 0x229ED520 | 0x229FE190 | 0x229ED520 | 0x228FE052 | 0x00000000 | 0x228F5930 | | - op_mode | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | diff --git a/src/portable/synopsys/dwc2/dwc2_info.py b/src/portable/synopsys/dwc2/dwc2_info.py index 03c095655..55bec3d23 100644 --- a/src/portable/synopsys/dwc2/dwc2_info.py +++ b/src/portable/synopsys/dwc2/dwc2_info.py @@ -36,6 +36,7 @@ dwc2_reg_value = { # }, dwc2_info = {key: {field: value for field, value in zip(dwc2_reg_list, values)} for key, values in dwc2_reg_value.items()} + class GHWCFG2(ctypes.LittleEndianStructure): _fields_ = [ ("op_mode", ctypes.c_uint32, 3), @@ -130,13 +131,20 @@ def render_md(): # Create an empty list to hold the dictionaries dwc2_info_list = [] - #Iterate over the dwc2_info dictionary and extract fields + # Iterate over the dwc2_info dictionary and extract fields for device, reg_values in dwc2_info.items(): entry_dict = {"Device": device} for r_name, r_value in reg_values.items(): entry_dict[r_name] = f"0x{r_value:08X}" - # Print bit-field values - if r_name.upper() in globals(): + + if r_name == 'gsnpsid': + # Get dwc2 specs version + major = ((r_value >> 8) >> 4) & 0x0F + minor = (r_value >> 4) & 0xFF + patch = chr((r_value & 0x0F) + ord('a') - 0xA) + entry_dict[f' - specs version'] = f"{major:X}.{minor:02X}{patch}" + elif r_name.upper() in globals(): + # Get bit-field values which exist as ctypes structures class_name = globals()[r_name.upper()] ghwcfg = class_name.from_buffer_copy(r_value.to_bytes(4, byteorder='little')) for field_name, field_type, _ in class_name._fields_: diff --git a/src/portable/synopsys/dwc2/hwcfg_list.md b/src/portable/synopsys/dwc2/hwcfg_list.md deleted file mode 100644 index b5590da00..000000000 --- a/src/portable/synopsys/dwc2/hwcfg_list.md +++ /dev/null @@ -1,777 +0,0 @@ -# DWC2 Hardware Configuration Registers - -## Broadcom BCM2711 (Pi4) - -dwc2->guid = 2708A000 -dwc2->gsnpsid = 4F54280A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 228DDD50 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 2 -hw_cfg2->point2point = 0 -hw_cfg2->hs_phy_type = 1 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 7 -hw_cfg2->num_host_ch = 7 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 0 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = FF000E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 0 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 0 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 0 -hw_cfg3->lpm_mode = 0 -hw_cfg3->total_fifo_size = 4080 - -dwc2->ghwcfg4 = 1FF00020 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 0 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 0 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 15 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## EFM32GG FS - -dwc2->guid = 0 -dwc2->gsnpsid = 4F54330A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 228F5910 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 2 -hw_cfg2->point2point = 0 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 6 -hw_cfg2->num_host_ch = 13 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 0 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 1F204E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 0 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 1 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 0 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 0 -hw_cfg3->lpm_mode = 0 -hw_cfg3->total_fifo_size = 498 - -dwc2->ghwcfg4 = 1BF08030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 2 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 13 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## ESP32-S2 Fullspeed - -dwc2->guid = 0 -dwc2->gsnpsid = 4F54400A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 224DD930 -hw_cfg2->op_mode = 2 -hw_cfg2->arch = 3 -hw_cfg2->point2point = 0 -hw_cfg2->hs_phy_type = 1 -hw_cfg2->fs_phy_type = 2 -hw_cfg2->num_dev_ep = 6 -hw_cfg2->num_host_ch = 9 -hw_cfg2->period_channel_support = 0 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 1 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 22 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = C804B5 -hw_cfg3->xfer_size_width = 10 -hw_cfg3->packet_size_width = 5 -hw_cfg3->otg_enable = 0 -hw_cfg3->i2c_enable = 0 -hw_cfg3->vendor_ctrl_itf = 1 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 1 -hw_cfg3->otg_adp_support = 1 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 1 -hw_cfg3->lpm_mode = 0 -hw_cfg3->total_fifo_size = 23130 - -dwc2->ghwcfg4 = D3F0A030 -hw_cfg4->num_dev_period_in_ep = 10 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 0 -hw_cfg4->hibernation = 1 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 1 -hw_cfg4->acg_enable = 1 -hw_cfg4->utmi_phy_data_width = 1 -hw_cfg4->dev_ctrl_ep_num = 10 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 0 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 0 -hw_cfg4->dedicated_fifos = 0 -hw_cfg4->num_dev_in_eps = 13 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 1 - -## STM32F407 and STM32F207 - -STM32F407 and STM32F207 are exactly the same - -### STM32F407 Fullspeed - -dwc2->guid = 1200 -dwc2->gsnpsid = 4F54281A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229DCD20 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 0 -hw_cfg2->point2point = 1 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 3 -hw_cfg2->num_host_ch = 7 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 20001E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 1 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 0 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 0 -hw_cfg3->lpm_mode = 0 -hw_cfg3->total_fifo_size = 512 - -dwc2->ghwcfg4 = FF08030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 2 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 7 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -### STM32F407 Highspeed - -dwc2->guid = 1100 -dwc2->gsnpsid = 4F54281A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229ED590 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 2 -hw_cfg2->point2point = 0 -hw_cfg2->hs_phy_type = 2 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 5 -hw_cfg2->num_host_ch = 11 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 3F403E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 1 -hw_cfg3->vendor_ctrl_itf = 1 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 0 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 0 -hw_cfg3->lpm_mode = 0 -hw_cfg3->total_fifo_size = 1012 - -dwc2->ghwcfg4 = 17F00030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 0 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 11 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## STM32F411 Fullspeed - -dwc2->guid = 1200 -dwc2->gsnpsid = 4F54281A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229DCD20 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 0 -hw_cfg2->point2point = 1 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 3 -hw_cfg2->num_host_ch = 7 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 20001E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 1 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 0 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 0 -hw_cfg3->lpm_mode = 0 -hw_cfg3->total_fifo_size = 512 - -dwc2->ghwcfg4 = FF08030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 2 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 7 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## STM32F412 FS - -dwc2->guid = 2000 -dwc2->gsnpsid = 4F54320A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229ED520 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 0 -hw_cfg2->point2point = 1 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 5 -hw_cfg2->num_host_ch = 11 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 200D1E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 1 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 1 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 1 -hw_cfg3->lpm_mode = 1 -hw_cfg3->total_fifo_size = 512 - -dwc2->ghwcfg4 = 17F08030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 2 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 11 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## STM32F723 - -### STM32F723 HighSpeed - -dwc2->guid = 3100 -dwc2->gsnpsid = 4F54330A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229FE1D0 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 2 -hw_cfg2->point2point = 0 -hw_cfg2->hs_phy_type = 3 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 8 -hw_cfg2->num_host_ch = 15 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 3EED2E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 0 -hw_cfg3->vendor_ctrl_itf = 1 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 1 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 1 -hw_cfg3->lpm_mode = 1 -hw_cfg3->total_fifo_size = 1006 - -dwc2->ghwcfg4 = 23F00030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 0 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 1 -hw_cfg4->dma_desc_enable = 1 -hw_cfg4->dma_dynamic = 0 - -### STM32F723 Fullspeed - -dwc2->guid = 3000 -dwc2->gsnpsid = 4F54330A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229ED520 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 0 -hw_cfg2->point2point = 1 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 5 -hw_cfg2->num_host_ch = 11 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 200D1E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 1 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 1 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 1 -hw_cfg3->lpm_mode = 1 -hw_cfg3->total_fifo_size = 512 - -dwc2->ghwcfg4 = 17F08030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 2 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 11 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## STM32F767 FS - -dwc2->guid = 2000 -dwc2->gsnpsid = 4F54320A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229ED520 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 0 -hw_cfg2->point2point = 1 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 5 -hw_cfg2->num_host_ch = 11 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 200D1E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 1 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 1 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 1 -hw_cfg3->lpm_mode = 1 -hw_cfg3->total_fifo_size = 512 - -dwc2->ghwcfg4 = 17F08030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 2 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 11 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## STM32H743 (both cores HS) - -dwc2->guid = 2300 -dwc2->gsnpsid = 4F54330A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229FE190 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 2 -hw_cfg2->point2point = 0 -hw_cfg2->hs_phy_type = 2 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 8 -hw_cfg2->num_host_ch = 15 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 3B8D2E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 0 -hw_cfg3->vendor_ctrl_itf = 1 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 1 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 1 -hw_cfg3->lpm_mode = 1 -hw_cfg3->total_fifo_size = 952 - -dwc2->ghwcfg4 = E3F00030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 0 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 1 -hw_cfg4->dma_desc_enable = 1 -hw_cfg4->dma_dynamic = 1 - -## STM32L476 FS - -dwc2->guid = 2000 -dwc2->gsnpsid = 4F54310A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 229ED520 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 0 -hw_cfg2->point2point = 1 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 5 -hw_cfg2->num_host_ch = 11 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 1 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 200D1E8 -hw_cfg3->xfer_size_width = 8 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 1 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 1 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 1 -hw_cfg3->lpm_mode = 1 -hw_cfg3->total_fifo_size = 512 - -dwc2->ghwcfg4 = 17F08030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 2 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 11 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## GD32VF103 Fullspeed - -dwc2->guid = 1000 -dwc2->gsnpsid = 0 -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 0 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 0 -hw_cfg2->point2point = 0 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 0 -hw_cfg2->num_dev_ep = 0 -hw_cfg2->num_host_ch = 0 -hw_cfg2->period_channel_support = 0 -hw_cfg2->enable_dynamic_fifo = 0 -hw_cfg2->mul_cpu_int = 0 -hw_cfg2->nperiod_tx_q_depth = 0 -hw_cfg2->host_period_tx_q_depth = 0 -hw_cfg2->dev_token_q_depth = 0 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 0 -hw_cfg3->xfer_size_width = 0 -hw_cfg3->packet_size_width = 0 -hw_cfg3->otg_enable = 0 -hw_cfg3->i2c_enable = 0 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 0 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 0 -hw_cfg3->lpm_mode = 0 -hw_cfg3->total_fifo_size = 0 - -dwc2->ghwcfg4 = 0 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 0 -hw_cfg4->ahb_freq_min = 0 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 0 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 0 -hw_cfg4->vbus_valid_filter_enabled = 0 -hw_cfg4->a_valid_filter_enabled = 0 -hw_cfg4->b_valid_filter_enabled = 0 -hw_cfg4->dedicated_fifos = 0 -hw_cfg4->num_dev_in_eps = 0 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 0 - -## XMC4500 - -dwc2->guid = AEC000 -dwc2->gsnpsid = 4F54292A -dwc2->ghwcfg1 = 0 - -dwc2->ghwcfg2 = 228F5930 -hw_cfg2->op_mode = 0 -hw_cfg2->arch = 2 -hw_cfg2->point2point = 1 -hw_cfg2->hs_phy_type = 0 -hw_cfg2->fs_phy_type = 1 -hw_cfg2->num_dev_ep = 6 -hw_cfg2->num_host_ch = 13 -hw_cfg2->period_channel_support = 1 -hw_cfg2->enable_dynamic_fifo = 1 -hw_cfg2->mul_cpu_int = 0 -hw_cfg2->nperiod_tx_q_depth = 2 -hw_cfg2->host_period_tx_q_depth = 2 -hw_cfg2->dev_token_q_depth = 8 -hw_cfg2->otg_enable_ic_usb = 0 - -dwc2->ghwcfg3 = 27A01E5 -hw_cfg3->xfer_size_width = 5 -hw_cfg3->packet_size_width = 6 -hw_cfg3->otg_enable = 1 -hw_cfg3->i2c_enable = 1 -hw_cfg3->vendor_ctrl_itf = 0 -hw_cfg3->optional_feature_removed = 0 -hw_cfg3->synch_reset = 0 -hw_cfg3->otg_adp_support = 0 -hw_cfg3->otg_enable_hsic = 0 -hw_cfg3->battery_charger_support = 0 -hw_cfg3->lpm_mode = 0 -hw_cfg3->total_fifo_size = 634 - -dwc2->ghwcfg4 = DBF08030 -hw_cfg4->num_dev_period_in_ep = 0 -hw_cfg4->power_optimized = 1 -hw_cfg4->ahb_freq_min = 1 -hw_cfg4->hibernation = 0 -hw_cfg4->service_interval_mode = 0 -hw_cfg4->ipg_isoc_en = 0 -hw_cfg4->acg_enable = 0 -hw_cfg4->utmi_phy_data_width = 2 -hw_cfg4->dev_ctrl_ep_num = 0 -hw_cfg4->iddg_filter_enabled = 1 -hw_cfg4->vbus_valid_filter_enabled = 1 -hw_cfg4->a_valid_filter_enabled = 1 -hw_cfg4->b_valid_filter_enabled = 1 -hw_cfg4->dedicated_fifos = 1 -hw_cfg4->num_dev_in_eps = 13 -hw_cfg4->dma_desc_enable = 0 -hw_cfg4->dma_dynamic = 1 -- cgit v1.3.1 From 01f22a9e25c9581c1a38559737a7ca7d1fc22c15 Mon Sep 17 00:00:00 2001 From: hathach Date: Wed, 22 Nov 2023 22:50:10 +0700 Subject: fix h7 running on fullspeed phy has issue with WFI if not disable ULPI clock --- src/portable/synopsys/dwc2/dwc2_stm32.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'src') diff --git a/src/portable/synopsys/dwc2/dwc2_stm32.h b/src/portable/synopsys/dwc2/dwc2_stm32.h index 2070c3943..dd78ccd06 100644 --- a/src/portable/synopsys/dwc2/dwc2_stm32.h +++ b/src/portable/synopsys/dwc2/dwc2_stm32.h @@ -145,6 +145,22 @@ static inline void dwc2_phy_init(dwc2_regs_t* dwc2, uint8_t hs_phy_type) { if (hs_phy_type == HS_PHY_TYPE_NONE) { // Enable on-chip FS PHY dwc2->stm32_gccfg |= STM32_GCCFG_PWRDWN; + + // https://community.st.com/t5/stm32cubemx-mcus/why-stm32h743-usb-fs-doesn-t-work-if-freertos-tickless-idle/m-p/349480#M18867 + // H7 running on full-speed phy need to disable ULPI clock in sleep mode. + // Otherwise, USB won't work when mcu executing WFI/WFE instruction i.e tick-less RTOS. + // Note: there may be other family that is affected by this, but only H7 is tested so far + #if defined(USB_OTG_FS_PERIPH_BASE) && defined(RCC_AHB1LPENR_USB2OTGFSULPILPEN) + if ( USB_OTG_FS_PERIPH_BASE == (uint32_t) dwc2 ) { + RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB2OTGFSULPILPEN; + } + #endif + + #if defined(USB_OTG_HS_PERIPH_BASE) && defined(RCC_AHB1LPENR_USB1OTGHSULPILPEN) + if ( USB_OTG_HS_PERIPH_BASE == (uint32_t) dwc2 ) { + RCC->AHB1LPENR &= ~RCC_AHB1LPENR_USB1OTGHSULPILPEN; + } + #endif } else { #if CFG_TUSB_MCU != OPT_MCU_STM32U5 // Disable FS PHY, TODO on U5A5 (dwc2 4.11a) 16th bit is 'Host CDP behavior enable' -- cgit v1.3.1 From 54356a719e3968702d86346ec6305679ebd9dd0f Mon Sep 17 00:00:00 2001 From: hathach Date: Thu, 23 Nov 2023 17:53:17 +0700 Subject: minor-update --- hw/bsp/board.c | 20 ++++++++---- hw/bsp/family_support.cmake | 5 +-- hw/bsp/nrf/family.cmake | 4 +-- hw/bsp/nrf/family.mk | 3 ++ hw/bsp/stm32h7/family.cmake | 4 +-- src/osal/osal_none.h | 64 ++++++++++++++----------------------- tools/cmake/toolchain/arm_gcc.cmake | 2 +- 7 files changed, 47 insertions(+), 55 deletions(-) (limited to 'src') diff --git a/hw/bsp/board.c b/hw/bsp/board.c index 562792625..23b4b6628 100644 --- a/hw/bsp/board.c +++ b/hw/bsp/board.c @@ -44,13 +44,12 @@ // If using SES IDE, use the Syscalls/SEGGER_RTT_Syscalls_SES.c instead #if !(defined __SES_ARM) && !(defined __SES_RISCV) && !(defined __CROSSWORKS_ARM) - #include "SEGGER_RTT.h" -TU_ATTR_USED int sys_write(int fhdl, const void *buf, size_t count) { +TU_ATTR_USED int sys_write(int fhdl, const char *buf, size_t count) { (void) fhdl; SEGGER_RTT_Write(0, (const char *) buf, (int) count); - return count; + return (int) count; } TU_ATTR_USED int sys_read(int fhdl, char *buf, size_t count) { @@ -63,10 +62,9 @@ TU_ATTR_USED int sys_read(int fhdl, char *buf, size_t count) { #elif defined(LOGGER_SWO) // Logging with SWO for ARM Cortex - #include "board_mcu.h" -TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) { +TU_ATTR_USED int sys_write (int fhdl, const char *buf, size_t count) { (void) fhdl; uint8_t const* buf8 = (uint8_t const*) buf; @@ -87,7 +85,7 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) { #else // Default logging with on-board UART -TU_ATTR_USED int sys_write (int fhdl, const void *buf, size_t count) { +TU_ATTR_USED int sys_write (int fhdl, const char *buf, size_t count) { (void) fhdl; return board_uart_write(buf, (int) count); } @@ -100,6 +98,16 @@ TU_ATTR_USED int sys_read (int fhdl, char *buf, size_t count) { #endif +//TU_ATTR_USED int _close(int fhdl) { +// (void) fhdl; +// return 0; +//} + +//TU_ATTR_USED int _fstat(int file, struct stat *st) { +// memset(st, 0, sizeof(*st)); +// st->st_mode = S_IFCHR; +//} + int board_getchar(void) { char c; return (sys_read(0, &c, 1) > 0) ? (int) c : (-1); diff --git a/hw/bsp/family_support.cmake b/hw/bsp/family_support.cmake index eec42160e..930237fea 100644 --- a/hw/bsp/family_support.cmake +++ b/hw/bsp/family_support.cmake @@ -201,6 +201,9 @@ function(family_configure_common TARGET RTOS) # Generate linker map file if (CMAKE_C_COMPILER_ID STREQUAL "GNU") target_link_options(${TARGET} PUBLIC "LINKER:-Map=$.map") + if (CMAKE_C_COMPILER_VERSION VERSION_GREATER_EQUAL 12.0) + target_link_options(${TARGET} PUBLIC "LINKER:--no-warn-rwx-segments") + endif () endif() # ETM Trace option @@ -289,13 +292,11 @@ function(family_configure_device_example TARGET RTOS) family_configure_example(${TARGET} ${RTOS}) endfunction() - # Configure host example with RTOS function(family_configure_host_example TARGET RTOS) family_configure_example(${TARGET} ${RTOS}) endfunction() - # Configure host + device example with RTOS function(family_configure_dual_usb_example TARGET RTOS) family_configure_example(${TARGET} ${RTOS}) diff --git a/hw/bsp/nrf/family.cmake b/hw/bsp/nrf/family.cmake index 99d9ac6dd..8cee2b433 100644 --- a/hw/bsp/nrf/family.cmake +++ b/hw/bsp/nrf/family.cmake @@ -84,9 +84,7 @@ function(add_board_target BOARD_TARGET) # linker file "LINKER:--script=${LD_FILE_GNU}" -L${NRFX_DIR}/mdk - # nanolib - --specs=nosys.specs - --specs=nano.specs + --specs=nosys.specs --specs=nano.specs ) elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") target_link_options(${BOARD_TARGET} PUBLIC diff --git a/hw/bsp/nrf/family.mk b/hw/bsp/nrf/family.mk index df22477df..29802dc37 100644 --- a/hw/bsp/nrf/family.mk +++ b/hw/bsp/nrf/family.mk @@ -12,6 +12,9 @@ CFLAGS += \ -DCFG_TUSB_MCU=OPT_MCU_NRF5X \ -DCONFIG_GPIO_AS_PINRESET +#CFLAGS += -nostdlib +#CFLAGS += -D__START=main + # suppress warning caused by vendor mcu driver CFLAGS += \ -Wno-error=undef \ diff --git a/hw/bsp/stm32h7/family.cmake b/hw/bsp/stm32h7/family.cmake index c08857a50..2d6ec76c8 100644 --- a/hw/bsp/stm32h7/family.cmake +++ b/hw/bsp/stm32h7/family.cmake @@ -66,9 +66,7 @@ function(add_board_target BOARD_TARGET) target_link_options(${BOARD_TARGET} PUBLIC "LINKER:--script=${LD_FILE_GNU}" -nostartfiles - # nanolib - --specs=nosys.specs - --specs=nano.specs + --specs=nosys.specs --specs=nano.specs ) elseif (CMAKE_C_COMPILER_ID STREQUAL "IAR") target_link_options(${BOARD_TARGET} PUBLIC diff --git a/src/osal/osal_none.h b/src/osal/osal_none.h index 76e77c25d..a07d39828 100644 --- a/src/osal/osal_none.h +++ b/src/osal/osal_none.h @@ -24,11 +24,11 @@ * This file is part of the TinyUSB stack. */ -#ifndef _TUSB_OSAL_NONE_H_ -#define _TUSB_OSAL_NONE_H_ +#ifndef TUSB_OSAL_NONE_H_ +#define TUSB_OSAL_NONE_H_ #ifdef __cplusplus - extern "C" { +extern "C" { #endif //--------------------------------------------------------------------+ @@ -43,39 +43,34 @@ TU_ATTR_WEAK void osal_task_delay(uint32_t msec); //--------------------------------------------------------------------+ // Binary Semaphore API //--------------------------------------------------------------------+ -typedef struct -{ +typedef struct { volatile uint16_t count; -}osal_semaphore_def_t; +} osal_semaphore_def_t; typedef osal_semaphore_def_t* osal_semaphore_t; -TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) -{ +TU_ATTR_ALWAYS_INLINE static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef) { semdef->count = 0; return semdef; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) { (void) in_isr; sem_hdl->count++; return true; } // TODO blocking for now -TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) { (void) msec; - while (sem_hdl->count == 0) { } + while (sem_hdl->count == 0) {} sem_hdl->count--; return true; } -TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) -{ +TU_ATTR_ALWAYS_INLINE static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl) { sem_hdl->count = 0; } @@ -90,19 +85,16 @@ typedef osal_semaphore_t osal_mutex_t; // Note: multiple cores MCUs usually do provide IPC API for mutex // or we can use std atomic function -TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) -{ +TU_ATTR_ALWAYS_INLINE static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef) { mdef->count = 1; return mdef; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec) { return osal_semaphore_wait(mutex_hdl, msec); } -TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) { return osal_semaphore_post(mutex_hdl, false); } @@ -119,11 +111,10 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd //--------------------------------------------------------------------+ #include "common/tusb_fifo.h" -typedef struct -{ - void (*interrupt_set)(bool); +typedef struct { + void (* interrupt_set)(bool); tu_fifo_t ff; -}osal_queue_def_t; +} osal_queue_def_t; typedef osal_queue_def_t* osal_queue_t; @@ -136,27 +127,23 @@ typedef osal_queue_def_t* osal_queue_t; } // lock queue by disable USB interrupt -TU_ATTR_ALWAYS_INLINE static inline void _osal_q_lock(osal_queue_t qhdl) -{ +TU_ATTR_ALWAYS_INLINE static inline void _osal_q_lock(osal_queue_t qhdl) { // disable dcd/hcd interrupt qhdl->interrupt_set(false); } // unlock queue -TU_ATTR_ALWAYS_INLINE static inline void _osal_q_unlock(osal_queue_t qhdl) -{ +TU_ATTR_ALWAYS_INLINE static inline void _osal_q_unlock(osal_queue_t qhdl) { // enable dcd/hcd interrupt qhdl->interrupt_set(true); } -TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) -{ +TU_ATTR_ALWAYS_INLINE static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef) { tu_fifo_clear(&qdef->ff); return (osal_queue_t) qdef; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, void* data, uint32_t msec) { (void) msec; // not used, always behave as msec = 0 _osal_q_lock(qhdl); @@ -166,8 +153,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, v return success; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void const* data, bool in_isr) { if (!in_isr) { _osal_q_lock(qhdl); } @@ -179,19 +165,17 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void } TU_ASSERT(success); - return success; } -TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) -{ +TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_empty(osal_queue_t qhdl) { // Skip queue lock/unlock since this function is primarily called // with interrupt disabled before going into low power mode return tu_fifo_empty(&qhdl->ff); } #ifdef __cplusplus - } +} #endif -#endif /* _TUSB_OSAL_NONE_H_ */ +#endif diff --git a/tools/cmake/toolchain/arm_gcc.cmake b/tools/cmake/toolchain/arm_gcc.cmake index cefa9d2ce..7680d75ab 100644 --- a/tools/cmake/toolchain/arm_gcc.cmake +++ b/tools/cmake/toolchain/arm_gcc.cmake @@ -29,7 +29,7 @@ list(APPEND TOOLCHAIN_COMMON_FLAGS -fno-strict-aliasing ) -set(TOOLCHAIN_EXE_LINKER_FLAGS +list(APPEND TOOLCHAIN_EXE_LINKER_FLAGS -Wl,--print-memory-usage -Wl,--gc-sections -Wl,--cref -- cgit v1.3.1